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Loads ID_AA64MMFR1_EL1 (#980)
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@ -5,6 +5,8 @@ use bitfield_struct::bitfield;
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pub struct CpuFeats {
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/// Raw value of `ID_AA64MMFR0_EL1`.
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pub mmfr0: Mmfr0,
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/// Raw value of `ID_AA64MMFR1_EL1`.
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pub mmfr1: Mmfr1,
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}
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/// Represents a value of `PSTATE`.
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@ -23,6 +25,8 @@ pub struct Pstate {
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}
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/// Represents a value of `ID_AA64MMFR0_EL1`.
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///
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/// All documentation copied from Arm Architecture Reference Manual for A-profile architecture.
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#[bitfield(u64)]
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pub struct Mmfr0 {
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/// Physical Address range supported.
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@ -188,3 +192,251 @@ pub struct Mmfr0 {
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#[bits(4)]
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pub ecv: u8,
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}
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/// Represents a value of `ID_AA64MMFR1_EL1`.
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///
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/// All documentation copied from Arm Architecture Reference Manual for A-profile architecture.
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#[bitfield(u64)]
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pub struct Mmfr1 {
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/// Hardware updates to Access flag and Dirty state in translation tables.
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///
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/// - `0b0000`: Hardware update of the Access flag and dirty state are not supported.
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/// - `0b0001`: Support for hardware update of the Access flag for Block and Page descriptors.
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/// - `0b0010`: As `0b0001`, and adds support for hardware update of the Access flag for Block
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/// and Page descriptors. Hardware update of dirty state is supported.
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/// - `0b0011`: As `0b0010`, and adds support for hardware update of the Access flag for Table
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/// descriptors.
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///
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/// All other values are reserved.
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///
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/// FEAT_HAFDBS implements the functionality identified by the values `0b0001` and `0b0010`.
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///
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/// FEAT_HAFT implements the functionality identified by the value `0b0011`.
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#[bits(4)]
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pub hafdbs: u8,
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/// Number of VMID bits.
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///
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/// - `0b0000`: 8 bits
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/// - `0b0010`: 16 bits
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///
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/// All other values are reserved.
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///
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/// FEAT_VMID16 implements the functionality identified by the value `0b0010`.
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///
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/// From Armv8.1, the permitted values are `0b0000` and `0b0010`.
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#[bits(4)]
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pub vmid_bits: u8,
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/// Virtualization Host Extensions.
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///
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/// - `0b0000`: Virtualization Host Extensions not supported.
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/// - `0b0001`: Virtualization Host Extensions supported.
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///
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/// All other values are reserved.
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///
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/// FEAT_VHE implements the functionality identified by the value `0b0001`.
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///
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/// From Armv8.1, the only permitted value is `0b0001`.
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#[bits(4)]
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pub vh: u8,
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/// Hierarchical Permission Disables. Indicates support for disabling hierarchical controls in
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/// translation tables.
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///
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/// - `0b0000`: Disabling of hierarchical controls not supported.
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/// - `0b0001`: Disabling of hierarchical controls supported with the TCR_EL1.{HPD1, HPD0},
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/// TCR_EL2.HPD or TCR_EL2.{HPD1, HPD0}, and TCR_EL3.HPD bits.
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/// - `0b0010`: As for value `0b0001`, and adds possible hardware allocation of bits[62:59] of
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/// the Translation table descriptors from the final lookup level for `IMPLEMENTATION DEFINED`
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/// use.
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///
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/// All other values are reserved.
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///
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/// FEAT_HPDS implements the functionality identified by the value `0b0001`.
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///
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/// FEAT_HPDS2 implements the functionality identified by the value `0b0010`.
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///
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/// From Armv8.1, the value `0b0000` is not permitted.
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#[bits(4)]
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pub hpds: u8,
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/// LORegions. Indicates support for LORegions.
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///
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/// - `0b0000`: LORegions not supported.
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/// - `0b0001`: LORegions supported.
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///
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/// All other values are reserved.
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///
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/// FEAT_LOR implements the functionality identified by the value `0b0001`.
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///
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/// From Armv8.1, the only permitted value is `0b0001`.
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#[bits(4)]
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pub lo: u8,
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/// Privileged Access Never. Indicates support for the PAN bit in PSTATE, SPSR_EL1, SPSR_EL2,
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/// SPSR_EL3, and DSPSR_EL0.
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///
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/// - `0b0000`: PAN not supported.
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/// - `0b0001`: PAN supported.
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/// - `0b0010`: PAN supported and AT S1E1RP and AT S1E1WP instructions supported.
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/// - `0b0011`: PAN supported, AT S1E1RP and AT S1E1WP instructions supported, and
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/// SCTLR_EL1.EPAN and SCTLR_EL2.EPAN bits supported.
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///
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/// All other values are reserved.
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///
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/// FEAT_PAN implements the functionality identified by the value `0b0001`.
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///
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/// FEAT_PAN2 implements the functionality added by the value `0b0010`.
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///
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/// FEAT_PAN3 implements the functionality added by the value `0b0011`.
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///
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/// In Armv8.1, the permitted values are `0b0001`, `0b0010`, and `0b0011`.
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///
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/// From Armv8.2, the permitted values are `0b0010` and `0b0011`.
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///
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/// From Armv8.7, the only permitted value is `0b0011`.
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#[bits(4)]
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pub pan: u8,
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/// ***When FEAT_RAS is implemented:***
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///
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/// Describes whether the PE can generate SError exceptions from speculative reads of memory,
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/// including speculative instruction fetches.
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///
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/// - `0b0000`: The PE never generates an SError exception due to an External abort on a
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/// speculative read.
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/// - `0b0001`: The PE might generate an SError exception due to an External abort on a
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/// speculative read.
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///
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/// All other values are reserved.
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///
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/// ***Otherwise:***
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///
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/// Reserved, `RES0`.
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#[bits(4)]
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pub spec_sei: u8,
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/// Indicates support for execute-never control distinction by Exception level at stage 2.
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///
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/// - `0b0000`: Distinction between EL0 and EL1 execute-never control at stage 2 not supported.
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/// - `0b0001`: Distinction between EL0 and EL1 execute-never control at stage 2 supported.
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///
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/// All other values are reserved.
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///
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/// FEAT_XNX implements the functionality identified by the value `0b0001`.
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///
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/// From Armv8.2, the only permitted value is `0b0001`.
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#[bits(4)]
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pub xnx: u8,
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/// Indicates support for the configurable delayed trapping of WFE.
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///
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/// - `0b0000`: Configurable delayed trapping of WFE is not supported.
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/// - `0b0001`: Configurable delayed trapping of WFE is supported.
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///
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/// All other values are reserved.
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///
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/// FEAT_TWED implements the functionality identified by the value `0b0001`.
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///
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/// From Armv8.6, the permitted values are `0b0000` and `0b0001`.
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#[bits(4)]
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pub twed: u8,
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/// Indicates support for Enhanced Translation Synchronization.
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///
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/// - `0b0000`: Enhanced Translation Synchronization is not supported.
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/// - `0b0001`: Enhanced Translation Synchronization is not supported.
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/// - `0b0010`: Enhanced Translation Synchronization is supported.
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///
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/// All other values are reserved.
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///
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/// FEAT_ETS2 implements the functionality identified by the value `0b0010`.
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///
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/// From Armv8.8, the values `0b0000` and `0b0001` are not permitted.
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#[bits(4)]
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pub ets: u8,
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/// Indicates support for HCRX_EL2 and its associated EL3 trap.
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///
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/// - `0b0000`: HCRX_EL2 and its associated EL3 trap are not supported.
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/// - `0b0001`: HCRX_EL2 and its associated EL3 trap are supported.
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///
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/// All other values are reserved.
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///
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/// FEAT_HCX implements the functionality identified by the value `0b0001`.
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///
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/// From Armv8.7, if EL2 is implemented, the only permitted value is `0b0001`.
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#[bits(4)]
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pub hcx: u8,
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/// Indicates support for FPCR.{AH, FIZ, NEP}.
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///
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/// - `0b0000`: The FPCR.{AH, FIZ, NEP} fields are not supported.
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/// - `0b0001`: The FPCR.{AH, FIZ, NEP} fields are supported.
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///
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/// All other values are reserved.
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///
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/// FEAT_AFP implements the functionality identified by the value `0b0001`.
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///
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/// From Armv8.7, if Advanced SIMD and floating-point is implemented, the only permitted value
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/// is `0b0001`.
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#[bits(4)]
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pub afp: u8,
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/// Indicates support for intermediate caching of translation table walks.
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///
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/// - `0b0000`: The intermediate caching of translation table walks might include non-coherent
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/// physical translation caches.
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/// - `0b0001`: The intermediate caching of translation table walks does not include
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/// non-coherent physical translation caches.
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///
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/// All other values are reserved.
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///
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/// Non-coherent physical translation caches are non-coherent caches of previous valid
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/// translation table entries since the last completed relevant TLBI applicable to the PE, where
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/// either:
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///
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/// - The caching is indexed by the physical address of the location holding the translation
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/// table entry.
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/// - The caching is used for stage 1 translations and is indexed by the intermediate physical
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/// address of the location holding the translation table entry.
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///
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/// FEAT_nTLBPA implements the functionality identified by the value `0b0001`.
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///
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/// From Armv8.0, the permitted values are `0b0000` and `0b0001`.
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#[bits(4)]
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pub n_tlbpa: u8,
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/// Indicates whether SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP are implemented in AArch64 state.
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///
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/// - `0b0000`: SCTLR_EL1.TIDCP and SCTLR_EL2.TIDCP bits are not implemented and are `RES0`.
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/// - `0b0001`: SCTLR_EL1.TIDCP bit is implemented. If EL2 is implemented, SCTLR_EL2.TIDCP bit
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/// is implemented.
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///
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/// All other values are reserved.
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///
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/// FEAT_TIDCP1 implements the functionality identified by the value `0b0001`.
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///
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/// From Armv8.8, the only permitted value is `0b0001`.
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#[bits(4)]
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pub tidcp1: u8,
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/// Indicates support for cache maintenance instruction permission.
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///
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/// - `0b0000`: SCTLR_EL1.CMOW, SCTLR_EL2.CMOW, and HCRX_EL2.CMOW bits are not implemented.
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/// - `0b0001`: SCTLR_EL1.CMOW is implemented. If EL2 is implemented, SCTLR_EL2.CMOW and
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/// HCRX_EL2.CMOW bits are implemented.
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///
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/// All other values are reserved.
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///
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/// FEAT_CMOW implements the functionality identified by the value `0b0001`.
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///
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/// From Armv8.8, the only permitted value is `0b0001`.
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#[bits(4)]
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pub cmow: u8,
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/// Indicates support for restrictions on branch history speculation around exceptions.
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///
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/// - `0b0000`: The implementation does not disclose whether the branch history information
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/// created in a context before an exception to a higher Exception level using AArch64 can be
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/// used by code before that exception to exploitatively control the execution of any indirect
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/// branches in code in a different context after the exception.
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/// - `0b0001`: The branch history information created in a context before an exception to a
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/// higher Exception level using AArch64 cannot be used by code before that exception to
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/// exploitatively control the execution of any indirect branches in code in a different
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/// context after the exception.
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///
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/// All other values are reserved.
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///
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/// FEAT_ECBHB implements the functionality identified by the value `0b0001`.
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///
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/// From Armv8.9, the value `0b0000` is not permitted.
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#[bits(4)]
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pub ecbhb: u8,
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}
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@ -90,14 +90,21 @@ impl Hypervisor for Hvf {
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#[cfg(target_arch = "aarch64")]
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fn cpu_features(&mut self) -> Result<CpuFeats, Self::CpuErr> {
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use hv_sys::hv_feature_reg_t_HV_FEATURE_REG_ID_AA64MMFR0_EL1 as HV_FEATURE_REG_ID_AA64MMFR0_EL1;
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use hv_sys::{
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hv_feature_reg_t_HV_FEATURE_REG_ID_AA64MMFR0_EL1 as HV_FEATURE_REG_ID_AA64MMFR0_EL1,
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hv_feature_reg_t_HV_FEATURE_REG_ID_AA64MMFR1_EL1 as HV_FEATURE_REG_ID_AA64MMFR1_EL1,
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};
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let mmfr0 = self
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.read_feature_reg(HV_FEATURE_REG_ID_AA64MMFR0_EL1)
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.map_err(HvfCpuError::ReadMmfr0Failed)?;
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let mmfr1 = self
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.read_feature_reg(HV_FEATURE_REG_ID_AA64MMFR1_EL1)
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.map_err(HvfCpuError::ReadMmfr1Failed)?;
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Ok(CpuFeats {
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mmfr0: mmfr0.into(),
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mmfr1: mmfr1.into(),
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})
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}
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@ -150,6 +157,10 @@ pub enum HvfCpuError {
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#[cfg(target_arch = "aarch64")]
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#[error("couldn't read ID_AA64MMFR0_EL1 ({0:#x})")]
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ReadMmfr0Failed(NonZero<hv_return_t>),
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#[cfg(target_arch = "aarch64")]
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#[error("couldn't read ID_AA64MMFR1_EL1 ({0:#x})")]
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ReadMmfr1Failed(NonZero<hv_return_t>),
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}
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#[cfg(target_arch = "aarch64")]
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