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fix some code check error

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Signed-off-by: zipper1956 <zipper1956@hotmail.com>
This commit is contained in:
peizhu
2022-04-24 10:31:01 +08:00
parent 24cbf0c98f
commit 7f68c3665c
46 changed files with 398 additions and 378 deletions
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asr582x/liteos_m/components/mbedtls/config/config_liteos_m.h
+4 -4
View File
@@ -517,9 +517,9 @@
* Any of these options become available by defining MBEDTLS_ECP_INTERNAL_ALT
* and implementing the following functions:
* unsigned char mbedtls_internal_ecp_grp_capable(
* const mbedtls_ecp_group *grp )
* int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp )
* void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp )
* const mbedtls_ecp_group *grp)
* int mbedtls_internal_ecp_init(const mbedtls_ecp_group *grp)
* void mbedtls_internal_ecp_free(const mbedtls_ecp_group *grp)
* The mbedtls_internal_ecp_grp_capable function should return 1 if the
* replacement functions implement arithmetic for the given group and 0
* otherwise.
@@ -3225,7 +3225,7 @@
*
* \param cond The expression that should evaluate to true, but doesn't.
*/
// #define MBEDTLS_PARAM_FAILED( cond ) assert( cond )
// #define MBEDTLS_PARAM_FAILED(cond) assert(cond)
/* SSL Cache options */
// #define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */
asr582x/liteos_m/components/mbedtls/library/entropy_hardware_alt.c
+3 -3
View File
@@ -20,8 +20,8 @@
#include "lega_rnd.h"
#include "lega_hw_common.h"
int mbedtls_hardware_poll( void *data,
unsigned char *output, size_t len, size_t *olen )
int mbedtls_hardware_poll(void *data,
unsigned char *output, size_t len, size_t *olen)
{
int ret = 0;
lega_rnd_init();
@@ -54,7 +54,7 @@ uint32_t mbedtls_hw_rand()
uint32_t ret = 0;
uint8_t buffer[RND_MAX_LEN] = {0};
uint32_t olen = 0;
mbedtls_hardware_poll( "0", &buffer[0], RND_TEST_LEN, &olen );
mbedtls_hardware_poll("0", &buffer[0], RND_TEST_LEN, &olen);
printf("data len = %d, data = \n", (int)olen);
for (ret = 0; ret < RND_TEST_LEN; ret++) {
printf("0x%x ", buffer[ret]);
asr582x/liteos_m/sdk/adapter/hals/iot_hardware/wifiiot_lite/hal_iot_gpio.c
+2 -2
View File
@@ -56,7 +56,7 @@ unsigned int IoTGpioGetDir(unsigned int id, IotGpioDir *dir)
duet_cfg = g_duet_gpio[id].config;
if ( duet_cfg >= DUET_OUTPUT_PUSH_PULL) {
if (duet_cfg >= DUET_OUTPUT_PUSH_PULL) {
return IOT_GPIO_DIR_OUT;
} else {
return IOT_GPIO_DIR_IN;
@@ -157,7 +157,7 @@ unsigned int IoTGpioSetIsrMode(unsigned int id, IotGpioIntType intType, IotGpioI
trigger = DUET_IRQ_TRIGGER_RISING_EDGE;
}
if (duet_gpio_disable_irq(&g_duet_gpio[id]) != 0 ) {
if (duet_gpio_disable_irq(&g_duet_gpio[id]) != 0) {
return IOT_FAILURE;
}
asr582x/liteos_m/sdk/drivers/at_cmd/atcmdplus_ble.c
+3 -3
View File
@@ -158,7 +158,7 @@ void apcmdplue_print_command(int argc, char **argv)
int atcmdplus_adv(int argc, char **argv)
{
apcmdplue_print_command(argc, argv);
if (strcmp(argv[PARA_ID_1], "1") == 0 ) {
if (strcmp(argv[PARA_ID_1], "1") == 0) {
app_ble_config_legacy_advertising();
} else if (strcmp(argv[PARA_ID_1], "0") == 0) {
app_ble_advertising_stop(0);
@@ -169,7 +169,7 @@ int atcmdplus_adv(int argc, char **argv)
int atcmdplus_scan(int argc, char **argv)
{
apcmdplue_print_command(argc, argv);
if (strcmp(argv[PARA_ID_1], "1") == 0 ) {
if (strcmp(argv[PARA_ID_1], "1") == 0) {
app_ble_config_scanning();
} else if (strcmp(argv[PARA_ID_1], "0") == 0) {
app_ble_stop_scanning();
@@ -242,7 +242,7 @@ int atcmdplus_ntf(int argc, char **argv)
}
uint8_t idValue = *argv[PARA_ID_1] - '0';
if (strcmp(argv[PARA_ID_2], "1") == 0 ) {
if (strcmp(argv[PARA_ID_2], "1") == 0) {
app_ble_master_turn_ntf(idValue, true);
} else if (strcmp(argv[PARA_ID_2], "0") == 0) {
app_ble_master_turn_ntf(idValue, false);
asr582x/liteos_m/sdk/drivers/at_cmd/lega_at_api.h
+2 -2
View File
@@ -158,8 +158,8 @@ extern int printf2(const char *format, ...);
#define printf2 printf
#endif
#define dbg_at(Fmt, ...) do{if(at_dbgflg) printf2(Fmt "\r\n", ## __VA_ARGS__);}while(0)
#define dbg_atnn(Fmt, ...) do{if(at_dbgflg) printf2(Fmt, ## __VA_ARGS__);}while(0)
#define dbg_at(Fmt, ...) do {if (at_dbgflg) printf2(Fmt "\r\n", ## __VA_ARGS__);} while (0)
#define dbg_atnn(Fmt, ...) do {if (at_dbgflg) printf2(Fmt, ## __VA_ARGS__);} while (0)
#define at_rspdata(Fmt, ...) printf2("+" Fmt "\r\n", ## __VA_ARGS__)
#define at_rspdatann(Fmt, ...) printf2("+" Fmt, ## __VA_ARGS__)
#define at_rspinfor(Fmt, ...) printf2(Fmt "\r\n", ## __VA_ARGS__)
asr582x/liteos_m/sdk/drivers/ble_inc/arch.h
+3 -3
View File
@@ -188,7 +188,7 @@ extern void (*pf_sonata_assert_warn)(uint16_t id, int param0, int param1);
pf_sonata_assert_err(id,1); \
} \
} \
} while(0)
} while (0)
// Assertions showing a critical error that could require a full system reset
#define ASSERT_INFO(id, cond, param0, param1) \
@@ -199,7 +199,7 @@ extern void (*pf_sonata_assert_warn)(uint16_t id, int param0, int param1);
pf_sonata_assert_param(id, (int)(param0), (int)(param1)); \
} \
} \
} while(0)
} while (0)
// Assertions showing a non-critical problem that has to be fixed by the SW
#define ASSERT_WARN(id, cond, param0, param1) \
@@ -210,7 +210,7 @@ extern void (*pf_sonata_assert_warn)(uint16_t id, int param0, int param1);
pf_sonata_assert_warn(id, (int)(param0), (int)(param1)); \
} \
} \
} while(0)
} while (0)
// modified for rom code 20200224
asr582x/liteos_m/sdk/drivers/ble_inc/at_api.h
+3 -3
View File
@@ -76,7 +76,7 @@ void at_command_process_ble(void);
* @param cmd_entry : user at cmd array pointer
* @param cmd_num : user at cmd number
*/
void at_cmd_register( const cmd_entry *cmd);
void at_cmd_register(const cmd_entry *cmd);
/** @brief at init functin, user should call it before use at cmd
* @return 0 : on success.
@@ -117,8 +117,8 @@ extern char at_dbgflg;
#define at_printf printf
#define dbg_at(Fmt, ...) do{if(at_dbgflg) at_printf(Fmt "\r\n", ## __VA_ARGS__);}while(0)
#define dbg_atnn(Fmt, ...) do{if(at_dbgflg) at_printf(Fmt, ## __VA_ARGS__);}while(0)
#define dbg_at(Fmt, ...) do {if (at_dbgflg) at_printf(Fmt "\r\n", ## __VA_ARGS__);} while (0)
#define dbg_atnn(Fmt, ...) do {if (at_dbgflg) at_printf(Fmt, ## __VA_ARGS__);} while (0)
#define at_rspdata(Fmt, ...) at_printf("+" Fmt "\r\n", ## __VA_ARGS__)
#define at_rspdatann(Fmt, ...) at_printf("+" Fmt, ## __VA_ARGS__)
asr582x/liteos_m/sdk/drivers/ble_inc/msm_ble_api.h
+1 -1
View File
@@ -31,7 +31,7 @@
#define PRD_AU (SONATA_PERM(RD, ENABLE) | SONATA_PERM(RP, AUTH))
/// GATT write perm auth (0x0808)
#define PWR_AU (SONATA_PERM(WRITE_REQ, ENABLE) | SONATA_PERM(WP, AUTH))
/// GATT ind perm auth( 0X2020)
/// GATT ind perm auth (0X2020)
#define PIND_AU (SONATA_PERM(IND, ENABLE) | SONATA_PERM(IP, AUTH))
/// GATT notify perm auth (0x1080)
#define PNTF_AU (SONATA_PERM(NTF, ENABLE) | SONATA_PERM(NP, AUTH))
asr582x/liteos_m/sdk/drivers/ble_inc/ohos_bt_gatt_client.h
+1 -1
View File
@@ -107,7 +107,7 @@ typedef struct {
* @param[in] <appUuid> specified by upper layer
* @return 0-success, other-fail
*/
int BleGattcRegister( BtUuid appUuid);
int BleGattcRegister( BtUuid appUuid);
/*
* @brief gatt client deregister
asr582x/liteos_m/sdk/drivers/ble_inc/sonata_att.h
+2 -2
View File
@@ -940,11 +940,11 @@ struct sonata_att_incl128_desc {
// --------------------------- Database permissions -----------------------------
/// Macro used to retrieve access permission rights
#define SONATA_PERM_GET(perm, access)\
#define SONATA_PERM_GET(perm, access) \
(((perm) & (SONATA_PERM_MASK_ ## access)) >> (SONATA_PERM_POS_ ## access))
/// Macro used to set a permission value
#define SONATA_PERM_SET(perm, access, value)\
#define SONATA_PERM_SET(perm, access, value) \
perm = (((perm) & ~(SONATA_PERM_MASK_ ## access)) | (((value) << (SONATA_PERM_POS_ ## access)) & (SONATA_PERM_MASK_ ## access)))
/// Macro used to retrieve permission value from access and rights on attribute.
asr582x/liteos_m/sdk/drivers/ble_inc/sonata_gap.h
+1 -1
View File
@@ -594,7 +594,7 @@ struct sonata_gap_iq_sample {
int8_t q;
};
typedef uint16_t (*sonata_gap_check_pkt_type_t )(uint8_t pkt_type);
typedef uint16_t (*sonata_gap_check_pkt_type_t)(uint8_t pkt_type);
// @} GAP
#endif // SONATA_SONATA_GAP_H_
asr582x/liteos_m/sdk/drivers/ble_inc/sonata_gap_api.h
+2 -2
View File
@@ -1767,10 +1767,10 @@ typedef struct {
uint16_t (*gap_scan_result)(sonata_gap_ext_adv_report_ind_t *result);
/// Callback for get peer name
uint16_t (*gap_get_peer_name)( uint8_t addr_type, uint8_t *peer_addr, uint8_t name_len, uint8_t *name);
uint16_t (*gap_get_peer_name)(uint8_t addr_type, uint8_t *peer_addr, uint8_t name_len, uint8_t *name);
/// Callback for random address has been solved
uint16_t (*gap_addr_solved)( uint8_t *addr, uint8_t *key);
uint16_t (*gap_addr_solved)(uint8_t *addr, uint8_t *key);
/// Callback for AES-128 block result indication
uint16_t (*gap_use_enc_block)(uint8_t *result);
asr582x/liteos_m/sdk/drivers/ble_inc/sonata_gatt_api.h
+1 -1
View File
@@ -52,7 +52,7 @@
#define PRD_AU (SONATA_PERM(RD, ENABLE) | SONATA_PERM(RP, AUTH))
/// GATT write perm auth (0x0808)
#define PWR_AU (SONATA_PERM(WRITE_REQ, ENABLE) | SONATA_PERM(WP, AUTH))
/// GATT ind perm auth( 0X2020)
/// GATT ind perm auth (0X2020)
#define PIND_AU (SONATA_PERM(IND, ENABLE) | SONATA_PERM(IP, AUTH))
/// GATT notify perm auth (0x1080)
#define PNTF_AU (SONATA_PERM(NTF, ENABLE) | SONATA_PERM(NP, AUTH))
asr582x/liteos_m/sdk/drivers/ble_inc/sonata_log.h
+58 -38
View File
@@ -65,63 +65,83 @@ typedef int (*vprintf_like_t)(const char *, va_list);
#ifdef CFG_SONATA_LOG
#define SONATA_LOGT_FORMAT_SIMPLE(format) "%s: " format "\r\n"
#define SONATA_LOGT_LEVEL_SIMPLE(level, tag, format, ...) do { \
if (level==SONATA_LOG_ERROR ) { sonata_logt_write(SONATA_LOG_ERROR, tag, SONATA_LOGT_FORMAT_SIMPLE(format), tag, ##__VA_ARGS__); } \
else if (level==SONATA_LOG_WARN ) { sonata_logt_write(SONATA_LOG_WARN, tag, SONATA_LOGT_FORMAT_SIMPLE(format), tag, ##__VA_ARGS__); } \
else if (level==SONATA_LOG_DEBUG ) { sonata_logt_write(SONATA_LOG_DEBUG, tag, SONATA_LOGT_FORMAT_SIMPLE(format), tag, ##__VA_ARGS__); } \
else if (level==SONATA_LOG_VERBOSE ) { sonata_logt_write(SONATA_LOG_VERBOSE, tag, SONATA_LOGT_FORMAT_SIMPLE(format), tag, ##__VA_ARGS__); } \
else { sonata_logt_write(SONATA_LOG_INFO, tag, SONATA_LOGT_FORMAT_SIMPLE(format), tag, ##__VA_ARGS__); } \
} while(0)
if (level==SONATA_LOG_ERROR) { sonata_logt_write(SONATA_LOG_ERROR, tag, \
SONATA_LOGT_FORMAT_SIMPLE(format), \
tag, ##__VA_ARGS__); } \
else if (level == SONATA_LOG_WARN) { sonata_logt_write(SONATA_LOG_WARN, tag, \
SONATA_LOGT_FORMAT_SIMPLE(format), tag, \
##__VA_ARGS__); } \
else if (level == SONATA_LOG_DEBUG) { sonata_logt_write(SONATA_LOG_DEBUG, tag, \
SONATA_LOGT_FORMAT_SIMPLE(format), tag, \
##__VA_ARGS__); } \
else if (level == SONATA_LOG_VERBOSE) { sonata_logt_write(SONATA_LOG_VERBOSE, tag, \
SONATA_LOGT_FORMAT_SIMPLE(format), tag, \
##__VA_ARGS__); } \
else { sonata_logt_write(SONATA_LOG_INFO, tag, \
SONATA_LOGT_FORMAT_SIMPLE(format), tag, \
##__VA_ARGS__); } \
} while (0)
#define SONATA_LOGT_LEVEL_LOCAL_SIMPLE(level, tag, format, ...) do { \
if ( LOG_LOCAL_LEVEL >= level ) SONATA_LOGT_LEVEL_SIMPLE(level, tag, format, ##__VA_ARGS__); \
} while(0)
if (LOG_LOCAL_LEVEL >= level) SONATA_LOGT_LEVEL_SIMPLE(level, tag, format, ##__VA_ARGS__); \
} while (0)
/*!
* @brief Log function With TAG
* @example LOGTE("TagE","A Simple logE: %02X, %s", 0,__FUNCTION__ );
* @example LOGTE("TagE","A Simple logE: %02X, %s", 0,__FUNCTION__);
* @note LOGTX function will auto add linefeed for every log string.
*/
#define LOGTE( tag, format, ... ) SONATA_LOGT_LEVEL_LOCAL_SIMPLE(SONATA_LOG_ERROR, tag, format, ##__VA_ARGS__)
#define LOGTW( tag, format, ... ) SONATA_LOGT_LEVEL_LOCAL_SIMPLE(SONATA_LOG_WARN, tag, format, ##__VA_ARGS__)
#define LOGTI( tag, format, ... ) SONATA_LOGT_LEVEL_LOCAL_SIMPLE(SONATA_LOG_INFO, tag, format, ##__VA_ARGS__)
#define LOGTD( tag, format, ... ) SONATA_LOGT_LEVEL_LOCAL_SIMPLE(SONATA_LOG_DEBUG, tag, format, ##__VA_ARGS__)
#define LOGTV( tag, format, ... ) SONATA_LOGT_LEVEL_LOCAL_SIMPLE(SONATA_LOG_VERBOSE, tag, format, ##__VA_ARGS__)
#define LOGTE(tag, format, ...) SONATA_LOGT_LEVEL_LOCAL_SIMPLE(SONATA_LOG_ERROR, tag, format, ##__VA_ARGS__)
#define LOGTW(tag, format, ...) SONATA_LOGT_LEVEL_LOCAL_SIMPLE(SONATA_LOG_WARN, tag, format, ##__VA_ARGS__)
#define LOGTI(tag, format, ...) SONATA_LOGT_LEVEL_LOCAL_SIMPLE(SONATA_LOG_INFO, tag, format, ##__VA_ARGS__)
#define LOGTD(tag, format, ...) SONATA_LOGT_LEVEL_LOCAL_SIMPLE(SONATA_LOG_DEBUG, tag, format, ##__VA_ARGS__)
#define LOGTV(tag, format, ...) SONATA_LOGT_LEVEL_LOCAL_SIMPLE(SONATA_LOG_VERBOSE, tag, format, ##__VA_ARGS__)
/********************************************* Log function for no TAG ***********************************************************/
#define SONATA_LOG_FORMAT_SIMPLE(format) "" format ""
#define SONATA_LOG_LEVEL_SIMPLE(level, format, ...) do { \
if (level==SONATA_LOG_ERROR ) { sonata_logt_write(SONATA_LOG_ERROR, NULL, SONATA_LOG_FORMAT_SIMPLE(format), ##__VA_ARGS__); } \
else if (level==SONATA_LOG_WARN ) { sonata_logt_write(SONATA_LOG_WARN, NULL, SONATA_LOG_FORMAT_SIMPLE(format), ##__VA_ARGS__); } \
else if (level==SONATA_LOG_DEBUG ) { sonata_logt_write(SONATA_LOG_DEBUG, NULL, SONATA_LOG_FORMAT_SIMPLE(format), ##__VA_ARGS__); } \
else if (level==SONATA_LOG_VERBOSE ) { sonata_logt_write(SONATA_LOG_VERBOSE, NULL, SONATA_LOG_FORMAT_SIMPLE(format), ##__VA_ARGS__); } \
else { sonata_logt_write(SONATA_LOG_INFO, NULL, SONATA_LOG_FORMAT_SIMPLE(format), ##__VA_ARGS__); } \
} while(0)
if (level==SONATA_LOG_ERROR) { sonata_logt_write(SONATA_LOG_ERROR, NULL, \
SONATA_LOG_FORMAT_SIMPLE(format), \
##__VA_ARGS__); } \
else if (level==SONATA_LOG_WARN) { sonata_logt_write(SONATA_LOG_WARN, NULL, \
SONATA_LOG_FORMAT_SIMPLE(format), \
##__VA_ARGS__); } \
else if (level==SONATA_LOG_DEBUG) { sonata_logt_write(SONATA_LOG_DEBUG, NULL, \
SONATA_LOG_FORMAT_SIMPLE(format), \
##__VA_ARGS__); } \
else if (level==SONATA_LOG_VERBOSE) { sonata_logt_write(SONATA_LOG_VERBOSE, NULL, \
SONATA_LOG_FORMAT_SIMPLE(format), \
##__VA_ARGS__); } \
else { sonata_logt_write(SONATA_LOG_INFO, NULL, \
SONATA_LOG_FORMAT_SIMPLE(format), \
##__VA_ARGS__); } \
} while (0)
#define SONATA_LOG_LEVEL_LOCAL_SIMPLE(level, format, ...) do { \
if ( LOG_LOCAL_LEVEL >= level ) SONATA_LOG_LEVEL_SIMPLE(level, format, ##__VA_ARGS__); \
} while(0)
if (LOG_LOCAL_LEVEL >= level) SONATA_LOG_LEVEL_SIMPLE(level, format, ##__VA_ARGS__); \
} while (0)
/*!
* @brief Log function without TAG
* @example "LOGE("A Simple logE: %02X, %s r n", 0,__FUNCTION__ );"
* @example "LOGE("A Simple logE: %02X, %s r n", 0,__FUNCTION__);"
* @note user should add linefeed for every log string if necessary
*/
#define LOGE( format, ... ) SONATA_LOG_LEVEL_LOCAL_SIMPLE(SONATA_LOG_ERROR, format, ##__VA_ARGS__)
#define LOGW( format, ... ) SONATA_LOG_LEVEL_LOCAL_SIMPLE(SONATA_LOG_WARN, format, ##__VA_ARGS__)
#define LOGI( format, ... ) SONATA_LOG_LEVEL_LOCAL_SIMPLE(SONATA_LOG_INFO, format, ##__VA_ARGS__)
#define LOGD( format, ... ) SONATA_LOG_LEVEL_LOCAL_SIMPLE(SONATA_LOG_DEBUG, format, ##__VA_ARGS__)
#define LOGV( format, ... ) SONATA_LOG_LEVEL_LOCAL_SIMPLE(SONATA_LOG_VERBOSE, format, ##__VA_ARGS__)
#define LOGE(format, ...) SONATA_LOG_LEVEL_LOCAL_SIMPLE(SONATA_LOG_ERROR, format, ##__VA_ARGS__)
#define LOGW(format, ...) SONATA_LOG_LEVEL_LOCAL_SIMPLE(SONATA_LOG_WARN, format, ##__VA_ARGS__)
#define LOGI(format, ...) SONATA_LOG_LEVEL_LOCAL_SIMPLE(SONATA_LOG_INFO, format, ##__VA_ARGS__)
#define LOGD(format, ...) SONATA_LOG_LEVEL_LOCAL_SIMPLE(SONATA_LOG_DEBUG, format, ##__VA_ARGS__)
#define LOGV(format, ...) SONATA_LOG_LEVEL_LOCAL_SIMPLE(SONATA_LOG_VERBOSE, format, ##__VA_ARGS__)
#else // CFG_SONATA_LOG
#define LOGTE( tag, format, ... )
#define LOGTW( tag, format, ... )
#define LOGTI( tag, format, ... )
#define LOGTD( tag, format, ... )
#define LOGTV( tag, format, ... )
#define LOGE( format, ... )
#define LOGW( format, ... )
#define LOGI( format, ... )
#define LOGD( format, ... )
#define LOGV( format, ... )
#define LOGTE(tag, format, ...)
#define LOGTW(tag, format, ...)
#define LOGTI(tag, format, ...)
#define LOGTD(tag, format, ...)
#define LOGTV(tag, format, ...)
#define LOGE(format, ...)
#define LOGW(format, ...)
#define LOGI(format, ...)
#define LOGD(format, ...)
#define LOGV(format, ...)
#endif // CFG_SONATA_LOG
asr582x/liteos_m/sdk/drivers/ble_inc/sonata_mesh_api.h
+14 -14
View File
@@ -1234,15 +1234,15 @@ typedef struct {
/// Publish Friendship CredentialFlag
uint16_t credentialFlag : 1;
/// Reserved for Future Use
uint16_t rfu: 3;
uint16_t rfu : 3;
/// Default TTL value for the outgoing messages
uint8_t ttl;
/// Period for periodic status publishing
uint8_t period;
/// Number of retransmissions for each published message
uint8_t retransmitCount: 3;
uint8_t retransmitCount : 3;
/// Number of 50-millisecond steps between retransmissions
uint8_t retransmitIntervalSteps: 5;
uint8_t retransmitIntervalSteps : 5;
/// Model Identifier
uint32_t model_id;
} provisioner_pub_set_status_t;
@@ -1252,9 +1252,9 @@ typedef struct {
/// Source Address
uint16_t src_addr;
/// Network Transmit Count
uint8_t retransmitCount: 3;
uint8_t retransmitCount : 3;
/// Network Transmit Interval Steps
uint8_t retransmitIntervalSteps: 5;
uint8_t retransmitIntervalSteps : 5;
} provisioner_nettransmit_status_t;
// Mesh Core Provision Event Indicate Parameter union
@@ -1332,15 +1332,15 @@ typedef struct mesh_local_pub_set {
/// Publish Friendship CredentialFlag
uint16_t credentialFlag : 1;
/// Reserved for Future Use
uint16_t rfu: 3;
uint16_t rfu : 3;
/// Default TTL value for the outgoing messages
uint8_t ttl;
/// Period for periodic status publishing
uint8_t period;
/// Number of retransmissions for each published message
uint8_t retransmitCount: 3;
uint8_t retransmitCount : 3;
/// Number of 50-millisecond steps between retransmissions
uint8_t retransmitIntervalSteps: 5;
uint8_t retransmitIntervalSteps : 5;
/// Model Identifier
uint32_t model_id;
} mesh_local_pub_set_t;
@@ -1645,15 +1645,15 @@ typedef struct mesh_provisioner_set_pub_param {
/// Value of the Friendship Credential Flag
uint16_t credentialFlag : 1;
/// Reserved for Future Use
uint16_t rfu: 3;
uint16_t rfu : 3;
/// Default TTL value for the outgoing messages
uint8_t ttl;
/// Period for periodic status publishing
uint8_t period;
/// Number of retransmissions for each published message
uint8_t retransmitCount: 3;
uint8_t retransmitCount : 3;
/// Number of 50-millisecond steps between retransmissions
uint8_t retransmitIntervalSteps: 5;
uint8_t retransmitIntervalSteps : 5;
/// Model Identifier
uint32_t model_id;
/// Index of the Network key
@@ -1667,9 +1667,9 @@ typedef struct mesh_provisioner_set_nettransmit_param {
/// Index of Netkey
uint16_t netkey_index;
/// Number of transmissions for each Network PDU originating from the node
uint8_t retransmitCount: 3;
uint8_t retransmitCount : 3;
/// Number of 10-millisecond steps between transmissions
uint8_t retransmitIntervalSteps: 5;
uint8_t retransmitIntervalSteps : 5;
} mesh_provisioner_set_nettransmit_param_t;
// Mesh Core Provisioner Event Callback Parameter Union
@@ -1764,7 +1764,7 @@ typedef struct mesh_model_publish_param {
typedef STATUS (* msg_published_cb)(mesh_model_publish_param_t *p_param, STATUS status) ;
// Sig Nodel State callback
typedef void (* sig_model_state_cb)(mesh_state_ind_t *p_state ) ;
typedef void (* sig_model_state_cb)(mesh_state_ind_t *p_state) ;
/**@}*/
/**
asr582x/liteos_m/sdk/drivers/ble_inc/sonata_prf_hogpd_api.h
+1 -1
View File
@@ -118,7 +118,7 @@
#define HID_BUTTON_7 0x24 // Keyboard 7 and &
#define HID_BUTTON_8 0x25 // Keyboard 8 and *
#define HID_BUTTON_9 0x26 // Keyboard 9 and (
#define HID_BUTTON_0 0x27 // Keyboard 0 and )
#define HID_BUTTON_0 0x27 // Keyboard 0 and)
#define HID_BUTTON_ENTER 0x28 // Keyboard Return and Enter
#define HID_BUTTON_ESC 0x29 // Keyboard ESPACE
#define HID_BUTTON_BACKSPACE 0x2A // Keyboard DELET (Backspace)
asr582x/liteos_m/sdk/drivers/ble_inc/sonata_prf_hogprh_api.h
+1 -1
View File
@@ -222,7 +222,7 @@ typedef struct sonata_hogprh_write_req {
/// - info = HOGPRH_REPORT
/// - info = HOGPRH_REPORT_NTF_CFG
uint8_t report_idx;
/// Write type ( Write without Response True or Write Request)
/// Write type (Write without Response True or Write Request)
/// - only valid for HOGPRH_REPORT
bool wr_cmd;
/// Information data
asr582x/liteos_m/sdk/drivers/ble_inc/sonata_stack_config.h
+2 -2
View File
@@ -82,9 +82,9 @@
#define CFG_BLE_ADV_TEST_MODE
#if ( (defined SONATA_CFG_MESH_DBG) && (defined SONATA_CFG_DBG) )
#if ((defined SONATA_CFG_MESH_DBG) && (defined SONATA_CFG_DBG))
#define CFG_BLE_MESH_DBG
#endif // ( (defined SONATA_CFG_MESH_DBG) && (defined SONATA_CFG_DBG) )
#endif // ((defined SONATA_CFG_MESH_DBG) && (defined SONATA_CFG_DBG))
#define CFG_BLE_MESH_RELAY
asr582x/liteos_m/sdk/drivers/ble_src/app.c
+9 -9
View File
@@ -251,7 +251,7 @@ static sonata_app_timer_callback_t app_timer_callbacks = {
.timeout = app_timer_handler,
};
static void app_print_hex(uint8_t *hex, uint8_t len )
static void app_print_hex(uint8_t *hex, uint8_t len)
{
for (int i = 0; i < len; i++) {
APP_TRC("%x%x", hex[i] >> 4, hex[i] & 0xf);
@@ -302,7 +302,7 @@ static uint8_t app_get_conidx_by_addr(uint8_t *addr)
static uint8_t *app_get_addr_by_conidx(uint8_t conidx)
{
for (int idx = 0; idx < APP_BLE_CONNECT_MAX; idx++) {
if (connect_req_list[idx].conidx == conidx ) {
if (connect_req_list[idx].conidx == conidx) {
return connect_req_list[idx].bd_addr;
}
}
@@ -1272,7 +1272,7 @@ static uint16_t app_gap_scan_result_callback(sonata_gap_ext_adv_report_ind_t *re
void app_active_delete(uint8_t conIdx)
{
if (conIdx > APP_ACTIVE_MAX) {
APP_TRC("APP: %s,ERROR:ACTIVE overflow\r\n", __FUNCTION__ );
APP_TRC("APP: %s,ERROR:ACTIVE overflow\r\n", __FUNCTION__);
return;
}
gAppEnv.act[conIdx].runing = false;
@@ -1600,10 +1600,10 @@ int app_ble_gatt_add_svc_helper(uint16_t *start_hdl, uint8_t nb_att, ble_gatt_at
}
}
APP_TRC("struc %d %d\r\n", sizeof(ble_gatt_att_reg_list_t), sizeof(ble_gatt_att_manager_t));
ble_gatt_att_reg_list_t *p_list = ( ble_gatt_att_reg_list_t * ) sonata_api_malloc(sizeof(ble_gatt_att_opr_t) *
ble_gatt_att_reg_list_t *p_list = (ble_gatt_att_reg_list_t *) sonata_api_malloc(sizeof(ble_gatt_att_opr_t) *
(nb_att - 1) + sizeof(ble_gatt_att_reg_list_t));
memset(p_list, 0, sizeof(ble_gatt_att_opr_t) * (nb_att - 1) + sizeof(ble_gatt_att_reg_list_t));
p_list->att_opr_list = (ble_gatt_att_opr_t *)( (uint8_t *)p_list + sizeof(ble_gatt_att_reg_list_t));
p_list->att_opr_list = (ble_gatt_att_opr_t *)((uint8_t *)p_list + sizeof(ble_gatt_att_reg_list_t));
p_list->nb_att = nb_att - 1;
APP_TRC("nb_att %d\r\n", p_list->nb_att);
@@ -1678,7 +1678,7 @@ static void print_peer_bond_request(struct sonata_gap_bond_req_ind *request)
switch (request->request) {
case SONATA_GAP_PAIRING_REQ:
APP_TRC("PEER_PAIR: SONATA_GAP_PAIRING_REQ,auth_req=%02X(X)", request->data.auth_req);
switch (request->data.auth_req ) {
switch (request->data.auth_req) {
case SONATA_GAP_AUTH_REQ_NO_MITM_NO_BOND:
APP_TRC(" (GAP_AUTH_REQ_NO_MITM_NO_BOND)\r\n");
break;
@@ -1705,7 +1705,7 @@ static void print_peer_bond_request(struct sonata_gap_bond_req_ind *request)
break;
case SONATA_GAP_TK_EXCH:
APP_TRC("PEER_PAIR: SONATA_GAP_TK_EXCH,tk_type=%02X(X)\r\n", request->data.tk_type);
switch (request->data.auth_req ) {
switch (request->data.auth_req) {
case SONATA_GAP_TK_OOB:
APP_TRC(" (GAP_TK_OOB)\r\n");
break;
@@ -2293,11 +2293,11 @@ void app_gap_connect_confirm(uint8_t *addr, uint8_t auth)
void app_active_update(uint8_t conIdx, uint8_t *mac)
{
if (conIdx > APP_ACTIVE_MAX) {
APP_TRC("APP: %s,ERROR:ACTIVE overflow\r\n", __FUNCTION__ );
APP_TRC("APP: %s,ERROR:ACTIVE overflow\r\n", __FUNCTION__);
return;
}
if (gAppEnv.act[conIdx].runing == true) {
APP_TRC("APP: %s,ERROR:ACTIVE id error\r\n", __FUNCTION__ );
APP_TRC("APP: %s,ERROR:ACTIVE id error\r\n", __FUNCTION__);
return;
}
gAppEnv.act[conIdx].runing = true;
asr582x/liteos_m/sdk/drivers/ble_src/at_ble.c
+1 -1
View File
@@ -198,7 +198,7 @@ static struct cli_command write_cmd = {
void lega_ble_disconnect_test(char *pwbuf, int blen, int argc, char **argv)
{
int c = 1;
if (argc == 2 ) {
if (argc == 2) {
app_ble_disconnect(0);
}
}
asr582x/liteos_m/sdk/drivers/ble_src/harmony_ble_adpter.c
+6 -6
View File
@@ -307,9 +307,9 @@ ble_gatt_att_reg_t *ble_ohos_add_char(ble_gatt_att_reg_t *dst_attr, BleGattAttr
dst_attr->att_desc.ext_perm |= PRI;
dst_attr->att_desc.max_len = 512;
if (((char_attr->properties & OHOS_GATT_CHARACTER_PROPERTY_BIT_INDICATE) == OHOS_GATT_CHARACTER_PROPERTY_BIT_INDICATE
|| (char_attr->properties & OHOS_GATT_CHARACTER_PROPERTY_BIT_NOTIFY) == OHOS_GATT_CHARACTER_PROPERTY_BIT_NOTIFY )
&& isLast) {
if (((char_attr->properties & OHOS_GATT_CHARACTER_PROPERTY_BIT_INDICATE) == OHOS_GATT_CHARACTER_PROPERTY_BIT_INDICATE
|| (char_attr->properties & OHOS_GATT_CHARACTER_PROPERTY_BIT_NOTIFY) == OHOS_GATT_CHARACTER_PROPERTY_BIT_NOTIFY)
&& isLast) {
dst_attr++;
uint8_t char_uuid2[ATT_SIG_UUID_128_LEN] = {0x02, 0x29, 0x0};
@@ -477,11 +477,11 @@ int BleGattsStartServiceEx(int *srvcHandle, BleGattService *srvcInfo)
if ((srvcInfo->attrList[att_nb - 1].properties & OHOS_GATT_CHARACTER_PROPERTY_BIT_INDICATE) ==
OHOS_GATT_CHARACTER_PROPERTY_BIT_INDICATE
|| (srvcInfo->attrList[att_nb - 1].properties & OHOS_GATT_CHARACTER_PROPERTY_BIT_NOTIFY) ==
OHOS_GATT_CHARACTER_PROPERTY_BIT_NOTIFY ) {
OHOS_GATT_CHARACTER_PROPERTY_BIT_NOTIFY) {
indicate_is_exit = 1;
}
att_nb = get_service_num(srvcInfo->attrNum, indicate_is_exit);
uint32_t len = (att_nb ) * sizeof(ble_gatt_att_reg_t) ;
uint32_t len = (att_nb) * sizeof(ble_gatt_att_reg_t) ;
ble_gatt_att_reg_t *att_list;
ble_gatt_att_reg_t *att_temp;
att_list = (ble_gatt_att_reg_t *)malloc(len);
@@ -537,7 +537,7 @@ int BleGattRegisterCallbacks(BtGattCallbacks *func)
{
print_log("harmony : %s \r\n", __FUNCTION__);
memmove(&bt_gattcallback, func, sizeof(BtGattCallbacks));
app_register_sec_cb((app_sec_req_cb )bt_gattcallback.securityRespondCb);
app_register_sec_cb((app_sec_req_cb)bt_gattcallback.securityRespondCb);
return BT_STATUS_SUCCESS;
}
asr582x/liteos_m/sdk/drivers/common/lega_dbg.h
+2 -2
View File
@@ -57,12 +57,12 @@ extern char *component_info(uint32_t module_t);
#define component_t(module_t) component_info(module_t)
#define dbg(Level, Comp, Fmt, ...)\
#define dbg(Level, Comp, Fmt, ...) \
do {\
if(GlobalDebugEn && (Comp & GlobalDebugComponents) && (Level <= GlobalDebugLevel)) {\
printf("[%u] ",(unsigned int)lega_rtos_get_time());\
printf(Fmt "\r\n", ## __VA_ARGS__);\
}\
}while(0)
} while (0)
#endif // _LEGA_DBG_H_
asr582x/liteos_m/sdk/drivers/driver/inc/duet.h
+11 -11
View File
@@ -77,7 +77,7 @@ typedef struct Sys_Con_Block {
__IO uint32_t timer2_sclk_sel : 1;
__IO uint32_t timer3_sclk_sel : 1;
__IO uint32_t timer4_sclk_sel : 1;
__IO uint32_t rw_mst_clk_freq_sel: 6;
__IO uint32_t rw_mst_clk_freq_sel : 6;
__I uint32_t rsv0 : 1;
__IO uint32_t pwm_pclk_sel : 1;
__I uint32_t rsv1 : 14;
@@ -200,8 +200,8 @@ typedef struct Sys_Con_Block {
#define PERI_CG_REG_BASE (SYS_CON_REG_BASE + 0x14)
#define PERI_SOFT_RESET_REG_BASE (SYS_CON_REG_BASE + 0x18)
#define REG_PERI_CG_EN (*( (volatile uint32_t *)(PERI_CG_REG_BASE) ))
#define REG_PERI_SOFT_RESET_REG (*( (volatile uint32_t *)(PERI_SOFT_RESET_REG_BASE) ))
#define REG_PERI_CG_EN (*((volatile uint32_t *)(PERI_CG_REG_BASE)))
#define REG_PERI_SOFT_RESET_REG (*((volatile uint32_t *)(PERI_SOFT_RESET_REG_BASE)))
#define SYSCTRL_BASE SYS_CON_REG_BASE
#define SYS_CON_00 *(volatile int unsigned *)(SYSCTRL_BASE + (0x000*4))
@@ -317,9 +317,9 @@ typedef struct __I2S {
__I uint32_t I2S_COMP_TYPE;
} I2S_TypeDef;
#define REG_I2S_HW_SHFIT_SET ( *(volatile uint32_t *)(SYS_CON_REG_BASE + 0xC0) )
#define REG_I2S_HW_SHIFT_DATAIN ( *(volatile uint32_t *)(SYS_CON_REG_BASE + 0xC4) )
#define REG_I2S_HW_SHIFT_DATAOUT ( *(volatile uint32_t *)(SYS_CON_REG_BASE + 0xC8) )
#define REG_I2S_HW_SHFIT_SET (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0xC0))
#define REG_I2S_HW_SHIFT_DATAIN (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0xC4))
#define REG_I2S_HW_SHIFT_DATAOUT (*(volatile uint32_t *)(SYS_CON_REG_BASE + 0xC8))
#define I2S_BASE (0x4008D000)
#define I2S ((I2S_TypeDef *)I2S_BASE)
@@ -334,7 +334,7 @@ typedef struct {
__IO uint32_t reserved : 1;
} I2S_CLK_DIV_TypeDef;
#define I2S_CLK_DIV ((I2S_CLK_DIV_TypeDef *)0x40000810 )
#define I2S_CLK_DIV ((I2S_CLK_DIV_TypeDef *)0x40000810)
/*
DUET SPI definitions
@@ -359,9 +359,9 @@ typedef struct __SPI {
#define SPI1_BASE (0x40080000+0x5000)
#define SPI2_BASE (0x40080000+0x6000)
#define SPI0 ( (SPI_TypeDef *)SPI0_BASE )
#define SPI1 ( (SPI_TypeDef *)SPI1_BASE )
#define SPI2 ( (SPI_TypeDef *)SPI2_BASE )
#define SPI0 ((SPI_TypeDef *)SPI0_BASE)
#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
#define SPI0_BUS_CLK_EN (0X01<<4)
#define SPI0_PERI_CLK_EN (0X01<<17)
@@ -400,7 +400,7 @@ typedef struct __KEYPAD {
} KEYPAD_TypeDef;
#define KEYPAD_BASE (0x40015000)
#define KEYPAD ( (KEYPAD_TypeDef *)KEYPAD_BASE )
#define KEYPAD ((KEYPAD_TypeDef *)KEYPAD_BASE)
/*
DUET GPIO definitons
*/
asr582x/liteos_m/sdk/drivers/driver/inc/duet_adc.h
+1 -1
View File
@@ -57,7 +57,7 @@ typedef struct {
};
__IO uint32_t ADC_DATA;
} duet_ADC;
#define ADC (( duet_ADC *)(SYS_REG_BASE_AUXADC))
#define ADC ((duet_ADC *)(SYS_REG_BASE_AUXADC))
#define BIT(pos) (1U<<(pos))
/* Modem Config */
#define MDM_CLKGATEFCTRL0_ADDR 0x60C00874
asr582x/liteos_m/sdk/drivers/driver/inc/duet_dma.h
+9 -9
View File
@@ -85,16 +85,16 @@ typedef enum {
typedef void (*duet_dma_callback_func)(uint32_t);
typedef struct {
uint32_t cycle_ctl: 3;
uint32_t cycle_ctl : 3;
uint32_t next_useburst : 1;
uint32_t n_minus_1: 10;
uint32_t R_pow: 4;
uint32_t src_prot: 3;
uint32_t dest_prot: 3;
uint32_t src_size: 2;
uint32_t src_inc: 2;
uint32_t dst_size: 2;
uint32_t dst_inc: 2;
uint32_t n_minus_1 : 10;
uint32_t R_pow : 4;
uint32_t src_prot : 3;
uint32_t dest_prot : 3;
uint32_t src_size : 2;
uint32_t src_inc : 2;
uint32_t dst_size : 2;
uint32_t dst_inc : 2;
} Chan_Ctl_Data_TypeDef;
asr582x/liteos_m/sdk/drivers/driver/inc/duet_flash.h
+8 -8
View File
@@ -19,16 +19,16 @@
#define LOW_LEVEL_FLASH_RW_SUPPORT 1
#define PAR_OPT_READ_POS ( 0 )
#define PAR_OPT_WRITE_POS ( 1 )
#define PAR_OPT_READ_POS (0)
#define PAR_OPT_WRITE_POS (1)
#define PAR_OPT_READ_MASK ( 0x1u << PAR_OPT_READ_POS )
#define PAR_OPT_WRITE_MASK ( 0x1u << PAR_OPT_WRITE_POS )
#define PAR_OPT_READ_MASK (0x1u << PAR_OPT_READ_POS)
#define PAR_OPT_WRITE_MASK (0x1u << PAR_OPT_WRITE_POS)
#define PAR_OPT_READ_DIS ( 0x0u << PAR_OPT_READ_POS )
#define PAR_OPT_READ_EN ( 0x1u << PAR_OPT_READ_POS )
#define PAR_OPT_WRITE_DIS ( 0x0u << PAR_OPT_WRITE_POS )
#define PAR_OPT_WRITE_EN ( 0x1u << PAR_OPT_WRITE_POS )
#define PAR_OPT_READ_DIS (0x0u << PAR_OPT_READ_POS)
#define PAR_OPT_READ_EN (0x1u << PAR_OPT_READ_POS)
#define PAR_OPT_WRITE_DIS (0x0u << PAR_OPT_WRITE_POS)
#define PAR_OPT_WRITE_EN (0x1u << PAR_OPT_WRITE_POS)
typedef enum {
PARTITION_ERROR = -1,
asr582x/liteos_m/sdk/drivers/driver/inc/duet_i2s.h
+12 -12
View File
@@ -115,26 +115,26 @@ extern "c" {
uint8_t i2s_mode;
} duet_i2s_dev_t;
__STATIC_INLINE ITstatus i2s_get_interrupt_status(I2S_TypeDef * I2Sx, uint32_t i2s_interrupt)
__STATIC_INLINE ITstatus i2s_get_interrupt_status(I2S_TypeDef *I2Sx, uint32_t i2s_interrupt)
{
return (I2Sx->ISR & i2s_interrupt) ? SET : RESET;
}
void duet_i2s_send_data(I2S_TypeDef * I2Sx, uint32_t *left_chan_data, uint32_t *right_chan_data, uint32_t len);
void duet_i2s_send_data(I2S_TypeDef *I2Sx, uint32_t *left_chan_data, uint32_t *right_chan_data, uint32_t len);
void duet_i2s_struct_init(duet_i2s_dev_t *pI2S_struct);
void duet_i2s_interrupt_config(I2S_TypeDef * I2Sx, uint32_t i2s_interrupt, uint32_t new_state);
void duet_i2s_interrupt_clear(I2S_TypeDef * I2Sx, uint32_t i2s_interrupt);
void duet_i2s_cmd(I2S_TypeDef * I2Sx, uint32_t new_state);
void duet_i2s_interrupt_config(I2S_TypeDef *I2Sx, uint32_t i2s_interrupt, uint32_t new_state);
void duet_i2s_interrupt_clear(I2S_TypeDef *I2Sx, uint32_t i2s_interrupt);
void duet_i2s_cmd(I2S_TypeDef *I2Sx, uint32_t new_state);
void duet_i2s_tx_block_cmd(I2S_TypeDef * I2Sx, uint32_t new_state);
void duet_i2s_rx_block_cmd(I2S_TypeDef * I2Sx, uint32_t new_state);
void duet_i2s_tx_channel_cmd(I2S_TypeDef * I2Sx, uint32_t new_state);
void duet_i2s_rx_channel_cmd(I2S_TypeDef * I2Sx, uint32_t new_state);
void duet_i2s_master_clock_cmd(I2S_TypeDef * I2Sx, uint32_t new_state);
int duet_i2s_init(I2S_TypeDef * I2Sx, duet_i2s_dev_t *pI2S_struct);
uint32_t duet_i2s_receive_data(I2S_TypeDef * I2Sx, uint8_t lr);
void duet_i2s_tx_block_cmd(I2S_TypeDef *I2Sx, uint32_t new_state);
void duet_i2s_rx_block_cmd(I2S_TypeDef *I2Sx, uint32_t new_state);
void duet_i2s_tx_channel_cmd(I2S_TypeDef *I2Sx, uint32_t new_state);
void duet_i2s_rx_channel_cmd(I2S_TypeDef *I2Sx, uint32_t new_state);
void duet_i2s_master_clock_cmd(I2S_TypeDef *I2Sx, uint32_t new_state);
int duet_i2s_init(I2S_TypeDef *I2Sx, duet_i2s_dev_t *pI2S_struct);
uint32_t duet_i2s_receive_data(I2S_TypeDef *I2Sx, uint8_t lr);
#ifdef __cplusplus
}
asr582x/liteos_m/sdk/drivers/driver/inc/duet_rnd.h
+7 -7
View File
@@ -44,7 +44,7 @@ int duet_RND_Instantiation(CRYS_RND_Context_t
parameter to any API that uses the RND module.
\note the context must be cleared before sent to the function. */
CRYS_RND_WorkBuff_t *rndWorkBuff_ptr /* !< [in/out] Scratchpad for the RND module's work. */
);
);
/*!
@brief Clears existing RNG instantiation state.
@@ -65,7 +65,7 @@ It implements referenced standard [SP800-90] - 10.2.1.4.2 - CTR-DRBG Reseeding a
*/
int duet_RND_Reseeding(CRYS_RND_Context_t *rndContext_ptr, /* !< [in/out] Pointer to the RND context buffer. */
CRYS_RND_WorkBuff_t *rndWorkBuff_ptr /* !< [in/out] Scratchpad for the RND module's work. */
);
);
/****************************************************************************************/
/*!
@@ -86,7 +86,7 @@ int duet_RND_GenerateVector(CRYS_RND_State_t
Use rndContext->rndState field of the context for this parameter. */
uint16_t outSizeBytes, /* !< [in] The size in bytes of the random vector required. The maximal size is 2^16 -1 bytes. */
uint8_t *out_ptr /* !< [out] The pointer to output buffer. */
);
);
/****************************************************************************************/
/*!
@@ -106,7 +106,7 @@ int duet_RND_SetGenerateVectorFunc(CRYS_RND_Context_t
to the functions used for random vector generation. */
SaSiRndGenerateVectWorkFunc_t rndGenerateVectFunc /* !< [in] Pointer to the random vector generation function.
The pointer should point to the ::CRYS_RND_GenerateVector function. */
);
);
/**********************************************************************************************************/
/*!
@@ -144,7 +144,7 @@ int duet_RND_AddAdditionalInput(CRYS_RND_Context_t
*rndContext_ptr, /* !< [in/out] Pointer to the RND context buffer. */
uint8_t *additonalInput_ptr, /* !< [in] The Additional Input buffer. */
uint16_t additonalInputSize /* !< [in] The size of the Additional Input buffer. Must be <= 48, and a multiple of 4. */
);
);
/*!
@brief The CRYS_RND_EnterKatMode function sets KAT mode bit into StateFlag of global CRYS_RND_WorkingState structure.
@@ -164,7 +164,7 @@ int duet_RND_EnterKatMode(CRYS_RND_Context_t *rndContext_ptr, /* !< [in/out]
CRYS_RND_WorkBuff_t
*workBuff_ptr /* !< [out] RND working buffer, must be the same buffer, which should be passed into
Instantiation/Reseeding functions. */
);
);
/**********************************************************************************************************/
/*!
@@ -176,6 +176,6 @@ The user must call this function after KAT tests before actual using RND module
@return A non-zero value from crys_rnd_error.h on failure.
*/
void duet_RND_DisableKatMode(CRYS_RND_Context_t *rndContext_ptr /* !< [in/out] Pointer to the RND context buffer. */
);
);
#endif // _DUET_RND_H_
asr582x/liteos_m/sdk/drivers/driver/src/duet_adc.c
+1 -1
View File
@@ -58,7 +58,7 @@ int32_t duet_adc_init(duet_adc_dev_t *adc_config)
reg_value = REG_RD(HW_CTRL_PE_PS);
REG_WR(HW_CTRL_PE_PS, (reg_value & (~(1 << config_gpio.port)))); // cfg by// user
reg_value = REG_RD(PAD_PE_REG); //
// REG_WR(PAD_PE_REG, (reg_value|( (1 << gpio->port))));
// REG_WR(PAD_PE_REG, (reg_value|((1 << gpio->port))));
REG_WR(PAD_PE_REG, (reg_value & (~(1 << config_gpio.port))));
// adc_config->duet_adc_handler_struct.cb = adc_config->priv;
if (adc_config->priv) {
asr582x/liteos_m/sdk/drivers/driver/src/duet_dma.c
+17 -17
View File
@@ -43,7 +43,7 @@ void duet_dma_interrupt_clear(uint32_t chan_idx)
ITstatus duet_dma_get_interrupt_status(uint32_t chan_idx)
{
if ( DMA_INT_STAT & (1 << chan_idx) ) {
if (DMA_INT_STAT & (1 << chan_idx)) {
return SET;
} else {
return RESET;
@@ -52,7 +52,7 @@ ITstatus duet_dma_get_interrupt_status(uint32_t chan_idx)
void duet_dma_interrupt_config(uint32_t chan_idx, uint8_t new_state)
{
if ( new_state == ENABLE ) {
if (new_state == ENABLE) {
DMA_INT_MASK |= (1 << chan_idx); // write 1 to unmask
} else {
DMA_INT_MASK &= ~(1 << chan_idx);
@@ -61,7 +61,7 @@ void duet_dma_interrupt_config(uint32_t chan_idx, uint8_t new_state)
void duet_dma_channel_cmd(uint32_t chan_idx, uint8_t new_state)
{
if ( new_state == ENABLE ) {
if (new_state == ENABLE) {
DMA->CHAN_EN_SET |= (1 << chan_idx);
} else {
DMA->CHAN_EN_CLR |= (1 << chan_idx);
@@ -70,7 +70,7 @@ void duet_dma_channel_cmd(uint32_t chan_idx, uint8_t new_state)
void duet_dma_alt_channel_cmd(uint32_t chan_idx, uint8_t new_state)
{
if ( new_state == ENABLE ) {
if (new_state == ENABLE) {
DMA->CHAN_PRI_ALT_SET |= (1 << chan_idx);
} else {
DMA->CHAN_PRI_ALT_CLR |= (1 << chan_idx);
@@ -125,13 +125,13 @@ void duet_dma_uart_rx(uint8_t uart_idx, uint8_t *data, uint16_t len)
UART_TypeDef *UARTx;
UARTx = NULL;
dma_chan = 0;
if ( uart_idx == 2) {
if (uart_idx == 2) {
dma_chan = 5; // uart2 rx channel
UARTx = UART2;
} else if ( uart_idx == 1) {
} else if (uart_idx == 1) {
dma_chan = 3; // uart1 rx channel
UARTx = UART1;
} else if ( uart_idx == 0) {
} else if (uart_idx == 0) {
dma_chan = 1; // uart0 rx channel
UARTx = UART0;
} else {
@@ -172,13 +172,13 @@ void duet_dma_uart_tx(uint8_t uart_idx, uint8_t *data, uint16_t len)
uint8_t dma_chan = 0;
UART_TypeDef *UARTx = NULL;
if ( uart_idx == 2) {
if (uart_idx == 2) {
dma_chan = 4; // uart2 tx channel
UARTx = UART2;
} else if ( uart_idx == 1) {
} else if (uart_idx == 1) {
dma_chan = 2; // uart1 tx channel
UARTx = UART1;
} else if ( uart_idx == 0) {
} else if (uart_idx == 0) {
dma_chan = 0; // uart0 tx channel
UARTx = UART0;
} else {
@@ -219,13 +219,13 @@ void duet_dma_spi_tx(uint8_t ssp_idx, uint8_t *data, uint16_t len)
// malloc for channel descriptor
Chan_Cfg_TypeDef *pChan_Cfg_Align = duet_dma_ctrl_block_init();
SPI_TypeDef *SPIx = NULL;
if ( ssp_idx == 0) {
if (ssp_idx == 0) {
dma_chan = 6; // SPI0 tx channel
SPIx = SPI0;
} else if ( ssp_idx == 1) {
} else if (ssp_idx == 1) {
dma_chan = 8; // SPI1 tx channel
SPIx = SPI1;
} else if ( ssp_idx == 2) {
} else if (ssp_idx == 2) {
dma_chan = 10; // SPI2 tx channel
SPIx = SPI2;
} else {
@@ -268,13 +268,13 @@ void duet_dma_spi_rx(uint8_t ssp_idx, uint8_t *data, uint16_t len)
Chan_Ctl_Data_TypeDef ch_ctl_data;
Chan_Cfg_TypeDef ch_cfg;
SPI_TypeDef *SPIx = NULL;
if ( ssp_idx == 0) {
if (ssp_idx == 0) {
dma_chan = 7; // SPI0 Rx channel
SPIx = SPI0;
} else if ( ssp_idx == 1) {
} else if (ssp_idx == 1) {
dma_chan = 9; // SPI1 Rx channel
SPIx = SPI1;
} else if ( ssp_idx == 2) {
} else if (ssp_idx == 2) {
dma_chan = 11; // SPI2 Rx channel
SPIx = SPI2;
} else {
@@ -320,7 +320,7 @@ void DMA_IRQHandler(void)
uint8_t i;
uint32_t chan_used = DMA_INT_STAT; // get all enabled channels
for (i = 0; i < DMA_MAX_CHAN_NUM; i++) {
if ( chan_used & (1 << i)) {
if (chan_used & (1 << i)) {
duet_dma_interrupt_clear(i);
if (g_duet_dma_callback_handler[i] != NULL) {
g_duet_dma_callback_handler[i](i);
asr582x/liteos_m/sdk/drivers/driver/src/duet_flash.c
+8 -8
View File
@@ -98,7 +98,7 @@ static int32_t refresh_flash_sector(duet_partition_t current_partition, uint32_t
uint32_t end_offset = start_offset + len;
memset(tmpbuf, 0, SPI_FLASH_SEC_SIZE);
if ((FLASH_ACCESS_CONTROL0_DEFAULT_VALUE == FLASH_ACCESS_CONTROL0)
&& (FLASH_ACCESS_CONTROL1_DEFAULT_VALUE == FLASH_ACCESS_CONTROL1) ) { // default flash remapping
&& (FLASH_ACCESS_CONTROL1_DEFAULT_VALUE == FLASH_ACCESS_CONTROL1)) { // default flash remapping
tran_partition = current_partition;
} else {
if (current_partition == PARTITION_OTA_TEMP) {
@@ -219,7 +219,7 @@ int32_t duet_flash_erase(duet_partition_t in_partition, uint32_t off_set, uint32
int32_t ret = 0;
duet_logic_partition_t *partition_info;
partition_info = duet_flash_get_info( in_partition );
partition_info = duet_flash_get_info(in_partition);
if (size + off_set > partition_info->partition_length) {
return EIO;
}
@@ -294,7 +294,7 @@ int32_t duet_flash_write(duet_partition_t in_partition, uint32_t *off_set,
uint32_t prg_size;
uint32_t left_buf_len = in_buf_len;
partition_info = duet_flash_get_info( in_partition );
partition_info = duet_flash_get_info(in_partition);
if (off_set == NULL || in_buf == NULL || ((*off_set + in_buf_len) > partition_info->partition_length)) {
// ptr and size over range check
return EIO;
@@ -365,7 +365,7 @@ int32_t duet_flash_read(duet_partition_t in_partition, uint32_t *off_set,
uint32_t start_addr;
duet_logic_partition_t *partition_info;
partition_info = duet_flash_get_info( in_partition );
partition_info = duet_flash_get_info(in_partition);
if (off_set == NULL || out_buf == NULL || *off_set + in_buf_len > partition_info->partition_length) {
return EIO;
@@ -389,7 +389,7 @@ int32_t duet_flash_read_common(uint32_t addr,
return -1;
}
partition_info = duet_flash_get_info(current_partition);
if (addr == 0 || ((addr + in_buf_len) > ( partition_info->partition_start_addr + partition_info->partition_length)) \
if (addr == 0 || ((addr + in_buf_len) > (partition_info->partition_start_addr + partition_info->partition_length)) \
|| (addr < partition_info->partition_start_addr)) {
return -1;
}
@@ -427,7 +427,7 @@ int32_t duet_flash_erase_common(uint32_t addr, uint32_t len)
return -1;
}
partition_info = duet_flash_get_info(current_partition);
if (addr == 0 || ((addr + len) > ( partition_info->partition_start_addr + partition_info->partition_length)) \
if (addr == 0 || ((addr + len) > (partition_info->partition_start_addr + partition_info->partition_length)) \
|| (addr < partition_info->partition_start_addr)) {
return -1;
}
@@ -490,7 +490,7 @@ int32_t duet_flash_write_common(uint32_t addr, const void *in_buff, uint32_t len
}
partition_info = duet_flash_get_info(current_partition);
if (addr == 0 || in_buff == NULL
|| ((addr + len) > ( partition_info->partition_start_addr + partition_info->partition_length)) \
|| ((addr + len) > (partition_info->partition_start_addr + partition_info->partition_length)) \
|| (addr < partition_info->partition_start_addr)) {
return -1;
}
@@ -550,7 +550,7 @@ int32_t duet_flash_write_saved(duet_partition_t in_partition, uint32_t *off_set,
uint8_t *buf_malloc = NULL;
uint32_t off_set_tmp = 0;
uint32_t len_tmp = 0;
partition_info = duet_flash_get_info( in_partition );
partition_info = duet_flash_get_info(in_partition);
if (off_set == NULL || in_buf == NULL || ((*off_set + in_buf_len) > partition_info->partition_length)) {
return -1;
}
asr582x/liteos_m/sdk/drivers/driver/src/duet_flash_encrypt.c
+1 -1
View File
@@ -52,7 +52,7 @@ int switch_flash_encrypt(void)
int duet_flash_encrypt(void)
{
if ( duet_flash_encrypt_status()) {
if (duet_flash_encrypt_status()) {
return 0;
}
asr582x/liteos_m/sdk/drivers/driver/src/duet_i2c.c
+33 -33
View File
@@ -33,16 +33,16 @@ duet_i2c_priv_cfg_t duet_i2c_priv_cfg = {
void I2C0_IRQHandler(void)
{
duet_intrpt_enter();
if ( (I2C0->SR) & I2C_STATUS_TRANS_DONE) {
if ((I2C0->SR) & I2C_STATUS_TRANS_DONE) {
// printf("I2C0 trans done interrupt\n");
I2C0->CR &= (~I2C_CR_SEND_STOP);
I2C0->SR |= I2C_STATUS_TRANS_DONE;
}
if ( (I2C0->SR) & I2C_STATUS_SLAVE_ADDR_DET) {
if ((I2C0->SR) & I2C_STATUS_SLAVE_ADDR_DET) {
printf("I2C0 slave addr det\n");
I2C0->SR |= I2C_STATUS_SLAVE_ADDR_DET;
}
if ( (I2C0->SR) & I2C_STATUS_RX_FIFO_FULL) {
if ((I2C0->SR) & I2C_STATUS_RX_FIFO_FULL) {
printf("I2C0 I2C_STATUS_RX_FIFO_FULL\n");
I2C0->SR |= I2C_STATUS_RX_FIFO_FULL;
}
@@ -52,15 +52,15 @@ void I2C1_IRQHandler(void)
{
duet_intrpt_enter();
if ( (I2C1->SR) & I2C_STATUS_TRANS_DONE) {
if ((I2C1->SR) & I2C_STATUS_TRANS_DONE) {
printf("I2C1 trans done interrupt\n");
I2C1->SR |= I2C_STATUS_TRANS_DONE;
}
if ( (I2C1->SR) & I2C_STATUS_SLAVE_ADDR_DET) {
if ((I2C1->SR) & I2C_STATUS_SLAVE_ADDR_DET) {
printf("I2C1 slave addr det\n");
I2C1->SR |= I2C_STATUS_SLAVE_ADDR_DET;
}
if ( (I2C1->SR) & I2C_STATUS_RX_FIFO_HALF_FULL) {
if ((I2C1->SR) & I2C_STATUS_RX_FIFO_HALF_FULL) {
printf("I2C1 RX_FIFO_HALF_FULL\n");
I2C1->SR |= I2C_STATUS_RX_FIFO_HALF_FULL;
}
@@ -69,14 +69,14 @@ void I2C1_IRQHandler(void)
ITstatus i2c_get_flag_status(I2C_TypeDef *I2Cx, uint32_t I2C_flag)
{
if (I2C_flag == I2C_STATUS_TX_FIFO_EMPTY) {
if ( I2Cx->WFIFO_WPTR != I2Cx->WFIFO_RPTR) {
if (I2Cx->WFIFO_WPTR != I2Cx->WFIFO_RPTR) {
return RESET;
} else {
return SET;
}
} else if (I2C_flag == I2C_STATUS_TX_FIFO_FULL) {
if ( (I2Cx->WFIFO_WPTR > I2Cx->WFIFO_RPTR) ? (I2Cx->WFIFO_WPTR - I2Cx->WFIFO_RPTR) :
(I2Cx->WFIFO_RPTR - I2Cx->WFIFO_WPTR) != I2C_TX_FIFO_DEPTH ) {
if ((I2Cx->WFIFO_WPTR > I2Cx->WFIFO_RPTR) ? (I2Cx->WFIFO_WPTR - I2Cx->WFIFO_RPTR) :
(I2Cx->WFIFO_RPTR - I2Cx->WFIFO_WPTR) != I2C_TX_FIFO_DEPTH) {
return RESET;
} else {
return SET;
@@ -90,15 +90,15 @@ ITstatus i2c_get_flag_status(I2C_TypeDef *I2Cx, uint32_t I2C_flag)
}
}
int32_t duet_i2c_reset( I2C_TypeDef *I2Cx)
int32_t duet_i2c_reset(I2C_TypeDef *I2Cx)
{
/* check unit busy */
int32_t temp = I2C_WAIT_FOREVER;
while ( i2c_get_flag_status(I2Cx, I2C_STATUS_UNIT_BUSY) ) {
while (i2c_get_flag_status(I2Cx, I2C_STATUS_UNIT_BUSY)) {
temp --;
}
if ( temp ) {
if (temp) {
I2Cx->CR &= I2C_UNIT_RESET; // clear rest of CR
I2Cx->CR |= I2C_UNIT_RESET; // set RESET bit
I2Cx->SR = 0;
@@ -242,7 +242,7 @@ int32_t duet_i2c_init(duet_i2c_dev_t *i2c)
}
/* check the bus busy after unit enable */
if ( i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_BUSY) ) {
if (i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_BUSY)) {
return EIO;
} else {
return 0;
@@ -294,7 +294,7 @@ int32_t duet_i2c_master_send(duet_i2c_dev_t *i2c, uint16_t dev_addr, const uint8
// send write cmd
while (1) {
//wait till tx fifo is empty to avoid overflowing tx fifo
while ( !i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY) ) {
while (!i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY)) {
if (g_duet_i2c_timeout) {
g_duet_i2c_timeout = 0;
ret = -ETIMEOUT;
@@ -311,7 +311,7 @@ int32_t duet_i2c_master_send(duet_i2c_dev_t *i2c, uint16_t dev_addr, const uint8
goto EXIT;
}
if ( i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET) ) {
if (i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET)) {
ret = -EBUSERR; // bus error
goto EXIT;
} else {
@@ -328,7 +328,7 @@ int32_t duet_i2c_master_send(duet_i2c_dev_t *i2c, uint16_t dev_addr, const uint8
goto EXIT;
}
if ( i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET) ) {
if (i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET)) {
ret = -EBUSERR; // bus error
goto EXIT;
} else {
@@ -394,7 +394,7 @@ int32_t duet_i2c_master_recv(duet_i2c_dev_t *i2c, uint16_t dev_addr, uint8_t *da
ret = -ETIMEOUT;
goto EXIT;
}
while ( !i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY) ) {
while (!i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY)) {
if (g_duet_i2c_timeout) {
g_duet_i2c_timeout = 0;
ret = -ETIMEOUT;
@@ -442,12 +442,12 @@ int8_t duet_i2c_master_repeated_write_read(I2C_TypeDef *I2Cx, uint8_t slave_addr
// send write cmd
while (1) {
//wait till tx fifo is empty to avoid overflowing tx fifo
while ( !i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY) );
while (!i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY));
if (wlen > I2C_TX_FIFO_DEPTH) {
// send 8 bytes
for (temp = 0; temp < I2C_TX_FIFO_DEPTH; temp++) {
if ( i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET) ) {
if (i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET)) {
return EIO; // bus error
} else {
I2Cx->WFIFO = (*pwdata++) | I2C_TB;
@@ -457,7 +457,7 @@ int8_t duet_i2c_master_repeated_write_read(I2C_TypeDef *I2Cx, uint8_t slave_addr
} else {
// send remaining bytes
for (temp = 0; temp < wlen; temp++) {
if ( i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET) ) {
if (i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET)) {
return EIO; // bus error
} else {
if (temp == wlen - 1) {
@@ -473,15 +473,15 @@ int8_t duet_i2c_master_repeated_write_read(I2C_TypeDef *I2Cx, uint8_t slave_addr
}
/**** master read ****/
while ( !i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY) );
while (!i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY));
// send slave address first
I2Cx->WFIFO = (slave_addr << 1) | I2C_READ | I2C_SEND_START | I2C_TB;
while (i < rlen) {
while ( !i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY) );
while (!i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY));
if ((rlen - 1) == i) {
I2Cx->WFIFO = I2C_SEND_STOP | I2C_SEND_NACK | I2C_TB;
while ( !i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY) );
while (!i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY));
} else {
I2Cx->WFIFO = I2C_TB;
}
@@ -538,7 +538,7 @@ int32_t duet_i2c_mem_write(duet_i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_
i2c_write_byte(I2Cx, ((uint8_t)dev_addr << 1) | I2C_WRITE | I2C_SEND_START | I2C_TB);
// send memory address
for ( i = 0; i < mem_addr_size; i++) {
for (i = 0; i < mem_addr_size; i++) {
i2c_write_byte(I2Cx, ((mem_addr >> (8 * i)) & 0xff) | I2C_WRITE | I2C_TB);
}
@@ -550,7 +550,7 @@ int32_t duet_i2c_mem_write(duet_i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_
goto EXIT;
}
//wait till tx fifo is empty to avoid overflowing tx fifo
while ( !i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY) ) {
while (!i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY)) {
if (g_duet_i2c_timeout) {
g_duet_i2c_timeout = 0;
ret = -ETIMEOUT;
@@ -567,7 +567,7 @@ int32_t duet_i2c_mem_write(duet_i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_
goto EXIT;
}
if ( i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET) ) {
if (i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET)) {
ret = -EBUSERR; // bus error
goto EXIT;
} else {
@@ -584,7 +584,7 @@ int32_t duet_i2c_mem_write(duet_i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_
goto EXIT;
}
if ( i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET) ) {
if (i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET)) {
ret = -EBUSERR; // bus error
goto EXIT;
} else {
@@ -647,7 +647,7 @@ int32_t duet_i2c_mem_read(duet_i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_a
i2c_write_byte(I2Cx, ((uint8_t)dev_addr << 1) | I2C_WRITE | I2C_SEND_START | I2C_TB);
// send memory address
for ( i = 0; i < mem_addr_size; i++) {
for (i = 0; i < mem_addr_size; i++) {
if (g_duet_i2c_timeout) {
g_duet_i2c_timeout = 0;
ret = -ETIMEOUT;
@@ -656,7 +656,7 @@ int32_t duet_i2c_mem_read(duet_i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_a
i2c_write_byte(I2Cx, ((mem_addr >> (8 * i)) & 0xff) | I2C_WRITE | I2C_TB);
}
/**** master read ****/
while ( !i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY) );
while (!i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY));
// send slave address first
i2c_write_byte(I2Cx, (dev_addr << 1) | I2C_READ | I2C_SEND_START | I2C_TB);
@@ -665,7 +665,7 @@ int32_t duet_i2c_mem_read(duet_i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_a
// send read cmd
while (i < size) {
//wait till tx fifo is empty to avoid overflowing tx fifo
while ( !i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY) );
while (!i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY));
if (g_duet_i2c_timeout) {
g_duet_i2c_timeout = 0;
@@ -673,13 +673,13 @@ int32_t duet_i2c_mem_read(duet_i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_a
goto EXIT;
}
if ( i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET) ) {
if (i2c_get_flag_status(I2Cx, I2C_STATUS_BUS_ERROR_DET)) {
ret = -EBUSERR; // bus error
goto EXIT;
} else {
if (i == size - 1) {
i2c_write_byte(I2Cx, I2C_SEND_STOP | I2C_SEND_NACK | I2C_TB);
while ( !i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY) );
while (!i2c_get_flag_status(I2Cx, I2C_STATUS_TX_FIFO_EMPTY));
ret = I2C_SUCCESS;
while (!(I2Cx->RFIFO_STATUS & 0xF0)) {
if (g_duet_i2c_timeout) {
@@ -774,7 +774,7 @@ void duet_i2c_master_dma_send(uint8_t iic_idx, uint32_t *data, uint16_t len)
{
uint8_t dma_chan = 0;
I2C_TypeDef *I2Cx = 0;
if ( iic_idx == 0) {
if (iic_idx == 0) {
dma_chan = 12;
I2Cx = I2C0;
}
asr582x/liteos_m/sdk/drivers/driver/src/duet_i2s.c
+13 -13
View File
@@ -33,7 +33,7 @@ void duet_i2s_struct_init(duet_i2s_dev_t *pI2S_struct)
void duet_i2s_interrupt_config(I2S_TypeDef *I2Sx, uint32_t i2s_interrupt, uint32_t new_state)
{
if ( new_state == ENABLE) {
if (new_state == ENABLE) {
I2Sx->IMR &= ~i2s_interrupt;
} else {
I2Sx->IMR |= i2s_interrupt;
@@ -42,16 +42,16 @@ void duet_i2s_interrupt_config(I2S_TypeDef *I2Sx, uint32_t i2s_interrupt, uint32
void duet_i2s_interrupt_clear(I2S_TypeDef *I2Sx, uint32_t i2s_interrupt)
{
if ( i2s_interrupt == I2S_INTERRUPT_TXFO ) {
if (i2s_interrupt == I2S_INTERRUPT_TXFO) {
I2Sx->TOR; // read to clear interrupt
} else if ( i2s_interrupt == I2S_INTERRUPT_RXFO ) {
} else if (i2s_interrupt == I2S_INTERRUPT_RXFO) {
I2Sx->ROR;
}
}
void duet_i2s_cmd(I2S_TypeDef *I2Sx, uint32_t new_state)
{
if ( new_state == ENABLE ) {
if (new_state == ENABLE) {
I2Sx->IER |= ENABLE;
} else {
I2Sx->IER &= DISABLE;
@@ -60,7 +60,7 @@ void duet_i2s_cmd(I2S_TypeDef *I2Sx, uint32_t new_state)
void duet_i2s_tx_block_cmd(I2S_TypeDef *I2Sx, uint32_t new_state)
{
if ( new_state == ENABLE ) {
if (new_state == ENABLE) {
I2Sx->ITER |= ENABLE;
} else {
I2Sx->ITER &= DISABLE;
@@ -69,7 +69,7 @@ void duet_i2s_tx_block_cmd(I2S_TypeDef *I2Sx, uint32_t new_state)
void duet_i2s_rx_block_cmd(I2S_TypeDef *I2Sx, uint32_t new_state)
{
if ( new_state == ENABLE ) {
if (new_state == ENABLE) {
I2Sx->IRER |= ENABLE;
} else {
I2Sx->IRER &= DISABLE;
@@ -78,7 +78,7 @@ void duet_i2s_rx_block_cmd(I2S_TypeDef *I2Sx, uint32_t new_state)
void duet_i2s_tx_channel_cmd(I2S_TypeDef *I2Sx, uint32_t new_state)
{
if ( new_state == ENABLE ) {
if (new_state == ENABLE) {
I2Sx->TER |= ENABLE;
} else {
I2Sx->TER &= DISABLE;
@@ -87,7 +87,7 @@ void duet_i2s_tx_channel_cmd(I2S_TypeDef *I2Sx, uint32_t new_state)
void duet_i2s_rx_channel_cmd(I2S_TypeDef *I2Sx, uint32_t new_state)
{
if ( new_state == ENABLE ) {
if (new_state == ENABLE) {
I2Sx->RER |= ENABLE;
} else {
I2Sx->RER &= DISABLE;
@@ -96,7 +96,7 @@ void duet_i2s_rx_channel_cmd(I2S_TypeDef *I2Sx, uint32_t new_state)
void duet_i2s_master_clock_cmd(I2S_TypeDef *I2Sx, uint32_t new_state)
{
if ( new_state == ENABLE) {
if (new_state == ENABLE) {
I2Sx->CER |= ENABLE;
REG_WR(0X40000844, (0x1 << 13) | (0x1 << 24)); // open clock source of i2s
} else {
@@ -197,20 +197,20 @@ uint32_t duet_i2s_receive_data(I2S_TypeDef *I2Sx, uint8_t lr)
void duet_i2s_send_data(I2S_TypeDef *I2Sx, uint32_t *left_chan_data, uint32_t *right_chan_data, uint32_t len)
{
while (len) {
while ( !i2s_get_interrupt_status(I2Sx, I2S_INTERRUPT_TXFE) ); // wait till tx fifo emptys
for ( int i = 0; i < I2S_FIFO_DEPTH && len > 0; i++, len--) {
while (!i2s_get_interrupt_status(I2Sx, I2S_INTERRUPT_TXFE)); // wait till tx fifo emptys
for (int i = 0; i < I2S_FIFO_DEPTH && len > 0; i++, len--) {
I2Sx->LRBR_LTHR = *left_chan_data++;
I2Sx->RRBR_RTHR = *right_chan_data++;
}
}
while ( !i2s_get_interrupt_status(I2Sx, I2S_INTERRUPT_TXFE) ); // wait till tx fifo emptys
while (!i2s_get_interrupt_status(I2Sx, I2S_INTERRUPT_TXFE)); // wait till tx fifo emptys
}
void I2S_IRQHandler(void)
{
uint32_t g_data_l = 0;
uint32_t g_data_r = 0;
if ( i2s_get_interrupt_status(I2S, I2S_INTERRUPT_RXDA) ) { // rx data available
if (i2s_get_interrupt_status(I2S, I2S_INTERRUPT_RXDA)) { // rx data available
g_data_l = I2S->LRBR_LTHR;
g_data_r = I2S->RRBR_RTHR;
if (g_duet_i2s_callback_handler != NULL) {
asr582x/liteos_m/sdk/drivers/driver/src/duet_psram.c
+6 -6
View File
@@ -90,7 +90,7 @@ static void psram_init_lut_ps_mode_register_read(unsigned int seq_id)
((PSRAM_CMD_ADDR << 26) | (0x0 << 24) | (0x18 << 16) | (PSRAM_CMD_CMD << 10) | (0x0 << 8) | FLASH_CMD_MODE_REG_READ));
REG_WR((PSRAM_LUT1 + 0x10 * seq_id),
((PSRAM_CMD_READ << 26) | (0x0 << 24) | (0x2 << 16) | (PSRAM_CMD_DUMMY << 10) | (0x0 << 8) | (8 - 1)));
REG_WR((PSRAM_LUT2 + 0x10 * seq_id), ( (PSRAM_CMD_JMP_ON_CS << 10) | (0x0 << 8) | 0x0));
REG_WR((PSRAM_LUT2 + 0x10 * seq_id), ((PSRAM_CMD_JMP_ON_CS << 10) | (0x0 << 8) | 0x0));
REG_WR((PSRAM_LUT3 + 0x10 * seq_id), 0);
}
@@ -126,7 +126,7 @@ static void psram_init_lut_ps_read_4x(unsigned int seq_id)
((PSRAM_CMD_ADDR << 26) | (0x2 << 24) | (0x18 << 16) | (PSRAM_CMD_CMD << 10) | (0x2 << 8) | FLASH_CMD_FAST_READ_QUAD));
REG_WR((PSRAM_LUT1 + 0x10 * seq_id),
((PSRAM_CMD_READ << 26) | (0x2 << 24) | (0x20 << 16) | (PSRAM_CMD_DUMMY << 10) | (0x2 << 8) | (6 - 1)));
REG_WR((PSRAM_LUT2 + 0x10 * seq_id), ((PSRAM_CMD_JMP_ON_CS << 10) | (0x2 << 8) | 0x00) );
REG_WR((PSRAM_LUT2 + 0x10 * seq_id), ((PSRAM_CMD_JMP_ON_CS << 10) | (0x2 << 8) | 0x00));
REG_WR((PSRAM_LUT3 + 0x10 * seq_id), 0);
}
@@ -152,8 +152,8 @@ static void psram_init_lut_ps_write_evict_4x(unsigned int seq_id)
static void psram_init_lut_ps_readid(unsigned int seq_id)
{
REG_WR((PSRAM_LUT0 + 0x10 * seq_id),
( (PSRAM_CMD_ADDR << 26) | (0x0 << 24) | (0x18 << 16) | (PSRAM_CMD_CMD << 10) | (0x0 << 8) | FLASH_CMD_READ_ID));
REG_WR((PSRAM_LUT1 + 0x10 * seq_id), ( (PSRAM_CMD_READ << 10) | (0x0 << 8) | 0x9));
((PSRAM_CMD_ADDR << 26) | (0x0 << 24) | (0x18 << 16) | (PSRAM_CMD_CMD << 10) | (0x0 << 8) | FLASH_CMD_READ_ID));
REG_WR((PSRAM_LUT1 + 0x10 * seq_id), ((PSRAM_CMD_READ << 10) | (0x0 << 8) | 0x9));
REG_WR((PSRAM_LUT2 + 0x10 * seq_id), 0);
REG_WR((PSRAM_LUT3 + 0x10 * seq_id), 0);
}
@@ -239,13 +239,13 @@ int psram_config(duet_psram_mode mode)
// REG_WR(PSRAM_FLSHCR, REG_RD(PSRAM_FLSHCR)| 0x00010000);
// MCR SCLKCFG 0, dqs en =1
REG_WR(PSRAM_MCR, REG_RD(PSRAM_MCR) & 0xfbffffff );
REG_WR(PSRAM_MCR, REG_RD(PSRAM_MCR) & 0xfbffffff);
// dqs_loopback_en = 1, dqs_loopback_from_pad = 1
REG_WR(PSRAM_MCR, REG_RD(PSRAM_MCR) | (3 << 24));
// ddr_en = 1, enable 2x and 4x clock
/// REG_WR(PSRAM_MCR, REG_RD(PSRAM_MCR)| 1<<7 );
/// REG_WR(PSRAM_MCR, REG_RD(PSRAM_MCR)| 1<<7);
// MDIS = 0, enable psram clocks,must clear MDIS to enable clock for transfer.
REG_WR(PSRAM_MCR, REG_RD(PSRAM_MCR) & 0xffffbfff);
asr582x/liteos_m/sdk/drivers/driver/src/duet_rf_spi.c
+1 -1
View File
@@ -63,7 +63,7 @@ uint16_t spi_sw_protect_read(uint16_t addr)
while (1) {
if (*((volatile int *)(SPI_COMMAND + START_FLAG_OFT)) == 0) {
return ( (uint16_t) * ((volatile uint32_t *)(SPI_RDATA + RDATA_REG_OFT)));
return ((uint16_t) *((volatile uint32_t *)(SPI_RDATA + RDATA_REG_OFT)));
}
}
asr582x/liteos_m/sdk/drivers/driver/src/duet_spi.c
+7 -7
View File
@@ -294,7 +294,7 @@ int32_t duet_spi_send(duet_spi_dev_t *spi, const uint8_t *data, uint16_t size, u
return EIO;
}
while (size--) {
while ( !(duet_spi_get_flag_status(SPIx, SPI_FLAG_TX_FIFO_NOT_FULL)) ); // wait till tx fifo is not full
while (!(duet_spi_get_flag_status(SPIx, SPI_FLAG_TX_FIFO_NOT_FULL))); // wait till tx fifo is not full
SPIx->DR = *data++;
}
return 0;
@@ -302,9 +302,9 @@ int32_t duet_spi_send(duet_spi_dev_t *spi, const uint8_t *data, uint16_t size, u
// void duet_spi_receive(SPI_TypeDef * SPIx, void * rx_data, uint16_t len)
// {
// while(len--)
// while (len--)
// {
// while( !(spi_get_flag_status(SPIx, SPI_FLAG_RX_FIFO_NOT_EMPTY)) ); // wait till rx fifo is not empty, change to timeout mechanism???
// while (!(spi_get_flag_status(SPIx, SPI_FLAG_RX_FIFO_NOT_EMPTY))); // wait till rx fifo is not empty, change to timeout mechanism???
// *rx_data++ = SPIx->DR ;
// }
@@ -329,16 +329,16 @@ void SPIX_IRQHandler(uint8_t spi_idx)
{
uint16_t tmp;
SPI_TypeDef *SPIx = getSpixViaIdx(spi_idx);
if ( duet_spi_get_interrupt_status(SPIx, SPI_INTERRUPT_TX_FIFO_TRIGGER)) {
if (duet_spi_get_interrupt_status(SPIx, SPI_INTERRUPT_TX_FIFO_TRIGGER)) {
duet_spi_interrupt_config(SPIx, SPI_INTERRUPT_TX_FIFO_TRIGGER, DISABLE); // disable
duet_spi_interrupt_clear(SPIx, SPI_INTERRUPT_TX_FIFO_TRIGGER); // clear
duet_spi_interrupt_config(SPIx, SPI_INTERRUPT_TX_FIFO_TRIGGER, ENABLE); // enable
}
if ( duet_spi_get_interrupt_status(SPIx, SPI_INTERRUPT_RX_FIFO_TRIGGER)
|| duet_spi_get_interrupt_status(SPIx, SPI_INTERRUPT_RX_TIMEOUT) ) {
if (duet_spi_get_interrupt_status(SPIx, SPI_INTERRUPT_RX_FIFO_TRIGGER)
|| duet_spi_get_interrupt_status(SPIx, SPI_INTERRUPT_RX_TIMEOUT)) {
duet_spi_interrupt_config(SPIx, SPI_INTERRUPT_RX_FIFO_TRIGGER | SPI_INTERRUPT_RX_TIMEOUT, DISABLE); // disable
duet_spi_interrupt_clear(SPIx, SPI_INTERRUPT_RX_FIFO_TRIGGER | SPI_INTERRUPT_RX_TIMEOUT); // clear
while ( SPIx->SR & SPI_FLAG_RX_FIFO_NOT_EMPTY) {
while (SPIx->SR & SPI_FLAG_RX_FIFO_NOT_EMPTY) {
tmp = (uint16_t)(SPIx->DR);
if (g_duet_spi_callback_handler[spi_idx] != NULL) {
g_duet_spi_callback_handler[spi_idx](tmp);
asr582x/liteos_m/sdk/drivers/driver/src/duet_uart.c
+8 -8
View File
@@ -91,14 +91,14 @@ void UART_SendData(UART_TypeDef *UARTx, unsigned char Data)
return;
}
/* wait till tx fifo is not full */
while ( duet_uart_get_flag_status(UARTx, UART_FLAG_TX_FIFO_FULL) == SET );
while (duet_uart_get_flag_status(UARTx, UART_FLAG_TX_FIFO_FULL) == SET);
UARTx->DR = Data;
}
uint8_t UART_ReceiveData(UART_TypeDef *UARTx)
{
/* wait till rx fifo is not empty */
while ( duet_uart_get_flag_status(UARTx, UART_FLAG_RX_FIFO_EMPTY) == SET);
while (duet_uart_get_flag_status(UARTx, UART_FLAG_RX_FIFO_EMPTY) == SET);
return UARTx->DR;
}
@@ -113,7 +113,7 @@ void duet_uart_interrupt_config(UART_TypeDef *UARTx, uint32_t uart_int, bool new
ITstatus duet_uart_get_interrupt_status(UART_TypeDef *UARTx, uint32_t uart_interrupt)
{
if ( UARTx->MIS & uart_interrupt ) {
if (UARTx->MIS & uart_interrupt) {
return SET;
} else {
return RESET;
@@ -122,7 +122,7 @@ ITstatus duet_uart_get_interrupt_status(UART_TypeDef *UARTx, uint32_t uart_inter
ITstatus duet_uart_get_raw_interrupt_status(UART_TypeDef *UARTx, uint32_t uart_interrupt)
{
if ( UARTx->RIS & uart_interrupt ) {
if (UARTx->RIS & uart_interrupt) {
return SET;
} else {
return RESET;
@@ -416,14 +416,14 @@ static void UARTX_IRQHandler(uint8_t uart_idx)
{
char tmp;
UART_TypeDef *UARTx = getUartxViaIdx(uart_idx);
if ( duet_uart_get_interrupt_status(UARTx, UART_RX_INTERRUPT)
if (duet_uart_get_interrupt_status(UARTx, UART_RX_INTERRUPT)
|| duet_uart_get_interrupt_status(UARTx, UART_RX_TIMEOUT_INTERRUPT)) {
duet_uart_interrupt_config(UARTx, UART_RX_INTERRUPT | UART_RX_TIMEOUT_INTERRUPT, DISABLE);
duet_uart_clear_interrupt(UARTx, UART_RX_INTERRUPT | UART_RX_TIMEOUT_INTERRUPT);
/* read rx fifo till it's empty */
while ( ! duet_uart_get_flag_status(UARTx, UART_FLAG_RX_FIFO_EMPTY) ) {
tmp = (char)(UARTx->DR); // uart_receive_data(UART );
while (! duet_uart_get_flag_status(UARTx, UART_FLAG_RX_FIFO_EMPTY)) {
tmp = (char)(UARTx->DR); // uart_receive_data(UART);
if (g_duet_uart_callback_handler[uart_idx] != NULL) {
g_duet_uart_callback_handler[uart_idx](tmp);
}
@@ -441,7 +441,7 @@ static void UARTX_Shell_IRQHandler(uint8_t uart_idx)
{
// char tmp;
UART_TypeDef *UARTx = getUartxViaIdx(uart_idx);
if ( duet_uart_get_interrupt_status(UARTx, UART_RX_INTERRUPT)
if (duet_uart_get_interrupt_status(UARTx, UART_RX_INTERRUPT)
|| duet_uart_get_interrupt_status(UARTx, UART_RX_TIMEOUT_INTERRUPT)) {
duet_uart_interrupt_config(UARTx, UART_RX_INTERRUPT | UART_RX_TIMEOUT_INTERRUPT, DISABLE);
duet_uart_clear_interrupt(UARTx, UART_RX_INTERRUPT | UART_RX_TIMEOUT_INTERRUPT);
asr582x/liteos_m/sdk/drivers/iperf/lwip_iperf.c
+1 -1
View File
@@ -229,7 +229,7 @@ void lega_wifi_iperf_client_start()
if (lega_rtos_init_timer(&iperf_output_timer, IPERF_OUTPUT_INTERVIEW * 1000, iperf_output, NULL) != kNoErr) {
iperf_printf("iperf timer fail!\r\n");
}
for ( ;; ) {
for (;;) {
if (lega_rtos_get_semaphore(&iperf_Semaphore, IPERF_CLIENT_TIMEOUT_MS) == kNoErr) {
// AT command set lwip_iperf_config over and begin to run
asr582x/liteos_m/sdk/drivers/platform/CMSIS/Include/core_cm4.h
+82 -82
View File
@@ -22,7 +22,7 @@
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#if defined (__ICCARM__)
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
@@ -65,14 +65,14 @@ extern "C" {
#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /* !< \deprecated [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /* !< \deprecated [15:0] CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
__CM4_CMSIS_VERSION_SUB ) /* !< \deprecated CMSIS HAL version number */
__CM4_CMSIS_VERSION_SUB ) /* !< \deprecated CMSIS HAL version number */
#define __CORTEX_M (4U) /* !< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined ( __CC_ARM )
#if defined (__CC_ARM)
#if defined __TARGET_FPU_VFP
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
@@ -96,7 +96,7 @@ extern "C" {
#define __FPU_USED 0U
#endif
#elif defined ( __GNUC__ )
#elif defined (__GNUC__)
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
@@ -108,7 +108,7 @@ extern "C" {
#define __FPU_USED 0U
#endif
#elif defined ( __ICCARM__ )
#elif defined (__ICCARM__)
#if defined __ARMVFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
@@ -120,7 +120,7 @@ extern "C" {
#define __FPU_USED 0U
#endif
#elif defined ( __TI_ARM__ )
#elif defined (__TI_ARM__)
#if defined __TI_VFP_SUPPORT__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
@@ -132,7 +132,7 @@ extern "C" {
#define __FPU_USED 0U
#endif
#elif defined ( __TASKING__ )
#elif defined (__TASKING__)
#if defined __FPU_VFP__
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
@@ -144,8 +144,8 @@ extern "C" {
#define __FPU_USED 0U
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#elif defined (__CSMC__)
#if (__CSMC__ & 0x400U)
#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
#define __FPU_USED 1U
#else
@@ -415,7 +415,7 @@ typedef struct {
uint32_t RESERVED4[56U];
__IOM uint8_t IP[240U]; /* !< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644U];
__OM uint32_t STIR; /* !< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
__OM uint32_t STIR; /* !< Offset: 0xE00 (/W) Software Trigger Interrupt Register */
} NVIC_Type;
/* Software Triggered Interrupt Register Definitions */
@@ -435,7 +435,7 @@ typedef struct {
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct {
__IM uint32_t CPUID; /* !< Offset: 0x000 (R/ ) CPUID Base Register */
__IM uint32_t CPUID; /* !< Offset: 0x000 (R/) CPUID Base Register */
__IOM uint32_t ICSR; /* !< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /* !< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /* !< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
@@ -450,35 +450,35 @@ typedef struct {
__IOM uint32_t MMFAR; /* !< Offset: 0x034 (R/W) MemManage Fault Address Register */
__IOM uint32_t BFAR; /* !< Offset: 0x038 (R/W) BusFault Address Register */
__IOM uint32_t AFSR; /* !< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__IM uint32_t PFR[2U]; /* !< Offset: 0x040 (R/ ) Processor Feature Register */
__IM uint32_t DFR; /* !< Offset: 0x048 (R/ ) Debug Feature Register */
__IM uint32_t ADR; /* !< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__IM uint32_t MMFR[4U]; /* !< Offset: 0x050 (R/ ) Memory Model Feature Register */
__IM uint32_t ISAR[5U]; /* !< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
__IM uint32_t PFR[2U]; /* !< Offset: 0x040 (R/) Processor Feature Register */
__IM uint32_t DFR; /* !< Offset: 0x048 (R/) Debug Feature Register */
__IM uint32_t ADR; /* !< Offset: 0x04C (R/) Auxiliary Feature Register */
__IM uint32_t MMFR[4U]; /* !< Offset: 0x050 (R/) Memory Model Feature Register */
__IM uint32_t ISAR[5U]; /* !< Offset: 0x060 (R/) Instruction Set Attributes Register */
uint32_t RESERVED0[1U];
__IM uint32_t CLIDR; /* !< Offset: 0x078 (R/ ) Cache Level ID register */
__IM uint32_t CTR; /* !< Offset: 0x07C (R/ ) Cache Type register */
__IM uint32_t CCSIDR; /* !< Offset: 0x080 (R/ ) Cache Size ID Register */
__IM uint32_t CLIDR; /* !< Offset: 0x078 (R/) Cache Level ID register */
__IM uint32_t CTR; /* !< Offset: 0x07C (R/) Cache Type register */
__IM uint32_t CCSIDR; /* !< Offset: 0x080 (R/) Cache Size ID Register */
__IOM uint32_t CSSELR; /* !< Offset: 0x084 (R/W) Cache Size Selection Register */
__IOM uint32_t
CPACR; /* !< Offset: 0x088 (R/W) Coprocessor Access Control Register */
uint32_t RESERVED3[93U];
__OM uint32_t STIR; /* !< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
__OM uint32_t STIR; /* !< Offset: 0x200 (/W) Software Triggered Interrupt Register */
uint32_t RESERVED4[15U];
__IM uint32_t MVFR0; /* !< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /* !< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /* !< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
__IM uint32_t MVFR0; /* !< Offset: 0x240 (R/) Media and VFP Feature Register 0 */
__IM uint32_t MVFR1; /* !< Offset: 0x244 (R/) Media and VFP Feature Register 1 */
__IM uint32_t MVFR2; /* !< Offset: 0x248 (R/) Media and VFP Feature Register 1 */
uint32_t RESERVED5[1U];
__OM uint32_t ICIALLU; /* !< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
__OM uint32_t ICIALLU; /* !< Offset: 0x250 (/W) I-Cache Invalidate All to PoU */
uint32_t RESERVED6[1U];
__OM uint32_t ICIMVAU; /* !< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
__OM uint32_t DCIMVAC; /* !< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
__OM uint32_t DCISW; /* !< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
__OM uint32_t DCCMVAU; /* !< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
__OM uint32_t DCCMVAC; /* !< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
__OM uint32_t DCCSW; /* !< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /* !< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /* !< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
__OM uint32_t ICIMVAU; /* !< Offset: 0x258 (/W) I-Cache Invalidate by MVA to PoU */
__OM uint32_t DCIMVAC; /* !< Offset: 0x25C (/W) D-Cache Invalidate by MVA to PoC */
__OM uint32_t DCISW; /* !< Offset: 0x260 (/W) D-Cache Invalidate by Set-way */
__OM uint32_t DCCMVAU; /* !< Offset: 0x264 (/W) D-Cache Clean by MVA to PoU */
__OM uint32_t DCCMVAC; /* !< Offset: 0x268 (/W) D-Cache Clean by MVA to PoC */
__OM uint32_t DCCSW; /* !< Offset: 0x26C (/W) D-Cache Clean by Set-way */
__OM uint32_t DCCIMVAC; /* !< Offset: 0x270 (/W) D-Cache Clean and Invalidate by MVA to PoC */
__OM uint32_t DCCISW; /* !< Offset: 0x274 (/W) D-Cache Clean and Invalidate by Set-way */
uint32_t RESERVED7[6U];
__IOM uint32_t ITCMCR; /* !< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
__IOM uint32_t DTCMCR; /* !< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
@@ -901,7 +901,7 @@ typedef struct {
*/
typedef struct {
uint32_t RESERVED0[1U];
__IM uint32_t ICTR; /* !< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
__IM uint32_t ICTR; /* !< Offset: 0x004 (R/) Interrupt Controller Type Register */
__IOM uint32_t ACTLR; /* !< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
@@ -941,7 +941,7 @@ typedef struct {
__IOM uint32_t CTRL; /* !< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /* !< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /* !< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /* !< Offset: 0x00C (R/ ) SysTick Calibration Register */
__IM uint32_t CALIB; /* !< Offset: 0x00C (R/) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
@@ -989,10 +989,10 @@ typedef struct {
*/
typedef struct {
__OM union {
__OM uint8_t u8; /* !< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /* !< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /* !< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32U]; /* !< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
__OM uint8_t u8; /* !< Offset: 0x000 (/W) ITM Stimulus Port 8-bit */
__OM uint16_t u16; /* !< Offset: 0x000 (/W) ITM Stimulus Port 16-bit */
__OM uint32_t u32; /* !< Offset: 0x000 (/W) ITM Stimulus Port 32-bit */
} PORT [32U]; /* !< Offset: 0x000 (/W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864U];
__IOM uint32_t TER; /* !< Offset: 0xE00 (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15U];
@@ -1001,21 +1001,21 @@ typedef struct {
__IOM uint32_t TCR; /* !< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t RESERVED3[32U];
uint32_t RESERVED4[43U];
__OM uint32_t LAR; /* !< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__IM uint32_t LSR; /* !< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
__OM uint32_t LAR; /* !< Offset: 0xFB0 (/W) ITM Lock Access Register */
__IM uint32_t LSR; /* !< Offset: 0xFB4 (R/) ITM Lock Status Register */
uint32_t RESERVED5[6U];
__IM uint32_t PID4; /* !< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /* !< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /* !< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /* !< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /* !< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /* !< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /* !< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /* !< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /* !< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
__IM uint32_t CID1; /* !< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
__IM uint32_t CID2; /* !< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
__IM uint32_t CID3; /* !< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
__IM uint32_t PID4; /* !< Offset: 0xFD0 (R/) ITM Peripheral Identification Register #4 */
__IM uint32_t PID5; /* !< Offset: 0xFD4 (R/) ITM Peripheral Identification Register #5 */
__IM uint32_t PID6; /* !< Offset: 0xFD8 (R/) ITM Peripheral Identification Register #6 */
__IM uint32_t PID7; /* !< Offset: 0xFDC (R/) ITM Peripheral Identification Register #7 */
__IM uint32_t PID0; /* !< Offset: 0xFE0 (R/) ITM Peripheral Identification Register #0 */
__IM uint32_t PID1; /* !< Offset: 0xFE4 (R/) ITM Peripheral Identification Register #1 */
__IM uint32_t PID2; /* !< Offset: 0xFE8 (R/) ITM Peripheral Identification Register #2 */
__IM uint32_t PID3; /* !< Offset: 0xFEC (R/) ITM Peripheral Identification Register #3 */
__IM uint32_t CID0; /* !< Offset: 0xFF0 (R/) ITM Component Identification Register #0 */
__IM uint32_t CID1; /* !< Offset: 0xFF4 (R/) ITM Component Identification Register #1 */
__IM uint32_t CID2; /* !< Offset: 0xFF8 (R/) ITM Component Identification Register #2 */
__IM uint32_t CID3; /* !< Offset: 0xFFC (R/) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
@@ -1080,7 +1080,7 @@ typedef struct {
__IOM uint32_t SLEEPCNT; /* !< Offset: 0x010 (R/W) Sleep Count Register */
__IOM uint32_t LSUCNT; /* !< Offset: 0x014 (R/W) LSU Count Register */
__IOM uint32_t FOLDCNT; /* !< Offset: 0x018 (R/W) Folded-instruction Count Register */
__IM uint32_t PCSR; /* !< Offset: 0x01C (R/ ) Program Counter Sample Register */
__IM uint32_t PCSR; /* !< Offset: 0x01C (R/) Program Counter Sample Register */
__IOM uint32_t COMP0; /* !< Offset: 0x020 (R/W) Comparator Register 0 */
__IOM uint32_t MASK0; /* !< Offset: 0x024 (R/W) Mask Register 0 */
__IOM uint32_t FUNCTION0; /* !< Offset: 0x028 (R/W) Function Register 0 */
@@ -1218,30 +1218,30 @@ typedef struct {
\brief Structure type to access the Trace Port Interface Register (TPI).
*/
typedef struct {
__IM uint32_t SSPSR; /* !< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
__IM uint32_t SSPSR; /* !< Offset: 0x000 (R/) Supported Parallel Port Size Register */
__IOM uint32_t CSPSR; /* !< Offset: 0x004 (R/W) Current Parallel Port Size Register */
uint32_t RESERVED0[2U];
__IOM uint32_t ACPR; /* !< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
uint32_t RESERVED1[55U];
__IOM uint32_t SPPR; /* !< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
uint32_t RESERVED2[131U];
__IM uint32_t FFSR; /* !< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
__IM uint32_t FFSR; /* !< Offset: 0x300 (R/) Formatter and Flush Status Register */
__IOM uint32_t FFCR; /* !< Offset: 0x304 (R/W) Formatter and Flush Control Register */
__IM uint32_t FSCR; /* !< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
__IM uint32_t FSCR; /* !< Offset: 0x308 (R/) Formatter Synchronization Counter Register */
uint32_t RESERVED3[759U];
__IM uint32_t TRIGGER; /* !< Offset: 0xEE8 (R/ ) TRIGGER Register */
__IM uint32_t FIFO0; /* !< Offset: 0xEEC (R/ ) Integration ETM Data */
__IM uint32_t ITATBCTR2; /* !< Offset: 0xEF0 (R/ ) ITATBCTR2 */
__IM uint32_t TRIGGER; /* !< Offset: 0xEE8 (R/) TRIGGER Register */
__IM uint32_t FIFO0; /* !< Offset: 0xEEC (R/) Integration ETM Data */
__IM uint32_t ITATBCTR2; /* !< Offset: 0xEF0 (R/) ITATBCTR2 */
uint32_t RESERVED4[1U];
__IM uint32_t ITATBCTR0; /* !< Offset: 0xEF8 (R/ ) ITATBCTR0 */
__IM uint32_t FIFO1; /* !< Offset: 0xEFC (R/ ) Integration ITM Data */
__IM uint32_t ITATBCTR0; /* !< Offset: 0xEF8 (R/) ITATBCTR0 */
__IM uint32_t FIFO1; /* !< Offset: 0xEFC (R/) Integration ITM Data */
__IOM uint32_t ITCTRL; /* !< Offset: 0xF00 (R/W) Integration Mode Control */
uint32_t RESERVED5[39U];
__IOM uint32_t CLAIMSET; /* !< Offset: 0xFA0 (R/W) Claim tag set */
__IOM uint32_t CLAIMCLR; /* !< Offset: 0xFA4 (R/W) Claim tag clear */
uint32_t RESERVED7[8U];
__IM uint32_t DEVID; /* !< Offset: 0xFC8 (R/ ) TPIU_DEVID */
__IM uint32_t DEVTYPE; /* !< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
__IM uint32_t DEVID; /* !< Offset: 0xFC8 (R/) TPIU_DEVID */
__IM uint32_t DEVTYPE; /* !< Offset: 0xFCC (R/) TPIU_DEVTYPE */
} TPI_Type;
/* TPI Asynchronous Clock Prescaler Register Definitions */
@@ -1378,7 +1378,7 @@ typedef struct {
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct {
__IM uint32_t TYPE; /* !< Offset: 0x000 (R/ ) MPU Type Register */
__IM uint32_t TYPE; /* !< Offset: 0x000 (R/) MPU Type Register */
__IOM uint32_t CTRL; /* !< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /* !< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /* !< Offset: 0x00C (R/W) MPU Region Base Address Register */
@@ -1476,9 +1476,9 @@ typedef struct {
__IOM uint32_t FPCCR; /* !< Offset: 0x004 (R/W) Floating-Point Context Control Register */
__IOM uint32_t FPCAR; /* !< Offset: 0x008 (R/W) Floating-Point Context Address Register */
__IOM uint32_t FPDSCR; /* !< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
__IM uint32_t MVFR0; /* !< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
__IM uint32_t MVFR1; /* !< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
__IM uint32_t MVFR2; /* !< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
__IM uint32_t MVFR0; /* !< Offset: 0x010 (R/) Media and FP Feature Register 0 */
__IM uint32_t MVFR1; /* !< Offset: 0x014 (R/) Media and FP Feature Register 1 */
__IM uint32_t MVFR2; /* !< Offset: 0x018 (R/) Media and FP Feature Register 2 */
} FPU_Type;
/* Floating-Point Context Control Register Definitions */
@@ -1583,7 +1583,7 @@ typedef struct {
*/
typedef struct {
__IOM uint32_t DHCSR; /* !< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__OM uint32_t DCRSR; /* !< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__OM uint32_t DCRSR; /* !< Offset: 0x004 (/W) Debug Core Register Selector Register */
__IOM uint32_t DCRDR; /* !< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IOM uint32_t DEMCR; /* !< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
@@ -1716,22 +1716,22 @@ typedef struct {
#define NVIC_BASE (SCS_BASE + 0x0100UL) /* !< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /* !< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /* !< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /* !< SCB configuration struct */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /* !< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /* !< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /* !< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /* !< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /* !< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /* !< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /* !< TPI configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /* !< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE ) /* !< ITM configuration struct */
#define DWT ((DWT_Type *) DWT_BASE ) /* !< DWT configuration struct */
#define TPI ((TPI_Type *) TPI_BASE ) /* !< TPI configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /* !< Core Debug configuration struct */
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /* !< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /* !< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /* !< Memory Protection Unit */
#endif
#define FPU_BASE (SCS_BASE + 0x0F30UL) /* !< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /* !< Floating Point Unit */
#define FPU ((FPU_Type *) FPU_BASE ) /* !< Floating Point Unit */
/* @} */
@@ -1813,7 +1813,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)); /* Insert write key and priority group */
SCB->AIRCR = reg_value;
}
@@ -1998,8 +1998,8 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
@@ -2026,7 +2026,7 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
@@ -2069,7 +2069,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for (;;) { /* wait until reset */
@@ -2179,7 +2179,7 @@ extern volatile int32_t ITM_RxBuffer; /* !< Externa
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
((ITM->TER & 1UL ) != 0UL) ) { /* ITM Port #0 enabled */
while (ITM->PORT[0U].u32 == 0UL) {
__NOP();
}
asr582x/liteos_m/sdk/drivers/platform/system/duet_common.c
+1 -1
View File
@@ -72,7 +72,7 @@ void udelay_pl(unsigned int us)
#ifdef CFG_DUET_FREERTOS
void lega_enter_critical_expble(void)
{
portCLEAR_INTERRUPT_MASK_FROM_ISR( (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1) << (8 - configPRIO_BITS) );
portCLEAR_INTERRUPT_MASK_FROM_ISR((configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY + 1) << (8 - configPRIO_BITS));
}
void lega_exit_critical_expble(void)
asr582x/liteos_m/sdk/drivers/platform/system/include/panic_mpu.h
+1 -1
View File
@@ -18,7 +18,7 @@
#ifdef STAR_MPU_ENABLE
typedef struct {
unsigned int type; /* !< Offset: 0x000 (R/ ) MPU Type Register */
unsigned int type; /* !< Offset: 0x000 (R/) MPU Type Register */
unsigned int ctrl; /* !< Offset: 0x004 (R/W) MPU Control Register */
unsigned int rnr; /* !< Offset: 0x008 (R/W) MPU Region RNRber Register */
unsigned int rbar; /* !< Offset: 0x00C (R/W) MPU Region Base Address Register */
asr582x/liteos_m/sdk/drivers/platform/system/include/pmu.h
+4 -4
View File
@@ -31,11 +31,11 @@ typedef enum pmu_state {
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static inline void __WFI__(void)
__attribute__((always_inline)) static inline void __WFI__(void)
{
__asm volatile( "dsb" );
__asm volatile( "wfi" );
__asm volatile( "isb" );
__asm volatile("dsb");
__asm volatile("wfi");
__asm volatile("isb");
}
/** @brief get current RTC counter, only used when RTC enabled.
asr582x/liteos_m/sdk/hal/inc/flash.h
+8 -8
View File
@@ -22,16 +22,16 @@
extern "C" {
#endif
#define PAR_OPT_READ_POS ( 0 )
#define PAR_OPT_WRITE_POS ( 1 )
#define PAR_OPT_READ_POS (0)
#define PAR_OPT_WRITE_POS (1)
#define PAR_OPT_READ_MASK ( 0x1u << PAR_OPT_READ_POS )
#define PAR_OPT_WRITE_MASK ( 0x1u << PAR_OPT_WRITE_POS )
#define PAR_OPT_READ_MASK (0x1u << PAR_OPT_READ_POS)
#define PAR_OPT_WRITE_MASK (0x1u << PAR_OPT_WRITE_POS)
#define PAR_OPT_READ_DIS ( 0x0u << PAR_OPT_READ_POS )
#define PAR_OPT_READ_EN ( 0x1u << PAR_OPT_READ_POS )
#define PAR_OPT_WRITE_DIS ( 0x0u << PAR_OPT_WRITE_POS )
#define PAR_OPT_WRITE_EN ( 0x1u << PAR_OPT_WRITE_POS )
#define PAR_OPT_READ_DIS (0x0u << PAR_OPT_READ_POS)
#define PAR_OPT_READ_EN (0x1u << PAR_OPT_READ_POS)
#define PAR_OPT_WRITE_DIS (0x0u << PAR_OPT_WRITE_POS)
#define PAR_OPT_WRITE_EN (0x1u << PAR_OPT_WRITE_POS)
typedef enum {
HAL_PARTITION_ERROR = -1,
asr582x/liteos_m/sdk/rtos/lega_rtos.h
+35 -35
View File
@@ -85,7 +85,7 @@ typedef void *lega_semaphore_t;
typedef void *lega_mutex_t;
typedef void *lega_thread_t;
typedef void *lega_queue_t;
typedef void (*timer_handler_t)( void *arg );
typedef void (*timer_handler_t)(void *arg);
typedef struct {
void *handle;
@@ -106,7 +106,7 @@ typedef struct {
} lega_threadinfo_t;
typedef uint32_t lega_thread_arg_t;
typedef void (*lega_thread_function_t)( lega_thread_arg_t arg );
typedef void (*lega_thread_function_t)(lega_thread_arg_t arg);
/** @defgroup LEGA_RTOS_Thread LEGA RTOS Thread Management Functions
* @brief Provide thread creation, delete, suspend, resume, and other RTOS management API
@@ -139,7 +139,7 @@ OSBool lega_rtos_is_in_interrupt_context(void);
*
* @return none
*/
lega_cpsr_t _lega_rtos_enter_critical( void );
lega_cpsr_t _lega_rtos_enter_critical(void);
#define lega_rtos_enter_critical() \
do { \
critical_cpsr = _lega_rtos_enter_critical(); \
@@ -148,7 +148,7 @@ lega_cpsr_t _lega_rtos_enter_critical( void );
*
* @return none
*/
void _lega_rtos_exit_critical( lega_cpsr_t cpsr_store);
void _lega_rtos_exit_critical(lega_cpsr_t cpsr_store);
#define lega_rtos_exit_critical() \
do { \
_lega_rtos_exit_critical(critical_cpsr); \
@@ -169,8 +169,8 @@ void _lega_rtos_exit_critical( lega_cpsr_t cpsr_store);
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_create_thread( lega_thread_t *thread, uint8_t priority, const char *name,
lega_thread_function_t function, uint32_t stack_size, lega_thread_arg_t arg );
OSStatus lega_rtos_create_thread(lega_thread_t *thread, uint8_t priority, const char *name,
lega_thread_function_t function, uint32_t stack_size, lega_thread_arg_t arg);
/** @brief Deletes a terminated thread
*
@@ -179,7 +179,7 @@ OSStatus lega_rtos_create_thread( lega_thread_t *thread, uint8_t priority, const
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_delete_thread( lega_thread_t *thread );
OSStatus lega_rtos_delete_thread(lega_thread_t *thread);
/** @defgroup LEGA_RTOS_SEM LEGA RTOS Semaphore Functions
* @brief Provide management APIs for semaphore such as init,set,get and dinit.
@@ -194,7 +194,7 @@ OSStatus lega_rtos_delete_thread( lega_thread_t *thread );
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_init_semaphore( lega_semaphore_t *semaphore, int count );
OSStatus lega_rtos_init_semaphore(lega_semaphore_t *semaphore, int count);
/** @brief Set (post/put/increment) a semaphore
*
@@ -203,7 +203,7 @@ OSStatus lega_rtos_init_semaphore( lega_semaphore_t *semaphore, int count );
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_set_semaphore( lega_semaphore_t *semaphore );
OSStatus lega_rtos_set_semaphore(lega_semaphore_t *semaphore);
/** @brief Get (wait/decrement) a semaphore
*
@@ -217,7 +217,7 @@ OSStatus lega_rtos_set_semaphore( lega_semaphore_t *semaphore );
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_get_semaphore( lega_semaphore_t *semaphore, uint32_t timeout_ms );
OSStatus lega_rtos_get_semaphore(lega_semaphore_t *semaphore, uint32_t timeout_ms);
/** @brief De-initialise a semaphore
*
@@ -228,7 +228,7 @@ OSStatus lega_rtos_get_semaphore( lega_semaphore_t *semaphore, uint32_t timeout_
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_deinit_semaphore( lega_semaphore_t *semaphore );
OSStatus lega_rtos_deinit_semaphore(lega_semaphore_t *semaphore);
/** @brief if the task num pending by this semaphore is 0
*
@@ -239,7 +239,7 @@ OSStatus lega_rtos_deinit_semaphore( lega_semaphore_t *semaphore );
* @return TRUE : pending task num is 0
* @return FALSE : pending task num is not 0
*/
OSBool lega_rtos_semaphore_pending_task_null( lega_semaphore_t *semaphore );
OSBool lega_rtos_semaphore_pending_task_null(lega_semaphore_t *semaphore);
/**
* @}
@@ -261,7 +261,7 @@ OSBool lega_rtos_semaphore_pending_task_null( lega_semaphore_t *semaphore );
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_init_mutex( lega_mutex_t *mutex );
OSStatus lega_rtos_init_mutex(lega_mutex_t *mutex);
/** @brief Obtains the lock on a mutex
*
@@ -274,7 +274,7 @@ OSStatus lega_rtos_init_mutex( lega_mutex_t *mutex );
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_lock_mutex( lega_mutex_t *mutex, uint32_t timeout_ms );
OSStatus lega_rtos_lock_mutex(lega_mutex_t *mutex, uint32_t timeout_ms);
/** @brief Releases the lock on a mutex
*
@@ -286,7 +286,7 @@ OSStatus lega_rtos_lock_mutex( lega_mutex_t *mutex, uint32_t timeout_ms );
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_unlock_mutex( lega_mutex_t *mutex );
OSStatus lega_rtos_unlock_mutex(lega_mutex_t *mutex);
/** @brief De-initialise a mutex
*
@@ -297,7 +297,7 @@ OSStatus lega_rtos_unlock_mutex( lega_mutex_t *mutex );
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_deinit_mutex( lega_mutex_t *mutex );
OSStatus lega_rtos_deinit_mutex(lega_mutex_t *mutex);
/**
* @}
*/
@@ -317,8 +317,8 @@ OSStatus lega_rtos_deinit_mutex( lega_mutex_t *mutex );
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_init_queue( lega_queue_t *queue, const char *name, uint32_t message_size,
uint32_t number_of_messages );
OSStatus lega_rtos_init_queue(lega_queue_t *queue, const char *name, uint32_t message_size,
uint32_t number_of_messages);
/** @brief Pushes an object onto a queue
*
@@ -330,7 +330,7 @@ OSStatus lega_rtos_init_queue( lega_queue_t *queue, const char *name, uint32_t m
* @return kNoErr : on success.
* @return kGeneralErr : if an error or timeout occurred
*/
OSStatus lega_rtos_push_to_queue( lega_queue_t *queue, void *message, uint32_t timeout_ms );
OSStatus lega_rtos_push_to_queue(lega_queue_t *queue, void *message, uint32_t timeout_ms);
/** @brief Pops an object off a queue
*
@@ -345,7 +345,7 @@ OSStatus lega_rtos_push_to_queue( lega_queue_t *queue, void *message, uint32_t t
* @return kNoErr : on success.
* @return kGeneralErr : if an error or timeout occurred
*/
OSStatus lega_rtos_pop_from_queue( lega_queue_t *queue, void *message, uint32_t timeout_ms );
OSStatus lega_rtos_pop_from_queue(lega_queue_t *queue, void *message, uint32_t timeout_ms);
/** @brief De-initialise a queue created with @ref lega_rtos_init_queue
*
@@ -354,7 +354,7 @@ OSStatus lega_rtos_pop_from_queue( lega_queue_t *queue, void *message, uint32_t
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_deinit_queue( lega_queue_t *queue );
OSStatus lega_rtos_deinit_queue(lega_queue_t *queue);
/** @brief Check if a queue is empty
*
@@ -363,7 +363,7 @@ OSStatus lega_rtos_deinit_queue( lega_queue_t *queue );
* @return true : queue is empty.
* @return false : queue is not empty.
*/
OSBool lega_rtos_is_queue_empty( lega_queue_t *queue );
OSBool lega_rtos_is_queue_empty(lega_queue_t *queue);
/** @brief Check if a queue is full
*
@@ -372,7 +372,7 @@ OSBool lega_rtos_is_queue_empty( lega_queue_t *queue );
* @return true : queue is empty.
* @return false : queue is not empty.
*/
OSBool lega_rtos_is_queue_full( lega_queue_t *queue );
OSBool lega_rtos_is_queue_full(lega_queue_t *queue);
/**
* @}
@@ -399,11 +399,11 @@ OSBool lega_rtos_is_queue_full( lega_queue_t *queue );
* @return kGeneralErr : if an error occurred
*/
#ifdef USE_TIMER_NAME
OSStatus lega_rtos_init_timer_name( lega_timer_t *timer, uint32_t time_ms, timer_handler_t function, void *arg,
uint8_t *name);
OSStatus lega_rtos_init_timer_name(lega_timer_t *timer, uint32_t time_ms, timer_handler_t function, void *arg,
uint8_t *name);
#define lega_rtos_init_timer(timer,time_ms,function,arg) lega_rtos_init_timer_name(timer,time_ms,function,arg,__FUNCTION__)
#else
OSStatus lega_rtos_init_timer( lega_timer_t *timer, uint32_t time_ms, timer_handler_t function, void *arg);
OSStatus lega_rtos_init_timer(lega_timer_t *timer, uint32_t time_ms, timer_handler_t function, void *arg);
#endif
/** @brief Starts a RTOS timer running
@@ -415,7 +415,7 @@ OSStatus lega_rtos_init_timer( lega_timer_t *timer, uint32_t time_ms, timer_hand
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_start_timer( lega_timer_t *timer );
OSStatus lega_rtos_start_timer(lega_timer_t *timer);
/** @brief Stops a running RTOS timer
*
@@ -426,7 +426,7 @@ OSStatus lega_rtos_start_timer( lega_timer_t *timer );
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_stop_timer( lega_timer_t *timer );
OSStatus lega_rtos_stop_timer(lega_timer_t *timer);
/** @brief Reloads a RTOS timer that has expired
*
@@ -438,7 +438,7 @@ OSStatus lega_rtos_stop_timer( lega_timer_t *timer );
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_reload_timer( lega_timer_t *timer );
OSStatus lega_rtos_reload_timer(lega_timer_t *timer);
/** @brief De-initialise a RTOS timer
*
@@ -449,7 +449,7 @@ OSStatus lega_rtos_reload_timer( lega_timer_t *timer );
* @return kNoErr : on success.
* @return kGeneralErr : if an error occurred
*/
OSStatus lega_rtos_deinit_timer( lega_timer_t *timer );
OSStatus lega_rtos_deinit_timer(lega_timer_t *timer);
/** @brief Check if an RTOS timer is running
*
@@ -458,7 +458,7 @@ OSStatus lega_rtos_deinit_timer( lega_timer_t *timer );
* @return true : if running.
* @return false : if not running
*/
OSBool lega_rtos_is_timer_running( lega_timer_t *timer );
OSBool lega_rtos_is_timer_running(lega_timer_t *timer);
/**
* @brief Gets time in miiliseconds since RTOS start
@@ -479,10 +479,10 @@ uint32_t lega_rtos_get_time(void);
*
* @return kNoErr.
*/
OSStatus lega_rtos_delay_milliseconds( uint32_t num_ms );
OSStatus lega_rtos_delay_milliseconds(uint32_t num_ms);
#endif
#define lega_rtos_malloc(s) _lega_rtos_malloc(s,__FUNCTION__,__LINE__)
#define lega_rtos_malloc(s) _lega_rtos_malloc(s, __FUNCTION__, __LINE__)
void *_lega_rtos_malloc(uint32_t xWantedSize, const char *function, uint32_t line);
void lega_rtos_free(void *mem);
@@ -494,8 +494,8 @@ const char *lega_rtos_get_system_version(void);
void lega_intrpt_enter(void);
void lega_intrpt_exit(void);
uint32_t lega_rtos_get_system_ticks(void);
uint32_t lega_rtos_int_disable( void );
void lega_rtos_int_enable( uint32_t int_mask );
uint32_t lega_rtos_int_disable(void);
void lega_rtos_int_enable(uint32_t int_mask);
void lega_rtos_systick_reconfig(void);
int lega_rtos_running(void);
OSStatus lega_rtos_get_threadinfo(lega_thread_t *thread, lega_threadinfo_t *info);
asr582x/liteos_m/sdk/startup/board.c
+1 -1
View File
@@ -240,7 +240,7 @@ int board_after_init(void)
lega_log_disable();
#endif
#ifdef WIFI_BLE_INIT_ENABLE
tcpip_init( NULL, NULL );
tcpip_init(NULL, NULL);
lega_wlan_init();
#endif
#if 0