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!11 add stm32mp157 soc

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Merge pull request !11 from Laowang-BearPi/master
This commit is contained in:
openharmony_sig_ci
2022-03-07 09:50:20 +00:00
committed by Gitee
parent 5df4b5935f 9aaae45136
commit 4d48db66eb
89 changed files with 62721 additions and 1285 deletions
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README_zh.md
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# ST（STMicroelectronics）
# device_soc_st
- [简介]()
- [目录]()
- [约束]()
- [简介](#section469617221261)
- [目录](#section469617221262)
- [约束](#section469617221263)
- [使用说明]()
- [相关仓]()
## 简介<a name=""></a>
## 简介<a name="section469617221261"></a>
该仓库为意法半导体单板相关代码。
该仓库为STM32（意法半导体）芯片相关代码仓库。
## 目录<a name=""></a>
## 目录<a name="section469617221262"></a>
```
device/soc/st
├── common # 公共驱动
│ └── hal # hal适配目录
│ └── platform # 平台驱动适配
├── stm32mp157 # 芯片SOC名称
```
## 约束<a name=""></a>
支持STM32MP157芯片。
## 使用说明<a name=""></a>
参考各开发板readme。
## 相关仓<a name=""></a>
**device\_st**
**device\_soc\_st**
common/hal/display/BUILD.gn
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# Copyright (c) 2021 Huawei Device Co., Ltd.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import("//build/lite/config/component/lite_component.gni")
shared_library("display_layer") {
output_name = "display_layer"
sources = [
"//drivers/peripheral/display/hal/disp_hal.c",
"display_layer.c",
]
include_dirs = [
"//drivers/peripheral/base",
"//drivers/peripheral/display/hal",
"//drivers/peripheral/display/interfaces/include",
"//drivers/adapter/uhdf/posix/include",
"//drivers/framework/include/utils",
"//drivers/framework/ability/sbuf/include",
"//drivers/framework/utils/include",
"//drivers/framework/include/core",
"//base/hiviewdfx/hilog_lite/interfaces/native/innerkits",
]
deps = [
"//drivers/adapter/uhdf/manager:hdf_core",
"//drivers/adapter/uhdf/posix:hdf_posix_osal",
"//third_party/bounds_checking_function:libsec_shared",
]
defines = [ "__USER__" ]
cflags = [
"-Wall",
"-Wextra",
"-Werror",
"-fsigned-char",
"-fno-common",
"-fno-strict-aliasing",
"-Wno-format",
"-Wno-format-extra-args",
]
}
shared_library("display_gralloc") {
output_name = "display_gralloc"
sources = [ "display_gralloc.c" ]
include_dirs = [
"//drivers/peripheral/base",
"//drivers/peripheral/display/hal",
"//drivers/drivers/peripheral/display/hal",
"//drivers/peripheral/display/interfaces/include",
"//drivers/framework/include/utils",
"//base/hiviewdfx/hilog_lite/interfaces/native/innerkits",
"//drivers/adapter/uhdf/posix/include",
]
deps = [
"//drivers/adapter/uhdf/posix:hdf_posix_osal",
"//third_party/bounds_checking_function:libsec_shared",
]
cflags = [
"-Wall",
"-Wextra",
"-Werror",
"-fsigned-char",
"-fno-common",
"-fno-strict-aliasing",
"-Wno-format",
"-Wno-format-extra-args",
]
}
shared_library("display_gfx") {
output_name = "display_gfx"
sources = [ "display_gfx.c" ]
include_dirs = [
"//drivers/peripheral/base",
"//drivers/peripheral/display/hal",
"//drivers/peripheral/display/interfaces/include",
"//drivers/framework/include/utils",
"//base/hiviewdfx/hilog_lite/interfaces/native/innerkits",
"//drivers/adapter/uhdf/posix/include",
]
deps = [
"//drivers/adapter/uhdf/posix:hdf_posix_osal",
"//third_party/bounds_checking_function:libsec_shared",
]
cflags = [
"-Wall",
"-Wextra",
"-Werror",
"-fsigned-char",
"-fno-common",
"-fno-strict-aliasing",
"-Wno-format",
"-Wno-format-extra-args",
]
}
lite_component("hdi_display") {
features = [
":display_layer",
":display_gralloc",
":display_gfx",
]
}
common/hal/display/display_gfx.c
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/*
* Copyright (c) 2021 Huawei Device Co., Ltd.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "display_gfx.h"
#include <stdio.h>
#include "hdf_log.h"
#include "display_type.h"
int32_t GfxInitialize(GfxFuncs **funcs)
{
if (funcs == NULL) {
HDF_LOGE("%s: funcs is null", __func__);
return DISPLAY_NULL_PTR;
}
*funcs = NULL;
HDF_LOGI("%s: gfx initialize success", __func__);
return DISPLAY_SUCCESS;
}
int32_t GfxUninitialize(GfxFuncs *funcs)
{
if (funcs == NULL) {
HDF_LOGE("%s: funcs is null", __func__);
return DISPLAY_NULL_PTR;
}
free(funcs);
HDF_LOGI("%s: gfx uninitialize success", __func__);
return DISPLAY_SUCCESS;
}
common/hal/display/display_gralloc.c
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/*
* Copyright (c) 2021 Huawei Device Co., Ltd.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "display_gralloc.h"
#include <errno.h>
#include <inttypes.h>
#include <stdio.h>
#include <sys/mman.h>
#include <sys/shm.h>
#include <securec.h>
#include "buffer_handle.h"
#include "display_type.h"
#include "disp_common.h"
#include "hdf_log.h"
#define DEFAULT_READ_WRITE_PERMISSIONS 0666
#define MAX_MALLOC_SIZE 0x10000000L
#define SHM_MAX_KEY 10000
#define SHM_START_KEY 1
#define INVALID_SHMID -1
#define BITS_PER_BYTE 8
#define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d))
#define ALIGN_UP(x, a) ((((x) + ((a)-1)) / (a)) * (a))
#define HEIGHT_ALIGN 2U
#define WIDTH_ALIGN 8U
#define MAX_PLANES 3
typedef struct {
BufferHandle hdl;
int32_t shmid;
} PriBufferHandle;
typedef struct {
uint32_t numPlanes;
uint32_t radio[MAX_PLANES];
} PlaneLayoutInfo;
typedef struct {
uint32_t format;
uint32_t bitsPerPixel; // bits per pixel for first plane
const PlaneLayoutInfo *planes;
} FormatInfo;
static const PlaneLayoutInfo g_yuv420SPLayout = {
.numPlanes = 2,
.radio = { 4, 2 },
};
static const PlaneLayoutInfo g_yuv420PLayout = {
.numPlanes = 3,
.radio = { 4, 1, 1 },
};
static const FormatInfo *GetFormatInfo(uint32_t format)
{
static const FormatInfo fmtInfos[] = {
{PIXEL_FMT_RGBX_8888, 32, NULL}, {PIXEL_FMT_RGBA_8888, 32, NULL},
{PIXEL_FMT_BGRX_8888, 32, NULL}, {PIXEL_FMT_BGRA_8888, 32, NULL},
{PIXEL_FMT_RGB_888, 24, NULL}, {PIXEL_FMT_BGR_565, 16, NULL},
{PIXEL_FMT_RGBA_5551, 16, NULL}, {PIXEL_FMT_RGB_565, 16, NULL},
{PIXEL_FMT_BGRX_4444, 16, NULL}, {PIXEL_FMT_BGRA_4444, 16, NULL},
{PIXEL_FMT_RGBA_4444, 16, NULL}, {PIXEL_FMT_RGBX_4444, 16, NULL},
{PIXEL_FMT_BGRX_5551, 16, NULL}, {PIXEL_FMT_BGRA_5551, 16, NULL},
{PIXEL_FMT_YCBCR_420_SP, 8, &g_yuv420SPLayout}, {PIXEL_FMT_YCRCB_420_SP, 8, &g_yuv420SPLayout},
{PIXEL_FMT_YCBCR_420_P, 8, &g_yuv420PLayout}, {PIXEL_FMT_YCRCB_420_P, 8, &g_yuv420PLayout},
};
for (uint32_t i = 0; i < sizeof(fmtInfos) / sizeof(FormatInfo); i++) {
if (fmtInfos[i].format == format) {
return &fmtInfos[i];
}
}
HDF_LOGE("the format can not support %d %d", format, PIXEL_FMT_RGBA_8888);
return NULL;
}
static uint32_t AdjustStrideFromFormat(uint32_t format, uint32_t width)
{
const FormatInfo *fmtInfo = GetFormatInfo(format);
if ((fmtInfo != NULL) && (fmtInfo->planes != NULL)) {
uint32_t sum = fmtInfo->planes->radio[0];
for (uint32_t i = 1; (i < fmtInfo->planes->numPlanes) && (i < MAX_PLANES); i++) {
sum += fmtInfo->planes->radio[i];
}
if (sum > 0) {
width = DIV_ROUND_UP((width * sum), fmtInfo->planes->radio[0]);
}
}
return width;
}
static int32_t InitBufferHandle(PriBufferHandle* buffer, const AllocInfo* info)
{
int32_t size;
int32_t stride;
int32_t h = ALIGN_UP(info->height, HEIGHT_ALIGN);
const FormatInfo *fmtInfo = GetFormatInfo(info->format);
if (fmtInfo == NULL) {
HDF_LOGE("can not get format information : %d", buffer->hdl.format);
return DISPLAY_FAILURE;
}
stride = ALIGN_UP(AdjustStrideFromFormat(info->format, info->width), WIDTH_ALIGN) *
fmtInfo->bitsPerPixel / BITS_PER_BYTE;
size = h * stride;
buffer->hdl.width = info->width;
buffer->hdl.stride = stride;
buffer->hdl.height = info->height;
buffer->hdl.size = size;
buffer->hdl.usage = info->usage;
buffer->hdl.fd = -1;
buffer->shmid = INVALID_SHMID;
buffer->hdl.format = info->format;
buffer->hdl.reserveInts = (sizeof(PriBufferHandle) - sizeof(BufferHandle) -
buffer->hdl.reserveFds * sizeof(uint32_t)) / sizeof(uint32_t);
return DISPLAY_SUCCESS;
}
static int32_t AllocShm(BufferHandle *buffer)
{
static int32_t key = SHM_START_KEY;
int32_t shmid;
while ((shmid = shmget(key, buffer->size, IPC_CREAT | IPC_EXCL | DEFAULT_READ_WRITE_PERMISSIONS)) < 0) {
if (errno != EEXIST) {
HDF_LOGE("%s: fail to alloc the shared memory, errno = %d", __func__, errno);
return DISPLAY_FAILURE;
}
key++;
if (key >= SHM_MAX_KEY) {
key = SHM_START_KEY;
}
}
void *pBase = shmat(shmid, NULL, 0);
if (pBase == ((void *)-1)) {
HDF_LOGE("%s: Fail to attach the shared memory, errno = %d", __func__, errno);
if (shmctl(shmid, IPC_RMID, 0) == -1) {
HDF_LOGE("%s: Fail to free shmid, errno = %d", __func__, errno);
}
return DISPLAY_FAILURE;
}
buffer->virAddr = pBase;
buffer->key = key;
((PriBufferHandle*)buffer)->shmid = shmid;
key++;
if (key >= SHM_MAX_KEY) {
key = SHM_START_KEY;
}
return DISPLAY_SUCCESS;
}
static int32_t AllocMem(const AllocInfo* info, BufferHandle **buffer)
{
int32_t ret;
BufferHandle *bufferHdl = NULL;
DISPLAY_CHK_RETURN((buffer == NULL), DISPLAY_NULL_PTR, HDF_LOGE("%s: in buffer is null", __func__));
DISPLAY_CHK_RETURN((info == NULL), DISPLAY_NULL_PTR, HDF_LOGE("%s: in info is null", __func__));
PriBufferHandle* priBuffer = calloc(1, sizeof(PriBufferHandle));
DISPLAY_CHK_RETURN((priBuffer == NULL), DISPLAY_NULL_PTR, HDF_LOGE("%s: can not calloc errno : %d",
__func__, errno));
ret = InitBufferHandle(priBuffer, info);
DISPLAY_CHK_RETURN((ret != DISPLAY_SUCCESS), DISPLAY_FAILURE, HDF_LOGE("%s: can not init buffe handle",
__func__); goto OUT);
bufferHdl = &priBuffer->hdl;
DISPLAY_CHK_RETURN(((bufferHdl->size > MAX_MALLOC_SIZE) || (bufferHdl->size == 0)),
DISPLAY_FAILURE, HDF_LOGE("%s: size is invalid %d ", __func__, bufferHdl->size););
/*****海思强绑定******/
// if (bufferHdl->usage == HBM_USE_MEM_SHARE) {
ret = AllocShm(bufferHdl);
// } else {
// dprintf(1,"%s: not support memory usage: 0x%" PRIx64 "", __func__, bufferHdl->usage);
// ret = DISPLAY_NOT_SUPPORT;
// }
OUT:
if ((ret != DISPLAY_SUCCESS) && (bufferHdl != NULL)) {
free(bufferHdl);
bufferHdl = NULL;
}
*buffer = bufferHdl;
return ret;
}
static void FreeShm(BufferHandle *buffer)
{
CHECK_NULLPOINTER_RETURN(buffer->virAddr);
if (shmdt(buffer->virAddr) == -1) {
HDF_LOGE("%s: Fail to free shared memory, errno = %d", __func__, errno);
}
if (shmctl(((PriBufferHandle*)buffer)->shmid, IPC_RMID, 0) == -1) {
HDF_LOGE("%s: Fail to free shmid, errno = %d", __func__, errno);
}
}
static void FreeMem(BufferHandle *buffer)
{
CHECK_NULLPOINTER_RETURN(buffer);
if ((buffer->size > MAX_MALLOC_SIZE) || (buffer->size == 0)) {
HDF_LOGE("%s: size is invalid, buffer->size = %d", __func__, buffer->size);
return;
}
/*****海思强绑定******/
// if (buffer->usage == HBM_USE_MEM_SHARE) {
FreeShm(buffer);
return;
// } else {
// HDF_LOGE("%s: not support memory usage: 0x%" PRIx64 "", __func__, buffer->usage);
// }
}
static void *Mmap(BufferHandle *buffer)
{
CHECK_NULLPOINTER_RETURN_VALUE(buffer, NULL);
if ((buffer->size > MAX_MALLOC_SIZE) || (buffer->size == 0)) {
HDF_LOGE("%s: size is invalid, buffer->size = %d", __func__, buffer->size);
return NULL;
}
int32_t shmid = shmget(buffer->key, buffer->size, IPC_EXCL | DEFAULT_READ_WRITE_PERMISSIONS);
if (shmid < 0) {
HDF_LOGE("%s: Fail to mmap the shared memory, errno = %d", __func__, errno);
return NULL;
}
void *pBase = shmat(shmid, NULL, 0);
if (pBase == ((void *)-1)) {
HDF_LOGE("%s: Fail to attach the shared memory, errno = %d", __func__, errno);
return NULL;
}
((PriBufferHandle*)buffer)->shmid = shmid;
buffer->virAddr = pBase;
HDF_LOGI("%s: Mmap shared memory succeed", __func__);
return pBase;
}
static int32_t Unmap(BufferHandle *buffer)
{
CHECK_NULLPOINTER_RETURN_VALUE(buffer, DISPLAY_NULL_PTR);
CHECK_NULLPOINTER_RETURN_VALUE(buffer->virAddr, DISPLAY_NULL_PTR);
if ((buffer->size > MAX_MALLOC_SIZE) || (buffer->size == 0)) {
HDF_LOGE("%s: size is invalid, buffer->size = %d", __func__, buffer->size);
return DISPLAY_FAILURE;
}
if (shmdt(buffer->virAddr) == -1) {
HDF_LOGE("%s: Fail to unmap shared memory errno = %d", __func__, errno);
return DISPLAY_FAILURE;
}
int32_t shmid = ((PriBufferHandle*)buffer)->shmid;
dprintf(1,"Unmap------------%d\r\n", shmid);
if ((shmid != INVALID_SHMID) && (shmctl(shmid, IPC_RMID, 0) == -1)) {
HDF_LOGE("%s: Fail to free shmid, errno = %d", __func__, errno);
}
return DISPLAY_SUCCESS;
}
int32_t GrallocInitialize(GrallocFuncs **funcs)
{
if (funcs == NULL) {
HDF_LOGE("%s: funcs is null", __func__);
return DISPLAY_NULL_PTR;
}
GrallocFuncs *gFuncs = (GrallocFuncs *)malloc(sizeof(GrallocFuncs));
if (gFuncs == NULL) {
HDF_LOGE("%s: gFuncs is null", __func__);
return DISPLAY_NULL_PTR;
}
(void)memset_s(gFuncs, sizeof(GrallocFuncs), 0, sizeof(GrallocFuncs));
gFuncs->AllocMem = AllocMem;
gFuncs->FreeMem = FreeMem;
gFuncs->Mmap = Mmap;
gFuncs->Unmap = Unmap;
*funcs = gFuncs;
HDF_LOGI("%s: gralloc initialize success", __func__);
return DISPLAY_SUCCESS;
}
int32_t GrallocUninitialize(GrallocFuncs *funcs)
{
if (funcs == NULL) {
HDF_LOGE("%s: funcs is null", __func__);
return DISPLAY_NULL_PTR;
}
free(funcs);
HDF_LOGI("%s: gralloc uninitialize success", __func__);
return DISPLAY_SUCCESS;
}
common/hal/display/display_layer.c
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/*
* Copyright (c) 2021 Huawei Device Co., Ltd.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "display_layer.h"
#include <errno.h>
#include <stdio.h>
#include <unistd.h>
#include <sys/mman.h>
#include <securec.h>
#include "hdf_log.h"
#include "display_type.h"
#define DEV_ID 0
#define LAYER_ID 0
#define FB_PATH "/dev/fb0"
#define DISP_WIDTH 800
#define DISP_HEIGHT 480
#define BITS_PER_PIXEL 32
#define BITS_TO_BYTE 8
struct LayerPrivate {
int32_t fd;
uint32_t width;
uint32_t height;
int32_t pitch;
void *fbAddr;
uint32_t fbSize;
void *layerAddr;
PixelFormat pixFmt;
};
static struct LayerPrivate *GetLayerInstance(void)
{
static struct LayerPrivate layerPriv = {
.fd = -1,
.width = DISP_WIDTH,
.height = DISP_HEIGHT,
.pixFmt = PIXEL_FMT_RGBA_8888,
};
return &layerPriv;
}
static int32_t InitDisplay(uint32_t devId)
{
if (devId != DEV_ID) {
HDF_LOGE("%s: devId invalid", __func__);
return DISPLAY_FAILURE;
}
return DISPLAY_SUCCESS;
}
static int32_t DeinitDisplay(uint32_t devId)
{
if (devId != DEV_ID) {
HDF_LOGE("%s: devId invalid", __func__);
return DISPLAY_FAILURE;
}
return DISPLAY_SUCCESS;
}
static void SetBackground(void)
{
struct LayerPrivate *priv = GetLayerInstance();
uint32_t i;
uint32_t j;
uint32_t *framebuffer = (uint32_t *)priv->fbAddr;
for (j = 0; j < priv->height; j++) {
for (i = 0; i < priv->width; i++) {
framebuffer[i + j * priv->width] = 0xFF00FF00; // Blue background
}
}
}
static int32_t CreateLayer(uint32_t devId, const LayerInfo *layerInfo, uint32_t *layerId)
{
if (layerInfo == NULL || layerId == NULL) {
HDF_LOGE("%s: pointer is null", __func__);
return DISPLAY_NULL_PTR;
}
if (devId != DEV_ID) {
HDF_LOGE("%s: devId invalid", __func__);
return DISPLAY_FAILURE;
}
struct LayerPrivate *priv = GetLayerInstance();
priv->fd = open(FB_PATH, O_RDWR, 0);
if (priv->fd < 0) {
HDF_LOGE("%s: open fb dev failed", __func__);
return DISPLAY_FD_ERR;
}
priv->pitch = layerInfo->width * BITS_PER_PIXEL / BITS_TO_BYTE;
priv->fbSize = ((priv->pitch * priv->height) + 0xfff) & (~0xfff);
priv->fbAddr = (void *)mmap(NULL, priv->fbSize, PROT_READ | PROT_WRITE, MAP_SHARED, priv->fd, 0);
if (priv->fbAddr == NULL) {
HDF_LOGE("%s: mmap fb address failure, errno: %d", __func__, errno);
close(priv->fd);
priv->fd = -1;
priv->pitch = 0;
priv->fbSize = 0;
return DISPLAY_FAILURE;
}
SetBackground();
*layerId = LAYER_ID;
HDF_LOGI("%s: open layer success", __func__);
return DISPLAY_SUCCESS;
}
static int32_t CloseLayer(uint32_t devId, uint32_t layerId)
{
if (devId != DEV_ID) {
HDF_LOGE("%s: devId invalid", __func__);
return DISPLAY_FAILURE;
}
if (layerId != LAYER_ID) {
HDF_LOGE("%s: layerId invalid", __func__);
return DISPLAY_FAILURE;
}
struct LayerPrivate *priv = GetLayerInstance();
if (priv->fd >= 0) {
close(priv->fd);
}
if (priv->layerAddr != NULL) {
free(priv->layerAddr);
priv->layerAddr = NULL;
}
if (priv->fbAddr != NULL) {
munmap(priv->fbAddr, priv->fbSize);
}
priv->fd = -1;
return DISPLAY_SUCCESS;
}
static int32_t GetDisplayInfo(uint32_t devId, DisplayInfo *dispInfo)
{
if (dispInfo == NULL) {
HDF_LOGE("%s: dispInfo is null", __func__);
return DISPLAY_NULL_PTR;
}
if (devId != DEV_ID) {
HDF_LOGE("%s: devId invalid", __func__);
return DISPLAY_FAILURE;
}
struct LayerPrivate *priv = GetLayerInstance();
dispInfo->width = priv->width;
dispInfo->height = priv->height;
dispInfo->rotAngle = ROTATE_NONE;
HDF_LOGD("%s: width = %u, height = %u, rotAngle = %u", __func__, dispInfo->width,
dispInfo->height, dispInfo->rotAngle);
return DISPLAY_SUCCESS;
}
static int32_t Flush(uint32_t devId, uint32_t layerId, LayerBuffer *buffer)
{
int32_t ret;
if (devId != DEV_ID) {
HDF_LOGE("%s: devId invalid", __func__);
return DISPLAY_FAILURE;
}
if (layerId != LAYER_ID) {
HDF_LOGE("%s: layerId invalid", __func__);
return DISPLAY_FAILURE;
}
if (buffer == NULL) {
HDF_LOGE("%s: buffer is null", __func__);
return DISPLAY_FAILURE;
}
struct LayerPrivate *priv = GetLayerInstance();
ret = memcpy_s(priv->fbAddr, priv->fbSize, buffer->data.virAddr, priv->fbSize);
if (ret != EOK) {
HDF_LOGE("%s: memcpy_s fail, ret %d", __func__, ret);
return ret;
}
return DISPLAY_SUCCESS;
}
static int32_t GetLayerBuffer(uint32_t devId, uint32_t layerId, LayerBuffer *buffer)
{
if (buffer == NULL) {
HDF_LOGE("%s: buffer is null", __func__);
return DISPLAY_NULL_PTR;
}
if (devId != DEV_ID) {
HDF_LOGE("%s: devId invalid", __func__);
return DISPLAY_FAILURE;
}
if (layerId != LAYER_ID) {
HDF_LOGE("%s: layerId invalid", __func__);
return DISPLAY_FAILURE;
}
struct LayerPrivate *priv = GetLayerInstance();
if (priv->fd < 0) {
HDF_LOGE("%s: fd invalid", __func__);
return DISPLAY_FAILURE;
}
buffer->fenceId = 0;
buffer->width = priv->width;
buffer->height = priv->height;
buffer->pixFormat = priv->pixFmt;
buffer->pitch = priv->pitch;
buffer->data.virAddr = malloc(priv->fbSize);
if (buffer->data.virAddr == NULL) {
HDF_LOGE("%s: malloc failure", __func__);
return DISPLAY_FAILURE;
}
priv->layerAddr = buffer->data.virAddr;
(void)memset_s(buffer->data.virAddr, priv->fbSize, 0x00, priv->fbSize);
HDF_LOGD("%s: fenceId = %d, width = %d, height = %d, pixFormat = %d, pitch = %d", __func__, buffer->fenceId,
buffer->width, buffer->height, buffer->pixFormat, buffer->pitch);
return DISPLAY_SUCCESS;
}
int32_t LayerInitialize(LayerFuncs **funcs)
{
if (funcs == NULL) {
HDF_LOGE("%s: funcs is null", __func__);
return DISPLAY_NULL_PTR;
}
LayerFuncs *lFuncs = (LayerFuncs *)malloc(sizeof(LayerFuncs));
if (lFuncs == NULL) {
HDF_LOGE("%s: lFuncs is null", __func__);
return DISPLAY_NULL_PTR;
}
(void)memset_s(lFuncs, sizeof(LayerFuncs), 0, sizeof(LayerFuncs));
lFuncs->InitDisplay = InitDisplay;
lFuncs->DeinitDisplay = DeinitDisplay;
lFuncs->GetDisplayInfo = GetDisplayInfo;
lFuncs->CreateLayer = CreateLayer;
lFuncs->CloseLayer = CloseLayer;
lFuncs->Flush = Flush;
lFuncs->GetLayerBuffer = GetLayerBuffer;
*funcs = lFuncs;
HDF_LOGI("%s: success", __func__);
return DISPLAY_SUCCESS;
}
int32_t LayerUninitialize(LayerFuncs *funcs)
{
if (funcs == NULL) {
HDF_LOGE("%s: funcs is null", __func__);
return DISPLAY_NULL_PTR;
}
free(funcs);
HDF_LOGI("%s: layer uninitialize success", __func__);
return DISPLAY_SUCCESS;
}
common/platform/BUILD.gn
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# Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology Co., Ltd.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import("//drivers/adapter/khdf/liteos/hdf.gni")
group("drivers") {
deps = [
"adc",
"gpio",
"i2c",
"iwdg",
"uart",
"stm32mp1xx_hal",
"wlan:wifi_firmware"
]
}
config("public") {
lib_dirs = [ "//device/soc/st/common/platform/libs/ohos/llvm/stm32mp157" ]
ldflags = [ "-Wl,--push-state,--whole-archive" ]
ldflags += [ "-lltdc" ]
if (defined(LOSCFG_DRIVERS_MMC)) {
ldflags += [ "-lmmc" ]
}
if (defined(LOSCFG_DRIVERS_HDF_WIFI)) {
ldflags += [ "-lhdf_vendor_wifi" ]
}
if (defined(LOSCFG_DRIVERS_HDF_WIFI) && defined(LOSCFG_DRIVERS_HI3881)) {
ldflags += [ "-lhi3881" ]
}
}
common/platform/Kconfig
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# none hdf driver configs
choice
prompt "Enable Uart"
default DRIVERS_HDF_PLATFORM_UART
help
Enable simple uart (without vfs) only for litekernel.
Enable general uart (with vfs) for full code.
config DRIVERS_HDF_PLATFORM_UART
bool "Enable HDF platform uart driver"
depends on DRIVERS_HDF_PLATFORM
help
Answer Y to enable HDF platform uart driver.
config PLATFORM_UART_WITHOUT_VFS
bool "Simple Uart"
config PLATFORM_NO_UART
bool "NO Uart"
endchoice
# mmc config start
config DRIVERS_MMC
depends on DRIVERS
bool "Enable MMC"
default y
depends on DRIVERS && FS_VFS
help
Answer Y to enable LiteOS support MMC driver.
config DRIVERS_EMMC
depends on DRIVERS_MMC && PLATFORM_STM32MP157
bool "Enable MMC0 support eMMC type"
# mmc config end
# mtd configs tart
config DRIVERS_MTD
bool "Enable MTD"
default y
depends on DRIVERS && FS_VFS
help
Answer Y to enable LiteOS support jffs2 multipartion.
# spi nor
config DRIVERS_MTD_SPI_NOR
bool "Enable MTD spi_nor flash"
default y
depends on DRIVERS_MTD
help
Answer Y to support spi_nor flash.
config DRIVERS_HI3881
bool "Enable Hi3881 Host driver"
default n
depends on DRIVERS_HDF_WIFI
help
Answer Y to enable Hi3881 Host driver.
common/platform/adc/BUILD.gn
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# Copyright (c) 2022 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import("//drivers/adapter/khdf/liteos/hdf.gni")
module_switch = defined(LOSCFG_DRIVERS_HDF_PLATFORM_ADC)
module_name = "hdf_adc"
hdf_driver(module_name) {
sources = [ "stm32mp1_adc.c" ]
include_dirs = [
".",
"../stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc",
]
}
common/platform/adc/stm32mp1_adc.c
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/*
* Copyright (c) 2022 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "stm32mp1_adc.h"
#include "device_resource_if.h"
#include "hdf_device_desc.h"
#include "hdf_log.h"
#include "osal_io.h"
#include "osal_mem.h"
#include "osal_time.h"
#include "stm32mp1xx.h"
#include "stm32mp1xx_hal_conf.h"
#define HDF_LOG_TAG stm32mp1_adc
static void Mp15xAdcPinInit(struct Mp15xAdcDevice *stm32mp1)
{
uint32_t i;
uint32_t value;
volatile unsigned char *gpioBase;
volatile unsigned char *comBase;
gpioBase = OsalIoRemap(MP15X_GPIO_BASE + MP15X_GPIO_MODE_REG_OFFSET,
MP15X_GPIO_GROUP_NUMBER * MP15X_GPIO_GROUP_SIZE);
for (i = 0; i < MP15X_ADC_CHANNEL_COUNT_MAX; i++) {
if (stm32mp1->validChannel[i] == 0 || stm32mp1->pins[i * MP1_ADC_PIN_DATA_WIDTH] >= MP15X_GPIO_GROUP_NUMBER) {
continue;
}
value = OSAL_READL(gpioBase);
value |= (MP15X_GPIO_ANALOG_MODE_MASK << MP15X_GPIO_REG_PIN_SHIFT);
OSAL_WRITEL(value, MP15X_GPIO_BASE + MP15X_GPIO_MODE_REG_OFFSET);
RCC->MC_AHB4ENSETR |= 0x1U << stm32mp1->pins[i * MP1_ADC_PIN_DATA_WIDTH];
}
RCC->PLL4CR |= 0x1U;
comBase = OsalIoRemap(MP15X_ADC_COMMON_REG_BASE, MP15X_ADC_COMMON_REG_SIZE);
OSAL_WRITEL(MP15X_ADC_CKMODE_SEL, comBase + MP15X_ADC_CCR_OFFSET);
if (stm32mp1->devNum == MP15X_ADC_DEVICE_2) {
value = stm32mp1->validChannel[MP15X_ADC_VDDCORE_CHANNEL] & 0x1U; // VddCore
OSAL_WRITEL(value, stm32mp1->regBase + MP15X_ADC_OR_OFFSET);
value = stm32mp1->validChannel[MP15X_ADC_VREF_CHANNEL] & 0x1U; // Vref
value |= (stm32mp1->validChannel[MP15X_ADC_TSEN_CHANNEL] & 0x1U) << MP15X_ADC_VREF_SHIFT; // Tsen
value |= (stm32mp1->validChannel[MP15X_ADC_VBAT_CHANNEL] & 0x1U) << MP15X_ADC_VBAT_SHIFT; // Vbat
OSAL_WRITEL(value, comBase + MP15X_ADC_CCR_OFFSET);
}
}
static inline void Mp15xAdcReset(struct Mp15xAdcDevice *stm32mp1)
{
(void)stm32mp1;
}
static inline void Mp15xAdcSetConfig(struct Mp15xAdcDevice *stm32mp1)
{
uint32_t value;
value = 0x1U << MP15X_ADC_JQDIS_SHIFT;
OSAL_WRITEL(value, stm32mp1->regBase + MP15X_ADC_CFGR_OFFSET);
}
static inline void Mp15xAdcSetSampleTime(struct Mp15xAdcDevice *stm32mp1)
{
uint32_t sampleTime;
uint32_t i;
sampleTime = 0;
for (i = 0; i <MP15X_CHANNLE_NUM_PER_REG; i++) {
sampleTime |= (stm32mp1->sampleTime & MP15X_SAMPLE_TIME_MASK) << (i * MP15X_SAMPLE_TIME_BITS);
}
OSAL_WRITEL(sampleTime, stm32mp1->regBase + MP15X_ADC_SMPR1_OFFSET);
OSAL_WRITEL(sampleTime, stm32mp1->regBase + MP15X_ADC_SMPR2_OFFSET);
}
static void Mp15xAdcCalibration(struct Mp15xAdcDevice *stm32mp1)
{
uint32_t value;
uint32_t delay = 0;
OSAL_WRITEL(0, stm32mp1->regBase + MP15X_ADC_CR_OFFSET);
OSAL_WRITEL(MP15X_ADC_REGULATOR_EN, stm32mp1->regBase + MP15X_ADC_CR_OFFSET);
while (1) {
value = OSAL_READL(stm32mp1->regBase + MP15X_ADC_ISR_OFFSET);
if (((value >> MP15X_ADC_REGULATOR_RDY_SHIFT) & 0x1U) == 1 || delay > MP15X_ADC_CAL_TIME_OUT) {
break;
}
OsalMDelay(1);
delay++;
}
delay = 0;
value = OSAL_READL(stm32mp1->regBase + MP15X_ADC_CR_OFFSET);
value |= 0x1U << MP15X_ADC_ADCAL_SHIFT;
OSAL_WRITEL(value, stm32mp1->regBase + MP15X_ADC_CR_OFFSET);
while (1) {
value = OSAL_READL(stm32mp1->regBase + MP15X_ADC_CR_OFFSET);
if (((value >> MP15X_ADC_ADCAL_SHIFT) & 0x1U) == 0 || delay > MP15X_ADC_CAL_TIME_OUT) {
break;
}
OsalMDelay(1);
delay++;
}
}
static inline void Mp15xAdcClkEnable(struct Mp15xAdcDevice *stm32mp1)
{
static bool hasInit = false;
if (hasInit == true) {
return;
}
__HAL_RCC_ADC12_CLK_ENABLE();
hasInit = true;
}
static inline void Mp15xAdcEnable(struct Mp15xAdcDevice *stm32mp1)
{
uint32_t value = 0;
value = OSAL_READL(stm32mp1->regBase + MP15X_ADC_CR_OFFSET);
OSAL_WRITEL((value | 1), stm32mp1->regBase + MP15X_ADC_CR_OFFSET);
}
static inline void Mp15xAdcDeviceInit(struct Mp15xAdcDevice *stm32mp1)
{
if (!stm32mp1->adcEnable) {
return;
}
Mp15xAdcClkEnable(stm32mp1);
Mp15xAdcPinInit(stm32mp1);
Mp15xAdcCalibration(stm32mp1);
Mp15xAdcReset(stm32mp1);
Mp15xAdcSetConfig(stm32mp1);
Mp15xAdcSetSampleTime(stm32mp1);
Mp15xAdcEnable(stm32mp1);
}
static inline void Mp15xAdcStart(struct Mp15xAdcDevice *stm32mp1)
{
uint32_t value;
value = OSAL_READL(stm32mp1->regBase + MP15X_ADC_CR_OFFSET);
value |= 0x1U << MP15X_ADC_ADSTART_SHIFT;
value |= MP15X_ADC_ENABLE;
OSAL_WRITEL(value, stm32mp1->regBase + MP15X_ADC_CR_OFFSET);
}
static int32_t Mp15xAdcOpen(struct AdcDevice *device)
{
struct Mp15xAdcDevice *stm32mp1 = NULL;
if (device == NULL) {
HDF_LOGE("%s: device is NULL!", __func__);
return HDF_ERR_INVALID_OBJECT;
}
stm32mp1 = (struct Mp15xAdcDevice *)device;
if (!stm32mp1->adcEnable) {
HDF_LOGE("%s: ADC %u is disabled!", __func__, stm32mp1->devNum);
return HDF_ERR_NOT_SUPPORT;
}
Mp15xAdcStart(stm32mp1);
return HDF_SUCCESS;
}
static int32_t Mp15xAdcClose(struct AdcDevice *device)
{
(void)device;
return HDF_SUCCESS;
}
static inline void Mp15xAdcSetSequence(struct Mp15xAdcDevice *stm32mp1, uint32_t channel)
{
uint32_t value;
if (channel >= MP15X_ADC_CHANNEL_COUNT_MAX) {
return;
}
value = channel << MP15X_ADC_SQ1_SHIFT;
OSAL_WRITEL(value, stm32mp1->regBase + MP15X_ADC_SQR1_OFFSET);
value = 0x1U << channel;
OSAL_WRITEL(value, stm32mp1->regBase + MP15X_ADC_PCSEL_OFFSET);
}
static int32_t Mp15xAdcRead(struct AdcDevice *device, uint32_t channel, uint32_t *val)
{
uint32_t value;
uint32_t delay = 0;
struct Mp15xAdcDevice *stm32mp1 = NULL;
if (device == NULL || val == NULL) {
HDF_LOGE("%s: device or val is NULL!", __func__);
return HDF_ERR_INVALID_OBJECT;
}
if (channel >= MP15X_ADC_CHANNEL_COUNT_MAX) {
HDF_LOGE("%s: invalid channel: %u!", __func__, channel);
return HDF_ERR_INVALID_PARAM;
}
stm32mp1 = (struct Mp15xAdcDevice *)device;
if (!stm32mp1->adcEnable) {
HDF_LOGE("%s: ADC %u is disabled!", __func__, stm32mp1->devNum);
return HDF_ERR_NOT_SUPPORT;
}
Mp15xAdcSetSequence(stm32mp1, channel);
Mp15xAdcStart(stm32mp1);
while (true) {
value = OSAL_READL(stm32mp1->regBase + MP15X_ADC_ISR_OFFSET);
if ((value & MP15X_ADC_EOC_MASK) != 0 || delay > MP15X_ADC_CONV_TIME_OUT) {
OSAL_WRITEL(value, stm32mp1->regBase + MP15X_ADC_ISR_OFFSET);
break;
}
OsalUDelay(1);
delay++;
}
value = OSAL_READL(stm32mp1->regBase + MP15X_ADC_DR_OFFSET);
*val = value >> (MP15X_ADC_DATA_WIDTH_MAX - stm32mp1->dataWidth);
return HDF_SUCCESS;
}
static const struct AdcMethod g_method = {
.start = Mp15xAdcOpen,
.stop = Mp15xAdcClose,
.read = Mp15xAdcRead,
};
static int32_t Mp15xAdcReadDrs(struct Mp15xAdcDevice *stm32mp1, const struct DeviceResourceNode *node)
{
int32_t ret;
struct DeviceResourceIface *drsOps = NULL;
drsOps = DeviceResourceGetIfaceInstance(HDF_CONFIG_SOURCE);
if (drsOps == NULL || drsOps->GetUint32 == NULL || drsOps->GetUint8Array == NULL || drsOps->GetBool == NULL) {
HDF_LOGE("%s: invalid drs ops", __func__);
return HDF_ERR_NOT_SUPPORT;
}
ret = drsOps->GetUint32(node, "reg_pbase", &stm32mp1->regBasePhy, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read regBasePhy failed", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "reg_size", &stm32mp1->regSize, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read regSize failed", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "dev_num", &stm32mp1->devNum, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read devNum failed", __func__);
return ret;
}
ret = drsOps->GetUint8Array(node, "channel_enable", stm32mp1->validChannel, MP15X_ADC_CHANNEL_COUNT_MAX, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read validChannel failed", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "sample_time", &stm32mp1->sampleTime, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read sampleTime failed", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "data_width", &stm32mp1->dataWidth, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read dataWidth failed", __func__);
return ret;
}
stm32mp1->adcEnable = drsOps->GetBool(node, "adc_enable");
ret = drsOps->GetUint8Array(node, "pins", stm32mp1->pins, MP15X_ADC_CHANNEL_COUNT_MAX, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read pin failed", __func__);
return ret;
}
return HDF_SUCCESS;
}
static int32_t Mp15xAdcParseInit(struct HdfDeviceObject *device, struct DeviceResourceNode *node)
{
int32_t ret;
struct Mp15xAdcDevice *stm32mp1 = NULL;
(void)device;
stm32mp1 = (struct Mp15xAdcDevice *)OsalMemCalloc(sizeof(*stm32mp1));
if (stm32mp1 == NULL) {
HDF_LOGE("%s: alloc stm32mp1 failed", __func__);
return HDF_ERR_MALLOC_FAIL;
}
ret = Mp15xAdcReadDrs(stm32mp1, node);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read drs failed:%d", __func__, ret);
goto ERR;
}
stm32mp1->regBase = OsalIoRemap(stm32mp1->regBasePhy, stm32mp1->regSize);
if (stm32mp1->regBase == NULL) {
HDF_LOGE("%s: remap regbase failed", __func__);
ret = HDF_ERR_IO;
goto ERR;
}
Mp15xAdcDeviceInit(stm32mp1);
stm32mp1->device.priv = (void *)node;
stm32mp1->device.devNum = stm32mp1->devNum;
stm32mp1->device.ops = &g_method;
ret = AdcDeviceAdd(&stm32mp1->device);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: add adc device:%u failed", __func__, stm32mp1->devNum);
goto ERR;
}
return HDF_SUCCESS;
ERR:
if (stm32mp1 != NULL) {
if (stm32mp1->regBase != NULL) {
OsalIoUnmap((void *)stm32mp1->regBase);
stm32mp1->regBase = NULL;
}
AdcDeviceRemove(&stm32mp1->device);
OsalMemFree(stm32mp1);
}
return ret;
}
static int32_t Mp15xAdcInit(struct HdfDeviceObject *device)
{
int32_t ret;
struct DeviceResourceNode *childNode = NULL;
HDF_LOGI("%s: Enter", __func__);
if (device == NULL || device->property == NULL) {
HDF_LOGE("%s: device or property is null", __func__);
return HDF_ERR_INVALID_OBJECT;
}
ret = HDF_SUCCESS;
DEV_RES_NODE_FOR_EACH_CHILD_NODE(device->property, childNode) {
ret = Mp15xAdcParseInit(device, childNode);
if (ret != HDF_SUCCESS) {
break;
}
}
return ret;
}
static void Mp15xAdcRemoveByNode(const struct DeviceResourceNode *node)
{
int32_t ret;
int32_t devNum;
struct AdcDevice *device = NULL;
struct Mp15xAdcDevice *stm32mp1 = NULL;
struct DeviceResourceIface *drsOps = NULL;
drsOps = DeviceResourceGetIfaceInstance(HDF_CONFIG_SOURCE);
if (drsOps == NULL || drsOps->GetUint32 == NULL) {
HDF_LOGE("%s: invalid drs ops", __func__);
return;
}
ret = drsOps->GetUint32(node, "devNum", (uint32_t *)&devNum, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read devNum failed", __func__);
return;
}
device = AdcDeviceGet(devNum);
if (device != NULL && device->priv == node) {
AdcDevicePut(device);
AdcDeviceRemove(device);
stm32mp1 = (struct Mp15xAdcDevice *)device;
OsalIoUnmap((void *)stm32mp1->regBase);
OsalMemFree(stm32mp1);
}
return;
}
static void Mp15xAdcRelease(struct HdfDeviceObject *device)
{
const struct DeviceResourceNode *childNode = NULL;
HDF_LOGI("%s: enter", __func__);
if (device == NULL || device->property == NULL) {
HDF_LOGE("%s: device or property is null", __func__);
return;
}
DEV_RES_NODE_FOR_EACH_CHILD_NODE(device->property, childNode) {
Mp15xAdcRemoveByNode(childNode);
}
}
static struct HdfDriverEntry g_stm32mp1AdcDriverEntry = {
.moduleVersion = 1,
.Init = Mp15xAdcInit,
.Release = Mp15xAdcRelease,
.moduleName = "stm32mp157_adc_driver",
};
HDF_INIT(g_stm32mp1AdcDriverEntry);
common/platform/adc/stm32mp1_adc.h
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/*
* Copyright (c) 2022 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __STM32MP1_ADC_H__
#define __STM32MP1_ADC_H__
#include "adc_core.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define MP15X_ADC_CHANNEL_COUNT_MAX 20
#define MP1_ADC_PIN_DATA_WIDTH 2
#define MP15X_ADC_GPIO_A 0
#define MP15X_ADC_GPIO_B 1
#define MP15X_ADC_GPIO_C 2
#define MP15X_ADC_GPIO_D 3
#define MP15X_ADC_GPIO_E 4
#define MP15X_ADC_GPIO_F 5
#define MP15X_ADC_INJECTED_CHANNEL_TAG 253
#define MP15X_ADC_DEDICATED_PIN_TAG 254
#define MP15X_ADC_UNAVAILABLE_CHANNEL_TAG 255
#define MP15X_ADC_DEVICE_1 1
#define MP15X_ADC_DEVICE_2 2
/* EACH ADC REGISITERS OFFSET */
#define MP15X_ADC_ISR_OFFSET 0x00 // ADC 中断和状态寄存器 (ADC_ISR)
#define MP15X_ADC_IER_OFFSET 0x04 // ADC 中断使能寄存器（ADC_IER）
#define MP15X_ADC_CR_OFFSET 0x08 // ADC 控制寄存器（ADC_CR）
#define MP15X_ADC_CFGR_OFFSET 0x0C // ADC 配置寄存器（ADC_CFGR）
#define MP15X_ADC_CFGR2_OFFSET 0x10 // ADC 配置寄存器 2 (ADC_CFGR2)
#define MP15X_ADC_SMPR1_OFFSET 0x14 // ADC 采样时间寄存器 1 (ADC_SMPR1)
#define MP15X_ADC_SMPR2_OFFSET 0x18 // ADC 采样时间寄存器 2 (ADC_SMPR2)
#define MP15X_ADC_PCSEL_OFFSET 0x1C // ADC 通道预选寄存器（ADC_PCSEL）
#define MP15X_ADC_LTR1_OFFSET 0x20 // ADC 看门狗阈值寄存器 1 (ADC_LTR1)
#define MP15X_ADC_HTR1_OFFSET 0x24 // ADC 看门狗阈值寄存器 1 (ADC_HTR1)
#define MP15X_ADC_SQR1_OFFSET 0x30 // ADC 常规序列寄存器 1 (ADC_SQR1)
#define MP15X_ADC_SQR2_OFFSET 0x34 // ADC 常规序列寄存器 2 (ADC_SQR2)
#define MP15X_ADC_SQR3_OFFSET 0x38 // ADC 常规序列寄存器 3 (ADC_SQR3)
#define MP15X_ADC_SQR4_OFFSET 0x3C // ADC 常规序列寄存器 4 (ADC_SQR4)
#define MP15X_ADC_DR_OFFSET 0x40 // ADC 常规数据寄存器 (ADC_DR)
#define MP15X_ADC_JSQR_OFFSET 0x4C // ADC 注入序列寄存器 (ADC_JSQR)
#define MP15X_ADC_OFR1_OFFSET 0x60 // ADC 注入通道 y 偏移寄存器 (ADC_OFR1)
#define MP15X_ADC_OFR2_OFFSET 0x64 // ADC 注入通道 y 偏移寄存器 (ADC_OFR2)
#define MP15X_ADC_OFR3_OFFSET 0x68 // ADC 注入通道 y 偏移寄存器 (ADC_OFR3)
#define MP15X_ADC_OFR4_OFFSET 0x6C // ADC 注入通道 y 偏移寄存器 (ADC_OFR4)
#define MP15X_ADC_JDR1_OFFSET 0x80 // ADC 注入通道 y 数据寄存器 (ADC_JDR1)
#define MP15X_ADC_JDR2_OFFSET 0x84 // ADC 注入通道 y 数据寄存器 (ADC_JDR2)
#define MP15X_ADC_JDR3_OFFSET 0x88 // ADC 注入通道 y 数据寄存器 (ADC_JDR3)
#define MP15X_ADC_JDR4_OFFSET 0x8C // ADC 注入通道 y 数据寄存器 (ADC_JDR4)
#define MP15X_ADC_AWD2CR_OFFSET 0xA0 // ADC 模拟看门狗 2 配置寄存器 (ADC_AWD2CR)
#define MP15X_ADC_AWD3CR_OFFSET 0xA4 // ADC 模拟看门狗 3 配置寄存器 (ADC_AWD3CR)
#define MP15X_ADC_LTR2_OFFSET 0xB0 // ADC 看门狗阈值下限寄存器 2 (ADC_LTR2)
#define MP15X_ADC_HTR2_OFFSET 0xB4 // ADC 看门狗高阈值寄存器 2 (ADC_HTR2)
#define MP15X_ADC_LTR3_OFFSET 0xB8 // ADC 看门狗阈值下限寄存器 3 (ADC_LTR3)
#define MP15X_ADC_HTR3_OFFSET 0xBC // ADC 看门狗高阈值寄存器 3 (ADC_HTR3)
#define MP15X_ADC_DIFSEL_OFFSET 0xC0 // ADC 差分模式选择寄存器（ADC_DIFSEL）
#define MP15X_ADC_CALFACT_OFFSET 0xC4 // ADC 校准因子寄存器 (ADC_CALFACT)
#define MP15X_ADC_CALFACT2_OFFSET 0xC8 // ADC 校准因子寄存器 2 (ADC_CALFACT2)
#define MP15X_ADC_OR_OFFSET 0xD0 // ADC2 选项寄存器（ADC2_OR）
/* MASTER AND SLAVE ADC COMMON REGISITERS OFFSET */
#define MP15X_ADC_COMMON_REG_BASE 0x48003300
#define MP15X_ADC_COMMON_REG_SIZE 0x100
#define MP15X_ADC_CCR_OFFSET 0x08
#define MP15X_ADC_CSR_OFFSET 0x00 // ADC 通用状态寄存器（ADC_CSR）
#define MP15X_ADC_CCR_OFFSET 0x08 // ADC 通用控制寄存器（ADC_CCR）
#define MP15X_ADC_CDR_OFFSET 0x0C // ADC 双模通用常规数据寄存器 (ADC_CDR)
#define MP15X_ADC_CDR2_OFFSET 0x10 // 32位双模ADC常用常规数据寄存器 (ADC_CDR2)
#define MP15X_ADC_HWCFGR0_OFFSET 0x3F0 // ADC 硬件配置寄存器（ADC_HWCFGR0）
#define MP15X_ADC_VERR_OFFSET 0x3F4 // ADC 版本寄存器（ADC_VERR）
#define MP15X_ADC_IPDR_OFFSET 0x3F8 // ADC 识别寄存器（ADC_IPIDR）
#define MP15X_ADC_SIDR_OFFSET 0x3FC // ADC 大小识别寄存器（ADC_SIDR）
#define MP15X_GPIO_BASE 0x50003000
#define MP15X_GPIO_GROUP_SIZE 0x1000
#define MP15X_GPIO_GROUP_NUMBER 11
#define MP15X_GPIO_MODE_REG_OFFSET 0x0
#define MP15X_GPIO_ANALOG_MODE_MASK 0x3
#define MP15X_GPIO_REG_PIN_SHIFT 2
#define MP15X_ADC_DEVICE_2 2
#define MP15X_ADC_DATA_WIDTH_MAX 16
#define MP15X_CHANNLE_NUM_PER_REG 10
#define MP15X_SAMPLE_TIME_MASK 0x7
#define MP15X_SAMPLE_TIME_BITS 3
#define MP15X_ADC_JQDIS_SHIFT 31
#define MP15X_ADC_SQ1_SHIFT 6
#define MP15X_ADC_ADCAL_SHIFT 31
#define MP15X_ADC_ADSTART_SHIFT 2
#define MP15X_ADC_ENABLE 0x1
#define MP15X_ADC_EOC_MASK (0x1 << 2)
#define MP15X_ADC_REGULATOR_EN (0x1 << 28)
#define MP15X_ADC_REGULATOR_RDY_SHIFT 12
#define MP15X_ADC_CKMODE_SEL (0x2 << 16)
#define MP15X_ADC_CONV_TIME_OUT 100
#define MP15X_ADC_CAL_TIME_OUT 10
#define MP15X_ADC_VDDCORE_CHANNEL 19
#define MP15X_ADC_VREF_CHANNEL 18
#define MP15X_ADC_TSEN_CHANNEL 17
#define MP15X_ADC_VBAT_CHANNEL 16
#define MP15X_ADC_VREF_SHIFT 22
#define MP15X_ADC_TSEN_SHIFT 23
#define MP15X_ADC_VBAT_SHIFT 24
struct Mp15xAdcDevice {
struct AdcDevice device;
uint32_t regBasePhy;
volatile unsigned char *regBase;
uint32_t regSize;
uint32_t devNum;
uint32_t dataWidth;
uint32_t sampleTime;
bool adcEnable;
uint8_t validChannel[MP15X_ADC_CHANNEL_COUNT_MAX];
uint8_t pins[MP15X_ADC_CHANNEL_COUNT_MAX * MP1_ADC_PIN_DATA_WIDTH];
};
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* __STM32MP1_ADC_H__ */
common/platform/gpio/BUILD.gn
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# Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import("//drivers/adapter/khdf/liteos/hdf.gni")
module_switch = defined(LOSCFG_DRIVERS_HDF_PLATFORM_GPIO)
hdf_driver("hdf_gpio") {
sources = [
"stm32mp1_gpio.c",
]
include_dirs = [
"." ,
"../stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc",
]
}
common/platform/gpio/stm32mp1_gpio.c
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/*
* Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "stm32mp1_gpio.h"
static inline struct Mp15xGpioCntlr *ToMp15xGpioCntlr(struct GpioCntlr *cntlr)
{
return (struct Mp15xGpioCntlr *)cntlr;
}
static inline uint16_t Mp15xToGroupNum(uint16_t gpio)
{
return (uint16_t)(gpio / g_Mp15xGpioCntlr.bitNum);
}
static inline uint16_t Mp15xToBitNum(uint16_t gpio)
{
return (uint16_t)(gpio % g_Mp15xGpioCntlr.bitNum);
}
static inline uint16_t Mp15xToGpioNum(uint16_t group, uint16_t bit)
{
return (uint16_t)(group * g_Mp15xGpioCntlr.bitNum + bit);
}
static int32_t Mp15xGetGroupByGpioNum(struct GpioCntlr *cntlr, uint16_t gpio, struct GpioGroup **group)
{
struct Mp15xGpioCntlr *stm32gpio = NULL;
uint16_t groupIndex = Mp15xToGroupNum(gpio);
if (cntlr == NULL || cntlr->priv == NULL) {
HDF_LOGE("%s: cntlr or priv is NULL", __func__);
return HDF_ERR_INVALID_OBJECT;
}
stm32gpio = ToMp15xGpioCntlr(cntlr);
if (groupIndex >= stm32gpio->groupNum) {
HDF_LOGE("%s: err group index:%u", __func__, groupIndex);
return HDF_ERR_INVALID_PARAM;
}
*group = &stm32gpio->groups[groupIndex];
return HDF_SUCCESS;
}
static int32_t Mp15xGpioSetDir(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t dir)
{
int32_t ret;
uint32_t irqSave;
unsigned int val;
volatile unsigned char *addr = NULL;
unsigned int bitNum = Mp15xToBitNum(gpio);
struct GpioGroup *group = NULL;
ret = Mp15xGetGroupByGpioNum(cntlr, gpio, &group);
if (ret != HDF_SUCCESS) {
HDF_LOGE("Mp15xGetGroupByGpioNum failed\n");
return ret;
}
if (OsalSpinLockIrqSave(&group->lock, &irqSave) != HDF_SUCCESS) {
HDF_LOGE("OsalSpinLockIrqSave failed\n");
return HDF_ERR_DEVICE_BUSY;
}
addr = STM32MP15X_GPIO_MODER(group->regBase);
val = OSAL_READL(addr);
if (dir == GPIO_DIR_IN) {
val &= ~(0X3 << (bitNum*2)); /* bit0:1 清零 */
} else if (dir == GPIO_DIR_OUT) {
val &= ~(0X3 << (bitNum*2)); /* bit0:1 清零 */
val |= (0X1 << (bitNum*2)); /* bit0:1 设置 01 */
}
OSAL_WRITEL(val, addr);
(void)OsalSpinUnlockIrqRestore(&group->lock, &irqSave);
return HDF_SUCCESS;
}
static int32_t Mp15xGpioGetDir(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t *dir)
{
int32_t ret;
unsigned int val;
volatile unsigned char *addr = NULL;
unsigned int bitNum = Mp15xToBitNum(gpio);
struct GpioGroup *group = NULL;
ret = Mp15xGetGroupByGpioNum(cntlr, gpio, &group);
if (ret != HDF_SUCCESS) {
return ret;
}
addr = STM32MP15X_GPIO_MODER(group->regBase);
val = OSAL_READL(addr);
if (val & (1 << (bitNum*2))) {
*dir = GPIO_DIR_OUT;
} else {
*dir = GPIO_DIR_IN;
}
return HDF_SUCCESS;
}
static int32_t Mp15xGpioWrite(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t val)
{
int32_t ret;
uint32_t irqSave;
unsigned int valCur;
unsigned int bitNum = Mp15xToBitNum(gpio);
volatile unsigned char *addr = NULL;
struct GpioGroup *group = NULL;
ret = Mp15xGetGroupByGpioNum(cntlr, gpio, &group);
if (ret != HDF_SUCCESS) {
return ret;
}
if (OsalSpinLockIrqSave(&group->lock, &irqSave) != HDF_SUCCESS) {
return HDF_ERR_DEVICE_BUSY;
}
addr = STM32MP15X_GPIO_BSRR(group->regBase);
valCur = OSAL_READL(addr);
if (val == GPIO_VAL_LOW) {
valCur &= ~(0x1 << bitNum);
valCur |= (0x1 << (bitNum+16));
} else {
valCur |= (0x1 << bitNum);
}
OSAL_WRITEL(valCur, addr);
(void)OsalSpinUnlockIrqRestore(&group->lock, &irqSave);
return HDF_SUCCESS;
}
static int32_t Mp15xGpioRead(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t *val)
{
int32_t ret;
unsigned int valCur;
volatile unsigned char *addr = NULL;
unsigned int bitNum = Mp15xToBitNum(gpio);
struct GpioGroup *group = NULL;
ret = Mp15xGetGroupByGpioNum(cntlr, gpio, &group);
if (ret != HDF_SUCCESS) {
return ret;
}
addr = STM32MP15X_GPIO_IDR(group->regBase);
valCur = OSAL_READL(addr);
if (valCur & (1 << bitNum)) {
*val = GPIO_VAL_HIGH;
} else{
*val = GPIO_VAL_LOW;
}
return HDF_SUCCESS;
}
static uint32_t IrqHandleNoShare(uint32_t irq, void *data)
{
unsigned int i;
struct GpioGroup *group = (struct GpioGroup *)data;
if (data == NULL) {
HDF_LOGW("%s: data is NULL!", __func__);
return HDF_ERR_INVALID_PARAM;
}
for (i = 0; i < g_Mp15xGpioCntlr.bitNum; i++) {
if(__HAL_GPIO_EXTI_GET_IT(1<<i,group->exitBase) != 0)
{
__HAL_GPIO_EXTI_CLEAR_IT(1<<i,group->exitBase);
GpioCntlrIrqCallback(&g_Mp15xGpioCntlr.cntlr, Mp15xToGpioNum(group->index, i));
}
}
return HDF_SUCCESS;
}
static uint32_t GetGpioIrqNum(uint16_t pinNum)
{
if(pinNum > 15)
{
HDF_LOGE("%s: get gpio irq num fail!", __func__);
return 0;
}
switch (pinNum)
{
case 0:
return EXTI0_IRQn;
break;
case 1:
return EXTI1_IRQn;
break;
case 2:
return EXTI2_IRQn;
break;
case 3:
return EXTI3_IRQn;
break;
case 4:
return EXTI4_IRQn;
break;
case 5:
return EXTI5_IRQn;
break;
case 6:
return EXTI6_IRQn;
break;
case 7:
return EXTI7_IRQn;
break;
case 8:
return EXTI8_IRQn;
break;
case 9:
return EXTI9_IRQn;
break;
case 10:
return EXTI10_IRQn;
break;
case 11:
return EXTI11_IRQn;
break;
case 12:
return EXTI12_IRQn;
break;
case 13:
return EXTI13_IRQn;
break;
case 14:
return EXTI14_IRQn;
break;
case 15:
return EXTI15_IRQn;
break;
default:
break;
}
return 0;
}
static int32_t GpioRegisterGroupIrqUnsafe(uint16_t pinNum, struct GpioGroup *group)
{
int ret;
ret = OsalRegisterIrq(GetGpioIrqNum(pinNum), 0, IrqHandleNoShare, "GPIO", group);
if (ret != 0) {
(void)OsalUnregisterIrq(GetGpioIrqNum(pinNum), group);
ret = OsalRegisterIrq(GetGpioIrqNum(pinNum), 0, IrqHandleNoShare, "GPIO", group);
}
if (ret != 0) {
HDF_LOGE("%s: irq reg fail:%d!", __func__, ret);
return HDF_FAILURE;
}
ret = OsalEnableIrq(GetGpioIrqNum(pinNum));
if (ret != 0) {
HDF_LOGE("%s: irq enable fail:%d!", __func__, ret);
(void)OsalUnregisterIrq(GetGpioIrqNum(pinNum), group);
return HDF_FAILURE;
}
group->irqFunc = IrqHandleNoShare;
return HDF_SUCCESS;
}
static void GpioClearIrqUnsafe(struct GpioGroup *group, uint16_t bitNum)
{
__HAL_GPIO_EXTI_CLEAR_IT(bitNum,group->exitBase);
}
static int32_t Mp15xGpioSetIrq(struct GpioCntlr *cntlr, uint16_t gpio, uint16_t mode)
{
int32_t ret = HDF_SUCCESS;
uint32_t irqSave;
struct GpioGroup *group = NULL;
unsigned int bitNum = Mp15xToBitNum(gpio);
ret = Mp15xGetGroupByGpioNum(cntlr, gpio, &group);
if (ret != HDF_SUCCESS) {
return ret;
}
if (OsalSpinLockIrqSave(&group->lock, &irqSave) != HDF_SUCCESS) {
return HDF_ERR_DEVICE_BUSY;
}
EXTI_ConfigTypeDef EXTI_ConfigStructure;
EXTI_HandleTypeDef hexti;
Mp15xGpioSetDir(cntlr,gpio,GPIO_DIR_IN);
EXTI_ConfigStructure.Line = EXTI_GPIO | EXTI_EVENT | EXTI_REG1 |bitNum;
EXTI_ConfigStructure.Trigger = EXTI_TRIGGER_FALLING;
EXTI_ConfigStructure.GPIOSel = Mp15xToGroupNum(gpio);
EXTI_ConfigStructure.Mode = EXTI_MODE_C1_INTERRUPT;
HAL_EXTI_SetConfigLine(&hexti, &EXTI_ConfigStructure);
GpioClearIrqUnsafe(group, bitNum); // clear irq on set
if (group->irqFunc != NULL) {
(void)OsalSpinUnlockIrqRestore(&group->lock, &irqSave);
HDF_LOGI("%s: group irq(%p) already registered!", __func__, group->irqFunc);
return HDF_SUCCESS;
}
ret = GpioRegisterGroupIrqUnsafe(bitNum, group);
(void)OsalSpinUnlockIrqRestore(&group->lock, &irqSave);
HDF_LOGI("%s: group irq(%p) registered!", __func__, group->irqFunc);
return ret;
}
static int32_t Mp15xGpioUnsetIrq(struct GpioCntlr *cntlr, uint16_t gpio)
{
int32_t ret = HDF_SUCCESS;
struct Mp15xGpioCntlr *gCntlr = NULL;
if (cntlr == NULL || cntlr->priv == NULL) {
HDF_LOGE("%s: GpioCntlr or cntlr.priv null!", __func__);
return HDF_ERR_INVALID_OBJECT;
}
gCntlr = (struct Mp15xGpioCntlr *)cntlr->priv;
return ret;
}
static int32_t Mp15xGpioEnableIrq(struct GpioCntlr *cntlr, uint16_t gpio)
{
int32_t ret = HDF_SUCCESS;
struct Mp15xGpioCntlr *gCntlr = NULL;
struct GpioGroup *group = NULL;
unsigned int bitNum = Mp15xToBitNum(gpio);
if (cntlr == NULL || cntlr->priv == NULL) {
HDF_LOGE("%s: GpioCntlr or cntlr.priv null!", __func__);
return HDF_ERR_INVALID_OBJECT;
}
ret = Mp15xGetGroupByGpioNum(cntlr, gpio, &group);
if (ret != HDF_SUCCESS) {
HDF_LOGE("Mp15xGetGroupByGpioNum failed\n");
return ret;
}
EXTI_ConfigTypeDef EXTI_ConfigStructure;
EXTI_HandleTypeDef hexti;
Mp15xGpioSetDir(cntlr,gpio,GPIO_DIR_IN);
EXTI_ConfigStructure.Line = EXTI_GPIO | EXTI_EVENT | EXTI_REG1 |bitNum;
EXTI_ConfigStructure.Trigger = EXTI_TRIGGER_FALLING;
EXTI_ConfigStructure.GPIOSel = Mp15xToGroupNum(gpio);
EXTI_ConfigStructure.Mode = EXTI_MODE_C1_INTERRUPT;
HAL_EXTI_SetConfigLine(&hexti, &EXTI_ConfigStructure);
gCntlr = (struct Mp15xGpioCntlr *)cntlr->priv;
return ret;
}
static int32_t Mp15xGpioDisableIrq(struct GpioCntlr *cntlr, uint16_t gpio)
{
int32_t ret = HDF_SUCCESS;
if (cntlr == NULL || cntlr->priv == NULL) {
HDF_LOGE("%s: GpioCntlr or cntlr.priv null!", __func__);
return HDF_ERR_INVALID_OBJECT;
}
struct GpioGroup *group = NULL;
ret = Mp15xGetGroupByGpioNum(cntlr, gpio, &group);
if (ret != HDF_SUCCESS) {
HDF_LOGE("Mp15xGetGroupByGpioNum failed\n");
return ret;
}
EXTI_HandleTypeDef hexti;
HAL_EXTI_ClearConfigLine(&hexti);
return ret;
}
/* GpioMethod definition */
struct GpioMethod g_GpioMethod = {
.request = NULL,
.release = NULL,
.write = Mp15xGpioWrite,
.read = Mp15xGpioRead,
.setDir = Mp15xGpioSetDir,
.getDir = Mp15xGpioGetDir,
.toIrq = NULL,
.setIrq = Mp15xGpioSetIrq,
.unsetIrq = Mp15xGpioUnsetIrq,
.enableIrq = Mp15xGpioEnableIrq,
.disableIrq = Mp15xGpioDisableIrq,
};
static int32_t Mp15xGpioReadDrs(struct Mp15xGpioCntlr *stm32gpio, const struct DeviceResourceNode *node)
{
int32_t ret;
struct DeviceResourceIface *drsOps = NULL;
drsOps = DeviceResourceGetIfaceInstance(HDF_CONFIG_SOURCE);
if (drsOps == NULL || drsOps->GetUint32 == NULL) {
HDF_LOGE("%s: invalid drs ops fail!", __func__);
return HDF_FAILURE;
}
ret = drsOps->GetUint32(node, "gpioRegBase", &stm32gpio->gpioPhyBase, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read regBase fail!", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "gpioRegStep", &stm32gpio->gpioRegStep, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read gpioRegStep fail!", __func__);
return ret;
}
ret = drsOps->GetUint16(node, "groupNum", &stm32gpio->groupNum, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read groupNum fail!", __func__);
return ret;
}
ret = drsOps->GetUint16(node, "bitNum", &stm32gpio->bitNum, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read bitNum fail!", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "irqRegBase", &stm32gpio->irqPhyBase, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read regBase fail!", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "irqRegStep", &stm32gpio->iqrRegStep, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read gpioRegStep fail!", __func__);
return ret;
}
return HDF_SUCCESS;
}
static int32_t InitGpioCntlrMem(struct Mp15xGpioCntlr *cntlr)
{
size_t groupMemSize;
struct GpioGroup *groups = NULL;
if (cntlr == NULL) {
return HDF_ERR_INVALID_PARAM;
}
groupMemSize = sizeof(struct GpioGroup) * cntlr->groupNum;
groups = (struct GpioGroup *)OsalMemCalloc(groupMemSize);
if (groups == NULL) {
return HDF_ERR_MALLOC_FAIL;
}
cntlr->groups = groups;
for (uint16_t i = 0; i < cntlr->groupNum; i++) {
groups[i].index = i;
groups[i].regBase = cntlr->regBase + (i * cntlr->gpioRegStep);
groups[i].exitBase = cntlr->exitBase;
if (OsalSpinInit(&groups[i].lock) != HDF_SUCCESS) {
for (; i > 0; i--) {
(void)OsalSpinDestroy(&groups[i - 1].lock);
}
OsalMemFree(groups);
return HDF_FAILURE;
}
}
return HDF_SUCCESS;
}
static void ReleaseGpioCntlrMem(struct Mp15xGpioCntlr *cntlr)
{
if (cntlr == NULL) {
return;
}
if (cntlr->groups != NULL) {
for (uint16_t i = 0; i < cntlr->groupNum; i++) {
(void)OsalSpinDestroy(&cntlr->groups[i].lock);
}
OsalMemFree(cntlr->groups);
cntlr->groups = NULL;
}
}
/* HdfDriverEntry hook function implementations */
static int32_t GpioDriverBind(struct HdfDeviceObject *device)
{
(void)device;
return HDF_SUCCESS;
}
static int32_t GpioDriverInit(struct HdfDeviceObject *device)
{
int32_t ret;
struct Mp15xGpioCntlr *stm32gpio = &g_Mp15xGpioCntlr;
dprintf("%s: Enter", __func__);
if (device == NULL || device->property == NULL) {
HDF_LOGE("%s: device or property NULL!", __func__);
return HDF_ERR_INVALID_OBJECT;
}
//获取属性数据
ret = Mp15xGpioReadDrs(stm32gpio, device->property);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: get gpio device resource fail:%d", __func__, ret);
return ret;
}
if (stm32gpio->groupNum > GROUP_MAX || stm32gpio->groupNum <= 0 || stm32gpio->bitNum > BIT_MAX ||
stm32gpio->bitNum <= 0) {
HDF_LOGE("%s: invalid groupNum:%u or bitNum:%u", __func__, stm32gpio->groupNum,
stm32gpio->bitNum);
return HDF_ERR_INVALID_PARAM;
}
//寄存器地址映射
stm32gpio->regBase = OsalIoRemap(stm32gpio->gpioPhyBase, stm32gpio->groupNum * stm32gpio->gpioRegStep);
if (stm32gpio->regBase == NULL) {
HDF_LOGE("%s: err remap phy:0x%x", __func__, stm32gpio->gpioPhyBase);
return HDF_ERR_IO;
}
/* OsalIoRemap: remap registers */
stm32gpio->exitBase = OsalIoRemap(stm32gpio->irqPhyBase, stm32gpio->iqrRegStep);
if (stm32gpio->exitBase == NULL) {
dprintf("%s: OsalIoRemap fail!", __func__);
return -1;
}
ret = InitGpioCntlrMem(stm32gpio);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: err init cntlr mem:%d", __func__, ret);
OsalIoUnmap((void *)stm32gpio->regBase);
stm32gpio->regBase = NULL;
return ret;
}
stm32gpio->cntlr.count = stm32gpio->groupNum * stm32gpio->bitNum;
stm32gpio->cntlr.priv = (void *)device->property;
stm32gpio->cntlr.ops = &g_GpioMethod;
ret = GpioCntlrAdd(&stm32gpio->cntlr);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: err add controller: %d", __func__, ret);
return ret;
}
HDF_LOGE("%s: dev service:%s init success!", __func__, HdfDeviceGetServiceName(device));
return ret;
}
static void GpioDriverRelease(struct HdfDeviceObject *device)
{
struct GpioCntlr *gpioCntlr = NULL;
struct Mp15xGpioCntlr *stm32gpioGpioCntlr = NULL;
HDF_LOGD("%s: Enter", __func__);
if (device == NULL) {
HDF_LOGE("%s: device is null!", __func__);
return;
}
GpioCntlrRemove(gpioCntlr);
stm32gpioGpioCntlr = (struct Mp15xGpioCntlr *)gpioCntlr;
ReleaseGpioCntlrMem(stm32gpioGpioCntlr);
OsalIoUnmap((void *)stm32gpioGpioCntlr->regBase);
stm32gpioGpioCntlr->regBase = NULL;
}
/* HdfDriverEntry definition */
struct HdfDriverEntry g_GpioDriverEntry = {
.moduleVersion = 1,
.moduleName = "HDF_PLATFORM_GPIO",
.Bind = GpioDriverBind,
.Init = GpioDriverInit,
.Release = GpioDriverRelease,
};
/* Init HdfDriverEntry */
HDF_INIT(g_GpioDriverEntry);
common/platform/gpio/stm32mp1_gpio.h
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/*
* Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __STM32MP1_GPIO_H__
#define __STM32MP1_GPIO_H__
#include "device_resource_if.h"
#include "gpio_core.h"
#include "hdf_device_desc.h"
#include "hdf_log.h"
#include "osal_io.h"
#include "osal_irq.h"
#include "osal_mem.h"
#include "osal_spinlock.h"
// #include "plat_log.h"
#include "stm32mp1xx_hal.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define HDF_LOG_TAG gpio_stm32mp15xx
#define STM32MP15X_GPIO_MODER(base) ((base) + 0x00)
#define STM32MP15X_GPIO_IDR(base) ((base) + 0x10)
#define STM32MP15X_GPIO_BSRR(base) ((base) + 0x18)
#define GROUP_MAX 13
#define BIT_MAX 16
struct GpioGroup {
volatile unsigned char *regBase;
EXTI_TypeDef *exitBase;
unsigned int index;
OsalIRQHandle irqFunc;
OsalSpinlock lock;
};
struct Mp15xGpioCntlr {
struct GpioCntlr cntlr;
volatile unsigned char *regBase;
EXTI_TypeDef *exitBase;
uint32_t gpioPhyBase;
uint32_t gpioRegStep;
uint32_t irqPhyBase;
uint32_t iqrRegStep;
uint16_t groupNum;
uint16_t bitNum;
struct GpioGroup *groups;
};
static struct Mp15xGpioCntlr g_Mp15xGpioCntlr = {
.groups = NULL,
.groupNum = GROUP_MAX,
.bitNum = BIT_MAX,
};
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif
common/platform/i2c/BUILD.gn
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# Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import("//drivers/adapter/khdf/liteos/hdf.gni")
module_switch = defined(LOSCFG_DRIVERS_HDF_PLATFORM_I2C)
module_name = "hdf_i2c"
hdf_driver(module_name) {
sources = [
"stm32mp1_i2c.c",
]
include_dirs = [
"." ,
"../stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc",
]
}
common/platform/i2c/stm32mp1_i2c.c
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/*
* Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "stm32mp1_i2c.h"
static int HdfCopyFromUser(void *to, const void *from, unsigned long n)
{
int ret;
ret = LOS_CopyToKernel(to, n, from, n);
if (ret != LOS_OK) {
dprintf("%s: copy from kernel fail:%d", __func__, ret);
return HDF_FAILURE;
}
return HDF_SUCCESS;
}
static int HdfCopyToUser(void *to, const void *from, unsigned long n)
{
int ret;
ret = LOS_CopyFromKernel(to, n, from, n);
if (ret != LOS_OK) {
dprintf("%s: copy from kernel fail:%d", __func__, ret);
return HDF_FAILURE;
}
return HDF_SUCCESS;
}
static GPIO_TypeDef * GPIORemp(uint32_t port)
{
if(port > 11)
{
HDF_LOGE("%s: gpio remp stm32mp1 fail!", __func__);
return 0;
}
switch (port)
{
case 0:
return OsalIoRemap(GPIOA_BASE, 0x400);
break;
case 1:
return OsalIoRemap(GPIOB_BASE, 0x400);
break;
case 2:
return OsalIoRemap(GPIOC_BASE, 0x400);
break;
case 3:
return OsalIoRemap(GPIOD_BASE, 0x400);
break;
case 4:
return OsalIoRemap(GPIOE_BASE, 0x400);
break;
case 5:
return OsalIoRemap(GPIOF_BASE, 0x400);
break;
case 6:
return OsalIoRemap(GPIOG_BASE, 0x400);
break;
case 7:
return OsalIoRemap(GPIOH_BASE, 0x400);
break;
case 8:
return OsalIoRemap(GPIOI_BASE, 0x400);
break;
case 9:
return OsalIoRemap(GPIOJ_BASE, 0x400);
break;
case 10:
return OsalIoRemap(GPIOK_BASE, 0x400);
break;
default:
break;
}
return 0;
}
static void Mp15xI2cCntlrInit(struct Mp15xI2cCntlr *stm32mp1)
{
GPIO_InitTypeDef GPIO_Init = {0};
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)&stm32mp1->hi2c;
/* init gpio */
GPIO_Init.Mode = GPIO_MODE_AF_OD; // 模式
GPIO_Init.Pull = GPIO_PULLUP; // 上拉
GPIO_Init.Speed = GPIO_SPEED_FREQ_VERY_HIGH; // 频率
if(stm32mp1->bus == 1) {
GPIO_Init.Alternate = GPIO_AF5;
} else {
GPIO_Init.Alternate = GPIO_AF4;
}
GPIO_Init.Pin = 1<<stm32mp1->i2cClkIomux[1];
HAL_GPIO_Init(GPIORemp(stm32mp1->i2cClkIomux[0]), &GPIO_Init);
GPIO_Init.Pin = 1<<stm32mp1->i2cDataIomux[1];
HAL_GPIO_Init(GPIORemp(stm32mp1->i2cDataIomux[0]), &GPIO_Init);
HAL_I2C_Init(hi2c);
}
static int32_t Mp15xI2cXferOneMsgPolling(const struct Mp15xI2cCntlr *stm32mp1, const struct Mp15xTransferData *td)
{
int32_t status = HDF_SUCCESS;
uint8_t val[255];
struct I2cMsg *msg = &td->msgs[td->index];
I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)&stm32mp1->hi2c;
if(msg->flags & I2C_FLAG_READ)
{
HAL_I2C_Master_Receive(hi2c, msg->addr+1, val, msg->len,1000);
status = HdfCopyToUser((void *)msg->buf, (void *)val, msg->len);
if (status != HDF_SUCCESS) {
HDF_LOGE("%s: HdfCopyFromUser fail:%d", __func__, status);
goto end;
}
}
else
{
status = HdfCopyFromUser((void *)val, (void *)msg->buf, msg->len);
if (status != HDF_SUCCESS) {
HDF_LOGE("%s: copy to kernel fail:%d", __func__, status);
goto end;
}
HAL_I2C_Master_Transmit(hi2c, msg->addr, val, msg->len,1000);
}
end:
return status;
}
static int32_t Mp15xI2cTransfer(struct I2cCntlr *cntlr, struct I2cMsg *msgs, int16_t count)
{
int32_t ret = HDF_SUCCESS;
unsigned long irqSave;
struct Mp15xI2cCntlr *stm32mp1 = NULL;
struct Mp15xTransferData td;
if (cntlr == NULL || cntlr->priv == NULL) {
HDF_LOGE("%s: cntlr lor stm32mp1 null!", __func__);
return HDF_ERR_INVALID_OBJECT;
}
stm32mp1 = (struct Mp15xI2cCntlr *)cntlr;
if (msgs == NULL || count <= 0) {
HDF_LOGE("%s: err parms! count:%d", __func__, count);
return HDF_ERR_INVALID_PARAM;
}
td.msgs = msgs;
td.count = count;
td.index = 0;
irqSave = LOS_IntLock();
while(td.index < td.count)
{
ret = Mp15xI2cXferOneMsgPolling(stm32mp1, &td);
if (ret != 0) {
break;
}
td.index++;
}
LOS_IntRestore(irqSave);
return (td.index > 0) ? td.index : ret;
}
static const struct I2cMethod g_method = {
.transfer = Mp15xI2cTransfer,
};
static int32_t Mp15xI2cLock(struct I2cCntlr *cntlr)
{
struct Mp15xI2cCntlr *stm32mp1 = (struct Mp15xI2cCntlr *)cntlr;
if(stm32mp1 != NULL)
{
return OsalSpinLock(&stm32mp1->spin);
}
return HDF_SUCCESS;
}
static void Mp15xI2cUnlock(struct I2cCntlr *cntlr)
{
struct Mp15xI2cCntlr *stm32mp1 = (struct Mp15xI2cCntlr *)cntlr;
if (stm32mp1 != NULL) {
(void)OsalSpinUnlock(&stm32mp1->spin);
}
}
static const struct I2cLockMethod g_lockOps = {
.lock = Mp15xI2cLock,
.unlock = Mp15xI2cUnlock,
};
static int32_t Mp15xI2cReadDrs(struct Mp15xI2cCntlr *stm32mp1, const struct DeviceResourceNode *node)
{
int32_t ret;
struct DeviceResourceIface *drsOps = NULL;
drsOps = DeviceResourceGetIfaceInstance(HDF_CONFIG_SOURCE);
if (drsOps == NULL || drsOps->GetUint32 == NULL) {
HDF_LOGE("%s: invalid drs ops fail!", __func__);
return HDF_FAILURE;
}
ret = drsOps->GetUint32(node, "reg_pbase", &stm32mp1->regBasePhy, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read regBase fail!", __func__);
return ret;
}
ret = drsOps->GetUint16(node, "reg_size", &stm32mp1->regSize, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read reg_size fail!", __func__);
return ret;
}
ret = drsOps->GetUint16(node, "bus", (uint16_t *)&stm32mp1->bus, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read bus fail!", __func__);
return ret;
}
ret = drsOps->GetUint32Array(node, "i2cClkIomux", stm32mp1->i2cClkIomux, 2, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read no_stretch_mode fail!", __func__);
return ret;
}
ret = drsOps->GetUint32Array(node, "i2cDataIomux", stm32mp1->i2cDataIomux, 2, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read no_stretch_mode fail!", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "timing", &stm32mp1->hi2c.Init.Timing, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read timing fail!", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "own_address1", &stm32mp1->hi2c.Init.OwnAddress1, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read own_address1 fail!", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "addressing_mode", &stm32mp1->hi2c.Init.AddressingMode, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read addressing_mode fail!", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "dual_address_mode", &stm32mp1->hi2c.Init.DualAddressMode, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read dual_address_mode fail!", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "own_address2", &stm32mp1->hi2c.Init.OwnAddress2, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read own_address2 fail!", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "own_address_2_masks", &stm32mp1->hi2c.Init.OwnAddress2Masks, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read own_address_2_masks fail!", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "general_call_mode", &stm32mp1->hi2c.Init.GeneralCallMode, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read general_call_mode fail!", __func__);
return ret;
}
ret = drsOps->GetUint32(node, "no_stretch_mode", &stm32mp1->hi2c.Init.NoStretchMode, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read no_stretch_mode fail!", __func__);
return ret;
}
return HDF_SUCCESS;
}
static void Mp15xI2cRccConfig(uint32_t bus)
{
RCC_PeriphCLKInitTypeDef I2C2_clock_source_config;
switch (bus)
{
case 1:
__HAL_RCC_I2C1_CLK_ENABLE();
I2C2_clock_source_config.I2c12ClockSelection = RCC_I2C12CLKSOURCE_HSI;
I2C2_clock_source_config.PeriphClockSelection = RCC_PERIPHCLK_I2C12;
HAL_RCCEx_PeriphCLKConfig(&I2C2_clock_source_config);
break;
case 2:
__HAL_RCC_I2C2_CLK_ENABLE();
I2C2_clock_source_config.I2c12ClockSelection = RCC_I2C12CLKSOURCE_HSI;
I2C2_clock_source_config.PeriphClockSelection = RCC_PERIPHCLK_I2C12;
HAL_RCCEx_PeriphCLKConfig(&I2C2_clock_source_config);
break;
case 3:
__HAL_RCC_I2C3_CLK_ENABLE();
I2C2_clock_source_config.I2c35ClockSelection = RCC_I2C35CLKSOURCE_HSI;
I2C2_clock_source_config.PeriphClockSelection = RCC_PERIPHCLK_I2C35;
HAL_RCCEx_PeriphCLKConfig(&I2C2_clock_source_config);
break;
case 4:
__HAL_RCC_I2C4_CLK_ENABLE();
I2C2_clock_source_config.I2c46ClockSelection = RCC_I2C46CLKSOURCE_HSI;
I2C2_clock_source_config.PeriphClockSelection = RCC_PERIPHCLK_I2C46;
HAL_RCCEx_PeriphCLKConfig(&I2C2_clock_source_config);
break;
case 5:
__HAL_RCC_I2C5_CLK_ENABLE();
I2C2_clock_source_config.I2c35ClockSelection = RCC_I2C35CLKSOURCE_HSI;
I2C2_clock_source_config.PeriphClockSelection = RCC_PERIPHCLK_I2C35;
HAL_RCCEx_PeriphCLKConfig(&I2C2_clock_source_config);
break;
case 6:
__HAL_RCC_I2C6_CLK_ENABLE();
I2C2_clock_source_config.I2c46ClockSelection = RCC_I2C46CLKSOURCE_HSI;
I2C2_clock_source_config.PeriphClockSelection = RCC_PERIPHCLK_I2C46;
HAL_RCCEx_PeriphCLKConfig(&I2C2_clock_source_config);
break;
default:
break;
}
}
static int32_t Mp15xI2cParseAndInit(struct HdfDeviceObject *device, const struct DeviceResourceNode *node)
{
int32_t ret;
struct Mp15xI2cCntlr *stm32mp1 = NULL;
(void)device;
stm32mp1 = (struct Mp15xI2cCntlr *)OsalMemCalloc(sizeof(*stm32mp1));
if (stm32mp1 == NULL) {
HDF_LOGE("%s: malloc stm32mp1 fail!", __func__);
return HDF_ERR_MALLOC_FAIL;
}
ret = Mp15xI2cReadDrs(stm32mp1, node);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read drs fail! ret:%d", __func__, ret);
goto __ERR__;
}
stm32mp1->hi2c.Instance = (I2C_TypeDef *)OsalIoRemap(stm32mp1->regBasePhy, stm32mp1->regSize);
if (stm32mp1->hi2c.Instance == NULL) {
HDF_LOGE("%s: ioremap regBase fail!", __func__);
ret = HDF_ERR_IO;
goto __ERR__;
}
Mp15xI2cRccConfig(stm32mp1->bus);
Mp15xI2cCntlrInit(stm32mp1);
stm32mp1->cntlr.priv = (void *)node;
stm32mp1->cntlr.busId = stm32mp1->bus;
stm32mp1->cntlr.ops = &g_method;
stm32mp1->cntlr.lockOps = &g_lockOps;
(void)OsalSpinInit(&stm32mp1->spin);
ret = I2cCntlrAdd(&stm32mp1->cntlr);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: add i2c controller fail:%d!", __func__, ret);
(void)OsalSpinDestroy(&stm32mp1->spin);
goto __ERR__;
}
//#ifdef USER_VFS_SUPPORT
(void)I2cAddVfsById(stm32mp1->cntlr.busId);
//#endif
return HDF_SUCCESS;
__ERR__:
if (stm32mp1 != NULL) {
if (stm32mp1->hi2c.Instance != NULL) {
OsalIoUnmap((void *)stm32mp1->hi2c.Instance);
stm32mp1->hi2c.Instance = NULL;
}
OsalMemFree(stm32mp1);
stm32mp1 = NULL;
}
return ret;
}
int32_t HdfI2cDeviceInit(struct HdfDeviceObject *device)
{
int32_t ret;
const struct DeviceResourceNode *childNode = NULL;
HDF_LOGE("%s: Enter", __func__);
if (device == NULL || device->property == NULL) {
HDF_LOGE("%s: device or property is NULL", __func__);
return HDF_ERR_INVALID_OBJECT;
}
ret = HDF_SUCCESS;
DEV_RES_NODE_FOR_EACH_CHILD_NODE(device->property, childNode) {
ret = Mp15xI2cParseAndInit(device, childNode);
if (ret != HDF_SUCCESS) {
break;
}
}
return ret;
}
static void Mp15xI2cRemoveByNode(const struct DeviceResourceNode *node)
{
int32_t ret;
int16_t bus;
struct I2cCntlr *cntlr = NULL;
struct Mp15xI2cCntlr *stm32mp1 = NULL;
struct DeviceResourceIface *drsOps = NULL;
drsOps = DeviceResourceGetIfaceInstance(HDF_CONFIG_SOURCE);
if (drsOps == NULL || drsOps->GetUint32 == NULL) {
HDF_LOGE("%s: invalid drs ops fail!", __func__);
return;
}
ret = drsOps->GetUint16(node, "bus", (uint16_t *)&bus, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read bus fail!", __func__);
return;
}
cntlr = I2cCntlrGet(bus);
if (cntlr != NULL && cntlr->priv == node) {
I2cCntlrPut(cntlr);
I2cCntlrRemove(cntlr);
stm32mp1 = (struct Mp15xI2cCntlr *)cntlr;
OsalIoUnmap((void *)stm32mp1->regBasePhy);
(void)OsalSpinDestroy(&stm32mp1->spin);
OsalMemFree(stm32mp1);
}
return;
}
void HdfI2cDeviceRelease(struct HdfDeviceObject *device)
{
const struct DeviceResourceNode *childNode = NULL;
HDF_LOGI("%s: enter", __func__);
if (device == NULL || device->property == NULL) {
HDF_LOGE("%s: device or property is NULL", __func__);
return;
}
DEV_RES_NODE_FOR_EACH_CHILD_NODE(device->property, childNode) {
Mp15xI2cRemoveByNode(childNode);
}
}
struct HdfDriverEntry g_i2cDriverEntry = {
.moduleVersion = 1,
.Init = HdfI2cDeviceInit,
.Release = HdfI2cDeviceRelease,
.moduleName = "HDF_PLATFORM_I2C",
};
HDF_INIT(g_i2cDriverEntry);
common/platform/i2c/stm32mp1_i2c.h
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/*
* Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __STM32MP1_I2C_H__
#define __STM32MP1_I2C_H__
#include "stm32mp1xx_hal_i2c.h"
#include "device_resource_if.h"
#include "hdf_device_desc.h"
#include "hdf_log.h"
#include "i2c_core.h"
#include "i2c_dev.h"
#include "osal_io.h"
#include "osal_mem.h"
#include "osal_spinlock.h"
#include "stm32mp1xx_hal.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
struct Mp15xI2cCntlr {
struct I2cCntlr cntlr;
OsalSpinlock spin;
I2C_HandleTypeDef hi2c;
int16_t bus;
uint16_t regSize;
uint32_t regBasePhy;
uint32_t i2cClkIomux[2];
uint32_t i2cDataIomux[2];
};
struct Mp15xTransferData {
struct I2cMsg *msgs;
int16_t index;
int16_t count;
};
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif
common/platform/iwdg/BUILD.gn
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# Copyright 2021 yhuan416
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import("//drivers/adapter/khdf/liteos/hdf.gni")
module_switch = defined(LOSCFG_DRIVERS_HDF_PLATFORM_WATCHDOG)
module_name = "hdf_iwdg"
hdf_driver(module_name) {
sources = [
"stm32mp1_iwdg.c"
]
}
common/platform/iwdg/stm32mp1_iwdg.c
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/*
* Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "device_resource_if.h"
#include "hdf_device_desc.h"
#include "osal_io.h"
#include "osal.h"
#include "watchdog_if.h"
#include "watchdog_core.h"
#include "securec.h"
#define HDF_LOG_TAG Mp15xIwdg
#define BITS_PER_LONG 32
#define GENMASK(h, l) \
(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
/* IWDG registers */
#define IWDG_KR 0x00 /* Key register */
#define IWDG_PR 0x04 /* Prescaler Register */
#define IWDG_RLR 0x08 /* ReLoad Register */
#define IWDG_SR 0x0C /* Status Register */
#define IWDG_WINR 0x10 /* Windows Register */
/* IWDG_KR register bit mask */
#define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
#define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
#define KR_KEY_EWA 0x5555 /* write access enable */
#define KR_KEY_DWA 0x0000 /* write access disable */
/* IWDG_PR register */
#define PR_SHIFT 2
#define PR_MIN BIT(PR_SHIFT)
/* IWDG_RLR register values */
#define RLR_MIN 0x2 /* min value recommended */
#define RLR_MAX GENMASK(11, 0) /* max value of reload register */
/* IWDG_SR register bit mask */
#define SR_PVU BIT(0) /* Watchdog prescaler value update */
#define SR_RVU BIT(1) /* Watchdog counter reload value update */
/* set timeout to 100000 us */
#define TIMEOUT_US 100000
#define SLEEP_US 1000
#define DEFAULT_TIMEOUT (32)
#define DEFAULT_TASK_STACK_SIZE (0x800)
#define DEFAULT_CLOCK_RATE (32000)
#define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d))
/**
* fls - find last (most-significant) bit set
* @x: the word to search
*
* This is defined the same way as ffs.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
static inline int generic_fls(int x)
{
int r = 32;
if (!x)
return 0;
if (!(x & 0xffff0000u)) {
x <<= 16;
r -= 16;
}
if (!(x & 0xff000000u)) {
x <<= 8;
r -= 8;
}
if (!(x & 0xf0000000u)) {
x <<= 4;
r -= 4;
}
if (!(x & 0xc0000000u)) {
x <<= 2;
r -= 2;
}
if (!(x & 0x80000000u)) {
x <<= 1;
r -= 1;
}
return r;
}
static inline int ilog2(unsigned int x)
{
return generic_fls(x) - 1;
}
unsigned long roundup_pow_of_two(unsigned long n)
{
return 1UL << generic_fls(n - 1);
}
struct Mp15xIwdg {
struct WatchdogCntlr wdt; // 控制器
uint32_t num; // 当前独立看门狗编号
void volatile *base; // 虚拟地址
uint32_t phy_base; // 物理地址
uint32_t reg_step; // 映射大小
uint32_t seconds; // 当前设置的超时值(s)
bool start; // 当前iwdg是否已经启动
uint32_t rate; // 时钟源频率
char *clock_source; // 时钟源名称
bool auto_feed; // 是否自动喂狗
uint32_t auto_feed_period; // 自动喂狗周期
OSAL_DECLARE_THREAD(feed_dog_thread); // 喂狗线程
uint32_t min_timeout; // 最小超时时间
uint32_t max_hw_heartbeat_ms; // 最大超时时间
};
static inline uint32_t reg_read(void volatile *base, uint32_t reg)
{
return OSAL_READL((uintptr_t)base + reg);
}
static inline void reg_write(void volatile *base, uint32_t reg, uint32_t val)
{
OSAL_WRITEL(val, (uintptr_t)base + reg);
}
// TODO : get clock source real rate
static inline int32_t Mp15xIwdgGetClockRate(struct Mp15xIwdg *iwdg)
{
int ret = HDF_SUCCESS;
/*
if "clock_source" is set, use the real rate of clock source
otherwise, use the default clock rate
*/
if (iwdg->clock_source != NULL) {
// get clock source real rate.
// ...
ret = HDF_SUCCESS;
}
return ret;
}
static inline uint32_t Mp15xIwdgGetSr(struct Mp15xIwdg *iwdg)
{
return reg_read(iwdg->base, IWDG_SR);
}
int32_t Mp15xIwdgStart(struct WatchdogCntlr *wdt)
{
struct Mp15xIwdg *iwdg = NULL;
uint32_t tout, presc, iwdg_pr, iwdg_rlr, iwdg_sr;
uint32_t i = 10;
if (wdt == NULL) {
return HDF_ERR_INVALID_OBJECT;
}
iwdg = (struct Mp15xIwdg *)wdt->priv;
// 计算装载值
tout = iwdg->seconds;// 超时秒数
// 计算边界
if (tout > (iwdg->max_hw_heartbeat_ms * 1000)) {
tout = iwdg->max_hw_heartbeat_ms * 1000;
}
if (tout < iwdg->min_timeout) {
tout = iwdg->min_timeout;
}
presc = DIV_ROUND_UP(tout * iwdg->rate, RLR_MAX + 1);
/* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
presc = roundup_pow_of_two(presc);
iwdg_pr = (presc <= (1 << PR_SHIFT)) ? 0 : ilog2(presc) - PR_SHIFT;
iwdg_rlr = ((tout * iwdg->rate) / presc) - 1;
/* enable write access */
reg_write(iwdg->base, IWDG_KR, KR_KEY_EWA);
/* set prescaler & reload registers */
reg_write(iwdg->base, IWDG_PR, iwdg_pr);
reg_write(iwdg->base, IWDG_RLR, iwdg_rlr);
reg_write(iwdg->base, IWDG_KR, KR_KEY_ENABLE);
// 等待状态寄存器 SR_PVU | SR_RVU 复位
while ((iwdg_sr = Mp15xIwdgGetSr(iwdg)) & (SR_PVU | SR_RVU))
{
OsalMDelay(10);
if(!(--i)) {
HDF_LOGE("Fail to set prescaler, reload regs.");
return HDF_FAILURE;
}
}
/* reload watchdog */
reg_write(iwdg->base, IWDG_KR, KR_KEY_RELOAD);
/* iwdg start */
iwdg->start = true;
return HDF_SUCCESS;
}
int32_t Mp15xIwdgSetTimeout(struct WatchdogCntlr *wdt, uint32_t seconds)
{
struct Mp15xIwdg *iwdg = NULL;
if (wdt == NULL) {
return HDF_ERR_INVALID_OBJECT;
}
iwdg = (struct Mp15xIwdg *)wdt->priv;
iwdg->seconds = seconds;
// 如果iwdg已经是启动状态, 需要重新装载超时值并继续喂狗操作
if (iwdg->start) {
return Mp15xIwdgStart(wdt);
}
return HDF_SUCCESS;
}
int32_t Mp15xIwdgGetTimeout(struct WatchdogCntlr *wdt, uint32_t *seconds)
{
struct Mp15xIwdg *iwdg = NULL;
if (wdt == NULL || seconds == NULL) {
return HDF_ERR_INVALID_OBJECT;
}
iwdg = (struct Mp15xIwdg *)wdt->priv;
*seconds = iwdg->seconds;
return HDF_SUCCESS;
}
static int32_t Mp15xIwdgFeed(struct WatchdogCntlr *wdt)
{
struct Mp15xIwdg *iwdg = NULL;
if (wdt == NULL) {
return HDF_ERR_INVALID_OBJECT;
}
iwdg = (struct Mp15xIwdg *)wdt->priv;
/* reload watchdog */
reg_write(iwdg->base, IWDG_KR, KR_KEY_RELOAD);
return HDF_SUCCESS;
}
static int32_t Mp15xIwdgGetStatus(struct WatchdogCntlr *wdt, int32_t *status)
{
int32_t ret = WATCHDOG_STOP;
struct Mp15xIwdg *iwdg = NULL;
if (wdt == NULL) {
return HDF_ERR_INVALID_OBJECT;
}
iwdg = (struct Mp15xIwdg *)wdt->priv;
if (iwdg->start) {
ret = WATCHDOG_START;
}
return ret;
}
/* WatchdogOpen 的时候被调用 */
static int32_t Mp15xIwdgGetPriv(struct WatchdogCntlr *wdt)
{
int32_t ret;
struct Mp15xIwdg *iwdg = NULL;
if (wdt == NULL) {
return HDF_ERR_INVALID_OBJECT;
}
iwdg = (struct Mp15xIwdg *)wdt->priv;
// 获取当前时钟源频率
ret = Mp15xIwdgGetClockRate(iwdg);
if (ret != HDF_SUCCESS) {
HDF_LOGE("Mp15xIwdgGetClockRate fail, ret : %#x.", ret);
return HDF_FAILURE;
}
// 计算最大最小的超时时间
iwdg->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, iwdg->rate);
iwdg->max_hw_heartbeat_ms = ((RLR_MAX + 1) * 1024 * 1000) / iwdg->rate;
return ret;
}
/* WatchdogClose 的时候被调用 */
static void Mp15xIwdgReleasePriv(struct WatchdogCntlr *wdt)
{
(void)wdt;
}
static struct WatchdogMethod g_stm32mp1_iwdg_ops = {
.feed = Mp15xIwdgFeed,
.getPriv = Mp15xIwdgGetPriv,
.getStatus = Mp15xIwdgGetStatus,
.getTimeout = Mp15xIwdgGetTimeout,
.releasePriv = Mp15xIwdgReleasePriv,
.setTimeout = Mp15xIwdgSetTimeout,
.start = Mp15xIwdgStart,
// stm32mp1的iwdg不支持软件停止
.stop = NULL
};
static int Mp15xIwdgFeedTaskFunc(void *arg)
{
// auto feed dog task
struct WatchdogCntlr *wdt = (struct WatchdogCntlr *)arg;
struct Mp15xIwdg *iwdg = (struct Mp15xIwdg *)wdt->priv;
while (1)
{
if (iwdg->start) {
Mp15xIwdgFeed(wdt);
}
OsalSleep(iwdg->auto_feed_period);
}
return 0;
}
// create timer for auto feed
static int32_t Mp15xIwdgCreateFeedDogTask(struct WatchdogCntlr *wdt)
{
#define TASK_NAME_SIZE (16)
int32_t ret;
struct Mp15xIwdg *iwdg = (struct Mp15xIwdg *)wdt->priv;
struct OsalThreadParam param = {0};
char task_name[TASK_NAME_SIZE] = {0};
// create thread
ret = OsalThreadCreate(&(iwdg->feed_dog_thread), (OsalThreadEntry)Mp15xIwdgFeedTaskFunc, (void *)wdt);
if (ret != HDF_SUCCESS) {
HDF_LOGE("OsalThreadCreate fail, ret : %#x.\r\n", ret);
return HDF_FAILURE;
}
// get task name
snprintf_s(task_name, TASK_NAME_SIZE, TASK_NAME_SIZE - 1, "iwdg%d_auto_feed", iwdg->num);
param.priority = OSAL_THREAD_PRI_DEFAULT;
param.stackSize = DEFAULT_TASK_STACK_SIZE;
param.name = task_name;
return OsalThreadStart(&(iwdg->feed_dog_thread), &param);
}
static int32_t Mp15xIwdgReadDrs(struct Mp15xIwdg *iwdg, const struct DeviceResourceNode *node)
{
int32_t ret;
struct DeviceResourceIface *drsOps = NULL;
drsOps = DeviceResourceGetIfaceInstance(HDF_CONFIG_SOURCE);
if (drsOps == NULL || drsOps->GetUint32 == NULL) {
HDF_LOGE("%s: invalid drs ops!", __func__);
return HDF_FAILURE;
}
// num
ret = drsOps->GetUint32(node, "num", &iwdg->num, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read num fail!", __func__);
return ret;
}
// reg_base
ret = drsOps->GetUint32(node, "reg_base", &iwdg->phy_base, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read regBase fail!", __func__);
return ret;
}
// reg_step
ret = drsOps->GetUint32(node, "reg_step", &iwdg->reg_step, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read regStep fail!", __func__);
return ret;
}
// default timeout
ret = drsOps->GetUint32(node, "timeout_sec", &iwdg->seconds, DEFAULT_TIMEOUT);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read timeout fail!", __func__);
return ret;
}
// default source rate
ret = drsOps->GetUint32(node, "clock_rate", &iwdg->rate, DEFAULT_CLOCK_RATE);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read clock_rate fail!", __func__);
return ret;
}
// start
iwdg->start = drsOps->GetBool(node, "start");
// auto_feed
iwdg->auto_feed = drsOps->GetBool(node, "auto_feed");
// auto_feed_period
ret = drsOps->GetUint32(node, "auto_feed_period", &iwdg->auto_feed_period, 10);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read auto_feed_period fail!", __func__);
}
return HDF_SUCCESS;
}
static int32_t Mp15xIwdgBind(struct HdfDeviceObject *device)
{
int32_t ret;
struct Mp15xIwdg *iwdg = NULL;
if (device == NULL || device->property == NULL) {
HDF_LOGE("%s: device or property is null!", __func__);
return HDF_ERR_INVALID_OBJECT;
}
// 申请内存空间
iwdg = (struct Mp15xIwdg *)OsalMemCalloc(sizeof(struct Mp15xIwdg));
if (iwdg == NULL) {
HDF_LOGE("%s: malloc iwdg fail!", __func__);
return HDF_ERR_MALLOC_FAIL;
}
// 解析配置
ret = Mp15xIwdgReadDrs(iwdg, device->property);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read drs fail:%d", __func__, ret);
OsalMemFree(iwdg);
return ret;
}
// 寄存器映射
iwdg->base = OsalIoRemap(iwdg->phy_base, iwdg->reg_step);
if (iwdg->base == NULL) {
HDF_LOGE("%s: ioremap regbase fail!", __func__);
OsalMemFree(iwdg);
return HDF_ERR_IO;
}
// 填充操作符
iwdg->wdt.priv = (void *)iwdg;
iwdg->wdt.ops = &g_stm32mp1_iwdg_ops;
iwdg->wdt.device = device;
iwdg->wdt.wdtId = iwdg->num;
// add device
ret = WatchdogCntlrAdd(&iwdg->wdt);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: err add watchdog:%d.", __func__, ret);
OsalIoUnmap((void *)iwdg->base);
OsalMemFree(iwdg);
return ret;
}
return HDF_SUCCESS;
}
static int32_t Mp15xIwdgInit(struct HdfDeviceObject *device)
{
int32_t ret;
struct WatchdogCntlr *wdt = NULL;
struct Mp15xIwdg *iwdg = NULL;
// get WatchdogCntlr
wdt = WatchdogCntlrFromDevice(device);
if (wdt == NULL) {
return HDF_FAILURE;
}
iwdg = (struct Mp15xIwdg *)wdt->priv;
// get priv data(get clock source)
ret = Mp15xIwdgGetPriv(wdt);
if (ret != HDF_SUCCESS) {
HDF_LOGE("Mp15xIwdgGetPriv fail.");
return HDF_FAILURE;
}
// set default timeout
ret = Mp15xIwdgSetTimeout(wdt, iwdg->seconds);
if (ret != HDF_SUCCESS) {
HDF_LOGE("Mp15xIwdgSetTimeout fail.");
return HDF_FAILURE;
}
// if need aotu feed, create a task
if (iwdg->auto_feed) {
ret = Mp15xIwdgCreateFeedDogTask(wdt);
if (ret != HDF_SUCCESS) {
HDF_LOGE("Mp15xIwdgCreateFeedDogTask fail, ret : %#x.", ret);
}
}
return HDF_SUCCESS;
}
static void Mp15xIwdgRelease(struct HdfDeviceObject *device)
{
struct WatchdogCntlr *wdt = NULL;
struct Mp15xIwdg *iwdg = NULL;
if (device == NULL) {
return;
}
wdt = WatchdogCntlrFromDevice(device);
if (wdt == NULL) {
return;
}
WatchdogCntlrRemove(wdt);
iwdg = (struct Mp15xIwdg *)wdt->priv;
if (iwdg->base != NULL) {
OsalIoUnmap((void *)iwdg->base);
iwdg->base = NULL;
}
OsalMemFree(iwdg);
}
struct HdfDriverEntry g_hdf_driver_iwdg_entry = {
.moduleVersion = 1,
.Bind = Mp15xIwdgBind,
.Init = Mp15xIwdgInit,
.Release = Mp15xIwdgRelease,
.moduleName = "stm32mp1_iwdg",
};
HDF_INIT(g_hdf_driver_iwdg_entry);
common/platform/libs/ohos/llvm/stm32mp157/libhdf_vendor_wifi.a
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common/platform/libs/ohos/llvm/stm32mp157/libhi3881.a
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common/platform/libs/ohos/llvm/stm32mp157/libltdc.a
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common/platform/libs/ohos/llvm/stm32mp157/libmmc.a
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common/platform/stm32mp1xx_hal/BUILD.gn
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# Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology Co., Ltd.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import("//drivers/adapter/khdf/liteos/hdf.gni")
module_name = "hdf_stm32mp1xx_hal"
hdf_driver(module_name) {
sources = [
"STM32MP1xx_HAL_Driver/Src/system_stm32mp1xx.c",
"STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c",
"STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_gpio.c",
"STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2c.c",
"STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c",
"STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ltdc.c",
"STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c",
"STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc_ex.c",
]
include_dirs = [
".",
"STM32MP1xx_HAL_Driver/Inc",
]
}
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/cmsis_compiler.h
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.00
* @date 22. Feb 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* ARM Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* ARM Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include "cmsis_iccarm.h"
/*
* TI ARM Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/cmsis_cp15.h
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/**************************************************************************//**
* @file cmsis_cp15.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.1
* @date 07. Sep 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_CP15_H
#define __CMSIS_CP15_H
/** \brief Get ACTLR
\return Auxiliary Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 1);
return(result);
}
/** \brief Set ACTLR
\param [in] actlr Auxiliary Control value to set
*/
__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
{
__set_CP(15, 0, actlr, 1, 0, 1);
}
/** \brief Get CPACR
\return Coprocessor Access Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 2);
return result;
}
/** \brief Set CPACR
\param [in] cpacr Coprocessor Access Control value to set
*/
__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
{
__set_CP(15, 0, cpacr, 1, 0, 2);
}
/** \brief Get DFSR
\return Data Fault Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
{
uint32_t result;
__get_CP(15, 0, result, 5, 0, 0);
return result;
}
/** \brief Set DFSR
\param [in] dfsr Data Fault Status value to set
*/
__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
{
__set_CP(15, 0, dfsr, 5, 0, 0);
}
/** \brief Get IFSR
\return Instruction Fault Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
{
uint32_t result;
__get_CP(15, 0, result, 5, 0, 1);
return result;
}
/** \brief Set IFSR
\param [in] ifsr Instruction Fault Status value to set
*/
__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
{
__set_CP(15, 0, ifsr, 5, 0, 1);
}
/** \brief Get ISR
\return Interrupt Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_ISR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 1, 0);
return result;
}
/** \brief Get CBAR
\return Configuration Base Address register value
*/
__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
{
uint32_t result;
__get_CP(15, 4, result, 15, 0, 0);
return result;
}
/** \brief Get TTBR0
This function returns the value of the Translation Table Base Register 0.
\return Translation Table Base Register 0 value
*/
__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
{
uint32_t result;
__get_CP(15, 0, result, 2, 0, 0);
return result;
}
/** \brief Set TTBR0
This function assigns the given value to the Translation Table Base Register 0.
\param [in] ttbr0 Translation Table Base Register 0 value to set
*/
__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
{
__set_CP(15, 0, ttbr0, 2, 0, 0);
}
/** \brief Get DACR
This function returns the value of the Domain Access Control Register.
\return Domain Access Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_DACR(void)
{
uint32_t result;
__get_CP(15, 0, result, 3, 0, 0);
return result;
}
/** \brief Set DACR
This function assigns the given value to the Domain Access Control Register.
\param [in] dacr Domain Access Control Register value to set
*/
__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
{
__set_CP(15, 0, dacr, 3, 0, 0);
}
/** \brief Set SCTLR
This function assigns the given value to the System Control Register.
\param [in] sctlr System Control Register value to set
*/
__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
{
__set_CP(15, 0, sctlr, 1, 0, 0);
}
/** \brief Get SCTLR
\return System Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 0);
return result;
}
/** \brief Set ACTRL
\param [in] actrl Auxiliary Control Register value to set
*/
__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
{
__set_CP(15, 0, actrl, 1, 0, 1);
}
/** \brief Get ACTRL
\return Auxiliary Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 1);
return result;
}
/** \brief Get MPIDR
This function returns the value of the Multiprocessor Affinity Register.
\return Multiprocessor Affinity Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
{
uint32_t result;
__get_CP(15, 0, result, 0, 0, 5);
return result;
}
/** \brief Get VBAR
This function returns the value of the Vector Base Address Register.
\return Vector Base Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 0, 0);
return result;
}
/** \brief Set VBAR
This function assigns the given value to the Vector Base Address Register.
\param [in] vbar Vector Base Address Register value to set
*/
__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
{
__set_CP(15, 0, vbar, 12, 0, 1);
}
#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
defined(DOXYGEN)
/** \brief Set CNTFRQ
This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
\param [in] value CNTFRQ Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
{
__set_CP(15, 0, value, 14, 0, 0);
}
/** \brief Get CNTFRQ
This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
\return CNTFRQ Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 0 , 0);
return result;
}
/** \brief Set CNTP_TVAL
This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
\param [in] value CNTP_TVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
{
__set_CP(15, 0, value, 14, 2, 0);
}
/** \brief Get CNTP_TVAL
This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
\return CNTP_TVAL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 2, 0);
return result;
}
/** \brief Get CNTPCT
This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
\return CNTPCT Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
{
uint64_t result;
__get_CP64(15, 0, result, 14);
return result;
}
/** \brief Set CNTP_CVAL
This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
\param [in] value CNTP_CVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
{
__set_CP64(15, 2, value, 14);
}
/** \brief Get CNTP_CVAL
This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
\return CNTP_CVAL Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
{
uint64_t result;
__get_CP64(15, 2, result, 14);
return result;
}
/** \brief Set CNTP_CTL
This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
\param [in] value CNTP_CTL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
{
__set_CP(15, 0, value, 14, 2, 1);
}
/** \brief Get CNTP_CTL register
\return CNTP_CTL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 2, 1);
return result;
}
#endif
/** \brief Set TLBIALL
TLB Invalidate All
*/
__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
{
__set_CP(15, 0, value, 8, 7, 0);
}
/** \brief Set BPIALL.
Branch Predictor Invalidate All
*/
__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 6);
}
/** \brief Set ICIALLU
Instruction Cache Invalidate All
*/
__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 0);
}
/** \brief Set DCCMVAC
Data cache clean
*/
__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 10, 1);
}
/** \brief Set DCIMVAC
Data cache invalidate
*/
__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 6, 1);
}
/** \brief Set DCCIMVAC
Data cache clean and invalidate
*/
__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 14, 1);
}
/** \brief Set CCSIDR
*/
__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
{
// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
__set_CP(15, 2, value, 0, 0, 0);
}
/** \brief Get CCSIDR
\return CCSIDR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
{
uint32_t result;
// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
__get_CP(15, 1, result, 0, 0, 0);
return result;
}
/** \brief Get CLIDR
\return CLIDR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
{
uint32_t result;
// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
__get_CP(15, 1, result, 0, 0, 1);
return result;
}
#endif
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/cmsis_gcc.h
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/**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.1
* @date 07. Sep 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_GCC_H
#define __CMSIS_GCC_H
/* ignore some GCC warnings */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
/* Fallback for __has_builtin */
#ifndef __has_builtin
#define __has_builtin(x) (0)
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE __attribute__((always_inline))
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
/* ########################## Core Instruction Access ######################### */
/**
\brief No Operation
*/
#define __NOP() __ASM volatile ("nop")
/**
\brief Wait For Interrupt
*/
#define __WFI() __ASM volatile ("wfi")
/**
\brief Wait For Event
*/
#define __WFE() __ASM volatile ("wfe")
/**
\brief Send Event
*/
#define __SEV() __ASM volatile ("sev")
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
__STATIC_FORCEINLINE void __ISB(void)
{
__ASM volatile ("isb 0xF":::"memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE void __DMB(void)
{
__ASM volatile ("dmb 0xF":::"memory");
}
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
// __ASM volatile ("rev %0, %1" : (__CMSIS_GCC_OUT_REG (result)) : (__CMSIS_GCC_USE_REG (value)) );
return result;
#endif
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
return result;
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (int16_t)__builtin_bswap16(value);
#else
int16_t result;
// __ASM volatile ("revsh %0, %1" : (__CMSIS_GCC_OUT_REG (result)): (__CMSIS_GCC_USE_REG (value)) );
return result;
#endif
}
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
op2 %= 32U;
if (op2 == 0U) {
return op1;
}
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
#else
int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
}
/**
\brief Count leading zeros
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __builtin_clz
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
__STATIC_FORCEINLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
__extension__ \
({ \
int32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/* ########################### Core Function Access ########################### */
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
return __builtin_arm_get_fpscr();
#else
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#endif
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
__builtin_arm_set_fpscr(fpscr);
#else
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
#endif
#else
(void)fpscr;
#endif
}
/** \brief Get CPSR Register
\return CPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
return(result);
}
/** \brief Set CPSR Register
\param [in] cpsr CPSR value to set
*/
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
{
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_FORCEINLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
/** \brief Get Stack Pointer
\return Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
return result;
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
{
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYS Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
{
uint32_t cpsr = __get_CPSR();
uint32_t result;
__ASM volatile(
"CPS #0x1F \n"
"MOV %0, sp " : "=r"(result) : : "memory"
);
__set_CPSR(cpsr);
__ISB();
return result;
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr = __get_CPSR();
__ASM volatile(
"CPS #0x1F \n"
"MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
);
__set_CPSR(cpsr);
__ISB();
}
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPEXC
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
__STATIC_FORCEINLINE int32_t log2_up(uint32_t n)
{
int32_t log = -1;
uint32_t t = n;
while(t)
{
log++; t >>=1;
}
/* if n not power of 2 -> round up*/
if ( n & (n - 1) ) log++;
return log;
}
__STATIC_INLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
{
register volatile uint32_t Dummy;
register volatile uint32_t ccsidr;
uint32_t num_sets;
uint32_t num_ways;
uint32_t shift_way;
uint32_t log2_linesize;
uint32_t log2_num_ways;
Dummy = level << 1;
/* set csselr, select ccsidr register */
__set_CCSIDR(Dummy);
/* get current ccsidr register */
ccsidr = __get_CCSIDR();
num_sets = ((ccsidr & 0x0FFFE000) >> 13) + 1;
num_ways = ((ccsidr & 0x00001FF8) >> 3) + 1;
log2_linesize = (ccsidr & 0x00000007) + 2 + 2;
log2_num_ways = log2_up(num_ways);
shift_way = 32 - log2_num_ways;
for(int way = num_ways-1; way >= 0; way--)
{
for(int set = num_sets-1; set >= 0; set--)
{
Dummy = (level << 1) | (set << log2_linesize) | (way << shift_way);
switch (maint)
{
case 0:
__ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(Dummy) : "memory"); // DCISW. Invalidate by Set/Way
break;
case 1:
__ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(Dummy) : "memory"); // DCCSW. Clean by Set/Way
break;
default:
__ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(Dummy) : "memory"); // DCCISW. Clean and Invalidate by Set/Way
break;
}
}
}
__DMB();
}
/** \brief Clean and Invalidate the entire data or unified cache
Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
*/
__STATIC_INLINE void __L1C_CleanInvalidateCache(uint32_t op)
{
register volatile uint32_t clidr;
uint32_t cache_type;
clidr = __get_CLIDR();
for(uint32_t i = 0; i<7; i++)
{
cache_type = (clidr >> i*3) & 0x7UL;
if ((cache_type >= 2) && (cache_type <= 4))
{
__L1C_MaintainDCacheSetWay(i, op);
}
}
}
/** \brief Enable Floating Point Unit
Critical section, called from undef handler, so systick is disabled
*/
__STATIC_INLINE void __FPU_Enable(void)
{
__ASM volatile(
//Permit access to VFP/NEON, registers by modifying CPACR
" MRC p15,0,R1,c1,c0,2 \n"
" ORR R1,R1,#0x00F00000 \n"
" MCR p15,0,R1,c1,c0,2 \n"
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
" ISB \n"
//Enable VFP/NEON
" VMRS R1,FPEXC \n"
" ORR R1,R1,#0x40000000 \n"
" VMSR FPEXC,R1 \n"
//Initialise VFP/NEON registers to 0
" MOV R2,#0 \n"
//Initialise D16 registers to 0
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
" VMOV D3, R2,R2 \n"
" VMOV D4, R2,R2 \n"
" VMOV D5, R2,R2 \n"
" VMOV D6, R2,R2 \n"
" VMOV D7, R2,R2 \n"
" VMOV D8, R2,R2 \n"
" VMOV D9, R2,R2 \n"
" VMOV D10,R2,R2 \n"
" VMOV D11,R2,R2 \n"
" VMOV D12,R2,R2 \n"
" VMOV D13,R2,R2 \n"
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"
#if __ARM_NEON == 1
//Initialise D32 registers to 0
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
" VMOV D19,R2,R2 \n"
" VMOV D20,R2,R2 \n"
" VMOV D21,R2,R2 \n"
" VMOV D22,R2,R2 \n"
" VMOV D23,R2,R2 \n"
" VMOV D24,R2,R2 \n"
" VMOV D25,R2,R2 \n"
" VMOV D26,R2,R2 \n"
" VMOV D27,R2,R2 \n"
" VMOV D28,R2,R2 \n"
" VMOV D29,R2,R2 \n"
" VMOV D30,R2,R2 \n"
" VMOV D31,R2,R2 \n"
#endif
//Initialise FPSCR to a known state
" VMRS R2,FPSCR \n"
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
" AND R2,R2,R3 \n"
" VMSR FPSCR,R2 "
);
}
#pragma GCC diagnostic pop
#endif /* __CMSIS_GCC_H */
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/core_ca.h
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common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp157axx_ca7.h
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common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx.h
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/**
******************************************************************************
* @file stm32mp1xx.h
* @author MCD Application Team
* @brief CMSIS STM32MP1xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32MP1xx device used in the target application
* - To use or not the peripheral�s drivers in application code(i.e.
* code will be based on direct access to peripheral�s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
#ifndef __STM32MP1xx_H
#define __STM32MP1xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include "stm32mp157axx_ca7.h"
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32MP1xx_H */
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h
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/**
******************************************************************************
* @file stm32mp1xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32MP1xx_HAL_H
#define STM32MP1xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal_conf.h"
#include "core_ca.h"
#include <stddef.h>
/** @addtogroup STM32MP1xx_HAL_Driver
* @{
*/
/** @addtogroup HAL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Types HAL Exported Types
* @{
*/
/** @defgroup HAL_Exported_Types_Group1 Tick Frequency
* @{
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/**
* @}
*/
/** @defgroup HAL_Exported_Types_Group2 HDP SW Signal
* @{
*/
/**
* @brief HDP SW Signal SET and Bit RESET enumeration
*/
typedef enum
{
HDP_SW_SIGNAL_RESET = 0,
HDP_SW_SIGNAL_SET
}HDP_SwSignalState;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup HAL_Exported_Constants_Group1 SYSCFG VREFBUF Voltage Scale
* @{
*/
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 0 (VREF_OUT2) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 1 (VREF_OUT1) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 2 (VREF_OUT4) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 3 (VREF_OUT3) */
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
/**
* @}
*/
/** @defgroup HAL_Exported_Constants_Group2 SYSCFG VREFBUF High Impedance
* @{
*/
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
/**
* @}
*/
/** @defgroup HAL_Exported_Constants_Group3 SYSCFG Ethernet Config
* @{
*/
#define SYSCFG_ETH_MII SYSCFG_PMCSETR_ETH_SELMII_SEL /*!< Select the Media Independent Interface */
#define SYSCFG_ETH_GMII ((uint32_t)0x00000000) /*!< Select the Gigabit Media Independent Interface */
#define SYSCFG_ETH_RMII SYSCFG_PMCSETR_ETH_SEL_2 /*!< Select the Reduced Media Independent Interface */
#define SYSCFG_ETH_RGMII SYSCFG_PMCSETR_ETH_SEL_0 /*!< Select the Reduced Gigabit Media Independent Interface */
#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || \
((CONFIG) == SYSCFG_ETH_RMII) || \
((CONFIG) == SYSCFG_ETH_GMII) || \
((CONFIG) == SYSCFG_ETH_RGMII))
/**
* @}
*/
/** @defgroup HAL_Exported_Constants_Group4 SYSCFG Analog Switch Config
* @{
*/
#define SYSCFG_SWITCH_PA0 SYSCFG_PMCSETR_ANA0_SEL_SEL /*!< Select PA0 analog switch */
#define SYSCFG_SWITCH_PA1 SYSCFG_PMCSETR_ANA1_SEL_SEL /*!< Select PA1 analog switch */
#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
(((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1))
#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCSETR_ANA0_SEL_SEL /*!< PA0 analog switch opened */
#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */
#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCSETR_ANA1_SEL_SEL /*!< PA1 analog switch opened */
#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/
#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \
(((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \
(((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \
(((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE))
/**
* @}
*/
/** @defgroup HAL_Exported_Constants_Group5 SYSCFG IOCompenstionCell Config
* @{
*/
#define SYSCFG_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */
#define SYSCFG_REGISTER_CODE SYSCFG_CMPCR_SW_CTRL /*!< Code from the SYSCFG compensation cell code register */
#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \
((SELECT) == SYSCFG_REGISTER_CODE))
#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10))
/**
* @}
*/
/** @defgroup HAL_Exported_Constants_Group6 SYSCFG IOControl HighSpeed Config
* @{
*/
#define SYSCFG_HIGHSPEED_TRACE_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_TRACE /*!< High Speed Low Voltage Pad mode Enable when a TRACEx signal is selected in AFMUX */
#define SYSCFG_HIGHSPEED_QUADSPI_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI /*!< High Speed Low Voltage Pad mode Enable when a QUADSPI_x signal is selected in AFMUX */
#define SYSCFG_HIGHSPEED_ETH_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_ETH /*!< High Speed Low Voltage Pad mode Enable when a ETH_x signal is selected in AFMUX */
#define SYSCFG_HIGHSPEED_SDMMC_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_SDMMC /*!< High Speed Low Voltage Pad mode Enable when a SDMMCy_x signal is selected in AFMUX */
#define SYSCFG_HIGHSPEED_SPI_SIGNAL SYSCFG_IOCTRLSETR_HSLVEN_SPI /*!< High Speed Low Voltage Pad mode Enable when a SPIy_x signal is selected in AFMUX */
/**
* @}
*/
/** @defgroup HAL_Exported_Constants_Group7 HDP Software signal define
* @{
*/
#define HDP_SW_SIGNAL_0 ((uint8_t)0x01U) /* HDP Software signal 0 selected */
#define HDP_SW_SIGNAL_1 ((uint8_t)0x02U) /* HDP Software signal 1 selected */
#define HDP_SW_SIGNAL_2 ((uint8_t)0x04U) /* HDP Software signal 2 selected */
#define HDP_SW_SIGNAL_3 ((uint8_t)0x08U) /* HDP Software signal 3 selected */
#define HDP_SW_SIGNAL_4 ((uint8_t)0x10U) /* HDP Software signal 4 selected */
#define HDP_SW_SIGNAL_5 ((uint8_t)0x20U) /* HDP Software signal 5 selected */
#define HDP_SW_SIGNAL_6 ((uint8_t)0x40U) /* HDP Software signal 6 selected */
#define HDP_SW_SIGNAL_7 ((uint8_t)0x80U) /* HDP Software signal 7 selected */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
* @{
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#if defined (CORE_CM4)
#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM12_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM12_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM13_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM13_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM14_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_TIM14_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG1() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG1() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_I2C1_STOP)
#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_I2C2_STOP)
#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_I2C3_STOP)
#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_I2C5_STOP)
#define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C5_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZ2, DBGMCU_APB1_FZ_DBG_I2C5_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM1_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM8_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM15_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM16_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_TIM17_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
#define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
#define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB2FZ2, DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
#endif
#if defined(DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
#endif
#if defined(DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
#endif
#if defined(DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
#endif
#if defined(DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZ2, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
#endif
#if defined(DBGMCU_APB5_FZ_DBG_I2C4_STOP)
#define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C4_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C4_STOP)
#endif
#if defined(DBGMCU_APB5_FZ_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_RTC_STOP)
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_RTC_STOP)
#endif
#if defined(DBGMCU_APB5_FZ_DBG_I2C6_STOP)
#define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C6_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB5FZ2, DBGMCU_APB5_FZ_DBG_I2C6_STOP)
#endif
#elif defined(CORE_CA7)
#if defined(DBGMCU_APB4_FZ_DBG_IWDG2_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG2() SET_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4_FZ_DBG_IWDG2_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG2() CLEAR_BIT(DBGMCU->APB4FZ1, DBGMCU_APB4_FZ_DBG_IWDG2_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM5_STOP)
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM12_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM12_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM13_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM13_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM14_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_TIM14_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG1() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG1() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_WWDG1_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_I2C1_STOP)
#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C1_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_I2C2_STOP)
#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C2_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_I2C3_STOP)
#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C3_STOP)
#endif
#if defined(DBGMCU_APB1_FZ_DBG_I2C5_STOP)
#define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C5_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZ1, DBGMCU_APB1_FZ_DBG_I2C5_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM1_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM8_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM15_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM16_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_TIM17_STOP)
#endif
#if defined(DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
#define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
#define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB2FZ1, DBGMCU_APB2_FZ_DBG_FDCAN_STOP)
#endif
#if defined(DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM2_STOP)
#endif
#if defined(DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM3_STOP)
#endif
#if defined(DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM4_STOP)
#endif
#if defined(DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZ1, DBGMCU_APB3_FZ_DBG_LPTIM5_STOP)
#endif
#if defined(DBGMCU_APB5_FZ_DBG_I2C4_STOP)
#define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C4_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C4_STOP)
#endif
#if defined(DBGMCU_APB5_FZ_DBG_IWDG1_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG1() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_IWDG1_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG1() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_IWDG1_STOP)
#endif
#if defined(DBGMCU_APB5_FZ_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_RTC_STOP)
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_RTC_STOP)
#endif
#if defined(DBGMCU_APB5_FZ_DBG_I2C6_STOP)
#define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C6_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB5FZ1, DBGMCU_APB5_FZ_DBG_I2C6_STOP)
#endif
#endif
/**
* @}
*/
/** @defgroup HDP_Exported_Macros HDP Exported Macros
* @{
*/
/** @addtogroup HDP_Enable
* @{
*/
#define __HAL_HDP_ENABLE() SET_BIT(HDP->HDP_CTRL, HDP_CTRL_EN)
/**
* @}
*/
/** @addtogroup HDP_Configure_SW_Programmable_Signals
* @{
*/
/** @brief This macros allows atomic write of HDP_GPOVAL register
It uses HDP_GPOSET and HDP_GPOCLR regsiters to toogle
*
* @param __HDP_SW_Signal__: specifies the sw signal bit to be written.
* This parameter can be one of HDP_SW_SIGNAL_x(s) where x can be (0..7).
* @param __HDP_SwSignalState__: specifies the value to be written to the selected bit.
* This parameter can be one of the HDP_SwSignalState enum values:
* @arg HDP_SW_SIGNAL_RESET: to clear the signal pin
* @arg HDP_SW_SIGNAL_SET: to set the signal pin
*/
#define __HAL_HDP_ATOMIC_WRITE_GPOVAL(__HDP_SW_Signal__, __HDP_SwSignalState__) \
do { \
if ((__HDP_SwSignalState__) != HDP_SW_SIGNAL_RESET) \
{ \
WRITE_REG(HDP->HDP_GPOSET, (uint8_t)(__HDP_SW_Signal__)); \
} \
else \
{ \
WRITE_REG(HDP->HDP_GPOCLR, (uint8_t)(__HDP_SW_Signal__)); \
} \
} while(0)
/** @brief This macros allows non-atomic write of HDP_GPOVAL register
*
* @param __GPOValue__: specifies the value to set in HDP_GPOVAL register
*
*/
#define __HAL_HDP_NON_ATOMIC_WRITE_GPOVAL(__GPOValue__) WRITE_REG(HDP->HDP_GPOVAL, (uint8_t)(__GPOValue__))
/** @brief This macros returns value of HDP_GPOVAL register
*
* @retval the value to set in HDP_GPOVAL register
*/
#define __HAL_HDP_READ_GPOVAL() READ_REG(HDP->HDP_GPOVAL)
/**
* @}
*/
/** @addtogroup HDP0_MUX0_Config
* @{
*/
#define __HAL_HDP0_SELECT_PWR_PWRWAKE_SYS() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) 0x00000000))
#define __HAL_HDP0_SELECT_CM4_SLEEPDEEP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_0))
#define __HAL_HDP0_SELECT_PWR_STDBY_WKUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_1))
#define __HAL_HDP0_SELECT_PWR_ENCOMP_VDDCORE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_1 | HDP_MUX_MUX0_0))
#define __HAL_HDP0_SELECT_BSEC_OUT_SEC_NIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_2))
#define __HAL_HDP0_SELECT_RCC_CM4_SLEEPDEEP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_2 | HDP_MUX_MUX0_1))
#define __HAL_HDP0_SELECT_GPU_DBG7() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_2 | HDP_MUX_MUX0_1 | HDP_MUX_MUX0_0))
#define __HAL_HDP0_SELECT_DDRCTRL_IP_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_3))
#define __HAL_HDP0_SELECT_PWR_DDR_RET_ENABLE_N() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_3 | HDP_MUX_MUX0_0))
#define __HAL_HDP0_SELECT_GPOVAL_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX0, ((uint32_t) HDP_MUX_MUX0_3 | HDP_MUX_MUX0_2 | HDP_MUX_MUX0_1 | HDP_MUX_MUX0_0))
/**
* @}
*/
/** @addtogroup HDP1_MUX1_Config
* @{
*/
#define __HAL_HDP1_SELECT_PWR_PWRWAKE_MCU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) 0x00000000))
#define __HAL_HDP1_SELECT_CM4_HALTED() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_0))
#define __HAL_HDP1_SELECT_CA7_nAXIERRIRQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_1))
#define __HAL_HDP1_SELECT_PWR_OKIN_MR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_1 | HDP_MUX_MUX1_0))
#define __HAL_HDP1_SELECT_BSEC_OUT_SEC_DBGEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2))
#define __HAL_HDP1_SELECT_EXTI_SYS_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2 | HDP_MUX_MUX1_0))
#define __HAL_HDP1_SELECT_RCC_PWRDS_MPU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2 | HDP_MUX_MUX1_1))
#define __HAL_HDP1_SELECT_GPU_DBG6() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_2 | HDP_MUX_MUX1_1 | HDP_MUX_MUX1_0))
#define __HAL_HDP1_SELECT_DDRCTRL_DFI_CTRLUPD_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_3))
#define __HAL_HDP1_SELECT_DDRCTRL_CACTIVE_DDRC_ASR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_3 | HDP_MUX_MUX1_0))
#define __HAL_HDP1_SELECT_GPOVAL_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX1, ((uint32_t) HDP_MUX_MUX1_3 | HDP_MUX_MUX1_2 | HDP_MUX_MUX1_1 | HDP_MUX_MUX1_0))
/**
* @}
*/
/** @addtogroup HDP2_MUX2_Config
* @{
*/
#define __HAL_HDP2_SELECT_PWR_PWRWAKE_MPU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) 0x00000000))
#define __HAL_HDP2_SELECT_CM4_RXEV() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_0))
#define __HAL_HDP2_SELECT_CA7_nPMUIRQ1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_1))
#define __HAL_HDP2_SELECT_CA7_nFIQOUT1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_1 | HDP_MUX_MUX2_0))
#define __HAL_HDP2_SELECT_BSEC_IN_RSTCORE_n() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2))
#define __HAL_HDP2_SELECT_EXTI_C2_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2 | HDP_MUX_MUX2_0))
#define __HAL_HDP2_SELECT_RCC_PWRDS_MCU() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2 | HDP_MUX_MUX2_1))
#define __HAL_HDP2_SELECT_GPU_DBG5() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_2 | HDP_MUX_MUX2_1 | HDP_MUX_MUX2_0))
#define __HAL_HDP2_SELECT_DDRCTRL_DFI_INIT_COMPLETE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3))
#define __HAL_HDP2_SELECT_DDRCTRL_PERF_OP_IS_REFRESH() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3 | HDP_MUX_MUX2_0))
#define __HAL_HDP2_SELECT_DDRCTRL_GSKP_DFI_LP_REQ() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3 | HDP_MUX_MUX2_1))
#define __HAL_HDP2_SELECT_GPOVAL_2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX2, ((uint32_t) HDP_MUX_MUX2_3 | HDP_MUX_MUX2_2 | HDP_MUX_MUX2_1 | HDP_MUX_MUX2_0))
/**
* @}
*/
/** @addtogroup HDP3_MUX3_Config
* @{
*/
#define __HAL_HDP3_SELECT_PWR_SEL_VTH_VDD_CORE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) 0x00000000))
#define __HAL_HDP3_SELECT_CM4_TXEV() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_0))
#define __HAL_HDP3_SELECT_CA7_nPMUIRQ0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_1))
#define __HAL_HDP3_SELECT_CA7_nFIQOUT0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_1 | HDP_MUX_MUX3_0))
#define __HAL_HDP3_SELECT_BSEC_OUT_SEC_DFTLOCK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2))
#define __HAL_HDP3_SELECT_EXTI_C1_WAKEUP() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2 | HDP_MUX_MUX3_0))
#define __HAL_HDP3_SELECT_RCC_PWRDS_SYS() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2 | HDP_MUX_MUX3_1))
#define __HAL_HDP3_SELECT_GPU_DBG4() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_2 | HDP_MUX_MUX3_1 | HDP_MUX_MUX3_0))
#define __HAL_HDP3_SELECT_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_3))
#define __HAL_HDP3_SELECT_DDRCTRL_CACTIVE_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_3 | HDP_MUX_MUX3_0))
#define __HAL_HDP3_SELECT_GPOVAL_3() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX3, ((uint32_t) HDP_MUX_MUX3_3 | HDP_MUX_MUX3_2 | HDP_MUX_MUX3_1 | HDP_MUX_MUX3_0))
/**
* @}
*/
/** @addtogroup HDP4_MUX4_Config
* @{
*/
#define __HAL_HDP4_SELECT_PWR_MPUCR() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) 0x00000000))
#define __HAL_HDP4_SELECT_CM4_SLEEPING() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_0))
#define __HAL_HDP4_SELECT_CA7_nRESET1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_1))
#define __HAL_HDP4_SELECT_CA7_nIRQOUT1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_1 | HDP_MUX_MUX4_0))
#define __HAL_HDP4_SELECT_BSEC_OUT_SEC_DFTEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2))
#define __HAL_HDP4_SELECT_BSEC_OUT_SEC_DBGSWENABLE() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2 | HDP_MUX_MUX4_0))
#define __HAL_HDP4_SELECT_ETH_OUT_PMT_INTR_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2 | HDP_MUX_MUX4_1))
#define __HAL_HDP4_SELECT_GPU_DBG3() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_2 | HDP_MUX_MUX4_1 | HDP_MUX_MUX4_0))
#define __HAL_HDP4_SELECT_DDRCTRL_STAT_DDRC_REG_SELREF_TYPE_1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_3))
#define __HAL_HDP4_SELECT_DDRCTRL_CACTIVE_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_3 | HDP_MUX_MUX4_0))
#define __HAL_HDP4_SELECT_GPOVAL_4() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX4, ((uint32_t) HDP_MUX_MUX4_3 | HDP_MUX_MUX4_2 | HDP_MUX_MUX4_1 | HDP_MUX_MUX4_0))
/**
* @}
*/
/** @addtogroup HDP5_MUX5_Config
* @{
*/
#define __HAL_HDP5_SELECT_CA7_STANDBYWFIL2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) 0x00000000))
#define __HAL_HDP5_SELECT_PWR_VTH_VDDCORE_ACK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_0))
#define __HAL_HDP5_SELECT_CA7_nRESET0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_1))
#define __HAL_HDP5_SELECT_CA7_nIRQOUT0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_1 | HDP_MUX_MUX5_0))
#define __HAL_HDP5_SELECT_BSEC_IN_PWROK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2))
#define __HAL_HDP5_SELECT_BSEC_OUT_SEC_DEVICEEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2 | HDP_MUX_MUX5_0))
#define __HAL_HDP5_SELECT_ETH_OUT_LPI_INTR_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2 | HDP_MUX_MUX5_1))
#define __HAL_HDP5_SELECT_GPU_DBG2() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_2 | HDP_MUX_MUX5_1 | HDP_MUX_MUX5_0))
#define __HAL_HDP5_SELECT_DDRCTRL_CACTIVE_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_3))
#define __HAL_HDP5_SELECT_DDRCTRL_WR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_3 | HDP_MUX_MUX5_0)))
#define __HAL_HDP5_SELECT_GPOVAL_5() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX5, ((uint32_t) HDP_MUX_MUX5_3 | HDP_MUX_MUX5_2 | HDP_MUX_MUX5_1 | HDP_MUX_MUX5_0))
/**
* @}
*/
/** @addtogroup HDP6_MUX6_Config
* @{
*/
#define __HAL_HDP6_SELECT_CA7_STANDBYWFI1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) 0x00000000))
#define __HAL_HDP6_SELECT_CA7_STANDBYWFE1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_0))
#define __HAL_HDP6_SELECT_CA7_EVENTO() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_1))
#define __HAL_HDP6_SELECT_CA7_DBGACK1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_1 | HDP_MUX_MUX6_0))
#define __HAL_HDP6_SELECT_BSEC_OUT_SEC_SPNIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_2 | HDP_MUX_MUX6_0))
#define __HAL_HDP6_SELECT_ETH_OUT_MAC_SPEED_O1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_2 | HDP_MUX_MUX6_1))
#define __HAL_HDP6_SELECT_GPU_DBG1() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_2 | HDP_MUX_MUX6_1 | HDP_MUX_MUX6_0))
#define __HAL_HDP6_SELECT_DDRCTRL_CSYSACK_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_3))
#define __HAL_HDP6_SELECT_DDRCTRL_LPR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_3 | HDP_MUX_MUX6_0))
#define __HAL_HDP6_SELECT_GPOVAL_6() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX6, ((uint32_t) HDP_MUX_MUX6_3 | HDP_MUX_MUX6_2 | HDP_MUX_MUX6_1 | HDP_MUX_MUX6_0))
/**
* @}
*/
/** @addtogroup HDP7_MUX7_Config
* @{
*/
#define __HAL_HDP7_SELECT_CA7_STANDBYWFI0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) 0x00000000))
#define __HAL_HDP7_SELECT_CA7_STANDBYWFE0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_0))
#define __HAL_HDP7_SELECT_CA7_DBGACK0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_1 | HDP_MUX_MUX7_0))
#define __HAL_HDP7_SELECT_BSEC_OUT_FUSE_OK() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2))
#define __HAL_HDP7_SELECT_BSEC_OUT_SEC_SPIDEN() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2 | HDP_MUX_MUX7_0))
#define __HAL_HDP7_SELECT_ETH_OUT_MAC_SPEED_O0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2 | HDP_MUX_MUX7_1))
#define __HAL_HDP7_SELECT_GPU_DBG0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_2 | HDP_MUX_MUX7_1 | HDP_MUX_MUX7_0))
#define __HAL_HDP7_SELECT_DDRCTRL_CSYSREQ_DDRC() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_3))
#define __HAL_HDP7_SELECT_DDRCTRL_HPR_CREDIT_CNT_4_0() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_3 | HDP_MUX_MUX7_0))
#define __HAL_HDP7_SELECT_GPOVAL_7() MODIFY_REG(HDP->HDP_MUX, HDP_MUX_MUX7, ((uint32_t) HDP_MUX_MUX7_3 | HDP_MUX_MUX7_2 | HDP_MUX_MUX7_1 | HDP_MUX_MUX7_0))
/**
* @}
*/
/**
* @}
*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/* Initialization and de-initialization functions ******************************/
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
void HAL_EnableDBGWakeUp(void);
void HAL_DisableDBGWakeUp(void);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
void HAL_SYSCFG_EnableBOOST(void);
void HAL_SYSCFG_DisableBOOST(void);
void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
void HAL_SYSCFG_EnableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal);
void HAL_SYSCFG_DisableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal);
void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
void HAL_EnableDBGSleepMode(void);
void HAL_DisableDBGSleepMode(void);
void HAL_EnableDBGStopMode(void);
void HAL_DisableDBGStopMode(void);
void HAL_EnableDBGStandbyMode(void);
void HAL_DisableDBGStandbyMode(void);
void HAL_EnableDBGWakeUp(void);
void HAL_DisableDBGWakeUp(void);
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32MP1xx_HAL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_conf.h
Executable
+391
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@@ -0,0 +1,391 @@
/**
******************************************************************************
* @file stm32mp1xx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32mp1xx_hal_conf.h.
******************************************************************************
*
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32MP1xx_HAL_CONF_H
#define __STM32MP1xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define CORE_CA7
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_CEC_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */
/*#define HAL_DSI_MODULE_ENABLED */
/*#define HAL_DFSDM_MODULE_ENABLED */
/*#define HAL_ETH_MODULE_ENABLED */
/*#define HAL_FDCAN_MODULE_ENABLED */
/*#define HAL_HASH_MODULE_ENABLED */
/*#define HAL_HSEM_MODULE_ENABLED */
/*#define HAL_HCD_MODULE_ENABLED */
#define HAL_I2C_MODULE_ENABLED
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IPCC_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
#define HAL_LTDC_MODULE_ENABLED
/*#define HAL_NAND_MODULE_ENABLED */
/*#define HAL_NOR_MODULE_ENABLED */
/*#define HAL_PCD_MODULE_ENABLED */
/*#define HAL_QSPI_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_SAI_MODULE_ENABLED */
/*#define HAL_SD_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_SPDIFRX_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */
/*#define HAL_TAMP_MODULE_ENABLED */
/*#define HAL_TIM_MODULE_ENABLED */
/*#define HAL_TMPSENS_MODULE_ENABLED */
/*#define HAL_UART_MODULE_ENABLED */
/*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
#define HAL_EXTI_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
/*#define HAL_DMA_MODULE_ENABLED */
/*#define HAL_MDMA_MODULE_ENABLED */
#define HAL_RCC_MODULE_ENABLED
/*#define HAL_PWR_MODULE_ENABLED */
/*#define HAL_CORTEX_MODULE_ENABLED */
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)24000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Time out for HSI start up value in ms.
*/
#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT 5000U /*!< Time out for HSI start up, in ms */
#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSE) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
/**
* @brief Time out for LSE start up value in ms.
*/
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief Internal oscillator (CSI) default value.
* This value is the default CSI value after Reset.
*/
#if !defined (CSI_VALUE)
#define CSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE 3300U /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY 0U /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 0U
#define INSTRUCTION_CACHE_ENABLE 0U
#define DATA_CACHE_ENABLE 0U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32mp1xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_HSEM_MODULE_ENABLED
#include "stm32mp1xx_hal_hsem.h"
#endif /* HAL_HSEM_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32mp1xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32mp1xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_MDMA_MODULE_ENABLED
#include "stm32mp1xx_hal_mdma.h"
#endif /* HAL_MDMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32mp1xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32mp1xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32mp1xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32mp1xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32mp1xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32mp1xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32mp1xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32mp1xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_DSI_MODULE_ENABLED
#include "stm32mp1xx_hal_dsi.h"
#endif /* HAL_DSI_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32mp1xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32mp1xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_FDCAN_MODULE_ENABLED
#include "stm32mp1xx_hal_fdcan.h"
#endif /* HAL_FDCAN_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32mp1xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32mp1xx_hal_hcd.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32mp1xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32mp1xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IPCC_MODULE_ENABLED
#include "stm32mp1xx_hal_ipcc.h"
#endif /* HAL_IPCC_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32mp1xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32mp1xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32mp1xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32mp1xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32mp1xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32mp1xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32mp1xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32mp1xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32mp1xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32mp1xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32mp1xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32mp1xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32mp1xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32mp1xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32mp1xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32mp1xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32mp1xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32mp1xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_TAMP_MODULE_ENABLED
#include "stm32mp1xx_hal_tamp.h"
#endif /* HAL_TAMP_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32mp1xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TMPSENS_MODULE_ENABLED
#include "stm32mp1xx_hal_tmpsens.h"
#endif /* HAL_TMPSENS_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32mp1xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32mp1xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32mp1xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32MP1xx_HAL_CONF_H */
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_def.h
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/**
******************************************************************************
* @file stm32mp1xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32MP1xx_HAL_DEF
#define STM32MP1xx_HAL_DEF
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx.h"
#include <stdio.h>
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macros -----------------------------------------------------------*/
//#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0U)
/** @brief Reset the Handle's State field.
* @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
#if (USE_RTOS == 1U)
/* Reserved for future use */
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0U)
#endif /* USE_RTOS */
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4U)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4U)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM )
/* ARM Compiler
------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#ifdef __cplusplus
}
#endif
#endif /* STM32MP1xx_HAL_DEF */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h
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/**
******************************************************************************
* @file stm32mp1xx_hal_exti.h
* @author MCD Application Team
* @brief Header file of EXTI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32MP1xx_HAL_EXTI_H
#define STM32MP1xx_HAL_EXTI_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal_def.h"
/** @addtogroup STM32MP1xx_HAL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00U,
HAL_EXTI_RISING_CB_ID = 0x01U,
HAL_EXTI_FALLING_CB_ID = 0x02U,
} EXTI_CallbackIDTypeDef;
/**
* @brief EXTI Handle structure definition
*/
typedef struct
{
uint32_t Line; /*!< Exti line number */
void (* RisingCallback)(void); /*!< Exti rising callback */
void (* FallingCallback)(void); /*!< Exti falling callback */
} EXTI_HandleTypeDef;
/**
* @brief EXTI Configuration structure definition
*/
typedef struct
{
uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x00u) /* EXTI_GPIO */
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x01u) /* EXTI_GPIO */
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x02u) /* EXTI_GPIO */
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x03u) /* EXTI_GPIO */
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x04u) /* EXTI_GPIO */
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x05u) /* EXTI_GPIO */
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x06u) /* EXTI_GPIO */
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x07u) /* EXTI_GPIO */
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x08u) /* EXTI_GPIO */
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x09u) /* EXTI_GPIO */
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Au) /* EXTI_GPIO */
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Bu) /* EXTI_GPIO */
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Cu) /* EXTI_GPIO */
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Du) /* EXTI_GPIO */
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Eu) /* EXTI_GPIO */
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_EVENT | EXTI_REG1 | 0x0Fu) /* EXTI_GPIO */
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u) /* PVD and AVD */
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x11u) /* RTC timestamp and SecureError wakeup */
#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x12u) /* TAMP tamper and SecureError wakeup */
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG1 | 0x13u) /* RTC Wakeup timer and Alarms (A and B) and SecureError wakeup */
#define EXTI_LINE_20 (EXTI_RESERVED | | EXTI_REG1 | 0x14u) /* RESERVED */
#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15u) /* I2C1 wakeup */
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16u) /* I2C2 wakeup */
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u) /* I2C3 wakeup */
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u) /* I2C4 wakeup */
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u) /* I2C5 wakeup */
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au) /* USART1 wakeup */
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu) /* USART2 wakeup */
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu) /* USART3 wakeup */
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1Du) /* USART6 wakeup */
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1Eu) /* UART4 wakeup */
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1Fu) /* UART5 wakeup */
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00u) /* UART7 wakeup */
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01u) /* UART8 wakeup */
#define EXTI_LINE_34 (EXTI_RESERVED | EXTI_REG2 | 0x02u) /* RESERVED */
#define EXTI_LINE_35 (EXTI_RESERVED | EXTI_REG2 | 0x03u) /* RESERVED */
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u) /* SPI1 wakeup */
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u) /* SPI2 wakeup */
#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06u) /* SPI3 wakeup */
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07u) /* SPI4 wakeup */
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | 0x08u) /* SPI5 wakeup */
#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_REG2 | 0x09u) /* SPI6 wakeup */
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au) /* MDIOS wakeup */
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu) /* USBH wakeup */
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu) /* OTG wakeup */
#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du) /* IWDG1 early wake */
#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu) /* IWDG1 early wake */
#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_REG2 | 0x0Fu) /* LPTIM1 wakeup */
#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10u) /* LPTIM2 wakeup */
#define EXTI_LINE_49 (EXTI_RESERVED | EXTI_REG2 | 0x11u) /* RESERVED */
#define EXTI_LINE_50 (EXTI_DIRECT | EXTI_REG2 | 0x12u) /* LPTIM3 wakeup */
#define EXTI_LINE_51 (EXTI_RESERVED | EXTI_REG2 | 0x13u) /* RESERVED */
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_REG2 | 0x14u) /* LPTIM4 wakeup */
#define EXTI_LINE_53 (EXTI_DIRECT | EXTI_REG2 | 0x15u) /* LPTIM5 wakeup */
#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_REG2 | 0x16u) /* I2C6 wakeup */
#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_REG2 | 0x17u) /* WKUP1 wakeup */
#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_REG2 | 0x18u) /* WKUP2 wakeup */
#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | 0x19u) /* WKUP3 wakeup */
#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_REG2 | 0x1Au) /* WKUP4 wakeup */
#define EXTI_LINE_59 (EXTI_DIRECT | EXTI_REG2 | 0x1Bu) /* WKUP5 wakeup */
#define EXTI_LINE_60 (EXTI_DIRECT | EXTI_REG2 | 0x1Cu) /* WKUP6 wakeup */
#define EXTI_LINE_61 (EXTI_DIRECT | EXTI_REG2 | 0x1Du) /* IPCC interrupt CPU1 */
#define EXTI_LINE_62 (EXTI_DIRECT | EXTI_REG2 | 0x1Eu) /* IPCC interrupt CPU2 */
#define EXTI_LINE_63 (EXTI_DIRECT | EXTI_REG2 | 0x1Fu) /* HSEM_IT1 interrupt */
#define EXTI_LINE_64 (EXTI_DIRECT | EXTI_REG3 | 0x00u) /* HSEM_IT2 interrupt */
#define EXTI_LINE_65 (EXTI_CONFIG | EXTI_REG3 | 0x01u) /* CPU2 SEV interrupt */
#define EXTI_LINE_66 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG3 | 0x02u) /* CPU1 SEV interrupt */
#define EXTI_LINE_67 (EXTI_RESERVED | EXTI_REG3 | 0x03u) /* RESERVED */
#define EXTI_LINE_68 (EXTI_CONFIG | EXTI_REG3 | 0x04u) /* WWDG1 reset */
#define EXTI_LINE_69 (EXTI_DIRECT | EXTI_REG3 | 0x05u) /* HDMI CEC wakeup */
#define EXTI_LINE_70 (EXTI_DIRECT | EXTI_REG3 | 0x06u) /* ETH1 pmt_intr_o wakeup */
#define EXTI_LINE_71 (EXTI_DIRECT | EXTI_REG3 | 0x07u) /* ETH1 lpi_intr_o wakeup */
#define EXTI_LINE_72 (EXTI_DIRECT | EXTI_REG3 | 0x08u) /* DTS wakeup */
#define EXTI_LINE_73 (EXTI_CONFIG | EXTI_REG3 | 0x09u) /* CPU2 SYSRESETREQ local CPU2 reset */
#define EXTI_LINE_74 (EXTI_RESERVED | EXTI_REG3 | 0x0Au) /* RESERVED */
#define EXTI_LINE_75 (EXTI_DIRECT | EXTI_REG3 | 0x0Bu) /* CDBGPWRUPREQ event */
/**
* @}
*/
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
#define EXTI_MODE_C1_NONE 0x00000010u
#define EXTI_MODE_C1_INTERRUPT 0x00000011u
#define EXTI_MODE_C1_EVENT 0x00000012u
#define EXTI_MODE_C2_NONE 0x00000020u
#define EXTI_MODE_C2_INTERRUPT 0x00000021u
#define EXTI_MODE_C2_EVENT 0x00000022u
/**
* @}
*/
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000u
#define EXTI_TRIGGER_RISING 0x00000001u
#define EXTI_TRIGGER_FALLING 0x00000002u
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u
#define EXTI_GPIOD 0x00000003u
#define EXTI_GPIOE 0x00000004u
#define EXTI_GPIOF 0x00000005u
#define EXTI_GPIOG 0x00000006u
#define EXTI_GPIOH 0x00000007u
#define EXTI_GPIOI 0x00000008u
#define EXTI_GPIOJ 0x00000009u
#define EXTI_GPIOK 0x0000000Au
#define EXTI_GPIOZ 0x0000000Bu
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
* @{
*/
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24u
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI Event presence definition
*/
#define EXTI_EVENT_PRESENCE_SHIFT 28u
#define EXTI_EVENT (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
#define EXTI_EVENT_PRESENCE_MASK (EXTI_EVENT)
/**
* @brief EXTI Register and bit usage
*/
#define EXTI_REG_SHIFT 16u
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define EXTI_PIN_MASK 0x0000001Fu
/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_C1 | EXTI_MODE_C2 | EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#define EXTI_LINE_NB 76uL
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u))
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
#define IS_EXTI_PENDING_EDGE(__LINE__) (((__LINE__) == EXTI_TRIGGER_RISING) || \
((__LINE__) == EXTI_TRIGGER_FALLING))
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI) || \
((__PORT__) == EXTI_GPIOK) || \
((__PORT__) == EXTI_GPIOZ))
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32MP1xx_HAL_EXTI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio.h
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/**
******************************************************************************
* @file stm32mp1xx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32MP1XX_HAL_GPIO_H__
#define __STM32MP1XX_HAL_GPIO_H__
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal_def.h"
/** @addtogroup STM32MP1xx_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode_define */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull_define */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed_define */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
This parameter can be a value of @ref GPIO_Alternate_function_selection */
}GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0,
GPIO_PIN_SET
}GPIO_PinState;
typedef enum
{
GPIO_DIR_OUTPUT = 0,
GPIO_DIR_INPUT
}GPIO_DirState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins_define GPIO pins define
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode_define GPIO mode define
* @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ
* - X : GPIO mode or EXTI Mode
* - y : External IT or Event trigger detection
* - z : IO configuration on External IT or Event
* - Y : Output type (Push Pull or Open Drain)
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_AF GPIO_MODE_AF_PP /*!< Alternate Function for Input PIN */
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup GPIO_speed_define GPIO speed define
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */
/**
* @}
*/
/** @defgroup GPIO_pull_define GPIO pull define
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__,EXTI) ((EXTI->RPR1 & (__EXTI_LINE__)) | (EXTI->FPR1 & (__EXTI_LINE__)))
/**
* @brief Clears the EXTI's line pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__,EXTI) do { \
EXTI->RPR1 = (__EXTI_LINE__); \
EXTI->FPR1 = (__EXTI_LINE__); \
} while (0);
/**
* @brief Checks whether the specified EXTI line is asserted or not for Rising edge.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__,EXTI) (EXTI->RPR1 & (__EXTI_LINE__))
/**
* @brief Checks whether the specified EXTI line is asserted or not for Falling edge.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__,EXTI) (EXTI->FPR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending bits for Risng edge.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__,EXTI) do { \
EXTI->RPR1 = (__EXTI_LINE__); \
} while (0);
/**
* @brief Clears the EXTI's line pending bits for Falling edge.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__,EXTI) do { \
EXTI->FPR1 = (__EXTI_LINE__); \
} while (0);
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__,EXTI) (EXTI->SWIER1 |= (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
/**
* @brief Clear the EXTI line pending flags.
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
/**
* @}
*/
/* Include GPIO HAL Extension module */
#include "stm32mp1xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions
* @{
*/
/** @addtogroup GPIO_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
GPIO_DirState HAL_GPIO_ReadDir(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK ) != 0x00u) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
((MODE) == GPIO_MODE_AF_PP) ||\
((MODE) == GPIO_MODE_AF_OD) ||\
((MODE) == GPIO_MODE_IT_RISING) ||\
((MODE) == GPIO_MODE_IT_FALLING) ||\
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING) ||\
((MODE) == GPIO_MODE_EVT_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
((PULL) == GPIO_PULLDOWN))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Functions GPIO Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_gpio_ex.h
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/**
******************************************************************************
* @file stm32mp1xx_hal_gpio_ex.h
* @author MCD Application Team
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32MP1xx_HAL_GPIO_EX_H
#define __STM32MP1xx_HAL_GPIO_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/** @addtogroup STM32MP1xx_HAL_Driver
* @{
*/
/** @addtogroup GPIOEx GPIOEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO1 ((uint8_t)0x00) /* MCO1 Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define GPIO_AF0_HDP ((uint8_t)0x00) /* HDP Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF1_MCO2 ((uint8_t)0x01) /* MCO2 Alternate Function mapping */
#define GPIO_AF1_RTC ((uint8_t)0x01) /* RTC Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
#define GPIO_AF2_SAI4 ((uint8_t)0x02) /* SAI4 Alternate Function mapping */
#define GPIO_AF2_I2C6 ((uint8_t)0x02) /* I2C6 Alternate Function mapping */
#define GPIO_AF2_MCO1 ((uint8_t)0x02) /* MCO1 Alternate Function mapping */
#define GPIO_AF2_MCO2 ((uint8_t)0x02) /* MCO2 Alternate Function mapping */
#define GPIO_AF2_HDP ((uint8_t)0x02) /* HDP Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM1 Alternate Function mapping */
#define GPIO_AF3_I2C2 ((uint8_t)0x03) /* I2C6 Alternate Function mapping */
#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
#define GPIO_AF3_SAI4 ((uint8_t)0x03) /* SAI4 Alternate Function mapping */
#define GPIO_AF3_SDIO1 ((uint8_t)0x03) /* SDIO1 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4 ((uint8_t)0x04)
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */
#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM1 Alternate Function mapping */
#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF4_SAI4 ((uint8_t)0x04) /* SAI4 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5 ((uint8_t)0x05)
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
#define GPIO_AF5_I2C1 ((uint8_t)0x05) /* I2C1 Alternate Function mapping */
#define GPIO_AF5_SDIO1 ((uint8_t)0x05) /* SDIO1 Alternate Function mapping */
#define GPIO_AF5_SDIO3 ((uint8_t)0x05) /* SDIO3 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
#define GPIO_AF6_SAI4 ((uint8_t)0x06) /* SAI4 Alternate Function mapping */
#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
#define GPIO_AF8_SDIO1 ((uint8_t)0x08) /* SDIO1 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#if defined (FDCAN1)
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#endif
#if defined (FDCAN2)
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#endif
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_SDIO2 ((uint8_t)0x09) /* SDIO2 Alternate Function mapping */
#define GPIO_AF9_LCD ((uint8_t)0x09) /* LCD Alternate Function mapping */
#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
#define GPIO_AF9_SDIO3 ((uint8_t)0x09) /* SDIO3 Alternate Function mapping */
#define GPIO_AF9_SDIO2 ((uint8_t)0x09) /* SDIO3 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
#define GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */
#define GPIO_AF10_SDIO2 ((uint8_t)0xA) /* SDIO2 Alternate Function mapping */
#define GPIO_AF10_SDIO3 ((uint8_t)0xA) /* SDIO3 Alternate Function mapping */
#define GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */
#define GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM1 Alternate Function mapping */
#define GPIO_AF11_QUADSPI ((uint8_t)0x0B) /* QUADSPI Alternate Function mapping */
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
#if defined (DSI)
#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */
#endif
#define GPIO_AF11_SDIO1 ((uint8_t)0x0B) /* SDIO1 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_UART5 ((uint8_t)0xC) /* UART5 Alternate Function mapping */
#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
#define GPIO_AF12_SDIO1 ((uint8_t)0xC) /* SDIO1 Alternate Function mapping */
#define GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */
#define GPIO_AF12_SAI4 ((uint8_t)0xC) /* SAI4 Alternate Function mapping */
#define GPIO_AF12_SDIO1 ((uint8_t)0xC) /* SAI4 Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_UART7 ((uint8_t)0x0D) /* UART7 Alternate Function mapping */
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#define GPIO_AF13_LCD ((uint8_t)0x0D) /* LCD Alternate Function mapping */
#if defined (DSI)
#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
#endif
#define GPIO_AF13_RNG ((uint8_t)0x0D) /* RNG Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
#define GPIO_AF14_LCD ((uint8_t)0x0E) /* LCD Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
* @{
*/
/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
* @{
*/
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U :\
((__GPIOx__) == (GPIOE))? 4U :\
((__GPIOx__) == (GPIOF))? 5U :\
((__GPIOx__) == (GPIOG))? 6U :\
((__GPIOx__) == (GPIOH))? 7U :\
((__GPIOx__) == (GPIOI))? 8U :\
((__GPIOx__) == (GPIOJ))? 9U :\
((__GPIOx__) == (GPIOK))? 10U :\
((__GPIOx__) == (GPIOZ))? 11U : 25U)
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIOEx_Exported_Functions GPIO Extended Exported Functions
* @{
*/
/** @addtogroup GPIOEx_Exported_Functions_Group1 Extended Peripheral Control functions
* @{
*/
void HAL_GPIOEx_SecurePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIOEx_NonSecurePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
GPIO_PinState HAL_GPIOEx_IsPinSecured(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32MP1xx_HAL_GPIO_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_i2c.h
Executable
+682
View File
@@ -0,0 +1,682 @@
/**
******************************************************************************
* @file stm32mp1xx_hal_i2c.h
* @author MCD Application Team
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32MP1xx_HAL_I2C_H
#define STM32MP1xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal_def.h"
/** @addtogroup STM32MP1xx_HAL_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization
section in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :\n
* b7-b6 Error information\n
* 00 : No Error\n
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
* b0 Tx state\n
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
} HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
} I2C_HandleTypeDef;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
} HAL_I2C_CallbackIDTypeDef;
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x000000AAU)
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Include I2C HAL Extended module */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
* @{
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions are defined in stm32mp1xx_hal_i2c.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_ltdc.h
Executable
+688
View File
@@ -0,0 +1,688 @@
/**
******************************************************************************
* @file stm32h7xx_hal_ltdc.h
* @author MCD Application Team
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_LTDC_H
#define STM32H7xx_HAL_LTDC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal_def.h"
#include "stm32mp157axx_ca7.h"
// #if defined (LTDC)
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup LTDC LTDC
* @brief LTDC HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup LTDC_Exported_Types LTDC Exported Types
* @{
*/
#define MAX_LAYER 2U
/**
* @brief LTDC color structure definition
*/
typedef struct
{
uint8_t Blue; /*!< Configures the blue value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Green; /*!< Configures the green value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Red; /*!< Configures the red value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Reserved; /*!< Reserved 0xFF */
} LTDC_ColorTypeDef;
/**
* @brief LTDC Init structure definition
*/
typedef struct
{
uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.
This parameter can be one value of @ref LTDC_HS_POLARITY */
uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.
This parameter can be one value of @ref LTDC_VS_POLARITY */
uint32_t DEPolarity; /*!< configures the data enable polarity.
This parameter can be one of value of @ref LTDC_DE_POLARITY */
uint32_t PCPolarity; /*!< configures the pixel clock polarity.
This parameter can be one of value of @ref LTDC_PC_POLARITY */
uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
uint32_t TotalWidth; /*!< configures the total width.
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
uint32_t TotalHeigh; /*!< configures the total height.
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
} LTDC_InitTypeDef;
/**
* @brief LTDC Layer structure definition
*/
typedef struct
{
uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
uint32_t PixelFormat; /*!< Specifies the pixel format.
This parameter can be one of value of @ref LTDC_Pixelformat */
uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Alpha0; /*!< Configures the default alpha value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t BlendingFactor1; /*!< Select the blending factor 1.
This parameter can be one of value of @ref LTDC_BlendingFactor1 */
uint32_t BlendingFactor2; /*!< Select the blending factor 2.
This parameter can be one of value of @ref LTDC_BlendingFactor2 */
uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
} LTDC_LayerCfgTypeDef;
/**
* @brief HAL LTDC State structures definition
*/
typedef enum
{
HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */
HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */
HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */
HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */
HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */
} HAL_LTDC_StateTypeDef;
/**
* @brief LTDC handle Structure definition
*/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
typedef struct __LTDC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
{
LTDC_TypeDef *Instance; /*!< LTDC Register base address */
LTDC_InitTypeDef Init; /*!< LTDC parameters */
LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */
HAL_LockTypeDef Lock; /*!< LTDC Lock */
__IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */
__IO uint32_t ErrorCode; /*!< LTDC Error code */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */
void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */
void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */
void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */
void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
} LTDC_HandleTypeDef;
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL LTDC Callback ID enumeration definition
*/
typedef enum
{
HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */
HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */
HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */
HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */
HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */
} HAL_LTDC_CallbackIDTypeDef;
/**
* @brief HAL LTDC Callback pointer definition
*/
typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
* @{
*/
/** @defgroup LTDC_Error_Code LTDC Error Code
* @{
*/
#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */
#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */
#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */
#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup LTDC_Layer LTDC Layer
* @{
*/
#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */
#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */
/**
* @}
*/
/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
* @{
*/
#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */
#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
/**
* @}
*/
/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
* @{
*/
#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */
#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
/**
* @}
*/
/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
* @{
*/
#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */
#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
/**
* @}
*/
/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
* @{
*/
#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */
#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
/**
* @}
*/
/** @defgroup LTDC_SYNC LTDC SYNC
* @{
*/
#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */
#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */
/**
* @}
*/
/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
* @{
*/
#define LTDC_COLOR 0x000000FFU /*!< Color mask */
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
* @{
*/
#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
* @{
*/
#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
/** @defgroup LTDC_Pixelformat LTDC Pixel format
* @{
*/
#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */
/**
* @}
*/
/** @defgroup LTDC_Alpha LTDC Alpha
* @{
*/
#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */
/**
* @}
*/
/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
* @{
*/
#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */
#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
/**
* @}
*/
/** @defgroup LTDC_Interrupts LTDC Interrupts
* @{
*/
#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */
#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */
#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */
#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */
/**
* @}
*/
/** @defgroup LTDC_Flags LTDC Flags
* @{
*/
#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */
#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */
#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */
#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */
/**
* @}
*/
/** @defgroup LTDC_Reload_Type LTDC Reload Type
* @{
*/
#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */
#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
* @{
*/
/** @brief Reset LTDC handle state.
* @param __HANDLE__ LTDC handle
* @retval None
*/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_LTDC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @brief Enable the LTDC.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
/**
* @brief Disable the LTDC.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
/**
* @brief Enable the LTDC Layer.
* @param __HANDLE__ LTDC handle
* @param __LAYER__ Specify the layer to be enabled.
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
/**
* @brief Disable the LTDC Layer.
* @param __HANDLE__ LTDC handle
* @param __LAYER__ Specify the layer to be disabled.
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
/**
* @brief Reload immediately all LTDC Layers.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
/**
* @brief Reload during vertical blanking period all LTDC Layers.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
/* Interrupt & Flag management */
/**
* @brief Get the LTDC pending flags.
* @param __HANDLE__ LTDC handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg LTDC_FLAG_LI: Line Interrupt flag
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/**
* @brief Clears the LTDC pending flags.
* @param __HANDLE__ LTDC handle
* @param __FLAG__ Specify the flag to clear.
* This parameter can be any combination of the following values:
* @arg LTDC_FLAG_LI: Line Interrupt flag
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enables the specified LTDC interrupts.
* @param __HANDLE__ LTDC handle
* @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
* @brief Disables the specified LTDC interrupts.
* @param __HANDLE__ LTDC handle
* @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified LTDC interrupt has occurred or not.
* @param __HANDLE__ LTDC handle
* @param __INTERRUPT__ Specify the LTDC interrupt source to check.
* This parameter can be one of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval The state of INTERRUPT (SET or RESET).
*/
#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/**
* @}
*/
/* Include LTDC HAL Extension module */
// #include "stm32h7xx_hal_ltdc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDC_Exported_Functions
* @{
*/
/** @addtogroup LTDC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group4
* @{
*/
/* Peripheral State functions *************************************************/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup LTDC_Private_Macros LTDC Private Macros
* @{
*/
#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))
#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))
#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup LTDC_Private_Functions LTDC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* LTDC */
#ifdef __cplusplus
}
#endif
// #endif /* STM32H7xx_HAL_LTDC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc.h
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common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h
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common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Inc/system_stm32mp1xx.h
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/**
******************************************************************************
* @file system_stm32mp1xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-Mx Device System Source File for STM32MP1xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32mp1xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32MP1XX_H
#define __SYSTEM_STM32MP1XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32MP1xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Core1 Clock Frequency */
extern uint32_t SystemCore1Clock; /*!< System Core1 Clock Frequency */
extern uint32_t SystemCore2Clock; /*!< System Core2 Clock Frequency */
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Exported_Functions
* @{
*/
extern void Hal_SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32MP1XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c
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/**
******************************************************************************
* @file stm32mp1xx_hal.c
* @author MCD Application Team
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The common HAL driver contains a set of generic and common APIs that can be
used by the PPP peripheral drivers and the user to start using the HAL.
[..]
The HAL contains two APIs' categories:
(+) Common HAL APIs
(+) Services HAL APIs
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal.h"
/** @addtogroup STM32MP1xx_HAL_Driver
* @{
*/
/** @defgroup HAL HAL
* @brief HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup HAL_Private_Defines HAL Private Defines
* @{
*/
/**
* @brief STM32MP1xx HAL Driver version number
*/
#define __STM32MP1xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32MP1xx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
#define __STM32MP1xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32MP1xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32MP1xx_HAL_VERSION ((__STM32MP1xx_HAL_VERSION_MAIN << 24)\
|(__STM32MP1xx_HAL_VERSION_SUB1 << 16)\
|(__STM32MP1xx_HAL_VERSION_SUB2 << 8 )\
|(__STM32MP1xx_HAL_VERSION_RC))
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
#define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup HAL_Private_Variables HAL Private Variables
* @{
*/
__IO uint32_t uwTick;
#if defined(CORE_CM4)
static uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
#endif
static HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HAL_Private_Functions HAL Private Functions
* @{
*/
/** @defgroup HAL_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initializes the Flash interface the NVIC allocation and initial clock
configuration. It initializes the systick also when timeout is needed
and the backup domain when enabled.
(+) De-Initializes common part of the HAL.
(+) Configure The time base source to have 1ms time base with a dedicated
Tick interrupt priority.
(++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
(++) Time base configuration function (HAL_InitTick ()) is called automatically
at the beginning of the program after reset by HAL_Init() or at any time
when clock is configured, by HAL_RCC_ClockConfig().
(++) Source of time base is configured to generate interrupts at regular
time intervals. Care must be taken if HAL_Delay() is called from a
peripheral ISR process, the Tick interrupt line must have higher priority
(numerically lower) than the peripheral interrupt. Otherwise the caller
ISR process will be blocked.
(++) functions affecting time base configurations are declared as __weak
to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
/**
* @brief This function is used to initialize the HAL Library; it must be the first
* instruction to be executed in the main program (before to call any other
* HAL function), it performs the following:
* Configures the SysTick to generate an interrupt each 1 millisecond,
* which is clocked by the HSI (at this stage, the clock is not yet
* configured and thus the system is running from the internal HSI at 16 MHz).
* Set NVIC Group Priority to 4.
* Calls the HAL_MspInit() callback function defined in user file
* "stm32mp1xx_hal_msp.c" to do the global low level hardware initialization
*
* @note SysTick is used as time base for the HAL_Delay() function, the application
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
/* Set Interrupt Group Priority */
#if defined (CORE_CM4)
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
#endif
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
{
return HAL_ERROR;
}
/* Init the low level hardware */
HAL_MspInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief This function de-Initializes common part of the HAL and stops the systick.
* This function is optional.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
/* De-Init the low level hardware */
HAL_MspDeInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the MSP.
* @retval None
*/
__weak void HAL_MspDeInit(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function configures the source of the time base.
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The the SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/*Configure the Tick to have interrupt in 1ms time basis*/
#if defined (CORE_CA7)
#if defined(USE_ST_CASIS)
HAL_SYSTICK_Config(SystemCoreClock/1000);
#elif defined (USE_PL1_SecurePhysicalTimer_IRQ)
/* Stop Timer */
PL1_SetControl(0x0);
PL1_SetCounterFrequency(HSI_VALUE);
/* Initialize Counter */
PL1_SetLoadValue(HSI_VALUE/1000);
/* Disable corresponding IRQ */
IRQ_Disable(SecurePhysicalTimer_IRQn);
IRQ_ClearPending(SecurePhysicalTimer_IRQn);
/* Set timer priority to lowest (Only bit 7:3 are implemented in MP1 CA7 GIC) */
/* TickPriority is based on 16 level priority (from MCUs) so set it in 7:4 and leave bit 3=0 */
IRQ_SetPriority(SecurePhysicalTimer_IRQn, TickPriority << 4);
/* Set edge-triggered IRQ */
IRQ_SetMode(SecurePhysicalTimer_IRQn, IRQ_MODE_TRIG_EDGE);
/* Enable corresponding interrupt */
IRQ_Enable(SecurePhysicalTimer_IRQn);
/* Kick start Timer */
PL1_SetControl(0x1);
#else
/*Set Counter Frequency */
PL1_SetCounterFrequency(HSI_VALUE);
// __set_CNTFRQ(HSI_VALUE);
/* Initialize Counter */
PL1_SetLoadValue(0x1);
// __set_CNTP_TVAL(0x1);
#endif
#endif /* CORE_CA7 */
#if defined (CORE_CM4)
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock /(1000U / uwTickFreq)) > 0U)
{
return HAL_ERROR;
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
uwTickPrio = TickPriority;
}
else
{
return HAL_ERROR;
}
#endif /* CORE_CM4 */
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup HAL_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Provide a tick value in millisecond
(+) Provide a blocking delay in millisecond
(+) Suspend the time base source interrupt
(+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
(+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP mode
(+) Enable/Disable Debug module during STANDBY mode
@endverbatim
* @{
*/
/**
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in Systick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick += (uint32_t)uwTickFreq;
}
/**
* @brief Provides a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
#if defined (CORE_CA7)
#if defined (USE_ST_CASIS)
return ( Gen_Timer_Get_PhysicalCount() / (HSI_VALUE/1000));
#elif defined (USE_PL1_SecurePhysicalTimer_IRQ)
/* tick is incremented in SecurePhysicalTimer_IRQ handler */
return uwTick;
#else
/* tick value directly got from 64bits CA7 register*/
return ( PL1_GetCurrentPhysicalValue() / (HSI_VALUE/1000));
#endif
#endif /* CORE_CA7 */
#if defined (CORE_CM4)
/* tick is incremented in systick handler */
return uwTick;
#endif /* CORE_CM4 */
}
#if defined (CORE_CM4)
/**
* @brief This function returns a tick priority.
* @retval tick priority
*/
uint32_t HAL_GetTickPrio(void)
{
return uwTickPrio;
}
/**
* @brief Set new tick Freq.
* @retval Status
*/
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
{
HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_TICKFREQ(Freq));
if (uwTickFreq != Freq)
{
uwTickFreq = Freq;
/* Apply the new tick Freq */
status = HAL_InitTick(uwTickPrio);
}
return status;
}
/**
* @brief Return tick frequency.
* @retval tick period in Hz
*/
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
{
return uwTickFreq;
}
#endif
/**
* @brief This function provides accurate delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note ThiS function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay: specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
wait += (uint32_t)(uwTickFreq);
}
while ((HAL_GetTick() - tickstart) < wait)
{
}
}
/**
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_SuspendTick(void)
{
#if defined (CORE_CA7)
#elif defined (CORE_CM4)
/* Disable SysTick Interrupt */
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
#endif
}
/**
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_ResumeTick(void)
{
#if defined (CORE_CA7)
#elif defined (CORE_CM4)
/* Enable SysTick Interrupt */
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
#endif
}
/**
* @brief Returns the HAL revision
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
return __STM32MP1xx_HAL_VERSION;
}
/**
* @brief Returns the device revision identifier.
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
{
return((DBGMCU->IDCODE) >> 16);
}
/**
* @brief Returns the device identifier.
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
{
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
}
/**
* @brief Enable DBG wake up on AIEC
* @retval None
*/
void HAL_EnableDBGWakeUp(void)
{
#if defined (CORE_CA7)
SET_BIT(EXTI_C1->IMR3, EXTI_IMR3_IM75);
#elif defined (CORE_CM4)
SET_BIT(EXTI_C2->IMR3, EXTI_IMR3_IM75);
#endif
}
/**
* @brief Disable DBG wake up on AIEC
* @retval None
*/
void HAL_DisableDBGWakeUp(void)
{
#if defined (CORE_CA7)
CLEAR_BIT(EXTI_C1->IMR3, EXTI_IMR3_IM75);
#elif defined (CORE_CM4)
CLEAR_BIT(EXTI_C2->IMR3, EXTI_IMR3_IM75);
#endif
}
/**
* @brief Enable the Debug Module during Domain1 SLEEP mode
* @retval None
*/
void HAL_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during Domain1 SLEEP mode
* @retval None
*/
void HAL_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during Domain1 STOP mode
* @retval None
*/
void HAL_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during Domain1 STOP mode
* @retval None
*/
void HAL_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during Domain1 STANDBY mode
* @retval None
*/
void HAL_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during Domain1 STANDBY mode
* @retval None
*/
void HAL_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Configure the internal voltage reference buffer voltage scale.
* @param VoltageScaling specifies the output voltage to achieve
* This parameter can be one of the following values:
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V.
* This requires VDDA equal to or higher than 2.4 V.
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.5 V.
* This requires VDDA equal to or higher than 2.8 V.
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.5 V.
* This requires VDDA equal to or higher than 1.8 V.
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.8 V.
* This requires VDDA equal to or higher than 2.1 V.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
}
/**
* @brief Configure the internal voltage reference buffer high impedance mode.
* @param Mode specifies the high impedance mode
* This parameter can be one of the following values:
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
}
/**
* @brief Tune the Internal Voltage Reference buffer (VREFBUF).
* @retval None
*/
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
{
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
}
/**
* @brief Enable the Internal Voltage Reference buffer (VREFBUF).
* @retval HAL_OK/HAL_TIMEOUT
*/
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
{
uint32_t tickstart = 0;
SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait for VRR bit */
while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET)
{
if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @brief Disable the Internal Voltage Reference buffer (VREFBUF).
*
* @retval None
*/
void HAL_SYSCFG_DisableVREFBUF(void)
{
CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
}
/**
* @brief Ethernet PHY Interface Selection either MII or RMII
* @param SYSCFG_ETHInterface: Selects the Ethernet PHY interface
* This parameter can be one of the following values:
* @arg SYSCFG_ETH_MII : Select the Media Independent Interface
* @arg SYSCFG_ETH_GMII : Select the Gigabit Media Independent Interface
* @arg SYSCFG_ETH_RGMII: Select the Gigabit Reduced Media Independent Interface
* @arg SYSCFG_ETH_RMII : Select the Reduced Media Independent Interface
* @retval None
*/
void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface)
{
/* Check the parameter */
assert_param(IS_SYSCFG_ETHERNET_CONFIG(SYSCFG_ETHInterface));
SET_BIT(SYSCFG->PMCCLRR, SYSCFG_PMCSETR_ETH_SEL|SYSCFG_PMCSETR_ETH_SELMII_SEL);
SET_BIT(SYSCFG->PMCSETR, (uint32_t)(SYSCFG_ETHInterface));
}
/**
* @brief Analog Switch control for dual analog pads.
* @param SYSCFG_AnalogSwitch: Selects the analog pad
* This parameter can be one or a combination of the following values:
* @arg SYSCFG_SWITCH_PA0 : Select PA0 analog switch
* @arg SYSCFG_SWITCH_PA1: Select PA1 analog switch
* @param SYSCFG_SwitchState: Open or Close the analog switch between dual pads (
* This parameter can be one or a combination of the following values:
* @arg SYSCFG_SWITCH_PA0_OPEN
* @arg SYSCFG_SWITCH_PA0_CLOSE
* @arg SYSCFG_SWITCH_PA1_OPEN
* @arg SYSCFG_SWITCH_PA1_CLOSE
* @retval None
*/
void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState )
{
/* Check the parameter */
assert_param(IS_SYSCFG_ANALOG_SWITCH(SYSCFG_AnalogSwitch));
assert_param(IS_SYSCFG_SWITCH_STATE(SYSCFG_SwitchState));
SET_BIT(SYSCFG->PMCCLRR, SYSCFG_AnalogSwitch);
SET_BIT(SYSCFG->PMCSETR, (uint32_t)(SYSCFG_SwitchState));
}
/**
* @brief Enables the booster to reduce the total harmonic distortion of the analog
* switch when the supply voltage is lower than 2.7 V.
* @note Activating the booster allows to guaranty the analog switch AC performance
* when the supply voltage is below 2.7 V: in this case, the analog switch
* performance is the same on the full voltage range
* @retval None
*/
void HAL_SYSCFG_EnableBOOST(void)
{
SET_BIT(SYSCFG->PMCSETR, SYSCFG_PMCSETR_EN_BOOSTER) ;
}
/**
* @brief Disables the booster
* @note Activating the booster allows to guaranty the analog switch AC performance
* when the supply voltage is below 2.7 V: in this case, the analog switch
* performance is the same on the full voltage range
* @retval None
*/
void HAL_SYSCFG_DisableBOOST(void)
{
SET_BIT(SYSCFG->PMCCLRR, SYSCFG_PMCCLRR_EN_BOOSTER) ;
}
/**
* @brief Enables the I/O Compensation Cell.
* @note The I/O compensation cell can be used only when the device supply
* voltage ranges from 2.4 to 3.6 V.
* @retval None
*/
void HAL_EnableCompensationCell(void)
{
#if defined(CORE_CM4)
SET_BIT(SYSCFG->CMPENSETR, SYSCFG_CMPENSETR_MCU_EN) ;
#elif defined(CORE_CA7)
SET_BIT(SYSCFG->CMPENSETR, SYSCFG_CMPENSETR_MPU_EN) ;
#endif
}
/**
* @brief Power-down the I/O Compensation Cell.
* @note The I/O compensation cell can be used only when the device supply
* voltage ranges from 2.4 to 3.6 V.
* @retval None
*/
void HAL_DisableCompensationCell(void)
{
#if defined(CORE_CM4)
SET_BIT(SYSCFG->CMPENCLRR, SYSCFG_CMPENCLRR_MCU_EN) ;
#elif defined(CORE_CA7)
SET_BIT(SYSCFG->CMPENCLRR, SYSCFG_CMPENCLRR_MPU_EN) ;
#endif
}
/**
* @brief To Enable optimize the I/O speed when the product voltage is low.
* @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
* used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
* higher than 2.5 V might be destructive.
* @param SYSCFG_HighSpeedSignal: Signal selection (TRACE, QUADSPI...)
* This parameter can be one or a combination of the following values:
* @arg SYSCFG_HIGHSPEED_TRACE_SIGNAL
* @arg SYSCFG_HIGHSPEED_QUADSPI_SIGNAL
* @arg SYSCFG_HIGHSPEED_ETH_SIGNAL
* @arg SYSCFG_HIGHSPEED_SDMMC_SIGNAL
* @arg SYSCFG_HIGHSPEED_SPI_SIGNAL
* @retval None
*/
void HAL_SYSCFG_EnableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal )
{
SET_BIT(SYSCFG->IOCTRLSETR, SYSCFG_HighSpeedSignal) ;
}
/**
* @brief To Disable optimize the I/O speed when the product voltage is low.
* @note This bit is active only if PRODUCT_BELOW_25V user option bit is set. It must be
* used only if the product supply voltage is below 2.5 V. Setting this bit when VDD is
* higher than 2.5 V might be destructive.
* @param SYSCFG_HighSpeedSignal: Signal selection (TRACE, QUADSPI...)
* This parameter can be one or a combination of the following values:
* @arg SYSCFG_HIGHSPEED_TRACE_SIGNAL
* @arg SYSCFG_HIGHSPEED_QUADSPI_SIGNAL
* @arg SYSCFG_HIGHSPEED_ETH_SIGNAL
* @arg SYSCFG_HIGHSPEED_SDMMC_SIGNAL
* @arg SYSCFG_HIGHSPEED_SPI_SIGNAL
* @retval None
*/
void HAL_SYSCFG_DisableIOSpeedOptimize(uint32_t SYSCFG_HighSpeedSignal )
{
SET_BIT(SYSCFG->IOCTRLCLRR, SYSCFG_HighSpeedSignal) ;
}
/**
* @brief Code selection for the I/O Compensation cell
* @param SYSCFG_CompCode: Selects the code to be applied for the I/O compensation cell
* This parameter can be one of the following values:
* @arg SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)
* @arg SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)
* @retval None
*/
void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode)
{
/* Check the parameter */
assert_param(IS_SYSCFG_CODE_SELECT(SYSCFG_CompCode));
MODIFY_REG(SYSCFG->CMPCR, SYSCFG_CMPCR_SW_CTRL, (uint32_t)(SYSCFG_CompCode));
}
/**
* @brief Code selection for the I/O Compensation cell
* @param SYSCFG_PMOSCode: PMOS compensation code
* This code is applied to the I/O compensation cell when the CS bit of the
* SYSCFG_CMPCR is set
* @param SYSCFG_NMOSCode: NMOS compensation code
* This code is applied to the I/O compensation cell when the CS bit of the
* SYSCFG_CMPCR is set
* @retval None
*/
void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode )
{
/* Check the parameter */
assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_PMOSCode));
assert_param(IS_SYSCFG_CODE_CONFIG(SYSCFG_NMOSCode));
MODIFY_REG(SYSCFG->CMPCR, SYSCFG_CMPCR_RANSRC|SYSCFG_CMPCR_RAPSRC, (((uint32_t)(SYSCFG_PMOSCode)<< 4)|(uint32_t)(SYSCFG_NMOSCode)) );
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_exti.c
Executable
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/**
******************************************************************************
* @file stm32mp1xx_hal_exti.c
* @author MCD Application Team
* @brief EXTI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (EXTI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
@verbatim
==============================================================================
##### EXTI Peripheral features #####
==============================================================================
[..]
(+) Each Exti line can be configured within this driver.
(+) Exti line can be configured in 3 different modes
(++) Interrupt
(++) Event
(++) Both of them
(+) Configurable Exti lines can be configured with 3 different triggers
(++) Rising
(++) Falling
(++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two diffenrents
interrupt pending registers which allow to distinguish which transition
occurs:
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected throught multiplexer.
##### How to use this driver #####
==============================================================================
[..]
(#) Configure the configurable EXTI line using HAL_EXTI_SetConfigLine().
NOTE: in addition HAL_EXTI_SetInterruptAndEventMask shall be used
to configure interrupt and events mask of this configurable line
(++) Choose the interrupt line number by setting "Line" member from
EXTI_ConfigTypeDef structure.
(++) Configure the interrupt and/or event mode using "Mode" member from
EXTI_ConfigTypeDef structure.
(++) For configurable lines, configure rising and/or falling trigger
"Trigger" member from EXTI_ConfigTypeDef structure.
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
member from GPIO_InitTypeDef structure.
(#) Get current Exti configuration of a dedicated line using
HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
(++) Provide exiting handle as parameter.
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
(++) Provide exiting handle as first parameter.
(++) Provide which callback will be registered using one value from
EXTI_CallbackIDTypeDef.
(++) Provide callback function pointer.
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal.h"
/** @addtogroup STM32MP1xx_HAL_Driver
* @{
*/
/** @addtogroup EXTI
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rule:
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
* of bounds [0,3] in following API :
* HAL_EXTI_SetConfigLine
* HAL_EXTI_GetConfigLine
* HAL_EXTI_ClearConfigLine
*/
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
#define EXTI_MODE_C1 0x10u
#define EXTI_MODE_C2 0x20u
#define EXTI_MODE_INTERRUPT 0x01u
#define EXTI_MODE_EVENT 0x02u
#define EXTI_MODE_OFFSET 0x04u /* 0x10: offset between CPU IMR/EMR registers */
#define EXTI_CONFIG_OFFSET 0x08u /* 0x20: offset between CPU Rising/Falling configuration registers */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_Exported_Functions
* @{
*/
/** @addtogroup EXTI_Exported_Functions_Group1
* @brief Configuration functions
*
@verbatim
===============================================================================
##### Configuration functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Set configuration except Interrupt and Event mask of a dedicated Exti line.
* It is relevant only for configurable events.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on EXTI configuration to be set.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check null pointer */
if ((hexti == 0) || (pExtiConfig == 0))
{
return HAL_ERROR;
}
/* Assign line number to handle */
hexti->Line = pExtiConfig->Line;
/* compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* Configure triggers for configurable lines */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
/* Configure rising trigger */
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store rising trigger mode */
*regaddr = regval;
/* Configure falling trigger */
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store falling trigger mode */
*regaddr = regval;
/* Configure gpio port selection in case of gpio exti line */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
regval = EXTI->EXTICR[linepos >> 2u];
regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
EXTI->EXTICR[linepos >> 2u] = regval;
}
}
/*Set Interrupt And Event Mask for Core 1 if configuration for Core 1 given into parameter mode */
if ((pExtiConfig->Mode & EXTI_MODE_C1) != 0x00u)
{
regaddr = (&EXTI->C1IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* The event mode cannot be configured if the line does not support it */
regaddr = (&EXTI->C1EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
}
/*Set Interrupt And Event Mask for Core 2 if configuration for Core 2 given into parameter mode */
if ((pExtiConfig->Mode & EXTI_MODE_C2) != 0x00u)
{
regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store interrupt mode */
*regaddr = regval;
/* The event mode cannot be configured if the line does not support it */
regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Mask or set line */
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
{
regval |= maskline;
}
else
{
regval &= ~maskline;
}
/* Store event mode */
*regaddr = regval;
}
return HAL_OK;
}
/**
* @brief Get configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @param pExtiConfig Pointer on structure to store Exti configuration.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check 0 pointer */
if ((hexti == 0) || (pExtiConfig == 0))
{
return HAL_ERROR;
}
/* Store handle line number to configiguration structure */
pExtiConfig->Line = hexti->Line;
/* compute line register offset and line mask */
offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Get core 1 mode : interrupt */
regaddr = (&EXTI->C1IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode = EXTI_MODE_C1_INTERRUPT;
}
else
{
pExtiConfig->Mode = EXTI_MODE_C1_NONE;
}
/* Get Core 1 mode : event */
regaddr = (&EXTI->C1EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode |= EXTI_MODE_C1_EVENT;
}
/* Get core 2 mode : interrupt */
regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode |= EXTI_MODE_C2_INTERRUPT;
}
else
{
pExtiConfig->Mode |= EXTI_MODE_C2_NONE;
}
/* Get Core 2 mode : event */
regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
regval = *regaddr;
/* Check if selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Mode |= EXTI_MODE_C2_EVENT;
}
/* 2] Get trigger for configurable lines : rising */
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
{
regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
}
/* Get falling configuration */
regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
regval = *regaddr;
/* Check if configuration of selected line is enable */
if ((regval & maskline) != 0x00u)
{
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
}
/* Get Gpio port selection for gpio lines */
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
{
regval = EXTI->EXTICR[linepos >> 2u];
pExtiConfig->GPIOSel = ((regval << (EXTI_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
}
else
{
pExtiConfig->GPIOSel = 0x00u;
}
}
else
{
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
pExtiConfig->GPIOSel = 0x00u;
}
return HAL_OK;
}
/**
* @brief Clear whole configuration of a dedicated Exti line.
* @param hexti Exti handle.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* Check 0 pointer */
if (hexti == 0)
{
return HAL_ERROR;
}
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
/* 1] Clear interrupt mode */
regaddr = (&EXTI->C1IMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
// regaddr = (&EXTI->C2IMR1 + (EXTI_MODE_OFFSET * offset));
// regval = (*regaddr & ~maskline);
// *regaddr = regval;
/* 2] Clear event mode */
regaddr = (&EXTI->C1EMR1 + (EXTI_MODE_OFFSET * offset));
regval = (*regaddr & ~maskline);
*regaddr = regval;
// regaddr = (&EXTI->C2EMR1 + (EXTI_MODE_OFFSET * offset));
// regval = (*regaddr & ~maskline);
// *regaddr = regval;
// /* 3] Clear triggers in case of configurable lines */
// if ((hexti->Line & EXTI_CONFIG) != 0x00u)
// {
// regaddr = (&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset));
// regval = (*regaddr & ~maskline);
// *regaddr = regval;
// regaddr = (&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset));
// regval = (*regaddr & ~maskline);
// *regaddr = regval;
// /* Get Gpio port selection for gpio lines */
// if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
// {
// assert_param(IS_EXTI_GPIO_PIN(linepos));
// regval = EXTI->EXTICR[linepos >> 2u];
// regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
// EXTI->EXTICR[linepos >> 2u] = regval;
// }
// }
return HAL_OK;
}
/**
* @brief Register callback for a dedicaated Exti line.
* @param hexti Exti handle.
* @param CallbackID User callback identifier.
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
* @param pPendingCbfn function pointer to be stored as callback.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
{
HAL_StatusTypeDef status = HAL_OK;
switch (CallbackID)
{
case HAL_EXTI_COMMON_CB_ID:
hexti->RisingCallback = pPendingCbfn;
hexti->FallingCallback = pPendingCbfn;
break;
case HAL_EXTI_RISING_CB_ID:
hexti->RisingCallback = pPendingCbfn;
break;
case HAL_EXTI_FALLING_CB_ID:
hexti->FallingCallback = pPendingCbfn;
break;
default:
status = HAL_ERROR;
break;
}
return status;
}
/**
* @brief Store line number as handle private field.
* @param hexti Exti handle.
* @param ExtiLine Exti line number.
* This parameter can be from 0 to @ref EXTI_LINE_NB.
* @retval HAL Status.
*/
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
{
/* Check null pointer */
if (hexti == NULL)
{
return HAL_ERROR;
}
else
{
/* Store line number as handle private field */
hexti->Line = ExtiLine;
return HAL_OK;
}
}
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group2
* @brief EXTI IO functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Handle EXTI interrupt request.
* @param hexti Exti handle.
* @retval none.
*/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t maskline;
uint32_t offset;
/* Compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
/* Get rising edge pending bit */
regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & maskline);
if (regval != 0x00u)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call rising callback */
if (hexti->RisingCallback != 0)
{
hexti->RisingCallback();
}
}
/* Get falling edge pending bit */
regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
regval = (*regaddr & maskline);
if (regval != 0x00u)
{
/* Clear pending bit */
*regaddr = maskline;
/* Call rising callback */
if (hexti->FallingCallback != 0)
{
hexti->FallingCallback();
}
}
}
/**
* @brief Get interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be checked.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING
* @arg @ref EXTI_TRIGGER_FALLING
* @retval 1 if interrupt is pending else 0.
*/
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t regval;
uint32_t linepos;
uint32_t maskline;
uint32_t offset;
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
linepos = (hexti->Line & EXTI_PIN_MASK);
maskline = (1uL << linepos);
if (Edge != EXTI_TRIGGER_RISING)
{
/* Get falling edge pending bit */
regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
}
else
{
/* Get rising edge pending bit */
regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
}
/* return 1 if bit is set else 0 */
regval = ((*regaddr & maskline) >> linepos);
return regval;
}
/**
* @brief Clear interrupt pending bit of a dedicated line.
* @param hexti Exti handle.
* @param Edge Specify which pending edge as to be clear.
* This parameter can be one of the following values:
* @arg @ref EXTI_TRIGGER_RISING
* @arg @ref EXTI_TRIGGER_FALLING
* @retval None.
*/
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
if (Edge != EXTI_TRIGGER_RISING)
{
/* Get falling edge pending register address */
regaddr = (&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset));
}
else
{
/* Get falling edge pending register address */
regaddr = (&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset));
}
/* Clear Pending bit */
*regaddr = maskline;
}
/**
* @brief Generate a software interrupt for a dedicated line.
* @param hexti Exti handle.
* @retval None.
*/
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
{
__IO uint32_t *regaddr;
uint32_t maskline;
uint32_t offset;
/* compute line register offset and line mask */
offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT);
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
regaddr = (&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset));
*regaddr = maskline;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_gpio.c
Executable
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/**
******************************************************************************
* @file stm32mp1xx_hal_gpio.c
* @author MCD Application Team
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
[..]
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
in several modes:
(+) Input mode
(+) Analog mode
(+) Output mode
(+) Alternate function mode
(+) External interrupt/event lines
[..]
During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
(+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
[..]
In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
[..]
All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
[..]
The external interrupt/event controller consists of up to 23 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure.
(++) In alternate mode is selection, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure.
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal.h"
/** @addtogroup STM32MP1xx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private defines ------------------------------------------------------------*/
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE ((uint32_t)0x00000003)
#define EXTI_MODE ((uint32_t)0x10000000)
#define GPIO_MODE_IT ((uint32_t)0x00010000)
#define GPIO_MODE_EVT ((uint32_t)0x00020000)
#define RISING_EDGE ((uint32_t)0x00100000)
#define FALLING_EDGE ((uint32_t)0x00200000)
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define GPIO_NUMBER ((uint32_t)16)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
This section provides functions allowing to initialize and de-initialize the GPIOs
to be ready for use.
@endverbatim
* @{
*/
/**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position;
uint32_t ioposition;
uint32_t iocurrent;
uint32_t temp;
#if 0 /* OHOS*/
EXTI_Core_TypeDef * EXTI_CurrentCPU;
#if defined(CORE_CM4)
EXTI_CurrentCPU = EXTI_C2; /* EXTI for CM4 CPU */
#else
EXTI_CurrentCPU = EXTI_C1; /* EXTI for CA7 CPU */
#endif
#endif
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
if(iocurrent == ioposition)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
GPIOx->AFR[position >> 3] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDR_OSPEEDR0 << (position * 2));
temp |= (GPIO_Init->Speed << (position * 2));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT0 << position) ;
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
GPIOx->OTYPER = temp;
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
temp |= ((GPIO_Init->Pull) << (position * 2));
GPIOx->PUPDR = temp;
}
}
}
/**
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
* @param GPIOx: where x can be (A..Z) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position;
uint32_t ioposition;
uint32_t iocurrent;
#if 0 /* OHOS*/
EXTI_Core_TypeDef * EXTI_CurrentCPU;
#if defined(CORE_CM4)
EXTI_CurrentCPU = EXTI_C2; /* EXTI for CM4 CPU */
#else
EXTI_CurrentCPU = EXTI_C1; /* EXTI for CA7 CPU */
#endif
#endif
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
/* Get the current IO position */
iocurrent = (GPIO_Pin) & ioposition;
if(iocurrent == ioposition)
{
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO in Analog Mode */
GPIOx->MODER |= (GPIO_MODER_MODER0 << (position * 2));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEEDR0 << (position * 2));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
}
}
}
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
{
bitstatus = GPIO_PIN_SET;
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
}
/**
* @brief Sets or clears the selected data port bit.
*
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
*
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
if (PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER;
}
}
/**
* @brief Toggles the specified GPIO pins.
* @param GPIOx: Where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
if ((GPIOx->ODR & GPIO_Pin) != 0x00u)
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
}
}
GPIO_DirState HAL_GPIO_ReadDir(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
GPIO_DirState bitstatus;
if((GPIOx->MODER & GPIO_Pin*2) != (uint32_t)GPIO_PIN_RESET)
{
bitstatus = GPIO_DIR_OUTPUT;
}
else
{
bitstatus = GPIO_DIR_INPUT;
}
return bitstatus;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_i2c.c
Executable
+960
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@@ -0,0 +1,960 @@
/**
******************************************************************************
* @file stm32mp1xx_hal_i2c.c
* @author MCD Application Team
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral State and Errors functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The I2C HAL driver can be used as follows:
(#) Declare a I2C_HandleTypeDef handle structure, for example:
I2C_HandleTypeDef hi2c;
(#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API:
(##) Enable the I2Cx interface clock
(##) I2C pins configuration
(+++) Enable the clock for the I2C GPIOs
(+++) Configure I2C pins as alternate function open-drain
(##) NVIC configuration if you need to use interrupt process
(+++) Configure the I2Cx interrupt priority
(+++) Enable the NVIC I2C IRQ Channel
(##) DMA Configuration if you need to use DMA process
(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
(+++) Configure the DMA Tx or Rx stream
(+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
the DMA Tx or Rx stream
(#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
(#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware
(GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit(&hi2c) API.
(#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady()
(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
*** Polling mode IO operation ***
=================================
[..]
(+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit()
(+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive()
(+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit()
(+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive()
*** Polling mode IO MEM operation ***
=====================================
[..]
(+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write()
(+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read()
*** Interrupt mode IO operation ***
===================================
[..]
(+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT()
(+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
(+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT()
(+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
(+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT()
(+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
(+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT()
(+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
(+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
(+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** Interrupt mode or DMA mode IO sequential operation ***
==========================================================
[..]
(@) These interfaces allow to manage a sequential transfer with a repeated start condition
when a direction change during transfer
[..]
(+) A specific option field manage the different steps of a sequential transfer
(+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
(++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition, an then permit a call the same master sequential interface
several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT()
or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA())
(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and without a final stop condition in both cases
(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and with a final stop condition in both cases
(++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
without stopping the communication and so generate a restart condition.
(++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential
interface.
Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME)
or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME).
Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition.
(+) Differents sequential I2C interfaces are listed below:
(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT()
or using @ref HAL_I2C_Master_Seq_Transmit_DMA()
(+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
(++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT()
or using @ref HAL_I2C_Master_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
(++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
(+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
(++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT()
(+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can
add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
(+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback()
(++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT()
or using @ref HAL_I2C_Slave_Seq_Transmit_DMA()
(+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
(++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT()
or using @ref HAL_I2C_Slave_Seq_Receive_DMA()
(+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
(++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
(++) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** Interrupt mode IO MEM operation ***
=======================================
[..]
(+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
@ref HAL_I2C_Mem_Write_IT()
(+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
@ref HAL_I2C_Mem_Read_IT()
(+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
(+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
*** DMA mode IO operation ***
==============================
[..]
(+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
@ref HAL_I2C_Master_Transmit_DMA()
(+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback()
(+) Receive in master mode an amount of data in non-blocking mode (DMA) using
@ref HAL_I2C_Master_Receive_DMA()
(+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback()
(+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
@ref HAL_I2C_Slave_Transmit_DMA()
(+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback()
(+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
@ref HAL_I2C_Slave_Receive_DMA()
(+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback()
(+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
(+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT()
(+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback()
(+) Discard a slave I2C process communication using @ref __HAL_I2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** DMA mode IO MEM operation ***
=================================
[..]
(+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
@ref HAL_I2C_Mem_Write_DMA()
(+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback()
(+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
@ref HAL_I2C_Mem_Read_DMA()
(+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback()
(+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback()
*** I2C HAL driver macros list ***
==================================
[..]
Below the list of most used macros in I2C HAL driver.
(+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral
(+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral
(+) @ref __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
(+) @ref __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
(+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
(+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
(+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
*** Callback registration ***
=============================================
[..]
The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
to register an interrupt callback.
[..]
Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
(+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
(+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
(+) ListenCpltCallback : callback for end of listen mode.
(+) MemTxCpltCallback : callback for Memory transmission end of transfer.
(+) MemRxCpltCallback : callback for Memory reception end of transfer.
(+) ErrorCallback : callback for error detection.
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function.
[..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
[..]
Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
weak function.
@ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID.
This function allows to reset following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer.
(+) SlaveTxCpltCallback : callback for Slave transmission end of transfer.
(+) SlaveRxCpltCallback : callback for Slave reception end of transfer.
(+) ListenCpltCallback : callback for end of listen mode.
(+) MemTxCpltCallback : callback for Memory transmission end of transfer.
(+) MemRxCpltCallback : callback for Memory reception end of transfer.
(+) ErrorCallback : callback for error detection.
(+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit.
[..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
[..]
By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions:
examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
Exception done for MspInit and MspDeInit functions that are
reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when
these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
or @ref HAL_I2C_Init() function.
[..]
When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions.
[..]
(@) You can refer to the I2C HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32mp1xx_hal.h"
#include "los_sys.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup I2C_Private_Define I2C Private Define
* @{
*/
#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
#define MAX_NBYTE_SIZE 255U
#define SlaveAddr_SHIFT 7U
#define SlaveAddr_MSK 0x06U
/* Private define for @ref PreviousState usage */
#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
/* Private define to centralize the enable/disable of Interrupts */
#define I2C_XFER_TX_IT (0x00000001U)
#define I2C_XFER_RX_IT (0x00000002U)
#define I2C_XFER_LISTEN_IT (0x00000004U)
#define I2C_XFER_ERROR_IT (0x00000011U)
#define I2C_XFER_CPLT_IT (0x00000012U)
#define I2C_XFER_RELOAD_IT (0x00000012U)
/* Private define Sequential Transfer Options default/reset value */
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
/**
* @}
*/
/**
* @brief Initializes the I2C according to the specified parameters
* in the I2C_InitTypeDef and initialize the associated handle.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
/* Check the I2C handle allocation */
if (hi2c == NULL)
{
return HAL_ERROR;
}
if (hi2c->State == HAL_I2C_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
}
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
/* Configure I2Cx: Frequency range */
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
/* Disable Own Address1 before set the Own Address1 configuration */
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
/* Configure I2Cx: Own Address1 and ack own address1 mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
}
else /* I2C_ADDRESSINGMODE_10BIT */
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
}
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
}
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
/* Disable Own Address2 before set the Own Address2 configuration */
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
/* Configure I2Cx: Dual mode and Own Address2 */
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
/* Configure I2Cx: Generalcall and NoStretch mode */
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
/* Enable the selected I2C peripheral */
__HAL_I2C_ENABLE(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
return HAL_OK;
}
/**
* @brief DeInitialize the I2C peripheral.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
{
/* Check the I2C handle allocation */
if (hi2c == NULL)
{
return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the I2C Peripheral Clock */
__HAL_I2C_DISABLE(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_RESET;
hi2c->PreviousState = I2C_STATE_NONE;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Release Lock */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief I2C Tx data register flush process.
* @param hi2c I2C handle.
* @retval None
*/
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
{
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
{
hi2c->Instance->TXDR = 0x00U;
}
/* Flush TX register if not empty */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
}
}
/**
* @brief This function handles Acknowledge failed detection during an I2C Communication.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
/* Wait until STOP Flag is reset */
/* AutoEnd should be initiate after AF */
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((LOS_TickCountGet() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
}
/* Clear NACKF Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
* @param hi2c I2C handle.
* @param DevAddress Specifies the slave address to be programmed.
* @param Size Specifies the number of bytes to be programmed.
* This parameter must be a value between 0 and 255.
* @param Mode New state of the I2C START condition generation.
* This parameter can be one of the following values:
* @arg @ref I2C_RELOAD_MODE Enable Reload mode .
* @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
* @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
* @param Request New state of the I2C START condition generation.
* This parameter can be one of the following values:
* @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
* @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
* @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
* @retval None
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
/* update CR2 register */
MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
(uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**
* @brief This function handles I2C Communication Timeout.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Flag Specifies the I2C flag to check.
* @param Status The new Flag status (SET or RESET).
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((LOS_TickCountGet() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
}
return HAL_OK;
}
/**
* @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
{
if (((LOS_TickCountGet() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
}
return HAL_OK;
}
/**
* @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
if (((LOS_TickCountGet() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
{
/* Check if a NACK is detected */
if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check if a STOPF is detected */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
/* Check if an RXNE is pending */
/* Store Last receive data if any */
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
{
/* Return HAL_OK */
/* The Reading of data from RXDR will be done in caller function */
return HAL_OK;
}
else
{
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
/* Check for the Timeout */
if (((LOS_TickCountGet() - Tickstart) > Timeout) || (Timeout == 0U))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_ERROR;
}
}
return HAL_OK;
}
/**
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param DevAddress Target device address: The device 7 bits address value
* in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
if(hi2c == NULL)
{
return -1;
}
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = LOS_TickCountGet();
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferISR = NULL;
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
}
while (hi2c->XferCount > 0U)
{
/* Wait until TXIS flag is set */
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Write data to TXDR */
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferCount--;
hi2c->XferSize--;
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
uint32_t tickstart;
if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
/* Init tickstart for timeout management*/
tickstart = LOS_TickCountGet();
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
hi2c->State = HAL_I2C_STATE_BUSY_RX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
hi2c->XferISR = NULL;
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
}
while (hi2c->XferCount > 0U)
{
/* Wait until RXNE flag is set */
if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
/* Increment Buffer pointer */
hi2c->pBuffPtr++;
hi2c->XferSize--;
hi2c->XferCount--;
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
{
/* Wait until TCR flag is set */
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
}
else
{
hi2c->XferSize = hi2c->XferCount;
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
}
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear Configuration Register 2 */
I2C_RESET_CR2(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_ltdc.c
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common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c
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common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc_ex.c
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common/platform/stm32mp1xx_hal/STM32MP1xx_HAL_Driver/Src/system_stm32mp1xx.c
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/**
******************************************************************************
* @file system_stm32mp1xx.c
* @author MCD Application Team
* @brief CMSIS Cortex Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32mp1xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock frequency, it can
* be used by the user application to setup
* the SysTick timer or configure other
* parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
*
******************************************************************************
*
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32mp1xx_system
* @{
*/
/** @addtogroup STM32MP1xx_System_Private_Includes
* @{
*/
#include "stm32mp1xx_hal.h"
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/*!< Uncomment the following line if you need to use external SRAM mounted
on EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) each time HAL_RCC_ClockConfig() is called to configure the system clock
frequency
Note: If you use this function to configure the system clock;
then there is no need to call the first functions listed above,
since SystemCoreClock variable is updated automatically.
*/
uint32_t SystemCoreClock = HSI_VALUE;
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_FunctionPrototypes
* @{
*/
#if defined (DATA_IN_ExtSRAM)
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32MP1xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the FPU setting, vector table location and External memory
* configuration.
* @param None
* @retval None
*/
void Hal_SystemInit (void)
{
/* FPU settings ------------------------------------------------------------*/
// #if defined (CORE_CM4)
// #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
// SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
// #endif
// /* Configure the Vector Table location add offset address ------------------*/
// #if defined (VECT_TAB_SRAM)
// SCB->VTOR = MCU_AHB_SRAM | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
// #endif
// /* Disable all interrupts and events */
// CLEAR_REG(EXTI_C2->IMR1);
// CLEAR_REG(EXTI_C2->IMR2);
// CLEAR_REG(EXTI_C2->IMR3);
// CLEAR_REG(EXTI_C2->EMR1);
// CLEAR_REG(EXTI_C2->EMR2);
// CLEAR_REG(EXTI_C2->EMR3);
// #else
// #error Please #define CORE_CM4
// #endif
SystemCoreClockUpdate();
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock frequency (Hz),
* it can be used by the user application to setup the SysTick timer or
* configure other parameters.
*
* @note Each time the core clock changes, this function must be called to
* update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the
* HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the
* HSE_VALUE(**)
*
* - If SYSCLK source is CSI, SystemCoreClock will contain the
* CSI_VALUE(***)
*
* - If SYSCLK source is PLL3_P, SystemCoreClock will contain the
* HSI_VALUE(*) or the HSE_VALUE(*) or the CSI_VALUE(***)
* multiplied/divided by the PLL3 factors.
*
* (*) HSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
* (default value 64 MHz) but the real value may vary depending
* on the variations in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
* (default value 24 MHz), user has to ensure that HSE_VALUE is
* same as the real frequency of the crystal used. Otherwise, this
* function may have wrong result.
*
* (***) CSI_VALUE is a constant defined in stm32mp1xx_hal_conf.h file
* (default value 4 MHz)but the real value may vary depending
* on the variations in voltage and temperature.
*
* - The result of this function could be not correct when using
* fractional value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t pllsource, pll3m, pll3fracen;
float fracn1, pll3vco;
switch (RCC->MSSCKSELR & RCC_MSSCKSELR_MCUSSRC)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = (HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV));
break;
case 0x01: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x02: /* CSI used as system clock source */
SystemCoreClock = CSI_VALUE;
break;
case 0x03: /* PLL3_P used as system clock source */
pllsource = (RCC->RCK3SELR & RCC_RCK3SELR_PLL3SRC);
pll3m = ((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVM3) >> RCC_PLL3CFGR1_DIVM3_Pos) + 1U;
pll3fracen = (RCC->PLL3FRACR & RCC_PLL3FRACR_FRACLE) >> 16U;
fracn1 = (pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_FRACV) >> 3U));
pll3vco = (((RCC->PLL3CFGR1 & RCC_PLL3CFGR1_DIVN) + 1U) + (fracn1/0x1FFFU));
if (pll3m != 0U)
{
switch (pllsource)
{
case 0x00: /* HSI used as PLL clock source */
pll3vco *= ((HSI_VALUE >> (RCC->HSICFGR & RCC_HSICFGR_HSIDIV)) / pll3m);
break;
case 0x01: /* HSE used as PLL clock source */
pll3vco *= (HSE_VALUE / pll3m);
break;
case 0x02: /* CSI used as PLL clock source */
pll3vco *= (CSI_VALUE / pll3m);
break;
case 0x03: /* No clock source for PLL */
pll3vco = 0U;
break;
}
SystemCoreClock = (uint32_t)(pll3vco/((RCC->PLL3CFGR2 & RCC_PLL3CFGR2_DIVP) + 1U));
}
else
{
SystemCoreClock = 0U;
}
break;
}
/* Compute mcu_ck */
SystemCoreClock = SystemCoreClock >> (RCC->MCUDIVR & RCC_MCUDIVR_MCUDIV);
}
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32L4xx.s before jump to main.
* This function configures the external SRAM mounted on Eval boards
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
}
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
common/platform/uart/BUILD.gn
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import("//drivers/adapter/khdf/liteos/hdf.gni")
module_switch = defined(LOSCFG_DRIVERS_HDF_PLATFORM_UART)
module_name = "hdf_uart"
hdf_driver(module_name) {
sources = [
"stm32mp1_uart.c",
"stm32mp1_uart_hw.c",
"KRecvBuf.c"
]
}
common/platform/uart/KRecvBuf.c
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/*
* Copyright (c) 2022 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "KRecvBuf.h"
#include "osal.h"
#include "securec.h"
#include "user_copy.h"
#define HDF_LOG_TAG KRecvBuf
#define MIN(a,b) (((a)<(b))?(a):(b))
UINT32 KRecvBufUsedSize(KRecvBuf *krbCB)
{
UINT32 size;
UINT32 intSave;
LOS_SpinLockSave(&krbCB->lock, &intSave);
size = krbCB->size - krbCB->remain;
LOS_SpinUnlockRestore(&krbCB->lock, intSave);
return size;
}
STATIC UINT32 KRecvBufWriteLinear(KRecvBuf *krbCB, const CHAR *buf, UINT32 size)
{
UINT32 cpSize;
errno_t err;
// get copy size
cpSize = MIN(krbCB->remain, size);
if (cpSize == 0) {
return 0;
}
// copy to buffer
err = memcpy_s(krbCB->fifo + krbCB->wIdx, MIN((krbCB->size - krbCB->wIdx), krbCB->remain), buf, cpSize);
if (err != EOK) {
HDF_LOGE("%s: something is wrong in memcpy_s.\r\n", __func__);
return 0;
}
krbCB->remain -= cpSize;
krbCB->wIdx += cpSize;
// write point roll to start
if (krbCB->wIdx >= krbCB->size) {
krbCB->wIdx = 0;
}
return cpSize;
}
STATIC UINT32 KRecvBufWriteLoop(KRecvBuf *krbCB, const CHAR *buf, UINT32 size)
{
UINT32 right, cpSize;
// get upper part space
right = krbCB->size - krbCB->wIdx;
// get upper part copy size
cpSize = MIN(right, size);
// copy upper part
cpSize = KRecvBufWriteLinear(krbCB, buf, cpSize);
if (cpSize == 0) {
HDF_LOGE("%s: something is wrong in KRecvBufWriteLinear.\r\n", __func__);
return 0;
}
// copy lower part (if needed)
if (cpSize != size) {
cpSize += KRecvBufWriteLinear(krbCB, buf + cpSize, size - cpSize);
}
return cpSize;
}
UINT32 KRecvBufWrite(KRecvBuf *krbCB, const CHAR *buf, UINT32 size)
{
UINT32 cpSize;
if ((krbCB == NULL) || (buf == NULL) || (size == 0)) {
return 0;
}
if ((krbCB->fifo == NULL) || (krbCB->remain == 0)) {
return 0;
}
if (krbCB->rIdx <= krbCB->wIdx) {
cpSize = KRecvBufWriteLoop(krbCB, buf, size);
} else {
cpSize = KRecvBufWriteLinear(krbCB, buf, size);
}
return cpSize;
}
STATIC UINT32 KRecvBufReadLinear(KRecvBuf *krbCB, const CHAR *buf, UINT32 size)
{
UINT32 cpSize;
errno_t err;
// this time max size
cpSize = MIN((krbCB->size - krbCB->remain),(krbCB->size - krbCB->rIdx));
// copy size
cpSize = MIN(cpSize, size);
if (cpSize == 0) {
return 0;
}
// copy data to user space
err = LOS_CopyFromKernel((void *)buf, size, (void *)(krbCB->fifo + krbCB->rIdx), cpSize);
// err = memcpy_s(buf, size, krbCB->fifo + krbCB->rIdx, cpSize);
if (err != EOK) {
return 0;
}
krbCB->remain += cpSize;
krbCB->rIdx += cpSize;
if (krbCB->rIdx >= krbCB->size) {
krbCB->rIdx = 0;
}
return cpSize;
}
STATIC UINT32 KRecvBufReadLoop(KRecvBuf *krbCB, const CHAR *buf, UINT32 size)
{
UINT32 right, cpSize;
// get upper part size
right = krbCB->size - krbCB->rIdx;
// get upper part copy size
cpSize = MIN(right, size);
// copy upper part
cpSize = KRecvBufReadLinear(krbCB, buf, cpSize);
if (cpSize == 0) {
HDF_LOGE("%s: something is wrong in KRecvBufReadLinear.\r\n", __func__);
return 0;
}
// copy lower part (if needed)
if (cpSize < size) {
cpSize += KRecvBufReadLinear(krbCB, buf + cpSize, size - cpSize);
}
return cpSize;
}
UINT32 KRecvBufRead(KRecvBuf *krbCB, CHAR *buf, UINT32 size)
{
UINT32 cpSize;
if ((krbCB == NULL) || (buf == NULL) || (size == 0)) {
return 0;
}
if ((krbCB->fifo == NULL) || (krbCB->remain == krbCB->size)) {
return 0;
}
if (krbCB->rIdx >= krbCB->wIdx) {
cpSize = KRecvBufReadLoop(krbCB, buf, size);
} else {
cpSize = KRecvBufReadLinear(krbCB, buf, size);
}
return cpSize;
}
UINT32 KRecvBufInit(KRecvBuf *krbCB, CHAR *fifo, UINT32 size)
{
if ((krbCB == NULL) || (fifo == NULL)) {
return LOS_NOK;
}
(VOID)memset_s(krbCB, sizeof(KRecvBuf), 0, sizeof(KRecvBuf));
LOS_SpinInit(&krbCB->lock);
krbCB->size = size;
krbCB->remain = size;
krbCB->status = BUF_USED;
krbCB->fifo = fifo;
return LOS_OK;
}
VOID KRecvBufDeinit(KRecvBuf *krbCB)
{
(VOID)memset_s(krbCB, sizeof(KRecvBuf), 0, sizeof(KRecvBuf));
}
VOID KRecvBufDump(KRecvBuf *krbCB)
{
dprintf("\r\nKRecvBufDump : \r\n");
dprintf("\r\n rIdx : %d\r\n", krbCB->rIdx);
dprintf("\r\n wIdx : %d\r\n", krbCB->wIdx);
dprintf("\r\n size : %d\r\n", krbCB->size);
dprintf("\r\n status : %d\r\n", krbCB->status);
dprintf("\r\n remain : %d\r\n", krbCB->remain);
dprintf("\r\n status : %d\r\n", krbCB->status);
}
common/platform/uart/KRecvBuf.h
Executable
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/*
* Copyright (c) 2022 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _KRECVBUF_H_
#define _KRECVBUF_H_
#include "stdio.h"
#include "stdlib.h"
#include "string.h"
#include "los_typedef.h"
#include "los_spinlock.h"
typedef enum {
BUF_UNUSED = 0,
BUF_USED = 1
} KRecvBufStatus;
typedef enum {
EVENTS_NEW_DATA = 0x01
} KRecvBufEvents;
typedef struct {
UINT32 wIdx;
UINT32 rIdx;
UINT32 size;
UINT32 remain;
SPIN_LOCK_S lock;
KRecvBufStatus status;
CHAR *fifo;
} KRecvBuf;
extern UINT32 KRecvBufInit(KRecvBuf *krbCB, CHAR *fifo, UINT32 size);
extern VOID KRecvBufDeinit(KRecvBuf *krbCB);
extern UINT32 KRecvBufWrite(KRecvBuf *krbCB, const CHAR *buf, UINT32 size);
extern UINT32 KRecvBufRead(KRecvBuf *krbCB, CHAR *buf, UINT32 size);
extern UINT32 KRecvBufUsedSize(KRecvBuf *krbCB);
extern VOID KRecvBufDump(KRecvBuf *krbCB);
#endif
common/platform/uart/stm32mp1_uart.c
Executable
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/*
* Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "device_resource_if.h"
#include "hdf_device_desc.h"
#include "osal_io.h"
#include "osal.h"
#include "uart_if.h"
#include "uart_core.h"
#include "uart_dev.h"
#include "securec.h"
#include "stm32mp1_uart_hw.h"
#define HDF_LOG_TAG Mp15xUart
#ifdef LOSCFG_QUICK_START
__attribute__ ((section(".data"))) uint32_t g_uart_fputc_en = 0;
#else
__attribute__ ((section(".data"))) uint32_t g_uart_fputc_en = 1;
#endif
static SPIN_LOCK_INIT(g_uartOutputSpin);
// for default out put
VOID UartPuts(const CHAR *s, UINT32 len, BOOL isLock)
{
uint32_t intSave;
void *base = (void *)IO_DEVICE_ADDR(DEBUG_UART_BASE);
if (isLock) {
LOS_SpinLockSave(&g_uartOutputSpin, &intSave);
}
Mp15xUartHwPuts(base, (char *)s, len);
if (isLock) {
LOS_SpinUnlockRestore(&g_uartOutputSpin, intSave);
}
}
static uint32_t stm32mp1_uart_recv_data_handle(struct Mp15xUart *uart, char *buf, uint32_t size)
{
uint32_t ret;
struct Mp15xUartRxCtl *rx_ctl = &(uart->rx_ctl);
// write data to recv buf
ret = KRecvBufWrite(&(rx_ctl->rx_krb), buf, size);
// if write success, post sem
if (ret != 0)
OsalSemPost(&(rx_ctl->rx_sem));
return HDF_SUCCESS;
}
static int32_t stm32mp1_uart_rx_ctl_init(struct Mp15xUartRxCtl *rx_ctl, uint32_t buf_size)
{
char *buf = NULL;
// 获取接收缓冲区
buf = OsalMemAlloc(buf_size);
if (buf == NULL) {
HDF_LOGE("%s: create recv buf fail.\r\n", __func__);
return HDF_FAILURE;
}
rx_ctl->fifo = buf;
OsalSemInit(&(rx_ctl->rx_sem), 0);
// 初始化KRecvBuf
KRecvBufInit(&(rx_ctl->rx_krb), rx_ctl->fifo, buf_size);
// 串口数据接收处理函数
rx_ctl->stm32mp1_uart_recv_hook = stm32mp1_uart_recv_data_handle;
return HDF_SUCCESS;
}
static int32_t stm32mp1_uart_rx_ctl_deinit(struct Mp15xUartRxCtl *rx_ctl)
{
char *buf = rx_ctl->fifo;
rx_ctl->stm32mp1_uart_recv_hook = NULL;
KRecvBufDeinit(&(rx_ctl->rx_krb));
OsalSemDestroy(&(rx_ctl->rx_sem));
if (buf) {
OsalMemFree(buf);
}
return HDF_SUCCESS;
}
// update regs
static int32_t stm32mp1_uart_config(struct Mp15xUart *uart)
{
int32_t ret;
struct UartAttribute *attr = (struct UartAttribute *)uart->priv;
// set bits
ret = Mp15xUartHwDataBits(uart, attr->dataBits);
// set stop bits
ret |= Mp15xUartHwStopBits(uart, attr->stopBits);
// set parity
ret |= Mp15xUartHwParity(uart, attr->parity);
return ret;
}
// TODO : get clock source real rate
static inline int32_t Mp15xUartGetClock(struct Mp15xUart *uart)
{
int ret = HDF_SUCCESS;
/*
if "clock_source" is set, use the real rate of clock source
otherwise, use the default clock rate
*/
if (uart->clock_source != NULL) {
// get clock source real rate.
// ...
ret = HDF_SUCCESS;
}
return ret;
}
static int32_t Mp15xUartOpen(struct UartHost *host)
{
int32_t ret = HDF_SUCCESS;
struct Mp15xUart *uart = (struct Mp15xUart *)host->priv;
struct Mp15xUartRxCtl *rx_ctl = &(uart->rx_ctl);
OsalSpinLock(&(uart->lock));
if (uart->state == UART_STATE_NOT_OPENED) {
uart->state = UART_STATE_OPENING;
// 1. disable
Mp15xUartHwEnable(uart, false);
// 2. update attr
ret = stm32mp1_uart_config(uart);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: uart config fail.", __func__);
goto stm32mp1_uart_open_out;
}
// 3. update baudrate
Mp15xUartHwBaudrate(uart, uart->baudrate);
// 4. init rx_ctl
ret = stm32mp1_uart_rx_ctl_init(rx_ctl, uart->rx_buf_size);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: rx ctl init fail.", __func__);
goto stm32mp1_uart_open_out;
}
// 5. enable uart rx
ret = Mp15xUartHwRxEnable(uart, true);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: rx enable fail.", __func__);
goto stm32mp1_uart_open_out;
}
// 6. enable uart
Mp15xUartHwEnable(uart, true);
Mp15xUartDump(uart);
}
stm32mp1_uart_open_out:
// current uart is opened
if (ret == HDF_SUCCESS) {
uart->state = UART_STATE_USEABLE;
uart->open_count++;
} else {
uart->state = UART_STATE_NOT_OPENED;
}
OsalSpinUnlock(&(uart->lock));
return ret;
}
static int32_t Mp15xUartClose(struct UartHost *host)
{
int32_t ret = HDF_SUCCESS;
struct Mp15xUart *uart = (struct Mp15xUart *)host->priv;
struct Mp15xUartRxCtl *rx_ctl = &(uart->rx_ctl);
OsalSpinLock(&(uart->lock));
if (--uart->open_count > 0) goto stm32mp1_uart_close_out;
// 失能设备
Mp15xUartHwEnable(uart, false);
// 关闭串口接收
Mp15xUartHwRxEnable(uart, false);
// 注销接收控制器
ret = stm32mp1_uart_rx_ctl_deinit(rx_ctl);
uart->state = UART_STATE_NOT_OPENED;
stm32mp1_uart_close_out:
OsalSpinUnlock(&(uart->lock));
return ret;
}
static int32_t Mp15xUartRead(struct UartHost *host, uint8_t *data, uint32_t size)
{
int32_t ret = HDF_SUCCESS;
struct Mp15xUart *uart = (struct Mp15xUart *)host->priv;
struct Mp15xUartRxCtl *rx_ctl = &(uart->rx_ctl);
OsalSpinLock(&(uart->lock));
if (uart->state != UART_STATE_USEABLE) {
HDF_LOGE("%s: device not opened.\r\n", __func__);
ret = HDF_ERR_IO;
goto stm32mp1_uart_read_out;
}
// 如果缓冲区中没有数据可以读取, 且当前是阻塞模式, 等待数据接收
while ((KRecvBufUsedSize(&(rx_ctl->rx_krb)) == 0)
&& (uart->flags & UART_FLG_RD_BLOCK))
{
OsalSpinUnlock(&(uart->lock));
OsalSemWait(&(rx_ctl->rx_sem), OSAL_WAIT_FOREVER);
OsalSpinLock(&(uart->lock));
}
// 接收数据
ret = KRecvBufRead(&(rx_ctl->rx_krb), (char *)data, size);
stm32mp1_uart_read_out:
OsalSpinUnlock(&(uart->lock));
return ret;
}
static int32_t Mp15xUartWrite(struct UartHost *host, uint8_t *data, uint32_t size)
{
int32_t ret;
uint32_t intSave;
uint32_t send_size = 0, cur_size = 0;
struct Mp15xUart *uart = (struct Mp15xUart *)host->priv;
if (host == NULL || host->priv == NULL || data == NULL) {
HDF_LOGE("%s: invalid parameter.\r\n", __func__);
return HDF_ERR_INVALID_PARAM;
}
OsalSpinLock(&(uart->lock));
// current device is debug uart, get global output lock
if (uart->debug_uart) {
LOS_SpinLockSave(&g_uartOutputSpin, &intSave);
}
if (uart->state != UART_STATE_USEABLE) {
HDF_LOGE("%s: device not opened.\r\n", __func__);
ret = HDF_ERR_IO;
goto stm32mp1_uart_write_out;
}
while (send_size < size)
{
// 获取本次传输的大小
cur_size = ((size - send_size) >= TX_BUF_SIZE)?TX_BUF_SIZE:(size - send_size);
ret = LOS_CopyToKernel((void *)uart->tx_buf, TX_BUF_SIZE, (void *)(data + send_size), cur_size);
if (ret != 0) {
HDF_LOGE("%s: CopyToKernel fail, size : %d, ret : %d.\r\n", __func__, cur_size, ret);
ret = HDF_FAILURE;
goto stm32mp1_uart_write_out;
}
Mp15xUartHwPuts((void *)uart->base, uart->tx_buf, cur_size);
send_size += cur_size;
}
stm32mp1_uart_write_out:
if (uart->debug_uart) {
LOS_SpinUnlockRestore(&g_uartOutputSpin, intSave);
}
OsalSpinUnlock(&(uart->lock));
return send_size;
}
static int32_t Mp15xUartGetBaud(struct UartHost *host, uint32_t *baudRate)
{
int32_t ret = HDF_SUCCESS;
struct Mp15xUart *uart = (struct Mp15xUart *)host->priv;
OsalSpinLock(&(uart->lock));
if (uart->state != UART_STATE_USEABLE) {
ret = HDF_FAILURE;
goto stm32mp1_uart_get_baud_out;
}
*baudRate = uart->baudrate;
stm32mp1_uart_get_baud_out:
OsalSpinUnlock(&(uart->lock));
return ret;
}
static int32_t Mp15xUartSetBaud(struct UartHost *host, uint32_t baudRate)
{
int32_t ret = HDF_SUCCESS;
struct Mp15xUart *uart = (struct Mp15xUart *)host->priv;
OsalSpinLock(&(uart->lock));
if (uart->state != UART_STATE_USEABLE) {
ret = HDF_FAILURE;
goto stm32mp1_uart_set_baud_out;
}
// set new baudrate
if (uart->baudrate != baudRate) {
// 1. disable uart
Mp15xUartHwEnable(uart, false);
// 2. update clock rate
Mp15xUartGetClock(uart);
// 3. set regs
Mp15xUartHwBaudrate(uart, baudRate);
// 4. enable uart
Mp15xUartHwEnable(uart, true);
uart->baudrate = baudRate;
}
stm32mp1_uart_set_baud_out:
OsalSpinUnlock(&(uart->lock));
return ret;
}
static int32_t Mp15xUartGetAttribute(struct UartHost *host, struct UartAttribute *attribute)
{
int32_t ret = HDF_SUCCESS;
struct Mp15xUart *uart = (struct Mp15xUart *)host->priv;
struct UartAttribute *attr = (struct UartAttribute *)uart->priv;
OsalSpinLock(&(uart->lock));
memcpy_s(attribute, sizeof(struct UartAttribute), attr, sizeof(struct UartAttribute));
OsalSpinUnlock(&(uart->lock));
return ret;
}
static int32_t Mp15xUartSetAttribute(struct UartHost *host, struct UartAttribute *attribute)
{
int32_t ret = HDF_SUCCESS;
struct Mp15xUart *uart = (struct Mp15xUart *)host->priv;
struct UartAttribute *attr = (struct UartAttribute *)uart->priv;
OsalSpinLock(&(uart->lock));
// 1. check attr
if (attribute->dataBits != UART_ATTR_DATABIT_8 || attribute->stopBits != UART_ATTR_STOPBIT_1) {
HDF_LOGE("%s: unsupport databits or stopbit.\r\n", __func__);
ret = HDF_FAILURE;
goto stm32mp1_uart_set_attribute_out;
}
// 保存新配置
memcpy_s(attr, sizeof(struct UartAttribute), attribute, sizeof(struct UartAttribute));
// 根据新配置，更新寄存器
ret = stm32mp1_uart_config(uart);
stm32mp1_uart_set_attribute_out:
OsalSpinUnlock(&(uart->lock));
return ret;
}
static int32_t Mp15xUartSetTransMode(struct UartHost *host, enum UartTransMode mode)
{
int32_t ret = HDF_SUCCESS;
struct Mp15xUart *uart = (struct Mp15xUart *)host->priv;
struct Mp15xUartRxCtl *rx_ctl = &(uart->rx_ctl);
OsalSpinLock(&(uart->lock));
switch (mode)
{
case UART_MODE_RD_BLOCK:
uart->flags |= UART_FLG_RD_BLOCK;
break;
case UART_MODE_RD_NONBLOCK:
uart->flags &= ~UART_FLG_RD_BLOCK;
OsalSemPost(&(rx_ctl->rx_sem));
break;
default:
HDF_LOGE("%s: unsupport mode %#x.\r\n", __func__, mode);
break;
}
OsalSpinUnlock(&(uart->lock));
return ret;
}
struct UartHostMethod g_stm32mp1_uart_ops = {
.Init = Mp15xUartOpen,
.Deinit = Mp15xUartClose,
.Read = Mp15xUartRead,
.Write = Mp15xUartWrite,
.GetBaud = Mp15xUartGetBaud,
.SetBaud = Mp15xUartSetBaud,
.GetAttribute = Mp15xUartGetAttribute,
.SetAttribute = Mp15xUartSetAttribute,
.SetTransMode = Mp15xUartSetTransMode,
.pollEvent = NULL
};
static int32_t stm32mp1_uart_read_drs(struct Mp15xUart *uart, const struct DeviceResourceNode *node)
{
int32_t ret;
struct DeviceResourceIface *drsOps = NULL;
drsOps = DeviceResourceGetIfaceInstance(HDF_CONFIG_SOURCE);
if (drsOps == NULL || drsOps->GetUint32 == NULL) {
HDF_LOGE("%s: invalid drs ops!\r\n", __func__);
return HDF_FAILURE;
}
// num
ret = drsOps->GetUint32(node, "num", &uart->num, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read num fail!\r\n", __func__);
return ret;
}
// reg_base
ret = drsOps->GetUint32(node, "reg_base", &uart->phy_base, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read reg_base fail!\r\n", __func__);
return ret;
}
// reg_step
ret = drsOps->GetUint32(node, "reg_step", &uart->reg_step, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read reg_step fail!\r\n", __func__);
return ret;
}
// flags
ret = drsOps->GetUint32(node, "flags", &uart->flags, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read flags fail!\r\n", __func__);
return ret;
}
// baudrate
ret = drsOps->GetUint32(node, "baudrate", &uart->baudrate, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read baudrate fail!\r\n", __func__);
return ret;
}
// rx_buf_size
ret = drsOps->GetUint32(node, "rx_buf_size", &uart->rx_buf_size, 4096);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read rx_buf_size fail!\r\n", __func__);
return ret;
}
// irq_num
ret = drsOps->GetUint32(node, "interrupt", &uart->irq_num, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read interrupt fail!\r\n", __func__);
return ret;
}
// clock_rate
ret = drsOps->GetUint32(node, "clock_rate", &uart->clock_rate, 0);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read clock_rate fail!\r\n", __func__);
return ret;
}
// fifo_en
uart->fifo_en = drsOps->GetBool(node, "fifo_en");
return HDF_SUCCESS;
}
static int32_t Mp15xUartBind(struct HdfDeviceObject *device)
{
int32_t ret;
struct UartHost *host = NULL;
struct Mp15xUart *uart = NULL;
struct UartAttribute *attr = NULL;
if (device == NULL || device->property == NULL) {
HDF_LOGE("%s: device or property is null!.\r\n", __func__);
return HDF_ERR_INVALID_OBJECT;
}
// 创建UartHost
host = UartHostCreate(device);
if (host == NULL) {
HDF_LOGE("%s: UartHostCreate fail!.\r\n", __func__);
return HDF_ERR_MALLOC_FAIL;
}
// 申请内存空间
uart = (struct Mp15xUart *)OsalMemCalloc(sizeof(struct Mp15xUart));
if (uart == NULL) {
HDF_LOGE("%s: malloc uart fail!.\r\n", __func__);
return HDF_ERR_MALLOC_FAIL;
}
// attr
attr = (struct UartAttribute *)OsalMemCalloc(sizeof(struct UartAttribute));
if (uart == NULL) {
HDF_LOGE("%s: malloc attr fail!.\r\n", __func__);
OsalMemFree(uart);
return HDF_ERR_MALLOC_FAIL;
}
uart->priv = (void *)attr;
// 解析配置
ret = stm32mp1_uart_read_drs(uart, device->property);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: read drs fail:%d.\r\n", __func__, ret);
OsalMemFree(attr);
OsalMemFree(uart);
return ret;
}
// 寄存器映射
uart->base = OsalIoRemap(uart->phy_base, uart->reg_step);
if (uart->base == NULL) {
HDF_LOGE("%s: ioremap regbase fail!.\r\n", __func__);
OsalMemFree(attr);
OsalMemFree(uart);
return HDF_ERR_IO;
}
// 填充私有属性
host->method = &g_stm32mp1_uart_ops;
host->priv = uart;
host->num = uart->num;
return HDF_SUCCESS;
}
static int32_t Mp15xUartInit(struct HdfDeviceObject *device)
{
int32_t ret = HDF_SUCCESS;
struct UartHost *host = NULL;
struct Mp15xUart *uart = NULL;
if (device == NULL) {
HDF_LOGE("%s: device is null.\r\n", __func__);
return HDF_FAILURE;
}
host = UartHostFromDevice(device);
if (host == NULL) {
HDF_LOGE("%s: host is null.\r\n", __func__);
return HDF_FAILURE;
}
uart = (struct Mp15xUart *)host->priv;
if (uart == NULL) {
HDF_LOGE("%s: uart is null.\r\n", __func__);
return HDF_FAILURE;
}
// 1. spin init
ret = OsalSpinInit(&(uart->lock));
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: OsalSpinInit fail.\r\n", __func__);
return HDF_FAILURE;
}
OsalSpinLock(&(uart->lock));
Mp15xUartDump(uart);
// 2. get new clock rate
Mp15xUartGetClock(uart);
// 3. disable uart
Mp15xUartHwEnable(uart, false);
// 4. fifo mode enable
Mp15xUartHwFifoEnable(uart, uart->fifo_en);
// 5. register irq
snprintf_s(uart->irq_name, UART_IRQ_NAME_SIZE, UART_IRQ_NAME_SIZE - 1, "uart%d_irq", uart->num);
ret = OsalRegisterIrq(uart->irq_num, 0, Mp15xUartIrqHandler, uart->irq_name, uart);
if (ret != HDF_SUCCESS) {
HDF_LOGE("%s: OsalRegisterIrq fail.\r\n", __func__);
ret = HDF_FAILURE;
goto stm32mp1_uart_init_out;
}
// 6. register uart device
UartAddDev(host);
// 7. 当前串口是否作为调试串口(如果是调试串口，打印时需要获取全局锁)
if (uart->phy_base == DEBUG_UART_BASE)
uart->debug_uart = true;
stm32mp1_uart_init_out:
OsalSpinUnlock(&(uart->lock));
return ret;
}
static void Mp15xUartRelease(struct HdfDeviceObject *device)
{
struct UartHost *host = NULL;
struct Mp15xUart *uart = NULL;
if (device == NULL) {
HDF_LOGE("%s: device is null.\r\n", __func__);
return;
}
host = UartHostFromDevice(device);
if (host == NULL) {
HDF_LOGE("%s: host is null.\r\n", __func__);
return;
}
uart = (struct Mp15xUart *)host->priv;
if (uart == NULL) {
HDF_LOGE("%s: uart is null.\r\n", __func__);
return;
}
OsalSpinLock(&(uart->lock));
if (uart->state != UART_STATE_NOT_OPENED) {
HDF_LOGE("%s: device is opened!!!.\r\n", __func__);
OsalSpinUnlock(&(uart->lock));
return;
}
UartRemoveDev(host);
OsalUnregisterIrq(uart->irq_num, uart);
// disable
Mp15xUartHwEnable(uart, false);
OsalSpinUnlock(&(uart->lock));
OsalSpinDestroy(&(uart->lock));
// unmap
OsalIoUnmap((void *)uart->base);
OsalMemFree(uart->priv);
OsalMemFree(uart);
UartHostDestroy(host);
}
struct HdfDriverEntry g_hdf_driver_uart_entry = {
.moduleVersion = 1,
.Bind = Mp15xUartBind,
.Init = Mp15xUartInit,
.Release = Mp15xUartRelease,
.moduleName = "stm32mp1_uart",
};
HDF_INIT(g_hdf_driver_uart_entry);
common/platform/uart/stm32mp1_uart_hw.c
Executable
+285
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@@ -0,0 +1,285 @@
/*
* Copyright (c) 2022 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "stm32mp1_uart_hw.h"
#include "los_magickey.h"
#include "console.h"
// offset
#define USART_CR1 (0x00)
#define USART_CR2 (0x04)
#define USART_CR3 (0x08)
#define USART_BRR (0x0C)
#define USART_GTPR (0x10)
#define USART_RTOR (0x14)
#define USART_RQR (0x18)
#define USART_ISR (0x1C)
#define USART_ICR (0x20)
#define USART_RDR (0x24)
#define USART_TDR (0x28)
#define USART_PRESC (0x2C)
#define USART_CR1_EN BIT(0) // 串口使能
#define USART_CR1_RE BIT(2) // 串口接收使能
#define USART_CR1_TE BIT(3) // 串口发送使能
#define USART_CR1_RXNEIE BIT(5) // 串口接收中断使能
#define USART_CR1_FIFOEN BIT(29)// fifo模式使能
#define USART_ISR_TXE BIT(7) // 该位为 1 表示可以写
#define USART_ISR_RXNE BIT(5) // 该位为 1 表示可读
/* Parity control enable */
#define USART_CR1_PCE BIT(10) // 串口校验使能
#define USART_CR1_PS BIT(9)
/* word length */
#define USART_CR1_M0 BIT(12)
#define USART_CR1_M1 BIT(28)
#define USART_CR1_WL_MASK (USART_CR1_M0 | USART_CR1_M1)
#define USART_CR1_WL_8B (0)
#define USART_CR1_WL_9B (USART_CR1_M0)
#define USART_CR1_WL_7B (USART_CR1_M1)
/* stop bit */
#define USART_CR2_STOP_OFFSET (12)
#define USART_CR2_STOP_MASK ((0x3) << USART_CR2_STOP_OFFSET)
#define USART_CR2_STOP_1P ((0x0) << USART_CR2_STOP_OFFSET)
#define USART_CR2_STOP_P5 ((0x1) << USART_CR2_STOP_OFFSET)
#define USART_CR2_STOP_2P ((0x2) << USART_CR2_STOP_OFFSET)
#define USART_CR2_STOP_1P5 ((0x3) << USART_CR2_STOP_OFFSET)
static inline uint32_t RegRead(void volatile *base, uint32_t reg)
{
return OSAL_READL((uintptr_t)base + reg);
}
static inline void RegWrite(void volatile *base, uint32_t reg, uint32_t val)
{
OSAL_WRITEL(val, (uintptr_t)base + reg);
}
void Mp15xUartDump(struct Mp15xUart *uart)
{
#ifdef STM32MP1_UART_DEBUG
dprintf("-------------------------------------\r\n");
dprintf("USART_CR1 : %#x.\r\n", RegRead(uart->base, USART_CR1));
dprintf("USART_CR2 : %#x.\r\n", RegRead(uart->base, USART_CR2));
dprintf("USART_CR3 : %#x.\r\n", RegRead(uart->base, USART_CR3));
dprintf("USART_BRR : %#x.\r\n", RegRead(uart->base, USART_BRR));
dprintf("USART_GTPR : %#x.\r\n", RegRead(uart->base, USART_GTPR));
dprintf("USART_RTOR : %#x.\r\n", RegRead(uart->base, USART_RTOR));
dprintf("USART_ISR : %#x.\r\n", RegRead(uart->base, USART_ISR));
dprintf("USART_ICR : %#x.\r\n", RegRead(uart->base, USART_ICR));
dprintf("USART_RDR : %#x.\r\n", RegRead(uart->base, USART_RDR));
dprintf("USART_TDR : %#x.\r\n", RegRead(uart->base, USART_TDR));
dprintf("USART_PRESC : %#x.\r\n", RegRead(uart->base, USART_PRESC));
dprintf("-------------------------------------\r\n");
#endif
}
int32_t Mp15xUartHwRxEnable(struct Mp15xUart *uart, int enable)
{
uint32_t val;
val = RegRead(uart->base, USART_CR1);
if (enable) {
val |= USART_CR1_RXNEIE;
} else {
val &= ~USART_CR1_RXNEIE;
}
RegWrite(uart->base, USART_CR1, val);
return 0;
}
void Mp15xUartHwPutc(void *base, char c)
{
while ((RegRead(base, USART_ISR) & USART_ISR_TXE) == 0) {};
RegWrite(base, USART_TDR, c);
}
void Mp15xUartHwPuts(void *base, char *s, uint32_t len)
{
uint32_t i;
for (i = 0; i < len; i++) {
if (*(s + i) == '\n') {
Mp15xUartHwPutc(base, '\r');
}
Mp15xUartHwPutc(base, *(s + i));
}
}
uint32_t Mp15xUartHwGetIsr(struct Mp15xUart *uart)
{
return RegRead(uart->base, USART_ISR);
}
// enable uart, and enable tx/rx mode
int32_t Mp15xUartHwEnable(struct Mp15xUart *uart, int enable)
{
uint32_t val;
val = RegRead(uart->base, USART_CR1);
val &= ~(USART_CR1_EN | USART_CR1_RE | USART_CR1_TE);
if (enable) {
val |= (USART_CR1_EN | USART_CR1_RE | USART_CR1_TE);
} else {
val &= ~(USART_CR1_EN | USART_CR1_RE | USART_CR1_TE);
}
RegWrite(uart->base, USART_CR1, val);
return 0;
}
int32_t Mp15xUartHwFifoEnable(struct Mp15xUart *uart, int enable)
{
uint32_t val;
val = RegRead(uart->base, USART_CR1);
if (enable) {
val |= USART_CR1_FIFOEN; // fifo mode enable
} else {
val &= ~USART_CR1_FIFOEN; // fifo mode disable
}
RegWrite(uart->base, USART_CR1, val);
return 0;
}
// set data bits
int32_t Mp15xUartHwDataBits(struct Mp15xUart *uart, uint32_t bits)
{
uint32_t val;
val = RegRead(uart->base, USART_CR1);
val &= ~USART_CR1_WL_MASK;
switch (bits)
{
case UART_HW_DATABIT_8:
// val = val;
break;
default:
HDF_LOGE("only support 8b.\r\n");
break;
}
RegWrite(uart->base, USART_CR1, val);
return 0;
}
int32_t Mp15xUartHwStopBits(struct Mp15xUart *uart, uint32_t bits)
{
uint32_t val;
val = RegRead(uart->base, USART_CR2);
val &= ~USART_CR2_STOP_MASK;
if (bits == UART_HW_STOPBIT_1P5) {
val |= USART_CR2_STOP_1P5;
} else if (bits == UART_HW_STOPBIT_2) {
val |= USART_CR2_STOP_2P;
}
RegWrite(uart->base, USART_CR2, val);
return 0;
}
int32_t Mp15xUartHwParity(struct Mp15xUart *uart, uint32_t parity)
{
uint32_t val;
val = RegRead(uart->base, USART_CR1);
val &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 | USART_CR1_M0);
switch (parity)
{
case UART_HW_PARITY_NONE:
// val = val;
break;
// if enable parity, use 9 bit mode
case UART_HW_PARITY_ODD:
val |= (USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0);
break;
case UART_HW_PARITY_EVEN:
val |= (USART_CR1_PCE | USART_CR1_M0);
break;
default:
break;
}
RegWrite(uart->base, USART_CR1, val);
return 0;
}
int32_t Mp15xUartHwBaudrate(struct Mp15xUart *uart, uint32_t baudrate)
{
uint32_t val;
uint32_t sorce_rate = uart->clock_rate;
val = (sorce_rate + baudrate - 1)/baudrate;
RegWrite(uart->base, USART_BRR, val);
return 0;
}
#define FIFO_SIZE (128)
uint32_t Mp15xUartIrqHandler(uint32_t irq, void *data)
{
(void)irq;
unsigned char ch = 0;
char buf[FIFO_SIZE];
uint32_t count = 0;
int max_count = FIFO_SIZE;
struct Mp15xUart *uart = (struct Mp15xUart *)data;
struct Mp15xUartRxCtl *rx_ctl = &(uart->rx_ctl);
if(Mp15xUartHwGetIsr(uart) & USART_ISR_RXNE) {
do {
// read data from RDR
ch = RegRead(uart->base, USART_RDR);
// add data to buffer
buf[count++] = (char)ch;
if (CheckMagicKey(buf[count - 1], CONSOLE_SERIAL)) {
goto end;
}
} while((Mp15xUartHwGetIsr(uart) & USART_ISR_RXNE) && (max_count-- > 0));
if (rx_ctl->stm32mp1_uart_recv_hook)
rx_ctl->stm32mp1_uart_recv_hook(uart, buf, count);
}
end:
return 0;
}
common/platform/uart/stm32mp1_uart_hw.h
Executable
+117
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@@ -0,0 +1,117 @@
/*
* Copyright (c) 2022 Nanjing Xiaoxiongpai Intelligent Technology CO., LIMITED.
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _STM32MP1_UART_HW_H_
#define _STM32MP1_UART_HW_H_
#include <stdint.h>
#include "osal.h"
#include "osal_io.h"
#include "KRecvBuf.h"
// #define STM32MP1_UART_DEBUG
#define TX_BUF_SIZE (64)
#define UART_IRQ_NAME_SIZE (16)
struct Mp15xUart;
#define UART_HW_PARITY_NONE (0)
#define UART_HW_PARITY_ODD (1)
#define UART_HW_PARITY_EVEN (2)
#define UART_HW_PARITY_MARK (3)
#define UART_HW_PARITY_SPACE (4)
/* data bit */
#define UART_HW_DATABIT_8 (0)
#define UART_HW_DATABIT_7 (1)
#define UART_HW_DATABIT_6 (2)
#define UART_HW_DATABIT_5 (3)
/* stop bit */
#define UART_HW_STOPBIT_1 (0)
#define UART_HW_STOPBIT_1P5 (1)
#define UART_HW_STOPBIT_2 (2)
struct Mp15xUartRxCtl {
char *fifo;
KRecvBuf rx_krb; // 输入缓冲区
OSAL_DECLARE_SEMAPHORE(rx_sem);
uint32_t (*stm32mp1_uart_recv_hook)(struct Mp15xUart *uart, char *buf, uint32_t size);
};
struct Mp15xUart {
uint32_t num; // 当前串口编号
void volatile *base; // 虚拟地址
uint32_t phy_base; // 物理地址
uint32_t reg_step; // 映射大小
uint32_t irq_num; // 中断号
char irq_name[UART_IRQ_NAME_SIZE]; // 中断名
OSAL_DECLARE_SPINLOCK(lock); // 自旋锁
uint32_t clock_rate; // 时钟源频率
char *clock_source; // 时钟源
bool debug_uart; // 是否作为调试串口
bool fifo_en; // fifo模式
uint32_t baudrate; // 波特率
// state
#define UART_STATE_NOT_OPENED (0)
#define UART_STATE_OPENING (1)
#define UART_STATE_USEABLE (2)
#define UART_STATE_SUSPENED (3)
int state; // 设备状态
int open_count; // 打开数量
// flags
#define UART_FLG_DMA_RX (1 << 0)
#define UART_FLG_DMA_TX (1 << 1)
#define UART_FLG_RD_BLOCK (1 << 2)
uint32_t flags;
// tx
char tx_buf[TX_BUF_SIZE];
// rx
uint32_t rx_buf_size;
struct Mp15xUartRxCtl rx_ctl;
void *priv;
};
extern void Mp15xUartHwPutc(void *base, char c);
extern void Mp15xUartHwPuts(void *base, char *s, uint32_t len);
extern uint32_t Mp15xUartIrqHandler(uint32_t irq, void *data);
extern void Mp15xUartDump(struct Mp15xUart *uart);
extern int32_t Mp15xUartHwFifoEnable(struct Mp15xUart *uart, int enable);
extern int32_t Mp15xUartHwRxEnable(struct Mp15xUart *uart, int enable);
extern int32_t Mp15xUartHwEnable(struct Mp15xUart *uart, int enable);
extern int32_t Mp15xUartHwDataBits(struct Mp15xUart *uart, uint32_t bits);
extern int32_t Mp15xUartHwStopBits(struct Mp15xUart *uart, uint32_t bits);
extern int32_t Mp15xUartHwParity(struct Mp15xUart *uart, uint32_t parity);
extern int32_t Mp15xUartHwBaudrate(struct Mp15xUart *uart, uint32_t baudrate);
#endif
common/platform/wlan/BUILD.gn
Executable
+44
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@@ -0,0 +1,44 @@
# Copyright (c) 2020 Huawei Device Co., Ltd.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
if (defined(ohos_lite)) {
import("//build/lite/config/component/lite_component.gni")
} else {
import("//build/ohos.gni")
}
if (defined(ohos_lite)) {
copy("wifi_firmware") {
sources = [ "./hi3881" ]
outputs = [ "$root_out_dir/vendor/firmware/hi3881" ]
}
} else {
ohos_prebuilt_etc("wifi_cfg") {
source = "hi3881/wifi_cfg"
module_install_dir = "firmware/hi3881"
install_images = [ "vendor" ]
part_name = "hdf"
}
ohos_prebuilt_etc("wifi_fw_bin") {
source = "hi3881/hi3881_fw.bin"
module_install_dir = "firmware/hi3881"
install_images = [ "vendor" ]
part_name = "hdf"
}
group("wifi_firmware") {
deps = [
":wifi_cfg",
":wifi_fw_bin",
]
}
}
common/platform/wlan/hi3881/hi3881_fw.bin
Executable
BIN
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common/platform/wlan/hi3881/hi3881_fw_b.bin
Executable
BIN
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common/platform/wlan/hi3881/hi3881_fw_c.bin
Executable
BIN
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common/platform/wlan/hi3881/hi3881_fw_h.bin
Executable
BIN
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common/platform/wlan/hi3881/wifi_cfg
Executable
+11
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@WiFi patch info
CFG_COUNTRY_CODE=CN;
CFG_RSSI_OFFSET=0;
CFG_MAC=00:00:00:00:00:00;
CFG_DBB_PARAMS=0x6B6B6D6E,0x67676767,0x50545F60,0x565E5E5E,0x4F4F5656,0x00000000,0x01000000;
CFG_FREQ_COMP=105,100,-30;
CFG_CH_TXPWR_OFFSET=0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff;
PARA_VERSION=Hi3881V100;
ADDR_FILE_FILES=1,0xe4800,/vendor/firmware/hi3881/hi3881_fw.bin;
PARA_CONFIG=0xe4800,4;
QUIT;
entrance_guard/BUILD.gn
-16
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@@ -1,16 +0,0 @@
# Copyright (c) 2020 Huawei Device Co., Ltd. All rights reserved.
import("//build/lite/config/component/lite_component.gni")
group("entrance_guard") {
}
build_ext_component("liteos") {
exec_path = rebase_path(".", root_build_dir)
outdir = rebase_path("$root_out_dir")
command = "sh ./build.sh ${outdir}"
deps = [
"//build/lite:ohos",
"//device/st/entrance_guard/board:board",
]
}
entrance_guard/Makefile
-60
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@@ -1,60 +0,0 @@
# Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
# Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without modification,
# are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice, this list of
# conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice, this list
# of conditions and the following disclaimer in the documentation and/or other materials
# provided with the distribution.
#
# 3. Neither the name of the copyright holder nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific prior written
# permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
TARGET = liteos
BUILD_DIR = $(OUTDIR)
PREFIX = arm-none-eabi-
CC = $(PREFIX)gcc
AS = $(PREFIX)gcc -x assembler-with-cpp
CP = $(PREFIX)objcopy
SZ = $(PREFIX)size
HEX = $(CP) -O ihex
BIN = $(CP) -O binary -S
LDSCRIPT = default.ld
LIBS = -lc -lm -lnosys
LIBDIR = $(BUILD_DIR)/libs
LIBS += $(foreach x,${LIBDIR}, $(wildcard $(addprefix ${x}/*, .a)))
LDFLAGS = -specs=nano.specs -T$(LDSCRIPT) -L$(LIBDIR) -Wl,--start-group $(LIBS) -Wl,--end-group -Wl,-Map=$(BUILD_DIR)/$(TARGET).map,--cref -Wl,--gc-sections
all: $(BUILD_DIR)/$(TARGET).elf $(BUILD_DIR)/$(TARGET).hex $(BUILD_DIR)/$(TARGET).bin
$(BUILD_DIR)/$(TARGET).elf:
$(CC) $(LDFLAGS) -o $@
$(SZ) $@
$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf
$(HEX) $< $@
$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf
$(BIN) $< $@
-include $(wildcard $(BUILD_DIR)/*.d)
entrance_guard/board/BUILD.gn
-21
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@@ -1,21 +0,0 @@
# Copyright (c) 2020 Huawei Device Co., Ltd. All rights reserved.
static_library("board") {
sources = [
"./fs/ff_gen_drv.c",
"./main.c",
"./dprintf.c",
"./test_sample.c",
"./startup.s"
]
include_dirs = [
"//kernel/liteos_m/kernel/include",
"//kernel/liteos_m/kernel/arch/include",
"//kernel/liteos_m/utils",
"//kernel/liteos_m/kal/cmsis",
"//kernel/liteos_m/components/power"
]
deps = [ "//kernel/liteos_m/kal/posix" ]
}
entrance_guard/board/config.gni
-81
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@@ -1,81 +0,0 @@
# Copyright (c) 2020-2021 Huawei Device Co., Ltd.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# Kernel type, e.g. "linux", "liteos_a", "liteos_m".
kernel_type = "liteos_m"
# Kernel version.
kernel_version = "3.0.0"
# Board CPU type, e.g. "cortex-a7", "riscv32".
board_cpu = "cortex-m4"
# Board arch, e.g. "armv7-a", "rv32imac".
board_arch = ""
# Toolchain name used for system compiling.
# E.g. gcc-arm-none-eabi, arm-linux-harmonyeabi-gcc, ohos-clang, riscv32-unknown-elf.
# Note: The default toolchain is "ohos-clang". It's not mandatory if you use the default toolchain.
board_toolchain = "arm-none-eabi-gcc"
use_board_toolchain = true
# The toolchain path installed, it's not mandatory if you have added toolchain path to your ~/.bashrc.
board_toolchain_path = ""
# Compiler prefix.
board_toolchain_prefix = "arm-none-eabi-"
# Compiler type, "gcc" or "clang".
board_toolchain_type = "gcc"
# Board related common compile flags.
board_cflags = [
"-mthumb",
"-mfpu=fpv4-sp-d16",
"-mfloat-abi=soft",
"-Wall",
"-fdata-sections",
"-ffunction-sections",
"-DSTM32F429xx",
"-DUSE_HAL_DRIVER",
"-D__LITEOS_M__"
]
board_cxx_flags = board_cflags
board_ld_flags = []
# Board related headfiles search path.
board_include_dirs = [
"//device/st/entrance_guard/board",
"//device/st/entrance_guard/board/fs",
"//kernel/liteos_m/kal/posix/include",
"//third_party/bounds_checking_function/include",
"//kernel/liteos_m/components/fs/fatfs",
"//utils/native/lite/include",
"//kernel/liteos_m/kernel/include",
"//kernel/liteos_m/kernel/arch/arm/cortex-m4/gcc",
"//kernel/liteos_m/utils",
"//kernel/liteos_m/kal/cmsis",
"//third_party/FatFs/source"
]
# Board adapter dir for OHOS components.
board_adapter_dir = ""
# Sysroot path.
board_configed_sysroot = ""
# Board storage type, it used for file system generation.
storage_type = "spinor"
entrance_guard/board/dprintf.c
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/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "stdarg.h"
#include <stdio.h>
#include "los_debug.h"
#define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f)
/**
* @brief Retargets the C library printf function to the USART.
* @param None
* @retval None
*/
PUTCHAR_PROTOTYPE
{
/* demo */
return ch;
}
static int hex2asc(int n)
{
n &= 15;
if(n > 9){
return ('a' - 10) + n;
} else {
return '0' + n;
}
}
static void dputs(char const *s, int (*pFputc)(int n, FILE *cookie), void *cookie)
{
while (*s) {
pFputc(*s++, cookie);
}
}
void __dprintf(char const *fmt, va_list ap,
int (*pFputc)(int n, FILE *cookie),
void *cookie)
{
char scratch[256];
for(;;){
switch(*fmt){
case 0:
va_end(ap);
return;
case '%':
switch(fmt[1]) {
case 'c': {
unsigned n = va_arg(ap, unsigned);
pFputc(n, cookie);
fmt += 2;
continue;
}
case 'h': {
unsigned n = va_arg(ap, unsigned);
pFputc(hex2asc(n >> 12), cookie);
pFputc(hex2asc(n >> 8), cookie);
pFputc(hex2asc(n >> 4), cookie);
pFputc(hex2asc(n >> 0), cookie);
fmt += 2;
continue;
}
case 'b': {
unsigned n = va_arg(ap, unsigned);
pFputc(hex2asc(n >> 4), cookie);
pFputc(hex2asc(n >> 0), cookie);
fmt += 2;
continue;
}
case 'p':
case 'X':
case 'x': {
unsigned n = va_arg(ap, unsigned);
char *p = scratch + 15;
*p = 0;
do {
*--p = hex2asc(n);
n = n >> 4;
} while(n != 0);
while(p > (scratch + 7)) *--p = '0';
dputs(p, pFputc, cookie);
fmt += 2;
continue;
}
case 'd': {
int n = va_arg(ap, int);
char *p = scratch + 15;
*p = 0;
if(n < 0) {
pFputc('-', cookie);
n = -n;
}
do {
*--p = (n % 10) + '0';
n /= 10;
} while(n != 0);
dputs(p, pFputc, cookie);
fmt += 2;
continue;
}
case 'u': {
unsigned int n = va_arg(ap, unsigned int);
char *p = scratch + 15;
*p = 0;
do {
*--p = (n % 10) + '0';
n /= 10;
} while(n != 0);
dputs(p, pFputc, cookie);
fmt += 2;
continue;
}
case 's': {
char *s = va_arg(ap, char*); /*lint !e64*/
if(s == 0) s = "(null)";
dputs(s, pFputc, cookie);
fmt += 2;
continue;
}
}
pFputc(*fmt++, cookie);
break;
case '\n':
pFputc('\r', cookie);
default: /*lint !e616*/
pFputc(*fmt++, cookie);
}
}
}
void HalConsoleOutput(LogModuleType type, const char *fmt, va_list ap)
{
(void)type;
__dprintf(fmt, ap, fputc, 0);
}
int printf(char const *fmt, ...)
{
va_list ap;
va_start(ap, fmt); /*lint !e1055 !e534 !e530*/
__dprintf(fmt, ap, fputc, 0); /*lint !e611 !e64*/
va_end(ap);
return 0;
}
entrance_guard/board/fs/ff_gen_drv.c
-36
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@@ -1,36 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "fs_config.h"
#include "fatfs.h"
#include "ff_gen_drv.h"
DiskDrvTypeDef g_diskDrv = { { 0 }, { 0 }, { 0 }, { 0 } };
entrance_guard/board/fs/ff_gen_drv.h
-66
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@@ -1,66 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef FF_GEN_DRV_H
#define FF_GEN_DRV_H
#include "stdint.h"
#include "diskio.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
typedef struct {
DSTATUS (*disk_initialize)(BYTE);
DSTATUS (*disk_status)(BYTE);
DSTATUS (*disk_read)(BYTE, BYTE *, DWORD, UINT);
DSTATUS (*disk_write)(BYTE, const BYTE *, DWORD, UINT);
DSTATUS (*disk_ioctl)(BYTE, BYTE, void *);
} DiskioDrvTypeDef;
typedef struct {
uint8_t initialized[FF_VOLUMES];
const DiskioDrvTypeDef *drv[FF_VOLUMES];
uint8_t lun[FF_VOLUMES];
volatile uint8_t nbr;
} DiskDrvTypeDef;
extern DiskDrvTypeDef g_diskDrv;
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* FS_CONFIG_H */
entrance_guard/board/fs/fs_config.h
-54
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@@ -1,54 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef FS_CONFIG_H
#define FS_CONFIG_H
#include "los_compiler.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
#define FF_VOLUME_STRS "system", "inner", "update", "user"
#define FS_MAX_SS 512
#define FAT_MAX_OPEN_FILES 50
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* FS_CONFIG_H */
entrance_guard/board/main.c
-69
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@@ -1,69 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "los_tick.h"
#include "los_task.h"
#include "los_config.h"
#include "los_interrupt.h"
#include "los_debug.h"
#include "los_compiler.h"
#include "los_sched.h"
VOID TaskSample(VOID);
/*****************************************************************************
Function : main
Description : Main function entry
Input : None
Output : None
Return : None
*****************************************************************************/
LITE_OS_SEC_TEXT_INIT int main(void)
{
unsigned int ret;
/* uart init */
printf("\n\rhello world!!\n\r");
ret = LOS_KernelInit();
if (ret == LOS_OK) {
TaskSample();
LOS_Start();
}
EXIT:
while (1) {
__asm volatile("wfi");
}
}
entrance_guard/board/st_config.h
-98
View File
@@ -1,98 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ST_CONFIG_H
#define _ST_CONFIG_H
typedef struct {
unsigned int VTOR;
unsigned int SHCSR;
} SCBContext;
#define SCB ((SCBContext *)0x10000)
#define SCB_SHCSR_MEMFAULTENA_Msk 1
typedef struct {
unsigned int CTRL;
unsigned int RNR;
unsigned int RBAR;
unsigned int RASR;
unsigned int TYPE;
} MPUContext;
#define MPU ((MPUContext *)0x10000)
#define MPU_CTRL_ENABLE_Msk 1
#define MPU_CTRL_PRIVDEFENA_Pos 1
#define MPU_CTRL_PRIVDEFENA_Msk 1
#define MPU_TYPE_DREGION_Msk 1
#define MPU_RASR_S_Pos 1
#define MPU_RASR_S_Msk 1
#define MPU_RASR_AP_Msk 1
#define MPU_RASR_AP_Pos 1
#define MPU_RASR_C_Pos 1
#define MPU_RASR_B_Pos 1
#define MPU_RASR_ENABLE_Msk 1
#define MPU_RASR_SIZE_Pos 1
#define MPU_RASR_SIZE_Msk 1
#define MPU_RASR_XN_Pos 1
#define MPU_RASR_XN_Msk 1
#define MPU_RBAR_ADDR_Msk 1
#define __get_IPSR() 0
#define __DSB()
#define __WFI()
#define __ISB()
#define NVIC_EnableIRQ(vector)
#define NVIC_SetPriority(vector, pri)
#define NVIC_DisableIRQ(vector)
typedef struct {
unsigned int CTRL;
unsigned int LOAD;
unsigned int VAL;
} SysTickCB;
#define SysTick ((SysTickCB *)0x100000)
#define SysTick_Config(vector) 0
#define NVIC_ClearPendingIRQ(vector)
#define SysTick_CTRL_ENABLE_Msk 1
#define SysTick_IRQn 0
#define NonMaskableInt_IRQn 1
#define MemoryManagement_IRQn 2
#define BusFault_IRQn 3
#define UsageFault_IRQn 4
#define SVCall_IRQn 5
#define PendSV_IRQn 6
#endif
entrance_guard/board/startup.s
-42
View File
@@ -1,42 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.cpu cortex-m4
.fpu softvfp
.thumb
.section .Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
b main
.size Reset_Handler, .-Reset_Handler
entrance_guard/board/target_config.h
-127
View File
@@ -1,127 +0,0 @@
/*
* Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
* Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**@defgroup los_config System configuration items
* @ingroup kernel
*/
#ifndef _TARGET_CONFIG_H
#define _TARGET_CONFIG_H
#include "st_config.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
/*=============================================================================
System clock module configuration
=============================================================================*/
#define OS_SYS_CLOCK 32000UL
#define LOSCFG_BASE_CORE_TICK_PER_SECOND (1000UL)
#define LOSCFG_BASE_CORE_TICK_HW_TIME 0
#define LOSCFG_BASE_CORE_TICK_WTIMER 0
#define LOSCFG_BASE_CORE_TICK_RESPONSE_MAX 0xFFFFFFFUL
/*=============================================================================
Hardware interrupt module configuration
=============================================================================*/
#define LOSCFG_PLATFORM_HWI 1
#define LOSCFG_USE_SYSTEM_DEFINED_INTERRUPT 1
#define LOSCFG_PLATFORM_HWI_LIMIT 128
/*=============================================================================
Task module configuration
=============================================================================*/
#define LOSCFG_BASE_CORE_TSK_LIMIT 24
#define LOSCFG_BASE_CORE_TSK_IDLE_STACK_SIZE (0x500U)
#define LOSCFG_BASE_CORE_TSK_DEFAULT_STACK_SIZE (0x2D0U)
#define LOSCFG_BASE_CORE_TSK_MIN_STACK_SIZE (0x130U)
#define LOSCFG_BASE_CORE_TIMESLICE 1
#define LOSCFG_BASE_CORE_TIMESLICE_TIMEOUT 20000
/*=============================================================================
Semaphore module configuration
=============================================================================*/
#define LOSCFG_BASE_IPC_SEM 1
#define LOSCFG_BASE_IPC_SEM_LIMIT 48
/*=============================================================================
Mutex module configuration
=============================================================================*/
#define LOSCFG_BASE_IPC_MUX 1
#define LOSCFG_BASE_IPC_MUX_LIMIT 24
/*=============================================================================
Queue module configuration
=============================================================================*/
#define LOSCFG_BASE_IPC_QUEUE 1
#define LOSCFG_BASE_IPC_QUEUE_LIMIT 24
/*=============================================================================
Software timer module configuration
=============================================================================*/
#define LOSCFG_BASE_CORE_SWTMR 1
#define LOSCFG_BASE_CORE_SWTMR_ALIGN 1
#define LOSCFG_BASE_CORE_SWTMR_LIMIT 48
/*=============================================================================
Memory module configuration
=============================================================================*/
#define LOSCFG_MEM_MUL_POOL 1
#define OS_SYS_MEM_NUM 20
/*=============================================================================
Exception module configuration
=============================================================================*/
#define LOSCFG_PLATFORM_EXC 1
/* =============================================================================
printf module configuration
============================================================================= */
#define LOSCFG_KERNEL_PRINTF 1
#define LOSCFG_BACKTRACE_TYPE 1
#define LOSCFG_BASE_CORE_TSK_MONITOR 1
#define LOSCFG_BASE_CORE_CPUP 1
#define LOSCFG_BASE_CORE_EXC_TSK_SWITCH 1
#define LOSCFG_SYS_EXTERNAL_HEAP 1
#define LOSCFG_MEM_FREE_BY_TASKID 1
#define LOSCFG_BASE_MEM_NODE_INTEGRITY_CHECK 1
#define LOSCFG_MEM_LEAKCHECK 1
#define LOSCFG_DEBUG_HOOK 1
#define LOSCFG_KERNEL_PM 1
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
#endif /* _TARGET_CONFIG_H */
entrance_guard/board/test_sample.c
-380
View File
@@ -1,380 +0,0 @@
#include "los_tick.h"
#include "los_task.h"
#include "los_config.h"
#include "los_interrupt.h"
#include "los_debug.h"
#include "los_compiler.h"
#include "los_swtmr.h"
#include "los_sched.h"
#include "los_pm.h"
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cpluscplus */
#endif /* __cpluscplus */
#define OS_SLEEP_S(val) ((val) * 1000)
#define OS_SAMPLE_TASK_STACK_SIZE 0x1000
#define SWTMR1_SLEEP_PERIOD 1000
#define SWTMR2_SLEEP_PERIOD 2000
#define SWTMR3_SLEEP_PERIOD 8000
#define SWTMR4_SLEEP_PERIOD 10000
STATIC UINT32 g_task1;
STATIC UINT32 g_task2;
STATIC UINT32 g_task3;
STATIC UINT32 g_task4;
STATIC UINT32 g_swtmr1;
STATIC UINT32 g_swtmr2;
STATIC UINT32 g_swtmr3;
STATIC UINT32 g_swtmr4;
STATIC UINT32 g_swtmr1TestCount;
STATIC UINT32 g_swtmr2TestCount;
STATIC UINT32 g_swtmr3TestCount;
STATIC UINT32 g_swtmr4TestCount;
STATIC VOID SwtmrSample1(UINT32 arg)
{
if (arg == 1) {
g_swtmr1TestCount++;
} else if (arg == 2) {
g_swtmr2TestCount++;
} else if (arg == 3) {
g_swtmr3TestCount++;
} else if (arg == 4) {
g_swtmr4TestCount++;
}
}
STATIC VOID TaskSampleEntry5(VOID)
{
UINT16 pri;
UINT32 ret;
pri = LOS_TaskPriGet(LOS_CurTaskIDGet());
if (pri != 6) {
printf("TaskSampleEntry5 LOS_TaskPriGet pri :%u failed, ERROR: 0x%x\n", pri);
}
ret = LOS_TaskDelete(LOS_CurTaskIDGet());
if (ret != LOS_OK) {
printf("TaskSampleEntry5 exit failed, ERROR: 0x%x\n", ret);
}
}
STATIC VOID TaskSampleEntry4(VOID)
{
UINT32 taskID;
UINT32 ret;
TSK_INIT_PARAM_S task = { 0 };
task.pfnTaskEntry = (TSK_ENTRY_FUNC)TaskSampleEntry5;
task.uwStackSize = OS_SAMPLE_TASK_STACK_SIZE;
task.pcName = "taskSampleEntry5";
task.usTaskPrio = 30;
while (1) {
printf("TaskSampleEntry4 running...\n\r");
ret = LOS_TaskCreate(&taskID, &task);
if (ret != LOS_OK) {
printf("TaskSampleEntry4 create task failed, ERROR : 0x%x\n", ret);
}
ret = LOS_TaskPriSet(taskID, 6);
if (ret != LOS_OK) {
printf("TaskSampleEntry4 LOS_TaskPriSet task :%u pri 6 failed, ERROR: 0x%x\n", taskID, ret);
}
LOS_TaskDelay(OS_SLEEP_S(2));
}
}
STATIC VOID TaskSampleEntry3(VOID)
{
UINT32 ret;
while (1) {
printf("TaskSampleEntry3 running...\n\r");
LOS_TaskYield();
ret = LOS_SwtmrStart(g_swtmr1);
if (ret != LOS_OK) {
printf("TaskSampleEntry3 LOS_SwtmrStart g_swtmr1 failed, ERROR: 0x%x\n", ret);
}
LOS_TaskDelay(OS_SLEEP_S(10));
ret = LOS_SwtmrStop(g_swtmr1);
if (ret != LOS_OK) {
printf("TaskSampleEntry3 LOS_SwtmrStop g_swtmr1 failed, ERROR: 0x%x\n", ret);
}
LOS_TaskDelay(OS_SLEEP_S(1));
}
}
STATIC VOID TaskSampleEntry2(VOID)
{
UINT32 ret;
while (1) {
printf("TaskSampleEntry2 running... swtmr1: %u swtmr2: %u swtmr3: %u swtmr4: %u\n\r",
g_swtmr1TestCount, g_swtmr2TestCount, g_swtmr3TestCount, g_swtmr4TestCount);
ret = LOS_TaskSuspend(g_task1);
if (ret != LOS_OK) {
printf("TaskSampleEntry2 LOS_TaskSuspend g_task1 failed, ERROR: 0x%x\n", ret);
}
LOS_TaskDelay(OS_SLEEP_S(2));
ret = LOS_TaskResume(g_task1);
if (ret != LOS_OK) {
printf("TaskSampleEntry2 LOS_TaskResume g_task1 failed, ERROR: 0x%x\n", ret);
}
}
}
#define BACKTRACE_LR_SIZE 10
STATIC VOID TaskSampleEntry1(VOID)
{
UINT32 LR[BACKTRACE_LR_SIZE] = { 0 };
UINT32 ret;
ret = LOS_SwtmrStart(g_swtmr2);
if (ret != LOS_OK) {
printf("TaskSampleEntry1 LOS_SwtmrStart g_swtmr2 failed, ERROR: 0x%x\n", ret);
}
ret = LOS_SwtmrStart(g_swtmr3);
if (ret != LOS_OK) {
printf("TaskSampleEntry1 LOS_SwtmrStart g_swtmr3 failed, ERROR: 0x%x\n", ret);
}
ret = LOS_SwtmrStart(g_swtmr4);
if (ret != LOS_OK) {
printf("TaskSampleEntry1 LOS_SwtmrStart g_swtmr4 failed, ERROR: 0x%x\n", ret);
}
LOS_RecordLR(LR, BACKTRACE_LR_SIZE, 0, 0);
while (1) {
printf("TaskSampleEntry1 running... time : %u s\n\r", (UINT32)(OsGetCurrSchedTimeCycle() / OS_SYS_CLOCK));
LOS_TaskDelay(OS_SLEEP_S(1));
}
}
STATIC UINT32 SwtmrSample(VOID)
{
UINT32 ret;
g_swtmr1TestCount = 0;
g_swtmr2TestCount = 0;
g_swtmr3TestCount = 0;
g_swtmr4TestCount = 0;
#if (LOSCFG_BASE_CORE_SWTMR_ALIGN == 1)
ret = LOS_SwtmrCreate(SWTMR1_SLEEP_PERIOD, LOS_SWTMR_MODE_PERIOD, SwtmrSample1, &g_swtmr1, 1,
OS_SWTMR_ROUSES_ALLOW, OS_SWTMR_ALIGN_SENSITIVE);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_SwtmrCreate(SWTMR2_SLEEP_PERIOD, LOS_SWTMR_MODE_PERIOD, SwtmrSample1, &g_swtmr2, 2,
OS_SWTMR_ROUSES_ALLOW, OS_SWTMR_ALIGN_SENSITIVE);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_SwtmrCreate(SWTMR3_SLEEP_PERIOD, LOS_SWTMR_MODE_PERIOD, SwtmrSample1, &g_swtmr3, 3,
OS_SWTMR_ROUSES_ALLOW, OS_SWTMR_ALIGN_SENSITIVE);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_SwtmrCreate(SWTMR4_SLEEP_PERIOD, LOS_SWTMR_MODE_PERIOD, SwtmrSample1, &g_swtmr4, 4,
OS_SWTMR_ROUSES_ALLOW, OS_SWTMR_ALIGN_SENSITIVE);
if (ret != LOS_OK) {
return ret;
}
#else
ret = LOS_SwtmrCreate(SWTMR1_SLEEP_PERIOD, LOS_SWTMR_MODE_PERIOD, SwtmrSample1, &g_swtmr1, 1);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_SwtmrCreate(SWTMR2_SLEEP_PERIOD, LOS_SWTMR_MODE_PERIOD, SwtmrSample1, &g_swtmr2, 2);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_SwtmrCreate(SWTMR3_SLEEP_PERIOD, LOS_SWTMR_MODE_PERIOD, SwtmrSample1, &g_swtmr3, 3);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_SwtmrCreate(SWTMR4_SLEEP_PERIOD, LOS_SWTMR_MODE_PERIOD, SwtmrSample1, &g_swtmr4, 4);
if (ret != LOS_OK) {
return ret;
}
#endif
return LOS_OK;
}
UINT32 SemSample(VOID)
{
UINT32 semID = 0;
UINT32 ret = LOS_SemCreate(1, &semID);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_SemPend(semID, 10);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_SemPost(semID);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_SemDelete(semID);
if (ret != LOS_OK) {
return ret;
}
return 0;
}
UINT32 MuxSample(VOID)
{
UINT32 muxID = 0;
UINT32 ret = LOS_MuxCreate(&muxID);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_MuxPend(muxID, 10);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_MuxPost(muxID);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_MuxDelete(muxID);
if (ret != LOS_OK) {
return ret;
}
return 0;
}
UINT32 EventSample(VOID)
{
EVENT_CB_S event = { 0 };
UINT32 ret = LOS_EventInit(&event);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_EventRead(&event, 0xff, LOS_WAITMODE_OR, LOS_WAIT_FOREVER);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_EventWrite(&event, 0x1);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_EventClear(&event, 0);
if (ret != LOS_OK) {
return ret;
}
ret = LOS_EventDestroy(&event);
if (ret != LOS_OK) {
return ret;
}
return 0;
}
UINT32 TaskSample(VOID)
{
UINT32 ret;
TSK_INIT_PARAM_S task = { 0 };
#if (LOSCFG_KERNEL_PM == 1)
(VOID)LOS_PmRegister(LOS_PM_TYPE_DEVICE, NULL);
(VOID)LOS_PmUnregister(LOS_PM_TYPE_DEVICE, NULL);
(VOID)LOS_PmModeSet(LOS_PmModeGet());
(VOID)LOS_PmLockRequest("lock");
(VOID)LOS_PmLockRelease("lock");
#endif
task.pfnTaskEntry = (TSK_ENTRY_FUNC)TaskSampleEntry1;
task.uwStackSize = OS_SAMPLE_TASK_STACK_SIZE;
task.pcName = "taskSampleEntry1";
task.usTaskPrio = 6;
ret = LOS_TaskCreate(&g_task1, &task);
if (ret != LOS_OK) {
printf("task1 create failed\n");
}
task.pfnTaskEntry = (TSK_ENTRY_FUNC)TaskSampleEntry2;
task.uwStackSize = OS_SAMPLE_TASK_STACK_SIZE;
task.pcName = "taskSampleEntry2";
task.usTaskPrio = 7;
ret = LOS_TaskCreate(&g_task2, &task);
if (ret != LOS_OK) {
printf("task2 create failed\n");
}
task.pfnTaskEntry = (TSK_ENTRY_FUNC)TaskSampleEntry3;
task.uwStackSize = OS_SAMPLE_TASK_STACK_SIZE;
task.pcName = "taskSampleEntry3";
task.usTaskPrio = 8;
ret = LOS_TaskCreate(&g_task3, &task);
if (ret != LOS_OK) {
printf("task2 create failed\n");
}
ret = SwtmrSample();
if (ret != LOS_OK) {
return ret;
}
task.pfnTaskEntry = (TSK_ENTRY_FUNC)TaskSampleEntry4;
task.uwStackSize = OS_SAMPLE_TASK_STACK_SIZE;
task.pcName = "taskSampleEntry4";
task.usTaskPrio = 8;
ret = LOS_TaskCreate(&g_task4, &task);
if (ret != LOS_OK) {
return ret;
}
SemSample();
MuxSample();
EventSample();
return LOS_OK;
}
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cpluscplus */
#endif /* __cpluscplus */
entrance_guard/build.sh
-13
View File
@@ -1,13 +0,0 @@
#!/bin/bash
# Copyright (c) 2020 Huawei Device Co., Ltd. All rights reserved.
#
# Compile mpp/sample project, this is the entrance script
# error out on errors
set -e
OUT_DIR="$1"
function main(){
make -j16 OUTDIR=$OUT_DIR
}
main "$@"
entrance_guard/default.ld
-37
View File
@@ -1,37 +0,0 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(Reset_Handler)
SECTIONS
{
_stext = .;
.text :
{
KEEP (*(SORT_NONE(.Reset_Handler)))
*(.text.*)
}
_etext = .;
.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
.rodata1 : { *(.rodata1) }
.got : { *(.got.plt) *(.igot.plt) *(.got) *(.igot) }
.data :
{
__data_start = . ;
*(.data .data.* .gnu.linkonce.d.*)
}
__bss_start = .;
.bss :
{
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
}
_bss_end__ = .;
_sstack = .;
.stack :
{
_stack = .;
*(.stack)
}
_estack = .;
/DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
}
stm32mp157/sdk_liteos/BUILD.gn
Executable
+36
View File
@@ -0,0 +1,36 @@
# Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology Co., Ltd.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# cmd = "if [ -f $product_path/hdf_config/BUILD.gn ]; then echo true; else echo false; fi"
# HAVE_PRODUCT_CONFIG = exec_script("//build/lite/run_shell_cmd.py", [ cmd ], "value")
cmd = "if [ -f $product_path/hdf_config/BUILD.gn ]; then echo true; else echo false; fi"
HAVE_PRODUCT_CONFIG = exec_script("//build/lite/run_shell_cmd.py", [ cmd ], "value")
group("sdk_liteos") {
deps = [
"board",
"drivers",
]
if (HAVE_PRODUCT_CONFIG) {
deps += [ "$product_path/hdf_config" ]
} else {
deps += [ "hdf_config" ]
}
}
config("public") {
configs = [
"board:public",
"drivers:public",
]
}
stm32mp157/sdk_liteos/hdf_config/BUILD.gn
Executable
+20
View File
@@ -0,0 +1,20 @@
# Copyright (c) 2021 Nanjing Xiaoxiongpai Intelligent Technology Co., Ltd.
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import("//drivers/adapter/khdf/liteos/hdf.gni")
module_switch = defined(LOSCFG_DRIVERS_HDF)
module_name = "hdf_config"
hdf_driver(module_name) {
hcs_sources = [ "hdf.hcs" ]
}
stm32mp157/sdk_liteos/hdf_config/adc/adc_config.hcs
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root {
platform {
adc_config {
match_attr = "st_stm32mp1_adc";
template stm32mp1_adc_device {
dev_num = 1;
adc_enable = false;
reg_pbase = 0x48003000;
reg_size = 0x100;
sample_time = 0x0; // 1.5 ADC clock cycles
/*
From left to right, indicate channels from low to high; 0:disable 1:enable
*/
channel_enable = [0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0];
data_width = 16;
/* [port,pin]
<port> 0:GPIOA 1:GPIOB 2:GPIOC ...... 253:internal channel 254:ADC dedicated pin 255:unavailable
<pin> 0:PIN0 1:PIN1 2:PIN2 ...... 253:internal channel 254:ADC dedicated pin 255:unavailable
*/
pins = [254,254 ,254,254 ,5,11 ,0,6
,2,4 ,1,1 ,5,12 ,0,7
,2,5 ,1,0 ,2,0 ,2,1
,2,2 ,2,3 ,0,2 ,0,3
,0,0 ,0,1 ,0,4 ,0,5];
}
adc_1_0x48003000 :: stm32mp1_adc_device {
dev_num = 1;
adc_enable = true;
data_width = 8;
}
adc_2_0x48003100 :: stm32mp1_adc_device {
dev_num = 2;
reg_pbase = 0x48003100;
reg_size = 0x200;
channel_enable = [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0];
pins = [254,254 ,254,254 ,5,13 ,0,6
,2,4 ,1,1 ,5,14 ,0,7
,2,5 ,1,0 ,2,0 ,2,1
,255,255 ,255,255 ,0,4 ,0,5
,253,253 ,253,253 ,253,253 ,253,253];
/** Vbat Tsen Vref VddCore */
}
}
}
}
stm32mp157/sdk_liteos/hdf_config/device_info/device_info.hcs
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root {
device_info {
match_attr = "hdf_manager";
template host {
hostName = "";
priority = 100;
template device{
template deviceNode {
policy = 0;
priority = 100;
preload = 0;
permission = 0664;
moduleName = "";
serviceName = "";
deviceMatchAttr = "";
}
}
}
platform :: host {
hostName = "platform_host";
priority = 50;
device_gpio :: device {
device0 :: deviceNode {
policy = 0;
priority = 10;
permission = 0644;
moduleName = "HDF_PLATFORM_GPIO";
serviceName = "HDF_PLATFORM_GPIO";
deviceMatchAttr = "st_stm32mp1_gpio";
}
}
device_iwdg :: device {
device0 :: deviceNode {
policy = 1;
priority = 20;
permission = 0644;
moduleName = "stm32mp1_iwdg";
serviceName = "HDF_PLATFORM_WATCHDOG_0";
deviceMatchAttr = "stm32mp1_iwdg_0";
}
device1 :: deviceNode {
policy = 1;
priority = 20;
permission = 0644;
moduleName = "stm32mp1_iwdg";
serviceName = "HDF_PLATFORM_WATCHDOG_1";
deviceMatchAttr = "stm32mp1_iwdg_1";
}
}
device_uart :: device {
device0 :: deviceNode {
policy = 1;
priority = 40;
permission = 0644;
moduleName = "stm32mp1_uart";
serviceName = "HDF_PLATFORM_UART_4";
deviceMatchAttr = "stm32mp1_uart_4";
}
}
device_mmc:: device {
device0 :: deviceNode {
policy = 2;
priority = 10;
permission = 0644;
moduleName = "HDF_PLATFORM_SDMMC";
serviceName = "HDF_PLATFORM_MMC_2";
deviceMatchAttr = "st_stm32mp1_sdmmc_emmc";
}
device1 :: deviceNode {
policy = 2;
priority = 20;
permission = 0644;
moduleName = "HDF_PLATFORM_SDMMC";
serviceName = "HDF_PLATFORM_MMC_1";
deviceMatchAttr = "st_stm32mp1_sdmmc_sd";
}
device2 :: deviceNode {
policy = 1;
priority = 30;
permission = 0644;
moduleName = "HDF_PLATFORM_SDMMC";
serviceName = "HDF_PLATFORM_MMC_3";
deviceMatchAttr = "st_stm32mp1_sdmmc_sdio";
}
}
device_ltdc:: device {
device0 :: deviceNode {
policy = 0;
priority = 170;
permission = 0644;
moduleName = "HDF_PLATFORM_LTDC";
serviceName = "HDF_PLATFORM_LTDC";
deviceMatchAttr = "st_stm32mp1_ltdc";
}
}
device_i2c :: device {
device0 :: deviceNode {
policy = 2;
priority = 50;
permission = 0644;
moduleName = "HDF_PLATFORM_I2C_MANAGER";
serviceName = "HDF_PLATFORM_I2C_MANAGER";
deviceMatchAttr = "hdf_platform_i2c_manager";
}
device1 :: deviceNode {
policy = 0;
priority = 55;
permission = 0644;
moduleName = "HDF_PLATFORM_I2C";
serviceName = "HDF_PLATFORM_I2C";
deviceMatchAttr = "st_stm32mp1_i2c";
}
}
device_adc :: device {
device0 :: deviceNode {
policy = 0;
priority = 50;
permission = 0644;
moduleName = "HDF_PLATFORM_ADC_MANAGER";
serviceName = "HDF_PLATFORM_ADC_MANAGER";
deviceMatchAttr = "hdf_platform_adc_manager";
}
device1 :: deviceNode {
policy = 0;
priority = 55;
permission = 0644;
moduleName = "stm32mp1_adc_driver";
deviceMatchAttr = "st_stm32mp1_adc";
}
}
}
input :: host {
hostName = "input_host";
priority = 100;
device_input_manager :: device {
device0 :: deviceNode {
policy = 2;
priority = 100;
preload = 0;
permission = 0660;
moduleName = "HDF_INPUT_MANAGER";
serviceName = "hdf_input_host";
deviceMatchAttr = "";
}
}
device_hdf_touch :: device {
device0 :: deviceNode {
policy = 2;
priority = 120;
preload = 0;
permission = 0660;
moduleName = "HDF_TOUCH";
serviceName = "hdf_input_event1";
deviceMatchAttr = "touch_device1";
}
}
device_touch_chip :: device {
device0 :: deviceNode {
policy = 0;
priority = 130;
preload = 0;
permission = 0660;
moduleName = "HDF_TOUCH_GT911";
serviceName = "hdf_touch_gt911_service";
deviceMatchAttr = "zsj_gt911_5p5";
}
}
}
network :: host {
hostName = "network_host";
device_wifi :: device {
device0 :: deviceNode {
policy = 2;
priority = 100;
preload = 0;
permission = 0664;
moduleName = "HDF_WIFI";
deviceMatchAttr = "hdf_wlan_driver";
serviceName = "hdfwifi";
}
}
device_wlan_chips :: device {
device0 :: deviceNode {
policy = 0;
preload = 2;
moduleName = "HDF_WLAN_CHIPS";
deviceMatchAttr = "hdf_wlan_chips_hi3881";
serviceName = "hisi";
}
}
}
}
}
stm32mp157/sdk_liteos/hdf_config/gpio/gpio_config.hcs
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root {
platform {
gpio_config {
controller_0x50002000 {
match_attr = "st_stm32mp1_gpio";
groupNum = 11;
bitNum = 16;
gpioRegBase = 0x50002000;
gpioRegStep = 0x1000;
irqRegBase = 0x5000D000;
irqRegStep = 0x400;
}
}
}
}
stm32mp157/sdk_liteos/hdf_config/hdf.hcs
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#include "device_info/device_info.hcs"
#include "adc/adc_config.hcs"
#include "gpio/gpio_config.hcs"
#include "i2c/i2c_config.hcs"
#include "uart/uart_config.hcs"
#include "watchdog/watchdog_config.hcs"
#include "mmc/mmc_config.hcs"
#include "input/input_config.hcs"
#include "ltdc/ltdc_config.hcs"
#include "wifi/wlan_platform.hcs"
#include "wifi/wlan_chip_hi3881.hcs"
root {
module = "st,stm32mp157";
}
stm32mp157/sdk_liteos/hdf_config/i2c/i2c_config.hcs
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root {
platform {
i2c_config {
match_attr = "st_stm32mp1_i2c";
template i2c_controller {
bus = 1;
reg_pbase = 0x40012000;
reg_size = 0x400;
timing = 0x10909CEC;
own_address1 = 0;
addressing_mode = 0x00000001;
dual_address_mode = 0x00000000;
own_address2 = 0;
own_address_2_masks = 0x00;
general_call_mode = 0x00000000;
no_stretch_mode = 0x00000000;
}
controller_0x40012000 :: i2c_controller {
bus = 1;
reg_pbase = 0x40012000;
/* [port,pin]
<port> 0:GPIOA 1:GPIOB 3:GPIOC ......
<pin> 0:PIN0 1:PIN1 2:PIN2 ......
*/
i2cClkIomux = [3, 12]; //PD12
i2cDataIomux = [5, 15]; //PF15
}
controller_0x40013000 :: i2c_controller {
bus = 2;
reg_pbase = 0x40013000;
i2cClkIomux = [7, 4]; //PH4
i2cDataIomux = [7, 5]; //PH5
}
controller_0x40015000 :: i2c_controller {
bus = 5;
reg_pbase = 0x40015000;
i2cClkIomux = [0, 11]; //PA11
i2cDataIomux = [0, 12]; //PA12
}
}
}
}
stm32mp157/sdk_liteos/hdf_config/input/input_config.hcs
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root {
input_config {
touchConfig {
touch0 {
boardConfig {
match_attr = "touch_device1";
inputAttr {
/* 0:touch 1:key 2:keyboard 3:mouse 4:button 5:crown 6:encoder */
inputType = 0;
solutionX = 480;
solutionY = 960;
devName = "main_touch";
}
busConfig {
// 0:i2c 1:spi
busType = 0;
busNum = 2;
clkGpio = 116;
dataGpio = 117;
i2cClkIomux = [0x50009020, 0x40000];
i2cDataIomux = [0x50009020, 0x400000];
}
pinConfig {
rstGpio = 71;
intGpio = 104;
rstRegCfg = [0x50008024, 0x0];
intRegCfg = [0x50007020, 0x0];
}
powerConfig {
/* 0:unused 1:ldo 2:gpio 3:pmic */
vccType = 1;
vccNum = 20; // gpio20
vccValue = 1800;
vciType = 1;
vciNum = 12; // ldo12
vciValue = 3300;
}
featureConfig {
capacitanceTest = 0;
gestureMode = 0;
gloverMOde = 0;
coverMode = 0;
chargerMode = 0;
knuckleMode = 0;
}
}
chipConfig {
template touchChip {
match_attr = "";
chipName = "gt911";
vendorName = "zsj";
chipInfo = "AAAA11222"; // 4-ProjectName, 2-TP IC, 3-TP Module
/* 0:i2c 1:spi*/
busType = 0;
deviceAddr = 0xBA;
/* 0:None 1:Rising 2:Failing 4:High-level 8:Low-level */
irqFlag = 2;
maxSpeed = 400;
chipVersion = 0; //parse Coord TypeA
powerSequence {
/* [type, status, dir , delay]
<type> 0:none 1:vcc-1.8v 2:vci-3.3v 3:reset 4:int
<status> 0:off or low 1:on or high 2:no ops
<dir> 0:input 1:output 2:no ops
<delay> meanings delay xms, 20: delay 20ms
*/
powerOnSeq = [4, 0, 1, 0,
3, 0, 1, 10,
3, 1, 2, 60,
4, 2, 0, 0];
suspendSeq = [3, 0, 2, 10];
resumeSeq = [3, 1, 2, 10];
powerOffSeq = [3, 0, 2, 10,
1, 0, 2, 20];
}
}
chip0 :: touchChip {
match_attr = "zsj_gt911_5p5";
chipInfo = "ZIDN45100"; // 4-ProjectName, 2-TP IC, 3-TP Module
chipVersion = 0; //parse point by TypeA
}
}
}
}
}
}
stm32mp157/sdk_liteos/hdf_config/ltdc/ltdc_config.hcs
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root {
platform {
ltdc_config {
match_attr = "st_stm32mp1_ltdc";
template ltdc_device {
vsync = 0;
vbp = 23;
vfp = 22;
vact = 480;
hsync = 1;
hbp = 46;
hfp = 210;
hact = 800;
reg_pbase = 0x5A001000;
reg_size = 0x400;
}
device_0 :: ltdc_device {
vsync = 1;
vbp = 23;
vfp = 22;
vact = 480;
hsync = 1;
hbp = 46;
hfp = 210;
hact = 800;
reg_pbase = 0x5A001000;
reg_size = 0x400;
}
}
}
}
stm32mp157/sdk_liteos/hdf_config/mmc/mmc_config.hcs
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root {
platform {
mmc_config {
template mmc_controller {
match_attr = "";
voltDef = 0; // 3.3V
freqMin = 50000;
freqMax = 50000000;
freqDef = 400000;
maxBlkNum = 2048;
maxBlkSize = 512;
ocrDef = 0x380000;
hostId = 0;
devType = 0;
caps2 = 0;
caps = 0x0001e045;
irqNum = 156;
regSize = 0x1000;
regBase = 0x58007000;
}
controller_0x58005000 :: mmc_controller {
match_attr = "st_stm32mp1_sdmmc_sd";
hostId = 0;
regBase = 0x58005000;
irqNum = 81;
devType = 1; // sd
cdGpio = 82;
caps = 0x9001e005;
}
controller_0x58007000 :: mmc_controller {
match_attr = "st_stm32mp1_sdmmc_emmc";
hostId = 1;
regBase = 0x58007000;
irqNum = 156;
devType = 0; // emmc
caps = 0xd001e045;
caps2 = 0x00;
}
controller_0x48004000 :: mmc_controller {
match_attr = "st_stm32mp1_sdmmc_sdio";
hostId = 2;
regBase = 0x48004000;
irqNum = 169;
devType = 2; // sdio
caps = 0x0001e04d;
}
}
}
}
stm32mp157/sdk_liteos/hdf_config/uart/uart_config.hcs
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root {
platform {
template uart_controller {
num = 0;
baudrate = 115200;
flags = 4;
reg_base = 0x12040000;
reg_step = 0x400;
interrupt = 39;
rx_buf_size = 0x1000; // default rx_buf_size 4096
clock_rate = 64000000; // clock_rate 64M
fifo_en = true;
}
controller_0x40010000 :: uart_controller {
match_attr = "stm32mp1_uart_4";
num = 4;
reg_base = 0x40010000;
interrupt = 84;
}
}
}
stm32mp157/sdk_liteos/hdf_config/watchdog/watchdog_config.hcs
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root {
platform {
template iwdg_controller {
num = 0; // iwdg num
reg_base = 0x5C003000;
reg_step = 0x400;
timeout_sec = 32; // default iwdg timeout(s)
auto_feed = false;
auto_feed_period = 10;
start = false;
clock_rate = 32000; // default clock source rate
}
controller_0x5C003000 :: iwdg_controller {
match_attr = "stm32mp1_iwdg_0";
}
controller_0x5A002000 :: iwdg_controller {
match_attr = "stm32mp1_iwdg_1";
num = 1;
reg_base = 0x5A002000;
auto_feed = true;
start = true;
}
}
}
stm32mp157/sdk_liteos/hdf_config/wifi/wlan_chip_hi3881.hcs
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root {
wlan_config {
hi3881 :& chipList {
chipHi3881 :: chipInst {
match_attr = "hdf_wlan_chips_hi3881";
driverName = "hisi";
sdio {
vendorId = 0x0296;
deviceId = [0x5347];
}
}
}
}
}
stm32mp157/sdk_liteos/hdf_config/wifi/wlan_platform.hcs
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root {
module = "wlan";
wlan_config {
match_attr = "hdf_wlan_driver";
hostChipName = "hi3516dv300";
moduleConfig {
featureMap = 0xFFFF;
msgName = "WalService";
Station {
name = "sta";
mode = true;
}
HostAp {
name = "ap";
mode = 0; /* 0-- notsupported; 1--softap-host; 2--soft AP DMAC HOST; 3-IOT 1:DMAC OFFLOAD: IPC */
vapResNum = 1; /*virtual ap*/
userResNum = 8; /*max users support each ap*/
}
P2P {
name = "p2p";
mode = false;
}
Mac80211 {
mode = true;
}
Phy {
mode = true;
}
}
deviceList {
template deviceInst {
deviceInstId = 0;
powers {
power0 {
powerSeqDelay = 0;
powerType = 1; /* AlwaysON(0);GPIO(1) */
gpioId = 1;
activeLevel=1; /* High(1); Low(0) */
}
power1 {
/* to support two-stage power supply */
powerSeqDelay = 0;
powerType = 0;
gpioId = 1;
activeLevel=1; /* High(1); Low(0) */
}
}
reset {
resetType = 1; /* NotManaged(0);GPIO(1) */
gpioId = 2;
activeLevel = 1; /* High(1); Low(0) */
resetHoldTime = 30; /*In ms*/
}
bootUpTimeOut = 30;
bus {
busType = 0; /* 0-sdio 1-usb 2-spi etc. */
busIdx = 2;
funcNum = [1,2];
timeout = 1000;
blockSize = 512;
}
}
}
hisi :& deviceList {
device0 :: deviceInst {
deviceInstId = 0;
powers {
power0 {
powerSeqDelay = 0;
powerType = 0; /* AlwaysON(0);GPIO(1) */
gpioId = 45;
activeLevel=1; /* High(1); Low(0) */
}
power1 {
powerSeqDelay = 0;
powerType = 0;
gpioId = 1;
activeLevel = 1; /* High(1); Low(0) */
}
}
reset {
resetType = 1; /* NotManaged(0);GPIO(1) */
gpioId = 45;
activeLevel = 0; /* High(1); Low(0) */
resetHoldTime = 16; /*In ms*/
}
bootUpTimeOut = 32;
bus {
busType = 0; /* 0-sdio 1-usb 2-spi etc. */
busIdx = 2;
funcNum = [1];
timeout = 1000;
blockSize = 512;
}
}
}
chipList {
template chipInst {
match_attr = "hdf_wlan_chips_hi3881";
driverName = "hi3881";
sdio {
vendorId = 0x0296;
deviceId = [0x5347];
}
}
}
}
}