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!33 修复代码质量缺陷

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Merge pull request !33 from Andy Liu/OpenHarmony-3.2-Beta2
This commit is contained in:
openharmony_ci
2022-07-27 02:07:22 +00:00
committed by Gitee
parent ed99202255 eee8637090
commit e56efb84f9
110 changed files with 2127 additions and 2597 deletions
Download Patch File Download Diff File Expand all files Collapse all files
b91/adapter/hals/utils/file/src/hal_file.c
+8 -5
View File
@@ -16,6 +16,8 @@
*
*****************************************************************************/
#include <securec.h>
#include <errno.h>
#include <fcntl.h>
#include <stdbool.h>
@@ -26,10 +28,11 @@
#include <sys/types.h>
#include <unistd.h>
#include "hal_file.h"
#include "utils_file.h"
#include <hiview_log.h>
#include <hal_file.h>
#include <utils_file.h>
#define RD_WR_FIELD_MASK 0x000f
#define CREAT_EXCL_FIELD_MASK 0x00f0
#define TRUNC_FILED_MASK 0x0f00
@@ -117,9 +120,9 @@ static char *GetActualFilePath(const char *path)
return NULL;
}
strcpy(file_path, ROOT_PATH);
strcat(file_path, DIR_SEPARATOR);
strcat(file_path, path);
strcpy_s(file_path, len, ROOT_PATH);
strcat_s(file_path, len, DIR_SEPARATOR);
strcat_s(file_path, len, path);
return file_path;
}
b91/b91_ble_sdk/algorithm/aes_ccm/aes_ccm.h
+29 -36
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_ALGORITHM_AES_CCM_AES_CCM_H
#define B91_B91_BLE_SDK_ALGORITHM_AES_CCM_AES_CCM_H
#include "stack/ble/ble_format.h"
@@ -27,30 +28,25 @@ enum {
AES_FAIL,
};
typedef struct
{
typedef struct {
u32 pkt;
u8 dir;
u8 iv[8];
} ble_cyrpt_nonce_t;
typedef struct
{
typedef struct {
u32 enc_pno;
u32 dec_pno;
u8 sk[16]; //session key
u8 sk[16]; // session key
ble_cyrpt_nonce_t nonce;
u8 st;
u8 enable; //1: slave enable; 2: master enable
u8 enable; // 1: slave enable; 2: master enable
u8 mic_fail;
} ble_crypt_para_t;
struct CCM_FLAGS_TAG
{
union
{
struct
{
struct CCM_FLAGS_TAG {
union {
struct {
u8 L : 3;
u8 M : 3;
u8 aData : 1;
@@ -62,10 +58,8 @@ struct CCM_FLAGS_TAG
typedef struct CCM_FLAGS_TAG ccm_flags_t;
typedef struct
{
union
{
typedef struct {
union {
u8 A[AES_BLOCK_SIZE];
u8 B[AES_BLOCK_SIZE];
} bf;
@@ -80,29 +74,26 @@ enum {
CRYPT_NONCE_TYPE_BIS = 2,
};
typedef union
{
struct
{
u8 enEncFlg : 1; //enable encryption
u8 noneType : 2; //ACL, CIS, BIS
u8 decMicFail : 1; //Decryption status
u8 role : 1; //ll_ccm_enc: Master role must use 1, Slave role must use 0;
//ll_ccm_dec: Master role must use 0, Slave role must use 1;
u8 rsvd : 3; //Rsvd
typedef union {
struct {
u8 enEncFlg : 1; // enable encryption
u8 noneType : 2; // ACL, CIS, BIS
u8 decMicFail : 1; // Decryption status
u8 role : 1; // ll_ccm_enc: Master role must use 1, Slave role must use 0;
// ll_ccm_dec: Master role must use 0, Slave role must use 1;
u8 rsvd : 3; // Rsvd
};
u8 cryptBitsInfo;
} cryptBitsInfo_t;
typedef struct
{
u64 txPayloadCnt; //Packet counter for Tx
u64 rxPayloadCnt; //Packet counter for Rx
u8 sk[16]; //Session key
ble_cyrpt_nonce_t ccmNonce; //CCM nonce format
cryptBitsInfo_t cryptBitsInfo; //To save Ram
u16 rsvd; //For align
llPhysChnPdu_t *pllPhysChnPdu; //LL physical channel PDU
typedef struct {
u64 txPayloadCnt; // Packet counter for Tx
u64 rxPayloadCnt; // Packet counter for Rx
u8 sk[16]; // Session key
ble_cyrpt_nonce_t ccmNonce; // CCM nonce format
cryptBitsInfo_t cryptBitsInfo; // To save Ram
u16 rsvd; // For align
llPhysChnPdu_t *pllPhysChnPdu; // LL physical channel PDU
} leCryptCtrl_t;
/**
@@ -160,3 +151,5 @@ int aes_ll_ccm_decryption(u8 *pkt, int master, ble_crypt_para_t *pd);
* @return 0: decryption succeeded; 1: decryption failed
*/
int aes_ll_ccm_decryption_v2(leCryptCtrl_t *pd);
#endif // B91_B91_BLE_SDK_ALGORITHM_AES_CCM_AES_CCM_H
b91/b91_ble_sdk/common/assert.h
+4 -1
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_COMMON_ASSERT_H
#define B91_B91_BLE_SDK_COMMON_ASSERT_H
#include "config/user_config.h" // for __DEBUG__
@@ -78,3 +79,5 @@
#else
#define NOTE(x)
#endif
#endif // B91_B91_BLE_SDK_COMMON_ASSERT_H
b91/b91_ble_sdk/common/bit.h
+158 -262
View File
@@ -15,325 +15,221 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_COMMON_BIT_H
#define B91_B91_BLE_SDK_COMMON_BIT_H
#include "macro_trick.h"
#define BIT(n) (1 << (n))
#define BIT(n) (1 << (n))
// BITSx are internal used macro, please use BITS instead
#define BITS1(a) BIT(a)
#define BITS2(a, b) (BIT(a) | BIT(b))
#define BITS3(a, b, c) (BIT(a) | BIT(b) | BIT(c))
#define BITS4(a, b, c, d) (BIT(a) | BIT(b) | BIT(c) | BIT(d))
#define BITS5(a, b, c, d, e) (BIT(a) | BIT(b) | BIT(c) | BIT(d) | BIT(e))
#define BITS6(a, b, c, d, e, f) (BIT(a) | BIT(b) | BIT(c) | BIT(d) | BIT(e) | BIT(f))
#define BITS7(a, b, c, d, e, f, g) (BIT(a) | BIT(b) | BIT(c) | BIT(d) | BIT(e) | BIT(f) | BIT(g))
#define BITS8(a, b, c, d, e, f, g, h) (BIT(a) | BIT(b) | BIT(c) | BIT(d) | BIT(e) | BIT(f) | BIT(g) | BIT(h))
#define BITS1(a) BIT(a)
#define BITS2(a, b) (BIT(a) | BIT(b))
#define BITS3(a, b, c) (BIT(a) | BIT(b) | BIT(c))
#define BITS4(a, b, c, d) (BIT(a) | BIT(b) | BIT(c) | BIT(d))
#define BITS5(a, b, c, d, e) (BIT(a) | BIT(b) | BIT(c) | BIT(d) | BIT(e))
#define BITS6(a, b, c, d, e, f) (BIT(a) | BIT(b) | BIT(c) | BIT(d) | BIT(e) | BIT(f))
#define BITS7(a, b, c, d, e, f, g) (BIT(a) | BIT(b) | BIT(c) | BIT(d) | BIT(e) | BIT(f) | BIT(g))
#define BITS8(a, b, c, d, e, f, g, h) (BIT(a) | BIT(b) | BIT(c) | BIT(d) | BIT(e) | BIT(f) | BIT(g) | BIT(h))
#define BITS(...) VARARG(BITS, __VA_ARGS__)
#define BITS(...) VARARG(BITS, __VA_ARGS__)
// bits range: BITS_RNG(4, 5) 0b000111110000, start from 4, length = 5
#define BIT_RNG(s, e) (BIT_MASK_LEN((e) - (s) + 1) << (s))
#define BIT_RNG(s, e) (BIT_MASK_LEN((e)-(s)+1) << (s))
#define BM_MASK_V(x, mask) ((x) | (mask))
#define BM_CLR_MASK_V(x, mask) ((x) & ~(mask))
#define BM_MASK_V(x, mask) ((x) | (mask))
#define BM_CLR_MASK_V(x, mask) ((x) & ~(mask))
#define BM_SET(x, mask) ((x) |= (mask))
#define BM_CLR(x, mask) ((x) &= ~(mask))
#define BM_IS_SET(x, mask) ((x) & (mask))
#define BM_IS_CLR(x, mask) ((~x) & (mask))
#define BM_FLIP(x, mask) ((x) ^= (mask))
#define BM_SET(x, mask) ((x) |= (mask))
#define BM_CLR(x, mask) ((x) &= ~(mask))
#define BM_IS_SET(x, mask) ((x) & (mask))
#define BM_IS_CLR(x, mask) ((~(x)) & (mask))
#define BM_FLIP(x, mask) ((x) ^= (mask))
// !!!! v is already a masked value, no need to shift
#define BM_MASK_VAL(x, mask, v) (((x) & ~(mask)) | (v))
#define BM_SET_MASK_VAL(x, mask, v) ((x) = BM_MASK_VAL(x, mask, v))
#define BM_MASK_VAL(x, mask, v) (((x) & ~(mask)) | (v))
#define BM_SET_MASK_VAL(x, mask, v) ((x) = BM_MASK_VAL(x, mask, v))
#define BIT_SET(x, n) ((x) |= BIT(n))
#define BIT_CLR(x, n) ((x) &= ~BIT(n))
#define BIT_IS_SET(x, n) ((x)&BIT(n))
#define BIT_FLIP(x, n) ((x) ^= BIT(n))
#define BIT_SET_HIGH(x) ((x) |= BIT((sizeof((x)) * 8 - 1))) // set the highest bit
#define BIT_CLR_HIGH(x) ((x) &= ~BIT((sizeof((x)) * 8 - 1))) // clr the highest bit
#define BIT_IS_SET_HIGH(x) ((x)&BIT((sizeof((x)) * 8 - 1))) // check the higest bit
#define BIT_MASK_LEN(len) (BIT(len) - 1)
#define BIT_MASK(start, len) (BIT_MASK_LEN(len) << (start))
#define BIT_SET(x, n) ((x) |= BIT(n))
#define BIT_CLR(x, n) ((x) &= ~ BIT(n))
#define BIT_IS_SET(x, n) ((x) & BIT(n))
#define BIT_FLIP(x, n) ((x) ^= BIT(n))
#define BIT_SET_HIGH(x) ((x) |= BIT((sizeof((x))*8-1))) // set the highest bit
#define BIT_CLR_HIGH(x) ((x) &= ~ BIT((sizeof((x))*8-1))) // clr the highest bit
#define BIT_IS_SET_HIGH(x) ((x) & BIT((sizeof((x))*8-1))) // check the higest bit
#define BIT_MASK_LEN(len) (BIT(len)-1)
#define BIT_MASK(start, len) (BIT_MASK_LEN(len) << (start))
//! Prepare a bitmask for insertion or combining.
#define BIT_PREP(x, start, len) ((x)&BIT_MASK(start, len))
#define BIT_PREP(x, start, len) ((x) & BIT_MASK(start, len))
//! Extract a bitfield of length \a len starting at bit \a start from \a y.
#define BIT_GET(x, start, len) (((x) >> (start)) & BIT_MASK_LEN(len))
#define BIT_GET_LOW(x, len) ((x)&BIT_MASK_LEN(len))
#define BIT_GET(x, start, len) (((x) >> (start)) & BIT_MASK_LEN(len))
#define BIT_GET_LOW(x, len) ((x) & BIT_MASK_LEN(len))
//! Insert a new bitfield value \a x into \a y.
#define BIT_MERGE(y, x, start, len) (y = ((y) & ~BIT_MASK(start, len)) | BIT_PREP(x, start, len))
#define BIT_MERGE(y, x, start, len) \
((y) = ((y) &~ BIT_MASK(start, len)) | BIT_PREP((x), start, len))
#define BIT_IS_EVEN(x) (((x)&1) == 0)
#define BIT_IS_EVEN(x) (((x)&1)==0)
#define BIT_IS_ODD(x) (!BIT_IS_EVEN((x)))
#define BIT_IS_POW2(x) (!((x) & ((x)-1)))
#define BIT_TURNOFF_1(x) ((x) &= ((x)-1))
#define BIT_ISOLATE_1(x) ((x) &= (-(x)))
#define BIT_PROPAGATE_1(x) ((x) |= ((x)-1))
#define BIT_ISOLATE_0(x) ((x) = ~(x) & ((x) + 1))
#define BIT_TURNON_0(x) ((x) |= ((x) + 1))
#define CLAMP_TO_ONE(x) (!!(x)) // compiler defined, not stardard. 0 --> 0, 1 --> 0xffffffff
#define BIT_ISOLATE_0(x) ((x) = ~(x) & ((x)+1))
#define BIT_TURNON_0(x) ((x) |= ((x)+1))
#define CLAMP_TO_ONE(x) (!!(x)) // compiler defined, not stardard. 0 --> 0, 1 --> 0xffffffff
#define ONES(x) BIT_MASK_LEN(x)
#define ONES_32 0xffffffff
#define ALL_SET 0xffffffff
#define ONES(x) BIT_MASK_LEN(x)
#define ONES_32 0xffffffff
#define ALL_SET 0xffffffff
// Return the bit index of the lowest 1 in y. ex: 0b00110111000 --> 3
#define BIT_LOW_BIT(y) \
( \
((y)&BIT(0)) ? 0 \
: ( \
((y)&BIT(1)) ? 1 \
: (((y)&BIT(2)) ? 2 \
: (((y)&BIT(3)) ? 3 \
: (((y)&BIT(4)) ? 4 \
: (((y)&BIT(5)) ? 5 \
: (((y)&BIT(6)) ? 6 \
: ( \
((y)&BIT(7)) ? 7 \
: ( \
((y)&BIT(8)) ? 8 \
: ( \
((y)&BIT(9)) ? 9 \
: ( \
((y)&BIT(10)) ? 10 \
: ( \
((y)&BIT(11)) ? 11 \
: ( \
( \
(y)&BIT( \
12)) \
? 12 \
: ( \
((y)&BIT(13)) ? 13 \
: ( \
((y)&BIT(14)) ? 14 \
: (((y)&BIT(15)) ? 15 \
: ( \
( \
(y)&BIT( \
16)) \
? 16 \
: ( \
((y)&BIT( \
17)) \
? 17 \
: ( \
((y)&BIT( \
18)) \
? 18 \
: ( \
(( \
y)&BIT(19)) \
? 19 \
: ( \
((y)&BIT( \
20)) \
? 20 \
: ( \
((y)&BIT(21)) ? 21 \
: ( \
((y)&BIT( \
22)) \
? 22 \
: (((y)&BIT(23)) ? 23 \
: ( \
((y)&BIT( \
24)) \
? 24 \
: ( \
((y)&BIT(25)) ? 25 \
: (( \
( \
y)&BIT(26)) \
? 26 \
: ( \
((y)&BIT(27)) ? 27 \
: ( \
((y)&BIT(28)) ? 28 \
: ( \
((y)&BIT(29)) ? 29 \
: ( \
((y)&BIT(30)) ? 30 : (((y)&BIT(31)) ? 31 : 32))))))))))))))))))))))))))))))))
#define BIT_LOW_BIT(y) (((y) & BIT(0)) ? 0 : (((y) & BIT(1)) ? 1 : (((y) & BIT(2)) ? 2 : \
(((y) & BIT(3)) ? 3 : (((y) & BIT(4)) ? 4 : (((y) & BIT(5)) ? 5 : \
(((y) & BIT(6)) ? 6 : (((y) & BIT(7)) ? 7 : (((y) & BIT(8)) ? 8 : \
(((y) & BIT(9)) ? 9 : (((y) & BIT(10)) ? 10 : (((y) & BIT(11)) ? 11 : \
(((y) & BIT(12)) ? 12 : (((y) & BIT(13)) ? 13 : (((y) & BIT(14)) ? 14 : \
(((y) & BIT(15)) ? 15 : (((y) & BIT(16)) ? 16 : (((y) & BIT(17)) ? 17 : \
(((y) & BIT(18)) ? 18 : (((y) & BIT(19)) ? 19 : (((y) & BIT(20)) ? 20 : \
(((y) & BIT(21)) ? 21 : (((y) & BIT(22)) ? 22 : (((y) & BIT(23)) ? 23 : \
(((y) & BIT(24)) ? 24 : (((y) & BIT(25)) ? 25 : (((y) & BIT(26)) ? 26 : \
(((y) & BIT(27)) ? 27 : (((y) & BIT(28)) ? 28 : (((y) & BIT(29)) ? 29 : \
(((y) & BIT(30)) ? 30 : (((y) & BIT(31)) ? 31 : 32 \
))))))))))))))))))))))))))))))))
// Return the bit index of the highest 1 in (y). ex: 0b00110111000 --> 8
#define BIT_HIGH_BIT(y) \
( \
((y)&BIT(31)) \
? 31 \
: ( \
((y)&BIT(30)) \
? 30 \
: ( \
((y)&BIT(29)) \
? 29 \
: ( \
((y)&BIT(28)) \
? 28 \
: ( \
((y)&BIT(27)) \
? 27 \
: (((y)&BIT(26)) \
? 26 \
: (((y)&BIT(25)) \
? 25 \
: (((y)&BIT(24)) \
? 24 \
: (((y)&BIT(23)) \
? 23 \
: (((y)&BIT(22)) \
? 22 \
: (((y)&BIT(21)) \
? 21 \
: (((y)&BIT(20)) ? 20 \
: (((y)&BIT(19)) ? 19 \
: ( \
((y)&BIT(18)) ? 18 \
: ( \
((y)&BIT(17)) ? 17 \
: ( \
((y)&BIT(16)) ? 16 \
: ( \
((y)&BIT(15)) ? 15 \
: ( \
((y)&BIT(14)) ? 14 \
: (((y)&BIT(13)) ? 13 \
: (((y)&BIT(12)) ? 12 \
: (((y)&BIT( \
11)) \
? 11 \
: ( \
((y)&BIT( \
10)) \
? 10 \
: ( \
((y)&BIT( \
9)) \
? 9 \
: ( \
( \
(y)&BIT(8)) \
? 8 \
: (((y)&BIT(7)) ? 7 \
: ( \
( \
( \
y)&BIT(6)) \
? 6 \
: (((y)&BIT( \
5)) \
? 5 \
: (((y)&BIT(4)) ? 4 \
: (((y)&BIT( \
3)) \
? 3 \
: (((y)&BIT( \
2)) \
? 2 \
: (((y)&BIT(1)) ? 1 \
: ( \
((y)&BIT(0)) ? 0 : 32))))))))))))))))))))))))))))))))
#define BIT_HIGH_BIT(y) (((y) & BIT(31)) ? 31 : (((y) & BIT(30)) ? 30 : (((y) & BIT(29)) ? 29 : \
(((y) & BIT(28)) ? 28 : (((y) & BIT(27)) ? 27 : (((y) & BIT(26)) ? 26 : \
(((y) & BIT(25)) ? 25 : (((y) & BIT(24)) ? 24 : (((y) & BIT(23)) ? 23 : \
(((y) & BIT(22)) ? 22 : (((y) & BIT(21)) ? 21 : (((y) & BIT(20)) ? 20 : \
(((y) & BIT(19)) ? 19 : (((y) & BIT(18)) ? 18 : (((y) & BIT(17)) ? 17 : \
(((y) & BIT(16)) ? 16 : (((y) & BIT(15)) ? 15 : (((y) & BIT(14)) ? 14 : \
(((y) & BIT(13)) ? 13 : (((y) & BIT(12)) ? 12 : (((y) & BIT(11)) ? 11 : \
(((y) & BIT(10)) ? 10 : (((y) & BIT(9)) ? 9 : (((y) & BIT(8)) ? 8 : \
(((y) & BIT(7)) ? 7 : (((y) & BIT(6)) ? 6 : (((y) & BIT(5)) ? 5 : \
(((y) & BIT(4)) ? 4 : (((y) & BIT(3)) ? 3 : (((y) & BIT(2)) ? 2 : \
(((y) & BIT(1)) ? 1 : (((y) & BIT(0)) ? 0 : 32 \
))))))))))))))))))))))))))))))))
#define BM_MASK_FLD(x, mask) (((x) & (mask)) >> BIT_LOW_BIT(mask))
#define BM_SET_MASK_FLD(x, mask, v) ((x) = BM_MASK_VAL(x, mask, v))
#define BM_MASK_FLD(x, mask) (((x) & (mask)) >> BIT_LOW_BIT(mask))
#define BM_SET_MASK_FLD(x, mask, v) ((x) = BM_MASK_VAL(x, mask, v))
//////////////////////
#define MV(m, v) (((v) << BIT_LOW_BIT(m)) & (m))
#define MV(m, v) (((v) << BIT_LOW_BIT(m)) & (m))
// warning MASK_VALn are internal used macro, please use MASK_VAL instead
#define MASK_VAL2(m, v) (MV(m, v))
#define MASK_VAL4(m1, v1, m2, v2) (MV(m1, v1) | MV(m2, v2))
#define MASK_VAL6(m1, v1, m2, v2, m3, v3) (MV(m1, v1) | MV(m2, v2) | MV(m3, v3))
#define MASK_VAL8(m1, v1, m2, v2, m3, v3, m4, v4) (MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4))
#define MASK_VAL10(m1, v1, m2, v2, m3, v3, m4, v4, m5, v5) \
(MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4) | MV(m5, v5))
#define MASK_VAL12(m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6) \
(MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4) | MV(m5, v5) | MV(m6, v6))
#define MASK_VAL14(m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6, m7, v7) \
(MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4) | MV(m5, v5) | MV(m6, v6) | MV(m7, v7))
#define MASK_VAL16(m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6, m7, v7, m8, v8) \
(MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4) | MV(m5, v5) | MV(m6, v6) | MV(m7, v7) | MV(m8, v8))
#define MASK_VAL2(m, v) (MV(m, v))
#define MASK_VAL4(m1, v1, m2, v2) (MV(m1, v1) | MV(m2, v2))
#define MASK_VAL6(m1, v1, m2, v2, m3, v3) (MV(m1, v1) | MV(m2, v2) | MV(m3, v3))
#define MASK_VAL8(m1, v1, m2, v2, m3, v3, m4, v4) (MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | \
MV(m4, v4))
#define MASK_VAL10(m1, v1, m2, v2, m3, v3, m4, v4, m5, v5) (MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | \
MV(m4, v4) | MV(m5, v5))
#define MASK_VAL12(m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6) (MV(m1, v1) | MV(m2, v2) | \
MV(m3, v3) | MV(m4, v4) | MV(m5, v5) | MV(m6, v6))
#define MASK_VAL14(m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6, m7, v7) (MV(m1, v1) | MV(m2, v2) | \
MV(m3, v3) | MV(m4, v4) | MV(m5, v5) | MV(m6, v6) | MV(m7, v7))
#define MASK_VAL16(m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6, m7, v7, m8, v8) (MV(m1, v1) | MV(m2, v2) | \
MV(m3, v3) | MV(m4, v4) | MV(m5, v5) | MV(m6, v6) | MV(m7, v7) | MV(m8, v8))
#define MASK_VAL(...) VARARG(MASK_VAL, __VA_ARGS__)
#define MASK_VAL(...) VARARG(MASK_VAL, __VA_ARGS__)
#define FLD_MASK_VAL(x, mask, v) BM_MASK_VAL(x, mask, MV(mask, v))
#define FLD_MASK_VAL(x, mask, v) BM_MASK_VAL(x, mask, MV(mask, v))
#define SET_FLD(x, mask) BM_SET(x, mask)
#define CLR_FLD(x, mask) BM_CLR(x, mask)
#define FLIP_FLD(x, mask) BM_FLIP(x, mask)
#define SET_FLD(x, mask) BM_SET(x, mask)
#define CLR_FLD(x, mask) BM_CLR(x, mask)
#define FLIP_FLD(x, mask) BM_FLIP(x, mask)
#define GET_FLD(x, mask) BM_MASK_FLD(x, mask)
#define GET_FLD(x, mask) BM_MASK_FLD(x, mask)
#define SET_FLD_V(...) VARARG(SET_FLD_V, __VA_ARGS__)
#define SET_FLD_V(...) VARARG(SET_FLD_V, __VA_ARGS__)
// ¸úÉÏÒ»¸öºê²»Ò»Ñù£¬Õâ¸ö±íʾֱ½Ó¸³Öµ
#define SET_FLD_FULL_V3(x, m, v) ((x) = MASK_VAL2(m, v))
#define SET_FLD_FULL_V5(x, m1, v1, m2, v2) ((x) = MASK_VAL4(m1, v1, m2, v2))
#define SET_FLD_FULL_V7(x, m1, v1, m2, v2, m3, v3) ((x) = MASK_VAL6(m1, v1, m2, v2, m3, v3))
#define SET_FLD_FULL_V9(x, m1, v1, m2, v2, m3, v3, m4, v4) ((x) = MASK_VAL8(m1, v1, m2, v2, m3, v3, m4, v4))
#define SET_FLD_FULL_V11(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5) \
((x) = MASK_VAL10(m1, v1, m2, v2, m3, v3, m4, v4, m5, v5))
#define SET_FLD_FULL_V13(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6) \
((x) = MASK_VAL12(m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6))
#define SET_FLD_FULL_V(...) VARARG(SET_FLD_FULL_V, __VA_ARGS__)
#define SET_FLD_FULL_V3(x, m, v) ((x) = MASK_VAL2(m, v))
#define SET_FLD_FULL_V5(x, m1, v1, m2, v2) ((x) = MASK_VAL4(m1, v1, m2, v2))
#define SET_FLD_FULL_V7(x, m1, v1, m2, v2, m3, v3) ((x) = MASK_VAL6(m1, v1, m2, v2, m3, v3))
#define SET_FLD_FULL_V9(x, m1, v1, m2, v2, m3, v3, m4, v4) ((x) = MASK_VAL8(m1, v1, m2, v2, m3, v3, \
m4, v4))
#define SET_FLD_FULL_V11(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5) ((x) = MASK_VAL10(m1, v1, m2, v2, m3, \
v3, m4, v4, m5, v5))
#define SET_FLD_FULL_V13(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6) ((x) = MASK_VAL12(m1, v1, m2, v2, m3, \
v3, m4, v4, m5, v5, m6, v6))
#define SET_FLD_FULL_V(...) VARARG(SET_FLD_FULL_V, __VA_ARGS__)
////////////////////////////////////////////////////////////////////////
#define BIT8_IFY(y) \
(((y & 0x0000000FLU) ? 1 : 0) + ((y & 0x000000F0LU) ? 2 : 0) + ((y & 0x00000F00LU) ? 4 : 0) + \
((y & 0x0000F000LU) ? 8 : 0) + ((y & 0x000F0000LU) ? 16 : 0) + ((y & 0x00F00000LU) ? 32 : 0) + \
((y & 0x0F000000LU) ? 64 : 0) + ((y & 0xF0000000LU) ? 128 : 0))
#define BIT8_IFY(y) ( \
(((y) & 0x0000000FLU) ? 1 : 0) + (((y) & 0x000000F0LU) ? 2 : 0) + \
(((y) & 0x00000F00LU) ? 4 : 0) + (((y) & 0x0000F000LU) ? 8 : 0) + \
(((y) & 0x000F0000LU) ? 16 : 0) + (((y) & 0x00F00000LU) ? 32 : 0) + \
(((y) & 0x0F000000LU) ? 64 : 0) + (((y) & 0xF0000000LU) ? 128 : 0) \
)
#define HEX_X(i) (0x##i##LU)
#define HEX_X(i) (0x##i##LU)
#define BIT_8(j) ((unsigned char)BIT8_IFY(HEX_X(j)))
#define BIT_8(j) ((unsigned char)BIT8_IFY(HEX_X(j)))
#ifndef WIN32
// warning SET_FLD_Vn are internal used macro, please use SET_FLD_V instead
#define SET_FLD_V3(x, m, v) BM_SET_MASK_FLD(x, m, MV(m, v))
// warning SET_FLD_Vn are internal used macro, please use SET_FLD_V instead
#define SET_FLD_V3(x, m, v) \
BM_SET_MASK_FLD(x, m, MV(m, v))
#define SET_FLD_V5(x, m1, v1, m2, v2) BM_SET_MASK_FLD(x, m1 | m2, MV(m1, v1) | MV(m2, v2))
#define SET_FLD_V5(x, m1, v1, m2, v2) \
BM_SET_MASK_FLD((x), (m1) | (m2), MV((m1), (v1)) | MV((m2), (v2)))
#define SET_FLD_V7(x, m1, v1, m2, v2, m3, v3) BM_SET_MASK_FLD(x, m1 | m2 | m3, MV(m1, v1) | MV(m2, v2) | MV(m3, v3))
#define SET_FLD_V7(x, m1, v1, m2, v2, m3, v3) \
BM_SET_MASK_FLD((x), (m1) | (m2) | (m3), MV((m1), (v1)) | MV((m2), (v2)) | MV((m3), (v3)))
#define SET_FLD_V9(x, m1, v1, m2, v2, m3, v3, m4, v4) \
BM_SET_MASK_FLD(x, m1 | m2 | m3 | m4, MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4))
#define SET_FLD_V9(x, m1, v1, m2, v2, m3, v3, m4, v4) \
BM_SET_MASK_FLD((x), (m1) | (m2) | (m3) | (m4), MV((m1), (v1)) | MV((m2), (v2)) | \
MV((m3), (v3)) | MV((m4), (v4)))
#define SET_FLD_V11(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5) \
BM_SET_MASK_FLD(x, m1 | m2 | m3 | m4 | m5, MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4) | MV(m5, v5))
#define SET_FLD_V11(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5) \
BM_SET_MASK_FLD((x), (m1) | (m2) | (m3) | (m4) | (m5), MV((m1), (v1)) | MV((m2), (v2)) | \
MV((m3), (v3)) | MV((m4), (v4)) | MV((m5), (v5)))
#define SET_FLD_V13(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6) \
BM_SET_MASK_FLD(x, m1 | m2 | m3 | m4 | m5 | m6, \
MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4) | MV(m5, v5) | MV(m6, v6))
#define SET_FLD_V13(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6) \
BM_SET_MASK_FLD((x), (m1) | (m2) | (m3) | (m4) | (m5) | (m6), MV((m1), (v1)) | MV((m2), (v2)) | \
MV((m3), (v3)) | MV((m4), (v4)) | MV((m5), (v5)) | MV((m6), (v6)))
#else
#define SET_FLD_V3(x, m, v) \
__pragma(warning(push)) __pragma(warning(disable : 4244)) BM_SET_MASK_FLD(x, m, MV(m, v)) __pragma(warning(pop))
#define SET_FLD_V5(x, m1, v1, m2, v2) \
__pragma(warning(push)) __pragma(warning(disable : 4244)) BM_SET_MASK_FLD(x, m1 | m2, MV(m1, v1) | MV(m2, v2)) \
#define SET_FLD_V3(x, m, v) \
__pragma(warning(push)) \
__pragma(warning(disable:4244)) \
BM_SET_MASK_FLD(x, m, MV(m, v)) \
__pragma(warning(pop))
#define SET_FLD_V7(x, m1, v1, m2, v2, m3, v3) \
__pragma(warning(push)) __pragma(warning(disable : 4244)) \
BM_SET_MASK_FLD(x, m1 | m2 | m3, MV(m1, v1) | MV(m2, v2) | MV(m3, v3)) __pragma(warning(pop))
#define SET_FLD_V5(x, m1, v1, m2, v2) \
__pragma(warning(push)) \
__pragma(warning(disable:4244)) \
BM_SET_MASK_FLD(x, m1 | m2, MV(m1, v1) | MV(m2, v2)) \
__pragma(warning(pop))
#define SET_FLD_V9(x, m1, v1, m2, v2, m3, v3, m4, v4) \
__pragma(warning(push)) __pragma(warning(disable : 4244)) \
BM_SET_MASK_FLD(x, m1 | m2 | m3 | m4, MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4)) \
__pragma(warning(pop))
#define SET_FLD_V7(x, m1, v1, m2, v2, m3, v3) \
__pragma(warning(push)) \
__pragma(warning(disable:4244)) \
BM_SET_MASK_FLD(x, m1 | m2 | m3, MV(m1, v1) | MV(m2, v2) | MV(m3, v3)) \
__pragma(warning(pop))
#define SET_FLD_V11(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5) \
__pragma(warning(push)) __pragma(warning(disable : 4244)) \
BM_SET_MASK_FLD(x, m1 | m2 | m3 | m4 | m5, MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4) | MV(m5, v5)) \
__pragma(warning(pop))
#define SET_FLD_V9(x, m1, v1, m2, v2, m3, v3, m4, v4) \
__pragma(warning(push)) \
__pragma(warning(disable:4244)) \
BM_SET_MASK_FLD(x, m1 | m2 | m3 | m4, MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4)) \
__pragma(warning(pop))
#define SET_FLD_V13(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6) \
__pragma(warning(push)) __pragma(warning(disable : 4244)) BM_SET_MASK_FLD( \
x, m1 | m2 | m3 | m4 | m5 | m6, MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4) | MV(m5, v5) | MV(m6, v6)) \
#define SET_FLD_V11(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5) \
__pragma(warning(push)) \
__pragma(warning(disable:4244)) \
BM_SET_MASK_FLD(x, m1 | m2 | m3 | m4 | m5, MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4) | MV(m5, v5)) \
__pragma(warning(pop))
#define SET_FLD_V13(x, m1, v1, m2, v2, m3, v3, m4, v4, m5, v5, m6, v6) \
__pragma(warning(push)) \
__pragma(warning(disable:4244)) \
BM_SET_MASK_FLD(x, m1 | m2 | m3 | m4 | m5 | m6, MV(m1, v1) | MV(m2, v2) | MV(m3, v3) | MV(m4, v4) | \
MV(m5, v5) | MV(m6, v6)) \
__pragma(warning(pop))
#endif
#endif // B91_B91_BLE_SDK_COMMON_BIT_H
b91/b91_ble_sdk/common/compiler.h
+1 -1
View File
@@ -37,7 +37,7 @@
#define _attribute_custom_code_ _attribute_session_(".custom") volatile
#define _attribute_no_inline_ __attribute__((noinline))
#define _inline_ inline
#define _attribute_data_dlm_ _attribute_session_(".dlm_data") //dlm:Data Local Memory
#define _attribute_data_dlm_ _attribute_session_(".dlm_data") // dlm:Data Local Memory
#ifndef BLC_PM_EN
#define BLC_PM_EN 1
#endif
b91/b91_ble_sdk/common/macro_trick.h
-16
View File
@@ -39,21 +39,6 @@
#define MACRO_GLUE(x, y) x y
#define VARARG(base, ...) MACRO_GLUE(MACRO_CHOOSE_HELPER(base, COUNT_ARGS(__VA_ARGS__)), (__VA_ARGS__))
// usage
/*
#define fun1(a) xxxx
#define fun2(a, b) xxxx
#define fun3(a, b, c) xxxx
#define fun(...) VARARG(fun, __VA_ARGS__)
int main(){
fun(1); // calls fun1(1)
fun(1, 2); // calls fun2(1,2)
fun(1, 2, 3); // calls fun3(1,2,3)
}
*/
#else
// a concise version that only works with GCC
@@ -67,7 +52,6 @@
#define VARARG(base, ...) VARARG_IMPL(base, VA_NARGS(__VA_ARGS__), __VA_ARGS__)
#endif
// #define NUMARGS(...) (sizeof((int[]){__VA_ARGS__})/sizeof(int))
///////////////// end of variadic macro //////////////////////
b91/b91_ble_sdk/common/static_assert.h
+4 -6
View File
@@ -15,12 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
// static assertion. evaluate at compile time. It is very useful like, STATIC_ASSERT(sizeof(a) == 5);
// #define STATIC_ASSERT(expr) { char static_assertion[(expr) ? 1 : -1]; ((void) static_assertion); } // (void) array; to remove compiler unused variable warning
#ifndef B91_B91_BLE_SDK_COMMON_STATIC_ASSERT_H
#define B91_B91_BLE_SDK_COMMON_STATIC_ASSERT_H
// more complicated version canbe used anywhere in the source
#define STATIC_ASSERT_M(COND, MSG) typedef char static_assertion_##MSG[(!!(COND)) * 2 - 1]
@@ -34,3 +30,5 @@
#define STATIC_ASSERT_EVEN(expr) STATIC_ASSERT(!((expr)&1))
#define STATIC_ASSERT_ODD(expr) STATIC_ASSERT(((expr)&1))
#define STATIC_ASSERT_INT_DIV(a, b) STATIC_ASSERT((a) / (b) * (b) == (a))
#endif // B91_B91_BLE_SDK_COMMON_STATIC_ASSERT_H
b91/b91_ble_sdk/common/types.h
+6 -9
View File
@@ -15,8 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_COMMON_TYPES_H
#define B91_B91_BLE_SDK_COMMON_TYPES_H
#include <stdbool.h>
@@ -37,13 +37,11 @@ typedef long long s64;
typedef unsigned long long u64;
// #ifndef NULL
// #define NULL 0
// #endif
#ifndef __cplusplus
//typedef u8 bool;
#ifndef FALSE
#define FALSE 0
#endif
@@ -51,15 +49,12 @@ typedef unsigned long long u64;
#define TRUE (!FALSE)
#endif
//#define false FALSE
//#define true TRUE
#endif
// There is no way to directly recognise whether a typedef is defined
// http://stackoverflow.com/questions/3517174/how-to-check-if-a-datatype-is-defined-with-typedef
#ifdef __GNUC__
//typedef u16 wchar_t;
#endif
#ifndef WIN32
@@ -89,3 +84,5 @@ typedef u32 size_t;
typedef u32 UTCTime;
typedef u32 arg_t;
typedef u32 status_t;
#endif // B91_B91_BLE_SDK_COMMON_TYPES_H
b91/b91_ble_sdk/common/utility.c
+1 -2
View File
@@ -99,8 +99,7 @@ u8 *my_fifo_wptr(my_fifo_t *f)
u8 *my_fifo_wptr_v2(my_fifo_t *f)
{
if (((f->wptr - f->rptr) & 255) < f->num - 3) //keep 3 fifo left for others evt
{
if (((f->wptr - f->rptr) & 255) < f->num - 3) { // keep 3 fifo left for others evt
return f->p + (f->wptr & (f->num - 1)) * f->size;
}
return 0;
b91/b91_ble_sdk/common/utility.h
+112 -101
View File
@@ -15,121 +15,108 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_COMMON_UTILITY_H
#define B91_B91_BLE_SDK_COMMON_UTILITY_H
#include "types.h"
#define abs(a) (((a) > 0) ? ((a)) : (-(a)))
#define abs(a) (((a)>0)?((a)):(-(a)))
#define cat2(i, j) i##j
#define cat3(i, j, k) i##j##k
#define cat2(i, j) i##j
#define cat3(i, j, k) i##j##k
#ifndef min
#define min(a, b) ((a) < (b) ? (a) : (b))
#define min(a, b) ((a) < (b) ? (a) : (b))
#endif
#ifndef min2
#define min2(a, b) ((a) < (b) ? (a) : (b))
#define min2(a, b) ((a) < (b) ? (a) : (b))
#endif
#ifndef min3
#define min3(a, b, c) min2(min2(a, b), c)
#define min3(a, b, c) min2(min2(a, b), c)
#endif
#ifndef max2
#define max2(a, b) ((a) > (b) ? (a) : (b))
#define max2(a, b) ((a) > (b) ? (a) : (b))
#endif
#ifndef max3
#define max3(a, b, c) max2(max2(a, b), c)
#define max3(a, b, c) max2(max2(a, b), c)
#endif
#define OFFSETOF(s, m) ((unsigned int)&((s *)0)->m)
#define ROUND_INT(x, r) (((x) + (r)-1) / (r) * (r))
#define ROUND_TO_POW2(x, r) (((x) + (r)-1) & ~((r)-1))
#define OFFSETOF(s, m) ((unsigned int) &((s *)0)->m)
#define ROUND_INT(x, r) (((x) + (r) - 1) / (r) * (r))
#define ROUND_TO_POW2(x, r) (((x) + (r) - 1) & ~((r) - 1))
// direct memory access
#define U8_GET(addr) (*(volatile unsigned char *)(addr))
#define U16_GET(addr) (*(volatile unsigned short *)(addr))
#define U32_GET(addr) (*(volatile unsigned int *)(addr))
#define U8_GET(addr) (*(volatile unsigned char *)(addr))
#define U16_GET(addr) (*(volatile unsigned short *)(addr))
#define U32_GET(addr) (*(volatile unsigned int *)(addr))
#define U8_SET(addr, v) (*(volatile unsigned char *)(addr) = (unsigned char)(v))
#define U16_SET(addr, v) (*(volatile unsigned short *)(addr) = (unsigned short)(v))
#define U32_SET(addr, v) (*(volatile unsigned int *)(addr) = (v))
#define U8_SET(addr, v) (*(volatile unsigned char *)(addr) = (unsigned char)(v))
#define U16_SET(addr, v) (*(volatile unsigned short *)(addr) = (unsigned short)(v))
#define U32_SET(addr, v) (*(volatile unsigned int *)(addr) = (v))
#define U8_INC(addr) U8_GET(addr) += 1
#define U16_INC(addr) U16_GET(addr) += 1
#define U32_INC(addr) U32_GET(addr) += 1
#define U8_INC(addr) U8_GET(addr) += 1
#define U16_INC(addr) U16_GET(addr) += 1
#define U32_INC(addr) U32_GET(addr) += 1
#define U8_DEC(addr) U8_GET(addr) -= 1
#define U16_DEC(addr) U16_GET(addr) -= 1
#define U32_DEC(addr) U32_GET(addr) -= 1
#define U8_DEC(addr) U8_GET(addr) -= 1
#define U16_DEC(addr) U16_GET(addr) -= 1
#define U32_DEC(addr) U32_GET(addr) -= 1
#define U8_CPY(addr1, addr2) U8_SET(addr1, U8_GET(addr2))
#define U16_CPY(addr1, addr2) U16_SET(addr1, U16_GET(addr2))
#define U32_CPY(addr1, addr2) U32_SET(addr1, U32_GET(addr2))
#define U8_CPY(addr1, addr2) U8_SET(addr1, U8_GET(addr2))
#define U16_CPY(addr1, addr2) U16_SET(addr1, U16_GET(addr2))
#define U32_CPY(addr1, addr2) U32_SET(addr1, U32_GET(addr2))
#define MAKE_U16(h, l) ((unsigned short)(((h) << 8) | (l)))
#define MAKE_U24(a, b, c) ((unsigned int)(((a) << 16) | ((b) << 8) | (c)))
#define MAKE_U32(a, b, c, d) ((unsigned int)(((a) << 24) | ((b) << 16) | ((c) << 8) | (d)))
#define MAKE_U16(h, l) ((unsigned short)(((h) << 8) | (l)))
#define MAKE_U24(a, b, c) ((unsigned int)(((a) << 16) | ((b) << 8) | (c)))
#define MAKE_U32(a, b, c, d) ((unsigned int)(((a) << 24) | ((b) << 16) | ((c) << 8) | (d)))
#define BOUND(x, l, m) ((x) < (l) ? (l) : ((x) > (m) ? (m) : (x)))
#define SET_BOUND(x, l, m) ((x) = BOUND(x, l, m))
#define BOUND_INC(x, m) \
do { \
++(x); \
(x) = (x) < (m) ? (x) : 0; \
} while (0)
#define BOUND_INC_POW2(x, m) \
do { \
(x) = ((x) + 1) & (m - 1); \
} while (0)
#define BOUND(x, l, m) ((x) < (l) ? (l) : ((x) > (m) ? (m) : (x)))
#define SET_BOUND(x, l, m) ((x) = BOUND(x, l, m))
#define BOUND_INC(x, m) do {++(x); (x) = (x) < (m) ? (x) :0;} while (0)
#define BOUND_INC_POW2(x, m) do { \
(x) = ((x)+1) & ((m)-1); \
} while (0)
#define IS_POWER_OF_2(x) (!(x & (x - 1)))
#define IS_LITTLE_ENDIAN (*(unsigned short *)"\0\xff" > 0x100)
#define IS_POWER_OF_2(x) (!((x) & ((x)-1)))
#define IS_LITTLE_ENDIAN (*(unsigned short*)"\0\xff" > 0x100)
#define IMPLIES(x, y) (!(x) || (y))
#define IMPLIES(x, y) (!(x) || (y))
// x > y ? 1 : (x ==y : 0 ? -1)
#define COMPARE(x, y) (((x) > (y)) - ((x) < (y)))
#define SIGN(x) COMPARE(x, 0)
#define COMPARE(x, y) (((x) > (y)) - ((x) < (y)))
#define SIGN(x) COMPARE(x, 0)
// better than xor swap: http://stackoverflow.com/questions/3912699/why-swap-with-xor-works-fine-in-c-but-in-java-doesnt-some-puzzle
#define SWAP(x, y, T) \
do { \
T tmp = (x); \
(x) = (y); \
(y) = tmp; \
} while (0)
#define SORT2(a, b, T) \
do { \
if ((a) > (b)) \
SWAP((a), (b), T); \
} while (0)
// better than xor swap:
// http://stackoverflow.com/questions/3912699/why-swap-with-xor-works-fine-in-c-but-in-java-doesnt-some-puzzle
#define SWAP(x, y, T) do { T tmp = (x); (x) = (y); (y) = tmp; } while (0)
#define SORT2(a, b, T) do { if ((a) > (b)) SWAP((a), (b), T); } while (0)
#define foreach(i, n) for (int i = 0; i < (n); ++i)
#define foreach_range(i, s, e) for (int i = (s); i < (e); ++i)
#define foreach_arr(i, arr) for (int i = 0; i < ARRAY_SIZE(arr); ++i)
// round robbin foreach, ´ÓÉÏÒ»¸öÖ¸¶¨µÄµã¿ªÊ¼£¬±éÀú, h ÊÇÒ»¸ö¾²Ì¬±äÁ¿»òÈ«¾Ö±äÁ¿£¬Òª¼ÇסÉÏÒ»´ÎµÄλÖá£h ³õʼֵÊÇn !!!
#define foreach_hint(i, n, h) for (int i = 0, ++h, h = h < n ? h : 0; i < n; ++h, h = h < n ? h : 0)
#define foreach(i, n) for (int (i) = 0; (i) < ((n)); ++(i))
#define foreach_range(i, s, e) for (int (i) = (s); (i) < (e); ++(i))
#define foreach_arr(i, arr) for (int (i) = 0; (i) < ARRAY_SIZE(arr); ++(i))
// round robbin foreach
#define foreach_hint(i, n, h) \
for (int(i) = 0, ++(h), (h) = (h) < (n) ? (h) : 0; (i) < (n); ++(h), (h) = (h) < (n) ? (h) : 0)
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(a) (sizeof(a) / sizeof(*a))
#endif // ARRAY_SIZE
#define ARRAY_SIZE(a) (sizeof(a) / sizeof(*(a)))
#endif // ARRAY_SIZE
#define everyN(i, n) \
++(i); \
(i) = ((i) < N ? (i) : 0); \
if (0 == (i))
#define everyN(i, n) ++(i); (i) = ((i) < N ? (i) : 0); if (0 == (i))
#define U16_HI(a) (((a) >> 8) & 0xFF)
#define U16_LO(a) ((a)&0xFF)
#define U16_HI(a) (((a) >> 8) & 0xFF)
#define U16_LO(a) ((a) & 0xFF)
#define U32_BYTE0(a) ((a)&0xFF)
#define U32_BYTE0(a) ((a) & 0xFF)
#define U32_BYTE1(a) (((a) >> 8) & 0xFF)
#define U32_BYTE2(a) (((a) >> 16) & 0xFF)
#define U32_BYTE3(a) (((a) >> 24) & 0xFF)
void swapN(unsigned char *p, int n);
void swapN (unsigned char *p, int n);
void swapX(const u8 *src, u8 *dst, int len);
void swap24(u8 dst[3], const u8 src[3]);
@@ -145,40 +132,64 @@ void flip_addr(u8 *dest, u8 *src);
static inline u64 mul64_32x32(u32 u, u32 v)
{
return (u64)u * v;
if (0) { // Eagle HW support this process
u32 u0, v0, w0;
u32 u1, v1, w1, w2, t;
u32 x, y;
u0 = u & 0xFFFF;
u1 = u >> 16;
v0 = v & 0xFFFF;
v1 = v >> 16;
w0 = u0 * v0;
t = u1 * v0 + (w0 >> 16);
w1 = t & 0xFFFF;
w2 = t >> 16;
w1 = u0 * v1 + w1;
// x is high 32 bits, y is low 32 bits
x = u1 * v1 + w2 + (w1 >> 16);
y = u * v;
return(((u64)x << 32) | y);
} else {
return (u64)u*v;
}
}
typedef struct
{
u32 size;
u16 num;
u8 wptr;
u8 rptr;
u8 *p;
} my_fifo_t;
typedef struct {
u32 size;
u16 num;
u8 wptr;
u8 rptr;
u8* p;
} my_fifo_t;
void my_fifo_init(my_fifo_t *f, int s, u8 n, u8 *p);
u8 *my_fifo_wptr(my_fifo_t *f);
u8 *my_fifo_wptr_v2(my_fifo_t *f);
void my_fifo_next(my_fifo_t *f);
int my_fifo_push(my_fifo_t *f, u8 *p, int n);
void my_fifo_pop(my_fifo_t *f);
u8 *my_fifo_get(my_fifo_t *f);
void my_fifo_init (my_fifo_t *f, int s, u8 n, u8 *p);
u8* my_fifo_wptr (my_fifo_t *f);
u8* my_fifo_wptr_v2 (my_fifo_t *f);
void my_fifo_next (my_fifo_t *f);
int my_fifo_push (my_fifo_t *f, u8 *p, int n);
void my_fifo_pop (my_fifo_t *f);
u8* my_fifo_get (my_fifo_t *f);
#define MYFIFO_INIT(name, size, n) \
u8 name##_b[size * n] = {0}; \
my_fifo_t name = {size, n, 0, 0, name##_b}
#define MYFIFO_INIT(name, size, n) u8 name##_b[(size) * (n)] = {0}; my_fifo_t (name) = {(size), (n), 0, 0, name##_b}
#if (1) //DEBUG_USB_LOG_EN
#define MYFIFO_INIT_IRAM(name, size, n) /*__attribute__ ((aligned (4)))*/ \
__attribute__((section(".retention_data"))) u8 name##_b[size * n] __attribute__((aligned(4))) /*={0}*/; \
__attribute__((section(".retention_data"))) my_fifo_t name = {size, n, 0, 0, name##_b}
#if (1) // DEBUG_USB_LOG_EN
#define MYFIFO_INIT_IRAM(name, size, n) \
__attribute__((section(".retention_data"))) u8 name##_b[(size) * (n)]__attribute__((aligned(4))); \
__attribute__((section(".retention_data"))) my_fifo_t name = { size, n, 0, 0, name##_b }
#endif
/*LL ACL RX buffer len = maxRxOct + 21, then 16 Byte align*/
#define CAL_LL_ACL_RX_FIFO_SIZE(maxRxOct) (((maxRxOct + 21) + 15) / 16 * 16)
/*LL ACL TX buffer len = maxTxOct + 10, then 16 Byte align*/
#define CAL_LL_ACL_TX_FIFO_SIZE(maxTxOct) (((maxTxOct + 10) + 15) / 16 * 16)
/* LL ACL RX buffer len = maxRxOct + 21, then 16 Byte align */
#define CAL_LL_ACL_RX_FIFO_SIZE(maxRxOct) ((((maxRxOct) + 21) + 15) / 16 * 16)
#define ATT_ALLIGN4_DMA_BUFF(n) (((n + 10) + 3) / 4 * 4)
/* LL ACL TX buffer len = maxTxOct + 10, then 16 Byte align */
#define CAL_LL_ACL_TX_FIFO_SIZE(maxTxOct) ((((maxTxOct) + 10) + 15) / 16 * 16)
#define ATT_ALLIGN4_DMA_BUFF(n) ((((n) + 10) + 3) / 4 * 4)
#endif // B91_B91_BLE_SDK_COMMON_UTILITY_H
b91/b91_ble_sdk/drivers.h
-2
View File
@@ -15,8 +15,6 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef DRIVERS_H
#define DRIVERS_H
b91/b91_ble_sdk/drivers/B91/adc.c
+36 -36
View File
@@ -19,25 +19,25 @@
#include "audio.h"
#include "compiler.h"
_attribute_data_retention_sec_ unsigned short g_adc_vref = 1175; //default ADC ref voltage (unit:mV)
_attribute_data_retention_sec_ unsigned short g_adc_vref = 1175; // default ADC ref voltage (unit:mV)
volatile unsigned char g_adc_pre_scale;
volatile unsigned char g_adc_vbat_divider;
dma_chn_e adc_dma_chn;
dma_config_t adc_rx_dma_config = {
.dst_req_sel = 0,
.src_req_sel = DMA_REQ_AUDIO1_RX, //adc use the audio1 interface
.src_req_sel = DMA_REQ_AUDIO1_RX, // adc use the audio1 interface
.dst_addr_ctrl = DMA_ADDR_INCREMENT,
.src_addr_ctrl = DMA_ADDR_FIX,
.dstmode = DMA_NORMAL_MODE,
.srcmode = DMA_HANDSHAKE_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must word
.srcwidth = DMA_CTR_WORD_WIDTH, //must word
.src_burst_size = 0, //must 0
.dstwidth = DMA_CTR_WORD_WIDTH, // must word
.srcwidth = DMA_CTR_WORD_WIDTH, // must word
.src_burst_size = 0, // must 0
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must 0
.auto_en = 0, // must 0
};
/**
* @brief This function serves to config adc_dma_chn channel.
@@ -51,7 +51,7 @@ void adc_set_dma_config(dma_chn_e chn)
dma_clr_irq_mask(adc_dma_chn, TC_MASK | ERR_MASK | ABT_MASK);
dma_set_irq_mask(adc_dma_chn, TC_MASK);
audio_data_fifo1_path_sel(SAR_ADC_DATA_IN_FIFO, OUT_NO_USE); //connect DMA and ADC by audio input fifo1.
audio_data_fifo1_path_sel(SAR_ADC_DATA_IN_FIFO, OUT_NO_USE); // connect DMA and ADC by audio input fifo1.
}
/**
* @brief This function serves to start sample with adc DMA channel.
@@ -138,13 +138,13 @@ void adc_set_ref_voltage(adc_ref_vol_e v_ref)
{
analog_write_reg8(areg_adc_vref, v_ref);
if (v_ref == ADC_VREF_1P2V) {
//Vref buffer bias current trimming: 150%
//Comparator preamp bias current trimming: 100%
// Vref buffer bias current trimming: 150%
// Comparator preamp bias current trimming: 100%
analog_write_reg8(areg_ain_scale, (analog_read_reg8(areg_ain_scale) & (0xC0)) | 0x3d);
g_adc_vref = 1175;
} else if (v_ref == ADC_VREF_0P9V) {
//Vref buffer bias current trimming: 100%
//Comparator preamp bias current trimming: 100%
// Vref buffer bias current trimming: 100%
// Comparator preamp bias current trimming: 100%
analog_write_reg8(areg_ain_scale, (analog_read_reg8(areg_ain_scale) & (0xC0)) | 0x15);
g_adc_vref = 900; // v_ref = ADC_VREF_0P9V,
}
@@ -163,15 +163,15 @@ void adc_set_sample_rate(adc_sample_freq_e sample_freq)
* The length of Tsample should match the sampling frequency.
* changed by chaofan,confirmed by haitao.20201230.
**/
adc_set_tsample_cycle(ADC_SAMPLE_CYC_24); //24 adc clocks for sample cycle
adc_set_tsample_cycle(ADC_SAMPLE_CYC_24); // 24 adc clocks for sample cycle
break;
case ADC_SAMPLE_FREQ_48K:
adc_set_state_length(490, 10);
adc_set_tsample_cycle(ADC_SAMPLE_CYC_12); //12 adc clocks for sample cycle
adc_set_tsample_cycle(ADC_SAMPLE_CYC_12); // 12 adc clocks for sample cycle
break;
case ADC_SAMPLE_FREQ_96K:
adc_set_state_length(240, 10);
adc_set_tsample_cycle(ADC_SAMPLE_CYC_6); //6 adc clocks for sample cycle
adc_set_tsample_cycle(ADC_SAMPLE_CYC_6); // 6 adc clocks for sample cycle
break;
}
}
@@ -212,19 +212,19 @@ void adc_set_vbat_divider(adc_vbat_div_e vbat_div)
*/
void adc_init(adc_ref_vol_e v_ref, adc_pre_scale_e pre_scale, adc_sample_freq_e sample_freq)
{
adc_power_off(); //power off sar adc
adc_reset(); //reset whole digital adc module
adc_clk_en(); //enable signal of 24M clock to sar adc
adc_set_clk(5); //default adc_clk 4M = 24M/(1+div),
adc_set_ref_voltage(v_ref); //set channel Vref
adc_set_scale_factor(pre_scale); //set Analog input pre-scaling
adc_set_sample_rate(sample_freq); //set sample frequency.
adc_set_resolution(ADC_RES14); //default adc_resolution set as 14bit ,BIT(13) is sign bit
adc_power_off(); // power off sar adc
adc_reset(); // reset whole digital adc module
adc_clk_en(); // enable signal of 24M clock to sar adc
adc_set_clk(5); // default adc_clk 4M = 24M/(1+div),
adc_set_ref_voltage(v_ref); // set channel Vref
adc_set_scale_factor(pre_scale); // set Analog input pre-scaling
adc_set_sample_rate(sample_freq); // set sample frequency.
adc_set_resolution(ADC_RES14); // default adc_resolution set as 14bit ,BIT(13) is sign bit
/**
* Move the Tsample set to function adc_set_sample_rate(),because of the length of Tsample should match the sampling frequency.
* changed by chaofan,confirmed by haitao.20201230.
**/
adc_set_m_chn_en(); //enable adc channel.
adc_set_m_chn_en(); // enable adc channel.
}
/**
* @brief This function serves to ADC gpio sample init.
@@ -233,7 +233,7 @@ void adc_init(adc_ref_vol_e v_ref, adc_pre_scale_e pre_scale, adc_sample_freq_e
* @param[in] pre_scale - enum variable of ADC pre_scaling factor.
* @param[in] sample_freq - enum variable of ADC sample frequency.
* @return none
* @attention gpio voltage sample suggested initial setting are Vref = 1.2V, pre_scale = 1/4.
* @attention gpio voltage sample suggested initial setting are Vref = 1.2V, pre_scale = 1/4.
* changed by chaofan.20201230.
*/
void adc_gpio_sample_init(adc_input_pin_def_e pin, adc_ref_vol_e v_ref, adc_pre_scale_e pre_scale,
@@ -287,22 +287,22 @@ void adc_battery_voltage_sample_init(void)
*/
void adc_get_code_dma(unsigned short *sample_buffer, unsigned short sample_num)
{
/******start adc sample********/
/****** start adc sample ********/
adc_start_sample_dma((unsigned short *)sample_buffer, sample_num << 1);
/******wait for adc sample finish********/
while (!adc_get_sample_status_dma())
;
/******stop dma smaple********/
/****** wait for adc sample finish ********/
while (!adc_get_sample_status_dma()) {
}
/****** stop dma smaple ********/
adc_stop_sample_dma();
/******clear adc sample finished status********/
adc_clr_sample_status_dma(); //must
/******get adc sample data and sort these data ********/
/****** clear adc sample finished status ********/
adc_clr_sample_status_dma(); // must
/****** get adc sample data and sort these data ********/
for (int i = 0; i < sample_num; i++) {
if (sample_buffer[i] &
BIT(13)) { //14 bit resolution, BIT(13) is sign bit, 1 means negative voltage in differential_mode
BIT(13)) { // 14 bit resolution, BIT(13) is sign bit, 1 means negative voltage in differential_mode
sample_buffer[i] = 0;
} else {
sample_buffer[i] = (sample_buffer[i] & 0x1fff); //BIT(12..0) is valid adc code
sample_buffer[i] = (sample_buffer[i] & 0x1fff); // BIT(12..0) is valid adc code
}
}
}
@@ -315,7 +315,7 @@ void adc_get_code_dma(unsigned short *sample_buffer, unsigned short sample_num)
unsigned short adc_get_code(void)
{
unsigned short adc_code;
/******Lock ADC code in analog register ********/
/****** Lock ADC code in analog register ********/
analog_write_reg8(areg_adc_data_sample_control,
analog_read_reg8(areg_adc_data_sample_control) | FLD_NOT_SAMPLE_ADC_DATA);
adc_code = analog_read_reg16(areg_adc_misc_l);
@@ -352,6 +352,6 @@ unsigned short adc_calculate_voltage(unsigned short adc_code)
unsigned short adc_calculate_temperature(unsigned short adc_code)
{
//////////////// adc sample data convert to temperature(Celsius) ////////////////
//adc_temp_value = 564 - ((adc_code * 819)>>13)
// adc_temp_value = 564 - ((adc_code * 819)>>13)
return 564 - ((adc_code * 819) >> 13);
}
b91/b91_ble_sdk/drivers/B91/adc.h
+10 -7
View File
@@ -25,7 +25,8 @@
* ===============
* Header File: adc.h
*/
#pragma once
#ifndef B91_B91_BLE_SDK_DRIVERS_B91_ADC_H
#define B91_B91_BLE_SDK_DRIVERS_B91_ADC_H
#include "compiler.h"
#include "dma.h"
@@ -132,10 +133,10 @@ typedef enum {
} adc_chn_e;
typedef enum {
ADC_PRESCALE_1 = 0x00, //Only for internal testing and temperature sensor sampling
// ADC_PRESCALE_1F2 = 0x01,//Only for internal testing
ADC_PRESCALE_1 = 0x00, // Only for internal testing and temperature sensor sampling
// ADC_PRESCALE_1F2 = 0x01,// Only for internal testing
ADC_PRESCALE_1F4 = 0x02,
// ADC_PRESCALE_1F8 = 0x03,//Only for internal testing
// ADC_PRESCALE_1F8 = 0x03, // Only for internal testing
} adc_pre_scale_e;
enum {
ADC_MAX_STATE_NUM = 0x02,
@@ -232,8 +233,8 @@ static inline void adc_set_resolution(adc_res_e res)
*/
static inline void adc_set_tsample_cycle(adc_sample_cycle_e sample_cycle)
{
//ana_ee<7:4> is reserved, so no need care its value
analog_write_reg8(areg_adc_tsmaple_m, sample_cycle); //optimize, <7:4> not cared
// ana_ee<7:4> is reserved, so no need care its value
analog_write_reg8(areg_adc_tsmaple_m, sample_cycle); // optimize, <7:4> not cared
}
/**
* @brief This function open temperature sensor power.
@@ -334,7 +335,7 @@ void adc_temperature_sample_init(void);
* @param[in] pre_scale - enum variable of ADC pre_scaling factor.
* @param[in] sample_freq - enum variable of ADC sample frequency.
* @return none
* @attention gpio voltage sample suggested initial setting are Vref = 1.2V, pre_scale = 1/4.
* @attention gpio voltage sample suggested initial setting are Vref = 1.2V, pre_scale = 1/4.
* changed by chaofan.20201230.
*/
void adc_gpio_sample_init(adc_input_pin_def_e pin, adc_ref_vol_e v_ref, adc_pre_scale_e pre_scale,
@@ -398,3 +399,5 @@ unsigned short adc_calculate_voltage(unsigned short adc_code);
* Temp = 564 - ((adc_code * 819)>>13),when Vref = 1.2V, pre_scale = 1.
*/
unsigned short adc_calculate_temperature(unsigned short adc_code);
#endif // B91_B91_BLE_SDK_DRIVERS_B91_ADC_H
b91/b91_ble_sdk/drivers/B91/aes.c
+8 -9
View File
@@ -60,7 +60,7 @@ static inline void aes_wait_done(void);
void aes_set_key_data(unsigned char *key, unsigned char *data)
{
unsigned int temp;
reg_embase_addr = aes_base_addr; //set the embase addr
reg_embase_addr = aes_base_addr; // set the embase addr
for (unsigned char i = 0; i < 4; i++) {
temp = key[16 - (4 * i) - 4] << 24 | key[16 - (4 * i) - 3] << 16 | key[16 - (4 * i) - 2] << 8 |
key[16 - (4 * i) - 1];
@@ -96,11 +96,10 @@ void aes_get_result(unsigned char *result)
*/
int aes_encrypt(unsigned char *key, unsigned char *plaintext, unsigned char *result)
{
//set the key
// set the key
aes_set_key_data(key, plaintext);
aes_set_mode(AES_ENCRYPT_MODE); //cipher mode
aes_set_mode(AES_ENCRYPT_MODE); // cipher mode
aes_wait_done();
@@ -118,10 +117,10 @@ int aes_encrypt(unsigned char *key, unsigned char *plaintext, unsigned char *res
*/
int aes_decrypt(unsigned char *key, unsigned char *decrypttext, unsigned char *result)
{
//set the key
// set the key
aes_set_key_data(key, decrypttext);
aes_set_mode(AES_DECRYPT_MODE); //decipher mode
aes_set_mode(AES_DECRYPT_MODE); // decipher mode
aes_wait_done();
@@ -139,7 +138,7 @@ int aes_decrypt(unsigned char *key, unsigned char *decrypttext, unsigned char *r
*/
void aes_set_em_base_addr(unsigned int addr)
{
aes_base_addr = addr; //set the embase addr
aes_base_addr = addr; // set the embase addr
}
/**
@@ -148,6 +147,6 @@ void aes_set_em_base_addr(unsigned int addr)
*/
static inline void aes_wait_done(void)
{
while (FLD_AES_START == (reg_aes_mode & FLD_AES_START))
;
while (FLD_AES_START == (reg_aes_mode & FLD_AES_START)) {
}
}
b91/b91_ble_sdk/drivers/B91/analog.c
+20 -17
View File
@@ -51,7 +51,7 @@ dma_config_t analog_tx_dma_config = {
.auto_en = 0, /* < must 0 */
};
dma_config_t analog_rx_dma_config = {
.dst_req_sel = 0, //tx req
.dst_req_sel = 0, // tx req
.src_req_sel = DMA_REQ_ALGM_RX,
.dst_addr_ctrl = DMA_ADDR_INCREMENT,
.src_addr_ctrl = DMA_ADDR_FIX,
@@ -63,7 +63,7 @@ dma_config_t analog_rx_dma_config = {
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must 0
.auto_en = 0, // must 0
};
/**********************************************************************************************************************
* local variable *
@@ -76,7 +76,7 @@ dma_config_t analog_rx_dma_config = {
* @brief This function serves to judge whether analog write/read is busy .
* @return none.
*/
static inline void analog_wait();
static inline void analog_wait(void);
/**********************************************************************************************************************
* global function implementation *
*********************************************************************************************************************/
@@ -244,8 +244,9 @@ _attribute_ram_code_sec_noinline_ void analog_write_buff(unsigned char addr, uns
reg_ana_addr = addr;
if (len_t <= 4) {
while (len_t--)
while (len_t--) {
reg_ana_data(wr_idx++) = *(buff++);
}
reg_ana_ctrl = FLD_ANA_CYC | FLD_ANA_RW;
} else {
len_t = 4;
@@ -259,12 +260,12 @@ _attribute_ram_code_sec_noinline_ void analog_write_buff(unsigned char addr, uns
reg_ana_data(wr_idx++) = *(buff++);
if (wr_idx == 4) {
wr_idx = 0;
while ((reg_ana_irq_sta & FLD_ANA_TXBUFF_IRQ) == 0)
; //tx_buf_irq
while ((reg_ana_irq_sta & FLD_ANA_TXBUFF_IRQ) == 0) {
} // tx_buf_irq
}
}
}
analog_wait(); //busy
analog_wait(); // busy
reg_ana_ctrl = 0x00;
core_restore_interrupt(r);
}
@@ -285,23 +286,25 @@ _attribute_ram_code_sec_noinline_ void analog_read_buff(unsigned char addr, unsi
reg_ana_addr = addr;
reg_ana_ctrl = FLD_ANA_CYC;
if (len_t > 4) {
while ((reg_ana_irq_sta & FLD_ANA_RXBUFF_IRQ) == 0)
; //rx_buf_irq
while ((reg_ana_irq_sta & FLD_ANA_RXBUFF_IRQ) == 0) {
} // rx_buf_irq
while (len_t--) {
(*buff++) = reg_ana_data(rd_idx++);
if (rd_idx == 4) {
rd_idx = 0;
if (len_t <= 4)
if (len_t <= 4) {
break;
else
while ((reg_ana_irq_sta & FLD_ANA_RXBUFF_IRQ) == 0)
; //rx_buf_irq
} else {
while ((reg_ana_irq_sta & FLD_ANA_RXBUFF_IRQ) == 0) {
} // rx_buf_irq
}
}
}
}
analog_wait();
while (len_t--)
while (len_t--) {
(*buff++) = reg_ana_data(rd_idx++);
}
reg_ana_ctrl = 0x00;
core_restore_interrupt(r);
@@ -395,8 +398,8 @@ void analog_write_addr_data_dma(dma_chn_e chn, void *pdat, int len)
reg_ana_ctrl = FLD_ANA_RW;
reg_ana_dma_ctl = FLD_ANA_CYC1 | FLD_ANA_DMA_EN;
delay_us(1);
while (!(reg_ana_sta & BIT(3)))
;
while (!(reg_ana_sta & BIT(3))) {
}
reg_ana_ctrl = 0x00;
reg_ana_dma_ctl = 0;
core_restore_interrupt(r);
@@ -409,7 +412,7 @@ void analog_write_addr_data_dma(dma_chn_e chn, void *pdat, int len)
* @brief This function serves to judge whether analog write/read is busy .
* @return none.
*/
static inline void analog_wait()
static inline void analog_wait(void)
{
while (reg_ana_ctrl & FLD_ANA_BUSY) {
}
b91/b91_ble_sdk/drivers/B91/analog.h
+4 -1
View File
@@ -26,7 +26,8 @@
* ===============
* Header File: analog.h
*/
#pragma once
#ifndef B91_B91_BLE_SDK_DRIVERS_B91_ANALOG_H
#define B91_B91_BLE_SDK_DRIVERS_B91_ANALOG_H
#include "compiler.h"
#include "dma.h"
@@ -175,3 +176,5 @@ void analog_read_buff_dma(dma_chn_e chn, unsigned char addr, unsigned char *pdat
* @return none.
*/
void analog_write_addr_data_dma(dma_chn_e chn, void *pdat, int len);
#endif // B91_B91_BLE_SDK_DRIVERS_B91_ANALOG_H
b91/b91_ble_sdk/drivers/B91/audio.c
+135 -181
View File
@@ -32,45 +32,45 @@ aduio_i2s_codec_config_t audio_i2s_codec_config = {
.i2s_data_select = I2S_BIT_16_DATA,
.codec_data_select = CODEC_BIT_16_DATA,
.i2s_codec_m_s_mode = I2S_M_CODEC_S,
.i2s_data_invert_select = I2S_DATA_INVERT_DIS, //L channel default
.i2s_data_invert_select = I2S_DATA_INVERT_DIS, // L channel default
.in_digital_gain = CODEC_IN_D_GAIN_0_DB,
.in_analog_gain = CODEC_IN_A_GAIN_0_DB,
.out_digital_gain = CODEC_OUT_D_GAIN_0_DB,
.out_analog_gain = CODEC_OUT_A_GAIN_0_DB,
.mic_input_mode_select = 1, //0 single-ended input, 1 differential input
.mic_input_mode_select = 1, // 0 single-ended input, 1 differential input
.adc_wnf_mode_select = CODEC_ADC_WNF_INACTIVE,
};
dma_config_t audio_dma_rx_config = {
.dst_req_sel = 0,
.src_req_sel = DMA_REQ_AUDIO0_RX, //rx req
.src_req_sel = DMA_REQ_AUDIO0_RX, // rx req
.dst_addr_ctrl = DMA_ADDR_INCREMENT,
.src_addr_ctrl = DMA_ADDR_FIX,
.dstmode = DMA_NORMAL_MODE,
.srcmode = DMA_HANDSHAKE_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must word
.srcwidth = DMA_CTR_WORD_WIDTH, //must word
.src_burst_size = 0, //must 0
.dstwidth = DMA_CTR_WORD_WIDTH, // must word
.srcwidth = DMA_CTR_WORD_WIDTH, // must word
.src_burst_size = 0, // must 0
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must 0
.auto_en = 0, // must 0
};
dma_config_t audio_dma_tx_config = {
.dst_req_sel = DMA_REQ_AUDIO0_TX, //tx req
.dst_req_sel = DMA_REQ_AUDIO0_TX, // tx req
.src_req_sel = 0,
.dst_addr_ctrl = DMA_ADDR_FIX,
.src_addr_ctrl = DMA_ADDR_INCREMENT, //increment
.dstmode = DMA_HANDSHAKE_MODE, //handshake
.src_addr_ctrl = DMA_ADDR_INCREMENT, // increment
.dstmode = DMA_HANDSHAKE_MODE, // handshake
.srcmode = DMA_NORMAL_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must word
.srcwidth = DMA_CTR_WORD_WIDTH, //must word
.src_burst_size = 0, //must 0
.dstwidth = DMA_CTR_WORD_WIDTH, // must word
.srcwidth = DMA_CTR_WORD_WIDTH, // must word
.src_burst_size = 0, // must 0
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must 0
.auto_en = 0, // must 0
};
/**
@@ -199,15 +199,14 @@ void aduio_set_chn_wl(audio_channel_wl_mode_e chn_wl)
*/
void audio_i2s_set_pin_mux(i2s_pin_e pin)
{
unsigned char val = 0;
unsigned char start_bit = (BIT_LOW_BIT(pin & 0xff) % 4) << 1;
unsigned char mask = (unsigned char)~BIT_RNG(start_bit, start_bit + 1);
if (pin == I2S_BCK_PC3) {
val = 0; //function 0
val = 0; // function 0
} else if ((pin == I2S_ADC_LR_PC4) || (pin == I2S_ADC_DAT_PC5) || (pin == I2S_DAC_LR_PC6) ||
(pin == I2S_DAC_DAT_PC7)) {
val = 1 << (start_bit); //function 1
val = 1 << (start_bit); // function 1
}
reg_gpio_func_mux(pin) = (reg_gpio_func_mux(pin) & mask) | val;
gpio_function_dis(pin);
@@ -235,26 +234,16 @@ void audio_i2s_set_pin(void)
*/
void audio_set_codec_supply(codec_volt_supply_e volt)
{
if (0xff == g_chip_version) //A0 1.8v default ( BIT(7) - 1: 2.8v 0: 1.8v )
{
if (0xff == g_chip_version) { // A0 1.8v default ( BIT(7) - 1: 2.8v 0: 1.8v )
if (CODEC_2P8V == volt) {
analog_write_reg8(0x02, analog_read_reg8(0x02) | BIT(7));
}
else if (CODEC_1P8V == volt) {
} else if (CODEC_1P8V == volt) {
analog_write_reg8(0x02, analog_read_reg8(0x02) & (~BIT(7)));
}
}
else //A1 2.8v default ( BIT(7) - 1: 1.8v 0: 2.8v )
{
} else { // A1 2.8v default ( BIT(7) - 1: 1.8v 0: 2.8v )
if (CODEC_1P8V == volt) {
analog_write_reg8(0x02, analog_read_reg8(0x02) | BIT(7));
}
else if (CODEC_2P8V == volt) {
} else if (CODEC_2P8V == volt) {
analog_write_reg8(0x02, analog_read_reg8(0x02) & (~BIT(7)));
}
}
@@ -276,9 +265,7 @@ void audio_set_dmic_pin(dmic_pin_group_e pin_gp)
reg_gpio_pad_mul_sel = BIT(0);
reg_gpio_pc_fuc_l = (reg_gpio_pc_fuc_l & (~BIT_RNG(2, 7))) | ((2 << 2) | (2 << 4) | (2 << 6));
gpio_function_dis(GPIO_PC1 | GPIO_PC2 | GPIO_PC3);
} else if (pin_gp == DMIC_GROUPD_D4_DAT_D5_D6_CLK) //can not use in A0
{
} else if (pin_gp == DMIC_GROUPD_D4_DAT_D5_D6_CLK) { // can not use in A0
reg_gpio_pd_fuc_h = (reg_gpio_pd_fuc_h & (~BIT_RNG(0, 5))) | ((1 << 0) | (1 << 2) | (1 << 4));
gpio_function_dis(GPIO_PD4 | GPIO_PD5 | GPIO_PD6);
} else if (pin_gp == DMIC_B2_DAT_B3_CLK) {
@@ -289,8 +276,7 @@ void audio_set_dmic_pin(dmic_pin_group_e pin_gp)
reg_gpio_pad_mul_sel = BIT(0);
reg_gpio_pc_fuc_l = (reg_gpio_pc_fuc_l & (~BIT_RNG(2, 5))) | ((2 << 2) | (2 << 4));
gpio_function_dis(GPIO_PC1 | GPIO_PC2);
} else if (pin_gp == DMIC_D4_DAT_D5_CLK) //can not use in A0
{
} else if (pin_gp == DMIC_D4_DAT_D5_CLK) { // can not use in A0
reg_gpio_pd_fuc_h = (reg_gpio_pd_fuc_h & (~BIT_RNG(0, 3))) | ((1 << 0) | (1 << 2));
gpio_function_dis(GPIO_PD4 | GPIO_PD5);
}
@@ -359,14 +345,14 @@ void audio_rx_dma_config(dma_chn_e chn, unsigned short *dst_addr, unsigned int d
* @param[in] data_len -the length of dma size by byte.
* @return none
*/
void audio_rx_dma_add_list_element(dma_chain_config_t *config_addr, dma_chain_config_t *llpointer,
void audio_rx_dma_add_list_element(dma_chain_config_t *rx_config, dma_chain_config_t *llpointer,
unsigned short *dst_addr, unsigned int data_len)
{
config_addr->dma_chain_ctl = reg_dma_ctrl(audio_rx_dma_chn) | BIT(0);
config_addr->dma_chain_src_addr = REG_AUDIO_AHB_BASE;
config_addr->dma_chain_dst_addr = (unsigned int)convert_ram_addr_cpu2bus(dst_addr);
config_addr->dma_chain_data_len = dma_cal_size(data_len, 4);
config_addr->dma_chain_llp_ptr = (unsigned int)convert_ram_addr_cpu2bus(llpointer);
rx_config->dma_chain_ctl = reg_dma_ctrl(audio_rx_dma_chn) | BIT(0);
rx_config->dma_chain_src_addr = REG_AUDIO_AHB_BASE;
rx_config->dma_chain_dst_addr = (unsigned int)convert_ram_addr_cpu2bus(dst_addr);
rx_config->dma_chain_data_len = dma_cal_size(data_len, 4);
rx_config->dma_chain_llp_ptr = (unsigned int)convert_ram_addr_cpu2bus(llpointer);
}
/**
@@ -416,15 +402,15 @@ void audio_tx_dma_add_list_element(dma_chain_config_t *config_addr, dma_chain_co
void audio_init(audio_flow_mode_e flow_mode, audio_sample_rate_e rate, audio_channel_wl_mode_e channel_wl)
{
aduio_set_chn_wl(channel_wl);
audio_set_codec_clk(1, 16); //from ppl 192/16=12M
audio_set_codec_clk(1, 16); // from ppl 192/16=12M
audio_mux_config(CODEC_I2S, audio_i2s_codec_config.audio_in_mode, audio_i2s_codec_config.audio_in_mode,
audio_i2s_codec_config.audio_out_mode);
audio_i2s_config(I2S_I2S_MODE, audio_i2s_codec_config.i2s_data_select, audio_i2s_codec_config.i2s_codec_m_s_mode,
audio_i2s_codec_config.i2s_data_invert_select);
audio_set_i2s_clock(rate, AUDIO_RATE_EQUAL, 0);
audio_clk_en(1, 1);
reg_audio_codec_vic_ctr = FLD_AUDIO_CODEC_SLEEP_ANALOG; //active analog sleep mode
while (!(reg_audio_codec_stat_ctr & FLD_AUDIO_CODEC_PON_ACK)) { //wait codec can be configed
reg_audio_codec_vic_ctr = FLD_AUDIO_CODEC_SLEEP_ANALOG; // active analog sleep mode
while (!(reg_audio_codec_stat_ctr & FLD_AUDIO_CODEC_PON_ACK)) { // wait codec can be configed
}
if (flow_mode < BUF_TO_LINE_OUT) {
audio_codec_adc_config(audio_i2s_codec_config.i2s_codec_m_s_mode, (flow_mode % 3), rate,
@@ -436,7 +422,7 @@ void audio_init(audio_flow_mode_e flow_mode, audio_sample_rate_e rate, audio_cha
audio_i2s_codec_config.codec_data_select, MCU_WREG);
}
while (!(reg_audio_codec_stat_ctr == (FLD_AUDIO_CODEC_ADC12_LOCKED | FLD_AUDIO_CODEC_DAC_LOCKED |
FLD_AUDIO_CODEC_PON_ACK))) { //wait codec adc/dac locked
FLD_AUDIO_CODEC_PON_ACK))) { // wait codec adc/dac locked
}
audio_data_fifo0_path_sel(I2S_DATA_IN_FIFO, I2S_OUT);
@@ -450,20 +436,20 @@ void audio_init(audio_flow_mode_e flow_mode, audio_sample_rate_e rate, audio_cha
unsigned char audio_i2c_codec_read(unsigned char addr)
{
reg_i2c_data_buf(0) = addr << 1;
reg_i2c_len = 0x01; //rx_len
reg_i2c_len = 0x01; // rx_len
reg_i2c_sct1 = FLD_I2C_LS_ID | FLD_I2C_LS_ADDR | FLD_I2C_LS_START;
while (i2c_master_busy()) { //wait busy=0
while (i2c_master_busy()) { // wait busy=0
}
while (reg_i2c_mst & FLD_I2C_ACK_IN) { //wait ack=0
while (reg_i2c_mst & FLD_I2C_ACK_IN) { // wait ack=0
}
reg_i2c_sct1 = FLD_I2C_LS_ID | FLD_I2C_LS_DATAR | FLD_I2C_LS_START | FLD_I2C_LS_ID_R | FLD_I2C_LS_ACK;
while (i2c_master_busy()) { //wait busy=0
while (i2c_master_busy()) { // wait busy=0
}
unsigned char rdat8 = reg_i2c_data_buf(0);
reg_i2c_sct1 = FLD_I2C_LS_STOP | FLD_I2C_LS_ID_R;
while (i2c_master_busy()) { //wait busy=0
while (i2c_master_busy()) { // wait busy=0
}
return rdat8;
}
@@ -475,14 +461,13 @@ unsigned char audio_i2c_codec_read(unsigned char addr)
*/
void audio_i2c_codec_write(unsigned char addr, unsigned char wdat)
{
reg_i2c_data_buf(0) = addr << 1;
reg_i2c_data_buf(1) = wdat;
reg_i2c_len = 2; //tx_len
reg_i2c_len = 2; // tx_len
reg_i2c_sct1 = FLD_I2C_LS_ID | FLD_I2C_LS_DATAW | FLD_I2C_LS_START | FLD_I2C_LS_STOP;
while (i2c_master_busy()) { //wait busy=0
while (i2c_master_busy()) { // wait busy=0
}
while (reg_i2c_mst & FLD_I2C_ACK_IN) { //wait ack=0
while (reg_i2c_mst & FLD_I2C_ACK_IN) { // wait ack=0
}
}
@@ -494,11 +479,10 @@ void audio_i2c_codec_write(unsigned char addr, unsigned char wdat)
void audio_i2c_init(codec_type_e codec_type, i2c_sda_pin_e sda_pin, i2c_scl_pin_e scl_pin)
{
i2c_master_init();
i2c_set_master_clk((unsigned char)(sys_clk.pclk * 1000 * 1000 / (4 * 20000))); //set i2c frequency 400K.
//reg_i2c_sp=0x1e;//200k sys_clk.pclk=24M
i2c_set_master_clk((unsigned char)(sys_clk.pclk * 1000 * 1000 / (4 * 20000))); // set i2c frequency 400K.
if (codec_type == INNER_CODEC) {
reg_audio_i2c_mode = 0x05; //codec config by i2c
reg_i2c_id = (0x34 << 1); //set i2c id
reg_audio_i2c_mode = 0x05; // codec config by i2c
reg_i2c_id = (0x34 << 1); // set i2c id
reg_audio_i2c_addr = 0x34;
} else if (codec_type == EXT_CODEC) {
reg_i2c_id = 0x34;
@@ -516,7 +500,7 @@ void audio_i2c_init(codec_type_e codec_type, i2c_sda_pin_e sda_pin, i2c_scl_pin_
void audio_init_i2c(audio_flow_mode_e flow_mode, audio_sample_rate_e rate, audio_channel_wl_mode_e channel_wl)
{
aduio_set_chn_wl(channel_wl);
audio_set_codec_clk(1, 16); ////from ppl 192/16=12M
audio_set_codec_clk(1, 16); // from ppl 192/16=12M
audio_mux_config(CODEC_I2S, audio_i2s_codec_config.audio_in_mode, audio_i2s_codec_config.audio_in_mode,
audio_i2s_codec_config.audio_out_mode);
audio_i2s_config(I2S_I2S_MODE, audio_i2s_codec_config.i2s_data_select, audio_i2s_codec_config.i2s_codec_m_s_mode,
@@ -524,9 +508,9 @@ void audio_init_i2c(audio_flow_mode_e flow_mode, audio_sample_rate_e rate, audio
audio_set_i2s_clock(rate, AUDIO_RATE_EQUAL, 0);
audio_clk_en(1, 1);
audio_i2c_init(INNER_CODEC, 0, 0);
audio_i2c_codec_write(addr_audio_codec_vic_ctr, FLD_AUDIO_CODEC_SLEEP_ANALOG); //active analog sleep mode
audio_i2c_codec_write(addr_audio_codec_vic_ctr, FLD_AUDIO_CODEC_SLEEP_ANALOG); // active analog sleep mode
while (
!(audio_i2c_codec_read(addr_audio_codec_stat_ctr) & FLD_AUDIO_CODEC_PON_ACK)) { //wait codec can be configed
!(audio_i2c_codec_read(addr_audio_codec_stat_ctr) & FLD_AUDIO_CODEC_PON_ACK)) { // wait codec can be configed
}
if (flow_mode < BUF_TO_LINE_OUT) {
audio_codec_adc_config(audio_i2s_codec_config.i2s_codec_m_s_mode, (flow_mode % 3), rate,
@@ -538,7 +522,7 @@ void audio_init_i2c(audio_flow_mode_e flow_mode, audio_sample_rate_e rate, audio
}
while (!(audio_i2c_codec_read(addr_audio_codec_stat_ctr) ==
(FLD_AUDIO_CODEC_ADC12_LOCKED | FLD_AUDIO_CODEC_DAC_LOCKED |
FLD_AUDIO_CODEC_PON_ACK))) { //wait codec adc/dac locked
FLD_AUDIO_CODEC_PON_ACK))) { // wait codec adc/dac locked
}
audio_data_fifo0_path_sel(I2S_DATA_IN_FIFO, I2S_OUT);
}
@@ -554,59 +538,56 @@ void audio_init_i2c(audio_flow_mode_e flow_mode, audio_sample_rate_e rate, audio
void audio_codec_dac_config(i2s_codec_m_s_mode_e mode, audio_sample_rate_e rate, codec_data_select_e data_select,
codec_wreg_mode_e wreg_mode)
{
if (wreg_mode == MCU_WREG) {
BM_SET(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SOFT_MUTE); //dac mute
BM_SET(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SOFT_MUTE); // dac mute
if ((audio_i2s_codec_config.audio_out_mode == BIT_16_MONO_FIFO0) ||
((audio_i2s_codec_config.audio_out_mode == BIT_20_OR_24_MONO_FIFO0))) {
BM_CLR(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SB); //active DAC power
BM_SET(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_LEFT_ONLY); //active left channel only
BM_CLR(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SB); // active DAC power
BM_SET(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_LEFT_ONLY); // active left channel only
} else {
BM_CLR(reg_audio_codec_dac_ctr,
FLD_AUDIO_CODEC_DAC_SB |
FLD_AUDIO_CODEC_DAC_LEFT_ONLY); //active DAC power,active left and right channel
FLD_AUDIO_CODEC_DAC_LEFT_ONLY); // active DAC power,active left and right channel
}
BM_CLR(reg_audio_codec_vic_ctr,
FLD_AUDIO_CODEC_SB | FLD_AUDIO_CODEC_SB_ANALOG |
FLD_AUDIO_CODEC_SLEEP_ANALOG); //disable sleep mode ,disable sb_analog,disable global standby
FLD_AUDIO_CODEC_SLEEP_ANALOG); // disable sleep mode ,disable sb_analog,disable global standby
/* data word length ,interface master/slave selection, audio interface protocol selection ,active dac audio interface*/
/* data word length ,interface master/slave selection, audio interface protocol selection ,active dac audio interface */
reg_audio_codec_dac_itf_ctr =
MASK_VAL(FLD_AUDIO_CODEC_FORMAT, CODEC_I2S_MODE, FLD_AUDIO_CODEC_DAC_ITF_SB, CODEC_ITF_AC,
FLD_AUDIO_CODEC_SLAVE, mode, FLD_AUDIO_CODEC_WL, data_select);
/*disable DAC digital gain coupling, Left channel DAC digital gain*/
/* disable DAC digital gain coupling, Left channel DAC digital gain */
reg_audio_codec_dacl_gain =
MASK_VAL(FLD_AUDIO_CODEC_DAC_LRGOD, 0, FLD_AUDIO_CODEC_DAC_GODL, audio_i2s_codec_config.out_digital_gain);
reg_audio_codec_dacr_gain = MASK_VAL(
FLD_AUDIO_CODEC_DAC_GODR, audio_i2s_codec_config.out_digital_gain); /*Right channel DAC digital gain*/
FLD_AUDIO_CODEC_DAC_GODR, audio_i2s_codec_config.out_digital_gain); /* Right channel DAC digital gain */
/*disable Headphone gain coupling, set Left channel HP amplifier gain*/
/* disable Headphone gain coupling, set Left channel HP amplifier gain */
reg_audio_codec_hpl_gain =
MASK_VAL(FLD_AUDIO_CODEC_HPL_LRGO, 0, FLD_AUDIO_CODEC_HPL_GOL, audio_i2s_codec_config.out_analog_gain);
reg_audio_codec_hpr_gain =
MASK_VAL(FLD_AUDIO_CODEC_HPR_GOR,
audio_i2s_codec_config.out_analog_gain); /* Right channel HP amplifier gain programming*/
audio_i2s_codec_config.out_analog_gain); /* Right channel HP amplifier gain programming */
reg_audio_codec_dac_freq_ctr = (FLD_AUDIO_CODEC_DAC_FREQ & (rate == AUDIO_ADC_16K_DAC_48K ? AUDIO_48K : rate));
BM_CLR(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SOFT_MUTE); /*dac mute*/
}
else if (wreg_mode == I2C_WREG) {
/*active DAC power,active left and right channel,dac mute*/
BM_CLR(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SOFT_MUTE); /* dac mute */
} else if (wreg_mode == I2C_WREG) {
/* active DAC power,active left and right channel,dac mute */
audio_i2c_codec_write(
addr_audio_codec_dac_ctr,
MASK_VAL(FLD_AUDIO_CODEC_DAC_SB, 0, FLD_AUDIO_CODEC_DAC_LEFT_ONLY, 0, FLD_AUDIO_CODEC_DAC_SOFT_MUTE, 1));
/*disable sleep mode ,disable sb_analog,disable global standby*/
/* disable sleep mode ,disable sb_analog,disable global standby */
audio_i2c_codec_write(addr_audio_codec_vic_ctr, MASK_VAL(FLD_AUDIO_CODEC_SB, 0, FLD_AUDIO_CODEC_SB_ANALOG, 0,
FLD_AUDIO_CODEC_SLEEP_ANALOG, 0));
/*data word length ,interface master/slave selection, audio interface protocol selection ,active dac audio interface */
/* data word length ,interface master/slave selection, audio interface protocol selection ,active dac audio interface */
audio_i2c_codec_write(addr_audio_codec_dac_itf_ctr,
MASK_VAL(FLD_AUDIO_CODEC_FORMAT, CODEC_I2S_MODE, FLD_AUDIO_CODEC_DAC_ITF_SB,
CODEC_ITF_AC, FLD_AUDIO_CODEC_SLAVE, mode, FLD_AUDIO_CODEC_WL, data_select));
@@ -627,11 +608,11 @@ void audio_codec_dac_config(i2s_codec_m_s_mode_e mode, audio_sample_rate_e rate,
audio_i2c_codec_write(
addr_audio_codec_hpr_gain,
MASK_VAL(FLD_AUDIO_CODEC_HPR_GOR,
audio_i2s_codec_config.out_analog_gain)); /* Right channel HP amplifier gain programming*/
audio_i2s_codec_config.out_analog_gain)); /* Right channel HP amplifier gain programming */
audio_i2c_codec_write(addr_audio_codec_dac_freq_ctr, (FLD_AUDIO_CODEC_DAC_FREQ & rate));
/*dac mute*/
/* dac mute */
audio_i2c_codec_write(
addr_audio_codec_dac_ctr,
MASK_VAL(FLD_AUDIO_CODEC_DAC_SB, 0, FLD_AUDIO_CODEC_DAC_LEFT_ONLY, 0, FLD_AUDIO_CODEC_DAC_SOFT_MUTE, 0));
@@ -650,33 +631,32 @@ void audio_codec_dac_config(i2s_codec_m_s_mode_e mode, audio_sample_rate_e rate,
void audio_codec_adc_config(i2s_codec_m_s_mode_e mode, audio_input_mode_e in_mode, audio_sample_rate_e rate,
codec_data_select_e data_select, codec_wreg_mode_e wreg_mode)
{
if (wreg_mode == MCU_WREG) {
BM_SET(reg_audio_codec_adc12_ctr, FLD_AUDIO_CODEC_ADC12_SOFT_MUTE); /*adc mute*/
BM_SET(reg_audio_codec_adc12_ctr, FLD_AUDIO_CODEC_ADC12_SOFT_MUTE); /* adc mute */
if ((audio_i2s_codec_config.audio_in_mode == BIT_16_MONO) ||
((audio_i2s_codec_config.audio_in_mode == BIT_20_OR_24_MONO))) {
BM_CLR(reg_audio_codec_adc12_ctr, FLD_AUDIO_CODEC_ADC1_SB); /*active anc0 channel,mono .*/
BM_CLR(reg_audio_codec_adc12_ctr, FLD_AUDIO_CODEC_ADC1_SB); /* active anc0 channel,mono . */
} else {
BM_CLR(reg_audio_codec_adc12_ctr,
FLD_AUDIO_CODEC_ADC1_SB | FLD_AUDIO_CODEC_ADC2_SB); /*active adc0 and adc1 channel*/
FLD_AUDIO_CODEC_ADC1_SB | FLD_AUDIO_CODEC_ADC2_SB); /* active adc0 and adc1 channel */
}
BM_CLR(reg_audio_codec_vic_ctr,
FLD_AUDIO_CODEC_SB | FLD_AUDIO_CODEC_SB_ANALOG |
FLD_AUDIO_CODEC_SLEEP_ANALOG); /*disable sleep mode ,disable sb_analog,disable global standby*/
FLD_AUDIO_CODEC_SLEEP_ANALOG); /* disable sleep mode ,disable sb_analog,disable global standby */
if (in_mode == AMIC_INPUT) {
/*Microphone 1 input selection ,Microphone biasing active,Single-ended input,MICBIAS1 output=2.08V,*/
/* Microphone 1 input selection ,Microphone biasing active,Single-ended input,MICBIAS1 output=2.08V, */
reg_audio_codec_mic1_ctr =
MASK_VAL(FLD_AUDIO_CODEC_MIC1_SEL, 0, FLD_AUDIO_CODEC_MICBIAS1_SB, 0, FLD_AUDIO_CODEC_MIC_DIFF1,
audio_i2s_codec_config.mic_input_mode_select, FLD_AUDIO_CODEC_MICBIAS1_V, 0);
/*Microphone 2 input selection,Single-ended input*/
/* Microphone 2 input selection,Single-ended input */
reg_audio_codec_mic2_ctr = MASK_VAL(FLD_AUDIO_CODEC_MIC2_SEL, 0, FLD_AUDIO_CODEC_MIC_DIFF2,
audio_i2s_codec_config.mic_input_mode_select);
/*set wind noise filter */
/* set wind noise filter */
reg_audio_codec_adc_wnf_ctr = audio_i2s_codec_config.adc_wnf_mode_select;
/*analog 0/4/8/12/16/20 dB boost gain*/
/* analog 0/4/8/12/16/20 dB boost gain */
reg_audio_codec_mic_l_R_gain =
MASK_VAL(FLD_AUDIO_CODEC_AMIC_L_GAIN, audio_i2s_codec_config.in_analog_gain,
FLD_AUDIO_CODEC_AMIC_R_GAIN, audio_i2s_codec_config.in_analog_gain);
@@ -684,77 +664,69 @@ void audio_codec_adc_config(i2s_codec_m_s_mode_e mode, audio_input_mode_e in_mod
reg_audio_dmic_12 =
MASK_VAL(FLD_AUDIO_CODEC_ADC_DMIC_SEL2, 1, FLD_AUDIO_CODEC_ADC_DMIC_SEL1, 1, FLD_AUDIO_CODEC_DMIC2_SB,
CODEC_ITF_AC, FLD_AUDIO_CODEC_DMIC1_SB, CODEC_ITF_AC);
}
else if (in_mode == LINE_INPUT) {
} else if (in_mode == LINE_INPUT) {
reg_audio_codec_mic1_ctr =
MASK_VAL(FLD_AUDIO_CODEC_MIC_DIFF1, audio_i2s_codec_config.mic_input_mode_select);
reg_audio_codec_mic2_ctr =
MASK_VAL(FLD_AUDIO_CODEC_MIC_DIFF2, audio_i2s_codec_config.mic_input_mode_select);
/*analog 0/4/8/12/16/20 dB boost gain*/
/* analog 0/4/8/12/16/20 dB boost gain */
reg_audio_codec_mic_l_R_gain =
MASK_VAL(FLD_AUDIO_CODEC_AMIC_L_GAIN, audio_i2s_codec_config.in_analog_gain,
FLD_AUDIO_CODEC_AMIC_R_GAIN, audio_i2s_codec_config.in_analog_gain);
}
/*0db~43db 1db step ,digital programmable gain*/
/* 0db~43db 1db step ,digital programmable gain */
reg_audio_adc1_gain =
MASK_VAL(FLD_AUDIO_CODEC_ADC_LRGID, 1, FLD_AUDIO_CODEC_ADC_GID1, audio_i2s_codec_config.in_digital_gain);
/*data word length ,interface master/slave selection, audio interface protocol selection */
/* data word length ,interface master/slave selection, audio interface protocol selection */
reg_audio_codec_adc_itf_ctr = MASK_VAL(FLD_AUDIO_CODEC_FORMAT, CODEC_I2S_MODE, FLD_AUDIO_CODEC_SLAVE, mode,
FLD_AUDIO_CODEC_WL, data_select);
/*audio adc interface active*/
/* audio adc interface active */
BM_CLR(reg_audio_codec_adc2_ctr, FLD_AUDIO_CODEC_ADC12_SB);
/* adc high pass filter active, set adc sample rate */
reg_audio_codec_adc_freq_ctr = MASK_VAL(FLD_AUDIO_CODEC_ADC12_HPF_EN, 1, FLD_AUDIO_CODEC_ADC_FREQ,
rate == AUDIO_ADC_16K_DAC_48K ? AUDIO_16K : rate);
BM_CLR(reg_audio_codec_adc12_ctr, FLD_AUDIO_CODEC_ADC12_SOFT_MUTE); /*adc unmute*/
}
else if (wreg_mode == I2C_WREG) {
/*active adc0 and adc1 channel, if mono only active adc1,adc mute*/
BM_CLR(reg_audio_codec_adc12_ctr, FLD_AUDIO_CODEC_ADC12_SOFT_MUTE); /* adc unmute */
} else if (wreg_mode == I2C_WREG) {
/* active adc0 and adc1 channel, if mono only active adc1,adc mute */
audio_i2c_codec_write(addr_audio_codec_adc12_ctr, MASK_VAL(FLD_AUDIO_CODEC_ADC1_SB, 0, FLD_AUDIO_CODEC_ADC2_SB,
0, FLD_AUDIO_CODEC_ADC12_SOFT_MUTE, 1));
/*disable sleep mode ,disable sb_analog,disable global standby*/
/* disable sleep mode ,disable sb_analog,disable global standby */
audio_i2c_codec_write(addr_audio_codec_vic_ctr, MASK_VAL(FLD_AUDIO_CODEC_SB, 0, FLD_AUDIO_CODEC_SB_ANALOG, 0,
FLD_AUDIO_CODEC_SLEEP_ANALOG, 0));
if (in_mode == AMIC_INPUT) {
/*Microphone 1 input selection ,Microphone biasing active,Single-ended input,MICBIAS1 output=2.08V,*/
/* Microphone 1 input selection ,Microphone biasing active,Single-ended input,MICBIAS1 output=2.08V, */
audio_i2c_codec_write(addr_audio_codec_mic1_ctr,
MASK_VAL(FLD_AUDIO_CODEC_MIC1_SEL, 0, FLD_AUDIO_CODEC_MICBIAS1_SB, 0,
FLD_AUDIO_CODEC_MIC_DIFF1, 0, FLD_AUDIO_CODEC_MICBIAS1_V, 0));
/*Microphone 2 input selection,Single-ended input*/
/* Microphone 2 input selection,Single-ended input */
audio_i2c_codec_write(addr_audio_codec_mic2_ctr,
MASK_VAL(FLD_AUDIO_CODEC_MIC2_SEL, 0, FLD_AUDIO_CODEC_MIC_DIFF2, 0));
/*analog 0/4/8/12/16/20 dB boost gain*/
/* analog 0/4/8/12/16/20 dB boost gain */
audio_i2c_codec_write(addr_audio_codec_mic_l_R_gain,
MASK_VAL(FLD_AUDIO_CODEC_AMIC_L_GAIN, audio_i2s_codec_config.in_analog_gain,
FLD_AUDIO_CODEC_AMIC_R_GAIN, audio_i2s_codec_config.in_analog_gain));
} else if (in_mode == DMIC_INPUT) {
audio_i2c_codec_write(addr_audio_dmic_12,
MASK_VAL(FLD_AUDIO_CODEC_ADC_DMIC_SEL2, 1, FLD_AUDIO_CODEC_ADC_DMIC_SEL1, 1,
FLD_AUDIO_CODEC_DMIC2_SB, CODEC_ITF_AC, FLD_AUDIO_CODEC_DMIC1_SB,
CODEC_ITF_AC));
}
else if (in_mode == LINE_INPUT) {
/*analog 0/4/8/12/16/20 dB boost gain*/
} else if (in_mode == LINE_INPUT) {
/* analog 0/4/8/12/16/20 dB boost gain */
audio_i2c_codec_write(addr_audio_codec_mic_l_R_gain,
MASK_VAL(FLD_AUDIO_CODEC_AMIC_L_GAIN, audio_i2s_codec_config.in_analog_gain,
FLD_AUDIO_CODEC_AMIC_R_GAIN, audio_i2s_codec_config.in_analog_gain));
}
/*0db~43db 1db step ,digital programmable gain*/
/* 0db~43db 1db step ,digital programmable gain */
audio_i2c_codec_write(addr_audio_adc1_gain, MASK_VAL(FLD_AUDIO_CODEC_ADC_LRGID, 1, FLD_AUDIO_CODEC_ADC_GID1,
audio_i2s_codec_config.in_digital_gain));
@@ -762,13 +734,13 @@ void audio_codec_adc_config(i2s_codec_m_s_mode_e mode, audio_input_mode_e in_mod
MASK_VAL(FLD_AUDIO_CODEC_FORMAT, CODEC_I2S_MODE, FLD_AUDIO_CODEC_SLAVE, mode,
FLD_AUDIO_CODEC_WL, data_select));
audio_i2c_codec_write(addr_audio_codec_adc2_ctr, ~FLD_AUDIO_CODEC_ADC12_SB); /*audio adc interface active*/
audio_i2c_codec_write(addr_audio_codec_adc2_ctr, ~FLD_AUDIO_CODEC_ADC12_SB); /* audio adc interface active */
/* adc high pass filter active, set adc sample rate */
audio_i2c_codec_write(addr_audio_codec_adc_freq_ctr,
MASK_VAL(FLD_AUDIO_CODEC_ADC12_HPF_EN, 1, FLD_AUDIO_CODEC_ADC_FREQ, rate));
/*dac mute*/
/* dac mute */
audio_i2c_codec_write(addr_audio_codec_adc12_ctr, MASK_VAL(FLD_AUDIO_CODEC_ADC1_SB, 0, FLD_AUDIO_CODEC_ADC2_SB,
0, FLD_AUDIO_CODEC_ADC12_SOFT_MUTE, 0));
}
@@ -801,7 +773,6 @@ void audio_mux_config(audio_flow_e audio_flow, audio_in_mode_e ain0_mode, audio_
void audio_i2s_config(i2s_mode_select_e i2s_format, i2s_data_select_e wl, i2s_codec_m_s_mode_e m_s,
audio_data_invert_e en)
{
reg_i2s_cfg = MASK_VAL(FLD_AUDIO_I2S_FORMAT, i2s_format, FLD_AUDIO_I2S_WL, wl, FLD_AUDIO_I2S_LRP, 0,
FLD_AUDIO_I2S_LRSWAP, en, FLD_AUDIO_I2S_ADC_DCI_MS, m_s, FLD_AUDIO_I2S_DAC_DCI_MS, m_s);
}
@@ -817,31 +788,31 @@ void audio_i2s_config(i2s_mode_select_e i2s_format, i2s_data_select_e wl, i2s_co
_attribute_ram_code_sec_noinline_ void audio_set_i2s_clock(audio_sample_rate_e audio_rate, audio_rate_match_e match,
unsigned char match_en)
{
reg_tx_wptr = 0xffff; //enable tx_rptr
reg_tx_wptr = 0xffff; // enable tx_rptr
unsigned short tx_rptr_old;
switch (audio_rate) {
case AUDIO_8K:
audio_set_i2s_clk(1, 8); //set i2s clk 24M
audio_set_i2s_bclk(12); //24/(2*12) = 1M bclk
audio_set_lrclk(125, 125); //bclk/125=8k
audio_set_i2s_clk(1, 8); // set i2s clk 24M
audio_set_i2s_bclk(12); // 24/(2*12) = 1M bclk
audio_set_lrclk(125, 125); // bclk/125=8k
break;
case AUDIO_16K:
audio_set_i2s_clk(1, 8); //set i2s clk 24M
audio_set_i2s_bclk(6); //24/(2*6) = 2M bclk
audio_set_lrclk(125, 125); //bclk/125=16k
audio_set_i2s_clk(1, 8); // set i2s clk 24M
audio_set_i2s_bclk(6); // 24/(2*6) = 2M bclk
audio_set_lrclk(125, 125); // bclk/125=16k
break;
case AUDIO_32K:
audio_set_i2s_clk(1, 8); //set i2s clk 24M
audio_set_i2s_bclk(3); //24/(2*3) = 4M bclk
audio_set_lrclk(125, 125); //bclk/125=32k
audio_set_i2s_clk(1, 8); // set i2s clk 24M
audio_set_i2s_bclk(3); // 24/(2*3) = 4M bclk
audio_set_lrclk(125, 125); // bclk/125=32k
break;
case AUDIO_ADC_16K_DAC_48K:
audio_set_i2s_clk(2, 125); //i2s clk 3.072 M
audio_set_i2s_bclk(0); //3.072/1 = 3.072M bclk
audio_set_lrclk(192, 64); //adc_lrclk=3.072/192=16K,dac_lrclk=3.072/64=48K
audio_set_i2s_clk(2, 125); // i2s clk 3.072 M
audio_set_i2s_bclk(0); // 3.072/1 = 3.072M bclk
audio_set_lrclk(192, 64); // adc_lrclk=3.072/192=16K,dac_lrclk=3.072/64=48K
break;
case AUDIO_48K:
@@ -850,33 +821,24 @@ _attribute_ram_code_sec_noinline_ void audio_set_i2s_clock(audio_sample_rate_e a
while (tx_rptr_old == reg_tx_rptr) {
}
}
if (match == AUDIO_RATE_EQUAL) //48000
{
audio_set_i2s_clk(2, 125); //i2s clk 3.072 M
audio_set_i2s_bclk(0); //3.072/1 = 3.072M bclk
audio_set_lrclk(64, 64); //bclk/64=48k
}
else if (match == AUDIO_RATE_GT_L0) //48004
{
if (match == AUDIO_RATE_EQUAL) { // 48000
audio_set_i2s_clk(2, 125); // i2s clk 3.072 M
audio_set_i2s_bclk(0); // 3.072/1 = 3.072M bclk
audio_set_lrclk(64, 64); // bclk/64=48k
} else if (match == AUDIO_RATE_GT_L0) { // 48004
audio_set_i2s_clk(3, 169);
audio_set_i2s_bclk(0);
audio_set_lrclk(71, 71);
}
else if (match == AUDIO_RATE_GT_L1) //48012.0
{
} else if (match == AUDIO_RATE_GT_L1) { // 48012.0
audio_set_i2s_clk(4, 129);
audio_set_i2s_bclk(0);
audio_set_lrclk(124, 124);
} else if (match == AUDIO_RATE_LT_L0) {
audio_set_i2s_clk(2, 63); //47994.0
audio_set_i2s_clk(2, 63); // 47994.0
audio_set_i2s_bclk(0);
audio_set_lrclk(127, 127);
}
else if (match == AUDIO_RATE_LT_L1) {
audio_set_i2s_clk(4, 165); //47985.0
} else if (match == AUDIO_RATE_LT_L1) {
audio_set_i2s_clk(4, 165); // 47985.0
audio_set_i2s_bclk(0);
audio_set_lrclk(97, 97);
}
@@ -889,39 +851,31 @@ _attribute_ram_code_sec_noinline_ void audio_set_i2s_clock(audio_sample_rate_e a
}
}
if (match == AUDIO_RATE_EQUAL) //44099.9
{
if (match == AUDIO_RATE_EQUAL) { // 44099.9
audio_set_i2s_clk(8, 215);
audio_set_i2s_bclk(0);
audio_set_lrclk(162, 162);
} else if (match == AUDIO_RATE_GT_L0) //44110.2
{
} else if (match == AUDIO_RATE_GT_L0) { // 44110.2
audio_set_i2s_clk(11, 228);
audio_set_i2s_bclk(0);
audio_set_lrclk(210, 210);
}
else if (match == AUDIO_RATE_GT_L1) //44117.6
{
} else if (match == AUDIO_RATE_GT_L1) { // 44117.6
audio_set_i2s_clk(5, 170);
audio_set_i2s_bclk(0);
audio_set_lrclk(128, 128);
}
else if (match == AUDIO_RATE_LT_L0) //44094.4
{
} else if (match == AUDIO_RATE_LT_L0) { // 44094.4
audio_set_i2s_clk(7, 254);
audio_set_i2s_bclk(0);
audio_set_lrclk(120, 120);
}
else if (match == AUDIO_RATE_LT_L1) //44081.6
{
} else if (match == AUDIO_RATE_LT_L1) { // 44081.6
audio_set_i2s_clk(9, 245);
audio_set_i2s_bclk(0);
audio_set_lrclk(160, 160);
}
break;
default:
break;
}
}
@@ -955,15 +909,15 @@ void audio_tx_dma_chain_init(dma_chn_e chn, unsigned short *out_buff, unsigned i
audio_tx_dma_en();
}
#define WM8731_ANA_AUDIO_PATH_CTRL 0x08 //Analogue Audio Path Control
#define WM8731_DIG_AUDIO_PATH_CTRL 0x0a //Digital Audio Path Control
#define WM8731_POWER_DOWN_CTRL 0x0c //Power Down Control
#define WM8731_ST_LINE_VOL 0x00 //Set linmute volume
#define WM8731_ST_RINE_VOL 0x02 //Set rinmute volume
#define WM8731_DIG_AUDIO_INTERFACE_FORMAT 0x0e //Digital Audio Interface Format
#define WM8731_SAMPLING_CTRL 0x10 //Sampling Control
#define WM8731_ACTIVE_CTRL 0x12 //Active Control
#define WM8731_RESET_CTRL 0x1e //Reset Register
#define WM8731_ANA_AUDIO_PATH_CTRL 0x08 // Analogue Audio Path Control
#define WM8731_DIG_AUDIO_PATH_CTRL 0x0a // Digital Audio Path Control
#define WM8731_POWER_DOWN_CTRL 0x0c // Power Down Control
#define WM8731_ST_LINE_VOL 0x00 // Set linmute volume
#define WM8731_ST_RINE_VOL 0x02 // Set rinmute volume
#define WM8731_DIG_AUDIO_INTERFACE_FORMAT 0x0e // Digital Audio Interface Format
#define WM8731_SAMPLING_CTRL 0x10 // Sampling Control
#define WM8731_ACTIVE_CTRL 0x12 // Active Control
#define WM8731_RESET_CTRL 0x1e // Reset Register
unsigned char LineIn_To_I2S_CMD_TAB[9][2] = {
{WM8731_RESET_CTRL, 0x00},
@@ -984,7 +938,7 @@ unsigned char LineIn_To_I2S_CMD_TAB[9][2] = {
*/
void audio_set_ext_codec(void)
{
for (unsigned char i = 0; i < 9; i++) {
for (unsigned char i = 0; i < ARRAY_SIZE(LineIn_To_I2S_CMD_TAB); i++) {
audio_i2c_codec_write(LineIn_To_I2S_CMD_TAB[i][0] >> 1, LineIn_To_I2S_CMD_TAB[i][1]);
}
}
@@ -997,13 +951,12 @@ void audio_set_ext_codec(void)
void pwm_set(pwm_pin_e pin)
{
reg_pwm_enable = 0;
reg_pwm0_enable = 0; //off pwm0
reg_pwm0_enable = 0; // off pwm0
pwm_set_pin(pin);
pwm_set_clk((unsigned char)(sys_clk.pclk * 1000 * 1000 / 24000000 - 1));
//reg_pwm_clkdiv = 0;//set pwm clk equal pclk 24M
pwm_set_pwm0_mode(PWM_NORMAL_MODE);
pwm_set_tcmp(PWM0_ID, 1);
pwm_set_tmax(PWM0_ID, 2); //24M/2=12M pwm mclk to ext codec clk
pwm_set_tmax(PWM0_ID, 2); // 24M/2=12M pwm mclk to ext codec clk
pwm_start(PWM0_ID);
}
@@ -1034,7 +987,7 @@ void audio_i2s_init(pwm_pin_e pwm0_pin, i2c_sda_pin_e sda_pin, i2c_scl_pin_e scl
*/
void audio_pause_out_path(void)
{
BM_SET(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SOFT_MUTE); //dac mute
BM_SET(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SOFT_MUTE); // dac mute
audio_tx_dma_dis();
}
@@ -1044,7 +997,7 @@ void audio_pause_out_path(void)
*/
void audio_resume_out_path(void)
{
BM_CLR(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SOFT_MUTE); //dac unmute
BM_CLR(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SOFT_MUTE); // dac unmute
audio_tx_dma_en();
}
/**
@@ -1089,7 +1042,7 @@ void audio_codec_dac_power_on(void)
BM_CLR(reg_audio_codec_dac_itf_ctr, FLD_AUDIO_CODEC_DAC_ITF_SB);
reg_audio_codec_vic_ctr = MASK_VAL(FLD_AUDIO_CODEC_SB, CODEC_ITF_AC, FLD_AUDIO_CODEC_SB_ANALOG, CODEC_ITF_AC,
FLD_AUDIO_CODEC_SLEEP_ANALOG, CODEC_ITF_AC);
BM_CLR(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SOFT_MUTE); //un mute
BM_CLR(reg_audio_codec_dac_ctr, FLD_AUDIO_CODEC_DAC_SOFT_MUTE); // un mute
audio_tx_dma_en();
}
@@ -1128,3 +1081,4 @@ void audio_codec_adc_power_on(void)
audio_rx_dma_en();
}
b91/b91_ble_sdk/drivers/B91/audio.h
+8 -11
View File
@@ -42,9 +42,9 @@ typedef enum {
} i2s_pin_e;
typedef enum {
DMIC_B2_DAT_B3_CLK, //mono B3 clk1
DMIC_C1_DAT_C2_CLK, //mono C2 clk1
DMIC_D4_DAT_D5_CLK, //mono D5 clk1
DMIC_B2_DAT_B3_CLK, // mono B3 clk1
DMIC_C1_DAT_C2_CLK, // mono C2 clk1
DMIC_D4_DAT_D5_CLK, // mono D5 clk1
DMIC_GROUPB_B2_DAT_B3_B4_CLK,
DMIC_GROUPC_C1_DAT_C2_C3_CLK,
DMIC_GROUPD_D4_DAT_D5_D6_CLK,
@@ -97,7 +97,6 @@ typedef enum {
BIT_20_OR_24_MONO_FIFO1,
BIT_16_STEREO_FIFO0_AND_FIFO1,
BIT_20_OR_24STEREO_FIFO0_AND_FIFO1,
} audio_out_mode_e;
typedef enum {
@@ -147,8 +146,7 @@ typedef enum {
I2S_DATA_INVERT_EN,
} audio_data_invert_e;
typedef struct
{
typedef struct {
unsigned char audio_in_mode;
unsigned char audio_out_mode;
unsigned char i2s_data_select;
@@ -212,7 +210,7 @@ typedef enum {
AUDIO_RATE_LT_L1,
} audio_rate_match_e;
/*[0,+43], 1 dB steps*/
/* [0,+43], 1 dB steps */
typedef enum {
CODEC_IN_D_GAIN_0_DB = 0,
CODEC_IN_D_GAIN_4_DB = 4,
@@ -301,7 +299,6 @@ typedef enum {
} codec_out_path_digital_gain_e;
typedef enum {
CODEC_OUT_A_GAIN_12_DB,
CODEC_OUT_A_GAIN_11_DB,
CODEC_OUT_A_GAIN_10_DB,
@@ -336,7 +333,7 @@ typedef enum {
CODEC_OUT_A_GAIN_m19_DB,
} codec_out_path_analog_gain_e;
/*The Wind Noise filter (WNF) is a programmable high pass filter feature enabling to reduce wind noise .
/* The Wind Noise filter (WNF) is a programmable high pass filter feature enabling to reduce wind noise .
The wind noise filter is a 1st order filter.
Mode1 -3dB 59Hz
corner frequency Mode2 -3dB 117Hz
@@ -351,7 +348,7 @@ typedef enum {
typedef enum {
INNER_CODEC,
EXT_CODEC, //wm8731
EXT_CODEC, // wm8731
} codec_type_e;
typedef enum {
@@ -380,7 +377,7 @@ static inline void audio_set_i2s_clk(unsigned char step, unsigned char mod)
*/
static inline void audio_set_codec_clk(unsigned char step, unsigned char mod)
{
BM_CLR(reg_dmic_clk_set, BIT(0)); //set dmic_div
BM_CLR(reg_dmic_clk_set, BIT(0)); // set dmic_div
reg_dmic_step = (step & FLD_DMIC_STEP) | FLD_DMIC_SEL;
reg_dmic_mod = mod;
}
b91/b91_ble_sdk/drivers/B91/clock.c
+42 -59
View File
@@ -66,9 +66,9 @@ void clock_32k_init(clk_32k_type_e src)
unsigned char power_32k = analog_read_reg8(0x05) & 0xfc;
analog_write_reg8(0x4e, sel_32k | (src << 7));
if (src) {
analog_write_reg8(0x05, power_32k | 0x1); //32k xtal
analog_write_reg8(0x05, power_32k | 0x1); // 32k xtal
} else {
analog_write_reg8(0x05, power_32k | 0x2); //32k rc
analog_write_reg8(0x05, power_32k | 0x2); // 32k rc
}
g_clk_32k_src = src;
}
@@ -85,35 +85,34 @@ unsigned char clock_kick_32k_xtal(unsigned char xtal_times)
for (unsigned char i = 0; i < xtal_times; i++) {
if (0xff == g_chip_version) {
delay_ms(1000);
} else //**Note that the clock is 24M crystal oscillator. PCLK is 24MHZ
{
//2.set PD0 as pwm output
unsigned char pwm_clk = read_reg8(0x1401d8); //**condition: PCLK is 24MHZ,PCLK = HCLK
write_reg8(0x1401d8, ((pwm_clk & 0xfc) | 0x01)); //PCLK = 12M
} else { // **Note that the clock is 24M crystal oscillator. PCLK is 24MHZ
// 2.set PD0 as pwm output
unsigned char pwm_clk = read_reg8(0x1401d8); // **condition: PCLK is 24MHZ,PCLK = HCLK
write_reg8(0x1401d8, ((pwm_clk & 0xfc) | 0x01)); // PCLK = 12M
unsigned char reg_31e = read_reg8(0x14031e); //PD0 -> pwm0
unsigned char reg_31e = read_reg8(0x14031e); // PD0 -> pwm0
write_reg8(0x14031e, reg_31e & 0xfe);
unsigned char reg_336 = read_reg8(0x140336);
write_reg8(0x140336, (reg_336 & 0xfc) | 0x02);
unsigned char reg_355 = read_reg8(0x140355);
write_reg8(0x140355, reg_355 | 0x01);
unsigned short reg_414 = read_reg16(0x140414); //pwm0 cmp
unsigned short reg_414 = read_reg16(0x140414); // pwm0 cmp
write_reg16(0x140414, 0x01);
unsigned short reg_416 = read_reg16(0x140416); //pwm0 max
unsigned short reg_416 = read_reg16(0x140416); // pwm0 max
write_reg16(0x140416, 0x02);
write_reg8(0x140402, 0xb6); //12M/(0xb6 + 1)/2 = 32k
unsigned char reg_401 = read_reg8(0x140401); //pwm_en pwm0 enable
write_reg8(0x140402, 0xb6); // 12M/(0xb6 + 1)/2 = 32k
unsigned char reg_401 = read_reg8(0x140401); // pwm_en pwm0 enable
write_reg8(0x140401, 0x01);
//3.wait for PWM wake up Xtal
// 3.wait for PWM wake up Xtal
delay_ms(10);
//4.Xtal 32k output
analog_write_reg8(0x03, 0x4f); //<7:6>current select
// 4.Xtal 32k output
analog_write_reg8(0x03, 0x4f); // <7:6>current select
//5.Recover PD0 as Xtal pin
// 5.Recover PD0 as Xtal pin
write_reg8(0x1401d8, pwm_clk);
write_reg8(0x14031e, reg_31e);
write_reg8(0x140336, reg_336);
@@ -124,10 +123,10 @@ unsigned char clock_kick_32k_xtal(unsigned char xtal_times)
}
last_32k_tick = clock_get_32k_tick();
delay_us(305); //for 32k tick accumulator, tick period: 30.5us, dly 10 ticks
delay_us(305); // for 32k tick accumulator, tick period: 30.5us, dly 10 ticks
curr_32k_tick = clock_get_32k_tick();
if ((curr_32k_tick - last_32k_tick) > 3) {
return 1; //pwm kick 32k pad success
return 1; // pwm kick 32k pad success
}
}
return 0;
@@ -149,10 +148,10 @@ void clock_cal_24m_rc(void)
analog_write_reg8(0xc7, 0x0e);
analog_write_reg8(0xc7, 0x0f);
while ((analog_read_reg8(0xcf) & 0x80) == 0)
;
while ((analog_read_reg8(0xcf) & 0x80) == 0) {
}
unsigned char cap = analog_read_reg8(0xcb);
analog_write_reg8(0x52, cap); //write 24m cap into manual register
analog_write_reg8(0x52, cap); // write 24m cap into manual register
analog_write_reg8(0x4f, analog_read_reg8(0x4f) & (~BIT(7)));
@@ -171,12 +170,12 @@ void clock_cal_32k_rc(void)
analog_write_reg8(0xc6, 0xf7);
while (0 == (analog_read_reg8(0xcf) & BIT(6))) {
};
unsigned char res1 = analog_read_reg8(0xc9); //read 32k res[13:6]
analog_write_reg8(0x51, res1); //write 32k res[13:6] into manual register
unsigned char res2 = analog_read_reg8(0xca); //read 32k res[5:0]
analog_write_reg8(0x4f, (res2 | (analog_read_reg8(0x4f) & 0xc0))); //write 32k res[5:0] into manual register
unsigned char res1 = analog_read_reg8(0xc9); // read 32k res[13:6]
analog_write_reg8(0x51, res1); // write 32k res[13:6] into manual register
unsigned char res2 = analog_read_reg8(0xca); // read 32k res[5:0]
analog_write_reg8(0x4f, (res2 | (analog_read_reg8(0x4f) & 0xc0))); // write 32k res[5:0] into manual register
analog_write_reg8(0xc6, 0xf6);
analog_write_reg8(0x4f, ((analog_read_reg8(0x4f) & 0x3f) | 0x00)); //manual on
analog_write_reg8(0x4f, ((analog_read_reg8(0x4f) & 0x3f) | 0x00)); // manual on
}
/**
@@ -186,13 +185,13 @@ void clock_cal_32k_rc(void)
*/
void clock_set_32k_tick(unsigned int tick)
{
reg_system_ctrl |= FLD_SYSTEM_32K_WR_EN; //r_32k_wr = 1;
reg_system_ctrl |= FLD_SYSTEM_32K_WR_EN; // r_32k_wr = 1;
while (reg_system_st & FLD_SYSTEM_RD_BUSY) {
}
reg_system_timer_set_32k = tick;
reg_system_st = FLD_SYSTEM_CMD_SYNC; //cmd_sync = 1,trig write
//delay 10us
reg_system_st = FLD_SYSTEM_CMD_SYNC; // cmd_sync = 1,trig write
// delay 10us
__asm__("nop");
__asm__("nop");
__asm__("nop");
@@ -209,7 +208,7 @@ void clock_set_32k_tick(unsigned int tick)
__asm__("nop");
__asm__("nop");
__asm__("nop");
while (reg_system_st & FLD_SYSTEM_CMD_SYNC) { //wait wr_busy = 0
while (reg_system_st & FLD_SYSTEM_CMD_SYNC) { // wait wr_busy = 0
}
}
@@ -217,19 +216,6 @@ void clock_set_32k_tick(unsigned int tick)
* @brief This function serves to get the 32k tick.
* @return none.
*/
#if 0
unsigned int clock_get_32k_tick(void)
{
unsigned int timer_32k_tick;
reg_system_st = FLD_SYSTEM_CLR_RD_DONE;//clr rd_done
while((reg_system_st & FLD_SYSTEM_CLR_RD_DONE) != 0);//wait rd_done = 0;
reg_system_ctrl &= ~FLD_SYSTEM_32K_WR_EN; //1:32k write mode; 0:32k read mode
while((reg_system_st & FLD_SYSTEM_CLR_RD_DONE) == 0);//wait rd_done = 1;
timer_32k_tick = reg_system_timer_read_32k;
reg_system_ctrl |= FLD_SYSTEM_32K_WR_EN; //1:32k write mode; 0:32k read mode
return timer_32k_tick;
}
#else
/*
* modify by yi.bao,confirmed by guangjun at 20210105
* Use digital register way to get 32k tick may read error tick,cause the wakeup time is
@@ -242,7 +228,6 @@ unsigned int clock_get_32k_tick(void)
unsigned int n = 0;
while (1) {
t0 = t1;
t1 = analog_read_reg32(0x60);
@@ -257,7 +242,6 @@ unsigned int clock_get_32k_tick(void)
}
return t1;
}
#endif
/**
* @brief This function use to select the system clock source.
@@ -273,50 +257,49 @@ void clock_init(sys_pll_clk_e pll, sys_clock_src_e src, sys_pll_div_to_cclk_e cc
sys_cclk_div_to_hclk_e hclk_div, sys_hclk_div_to_pclk_e pclk_div,
sys_pll_div_to_mspi_clk_e mspi_clk_div)
{
//pll clk
// pll clk
analog_write_reg8(0x80, (analog_read_reg8(0x80) & 0xe0) | ((pll >> 2) & 0x1f));
analog_write_reg8(0x09, (analog_read_reg8(0x09) & 0xf3) | ((pll & 0x03) << 2));
sys_clk.pll_clk = (pll >> 8);
//usb clock (192M/4 =48M) pll clock should be the multiple of 48, because USB clock is 48M.
// usb clock (192M/4 =48M) pll clock should be the multiple of 48, because USB clock is 48M.
write_reg8(0x1401fb, sys_clk.pll_clk / 48);
//wait for PLL stable
// wait for PLL stable
analog_write_reg8(0x81, (analog_read_reg8(0x81) | BIT(6)));
while (BIT(5) != (analog_read_reg8(0x88) & BIT(5)))
;
while (BIT(5) != (analog_read_reg8(0x88) & BIT(5))) {
}
analog_write_reg8(0x81, (analog_read_reg8(0x81) & ~BIT(6)));
//ensure mspi is not in busy status before change mspi clock
// ensure mspi is not in busy status before change mspi clock
mspi_stop_xip();
//change mspi clock should be ram code.
// change mspi clock should be ram code.
if (CCLK_TO_MSPI_CLK == mspi_clk_div) {
write_reg8(0x1401e8, read_reg8(0x1401e8) & 0x7f); //bit7 0
write_reg8(0x1401e8, read_reg8(0x1401e8) & 0x7f); // bit7 0
} else {
write_reg8(0x1401e9, (read_reg8(0x1401e9) & 0x0f) | (mspi_clk_div << 4));
write_reg8(0x1401e8, read_reg8(0x1401e8) |
BIT(7)); //if the div is odd, should set two times to ensure the correct sequence.
BIT(7)); // if the div is odd, should set two times to ensure the correct sequence.
write_reg8(0x1401e8, read_reg8(0x1401e8) | BIT(7));
sys_clk.mspi_clk = sys_clk.pll_clk / mspi_clk_div;
}
//hclk and pclk should be set ahead of cclk, ensure the hclk and pclk not exceed the max clk(cclk max 96M, hclk max 48M, pclk max 24M)
// hclk and pclk should be set ahead of cclk, ensure the hclk and pclk not exceed the max clk(cclk max 96M, hclk max 48M, pclk max 24M)
if (CCLK_DIV1_TO_HCLK == hclk_div) {
write_reg8(0x1401d8, read_reg8(0x1401d8) & ~BIT(2));
} else {
write_reg8(0x1401d8, read_reg8(0x1401d8) | BIT(2));
}
//pclk can div1/div2/div4 from hclk.
// pclk can div1/div2/div4 from hclk.
if (HCLK_DIV1_TO_PCLK == pclk_div) {
write_reg8(0x1401d8, read_reg8(0x1401d8) & 0xfc);
} else {
write_reg8(0x1401d8, (read_reg8(0x1401d8) & 0xfc) | (pclk_div / 2));
}
//select cclk source(RC24M/PAD24M/PAD_PLL_DIV/PAD_PLL)
// select cclk source(RC24M/PAD24M/PAD_PLL_DIV/PAD_PLL)
if (PAD_PLL_DIV == src) {
write_reg8(0x1401e8, (read_reg8(0x1401e8) & 0xf0) | cclk_div);
sys_clk.cclk = sys_clk.pll_clk / cclk_div;
@@ -327,7 +310,7 @@ void clock_init(sys_pll_clk_e pll, sys_clock_src_e src, sys_pll_div_to_cclk_e cc
}
write_reg8(0x1401e8, (read_reg8(0x1401e8) & 0x8f) | (src << 4));
//clk record.
// clk record.
sys_clk.hclk = sys_clk.cclk / hclk_div;
sys_clk.pclk = sys_clk.hclk / pclk_div;
if (CCLK_TO_MSPI_CLK == mspi_clk_div) {
b91/b91_ble_sdk/drivers/B91/clock.h
+2 -4
View File
@@ -56,8 +56,7 @@
/**
* @brief Define sys_clk struct.
*/
typedef struct
{
typedef struct {
unsigned short pll_clk; /**< pll clk */
unsigned char cclk; /**< cpu clk */
unsigned char hclk; /**< hclk */
@@ -160,7 +159,7 @@ typedef enum {
*/
typedef enum {
CCLK_DIV1_TO_HCLK = 1,
CCLK_DIV2_TO_HCLK = 2, /*< can not use in A0. if use reboot when hclk = 1/2cclk will cause problem */
CCLK_DIV2_TO_HCLK = 2, /* can not use in A0. if use reboot when hclk = 1/2cclk will cause problem */
} sys_cclk_div_to_hclk_e;
/**
@@ -169,7 +168,6 @@ typedef enum {
typedef enum {
RC_24M_CAL_DISABLE = 0,
RC_24M_CAL_ENABLE,
} rc_24M_cal_e;
/**********************************************************************************************************************
b91/b91_ble_sdk/drivers/B91/core.h
-2
View File
@@ -60,7 +60,6 @@ typedef enum {
*/
static inline unsigned int core_interrupt_disable(void)
{
unsigned int r = read_csr(NDS_MIE);
clear_csr(NDS_MIE, BIT(3) | BIT(7) | BIT(11));
return r;
@@ -74,7 +73,6 @@ static inline unsigned int core_interrupt_disable(void)
*/
static inline unsigned int core_restore_interrupt(unsigned int en)
{
set_csr(NDS_MIE, en);
return 0;
}
b91/b91_ble_sdk/drivers/B91/dma.h
+17 -20
View File
@@ -71,7 +71,6 @@ typedef enum {
DMA_REQ_AUDIO0_RX,
DMA_REQ_AUDIO1_TX,
DMA_REQ_AUDIO1_RX,
} dma_req_sel_e;
typedef enum {
@@ -103,26 +102,24 @@ typedef enum {
ABT_MASK = BIT(3),
} dma_irq_mask_e;
typedef struct
{
unsigned int dst_req_sel : 5; /*DstReqSel :8:4 */
unsigned int src_req_sel : 5; /*SrcReqSel :13:9 */
unsigned int dst_addr_ctrl : 2; /*DstAddrCtrl :15:14 0:increment address 1: decrement address 2: fixed address */
unsigned int src_addr_ctrl : 2; /*SrcAddrCtrl :17:16 0:increment address 1: decrement address 2: fixed address */
unsigned int dstmode : 1; /*DstMode:18 0 normal mode 1 handshake*/
unsigned int srcmode : 1; /*SrcMode :19 0 normal mode 1 handshake*/
unsigned int dstwidth : 2; /*DstWidth :21:20 00:byte 01:hword 02:word*/
unsigned int srcwidth : 2; /*SrcWidth :23:22 00:byte 01:hword 02:word*/
unsigned int src_burst_size : 3; /*SrcBurstSize: 26:24*/
unsigned int vacant_bit : 1; /*vacant:27*/
unsigned int read_num_en : 1; /*Rnum_en :28*/
unsigned int priority : 1; /*Pri :29*/
unsigned int write_num_en : 1; /*wnum_en : 30*/
unsigned int auto_en : 1; /*/*auto_en : 31*/
typedef struct {
unsigned int dst_req_sel : 5; /* DstReqSel :8:4 */
unsigned int src_req_sel : 5; /* SrcReqSel :13:9 */
unsigned int dst_addr_ctrl : 2; /* DstAddrCtrl :15:14 0:increment address 1: decrement address 2: fixed address */
unsigned int src_addr_ctrl : 2; /* SrcAddrCtrl :17:16 0:increment address 1: decrement address 2: fixed address */
unsigned int dstmode : 1; /* DstMode:18 0 normal mode 1 handshake */
unsigned int srcmode : 1; /* SrcMode :19 0 normal mode 1 handshake */
unsigned int dstwidth : 2; /* DstWidth :21:20 00:byte 01:hword 02:word */
unsigned int srcwidth : 2; /* SrcWidth :23:22 00:byte 01:hword 02:word */
unsigned int src_burst_size : 3; /* SrcBurstSize: 26:24 */
unsigned int vacant_bit : 1; /* vacant:27 */
unsigned int read_num_en : 1; /* Rnum_en :28 */
unsigned int priority : 1; /* Pri :29 */
unsigned int write_num_en : 1; /* wnum_en : 30 */
unsigned int auto_en : 1; /* auto_en : 31 */
} dma_config_t;
typedef struct
{
typedef struct {
unsigned int dma_chain_ctl;
unsigned int dma_chain_src_addr;
unsigned int dma_chain_dst_addr;
@@ -247,7 +244,7 @@ static inline void dma_clr_abt_irq_status(dma_irq_chn_e abt_chn)
* @param[in] chn - DMA channel
* @param[in] size_byte - the address of dma tx/rx size .The maximum transmission length of DMA is 0xFFFFFC bytes and cannot exceed this length.
* @param[in] byte_width - dma tx/rx width
* @return none
* @return none
*/
static inline void dma_set_size(dma_chn_e chn, unsigned int size_byte, dma_transfer_width_e byte_width)
{
b91/b91_ble_sdk/drivers/B91/driver_b91.h
-2
View File
@@ -15,8 +15,6 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef DRIVER_B91_H
#define DRIVER_B91_H
b91/b91_ble_sdk/drivers/B91/ext_driver/ext_misc.h
+3 -6
View File
@@ -62,7 +62,6 @@ typedef enum {
static inline void systimer_irq_enable(void)
{
reg_irq_src0 |= BIT(IRQ1_SYSTIMER);
//plic_interrupt_enable(IRQ1_SYSTIMER);
}
/**
@@ -72,7 +71,6 @@ static inline void systimer_irq_enable(void)
static inline void systimer_irq_disable(void)
{
reg_irq_src0 &= ~BIT(IRQ1_SYSTIMER);
//plic_interrupt_disable(IRQ1_SYSTIMER);
}
static inline void systimer_set_irq_mask(void)
@@ -136,7 +134,7 @@ typedef enum {
SYSCLK_64M = 64,
} sys_clk_fre_t;
static inline unsigned char clock_get_system_clk()
static inline unsigned char clock_get_system_clk(void)
{
return sys_clk.cclk;
}
@@ -163,7 +161,7 @@ void generateRandomNum(int len, unsigned char *data);
/******************************* sys_end ********************************************************************/
/******************************* plic_start ******************************************************************/
enum { //todo
enum { // todo
FLD_IRQ_EXCEPTION_EN,
FLD_IRQ_SYSTIMER_EN,
FLD_IRQ_ALG_EN,
@@ -181,7 +179,7 @@ enum { //todo
FLD_IRQ_ZB_BT_EN,
FLD_IRQ_ZB_RT_EN,
FLD_IRQ_PWM_EN,
FLD_IRQ_PKE_EN, //add
FLD_IRQ_PKE_EN, // add
FLD_IRQ_UART1_EN,
FLD_IRQ_UART0_EN,
FLD_IRQ_DFIFO_EN,
@@ -225,7 +223,6 @@ enum { //todo
FLD_IRQ_NPE_COMB_EN,
FLD_IRQ_PM_TM_EN,
FLD_IRQ_EOC_EN,
};
/******************************* plic_end ********************************************************************/
b91/b91_ble_sdk/drivers/B91/ext_driver/ext_pm.h
+12 -13
View File
@@ -30,7 +30,7 @@
* @brief available wake-up source for customer
*/
typedef enum {
//not available wake-up source for customer
// not available wake-up source for customer
PM_TIM_RECOVER_START = BIT(14),
PM_TIM_RECOVER_END = BIT(15),
} pm_tim_recover_wakeup_src_e;
@@ -62,9 +62,8 @@ typedef enum {
/**
* @brief deepsleep wakeup by external xtal
*/
typedef struct
{
unsigned char ext_cap_en; //24xtal cap
typedef struct {
unsigned char ext_cap_en; // 24xtal cap
unsigned char pad32k_en;
unsigned char pm_enter_en;
unsigned char rsvd;
@@ -84,22 +83,22 @@ void bls_pm_registerFuncBeforeSuspend(suspend_handler_t func);
* when MCU wakeup from deepsleep, read the information by by calling analog_read function
* Reset these analog registers only by power cycle
*/
#define DEEP_ANA_REG0 0x39 //initial value =0x00
#define DEEP_ANA_REG1 0x3a //initial value =0x00
#define DEEP_ANA_REG2 0x3b //initial value =0x00
#define DEEP_ANA_REG3 0x3c //initial value =0x00
#define DEEP_ANA_REG4 0x3d //initial value =0x00
#define DEEP_ANA_REG5 0x3e //initial value =0x00
#define DEEP_ANA_REG6 0x3f //initial value =0x0f
#define DEEP_ANA_REG0 0x39 // initial value =0x00
#define DEEP_ANA_REG1 0x3a // initial value =0x00
#define DEEP_ANA_REG2 0x3b // initial value =0x00
#define DEEP_ANA_REG3 0x3c // initial value =0x00
#define DEEP_ANA_REG4 0x3d // initial value =0x00
#define DEEP_ANA_REG5 0x3e // initial value =0x00
#define DEEP_ANA_REG6 0x3f // initial value =0x0f
/**
* @brief these analog register can store data in deepsleep mode or deepsleep with SRAM retention mode.
* Reset these analog registers by watchdog, chip reset, RESET Pin, power cycle
*/
#define DEEP_ANA_REG7 0x38 //initial value =0xff
#define DEEP_ANA_REG7 0x38 // initial value =0xff
//ana3e system used, user can not use
// ana3e system used, user can not use
#define SYS_DEEP_ANA_REG PM_ANA_REG_POWER_ON_CLR_BUF0
/**
b91/b91_ble_sdk/drivers/B91/ext_driver/ext_rf.h
+6 -6
View File
@@ -28,10 +28,10 @@
#define DMA_RFRX_OFFSET_DATA 6 // 826x: 14
#define RF_TX_PAKET_DMA_LEN(rf_data_len) ((((rf_data_len) + 3) / 4) | (((rf_data_len) % 4) << 22))
#define DMA_RFRX_OFFSET_CRC24(p) ((p)[DMA_RFRX_OFFSET_RFLEN] + 6) //data len:3
#define DMA_RFRX_OFFSET_TIME_STAMP(p) ((p)[DMA_RFRX_OFFSET_RFLEN] + 9) //data len:4
#define DMA_RFRX_OFFSET_FREQ_OFFSET(p) ((p)[DMA_RFRX_OFFSET_RFLEN] + 13) //data len:2
#define DMA_RFRX_OFFSET_RSSI(p) ((p)[DMA_RFRX_OFFSET_RFLEN] + 15) //data len:1, signed
#define DMA_RFRX_OFFSET_CRC24(p) ((p)[DMA_RFRX_OFFSET_RFLEN] + 6) // data len:3
#define DMA_RFRX_OFFSET_TIME_STAMP(p) ((p)[DMA_RFRX_OFFSET_RFLEN] + 9) // data len:4
#define DMA_RFRX_OFFSET_FREQ_OFFSET(p) ((p)[DMA_RFRX_OFFSET_RFLEN] + 13) // data len:2
#define DMA_RFRX_OFFSET_RSSI(p) ((p)[DMA_RFRX_OFFSET_RFLEN] + 15) // data len:1, signed
#define RF_BLE_RF_PAYLOAD_LENGTH_OK(p) ((p)[5] <= reg_rf_rxtmaxlen)
#define RF_BLE_RF_PACKET_CRC_OK(p) (((p)[(p)[5] + 5 + 11] & 0x01) == 0x0)
@@ -70,8 +70,8 @@ static inline void rf_tx_settle_adjust(unsigned short txstl_us)
*/
static inline void rf_reset_baseband(void)
{
REG_ADDR8(0x801404e3) = 0; //rf_reset_baseband,rf reg need re-setting
REG_ADDR8(0x801404e3) = BIT(0); //release reset signal
REG_ADDR8(0x801404e3) = 0; // rf_reset_baseband,rf reg need re-setting
REG_ADDR8(0x801404e3) = BIT(0); // release reset signal
}
/**
b91/b91_ble_sdk/drivers/B91/flash.c
+52 -57
View File
@@ -135,9 +135,9 @@ _attribute_ram_code_sec_noinline_ void flash_erase_sector_ram(unsigned long addr
}
_attribute_text_sec_ void flash_erase_sector(unsigned long addr)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_erase_sector_ram(addr);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -152,7 +152,7 @@ _attribute_ram_code_sec_noinline_ void flash_write_page_ram(unsigned long addr,
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 1;
#else
unsigned int r = core_interrupt_disable(); //???irq_disable();
unsigned int r = core_interrupt_disable(); // ???irq_disable();
#endif
mspi_stop_xip();
flash_send_cmd(FLASH_WRITE_ENABLE_CMD);
@@ -171,7 +171,7 @@ _attribute_ram_code_sec_noinline_ void flash_write_page_ram(unsigned long addr,
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_write_page(unsigned long addr, unsigned long len, unsigned char *buf)
@@ -181,9 +181,9 @@ _attribute_text_sec_ void flash_write_page(unsigned long addr, unsigned long len
do {
nw = len > ns ? ns : len;
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_write_page_ram(addr, nw, buf);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
ns = PAGE_SIZE;
addr += nw;
buf += nw;
@@ -203,7 +203,7 @@ _attribute_ram_code_sec_noinline_ void flash_read_page_ram(unsigned long addr, u
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 1;
#else
unsigned int r = core_interrupt_disable(); //???irq_disable();
unsigned int r = core_interrupt_disable(); // ???irq_disable();
#endif
mspi_stop_xip();
flash_send_cmd(FLASH_READ_CMD);
@@ -224,14 +224,14 @@ _attribute_ram_code_sec_noinline_ void flash_read_page_ram(unsigned long addr, u
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_read_page(unsigned long addr, unsigned long len, unsigned char *buf)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_read_page_ram(addr, len, buf);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -259,9 +259,9 @@ _attribute_ram_code_sec_noinline_ void flash_erase_chip_ram(void)
}
_attribute_text_sec_ void flash_erase_chip(void)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_erase_chip_ram();
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -287,14 +287,14 @@ _attribute_ram_code_sec_noinline_ void flash_erase_page_ram(unsigned int addr)
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_erase_page(unsigned int addr)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_erase_page_ram(addr);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -320,14 +320,14 @@ _attribute_ram_code_sec_noinline_ void flash_erase_32kblock_ram(unsigned int add
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_erase_32kblock(unsigned int addr)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_erase_32kblock_ram(addr);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -353,14 +353,14 @@ _attribute_ram_code_sec_noinline_ void flash_erase_64kblock_ram(unsigned int add
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_erase_64kblock(unsigned int addr)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_erase_64kblock_ram(addr);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -389,14 +389,14 @@ _attribute_ram_code_sec_noinline_ void flash_write_status_ram(unsigned short dat
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_write_status(unsigned short data)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_write_status_ram(data);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -424,15 +424,15 @@ _attribute_ram_code_sec_noinline_ unsigned short flash_read_status_ram(void)
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
return status;
}
_attribute_text_sec_ unsigned short flash_read_status(void)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
unsigned short status = flash_read_status_ram();
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
return status;
}
@@ -461,14 +461,14 @@ _attribute_ram_code_sec_noinline_ void flash_deep_powerdown_ram(void)
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_deep_powerdown(void)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_deep_powerdown_ram();
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -498,14 +498,14 @@ _attribute_ram_code_sec_noinline_ void flash_release_deep_powerdown_ram(void)
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_release_deep_powerdown(void)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_release_deep_powerdown_ram();
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -517,7 +517,6 @@ _attribute_text_sec_ void flash_release_deep_powerdown(void)
*/
_attribute_ram_code_sec_noinline_ void flash_read_mid_ram(unsigned char *buf)
{
unsigned char j = 0;
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 1;
@@ -543,15 +542,14 @@ _attribute_ram_code_sec_noinline_ void flash_read_mid_ram(unsigned char *buf)
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_read_mid(unsigned char *buf)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_read_mid_ram(buf);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -571,13 +569,11 @@ _attribute_ram_code_sec_noinline_ void flash_read_uid_ram(unsigned char idcmd, u
mspi_stop_xip();
flash_send_cmd(idcmd);
if (idcmd == FLASH_GD_PUYA_READ_UID_CMD) //< GD/puya
{
if (idcmd == FLASH_GD_PUYA_READ_UID_CMD) { // GD/puya
flash_send_addr(0x00);
mspi_write(0x00); /* dummy, to issue clock */
mspi_wait();
} else if (idcmd == FLASH_XTX_READ_UID_CMD) //< XTX
{
} else if (idcmd == FLASH_XTX_READ_UID_CMD) { // XTX
flash_send_addr(0x80);
mspi_write(0x00); /* dummy, to issue clock */
mspi_wait();
@@ -598,14 +594,14 @@ _attribute_ram_code_sec_noinline_ void flash_read_uid_ram(unsigned char idcmd, u
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_read_uid(unsigned char idcmd, unsigned char *buf)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_read_uid_ram(idcmd, buf);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -628,7 +624,7 @@ _attribute_ram_code_sec_noinline_ void flash_lock_ram(flash_type_e type, unsigne
if (type == FLASH_TYPE_PUYA) {
mspi_write((unsigned char)data);
mspi_wait();
mspi_write((unsigned char)(data >> 8)); //16bit status
mspi_write((unsigned char)(data >> 8)); // 16bit status
}
mspi_wait();
mspi_high();
@@ -639,14 +635,14 @@ _attribute_ram_code_sec_noinline_ void flash_lock_ram(flash_type_e type, unsigne
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_lock(flash_type_e type, unsigned short data)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_lock_ram(type, data);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
@@ -668,7 +664,7 @@ _attribute_ram_code_sec_noinline_ void flash_unlock_ram(flash_type_e type)
if (type == FLASH_TYPE_PUYA) {
mspi_write(0);
mspi_wait();
mspi_write(0); //16bit status
mspi_write(0); // 16bit status
}
mspi_wait();
mspi_high();
@@ -678,14 +674,14 @@ _attribute_ram_code_sec_noinline_ void flash_unlock_ram(flash_type_e type)
#if SUPPORT_PFT_ARCH
reg_irq_threshold = 0;
#else
core_restore_interrupt(r); //???irq_restore(r);
core_restore_interrupt(r); // ???irq_restore(r);
#endif
}
_attribute_text_sec_ void flash_unlock(flash_type_e type)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_unlock_ram(type);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/**
* @brief This function is used to update the configuration parameters of xip(eXecute In Place),
@@ -706,9 +702,9 @@ _attribute_ram_code_sec_noinline_ void flash_set_xip_config_sram(flash_xip_confi
}
_attribute_text_sec_ void flash_set_xip_config(flash_xip_config_t config)
{
__asm__("csrci mmisc_ctl,8"); //disable BTB
__asm__("csrci mmisc_ctl,8"); // disable BTB
flash_set_xip_config_sram(config);
__asm__("csrsi mmisc_ctl,8"); //enable BTB
__asm__("csrsi mmisc_ctl,8"); // enable BTB
}
/********************************************************************************************************
@@ -723,7 +719,6 @@ _attribute_text_sec_ void flash_set_xip_config(flash_xip_config_t config)
*/
_attribute_text_sec_ int flash_read_mid_uid_with_check(unsigned int *flash_mid, unsigned char *flash_uid)
{
unsigned char no_uid[16] = {0x51, 0x01, 0x51, 0x01, 0x51, 0x01, 0x51, 0x01,
0x51, 0x01, 0x51, 0x01, 0x51, 0x01, 0x51, 0x01};
int i, f_cnt = 0;
@@ -744,7 +739,7 @@ _attribute_text_sec_ int flash_read_mid_uid_with_check(unsigned int *flash_mid,
f_cnt++;
}
}
if (f_cnt == 16) { //no uid flash
if (f_cnt == 16) { // no uid flash
return 0;
} else {
return 1;
b91/b91_ble_sdk/drivers/B91/flash.h
+10 -8
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_DRIVERS_B91_FLASH_H
#define B91_B91_BLE_SDK_DRIVERS_B91_FLASH_H
#include "compiler.h"
#include "mspi.h"
@@ -34,7 +35,7 @@ typedef enum {
FLASH_READ_STATUS_CMD = 0x05,
FLASH_WRITE_ENABLE_CMD = 0x06,
FLASH_CHIP_ERASE_CMD = 0x60, //or 0xc7
FLASH_CHIP_ERASE_CMD = 0x60, // or 0xc7
FLASH_PES_CMD = 0x75,
FLASH_PER_CMD = 0x7A,
@@ -47,12 +48,12 @@ typedef enum {
FLASH_X4READ_CMD = 0xEB,
FLASH_QREAD_CMD = 0x6B,
FLASH_SECT_ERASE_CMD = 0x20, //sector size = 4KBytes
FLASH_SECT_ERASE_CMD = 0x20, // sector size = 4KBytes
FLASH_32KBLK_ERASE_CMD = 0x52,
FLASH_64KBLK_ERASE_CMD = 0xD8,
FLASH_GD_PUYA_READ_UID_CMD = 0x4B, //Flash Type = GD/PUYA
FLASH_XTX_READ_UID_CMD = 0x5A, //Flash Type = XTX
FLASH_PAGE_ERASE_CMD = 0x81, //caution: only P25Q40L support this function
FLASH_GD_PUYA_READ_UID_CMD = 0x4B, // Flash Type = GD/PUYA
FLASH_XTX_READ_UID_CMD = 0x5A, // Flash Type = XTX
FLASH_PAGE_ERASE_CMD = 0x81, // caution: only P25Q40L support this function
FLASH_POWER_DOWN = 0xB9,
FLASH_POWER_DOWN_RELEASE = 0xAB,
@@ -99,8 +100,7 @@ typedef enum {
FLASH_SIZE_8M = 0x17,
} flash_capacity_e;
typedef struct
{
typedef struct {
unsigned char flash_read_cmd; /**< xip read command */
unsigned char flash_read_dummy : 4; /**< dummy cycle = flash_read_dummy + 1 */
unsigned char flash_read_data_line : 2; /**< 0:single line; 1: dual line; 2:quad line; 3:quad line */
@@ -256,3 +256,5 @@ _attribute_text_sec_ void flash_set_xip_config(flash_xip_config_t config);
* @return none.
*/
_attribute_ram_code_sec_noinline_ void flash_send_cmd(unsigned char cmd);
#endif // B91_B91_BLE_SDK_DRIVERS_B91_FLASH_H
b91/b91_ble_sdk/drivers/B91/gpio.c
+21 -25
View File
@@ -57,13 +57,9 @@ void gpio_input_en(gpio_pin_e pin)
if (group == GPIO_GROUPA || group == GPIO_GROUPB || group == GPIO_GROUPE) {
BM_SET(reg_gpio_ie(pin), bit);
}
else if (group == GPIO_GROUPC) {
} else if (group == GPIO_GROUPC) {
analog_write_reg8(areg_gpio_pc_ie, analog_read_reg8(areg_gpio_pc_ie) | bit);
}
else if (group == GPIO_GROUPD) {
} else if (group == GPIO_GROUPD) {
analog_write_reg8(areg_gpio_pd_ie, analog_read_reg8(areg_gpio_pd_ie) | bit);
}
}
@@ -80,13 +76,9 @@ void gpio_input_dis(gpio_pin_e pin)
if (group == GPIO_GROUPA || group == GPIO_GROUPB || group == GPIO_GROUPE) {
BM_CLR(reg_gpio_ie(pin), bit);
}
else if (group == GPIO_GROUPC) {
} else if (group == GPIO_GROUPC) {
analog_write_reg8(areg_gpio_pc_ie, analog_read_reg8(areg_gpio_pc_ie) & (~bit));
}
else if (group == GPIO_GROUPD) {
} else if (group == GPIO_GROUPD) {
analog_write_reg8(areg_gpio_pd_ie, analog_read_reg8(areg_gpio_pd_ie) & (~bit));
}
}
@@ -153,9 +145,9 @@ void gpio_shutdown(gpio_pin_e pin)
unsigned char bit = pin & 0xff;
switch (group) {
case GPIO_GROUPA:
reg_gpio_pa_oen |= bit; //disable output
reg_gpio_pa_out &= (~bit); //set low level
reg_gpio_pa_ie &= (~bit); //disable input
reg_gpio_pa_oen |= bit; // disable output
reg_gpio_pa_out &= (~bit); // set low level
reg_gpio_pa_ie &= (~bit); // disable input
break;
case GPIO_GROUPB:
reg_gpio_pb_oen |= bit;
@@ -180,33 +172,38 @@ void gpio_shutdown(gpio_pin_e pin)
break;
case GPIO_ALL: {
//as gpio
// as gpio
reg_gpio_pa_gpio = 0x7f;
reg_gpio_pb_gpio = 0xff;
reg_gpio_pc_gpio = 0xff;
reg_gpio_pd_gpio = 0xff;
reg_gpio_pe_gpio = 0xff;
//output disable
// output disable
reg_gpio_pa_oen = 0xff;
reg_gpio_pb_oen = 0xff;
reg_gpio_pc_oen = 0xff;
reg_gpio_pd_oen = 0xff;
reg_gpio_pe_oen = 0xff;
//set low level
// set low level
reg_gpio_pa_out = 0x00;
reg_gpio_pb_out = 0x00;
reg_gpio_pc_out = 0x00;
reg_gpio_pd_out = 0x00;
reg_gpio_pe_out = 0x00;
//disable input
reg_gpio_pa_ie = 0x80; //SWS
// disable input
reg_gpio_pa_ie = 0x80; // SWS
reg_gpio_pb_ie = 0x00;
analog_write_reg8(areg_gpio_pc_ie, 0);
analog_write_reg8(areg_gpio_pd_ie, 0);
reg_gpio_pe_ie = 0x00;
break;
}
default: {
break;
}
}
}
@@ -242,7 +239,7 @@ void gpio_set_irq(gpio_pin_e pin, gpio_irq_trigger_type_e trigger_type)
break;
}
reg_gpio_irq_ctrl |= FLD_GPIO_CORE_INTERRUPT_EN;
reg_gpio_irq_clr = FLD_GPIO_IRQ_CLR; //must clear cause to unexpected interrupt.
reg_gpio_irq_clr = FLD_GPIO_IRQ_CLR; // must clear cause to unexpected interrupt.
BM_SET(reg_gpio_irq_risc_mask, FLD_GPIO_IRQ_MASK_GPIO);
}
@@ -254,7 +251,6 @@ void gpio_set_irq(gpio_pin_e pin, gpio_irq_trigger_type_e trigger_type)
*/
void gpio_set_gpio2risc0_irq(gpio_pin_e pin, gpio_irq_trigger_type_e trigger_type)
{
switch (trigger_type) {
case INTR_RISING_EDGE:
BM_CLR(reg_gpio_pol(pin), pin & 0xff);
@@ -273,7 +269,7 @@ void gpio_set_gpio2risc0_irq(gpio_pin_e pin, gpio_irq_trigger_type_e trigger_typ
BM_SET(reg_gpio_irq_risc_mask, FLD_GPIO_IRQ_LVL_GPIO2RISC0);
break;
}
reg_gpio_irq_clr = FLD_GPIO_IRQ_GPIO2RISC0_CLR; //must clear cause to unexpected interrupt.
reg_gpio_irq_clr = FLD_GPIO_IRQ_GPIO2RISC0_CLR; // must clear cause to unexpected interrupt.
BM_SET(reg_gpio_irq_risc_mask, FLD_GPIO_IRQ_MASK_GPIO2RISC0);
}
@@ -303,7 +299,7 @@ void gpio_set_gpio2risc1_irq(gpio_pin_e pin, gpio_irq_trigger_type_e trigger_typ
BM_SET(reg_gpio_irq_risc_mask, FLD_GPIO_IRQ_LVL_GPIO2RISC1);
break;
}
reg_gpio_irq_clr = FLD_GPIO_IRQ_GPIO2RISC1_CLR; //must clear cause to unexpected interrupt.
reg_gpio_irq_clr = FLD_GPIO_IRQ_GPIO2RISC1_CLR; // must clear cause to unexpected interrupt.
BM_SET(reg_gpio_irq_risc_mask, FLD_GPIO_IRQ_MASK_GPIO2RISC1);
}
@@ -317,7 +313,7 @@ void gpio_set_up_down_res(gpio_pin_e pin, gpio_pull_type_e up_down_res)
{
unsigned char r_val = up_down_res & 0x03;
unsigned char base_ana_reg = 0x0e + ((pin >> 8) << 1) + ((pin & 0xf0) ? 1 : 0); //group = gpio>>8;
unsigned char base_ana_reg = 0x0e + ((pin >> 8) << 1) + ((pin & 0xf0) ? 1 : 0); // group = gpio>>8;
unsigned char shift_num, mask_not;
if (pin & 0x11) {
b91/b91_ble_sdk/drivers/B91/gpio.h
-2
View File
@@ -108,7 +108,6 @@ typedef enum {
GPIO_PF1 = GPIO_GROUPF | BIT(1),
GPIO_PF2 = GPIO_GROUPF | BIT(2),
GPIO_PF3 = GPIO_GROUPF | BIT(3),
} gpio_pin_e;
/**
@@ -128,7 +127,6 @@ typedef enum {
AS_TDO,
AS_TMS,
AS_TCK,
} gpio_fuc_e;
/**
b91/b91_ble_sdk/drivers/B91/gpio_default.h
+33 -33
View File
@@ -39,13 +39,13 @@
#define PA4_INPUT_ENABLE 0
#endif
#ifndef PA5_INPUT_ENABLE
#define PA5_INPUT_ENABLE 0 //USB
#define PA5_INPUT_ENABLE 0 // USB
#endif
#ifndef PA6_INPUT_ENABLE
#define PA6_INPUT_ENABLE 0 //USB
#define PA6_INPUT_ENABLE 0 // USB
#endif
#ifndef PA7_INPUT_ENABLE
#define PA7_INPUT_ENABLE 1 //SWS
#define PA7_INPUT_ENABLE 1 // SWS
#endif
#ifndef PA0_OUTPUT_ENABLE
#define PA0_OUTPUT_ENABLE 0
@@ -165,7 +165,7 @@
#define PULL_WAKEUP_SRC_PA6 0
#endif
#ifndef PULL_WAKEUP_SRC_PA7
#define PULL_WAKEUP_SRC_PA7 GPIO_PIN_PULLUP_1M //sws pullup
#define PULL_WAKEUP_SRC_PA7 GPIO_PIN_PULLUP_1M // sws pullup
#endif
//////////////////////////////////////////////////
@@ -757,22 +757,22 @@
#endif
//////////////////////////////////////////////////
#ifndef PF0_INPUT_ENABLE
#define PF0_INPUT_ENABLE 1 //MSPI
#define PF0_INPUT_ENABLE 1 // MSPI
#endif
#ifndef PF1_INPUT_ENABLE
#define PF1_INPUT_ENABLE 1 //MSPI
#define PF1_INPUT_ENABLE 1 // MSPI
#endif
#ifndef PF2_INPUT_ENABLE
#define PF2_INPUT_ENABLE 1 //MSPI
#define PF2_INPUT_ENABLE 1 // MSPI
#endif
#ifndef PF3_INPUT_ENABLE
#define PF3_INPUT_ENABLE 1 //MSPI
#define PF3_INPUT_ENABLE 1 // MSPI
#endif
#ifndef PF4_INPUT_ENABLE
#define PF4_INPUT_ENABLE 1 //MSPI
#define PF4_INPUT_ENABLE 1 // MSPI
#endif
#ifndef PF5_INPUT_ENABLE
#define PF5_INPUT_ENABLE 1 //MSPI
#define PF5_INPUT_ENABLE 1 // MSPI
#endif
#ifndef PF0_OUTPUT_ENABLE
#define PF0_OUTPUT_ENABLE 0
@@ -862,43 +862,43 @@
*/
static inline void gpio_analog_resistance_init(void)
{
//A<3:0>
// A<3:0>
analog_write_reg8(0x0e, PULL_WAKEUP_SRC_PA0 | (PULL_WAKEUP_SRC_PA1 << 2) | (PULL_WAKEUP_SRC_PA2 << 4) |
(PULL_WAKEUP_SRC_PA3 << 6));
//A<7:4>
// A<7:4>
analog_write_reg8(0x0f, PULL_WAKEUP_SRC_PA4 | (PULL_WAKEUP_SRC_PA5 << 2) | (PULL_WAKEUP_SRC_PA6 << 4) |
(PULL_WAKEUP_SRC_PA7 << 6));
//B<3:0>
// B<3:0>
analog_write_reg8(0x10, PULL_WAKEUP_SRC_PB0 | (PULL_WAKEUP_SRC_PB1 << 2) | (PULL_WAKEUP_SRC_PB2 << 4) |
(PULL_WAKEUP_SRC_PB3 << 6));
//B<7:4>
// B<7:4>
analog_write_reg8(0x11, PULL_WAKEUP_SRC_PB4 | (PULL_WAKEUP_SRC_PB5 << 2) | (PULL_WAKEUP_SRC_PB6 << 4) |
(PULL_WAKEUP_SRC_PB7 << 6));
//C<3:0>
// C<3:0>
analog_write_reg8(0x12, PULL_WAKEUP_SRC_PC0 | (PULL_WAKEUP_SRC_PC1 << 2) | (PULL_WAKEUP_SRC_PC2 << 4) |
(PULL_WAKEUP_SRC_PC3 << 6));
//C<7:4>
// C<7:4>
analog_write_reg8(0x13, PULL_WAKEUP_SRC_PC4 | (PULL_WAKEUP_SRC_PC5 << 2) | (PULL_WAKEUP_SRC_PC6 << 4) |
(PULL_WAKEUP_SRC_PC7 << 6));
//D<3:0>
// D<3:0>
analog_write_reg8(0x14, PULL_WAKEUP_SRC_PD0 | (PULL_WAKEUP_SRC_PD1 << 2) | (PULL_WAKEUP_SRC_PD2 << 4) |
(PULL_WAKEUP_SRC_PD3 << 6));
//D<7:4>
// D<7:4>
analog_write_reg8(0x15, PULL_WAKEUP_SRC_PD4 | (PULL_WAKEUP_SRC_PD5 << 2) | (PULL_WAKEUP_SRC_PD6 << 4) |
(PULL_WAKEUP_SRC_PD7 << 6));
//E<3:0>
// E<3:0>
analog_write_reg8(0x16, PULL_WAKEUP_SRC_PE0 | (PULL_WAKEUP_SRC_PE1 << 2) | (PULL_WAKEUP_SRC_PE2 << 4) |
(PULL_WAKEUP_SRC_PE3 << 6));
//E<7:4>
// E<7:4>
analog_write_reg8(0x17, PULL_WAKEUP_SRC_PE4 | (PULL_WAKEUP_SRC_PE5 << 2) | (PULL_WAKEUP_SRC_PE6 << 4) |
(PULL_WAKEUP_SRC_PE7 << 6));
}
_attribute_ram_code_sec_ static inline void gpio_init(int anaRes_init_en)
{
//PA group
// PA group
reg_gpio_pa_setting1 = (PA0_INPUT_ENABLE << 8) | (PA1_INPUT_ENABLE << 9) | (PA2_INPUT_ENABLE << 10) |
(PA3_INPUT_ENABLE << 11) | (PA4_INPUT_ENABLE << 12) | (PA5_INPUT_ENABLE << 13) |
(PA6_INPUT_ENABLE << 14) | (PA7_INPUT_ENABLE << 15) | ((PA0_OUTPUT_ENABLE ? 0 : 1) << 16) |
@@ -916,7 +916,7 @@ _attribute_ram_code_sec_ static inline void gpio_init(int anaRes_init_en)
(PA4_FUNC == AS_GPIO ? BIT(20) : 0) | (PA5_FUNC == AS_GPIO ? BIT(21) : 0) |
(PA6_FUNC == AS_GPIO ? BIT(22) : 0) | (PA7_FUNC == AS_GPIO ? BIT(23) : 0);
//PB group
// PB group
reg_gpio_pb_setting1 = (PB0_INPUT_ENABLE << 8) | (PB1_INPUT_ENABLE << 9) | (PB2_INPUT_ENABLE << 10) |
(PB3_INPUT_ENABLE << 11) | (PB4_INPUT_ENABLE << 12) | (PB5_INPUT_ENABLE << 13) |
(PB6_INPUT_ENABLE << 14) | (PB7_INPUT_ENABLE << 15) | ((PB0_OUTPUT_ENABLE ? 0 : 1) << 16) |
@@ -934,23 +934,23 @@ _attribute_ram_code_sec_ static inline void gpio_init(int anaRes_init_en)
(PB4_FUNC == AS_GPIO ? BIT(20) : 0) | (PB5_FUNC == AS_GPIO ? BIT(21) : 0) |
(PB6_FUNC == AS_GPIO ? BIT(22) : 0) | (PB7_FUNC == AS_GPIO ? BIT(23) : 0);
//PC group
//ie
// PC group
// ie
analog_write_reg8(areg_gpio_pc_ie, (PC0_INPUT_ENABLE << 0) | (PC1_INPUT_ENABLE << 1) | (PC2_INPUT_ENABLE << 2) |
(PC3_INPUT_ENABLE << 3) | (PC4_INPUT_ENABLE << 4) |
(PC5_INPUT_ENABLE << 5) | (PC6_INPUT_ENABLE << 6) |
(PC7_INPUT_ENABLE << 7));
//oen
// oen
reg_gpio_pc_oen = ((PC0_OUTPUT_ENABLE ? 0 : 1) << 0) | ((PC1_OUTPUT_ENABLE ? 0 : 1) << 1) |
((PC2_OUTPUT_ENABLE ? 0 : 1) << 2) | ((PC3_OUTPUT_ENABLE ? 0 : 1) << 3) |
((PC4_OUTPUT_ENABLE ? 0 : 1) << 4) | ((PC5_OUTPUT_ENABLE ? 0 : 1) << 5) |
((PC6_OUTPUT_ENABLE ? 0 : 1) << 6) | ((PC7_OUTPUT_ENABLE ? 0 : 1) << 7);
//dataO
// dataO
reg_gpio_pc_out = (PC0_DATA_OUT << 0) | (PC1_DATA_OUT << 1) | (PC2_DATA_OUT << 2) | (PC3_DATA_OUT << 3) |
(PC4_DATA_OUT << 4) | (PC5_DATA_OUT << 5) | (PC6_DATA_OUT << 6) | (PC7_DATA_OUT << 7);
//ds
// ds
analog_write_reg8(areg_gpio_pc_ds, (PC0_DATA_STRENGTH << 0) | (PC1_DATA_STRENGTH << 1) | (PC2_DATA_STRENGTH << 2) |
(PC3_DATA_STRENGTH << 3) | (PC4_DATA_STRENGTH << 4) |
(PC5_DATA_STRENGTH << 5) | (PC6_DATA_STRENGTH << 6) |
@@ -961,23 +961,23 @@ _attribute_ram_code_sec_ static inline void gpio_init(int anaRes_init_en)
(PC4_FUNC == AS_GPIO ? BIT(4) : 0) | (PC5_FUNC == AS_GPIO ? BIT(5) : 0) |
(PC6_FUNC == AS_GPIO ? BIT(6) : 0) | (PC7_FUNC == AS_GPIO ? BIT(7) : 0);
//PD group
//ie
// PD group
// ie
analog_write_reg8(areg_gpio_pd_ie, (PD0_INPUT_ENABLE << 0) | (PD1_INPUT_ENABLE << 1) | (PD2_INPUT_ENABLE << 2) |
(PD3_INPUT_ENABLE << 3) | (PD4_INPUT_ENABLE << 4) |
(PD5_INPUT_ENABLE << 5) | (PD6_INPUT_ENABLE << 6) |
(PD7_INPUT_ENABLE << 7));
//oen
// oen
reg_gpio_pd_oen = ((PD0_OUTPUT_ENABLE ? 0 : 1) << 0) | ((PD1_OUTPUT_ENABLE ? 0 : 1) << 1) |
((PD2_OUTPUT_ENABLE ? 0 : 1) << 2) | ((PD3_OUTPUT_ENABLE ? 0 : 1) << 3) |
((PD4_OUTPUT_ENABLE ? 0 : 1) << 4) | ((PD5_OUTPUT_ENABLE ? 0 : 1) << 5) |
((PD6_OUTPUT_ENABLE ? 0 : 1) << 6) | ((PD7_OUTPUT_ENABLE ? 0 : 1) << 7);
//dataO
// dataO
reg_gpio_pd_out = (PD0_DATA_OUT << 0) | (PD1_DATA_OUT << 1) | (PD2_DATA_OUT << 2) | (PD3_DATA_OUT << 3) |
(PD4_DATA_OUT << 4) | (PD5_DATA_OUT << 5) | (PD6_DATA_OUT << 6) | (PD7_DATA_OUT << 7);
//ds
// ds
analog_write_reg8(areg_gpio_pd_ds, (PD0_DATA_STRENGTH << 0) | (PD1_DATA_STRENGTH << 1) | (PD2_DATA_STRENGTH << 2) |
(PD3_DATA_STRENGTH << 3) | (PD4_DATA_STRENGTH << 4) |
(PD5_DATA_STRENGTH << 5) | (PD6_DATA_STRENGTH << 6) |
@@ -988,7 +988,7 @@ _attribute_ram_code_sec_ static inline void gpio_init(int anaRes_init_en)
(PD4_FUNC == AS_GPIO ? BIT(4) : 0) | (PD5_FUNC == AS_GPIO ? BIT(5) : 0) |
(PD6_FUNC == AS_GPIO ? BIT(6) : 0) | (PD7_FUNC == AS_GPIO ? BIT(7) : 0);
//PE group
// PE group
reg_gpio_pe_setting1 = (PE0_INPUT_ENABLE << 8) | (PE1_INPUT_ENABLE << 9) | (PE2_INPUT_ENABLE << 10) |
(PE3_INPUT_ENABLE << 11) | (PE4_INPUT_ENABLE << 12) | (PE5_INPUT_ENABLE << 13) |
(PE6_INPUT_ENABLE << 14) | (PE7_INPUT_ENABLE << 15) | ((PE0_OUTPUT_ENABLE ? 0 : 1) << 16) |
b91/b91_ble_sdk/drivers/B91/i2c.c
+68 -72
View File
@@ -21,19 +21,19 @@ static unsigned char i2c_dma_tx_chn;
static unsigned char i2c_dma_rx_chn;
dma_config_t i2c_tx_dma_config = {
.dst_req_sel = DMA_REQ_I2C_TX, //tx req
.dst_req_sel = DMA_REQ_I2C_TX, // tx req
.src_req_sel = 0,
.dst_addr_ctrl = DMA_ADDR_FIX,
.src_addr_ctrl = DMA_ADDR_INCREMENT, //increment
.dstmode = DMA_HANDSHAKE_MODE, //handshake
.src_addr_ctrl = DMA_ADDR_INCREMENT, // increment
.dstmode = DMA_HANDSHAKE_MODE, // handshake
.srcmode = DMA_NORMAL_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must word
.srcwidth = DMA_CTR_WORD_WIDTH, //must word
.src_burst_size = 0, //must 0
.dstwidth = DMA_CTR_WORD_WIDTH, // must word
.srcwidth = DMA_CTR_WORD_WIDTH, // must word
.src_burst_size = 0, // must 0
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must 0
.auto_en = 0, // must 0
};
dma_config_t i2c_rx_dma_config = {
.dst_req_sel = DMA_REQ_AUDIO0_TX,
@@ -42,13 +42,13 @@ dma_config_t i2c_rx_dma_config = {
.src_addr_ctrl = DMA_ADDR_FIX,
.dstmode = DMA_NORMAL_MODE,
.srcmode = DMA_HANDSHAKE_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must word
.srcwidth = DMA_CTR_WORD_WIDTH, ////must word
.dstwidth = DMA_CTR_WORD_WIDTH, // must word
.srcwidth = DMA_CTR_WORD_WIDTH, //// must word
.src_burst_size = 0,
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must 0
.auto_en = 0, // must 0
};
/*
@@ -80,15 +80,14 @@ void i2c_master_send_stop(unsigned char en)
*/
void i2c_set_pin(i2c_sda_pin_e sda_pin, i2c_scl_pin_e scl_pin)
{
unsigned char val = 0;
unsigned char mask = 0xff;
//disable sda_pin and scl_pin gpio function.
// disable sda_pin and scl_pin gpio function.
gpio_function_dis(scl_pin);
gpio_function_dis(sda_pin);
//enable gpio as i2c sda function.
// enable gpio as i2c sda function.
if (sda_pin == I2C_GPIO_SDA_B3) {
mask = (unsigned char)~(BIT(7) | BIT(6));
val = BIT(6);
@@ -105,7 +104,7 @@ void i2c_set_pin(i2c_sda_pin_e sda_pin, i2c_scl_pin_e scl_pin)
reg_gpio_func_mux(sda_pin) = (reg_gpio_func_mux(sda_pin) & mask) | val;
//enable gpio as i2c scl function.
// enable gpio as i2c scl function.
if (scl_pin == I2C_GPIO_SCL_B2) {
mask = (unsigned char)~(BIT(5) | BIT(4));
val = BIT(4);
@@ -124,8 +123,8 @@ void i2c_set_pin(i2c_sda_pin_e sda_pin, i2c_scl_pin_e scl_pin)
gpio_set_up_down_res(sda_pin, GPIO_PIN_PULLUP_10K);
gpio_set_up_down_res(scl_pin, GPIO_PIN_PULLUP_10K);
gpio_input_en(sda_pin); //enable sda input
gpio_input_en(scl_pin); //enable scl input
gpio_input_en(sda_pin); // enable sda input
gpio_input_en(scl_pin); // enable scl input
}
/**
@@ -135,7 +134,7 @@ void i2c_set_pin(i2c_sda_pin_e sda_pin, i2c_scl_pin_e scl_pin)
*/
void i2c_master_init(void)
{
reg_i2c_sct0 |= FLD_I2C_MASTER; //i2c master enable.
reg_i2c_sct0 |= FLD_I2C_MASTER; // i2c master enable.
}
/**
@@ -146,11 +145,10 @@ void i2c_master_init(void)
*/
void i2c_set_master_clk(unsigned char clock)
{
//i2c frequency = system_clock/(4*clock)
// i2c frequency = system_clock/(4*clock)
reg_i2c_sp = clock;
//set enable flag.
// set enable flag.
reg_clk_en0 |= FLD_CLK0_I2C_EN;
}
@@ -162,9 +160,9 @@ void i2c_set_master_clk(unsigned char clock)
*/
void i2c_slave_init(unsigned char id)
{
reg_i2c_sct0 &= (~FLD_I2C_MASTER); //enable slave mode.
reg_i2c_sct0 &= (~FLD_I2C_MASTER); // enable slave mode.
reg_i2c_id = id; //defaul eagle slave ID is 0x5a
reg_i2c_id = id; // defaul eagle slave ID is 0x5a
}
/**
@@ -176,33 +174,33 @@ void i2c_slave_init(unsigned char id)
*/
unsigned char i2c_master_write(unsigned char id, unsigned char *data, unsigned char len)
{
BM_SET(reg_i2c_status, FLD_I2C_TX_CLR); //clear index
//set i2c master write.
reg_i2c_data_buf(0) = id & (~FLD_I2C_WRITE_READ_BIT); //BIT(0):R:High W:Low;
BM_SET(reg_i2c_status, FLD_I2C_TX_CLR); // clear index
// set i2c master write.
reg_i2c_data_buf(0) = id & (~FLD_I2C_WRITE_READ_BIT); // BIT(0):R:High W:Low;
reg_i2c_sct1 = (FLD_I2C_LS_ADDR | FLD_I2C_LS_START);
while (i2c_master_busy())
;
while (i2c_master_busy()) {
}
if (reg_i2c_mst & FLD_I2C_ACK_IN) {
reg_i2c_sct1 = (FLD_I2C_LS_STOP);
while (i2c_master_busy())
;
while (i2c_master_busy()) {
}
return 0;
}
reg_i2c_len = len;
//write data
// write data
unsigned int cnt = 0;
while (cnt < len) {
if (i2c_get_tx_buf_cnt() < 8) {
reg_i2c_data_buf(cnt % 4) = data[cnt]; //write data
reg_i2c_data_buf(cnt % 4) = data[cnt]; // write data
cnt++;
if (cnt == 1) {
reg_i2c_sct1 = (FLD_I2C_LS_DATAW | g_i2c_stop_en); //launch stop cycle
reg_i2c_sct1 = (FLD_I2C_LS_DATAW | g_i2c_stop_en); // launch stop cycle
}
}
}
while (i2c_master_busy())
;
while (i2c_master_busy()) {
}
return 1;
}
@@ -215,17 +213,17 @@ unsigned char i2c_master_write(unsigned char id, unsigned char *data, unsigned c
*/
unsigned char i2c_master_read(unsigned char id, unsigned char *data, unsigned char len)
{
//set i2c master read.
BM_SET(reg_i2c_status, FLD_I2C_RX_CLR); //clear index
reg_i2c_sct0 |= FLD_I2C_RNCK_EN; //i2c rnck enable.
reg_i2c_data_buf(0) = (id | FLD_I2C_WRITE_READ_BIT); //BIT(0):R:High W:Low;
// set i2c master read.
BM_SET(reg_i2c_status, FLD_I2C_RX_CLR); // clear index
reg_i2c_sct0 |= FLD_I2C_RNCK_EN; // i2c rnck enable.
reg_i2c_data_buf(0) = (id | FLD_I2C_WRITE_READ_BIT); // BIT(0):R:High W:Low;
reg_i2c_sct1 = (FLD_I2C_LS_ADDR | FLD_I2C_LS_START);
while (i2c_master_busy())
;
while (i2c_master_busy()) {
}
if (reg_i2c_mst & FLD_I2C_ACK_IN) {
reg_i2c_sct1 = (FLD_I2C_LS_STOP);
while (i2c_master_busy())
;
while (i2c_master_busy()) {
}
return 0;
}
reg_i2c_sct1 = (FLD_I2C_LS_DATAR | FLD_I2C_LS_ID_R | g_i2c_stop_en);
@@ -237,8 +235,8 @@ unsigned char i2c_master_read(unsigned char id, unsigned char *data, unsigned ch
cnt++;
}
}
while (i2c_master_busy())
;
while (i2c_master_busy()) {
}
return 1;
}
@@ -254,39 +252,39 @@ unsigned char i2c_master_read(unsigned char id, unsigned char *data, unsigned ch
unsigned char i2c_master_write_read(unsigned char id, unsigned char *wr_data, unsigned char wr_len,
unsigned char *rd_data, unsigned char rd_len)
{
BM_SET(reg_i2c_status, FLD_I2C_TX_CLR); //clear index
//set i2c master write.
reg_i2c_data_buf(0) = id & (~FLD_I2C_WRITE_READ_BIT); //BIT(0):R:High W:Low;
BM_SET(reg_i2c_status, FLD_I2C_TX_CLR); // clear index
// set i2c master write.
reg_i2c_data_buf(0) = id & (~FLD_I2C_WRITE_READ_BIT); // BIT(0):R:High W:Low;
reg_i2c_sct1 = (FLD_I2C_LS_ADDR | FLD_I2C_LS_START);
while (i2c_master_busy())
;
while (i2c_master_busy()) {
}
if (reg_i2c_mst & FLD_I2C_ACK_IN) {
reg_i2c_sct1 = (FLD_I2C_LS_STOP);
while (i2c_master_busy())
;
while (i2c_master_busy()) {
}
return 0;
}
reg_i2c_len = wr_len;
//write data
// write data
unsigned int cnt = 0;
while (cnt < wr_len) {
if (i2c_get_tx_buf_cnt() < 8) {
reg_i2c_data_buf(cnt % 4) = wr_data[cnt]; //write data
reg_i2c_data_buf(cnt % 4) = wr_data[cnt]; // write data
cnt++;
if (cnt == 1) {
reg_i2c_sct1 = (FLD_I2C_LS_DATAW);
}
}
}
while (i2c_master_busy())
;
//set i2c master read.
BM_SET(reg_i2c_status, FLD_I2C_RX_CLR); //clear index
reg_i2c_sct0 |= FLD_I2C_RNCK_EN; //i2c rnck enable.
reg_i2c_data_buf(0) = (id | FLD_I2C_WRITE_READ_BIT); //BIT(0):R:High W:Low;
while (i2c_master_busy()) {
}
// set i2c master read.
BM_SET(reg_i2c_status, FLD_I2C_RX_CLR); // clear index
reg_i2c_sct0 |= FLD_I2C_RNCK_EN; // i2c rnck enable.
reg_i2c_data_buf(0) = (id | FLD_I2C_WRITE_READ_BIT); // BIT(0):R:High W:Low;
reg_i2c_sct1 = (FLD_I2C_LS_ADDR | FLD_I2C_LS_START);
while (i2c_master_busy())
;
while (i2c_master_busy()) {
}
reg_i2c_sct1 = (FLD_I2C_LS_DATAR | FLD_I2C_LS_ID_R | FLD_I2C_LS_STOP);
reg_i2c_len = rd_len;
cnt = 0;
@@ -296,8 +294,8 @@ unsigned char i2c_master_write_read(unsigned char id, unsigned char *wr_data, un
cnt++;
}
}
while (i2c_master_busy())
;
while (i2c_master_busy()) {
}
return 1;
}
@@ -311,9 +309,8 @@ unsigned char i2c_master_write_read(unsigned char id, unsigned char *wr_data, un
*/
void i2c_master_write_dma(unsigned char id, unsigned char *data, unsigned char len)
{
//set id.
reg_i2c_id = (id & (~FLD_I2C_WRITE_READ_BIT)); //BIT(0):R:High W:Low
// set id.
reg_i2c_id = (id & (~FLD_I2C_WRITE_READ_BIT)); // BIT(0):R:High W:Low
dma_set_size(i2c_dma_tx_chn, len, DMA_WORD_WIDTH);
dma_set_address(i2c_dma_tx_chn, (unsigned int)convert_ram_addr_cpu2bus(data), reg_i2c_data_buf0_addr);
@@ -326,17 +323,16 @@ void i2c_master_write_dma(unsigned char id, unsigned char *data, unsigned char l
/**
* @brief This function serves to read a packet of data from the specified address of slave device.
* @param[in] id - to set the slave ID.for kite slave ID=0x5c,for eagle slave ID=0x5a.
* @param[in] rx_data - Store the read data
* @param[in] data - Store the read data
* @param[in] len - The total length of the data read back.
* @return none.
*/
void i2c_master_read_dma(unsigned char id, unsigned char *rx_data, unsigned char len)
void i2c_master_read_dma(unsigned char id, unsigned char *data, unsigned char len)
{
reg_i2c_sct0 |= FLD_I2C_RNCK_EN; // i2c rnck enable
reg_i2c_sct0 |= FLD_I2C_RNCK_EN; //i2c rnck enable
//set i2c master read.
reg_i2c_id = (id | FLD_I2C_WRITE_READ_BIT); //BIT(0):R:High W:Low
// set i2c master read.
reg_i2c_id = (id | FLD_I2C_WRITE_READ_BIT); // BIT(0):R:High W:Low
dma_set_size(i2c_dma_rx_chn, len, DMA_WORD_WIDTH);
dma_set_address(i2c_dma_rx_chn, reg_i2c_data_buf0_addr, (unsigned int)convert_ram_addr_cpu2bus(rx_data));
b91/b91_ble_sdk/drivers/B91/i2c.h
-2
View File
@@ -72,12 +72,10 @@ typedef enum {
} i2c_buff_clr_e;
typedef enum {
I2C_TXDONE_STATUS = BIT(0),
I2C_TX_BUF_STATUS = BIT(1),
I2C_RXDONE_STATUS = BIT(2),
I2C_RX_BUF_STATUS = BIT(3),
} i2c_irq_status_e;
typedef enum {
b91/b91_ble_sdk/drivers/B91/lpc.h
+4 -1
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_DRIVERS_B91_LPC_H
#define B91_B91_BLE_SDK_DRIVERS_B91_LPC_H
#include "analog.h"
@@ -116,3 +117,5 @@ static inline unsigned char lpc_get_result(void)
* @return none.
*/
void lpc_set_input_ref(lpc_mode_e mode, lpc_reference_e ref);
#endif // B91_B91_BLE_SDK_DRIVERS_B91_LPC_H
b91/b91_ble_sdk/drivers/B91/mdec.c
+1 -1
View File
@@ -29,7 +29,7 @@
*/
void mdec_init(mdec_pin_e pin)
{
analog_write_reg8(mdec_rst_addr, (analog_read_reg8(mdec_rst_addr) & (~FLD_CLS_MDEC)) | pin); //A0/B7/C4/D0/E0
analog_write_reg8(mdec_rst_addr, (analog_read_reg8(mdec_rst_addr) & (~FLD_CLS_MDEC)) | pin); // A0/B7/C4/D0/E0
}
/**
b91/b91_ble_sdk/drivers/B91/mdec.h
+4 -1
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_DRIVERS_B91_MDEC_H
#define B91_B91_BLE_SDK_DRIVERS_B91_MDEC_H
#include "analog.h"
#include "reg_include/mdec_reg.h"
@@ -67,3 +68,5 @@ void mdec_init(mdec_pin_e pin);
* @return 1 decode success, 0 decode failure.
*/
unsigned char mdec_read_dat(unsigned char *dat);
#endif // B91_B91_BLE_SDK_DRIVERS_B91_MDEC_H
b91/b91_ble_sdk/drivers/B91/mspi.h
+7 -4
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_DRIVERS_B91_MSPI_H
#define B91_B91_BLE_SDK_DRIVERS_B91_MSPI_H
#include "compiler.h"
#include "gpio.h"
@@ -113,8 +114,10 @@ _attribute_ram_code_sec_ static inline unsigned char mspi_read(void)
*/
_attribute_ram_code_sec_ static inline void mspi_stop_xip(void)
{
mspi_wait(); //wait xip busy=0
mspi_high(); //mspi_cn=1, stop xip read
while (gpio_get_level(GPIO_PF3) == 0) { //wait cn=1
mspi_wait(); // wait xip busy=0
mspi_high(); // mspi_cn=1, stop xip read
while (gpio_get_level(GPIO_PF3) == 0) { // wait cn=1
}
}
#endif // B91_B91_BLE_SDK_DRIVERS_B91_MSPI_H
b91/b91_ble_sdk/drivers/B91/pke.c
+76 -74
View File
@@ -15,9 +15,11 @@
* limitations under the License.
*
*****************************************************************************/
#include "pke.h"
#include <limits.h>
#include "string.h"
#include "pke.h"
/**
* @brief get real bit length of big number a of wordLen words.
* @param[in] a - the buffer a.
@@ -43,7 +45,7 @@ unsigned int valid_bits_get(const unsigned int *a, unsigned int wordLen)
return 0;
}
for (j = 32; j > 0; j--) {
for (j = (sizeof(*a)*CHAR_BIT); j > 0; j--) {
if (a[i - 1] & (0x1 << (j - 1))) {
break;
}
@@ -159,8 +161,7 @@ unsigned int div2n_u32(unsigned int a[], signed int aWordLen, unsigned int n)
return i;
}
return aWordLen;
} else //general method
{
} else { // general method
j = n >> 5;
n &= 31;
for (i = 0; i < aWordLen - (signed int)j - 1; i++) {
@@ -170,8 +171,9 @@ unsigned int div2n_u32(unsigned int a[], signed int aWordLen, unsigned int n)
a[i] = a[i + j] >> n;
memset(a + aWordLen - j, 0, j << 2);
if (!a[i])
if (!a[i]) {
return i;
}
return aWordLen - j;
}
}
@@ -238,7 +240,7 @@ unsigned char pke_opr_cal(pke_microcode_e addr, pke_exe_cfg_e cfg)
pke_opr_start();
while (!pke_get_irq_status(FLD_PKE_STAT_DONE)) {
} //0(in progress) 1(done))
} // 0(in progress) 1(done))
return (pke_check_rt_code());
}
@@ -272,7 +274,7 @@ unsigned char pke_calc_pre_mont(const unsigned int *modulus, unsigned int wordLe
pke_set_operand_width(wordLen << 5);
pke_load_operand((unsigned int *)reg_pke_b_ram(3), (unsigned int *)modulus, wordLen); //B3 modulus
pke_load_operand((unsigned int *)reg_pke_b_ram(3), (unsigned int *)modulus, wordLen); // B3 modulus
ret = pke_opr_cal(PKE_MICROCODE_CAL_PRE_MON, 0x00);
@@ -296,14 +298,14 @@ unsigned char pke_eccp_point_del(eccp_curve_t *curve, unsigned int *Px, unsigned
pke_set_operand_width(curve->eccp_p_bitLen);
pke_load_operand((unsigned int *)reg_pke_a_ram(0), Px, wordLen); //A0 Px
pke_load_operand((unsigned int *)reg_pke_a_ram(1), Py, wordLen); //A1 Py
pke_load_operand((unsigned int *)reg_pke_a_ram(5), curve->eccp_a, wordLen); //A5 a
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->eccp_p, wordLen); //B3 p
pke_load_operand((unsigned int *)reg_pke_a_ram(0), Px, wordLen); // A0 Px
pke_load_operand((unsigned int *)reg_pke_a_ram(1), Py, wordLen); // A1 Py
pke_load_operand((unsigned int *)reg_pke_a_ram(5), curve->eccp_a, wordLen); // A5 a
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->eccp_p, wordLen); // B3 p
if ((0 != curve->eccp_p_h) && (0 != curve->eccp_p_n1)) {
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->eccp_p_h, wordLen); //A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->eccp_p_n1, 1); //B4 p_n1
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->eccp_p_h, wordLen); // A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->eccp_p_n1, 1); // B4 p_n1
} else {
pke_opr_cal(PKE_MICROCODE_CAL_PRE_MON, 0x00);
}
@@ -340,15 +342,15 @@ unsigned char pke_eccp_point_add(eccp_curve_t *curve, unsigned int *P1x, unsigne
pke_set_operand_width(curve->eccp_p_bitLen);
pke_load_operand((unsigned int *)reg_pke_b_ram(0), P1x, wordLen); //B0 P1x
pke_load_operand((unsigned int *)reg_pke_b_ram(1), P1y, wordLen); //B1 P1y
pke_load_operand((unsigned int *)reg_pke_a_ram(0), P2x, wordLen); //A0 P2x
pke_load_operand((unsigned int *)reg_pke_a_ram(1), P2y, wordLen); //A1 P2y
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->eccp_p, wordLen); //B3 p
pke_load_operand((unsigned int *)reg_pke_b_ram(0), P1x, wordLen); // B0 P1x
pke_load_operand((unsigned int *)reg_pke_b_ram(1), P1y, wordLen); // B1 P1y
pke_load_operand((unsigned int *)reg_pke_a_ram(0), P2x, wordLen); // A0 P2x
pke_load_operand((unsigned int *)reg_pke_a_ram(1), P2y, wordLen); // A1 P2y
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->eccp_p, wordLen); // B3 p
if ((0 != curve->eccp_p_h) && (0 != curve->eccp_p_n1)) {
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->eccp_p_h, wordLen); //A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->eccp_p_n1, 1); //B4 p_n1
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->eccp_p_h, wordLen); // A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->eccp_p_n1, 1); // B4 p_n1
} else {
pke_opr_cal(PKE_MICROCODE_CAL_PRE_MON, 0x00);
}
@@ -378,15 +380,15 @@ unsigned char pke_eccp_point_verify(eccp_curve_t *curve, unsigned int *Px, unsig
pke_set_operand_width(curve->eccp_p_bitLen);
pke_load_operand((unsigned int *)reg_pke_b_ram(0), Px, wordLen); //B0 Px
pke_load_operand((unsigned int *)reg_pke_b_ram(1), Py, wordLen); //B1 Py
pke_load_operand((unsigned int *)reg_pke_a_ram(5), curve->eccp_a, wordLen); //A5 a
pke_load_operand((unsigned int *)reg_pke_a_ram(4), curve->eccp_b, wordLen); //A4 b
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->eccp_p, wordLen); //B3 p
pke_load_operand((unsigned int *)reg_pke_b_ram(0), Px, wordLen); // B0 Px
pke_load_operand((unsigned int *)reg_pke_b_ram(1), Py, wordLen); // B1 Py
pke_load_operand((unsigned int *)reg_pke_a_ram(5), curve->eccp_a, wordLen); // A5 a
pke_load_operand((unsigned int *)reg_pke_a_ram(4), curve->eccp_b, wordLen); // A4 b
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->eccp_p, wordLen); // B3 p
if ((0 != curve->eccp_p_h) && (0 != curve->eccp_p_n1)) {
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->eccp_p_h, wordLen); //A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->eccp_p_n1, 1); //B4 p_n1
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->eccp_p_h, wordLen); // A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->eccp_p_n1, 1); // B4 p_n1
} else {
pke_opr_cal(PKE_MICROCODE_CAL_PRE_MON, 0x00);
}
@@ -417,15 +419,15 @@ unsigned char pke_eccp_point_mul(eccp_curve_t *curve, unsigned int *k, unsigned
pke_set_operand_width(curve->eccp_p_bitLen);
pke_load_operand((unsigned int *)reg_pke_b_ram(0), Px, wordLen); //B0 Px
pke_load_operand((unsigned int *)reg_pke_b_ram(1), Py, wordLen); //B1 Py
pke_load_operand((unsigned int *)reg_pke_a_ram(5), curve->eccp_a, wordLen); //A5 a
pke_load_operand((unsigned int *)reg_pke_a_ram(4), k, wordLen); //A4 k
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->eccp_p, wordLen); //B3 p
pke_load_operand((unsigned int *)reg_pke_b_ram(0), Px, wordLen); // B0 Px
pke_load_operand((unsigned int *)reg_pke_b_ram(1), Py, wordLen); // B1 Py
pke_load_operand((unsigned int *)reg_pke_a_ram(5), curve->eccp_a, wordLen); // A5 a
pke_load_operand((unsigned int *)reg_pke_a_ram(4), k, wordLen); // A4 k
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->eccp_p, wordLen); // B3 p
if ((0 != curve->eccp_p_h) && (0 != curve->eccp_p_n1)) {
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->eccp_p_h, wordLen); //A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->eccp_p_n1, 1); //B4 p_n1
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->eccp_p_h, wordLen); // A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->eccp_p_n1, 1); // B4 p_n1
} else {
pke_opr_cal(PKE_MICROCODE_CAL_PRE_MON, 0x00);
}
@@ -459,16 +461,16 @@ unsigned char pke_mod_mul(const unsigned int *modulus, const unsigned int *a, co
pke_set_operand_width(wordLen << 5);
pke_load_operand((unsigned int *)(reg_pke_b_ram(3)), (unsigned int *)modulus, wordLen); //B3 modulus
pke_load_operand((unsigned int *)(reg_pke_a_ram(0)), (unsigned int *)a, wordLen); //A0 a
pke_load_operand((unsigned int *)(reg_pke_b_ram(0)), (unsigned int *)b, wordLen); //B0 b
pke_load_operand((unsigned int *)(reg_pke_b_ram(3)), (unsigned int *)modulus, wordLen); // B3 modulus
pke_load_operand((unsigned int *)(reg_pke_a_ram(0)), (unsigned int *)a, wordLen); // A0 a
pke_load_operand((unsigned int *)(reg_pke_b_ram(0)), (unsigned int *)b, wordLen); // B0 b
ret = pke_opr_cal(PKE_MICROCODE_MODMUL, PKE_EXE_CFG_ALL_NON_MONT);
if (ret) {
return ret;
}
pke_read_operand((unsigned int *)(reg_pke_a_ram(0)), out, wordLen); //A0 result
pke_read_operand((unsigned int *)(reg_pke_a_ram(0)), out, wordLen); // A0 result
return PKE_SUCCESS;
}
@@ -489,15 +491,15 @@ unsigned char pke_mod_inv(const unsigned int *modulus, const unsigned int *a, un
pke_set_operand_width(modWordLen << 5);
pke_load_operand((unsigned int *)(reg_pke_b_ram(3)), (unsigned int *)modulus, modWordLen); //B3 modulus
pke_load_operand((unsigned int *)(reg_pke_b_ram(0)), (unsigned int *)a, aWordLen); //B0 a
pke_load_operand((unsigned int *)(reg_pke_b_ram(3)), (unsigned int *)modulus, modWordLen); // B3 modulus
pke_load_operand((unsigned int *)(reg_pke_b_ram(0)), (unsigned int *)a, aWordLen); // B0 a
ret = pke_opr_cal(PKE_MICROCODE_MODINV, 0x00);
if (ret) {
return ret;
}
pke_read_operand((unsigned int *)(reg_pke_a_ram(0)), (unsigned int *)ainv, modWordLen); //A0 ainv
pke_read_operand((unsigned int *)(reg_pke_a_ram(0)), (unsigned int *)ainv, modWordLen); // A0 ainv
return PKE_SUCCESS;
}
@@ -518,16 +520,16 @@ unsigned char pke_mod_add(const unsigned int *modulus, const unsigned int *a, co
pke_set_operand_width(wordLen << 5);
pke_load_operand((unsigned int *)(reg_pke_b_ram(3)), (unsigned int *)modulus, wordLen); //B3 modulus
pke_load_operand((unsigned int *)(reg_pke_a_ram(0)), (unsigned int *)a, wordLen); //A0 a
pke_load_operand((unsigned int *)(reg_pke_b_ram(0)), (unsigned int *)b, wordLen); //B0 b
pke_load_operand((unsigned int *)(reg_pke_b_ram(3)), (unsigned int *)modulus, wordLen); // B3 modulus
pke_load_operand((unsigned int *)(reg_pke_a_ram(0)), (unsigned int *)a, wordLen); // A0 a
pke_load_operand((unsigned int *)(reg_pke_b_ram(0)), (unsigned int *)b, wordLen); // B0 b
ret = pke_opr_cal(PKE_MICROCODE_MODADD, 0x00);
if (ret) {
return ret;
}
pke_read_operand((unsigned int *)(reg_pke_a_ram(0)), out, wordLen); //A0 result
pke_read_operand((unsigned int *)(reg_pke_a_ram(0)), out, wordLen); // A0 result
return PKE_SUCCESS;
}
@@ -548,16 +550,16 @@ unsigned char pke_mod_sub(const unsigned int *modulus, const unsigned int *a, co
pke_set_operand_width(wordLen << 5);
pke_load_operand((unsigned int *)(reg_pke_b_ram(3)), (unsigned int *)modulus, wordLen); //B3 modulus
pke_load_operand((unsigned int *)(reg_pke_a_ram(0)), (unsigned int *)a, wordLen); //A0 a
pke_load_operand((unsigned int *)(reg_pke_b_ram(0)), (unsigned int *)b, wordLen); //B0 b
pke_load_operand((unsigned int *)(reg_pke_b_ram(3)), (unsigned int *)modulus, wordLen); // B3 modulus
pke_load_operand((unsigned int *)(reg_pke_a_ram(0)), (unsigned int *)a, wordLen); // A0 a
pke_load_operand((unsigned int *)(reg_pke_b_ram(0)), (unsigned int *)b, wordLen); // B0 b
ret = pke_opr_cal(PKE_MICROCODE_MODSUB, 0x00);
if (ret) {
return ret;
}
pke_read_operand((unsigned int *)(reg_pke_a_ram(0)), out, wordLen); //A0 result
pke_read_operand((unsigned int *)(reg_pke_a_ram(0)), out, wordLen); // A0 result
return PKE_SUCCESS;
}
@@ -577,14 +579,14 @@ unsigned char pke_x25519_point_mul(mont_curve_t *curve, unsigned int *k, unsigne
pke_set_operand_width(curve->mont_p_bitLen);
pke_load_operand((unsigned int *)reg_pke_a_ram(0), Pu, wordLen); //A0 Pu
pke_load_operand((unsigned int *)reg_pke_b_ram(0), curve->mont_a24, wordLen); //B0 a24
pke_load_operand((unsigned int *)reg_pke_a_ram(4), k, wordLen); //A4 k
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->mont_p, wordLen); //B3 p
pke_load_operand((unsigned int *)reg_pke_a_ram(0), Pu, wordLen); // A0 Pu
pke_load_operand((unsigned int *)reg_pke_b_ram(0), curve->mont_a24, wordLen); // B0 a24
pke_load_operand((unsigned int *)reg_pke_a_ram(4), k, wordLen); // A4 k
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->mont_p, wordLen); // B3 p
if ((NULL != curve->mont_p_h) && (NULL != curve->mont_p_n1)) {
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->mont_p_h, wordLen); //A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->mont_p_n1, 1); //B4 p_n1
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->mont_p_h, wordLen); // A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->mont_p_n1, 1); // B4 p_n1
} else {
pke_opr_cal(PKE_MICROCODE_CAL_PRE_MON, 0x00);
}
@@ -617,15 +619,15 @@ unsigned char pke_ed25519_point_mul(edward_curve_t *curve, unsigned int *k, unsi
pke_set_operand_width(curve->edward_p_bitLen);
pke_load_operand((unsigned int *)reg_pke_a_ram(1), Px, wordLen); //A1 Px
pke_load_operand((unsigned int *)reg_pke_a_ram(2), Py, wordLen); //A2 Py
pke_load_operand((unsigned int *)reg_pke_b_ram(0), curve->edward_d, wordLen); //B0 d
pke_load_operand((unsigned int *)reg_pke_a_ram(0), k, wordLen); //A0 k
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->edward_p, wordLen); //B3 p
pke_load_operand((unsigned int *)reg_pke_a_ram(1), Px, wordLen); // A1 Px
pke_load_operand((unsigned int *)reg_pke_a_ram(2), Py, wordLen); // A2 Py
pke_load_operand((unsigned int *)reg_pke_b_ram(0), curve->edward_d, wordLen); // B0 d
pke_load_operand((unsigned int *)reg_pke_a_ram(0), k, wordLen); // A0 k
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->edward_p, wordLen); // B3 p
if ((0 != curve->edward_p_h) && (0 != curve->edward_p_n1)) {
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->edward_p_h, wordLen); //A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->edward_p_n1, 1); //B4 p_n1
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->edward_p_h, wordLen); // A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->edward_p_n1, 1); // B4 p_n1
} else {
pke_opr_cal(PKE_MICROCODE_CAL_PRE_MON, 0x00);
}
@@ -662,16 +664,16 @@ unsigned char pke_ed25519_point_add(edward_curve_t *curve, unsigned int *P1x, un
pke_set_operand_width(curve->edward_p_bitLen);
pke_load_operand((unsigned int *)reg_pke_a_ram(1), P1x, wordLen); //A1 P1x
pke_load_operand((unsigned int *)reg_pke_a_ram(2), P1y, wordLen); //A2 P1y
pke_load_operand((unsigned int *)reg_pke_b_ram(1), P2x, wordLen); //B1 P2x
pke_load_operand((unsigned int *)reg_pke_b_ram(2), P2y, wordLen); //B2 P2y
pke_load_operand((unsigned int *)reg_pke_b_ram(0), curve->edward_d, wordLen); //B0 d
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->edward_p, wordLen); //B3 p
pke_load_operand((unsigned int *)reg_pke_a_ram(1), P1x, wordLen); // A1 P1x
pke_load_operand((unsigned int *)reg_pke_a_ram(2), P1y, wordLen); // A2 P1y
pke_load_operand((unsigned int *)reg_pke_b_ram(1), P2x, wordLen); // B1 P2x
pke_load_operand((unsigned int *)reg_pke_b_ram(2), P2y, wordLen); // B2 P2y
pke_load_operand((unsigned int *)reg_pke_b_ram(0), curve->edward_d, wordLen); // B0 d
pke_load_operand((unsigned int *)reg_pke_b_ram(3), curve->edward_p, wordLen); // B3 p
if ((0 != curve->edward_p_h) && (0 != curve->edward_p_n1)) {
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->edward_p_h, wordLen); //A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->edward_p_n1, 1); //B4 p_n1
pke_load_operand((unsigned int *)reg_pke_a_ram(3), curve->edward_p_h, wordLen); // A3 p_h
pke_load_operand((unsigned int *)reg_pke_b_ram(4), curve->edward_p_n1, 1); // B4 p_n1
} else {
pke_opr_cal(PKE_MICROCODE_CAL_PRE_MON, 0x00);
}
@@ -722,7 +724,7 @@ unsigned char pke_mod(unsigned int *a, unsigned int aWordLen, unsigned int *b, u
pke_set_operand_width(bWordLen << 5);
p = (unsigned int *)reg_pke_a_ram(1);
//get a_high mod b
// get a_high mod b
a_high = c;
if (bitLen) {
tmpLen = aWordLen - bWordLen + 1;
@@ -756,14 +758,14 @@ unsigned char pke_mod(unsigned int *a, unsigned int aWordLen, unsigned int *b, u
pke_load_pre_calc_mont(b_h, b_n1, bWordLen);
}
//get 1000...000 mod b
// get 1000...000 mod b
memset(p, 0, bWordLen << 2);
if (bitLen) {
p[bWordLen - 1] = 1 << (bitLen);
}
sub_u32(p, b, (unsigned int *)reg_pke_b_ram(1), bWordLen);
//get a_high * 1000..000 mod b
// get a_high * 1000..000 mod b
pke_set_exe_cfg(PKE_EXE_CFG_ALL_NON_MONT);
pke_calc_pre_mont(b, bWordLen);
ret = pke_mod_mul(b, (unsigned int *)reg_pke_b_ram(1), a_high, (unsigned int *)reg_pke_b_ram(1), bWordLen);
@@ -771,7 +773,7 @@ unsigned char pke_mod(unsigned int *a, unsigned int aWordLen, unsigned int *b, u
return ret;
}
//get a_low mod b
// get a_low mod b
if (bitLen) {
a_low = c;
memcpy(p, a, bWordLen << 2);
b91/b91_ble_sdk/drivers/B91/pke.h
+13 -15
View File
@@ -15,12 +15,13 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_DRIVERS_B91_PKE_H
#define B91_B91_BLE_SDK_DRIVERS_B91_PKE_H
#include "reg_include/register_b91.h"
#define GET_WORD_LEN(bitLen) ((bitLen + 31) / 32)
#define GET_BYTE_LEN(bitLen) ((bitLen + 7) / 8)
#define GET_WORD_LEN(bitLen) (((bitLen) + 31) / 32)
#define GET_BYTE_LEN(bitLen) (((bitLen) + 7) / 8)
#define PKE_BASE (0X80110000)
#define reg_pke_a_ram(a) ((volatile unsigned long *)(PKE_BASE + 0x0400 + (a) * (0x24)))
@@ -39,10 +40,9 @@
/**
* eccp curve
*/
typedef struct
{
unsigned int eccp_p_bitLen; //bit length of prime p
unsigned int eccp_n_bitLen; //bit length of order n
typedef struct {
unsigned int eccp_p_bitLen; // bit length of prime p
unsigned int eccp_n_bitLen; // bit length of order n
unsigned int *eccp_p;
unsigned int *eccp_p_h;
unsigned int *eccp_p_n1;
@@ -58,9 +58,8 @@ typedef struct
/**
* mont curve
*/
typedef struct
{
unsigned int mont_p_bitLen; //bit length of prime p
typedef struct {
unsigned int mont_p_bitLen; // bit length of prime p
unsigned int *mont_p;
unsigned int *mont_p_h;
unsigned int *mont_p_n1;
@@ -76,9 +75,8 @@ typedef struct
/**
* edward curve
*/
typedef struct
{
unsigned int edward_p_bitLen; //bit length of prime p
typedef struct {
unsigned int edward_p_bitLen; // bit length of prime p
unsigned int *edward_p;
unsigned int *edward_p_h;
unsigned int *edward_p_n1;
@@ -89,7 +87,6 @@ typedef struct
unsigned int *edward_n_h;
unsigned int *edward_n_n1;
unsigned int *edward_h;
} edward_curve_t;
/**
@@ -129,7 +126,6 @@ typedef enum {
PKE_MICROCODE_C25519_PMUL = 0x34,
PKE_MICROCODE_Ed25519_PMUL = 0x38,
PKE_MICROCODE_Ed25519_PADD = 0x3C,
} pke_microcode_e;
/**
@@ -424,3 +420,5 @@ unsigned char pke_ed25519_point_mul(edward_curve_t *curve, unsigned int *k, unsi
*/
unsigned char pke_ed25519_point_add(edward_curve_t *curve, unsigned int *P1x, unsigned int *P1y, unsigned int *P2x,
unsigned int *P2y, unsigned int *Qx, unsigned int *Qy);
#endif // B91_B91_BLE_SDK_DRIVERS_B91_PKE_H
b91/b91_ble_sdk/drivers/B91/plic.h
+3 -5
View File
@@ -33,8 +33,7 @@
#include "compiler.h"
#include "reg_include/register_b91.h"
typedef struct
{
typedef struct {
unsigned char preempt_en;
unsigned char threshold;
} preempt_config_t;
@@ -104,11 +103,10 @@ typedef enum {
IRQ61_NPE_COMB,
IRQ62_PM_TM,
IRQ63_EOC,
} irq_source_e;
typedef enum {
IRQ_PRI_LEV0, //Never interrupt
IRQ_PRI_LEV0, // Never interrupt
IRQ_PRI_LEV1,
IRQ_PRI_LEV2,
IRQ_PRI_LEV3,
@@ -121,7 +119,7 @@ typedef enum {
*/
static inline void plic_set_feature(feature_e feature)
{
reg_irq_feature = feature; //enable vectored in PLIC
reg_irq_feature = feature; // enable vectored in PLIC
}
/**
b91/b91_ble_sdk/drivers/B91/pm.h
+35 -36
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_DRIVERS_B91_PM_H
#define B91_B91_BLE_SDK_DRIVERS_B91_PM_H
#include "clock.h"
#include "compiler.h"
@@ -30,7 +31,8 @@
* This is currently included in the H file for compatibility with other SDKs.
*******************************************************************************************************/
//When the watchdog comes back, the Eagle chip does not clear 0x7f[0]. To avoid this problem, this macro definition is added.
// When the watchdog comes back, the Eagle chip does not clear 0x7f[0].
// To avoid this problem, this macro definition is added.
#ifndef WDT_REBOOT_RESET_ANA7F_WORK_AROUND
#define WDT_REBOOT_RESET_ANA7F_WORK_AROUND 1
#endif
@@ -82,23 +84,23 @@ typedef enum {
* @brief suspend power weather to power down definition
*/
typedef enum {
PM_POWERON_BASEBAND = BIT(0), //weather to power on the BASEBAND before suspend.
PM_POWERON_USB = BIT(1), //weather to power on the USB before suspend.
PM_POWERON_NPE = BIT(2), //weather to power on the NPE before suspend.
PM_POWERON_BASEBAND = BIT(0), // weather to power on the BASEBAND before suspend.
PM_POWERON_USB = BIT(1), // weather to power on the USB before suspend.
PM_POWERON_NPE = BIT(2), // weather to power on the NPE before suspend.
} pm_suspend_power_cfg_e;
/**
* @brief sleep mode.
*/
typedef enum {
//available mode for customer
SUSPEND_MODE = 0x00, //The A0 version of the suspend execution process is abnormal and the program restarts.
DEEPSLEEP_MODE = 0x30, //when use deep mode pad wakeup(low or high level), if the high(low) level always in
//the pad, system will not enter sleep and go to below of pm API, will reboot by core_6f = 0x20
//deep retention also had this issue, but not to reboot.
DEEPSLEEP_MODE_RET_SRAM_LOW32K = 0x21, //for boot from sram
DEEPSLEEP_MODE_RET_SRAM_LOW64K = 0x03, //for boot from sram
//not available mode
// available mode for customer
SUSPEND_MODE = 0x00, // The A0 version of the suspend execution process is abnormal and the program restarts.
DEEPSLEEP_MODE = 0x30, // when use deep mode pad wakeup(low or high level), if the high(low) level always in
// the pad, system will not enter sleep and go to below of pm API, will reboot by core_6f = 0x20
// deep retention also had this issue, but not to reboot.
DEEPSLEEP_MODE_RET_SRAM_LOW32K = 0x21, // for boot from sram
DEEPSLEEP_MODE_RET_SRAM_LOW64K = 0x03, // for boot from sram
// not available mode
DEEPSLEEP_RETENTION_FLAG = 0x0F,
} pm_sleep_mode_e;
@@ -135,44 +137,41 @@ typedef enum {
*/
typedef enum {
MCU_STATUS_POWER_ON = BIT(0),
MCU_STATUS_REBOOT_BACK = BIT(2), //the user will not see the reboot status.
MCU_STATUS_REBOOT_BACK = BIT(2), // the user will not see the reboot status.
MCU_STATUS_DEEPRET_BACK = BIT(3),
MCU_STATUS_DEEP_BACK = BIT(4),
MCU_STATUS_REBOOT_DEEP_BACK = BIT(5), //reboot + deep
MCU_STATUS_REBOOT_DEEP_BACK = BIT(5), // reboot + deep
} pm_mcu_status;
/**
* @brief early wakeup time
*/
typedef struct
{
unsigned short
suspend_early_wakeup_time_us; /**< suspend_early_wakeup_time_us = deep_ret_r_delay_us + xtal_stable_time + early_time*/
unsigned short
deep_ret_early_wakeup_time_us; /**< deep_ret_early_wakeup_time_us = deep_ret_r_delay_us + early_time*/
unsigned short deep_early_wakeup_time_us; /**< deep_early_wakeup_time_us = suspend_ret_r_delay_us*/
unsigned short sleep_min_time_us; /**< sleep_min_time_us = suspend_early_wakeup_time_us + 200*/
typedef struct {
/** suspend_early_wakeup_time_us = deep_ret_r_delay_us + xtal_stable_time + early_time */
unsigned short suspend_early_wakeup_time_us;
/** deep_ret_early_wakeup_time_us = deep_ret_r_delay_us + early_time */
unsigned short deep_ret_early_wakeup_time_us;
unsigned short deep_early_wakeup_time_us; /**< deep_early_wakeup_time_us = suspend_ret_r_delay_us */
unsigned short sleep_min_time_us; /**< sleep_min_time_us = suspend_early_wakeup_time_us + 200 */
} pm_early_wakeup_time_us_s;
/**
* @brief hardware delay time
*/
typedef struct
{
unsigned short deep_r_delay_cycle; /**< hardware delay time ,deep_ret_r_delay_us = deep_r_delay_cycle * 1/16k */
unsigned short
suspend_ret_r_delay_cycle; /**< hardware delay time ,suspend_ret_r_delay_us = suspend_ret_r_delay_cycle * 1/16k */
typedef struct {
/** hardware delay time ,deep_ret_r_delay_us = deep_r_delay_cycle * 1/16k */
unsigned short deep_r_delay_cycle;
/** hardware delay time ,suspend_ret_r_delay_us = suspend_ret_r_delay_cycle * 1/16k */
unsigned short suspend_ret_r_delay_cycle;
} pm_r_delay_cycle_s;
/**
* @brief deepsleep wakeup status
*/
typedef struct
{
typedef struct {
unsigned char is_pad_wakeup;
unsigned char
wakeup_src; //The pad pin occasionally wakes up abnormally in A0. The core wakeup flag will be incorrectly set in A0.
// The pad pin occasionally wakes up abnormally in A0. The core wakeup flag will be incorrectly set in A0.
unsigned char wakeup_src;
unsigned char mcu_status;
unsigned char rsvd;
} pm_status_info_s;
@@ -180,8 +179,7 @@ typedef struct
/**
* @brief pm 32k rc calibration algorithm.
*/
typedef struct pm_clock_drift
{
typedef struct pm_clock_drift {
unsigned int ref_tick;
unsigned int ref_tick_32k;
int offset;
@@ -193,7 +191,6 @@ typedef struct pm_clock_drift
int rc32_rt;
int s0;
unsigned char calib;
} pm_clock_drift_t;
extern pm_clock_drift_t pmcd;
@@ -298,3 +295,5 @@ _attribute_ram_code_sec_noinline_ void pm_cal_32k_rc_offset(int offset_tick);
* @return none.
*/
_attribute_ram_code_sec_noinline_ void pm_32k_rc_offset_init(void);
#endif // B91_B91_BLE_SDK_DRIVERS_B91_PM_H
b91/b91_ble_sdk/drivers/B91/pwm.c
+6 -6
View File
@@ -18,15 +18,15 @@
#include "pwm.h"
dma_config_t pwm_tx_dma_config = {
.dst_req_sel = DMA_REQ_PWM_TX, //tx req
.dst_req_sel = DMA_REQ_PWM_TX, // tx req
.src_req_sel = 0,
.dst_addr_ctrl = DMA_ADDR_FIX,
.src_addr_ctrl = DMA_ADDR_INCREMENT, //increment
.dstmode = DMA_HANDSHAKE_MODE, //handshake
.src_addr_ctrl = DMA_ADDR_INCREMENT, // increment
.dstmode = DMA_HANDSHAKE_MODE, // handshake
.srcmode = DMA_NORMAL_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must word
.srcwidth = DMA_CTR_WORD_WIDTH, //must word
.src_burst_size = 0, //must 0
.dstwidth = DMA_CTR_WORD_WIDTH, // must word
.srcwidth = DMA_CTR_WORD_WIDTH, // must word
.src_burst_size = 0, // must 0
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
b91/b91_ble_sdk/drivers/B91/pwm.h
+34 -67
View File
@@ -21,62 +21,37 @@
#include "gpio.h"
#include "reg_include/register_b91.h"
#define get_pwmid(gpio) \
((gpio == PWM_PWM0_PB4) \
? 0 \
: ((gpio == PWM_PWM0_PC0) \
? 0 \
: ((gpio == PWM_PWM0_PE3) \
? 0 \
: ((gpio == PWM_PWM0_N_PD0) \
? 0 \
: ((gpio == PWM_PWM1_PB5) \
? 1 \
: ((gpio == PWM_PWM1_PE1) \
? 1 \
: ((gpio == PWM_PWM1_N_PD1) \
? 1 \
: ((gpio == PWM_PWM2_PB7) \
? 2 \
: ((gpio == PWM_PWM2_PE2) \
? 2 \
: ((gpio == PWM_PWM2_N_PD2) \
? 2 \
: ((gpio == PWM_PWM2_N_PE6) \
? 2 \
: ((gpio == PWM_PWM3_PB1) \
? 3 \
: ((gpio == PWM_PWM3_PE0) \
? 3 \
: ((gpio == \
PWM_PWM3_N_PD3) \
? 3 \
: ((gpio == \
PWM_PWM3_N_PE7) \
? 3 \
: ((gpio == \
PWM_PWM4_PD7) \
? 4 \
: ((gpio == \
PWM_PWM4_PE4) \
? 4 \
: ((gpio == \
PWM_PWM4_N_PD4) \
? 4 \
: ((gpio == \
PWM_PWM5_PB0) \
? 5 \
: ((gpio == \
PWM_PWM5_PE5) \
? 5 \
: ((gpio == \
PWM_PWM5_N_PD5) \
? 5 \
: 0)))))))))))))))))))))
#define get_pwmid(gpio) (((gpio)==PWM_PWM0_PB4) ? 0 : ( \
((gpio)==PWM_PWM0_PC0) ? 0 : ( \
((gpio)==PWM_PWM0_PE3) ? 0 : ( \
((gpio)==PWM_PWM0_N_PD0) ? 0 : ( \
((gpio)==PWM_PWM1_PB5) ? 1 : ( \
((gpio)==PWM_PWM1_PE1) ? 1 : ( \
((gpio)==PWM_PWM1_N_PD1) ? 1 : ( \
((gpio)==PWM_PWM2_PB7) ? 2 : ( \
((gpio)==PWM_PWM2_PE2) ? 2 : ( \
((gpio)==PWM_PWM2_N_PD2) ? 2 : ( \
((gpio)==PWM_PWM2_N_PE6) ? 2 : ( \
((gpio)==PWM_PWM3_PB1) ? 3 : ( \
((gpio)==PWM_PWM3_PE0) ? 3 : ( \
((gpio)==PWM_PWM3_N_PD3) ? 3 : ( \
((gpio)==PWM_PWM3_N_PE7) ? 3 : ( \
((gpio)==PWM_PWM4_PD7) ? 4 : ( \
((gpio)==PWM_PWM4_PE4) ? 4 : ( \
((gpio)==PWM_PWM4_N_PD4) ? 4 : ( \
((gpio)==PWM_PWM5_PB0) ? 5 : ( \
((gpio)==PWM_PWM5_PE5) ? 5 : ( \
((gpio)==PWM_PWM5_N_PD5) ? 5 : 0 \
)))))))))))))))))))))
#define get_pwm_invert_val(gpio) \
((gpio == PWM_PWM0_N_PD0) || (gpio == PWM_PWM1_N_PD1) || (gpio == PWM_PWM2_N_PD2) || (gpio == PWM_PWM2_N_PE6) || \
(gpio == PWM_PWM3_N_PD3) || (gpio == PWM_PWM3_N_PE7) || (gpio == PWM_PWM4_N_PD4) || (gpio == PWM_PWM5_N_PD5))
#define get_pwm_invert_val(gpio) (((gpio)==PWM_PWM0_N_PD0) || \
((gpio)==PWM_PWM1_N_PD1) || \
((gpio)==PWM_PWM2_N_PD2) || \
((gpio)==PWM_PWM2_N_PE6) || \
((gpio)==PWM_PWM3_N_PD3) || \
((gpio)==PWM_PWM3_N_PE7) || \
((gpio)==PWM_PWM4_N_PD4) || \
((gpio)==PWM_PWM5_N_PD5))
/**
* @brief enum variable, the number of PWM channels supported
@@ -137,7 +112,6 @@ typedef enum {
* @brief Select the 32K clock source of pwm.
*/
typedef enum {
PWM_CLOCK_32K_CHN_NONE = 0x00,
PWM_CLOCK_32K_CHN_PWM0 = 0x01,
PWM_CLOCK_32K_CHN_PWM1 = 0x02,
@@ -145,7 +119,6 @@ typedef enum {
PWM_CLOCK_32K_CHN_PWM3 = 0x08,
PWM_CLOCK_32K_CHN_PWM4 = 0x10,
PWM_CLOCK_32K_CHN_PWM5 = 0x20
} pwm_clk_32k_en_chn_e;
/**
@@ -156,7 +129,6 @@ typedef enum {
*/
static inline void pwm_set_clk(unsigned char pwm_clk_div)
{
reg_pwm_clkdiv = pwm_clk_div;
}
@@ -170,7 +142,6 @@ static inline void pwm_set_clk(unsigned char pwm_clk_div)
static inline void pwm_32k_chn_en(pwm_clk_32k_en_chn_e pwm_32K_en_chn)
{
reg_pwm_mode32k |= pwm_32K_en_chn;
}
@@ -204,8 +175,8 @@ static inline void pwm_set_tmax(pwm_id_e id, unsigned short tmax)
}
/*
*@brief This function servers to update the duty cycle in 32K
*@return none.
* @brief This function servers to update the duty cycle in 32K
* @return none.
*/
static inline void pwm_32k_chn_update_duty_cycle(void)
{
@@ -307,7 +278,6 @@ static inline void pwm_set_polarity_dis(pwm_id_e id)
*/
static inline void pwm_set_irq_mask(pwm_irq_e mask)
{
if (mask == FLD_PWM0_IR_FIFO_IRQ) {
BM_SET(reg_pwm_irq_mask(1), BIT(0));
} else {
@@ -322,7 +292,6 @@ static inline void pwm_set_irq_mask(pwm_irq_e mask)
*/
static inline void pwm_clr_irq_mask(pwm_irq_e mask)
{
if (mask == FLD_PWM0_IR_FIFO_IRQ) {
BM_SET(reg_pwm_irq_mask(1), BIT(0));
} else {
@@ -337,7 +306,6 @@ static inline void pwm_clr_irq_mask(pwm_irq_e mask)
*/
static inline unsigned char pwm_get_irq_status(pwm_irq_e status)
{
if (status == FLD_PWM0_IR_FIFO_IRQ) {
return (reg_pwm_irq_sta(1) & BIT(0));
} else {
@@ -352,7 +320,6 @@ static inline unsigned char pwm_get_irq_status(pwm_irq_e status)
*/
static inline void pwm_clr_irq_status(pwm_irq_e status)
{
if (status == FLD_PWM0_IR_FIFO_IRQ) {
BM_SET(reg_pwm_irq_sta(1), BIT(0));
} else {
@@ -367,7 +334,7 @@ static inline void pwm_clr_irq_status(pwm_irq_e status)
*/
static inline void pwm_set_pwm0_mode(pwm_mode_e mode)
{
reg_pwm0_mode = mode; //only PWM0 has count/IR/fifo IR mode
reg_pwm0_mode = mode; // only PWM0 has count/IR/fifo IR mode
}
/**
@@ -417,7 +384,7 @@ static inline void pwm_clr_pwm0_ir_fifo(void)
* @brief This function serves to get the number of data in fifo.
* @return the number of data in fifo
*/
static inline unsigned char pwm_get_pwm0_ir_fifo_data_num(void) //????TODO
static inline unsigned char pwm_get_pwm0_ir_fifo_data_num(void)
{
return (reg_pwm_ir_fifo_data_status & FLD_PWM0_IR_FIFO_DATA_NUM);
}
b91/b91_ble_sdk/drivers/B91/reg_include/adc_reg.h
+3 -3
View File
@@ -44,12 +44,12 @@ enum {
};
#define areg_r_max_mc 0xef
enum {
FLD_R_MAX_MC0 = BIT_RNG(0, 7), //0xef<7:0> r_max_mc[7:0]
FLD_R_MAX_MC0 = BIT_RNG(0, 7), // 0xef<7:0> r_max_mc[7:0]
};
#define areg_r_max_s 0xf1
enum {
FLD_R_MAX_S = BIT_RNG(0, 3), //0xf1<3:0> r_max_s
FLD_R_MAX_MC1 = BIT_RNG(6, 7), //0xf1<7:6> r_max_mc[9:8]
FLD_R_MAX_S = BIT_RNG(0, 3), // 0xf1<3:0> r_max_s
FLD_R_MAX_MC1 = BIT_RNG(6, 7), // 0xf1<7:6> r_max_mc[9:8]
};
#define areg_adc_chn_en 0xf2
enum {
b91/b91_ble_sdk/drivers/B91/reg_include/analog_reg.h
+1 -2
View File
@@ -23,7 +23,7 @@
#define reg_ana_addr REG_ADDR8(ALG_BASE_ADDR)
#define reg_ana_ctrl REG_ADDR8(ALG_BASE_ADDR + 0x02)
enum {
//FLD_ANA_TX_EN = BIT(0),
// FLD_ANA_TX_EN = BIT(0),
FLD_ANA_RX_EN = BIT(1),
FLD_ANA_MASKX_TX_DONE = BIT(2),
FLD_ANA_MASKX_RX_DONE = BIT(3),
@@ -50,7 +50,6 @@ enum {
enum {
FLD_ANA_CYC1 = BIT(0),
FLD_ANA_DMA_EN = BIT(1),
};
#endif
b91/b91_ble_sdk/drivers/B91/reg_include/audio_reg.h
+9 -14
View File
@@ -22,7 +22,7 @@
#define REG_AUDIO_AHB_BASE 0x120000
#define REG_CODEC_BASE_ADDR 0x120200
#define REG_AUDIO_APB_BASE 0x140500
#define reg_fifo_buf_adr(i) REG_AUDIO_AHB_BASE + (i)*0x40
#define reg_fifo_buf_adr(i) (REG_AUDIO_AHB_BASE + (i)*0x40)
#define reg_audio_en REG_ADDR8(REG_AUDIO_APB_BASE + 0x00)
enum {
FLD_AUDIO_I2S_CLK_EN = BIT(0),
@@ -85,7 +85,6 @@ enum {
FLD_AUDIO_TX_RPTR_PTR_EN = BIT(1),
FLD_AUDIO_RX_WPTR_PTR_EN = BIT(2),
FLD_AUDIO_RX_RPTR_PTR_EN = BIT(3),
};
enum {
@@ -110,17 +109,17 @@ enum {
#define reg_rx_max REG_ADDR16(REG_AUDIO_APB_BASE + 0x2e)
#define reg_th0_h1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x30) //tx
#define reg_th0_l1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x32) //tx
#define reg_th0_h1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x30) // tx
#define reg_th0_l1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x32) // tx
#define reg_th0_h2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x38) //tx
#define reg_th0_l2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x3a) //tx
#define reg_th0_h2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x38) // tx
#define reg_th0_l2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x3a) // tx
#define reg_th1_h1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x40) //rx
#define reg_th1_l1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x42) //rx
#define reg_th1_h1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x40) // rx
#define reg_th1_l1 REG_ADDR16(REG_AUDIO_APB_BASE + 0x42) // rx
#define reg_th1_h2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x48) //rx
#define reg_th1_l2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x4a) //rx
#define reg_th1_h2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x48) // rx
#define reg_th1_l2 REG_ADDR16(REG_AUDIO_APB_BASE + 0x4a) // rx
#define reg_irq_fifo_state REG_ADDR8(REG_AUDIO_APB_BASE + 0x5c)
typedef enum {
@@ -133,7 +132,6 @@ typedef enum {
FLD_AUDIO_IRQ_RXFIFO_H_L1 = BIT(5),
FLD_AUDIO_IRQ_RXFIFO_L_L2 = BIT(6),
FLD_AUDIO_IRQ_RXFIFO_H_L2 = BIT(7),
} audio_fifo_irq_status_type_e;
#define reg_irq_fifo_mask REG_ADDR8(REG_AUDIO_APB_BASE + 0x5d)
@@ -148,7 +146,6 @@ typedef enum {
FLD_AUDIO_IRQ_RXFIFO_H_L1_EN = BIT(5),
FLD_AUDIO_IRQ_RXFIFO_L_L2_EN = BIT(6),
FLD_AUDIO_IRQ_RXFIFO_H_L2_EN = BIT(7),
} audio_fifo_irq_mask_type_e;
#define reg_irq_manual_en REG_ADDR8(REG_AUDIO_APB_BASE + 0x5e)
@@ -162,7 +159,6 @@ enum {
FLD_AUDIO_IRQ_RXFIFO_H_L1_MAN_EN = BIT(5),
FLD_AUDIO_IRQ_RXFIFO_L_L2_MAN_EN = BIT(6),
FLD_AUDIO_IRQ_RXFIFO_H_L2_MAN_EN = BIT(7)
};
#define reg_int_pcm_num REG_ADDR16(REG_AUDIO_APB_BASE + 0x50)
@@ -309,7 +305,6 @@ enum {
#define reg_audio_adc2_gain REG_ADDR8(REG_CODEC_BASE_ADDR + (0x2d << 2))
enum {
FLD_AUDIO_CODEC_ADC_GID2 = BIT_RNG(0, 5),
};
#endif
b91/b91_ble_sdk/drivers/B91/reg_include/dma_reg.h
+3 -8
View File
@@ -17,18 +17,13 @@
*****************************************************************************/
#ifndef DMA_REG_H
#define DMA_REG_H
#include "../sys.h"
/******************************* dma registers: 0x100400 ******************************/
#define reg_dma_id REG_ADDR32(0x100400)
#define reg_dma_cfg REG_ADDR32(0x100410)
//enum{
// FLD_DMA_CHANNEL_NUM = BIT_RNG(0,3),
// FLD_DMA_FIFO_DEPTH = BIT_RNG(4,9),
// FLD_DMA_REQ_NUM = BIT_RNG(10,14),
// FLD_DMA_REQ_SYNC = BIT(30),
// FLD_DMA_CHANINXFR = BIT(31),
//};
//in C99, FLD_DMA_CHANINXFR = BIT(31) is error
#define FLD_DMA_CHANNEL_NUM = BIT_RNG(0, 3),
#define FLD_DMA_FIFO_DEPTH = BIT_RNG(4, 9),
#define FLD_DMA_REQ_NUM = BIT_RNG(10, 14),
b91/b91_ble_sdk/drivers/B91/reg_include/gpio_reg.h
+19 -19
View File
@@ -19,7 +19,7 @@
#define GPIO_REG_H_
#include "../sys.h"
/******************************* gpio registers: 0x140300 ******************************/
//PA
// PA
#define reg_gpio_pa_setting1 REG_ADDR32(0x140300)
#define reg_gpio_pa_in REG_ADDR8(0x140300)
#define reg_gpio_pa_ie REG_ADDR8(0x140301)
@@ -36,7 +36,7 @@
#define reg_gpio_pa_fuc_l REG_ADDR8(0x140330)
#define reg_gpio_pa_fuc_h REG_ADDR8(0x140331)
//PB
// PB
#define reg_gpio_pb_setting1 REG_ADDR32(0x140308)
#define reg_gpio_pb_in REG_ADDR8(0x140308)
#define reg_gpio_pb_ie REG_ADDR8(0x140309)
@@ -53,7 +53,7 @@
#define reg_gpio_pb_fuc_l REG_ADDR8(0x140332)
#define reg_gpio_pb_fuc_h REG_ADDR8(0x140333)
//PC
// PC
#define reg_gpio_pc_setting1 REG_ADDR32(0x140310)
#define reg_gpio_pc_in REG_ADDR8(0x140310)
#define areg_gpio_pc_ie 0xbd
@@ -71,7 +71,7 @@
#define reg_gpio_pc_fuc_l REG_ADDR8(0x140334)
#define reg_gpio_pc_fuc_h REG_ADDR8(0x140335)
//PD
// PD
#define reg_gpio_pd_setting1 REG_ADDR32(0x140318)
#define reg_gpio_pd_in REG_ADDR8(0x140318)
#define areg_gpio_pd_ie 0xc0
@@ -86,10 +86,10 @@
#define reg_gpio_pd_irq_en REG_ADDR8(0x14031f)
#define reg_gpio_pd_fs REG_ADDR16(0x140336)
#define reg_gpio_pd_fuc_l REG_ADDR8(0x140336) //default 0xf0
#define reg_gpio_pd_fuc_l REG_ADDR8(0x140336) // default 0xf0
#define reg_gpio_pd_fuc_h REG_ADDR8(0x140337)
//PE
// PE
#define reg_gpio_pe_setting1 REG_ADDR32(0x140320)
#define reg_gpio_pe_in REG_ADDR8(0x140320)
#define reg_gpio_pe_ie REG_ADDR8(0x140321)
@@ -106,7 +106,7 @@
#define reg_gpio_pe_fuc_l REG_ADDR8(0x140350)
#define reg_gpio_pe_fuc_h REG_ADDR8(0x140351)
//PF
// PF
#define reg_gpio_pf_setting1 REG_ADDR32(0x140328)
#define reg_gpio_pf_in REG_ADDR8(0x140328)
#define reg_gpio_pf_ie REG_ADDR8(0x140329)
@@ -121,19 +121,20 @@
#define reg_gpio_pf_fuc_l REG_ADDR8(0x140356)
#define reg_gpio_pf_fuc_h REG_ADDR8(0x140357)
#define reg_gpio_in(i) REG_ADDR8(0x140300 + ((i >> 8) << 3))
#define reg_gpio_ie(i) REG_ADDR8(0x140301 + ((i >> 8) << 3))
#define reg_gpio_oen(i) REG_ADDR8(0x140302 + ((i >> 8) << 3))
#define reg_gpio_out(i) REG_ADDR8(0x140303 + ((i >> 8) << 3))
#define reg_gpio_pol(i) REG_ADDR8(0x140304 + ((i >> 8) << 3))
#define reg_gpio_ds(i) REG_ADDR8(0x140305 + ((i >> 8) << 3))
#define reg_gpio_in(i) REG_ADDR8(0x140300 + (((i) >> 8) << 3))
#define reg_gpio_ie(i) REG_ADDR8(0x140301 + (((i) >> 8) << 3))
#define reg_gpio_oen(i) REG_ADDR8(0x140302 + (((i) >> 8) << 3))
#define reg_gpio_out(i) REG_ADDR8(0x140303 + (((i) >> 8) << 3))
#define reg_gpio_pol(i) REG_ADDR8(0x140304 + (((i) >> 8) << 3))
#define reg_gpio_ds(i) REG_ADDR8(0x140305 + (((i) >> 8) << 3))
#define reg_gpio_func(i) REG_ADDR8(0x140306 + ((i >> 8) << 3))
#define reg_gpio_irq_en(i) REG_ADDR8(0x140307 + ((i >> 8) << 3)) // reg_irq_mask: FLD_IRQ_GPIO_EN
#define reg_gpio_irq_risc0_en(i) REG_ADDR8(0x140338 + (i >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_RISC0_EN
#define reg_gpio_irq_risc1_en(i) REG_ADDR8(0x140340 + (i >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_RISC1_EN
#define reg_gpio_func(i) REG_ADDR8(0x140306 + (((i) >> 8) << 3))
#define reg_gpio_irq_en(i) REG_ADDR8(0x140307 + (((i) >> 8) << 3)) // reg_irq_mask: FLD_IRQ_GPIO_EN
#define reg_gpio_irq_risc0_en(i) REG_ADDR8(0x140338 + ((i) >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_RISC0_EN
#define reg_gpio_irq_risc1_en(i) REG_ADDR8(0x140340 + ((i) >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_RISC1_EN
#define reg_gpio_func_mux(i) REG_ADDR8(0x140330 + (((i >> 8) > 3) ? 0x20 : ((i >> 8) << 1)) + ((i & 0x0f0) ? 1 : 0))
#define reg_gpio_func_mux(i) \
REG_ADDR8(0x140330 + ((((i) >> 8) > 3) ? 0x20 : (((i) >> 8) << 1)) + (((i) & 0x0f0) ? 1 : 0))
#define reg_gpio_irq_risc_mask REG_ADDR8(0x140352)
enum {
@@ -144,7 +145,6 @@ enum {
FLD_GPIO_IRQ_LVL_GPIO = BIT(4),
FLD_GPIO_IRQ_LVL_GPIO2RISC0 = BIT(5),
FLD_GPIO_IRQ_LVL_GPIO2RISC1 = BIT(6),
};
#define reg_gpio_irq_ctrl REG_ADDR8(0x140353)
enum {
b91/b91_ble_sdk/drivers/B91/reg_include/i2c_reg.h
+16 -8
View File
@@ -113,8 +113,10 @@ enum {
/**
* This is the register that configures the i2c trigger interrupt
* BIT_RNG[0,3] to configure the interrupt trigger level of rx_status, for example BIT_RNG[0:3]=0x04,when rx 4bytes,will trigger interrupt.
* BIT_RNG[4,7] to configure the interrupt trigger level of tx_status, for example BIT_RNG[0:3]=0x04,when tx 4bytes,will trigger interrupt.
* BIT_RNG[0,3] to configure the interrupt trigger level of rx_status,
* for example BIT_RNG[0:3]=0x04,when rx 4bytes,will trigger interrupt.
* BIT_RNG[4,7] to configure the interrupt trigger level of tx_status,
* for example BIT_RNG[0:3]=0x04,when tx 4bytes,will trigger interrupt.
*/
#define reg_i2c_trig REG_ADDR8(REG_I2C_BASE + 0x05)
enum {
@@ -122,16 +124,21 @@ enum {
FLD_I2C_TX_IRQ_TRIG_LEV = BIT_RNG(4, 7),
};
//As a master, you need to configure this length for both sending and receiving, and the hardware needs to know what the length is.
// As a master, you need to configure this length for both sending and receiving,
// and the hardware needs to know what the length is.
#define reg_i2c_len REG_ADDR8(REG_I2C_BASE + 0x06)
/**
* This register is to configure the slave stretch function.
* BIT[0] slave auto stretch clk eanble,open this function, use slave to receive data,when data buffer is full, scl bus will be low to stop receive data.
* BIT[1] slave manul stretch clk enable,open this function, use slave to receive data,when data buffer is full, scl bus will be low to stop receive data.
* BIT[0] slave auto stretch clk eanble,open this function, use slave to receive data,
* when data buffer is full, scl bus will be low to stop receive data.
* BIT[1] slave manul stretch clk enable,open this function, use slave to receive data,
* when data buffer is full, scl bus will be low to stop receive data.
* BIT[2] clear slave stretch.
* BIT[6] in high speed mode,when open slave auto stretch clk function,Suddenly data came over, to meet the requirements of time setting.
* BIT[7] in fast speed mode,when open slave auto stretch clk function,Suddenly data came over, to meet the requirements of time setting.
* BIT[6] in high speed mode,when open slave auto stretch clk function,
* Suddenly data came over, to meet the requirements of time setting.
* BIT[7] in fast speed mode,when open slave auto stretch clk function,
* Suddenly data came over, to meet the requirements of time setting.
*/
#define reg_i2c_slave_strech_en REG_ADDR8(REG_I2C_BASE + 0x07)
enum {
@@ -223,7 +230,8 @@ enum {
FLD_I2C_TX_EN = BIT(4),
};
//reg_i2c_rx_fifo_len is the number actually entered in the hardware fifo, it is an accumulated value, and fifo clear will clear.
// reg_i2c_rx_fifo_len is the number actually entered in the hardware fifo,
// it is an accumulated value, and fifo clear will clear.
#define reg_i2c_rx_fifo_len REG_ADDR8(REG_I2C_BASE + 0x0f)
enum {
FLD_I2C_RX_FIFO_LEN = BIT_RNG(0, 7),
b91/b91_ble_sdk/drivers/B91/reg_include/mdec_reg.h
-2
View File
@@ -15,8 +15,6 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef MDEC_REG_H
#define MDEC_REG_H
b91/b91_ble_sdk/drivers/B91/reg_include/mspi_reg.h
+2 -4
View File
@@ -15,8 +15,6 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef MSPI_REG_H
#define MSPI_REG_H
@@ -49,12 +47,12 @@ enum {
#define reg_mspi_set_l REG_ADDR8(0x140104)
enum {
FLD_MSPI_MULTIBOOT_ADDR_OFFSET =
BIT_RNG(0, 2), /**<mutiboot address offset option, 0:0k; 1:128k; 2:256k; 4:256k*/
BIT_RNG(0, 2), /**< mutiboot address offset option, 0:0k; 1:128k; 2:256k; 4:256k */
};
#define reg_mspi_set_h REG_ADDR8(0x140105)
enum {
FLD_MSPI_PROGRAM_SPACE_SIZE = BIT_RNG(0, 6), /**< program space size = mspi_set_h*4k*/
FLD_MSPI_PROGRAM_SPACE_SIZE = BIT_RNG(0, 6), /**< program space size = mspi_set_h*4k */
};
#define reg_mspi_xip_config REG_ADDR16(0x140106)
#define reg_mspi_cmd_ahb REG_ADDR8(0x140106)
b91/b91_ble_sdk/drivers/B91/reg_include/pke_reg.h
+4 -1
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef PKE_REG_H
#define PKE_REG_H
#include "../sys.h"
@@ -58,3 +59,5 @@ enum {
FLD_PKE_EXE_CONF_OMON = BIT(5),
FLD_PKE_EXE_CONF_ME_SCA_EN = BIT_RNG(8, 9),
};
#endif // PKE_REG_H
b91/b91_ble_sdk/drivers/B91/reg_include/pwm_reg.h
+7 -12
View File
@@ -132,10 +132,7 @@ enum {
* The lower 16 bits indicate the length of the CMP segment. The higher 16 bits indicate the length of the MAX segment.
*/
#define reg_pwm_cycle(i) REG_ADDR32(REG_PWM_BASE + 0x14 + (i << 2))
//enum{
// FLD_PWM_CMP = BIT_RNG(0,15),
// FLD_PWM_MAX = BIT_RNG(16,31),
//};
// in C99 FLD_PWM_MAX = BIT_RNG(16,31) is error
#define FLD_PWM_CMP = BIT_RNG(0, 15),
#define FLD_PWM_MAX = BIT_RNG(16, 31),
@@ -157,8 +154,8 @@ enum {
/**
* When PWM0 is in count mode or ir mode, the total number of pulse_number is set by the following two registers.
*/
#define reg_pwm0_pulse_num0 REG_ADDR8(REG_PWM_BASE + 0x2c) //0x2c[7:0]
#define reg_pwm0_pulse_num1 REG_ADDR8(REG_PWM_BASE + 0x2d) //0x2d[5:0]
#define reg_pwm0_pulse_num0 REG_ADDR8(REG_PWM_BASE + 0x2c) // 0x2c[7:0]
#define reg_pwm0_pulse_num1 REG_ADDR8(REG_PWM_BASE + 0x2d) // 0x2d[5:0]
/**
* PWM interrupt mask or interrupt status
@@ -175,7 +172,6 @@ typedef enum {
FLD_PWM5_FRAME_DONE_IRQ = BIT(7),
FLD_PWM0_IR_FIFO_IRQ = BIT(16),
} pwm_irq_e;
/**
@@ -190,7 +186,7 @@ typedef enum {
* BIT[7]:Enable pwm5 frame interrupt.
* BIT[16]:The Bit is to enable the mask_lvl(This level specifically indicates the number of bytes in the FIFO that can trigger an interrupt) interrupt.
*/
#define reg_pwm_irq_mask(i) REG_ADDR8(REG_PWM_BASE + 0x30 + i * 2)
#define reg_pwm_irq_mask(i) REG_ADDR8(REG_PWM_BASE + 0x30 + (i) * 2)
/**
* The bits in this register are used to indicate the various interrupt states of the PWM.
@@ -205,12 +201,12 @@ typedef enum {
* BIT[16]:When the FIFO value is less than the set value, an interrupt is generated(The premise is that this interrupt has been enabled by register 0x140432 previous).
* The user can know whether this interrupt is generated by reading the status of this register.If BIT(16):1 Indicates that this interrupt has been generated.
*/
#define reg_pwm_irq_sta(i) REG_ADDR8(REG_PWM_BASE + 0x31 + i * 2)
#define reg_pwm_irq_sta(i) REG_ADDR8(REG_PWM_BASE + 0x31 + (i) * 2)
/**
* This register is used to count the number of PWM5~PWM0 pulses.The number of pulses of each PWM consists of 16 bits
*/
#define reg_pwm_cnt(i) REG_ADDR16(REG_PWM_BASE + 0x34 + (i << 1))
#define reg_pwm_cnt(i) REG_ADDR16(REG_PWM_BASE + 0x34 + ((i) << 19))
/**
* PWM0 pulse_cnt value BIT[7:0].
@@ -235,7 +231,7 @@ typedef enum {
/**
* PWM data fifo.0x140448~0x14044b.
*/
#define reg_pwm_ir_fifo_dat(i) REG_ADDR16(REG_PWM_BASE + 0x48 + i * 2)
#define reg_pwm_ir_fifo_dat(i) REG_ADDR16(REG_PWM_BASE + 0x48 + (i) * 2)
/**
* This register BIT[3:0] indicates the interrupt trigger level in ir_fifo mode.
@@ -266,7 +262,6 @@ enum {
#define reg_pwm_ir_clr_fifo_data REG_ADDR8(0x14044e)
enum {
FLD_PWM0_IR_FIFO_CLR_DATA = BIT(0),
};
#endif
b91/b91_ble_sdk/drivers/B91/reg_include/rf_reg.h
+8 -58
View File
@@ -21,9 +21,9 @@
///******************************* RF ******************************/
#define APBADDR 0x140000
#define BBADDR APBADDR + 0x800 //0x140800
#define RADIOADDR APBADDR + 0xe00 //0x140e00
#define MODEMADDR APBADDR + 0xc00 //0x140c00
#define BBADDR (APBADDR + 0x800) // 0x140800
#define RADIOADDR (APBADDR + 0xe00) // 0x140e00
#define MODEMADDR (APBADDR + 0xc00) // 0x140c00
#define CHNADDR 0x100400
#define APBRG_BASE 0x140000
#define APBRG_APB_BASE (APBRG_BASE + 0x0000)
@@ -46,8 +46,8 @@ enum {
#define reg_rf_dma_rx_wptr REG_ADDR8(0x001004f4)
#define reg_rf_dma_rx_rptr REG_ADDR8(0x001004f5)
#define reg_rf_dma_tx_rptr(i) REG_ADDR8(0x00100501 + (i << 1))
#define reg_rf_dma_tx_wptr(i) REG_ADDR8(0x00100500 + (i << 1))
#define reg_rf_dma_tx_rptr(i) REG_ADDR8(0x00100501 + ((i) << 1))
#define reg_rf_dma_tx_wptr(i) REG_ADDR8(0x00100500 + ((i) << 1))
#define reg_rf_bb_rx_size REG_ADDR8(CHNADDR + 0xf6)
@@ -104,7 +104,6 @@ enum {
FLD_RF_PN_AUTO = BIT(7),
};
//#define reg_rf_acclen REG_ADDR8(REG_BASEBAND_BASE_ADDR+0x05)
#define reg_rf_acc_len REG_ADDR8(REG_BASEBAND_BASE_ADDR + 0x05)
enum {
FLD_RF_ACC_LEN = BIT_RNG(0, 2),
@@ -288,50 +287,6 @@ enum {
FLD_RF_ANT_LUT1 = BIT_RNG(4, 6),
};
#if 0
#define reg_rf_ant_lut_1 REG_ADDR8(REG_BASEBAND_BASE_ADDR + 0x69)
enum{
FLD_RF_ANT_LUT0 = BIT_RNG(0,2),
FLD_RF_ANT_LUT1 = BIT_RNG(4,6),
};
#define reg_rf_ant_lut_2 REG_ADDR8(REG_BASEBAND_BASE_ADDR + 0x6a)
enum{
FLD_RF_ANT_LUT0 = BIT_RNG(0,2),
FLD_RF_ANT_LUT1 = BIT_RNG(4,6),
};
#define reg_rf_ant_lut_3 REG_ADDR8(REG_BASEBAND_BASE_ADDR + 0x6b)
enum{
FLD_RF_ANT_LUT0 = BIT_RNG(0,2),
FLD_RF_ANT_LUT1 = BIT_RNG(4,6),
};
#define reg_rf_ant_lut_4 REG_ADDR8(REG_BASEBAND_BASE_ADDR + 0x6c)
enum{
FLD_RF_ANT_LUT0 = BIT_RNG(0,2),
FLD_RF_ANT_LUT1 = BIT_RNG(4,6),
};
#define reg_rf_ant_lut_5 REG_ADDR8(REG_BASEBAND_BASE_ADDR + 0x6d)
enum{
FLD_RF_ANT_LUT0 = BIT_RNG(0,2),
FLD_RF_ANT_LUT1 = BIT_RNG(4,6),
};
#define reg_rf_ant_lut_6 REG_ADDR8(REG_BASEBAND_BASE_ADDR + 0x6e)
enum{
FLD_RF_ANT_LUT0 = BIT_RNG(0,2),
FLD_RF_ANT_LUT1 = BIT_RNG(4,6),
};
#define reg_rf_ant_lut_7 REG_ADDR8(REG_BASEBAND_BASE_ADDR + 0x6f)
enum{
FLD_RF_ANT_LUT0 = BIT_RNG(0,2),
FLD_RF_ANT_LUT1 = BIT_RNG(4,6),
};
#endif
#define reg_rf_rxdma_adr 0x140880
#define reg_rf_rxdma_fifo0 REG_ADDR8(REG_BASEBAND_BASE_ADDR + 0x80)
enum {
@@ -424,7 +379,7 @@ enum {
FLD_RF_RX_TIMEOUT_EN = BIT(2),
FLD_RF_CRC_2_EN = BIT(3),
//BLE mode
// BLE mode
FLD_RF_BRX_SN_INIT = BIT(4),
FLD_RF_BRX_NESN_INIT = BIT(5),
FLD_RF_BTX_SN_INIT = BIT(6),
@@ -563,7 +518,7 @@ enum {
#define reg_rf_ll_2d_sclk REG_ADDR8(REG_BB_LL_BASE_ADDR + 0x24)
typedef enum {
FLD_RF_STATE_MACHINE_IDLE = 0, /**< idle */
FLD_RF_STATE_MACHINE_TX_SETTLE, /**< tx settle*/
FLD_RF_STATE_MACHINE_TX_SETTLE, /**< tx settle */
FLD_RF_STATE_MACHINE_TX, /**< tx */
FLD_RF_STATE_MACHINE_RX_WAIT, /**< rx wait */
FLD_RF_STATE_MACHINE_RX, /**< rx */
@@ -610,7 +565,7 @@ enum {
FLD_RF_RX_PRIO = BIT(6),
};
#define CLEAR_ALL_RFIRQ_STATUS (reg_rf_irq_status = 0xffff)
#define REG_TL_MODEM_BASE_ADDR 0x140c00 //140c00
#define REG_TL_MODEM_BASE_ADDR 0x140c00 // 140c00
#define reg_rf_modem_mode_cfg_rx1_0 REG_ADDR8(REG_TL_MODEM_BASE_ADDR + 0x20)
enum {
@@ -622,7 +577,6 @@ enum {
FLD_RF_RX_DATA_CLK_DBG = BIT(5),
FLD_RF_LR_TRIG_MODE = BIT(6),
FLD_RF_FDC_DBG_SEL = BIT(7),
};
#define reg_rf_modem_mode_ctrl_tx1_0 REG_ADDR8(REG_TL_MODEM_BASE_ADDR + 0x22)
enum {
@@ -646,7 +600,6 @@ enum {
FLD_RF_TX_IQ_EN = BIT(1),
FLD_RF_TX_MPSK_EN = BIT(2),
FLD_RF_TX_TP_ALIGN = BIT(3),
};
#define reg_rf_mode_cfg_rx1_0 REG_ADDR8(REG_TL_RADIO_BASE_ADDR + 0x20)
@@ -660,7 +613,6 @@ enum {
FLD_RF_MODE_VANT_RX = BIT(1),
FLD_RF_FE_RTRIM_RX = BIT_RNG(2, 4),
FLD_RF_IF_FREQ = BIT_RNG(5, 6),
};
#define reg_rf_mode_cfg_tx1_0 REG_ADDR8(REG_TL_RADIO_BASE_ADDR + 0x22)
@@ -674,7 +626,6 @@ enum {
enum {
FLD_RF_HPMC_EXP_DIFF_COUNT_H = BIT_RNG(0, 4),
FLD_RF_DAC_TRIM_CFBK = BIT_RNG(5, 6),
};
#define reg_rf_mode_cfg_txrx_0 REG_ADDR8(REG_TL_RADIO_BASE_ADDR + 0x26)
@@ -721,7 +672,6 @@ enum {
FLD_RF_BT_BLE_SEL_EN = BIT(3),
FLD_RF_TXC_PWR_SRL = BIT(4),
FLD_RF_BW_CODE_BLE = BIT_RNG(5, 7),
};
#define reg_rf_txrx_dbg3_0 REG_ADDR8(REG_TL_RADIO_BASE_ADDR + 0x44)
b91/b91_ble_sdk/drivers/B91/reg_include/soc.h
+9 -7
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef SOC_H
#define SOC_H
#include "../sys.h"
@@ -37,19 +38,19 @@ enum {
FLD_RST0_UART0 = BIT(2),
FLD_RST0_USB = BIT(3),
FLD_RST0_PWM = BIT(4),
//RSVD
// RSVD
FLD_RST0_UART1 = BIT(6),
FLD_RST0_SWIRE = BIT(7),
};
#define reg_rst1 REG_ADDR8(0x1401e1)
enum {
//RSVD
// RSVD
FLD_RST1_SYS_STIMER = BIT(1),
FLD_RST1_DMA = BIT(2),
FLD_RST1_ALGM = BIT(3),
FLD_RST1_PKE = BIT(4),
//RSVD
// RSVD
FLD_RST1_PSPI = BIT(6),
FLD_RST1_SPISLV = BIT(7),
};
@@ -59,11 +60,11 @@ enum {
FLD_RST2_TIMER = BIT(0),
FLD_RST2_AUD = BIT(1),
FLD_RST2_TRNG = BIT(2),
//RSVD
// RSVD
FLD_RST2_MCU = BIT(4),
FLD_RST2_LM = BIT(5),
FLD_RST2_NPE = BIT(6),
//RSVD
// RSVD
};
#define reg_rst3 REG_ADDR8(0x1401e3)
@@ -99,7 +100,6 @@ enum {
FLD_CLK1_MACHINETIME_EN = BIT(5),
FLD_CLK1_PSPI_EN = BIT(6),
FLD_CLK1_SPISLV_EN = BIT(7),
};
#define reg_clk_en2 REG_ADDR8(0x1401e6)
@@ -167,3 +167,5 @@ typedef enum {
FLD_WKUP_MDEC = BIT(4),
FLD_MDEC_RSVD = BIT_RNG(5, 7),
} wakeup_status_e;
#endif // SOC_H
b91/b91_ble_sdk/drivers/B91/reg_include/spi_reg.h
+5 -7
View File
@@ -28,7 +28,7 @@
#define reg_hspi_data_buf_adr 0x1FFFFC8
#define reg_hspi_xip_base_adr 0x1000000
#define reg_spi_data_buf_adr(i) 0x140048 + (i)*BASE_ADDR_DIFF
#define reg_spi_data_buf_adr(i) (0x140048 + (i)*BASE_ADDR_DIFF)
/**
* BIT[0:1] the minimum time between the edge of SPI_CS and the edges of SPI_CLK.the actual duration is (SPI_CLK_OUT/2)*(cs2sclk+1).master only
* BIT[2] set 3line mode ,MOSI is bi-directional signal in regular mode.master only
@@ -52,11 +52,10 @@ enum {
FLD_SPI_MASTER_MODE = BIT(7),
};
/*the clock freq ratio between the source_clock and spi_clock.master only
/* the clock freq ratio between the source_clock and spi_clock.master only
* spi_clock=source_clock/((spi_clk_div+1)*2)
* spi_clk_div=reg_hspi_mode1[7:0]. max_value=0xff,spi_clock==source_clock
*/
//#define reg_hspi_mode1 REG_ADDR8(HSPI_BASE_ADDR+0x01)
#define reg_spi_mode1(i) REG_ADDR8(PSPI_BASE_ADDR + 0x01 + (i)*BASE_ADDR_DIFF)
/**
@@ -85,7 +84,6 @@ enum {
*/
#define reg_spi_tx_cnt1(i) REG_ADDR8(PSPI_BASE_ADDR + 0x12 + (i) * (BASE_ADDR_DIFF - 0x12 + 0x20))
//#define reg_hspi_tx_cnt1 REG_ADDR8(HSPI_BASE_ADDR+0x20)
/**
* BIT[0:7] transfer count2 for write data.master only
*/
@@ -138,8 +136,8 @@ enum {
#define reg_spi_trans1(i) REG_ADDR8(PSPI_BASE_ADDR + 0x06 + (i)*BASE_ADDR_DIFF)
enum {
FLD_SPI_CMD_RESERVED = BIT(0),
FLD_SPI_CMD_TRANS_HWORD = BIT(1), //1 apb hword transfer
FLD_SPI_CMD_TRANS_WORD = BIT(2), //1 apb word transfer
FLD_SPI_CMD_TRANS_HWORD = BIT(1), // 1 apb hword transfer
FLD_SPI_CMD_TRANS_WORD = BIT(2), // 1 apb word transfer
FLD_SPI_CMD_RD_DUMMY_4CYCLE = BIT(3), // 0 8cycle 1 4cycle
FLD_SPI_CMD_ADDR_AUTO_INCREASE = BIT(4), // 0 AUTO incease
FLD_SPI_CMD_DATA_DUAL = BIT(5), // 0 Single 1 DuaL
@@ -279,7 +277,7 @@ enum {
*/
#define reg_hspi_addr3 REG_ADDR8(HSPI_BASE_ADDR + 0x13)
#define reg_hspi_addr(i) REG_ADDR8(HSPI_BASE_ADDR + 0x10 + i)
#define reg_hspi_addr(i) REG_ADDR8(HSPI_BASE_ADDR + 0x10 + (i))
/** hspi_addr0~ hspi_addr3.
*/
b91/b91_ble_sdk/drivers/B91/reg_include/stimer_reg.h
-4
View File
@@ -45,20 +45,17 @@ enum {
FLD_SYSTEM_TIMER_AUTO = BIT(2),
FLD_SYSTEM_32K_TRACK_EN = BIT(3),
FLD_SYSTEM_32K_CAL_MODE = BIT_RNG(4, 7),
};
#define reg_system_st REG_ADDR8(STIMER_BASE_ADDR + 0xb)
enum {
FLD_SYSTEM_CMD_STOP = BIT(1),
FLD_SYSTEM_CMD_SYNC = BIT(3),
FLD_SYSTEM_CLK_32K = BIT(4),
FLD_SYSTEM_CLR_RD_DONE = BIT(5),
FLD_SYSTEM_RD_BUSY = BIT(6),
FLD_SYSTEM_CMD_SET_DLY_DONE = BIT(7),
};
#define reg_system_timer_set_32k REG_ADDR32(STIMER_BASE_ADDR + 0xc)
@@ -69,7 +66,6 @@ enum {
#define reg_system_up_32k REG_ADDR32(STIMER_BASE_ADDR + 0x18)
enum {
FLD_SYSTEM_UPDATE_UPON_32K = BIT(0),
FLD_SYSTEM_RUN_UPON_NXT_32K = BIT(1),
};
b91/b91_ble_sdk/drivers/B91/reg_include/uart_reg.h
+12 -12
View File
@@ -21,12 +21,12 @@
/******************************* uart0 registers: 0x140080 *******************************/
/******************************* uart1 registers: 0x1400c0 ******************************/
#define reg_uart_data_buf_adr(i) (0x140080 + (i)*0x40) //uart(i)
#define reg_uart_data_buf_adr(i) (0x140080 + (i)*0x40) // uart(i)
#define reg_uart_data_buf(i, j) REG_ADDR8(reg_uart_data_buf_adr(i) + (j)) //uart(i)_buf(j)
#define reg_uart_data_buf(i, j) REG_ADDR8(reg_uart_data_buf_adr(i) + (j)) // uart(i)_buf(j)
#define reg_uart_data_hword_buf(i, j) REG_ADDR16(reg_uart_data_buf_adr(i) + (j)*2)
#define reg_uart_data_word_buf(i) REG_ADDR32(reg_uart_data_buf_adr(i)) //uart(i)
#define reg_uart_data_word_buf(i) REG_ADDR32(reg_uart_data_buf_adr(i)) // uart(i)
#define reg_uart_clk_div(i) REG_ADDR16(0x140084 + (i)*0x40)
@@ -42,7 +42,7 @@ enum {
FLD_UART_TX_CTS_POLARITY = BIT(0),
FLD_UART_TX_CTS_ENABLE = BIT(1),
FLD_UART_PARITY_ENABLE = BIT(2),
FLD_UART_PARITY_POLARITY = BIT(3), //1:odd parity 0:even parity
FLD_UART_PARITY_POLARITY = BIT(3), // 1:odd parity 0:even parity
FLD_UART_STOP_SEL = BIT_RNG(4, 5),
FLD_UART_TTL_ENABLE = BIT(6),
FLD_UART_LOOPBACK_O = BIT(7),
@@ -76,7 +76,7 @@ enum {
enum {
FLD_UART_TIMEOUT_MUL = BIT_RNG(0, 1),
FLD_UART_MARK_RXDONE = BIT(2),
//rsvd BIT(4)
// rsvd BIT(4)
FLD_UART_P7816_EN = BIT(5),
FLD_UART_MASK_TXDONE = BIT(6),
FLD_UART_MASK_ERR_IRQ = BIT(7),
@@ -92,24 +92,24 @@ enum {
enum {
FLD_UART_RBCNT = BIT_RNG(0, 2),
FLD_UART_IRQ_O = BIT(3),
FLD_UART_WBCNT = BIT_RNG(4, 6), //R
FLD_UART_CLEAR_RX = BIT(6), //Write 1 clear RX
FLD_UART_RX_ERR = BIT(7), //R
FLD_UART_CLEAR_TX = BIT(7), //Write 1 clear TX
FLD_UART_WBCNT = BIT_RNG(4, 6), // R
FLD_UART_CLEAR_RX = BIT(6), // Write 1 clear RX
FLD_UART_RX_ERR = BIT(7), // R
FLD_UART_CLEAR_TX = BIT(7), // Write 1 clear TX
};
#define reg_uart_status2(i) REG_ADDR8((0x14008e) + (0x40 * (i)))
enum {
FLD_UART_TX_DONE = BIT(0), //only for dma default 1.
FLD_UART_TX_DONE = BIT(0), // only for dma default 1.
FLD_UART_TX_BUF_IRQ = BIT(1),
FLD_UART_RX_DONE = BIT(2),
FLD_UART_RX_BUF_IRQ = BIT(3),
};
//state machine use for IC debug
// state machine use for IC debug
#define reg_uart_state(i) REG_ADDR8(0x14008f + 0x40 * (i))
enum {
FLD_UART_TSTATE_i = BIT_RNG(0, 2), //only for dma default 1.
FLD_UART_TSTATE_i = BIT_RNG(0, 2), // only for dma default 1.
FLD_UART_RSTATE_i = BIT_RNG(4, 7),
};
b91/b91_ble_sdk/drivers/B91/rf.h
+44 -42
View File
@@ -41,18 +41,18 @@
/**
* @brief According to the packet format find the information of packet through offset.
*/
#define rf_ble_dma_rx_offset_crc24(p) (p[RF_BLE_DMA_RFRX_OFFSET_RFLEN] + 6) //data len:3
#define rf_ble_dma_rx_offset_time_stamp(p) (p[RF_BLE_DMA_RFRX_OFFSET_RFLEN] + 9) //data len:4
#define rf_ble_dma_rx_offset_freq_offset(p) (p[RF_BLE_DMA_RFRX_OFFSET_RFLEN] + 13) //data len:2
#define rf_ble_dma_rx_offset_rssi(p) (p[RF_BLE_DMA_RFRX_OFFSET_RFLEN] + 15) //data len:1, signed
#define rf_ble_packet_length_ok(p) (p[5] <= reg_rf_rxtmaxlen) //dma_len must 4 byte aligned
#define rf_ble_packet_crc_ok(p) ((p[(p[5] + 5 + 11)] & 0x01) == 0x0)
#define rf_ble_dma_rx_offset_crc24(p) ((p)[RF_BLE_DMA_RFRX_OFFSET_RFLEN] + 6) // data len:3
#define rf_ble_dma_rx_offset_time_stamp(p) ((p)[RF_BLE_DMA_RFRX_OFFSET_RFLEN] + 9) // data len:4
#define rf_ble_dma_rx_offset_freq_offset(p) ((p)[RF_BLE_DMA_RFRX_OFFSET_RFLEN] + 13) // data len:2
#define rf_ble_dma_rx_offset_rssi(p) ((p)[RF_BLE_DMA_RFRX_OFFSET_RFLEN] + 15) // data len:1, signed
#define rf_ble_packet_length_ok(p) ((p)[5] <= reg_rf_rxtmaxlen) // dma_len must 4 byte aligned
#define rf_ble_packet_crc_ok(p) (((p)[((p)[5] + 5 + 11)] & 0x01) == 0x0)
/**
* @brief This define for ble debug the effect of rx_dly.
* when this function turn on the time of rx_dly will shorten 6.3us,
*/
#define RF_RX_SHORT_MODE_EN 1 //In order to debug whether the problem is caused by rx_dly.
#define RF_RX_SHORT_MODE_EN 1 // In order to debug whether the problem is caused by rx_dly.
/******************************************************FOR ESB************************************************************/
@@ -65,11 +65,11 @@
* @brief According to the packet format find the information of packet through offset.
*/
#define rf_pri_esb_dma_rx_offset_crc(p) (p[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN] + 5) //data len:2
#define rf_pri_esb_dma_rx_offset_time_stamp(p) (p[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN] + 7) //data len:4
#define rf_pri_esb_dma_rx_offset_freq_offset(p) (p[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN] + 11) //data len:2
#define rf_pri_esb_dma_rx_offset_rssi(p) (p[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN] + 13) //data len:1, signed
#define rf_pri_esb_packet_crc_ok(p) ((p[((p[4] & 0x3f) + 11 + 3)] & 0x01) == 0x00)
#define rf_pri_esb_dma_rx_offset_crc(p) ((p)[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN] + 5) // data len:2
#define rf_pri_esb_dma_rx_offset_time_stamp(p) ((p)[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN] + 7) // data len:4
#define rf_pri_esb_dma_rx_offset_freq_offset(p) ((p)[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN] + 11) // data len:2
#define rf_pri_esb_dma_rx_offset_rssi(p) ((p)[RF_PRI_ESB_DMA_RFRX_OFFSET_RFLEN] + 13) // data len:1, signed
#define rf_pri_esb_packet_crc_ok(p) (((p)[(((p)[4] & 0x3f) + 11 + 3)] & 0x01) == 0x00)
/******************************************************FOR ZIGBEE************************************************************/
@@ -83,20 +83,20 @@
* @brief According to the packet format find the information of packet through offset.
*/
#define rf_zigbee_dma_rx_offset_crc(p) (p[RF_ZIGBEE_DMA_RFRX_OFFSET_RFLEN] + 3) //data len:2
#define rf_zigbee_dma_rx_offset_time_stamp(p) (p[RF_ZIGBEE_DMA_RFRX_OFFSET_RFLEN] + 5) //data len:4
#define rf_zigbee_dma_rx_offset_freq_offset(p) (p[RF_ZIGBEE_DMA_RFRX_OFFSET_RFLEN] + 9) //data len:2
#define rf_zigbee_dma_rx_offset_rssi(p) (p[RF_ZIGBEE_DMA_RFRX_OFFSET_RFLEN] + 11) //data len:1, signed
#define rf_zigbee_packet_crc_ok(p) ((p[(p[4] + 9 + 3)] & 0x51) == 0x0)
#define rf_zigbee_get_payload_len(p) (p[4])
#define rf_zigbee_dma_rx_offset_crc(p) ((p)[RF_ZIGBEE_DMA_RFRX_OFFSET_RFLEN] + 3) // data len:2
#define rf_zigbee_dma_rx_offset_time_stamp(p) ((p)[RF_ZIGBEE_DMA_RFRX_OFFSET_RFLEN] + 5) // data len:4
#define rf_zigbee_dma_rx_offset_freq_offset(p) ((p)[RF_ZIGBEE_DMA_RFRX_OFFSET_RFLEN] + 9) // data len:2
#define rf_zigbee_dma_rx_offset_rssi(p) ((p)[RF_ZIGBEE_DMA_RFRX_OFFSET_RFLEN] + 11) // data len:1, signed
#define rf_zigbee_packet_crc_ok(p) (((p)[((p)[4] + 9 + 3)] & 0x51) == 0x0)
#define rf_zigbee_get_payload_len(p) ((p)[4])
#define rf_zigbee_packet_length_ok(p) (1)
/**
* @brief According to different packet format find the crc check digit.
*/
#define rf_pri_sb_packet_crc_ok(p) ((p[(reg_rf_sblen & 0x3f) + 4 + 9] & 0x01) == 0x00)
#define rf_hybee_packet_crc_ok(p) ((p[(p[4] + 9 + 3)] & 0x51) == 0x0)
#define rf_pri_sb_packet_crc_ok(p) (((p)[(reg_rf_sblen & 0x3f) + 4 + 9] & 0x01) == 0x00)
#define rf_hybee_packet_crc_ok(p) (((p)[(p[4] + 9 + 3)] & 0x51) == 0x0)
#define rf_ant_packet_crc_ok(p) ((p[(reg_rf_sblen & 0x3f) + 4 + 9] & 0x01) == 0x00)
#define rf_ant_packet_crc_ok(p) (((p)[(reg_rf_sblen & 0x3f) + 4 + 9] & 0x01) == 0x00)
/**********************************************************************************************************************
* RF global data type *
@@ -133,14 +133,14 @@ typedef enum {
* @brief Define power list of RF.
*/
typedef enum {
/*VBAT*/
/* VBAT */
RF_POWER_P9p11dBm = 63, /**< 9.1 dbm */
RF_POWER_P8p57dBm = 45, /**< 8.6 dbm */
RF_POWER_P8p05dBm = 35, /**< 8.1 dbm */
RF_POWER_P7p45dBm = 27, /**< 7.5 dbm */
RF_POWER_P6p98dBm = 23, /**< 7.0 dbm */
RF_POWER_P5p68dBm = 18, /**< 6.0 dbm */
/*VANT*/
/* VANT */
RF_POWER_P4p35dBm = BIT(7) | 63, /**< 4.4 dbm */
RF_POWER_P3p83dBm = BIT(7) | 50, /**< 3.8 dbm */
RF_POWER_P3p25dBm = BIT(7) | 41, /**< 3.3 dbm */
@@ -162,21 +162,20 @@ typedef enum {
RF_POWER_N30dBm = 0xff, /**< -30 dbm */
RF_POWER_N50dBm = BIT(7) | 0, /**< -50 dbm */
} rf_power_level_e;
/**
* @brief Define power index list of RF.
*/
typedef enum {
/*VBAT*/
/* VBAT */
RF_POWER_INDEX_P9p11dBm, /**< power index of 9.1 dbm */
RF_POWER_INDEX_P8p57dBm, /**< power index of 8.6 dbm */
RF_POWER_INDEX_P8p05dBm, /**< power index of 8.1 dbm */
RF_POWER_INDEX_P7p45dBm, /**< power index of 7.5 dbm */
RF_POWER_INDEX_P6p98dBm, /**< power index of 7.0 dbm */
RF_POWER_INDEX_P5p68dBm, /**< power index of 6.0 dbm */
/*VANT*/
/* VANT */
RF_POWER_INDEX_P4p35dBm, /**< power index of 4.4 dbm */
RF_POWER_INDEX_P3p83dBm, /**< power index of 3.8 dbm */
RF_POWER_INDEX_P3p25dBm, /**< power index of 3.3 dbm */
@@ -228,7 +227,7 @@ typedef enum {
RF_CHANNEL_3 = BIT(3), /**< RF channel 3 */
RF_CHANNEL_4 = BIT(4), /**< RF channel 4 */
RF_CHANNEL_5 = BIT(5), /**< RF channel 5 */
RF_CHANNEL_NONE = 0x00, /**< none RF channel*/
RF_CHANNEL_NONE = 0x00, /**< none RF channel */
RF_CHANNEL_ALL = 0x0f, /**< all RF channel */
} rf_channel_e;
@@ -248,7 +247,8 @@ extern const rf_power_level_e rf_power_Level_list[30];
*/
static inline unsigned char rf_receiving_flag(void)
{
//if the value of [2:0] of the reg_0x140840 isn't 0 , it means that the RF is in the receiving packet phase.(confirmed by junwen).
// if the value of [2:0] of the reg_0x140840 isn't 0 ,
// it means that the RF is in the receiving packet phase.(confirmed by junwen).
return ((read_reg8(0x140840) & 0x07) > 1);
}
@@ -293,12 +293,12 @@ static inline unsigned short rf_get_irq_status(rf_irq_e status)
}
/**
*@brief This function serves to clear the Tx/Rx finish flag bit.
* @brief This function serves to clear the Tx/Rx finish flag bit.
* After all packet data are sent, corresponding Tx finish flag bit
* will be set as 1.By reading this flag bit, it can check whether
* packet transmission is finished. After the check, it is needed to
* manually clear this flag bit so as to avoid misjudgment.
*@return none.
* @return none.
*/
static inline void rf_clr_irq_status(rf_irq_e status)
{
@@ -324,7 +324,7 @@ static inline void rf_tx_settle_us(unsigned short txstl_us)
static inline void rf_access_code_comm(unsigned int acc)
{
reg_rf_access_code = acc;
//The following two lines of code are for trigger access code in S2,S8 mode.It has no effect on other modes.
// The following two lines of code are for trigger access code in S2,S8 mode.It has no effect on other modes.
write_reg8(0x140c25, read_reg8(0x140c25) | 0x01);
}
@@ -340,7 +340,7 @@ static inline void rf_access_code_comm(unsigned int acc)
*/
static inline void rf_rx_acc_code_pipe_en(rf_channel_e pipe)
{
write_reg8(0x140c4d, (read_reg8(0x140c4d) & 0xc0) | pipe); //rx_access_code_chn_en
write_reg8(0x140c4d, (read_reg8(0x140c4d) & 0xc0) | pipe); // rx_access_code_chn_en
}
/**
@@ -355,7 +355,7 @@ static inline void rf_rx_acc_code_pipe_en(rf_channel_e pipe)
*/
static inline void rf_tx_acc_code_pipe_en(rf_channel_e pipe)
{
write_reg8(0x140a15, (read_reg8(0x140a15) & 0xf8) | pipe); //Tx_Channel_man[2:0]
write_reg8(0x140a15, (read_reg8(0x140a15) & 0xf8) | pipe); // Tx_Channel_man[2:0]
}
/**
@@ -424,8 +424,9 @@ static inline void rf_set_rx_dma_fifo_size(unsigned short fifo_byte_size)
*/
static inline void rf_set_rx_dma_fifo_num(unsigned char fifo_num)
{
reg_rf_rx_wptr_mask =
fifo_num; //rx_wptr_real=rx_wptr & mask:After receiving 4 packets,the address returns to original address.mask value must in (0x01,0x03,0x07,0x0f).
// rx_wptr_real=rx_wptr & mask:After receiving 4 packets,the address returns to original address.
// mask value must in (0x01,0x03,0x07,0x0f).
reg_rf_rx_wptr_mask = fifo_num;
}
/**
@@ -448,7 +449,7 @@ static inline void rf_set_rx_buffer(unsigned char *rx_addr)
*/
static inline void rf_set_tx_dma_fifo_num(unsigned char fifo_num)
{
reg_rf_bb_tx_chn_dep = fifo_num; //tx_chn_dep = 2^2 =4 (have 4 fifo)
reg_rf_bb_tx_chn_dep = fifo_num; // tx_chn_dep = 2^2 =4 (have 4 fifo)
}
/**
@@ -458,9 +459,10 @@ static inline void rf_set_tx_dma_fifo_num(unsigned char fifo_num)
*/
static inline void rf_set_tx_dma_fifo_size(unsigned short fifo_byte_size)
{
reg_rf_bb_tx_size =
fifo_byte_size >>
4; //tx_idx_addr = {tx_chn_adr*bb_tx_size,4'b0}// in this setting the max data in one dma buffer is 0x20<<4.And the The product of fifo_dep and bytesize cannot exceed 0xfff.
// tx_idx_addr = {tx_chn_adr*bb_tx_size,4'b0}
// in this setting the max data in one dma buffer is 0x20<<4.
// And the The product of fifo_dep and bytesize cannot exceed 0xfff.
reg_rf_bb_tx_size = fifo_byte_size >> 4;
}
/**
* @brief This function serves to set RF tx settle time.
@@ -470,7 +472,7 @@ static inline void rf_set_tx_dma_fifo_size(unsigned short fifo_byte_size)
static inline void rf_set_tx_settle_time(unsigned short tx_stl_us)
{
tx_stl_us &= 0x0fff;
write_reg8(0x140a04, (read_reg8(0x140a04) & 0xf000) | tx_stl_us); //txxstl 112us
write_reg8(0x140a04, (read_reg8(0x140a04) & 0xf000) | tx_stl_us); // txxstl 112us
}
/**
* @brief This function serves to set RF tx settle time and rx settle time.
@@ -480,7 +482,7 @@ static inline void rf_set_tx_settle_time(unsigned short tx_stl_us)
static inline void rf_set_rx_settle_time(unsigned short rx_stl_us)
{
rx_stl_us &= 0x0fff;
write_reg8(0x140a0c, (read_reg8(0x140a0c) & 0xf000) | rx_stl_us); //rxstl 85us
write_reg8(0x140a0c, (read_reg8(0x140a0c) & 0xf000) | rx_stl_us); // rxstl 85us
}
/**
@@ -549,7 +551,7 @@ static inline unsigned char rf_get_rx_rptr(void)
*/
static inline void rf_clr_rx_rptr(void)
{
write_reg8(0x1004f5, 0x80); //clear rptr
write_reg8(0x1004f5, 0x80); // clear rptr
}
/**
b91/b91_ble_sdk/drivers/B91/s7816.c
+13 -13
View File
@@ -23,7 +23,7 @@ volatile unsigned int s7816_rst_pin;
volatile unsigned int s7816_vcc_pin;
volatile unsigned int s7816_rtx_pin;
volatile unsigned char s7816_clock;
volatile int s7816_rst_time; //us
volatile int s7816_rst_time; // us
/**
* @brief This function is used to set the s7816 clock.
* @param[in] div - set the divider of clock of 7816 module.
@@ -88,7 +88,7 @@ void s7816_init(uart_num_e uart_num, s7816_clock_e clock, int f, int d)
unsigned short div;
unsigned char bwpc;
s7816_clock = clock;
s7816_rst_time = 40000 / clock; //us
s7816_rst_time = 40000 / clock; // us
int baud = clock * 1000000 * d / f;
if (clock == S7816_4MHZ) {
@@ -101,7 +101,7 @@ void s7816_init(uart_num_e uart_num, s7816_clock_e clock, int f, int d)
uart_reset(uart_num);
uart_cal_div_and_bwpc(baud, 24 * 1000 * 1000, &div, &bwpc);
uart_init(uart_num, div, bwpc, UART_PARITY_EVEN,
UART_STOP_BIT_ONE); //7816 protocol stipulate the parity bit should be even.
UART_STOP_BIT_ONE); // 7816 protocol stipulate the parity bit should be even.
}
/**
@@ -112,7 +112,7 @@ void s7816_init(uart_num_e uart_num, s7816_clock_e clock, int f, int d)
* @param[in] trx_pin - the trx pin of s7816.
* @return none.
*/
void s7816_set_pin(gpio_pin_e rst_pin, gpio_pin_e vcc_pin, s7816_clk_pin_e clk_pin, s7816_rtx_pin_e rtx_pin)
void s7816_set_pin(gpio_pin_e rst_pin, gpio_pin_e vcc_pin, s7816_clk_pin_e clk_pin, s7816_rtx_pin_e trx_pin)
{
s7816_set_rst_pin(rst_pin);
s7816_rst_pin = rst_pin;
@@ -123,8 +123,8 @@ void s7816_set_pin(gpio_pin_e rst_pin, gpio_pin_e vcc_pin, s7816_clk_pin_e clk_p
reg_gpio_func_mux(clk_pin) = (reg_gpio_func_mux(clk_pin) & (~BIT_RNG(0, 1))) | BIT(0);
gpio_function_dis(clk_pin);
s7816_rtx_pin =
rtx_pin; //if the trx function set to early,it may trigger interrupt by accident.so we set the function in coldreset.
// if the trx function set to early,it may trigger interrupt by accident.so we set the function in coldreset.
s7816_rtx_pin = trx_pin;
}
/**
@@ -133,14 +133,14 @@ void s7816_set_pin(gpio_pin_e rst_pin, gpio_pin_e vcc_pin, s7816_clk_pin_e clk_p
* @return none.
* @note extra time is needed for initial-atr after the function.
*/
void s7816_coldreset()
void s7816_coldreset(void)
{
gpio_set_high_level(s7816_vcc_pin);
delay_us(20); //wait for the vcc stable.
reg_7816_clk_div |= BIT(7); //enable the 7816 clk,the pin is A0.
delay_us(20); // wait for the vcc stable.
reg_7816_clk_div |= BIT(7); // enable the 7816 clk,the pin is A0.
delay_us(s7816_rst_time);
s7816_set_rtx_pin(s7816_rtx_pin); // uart tx/rx pin set,if the trx pin set before this place,it may
gpio_set_high_level(s7816_rst_pin); //the IC card will return the initial ATR.
gpio_set_high_level(s7816_rst_pin); // the IC card will return the initial ATR.
}
/**
@@ -148,7 +148,7 @@ void s7816_coldreset()
* @param[in] none.
* @return none.
*/
void s7816_release_trig()
void s7816_release_trig(void)
{
gpio_set_low_level(s7816_rst_pin);
reg_7816_clk_div &= (BIT(7) - 1);
@@ -161,11 +161,11 @@ void s7816_release_trig()
* @return none.
* @note the warmreset is required after the IC-CARD active,extra time is needed for initial-atr after the function.
*/
void s7816_warmreset()
void s7816_warmreset(void)
{
gpio_set_low_level(s7816_rst_pin);
delay_us(s7816_rst_time);
gpio_set_high_level(s7816_rst_pin); //The IC card will return the initial ATR.
gpio_set_high_level(s7816_rst_pin); // The IC card will return the initial ATR.
}
/**
b91/b91_ble_sdk/drivers/B91/s7816.h
+3 -3
View File
@@ -80,7 +80,7 @@ extern void s7816_init(uart_num_e uart_num, s7816_clock_e clock, int f, int d);
* @return none.
* @note extra time is needed for initial-atr after the function.
*/
extern void s7816_coldreset();
extern void s7816_coldreset(void);
/**
* @brief This function is used to set all the pin of s7816 module.
@@ -97,7 +97,7 @@ extern void s7816_set_pin(gpio_pin_e rst_pin, gpio_pin_e vcc_pin, s7816_clk_pin_
* @param[in] none.
* @return none.
*/
extern void s7816_release_trig();
extern void s7816_release_trig(void);
/**
* @brief This function is used to set the RST pin of s7816.
@@ -119,7 +119,7 @@ extern void s7816_set_vcc_pin(gpio_pin_e pin_7816_vcc);
* @return none.
* @note the warmreset is required after the IC-CARD active,extra time is needed for initial-atr after the function.
*/
extern void s7816_warmreset();
extern void s7816_warmreset(void);
/**
* @brief This function is used to set the rst-wait time of the s7816 module.
b91/b91_ble_sdk/drivers/B91/spi.c
+58 -60
View File
@@ -25,66 +25,66 @@ static unsigned char s_pspi_tx_dma_chn;
static unsigned char s_pspi_rx_dma_chn;
dma_config_t hspi_tx_dma_config = {
.dst_req_sel = DMA_REQ_SPI_AHB_TX, //tx req
.dst_req_sel = DMA_REQ_SPI_AHB_TX, // tx req
.src_req_sel = 0,
.dst_addr_ctrl = DMA_ADDR_FIX,
.src_addr_ctrl = DMA_ADDR_INCREMENT, //increment
.dstmode = DMA_HANDSHAKE_MODE, //handshake
.src_addr_ctrl = DMA_ADDR_INCREMENT, // increment
.dstmode = DMA_HANDSHAKE_MODE, // handshake
.srcmode = DMA_NORMAL_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must word
.srcwidth = DMA_CTR_WORD_WIDTH, //must word
.src_burst_size = 0, //must 0
.dstwidth = DMA_CTR_WORD_WIDTH, // must word
.srcwidth = DMA_CTR_WORD_WIDTH, // must word
.src_burst_size = 0, // must 0
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must 0
.auto_en = 0, // must 0
};
dma_config_t hspi_rx_dma_config = {
.dst_req_sel = 0, //tx req
.dst_req_sel = 0, // tx req
.src_req_sel = DMA_REQ_SPI_AHB_RX,
.dst_addr_ctrl = DMA_ADDR_INCREMENT,
.src_addr_ctrl = DMA_ADDR_FIX,
.dstmode = DMA_NORMAL_MODE,
.srcmode = DMA_HANDSHAKE_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must word
.srcwidth = DMA_CTR_WORD_WIDTH, ////must word
.dstwidth = DMA_CTR_WORD_WIDTH, // must word
.srcwidth = DMA_CTR_WORD_WIDTH, //// must word
.src_burst_size = 0,
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must 0
.auto_en = 0, // must 0
};
dma_config_t pspi_tx_dma_config = {
.dst_req_sel = DMA_REQ_SPI_APB_TX, //tx req
.dst_req_sel = DMA_REQ_SPI_APB_TX, // tx req
.src_req_sel = 0,
.dst_addr_ctrl = DMA_ADDR_FIX,
.src_addr_ctrl = DMA_ADDR_INCREMENT, //increment
.dstmode = DMA_HANDSHAKE_MODE, //handshake
.src_addr_ctrl = DMA_ADDR_INCREMENT, // increment
.dstmode = DMA_HANDSHAKE_MODE, // handshake
.srcmode = DMA_NORMAL_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must word
.srcwidth = DMA_CTR_WORD_WIDTH, //must word
.src_burst_size = 0, //must 0
.dstwidth = DMA_CTR_WORD_WIDTH, // must word
.srcwidth = DMA_CTR_WORD_WIDTH, // must word
.src_burst_size = 0, // must 0
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must 0
.auto_en = 0, // must 0
};
dma_config_t pspi_rx_dma_config = {
.dst_req_sel = 0, //tx req
.dst_req_sel = 0, // tx req
.src_req_sel = DMA_REQ_SPI_APB_RX,
.dst_addr_ctrl = DMA_ADDR_INCREMENT,
.src_addr_ctrl = DMA_ADDR_FIX,
.dstmode = DMA_NORMAL_MODE,
.srcmode = DMA_HANDSHAKE_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must word
.srcwidth = DMA_CTR_WORD_WIDTH, ////must word
.dstwidth = DMA_CTR_WORD_WIDTH, // must word
.srcwidth = DMA_CTR_WORD_WIDTH, //// must word
.src_burst_size = 0,
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must 0
.auto_en = 0, // must 0
};
/**
@@ -101,10 +101,10 @@ void hspi_set_pin_mux(hspi_pin_def_e pin)
if ((pin == HSPI_CLK_PB4_PIN) || (pin == HSPI_CSN_PB6_PIN) || (pin == HSPI_MOSI_IO0_PB3_PIN) ||
(pin == HSPI_MISO_IO1_PB2_PIN) || (pin == HSPI_WP_IO2_PB1_PIN) || (pin == HSPI_HOLD_IO3_PB0_PIN)) {
val = 0; //function 0
val = 0; // function 0
} else if ((pin == HSPI_CLK_PA2_PIN) || (pin == HSPI_CSN_PA1_PIN) || (pin == HSPI_MOSI_IO0_PA4_PIN) ||
(pin == HSPI_MISO_IO1_PA3_PIN)) {
val = 2 << (start_bit); //function 2
val = 2 << (start_bit); // function 2
reg_gpio_pad_mul_sel |= BIT(1);
}
reg_gpio_func_mux(pin) = (reg_gpio_func_mux(pin) & mask) | val;
@@ -164,13 +164,11 @@ void pspi_set_pin_mux(pspi_pin_def_e pin)
unsigned char mask = (unsigned char)~BIT_RNG(start_bit, start_bit + 1);
if ((pin == PSPI_CLK_PC5_PIN) || (pin == PSPI_CSN_PC4_PIN) || (pin == PSPI_MOSI_IO0_PC7_PIN) ||
(pin == PSPI_MISO_IO1_PC6_PIN)) {
val = 0; //function 0
}
else if ((pin == PSPI_CLK_PB5_PIN) || (pin == PSPI_CLK_PD1_PIN) || (pin == PSPI_CSN_PC0_PIN) ||
(pin == PSPI_CSN_PD0_PIN) || (pin == PSPI_MOSI_IO0_PB7_PIN) || (pin == PSPI_MOSI_IO0_PD3_PIN) ||
(pin == PSPI_MISO_IO1_PB6_PIN) || (pin == PSPI_MISO_IO1_PD2_PIN)) {
val = 1 << (start_bit); //function 1
val = 0; // function 0
} else if ((pin == PSPI_CLK_PB5_PIN) || (pin == PSPI_CLK_PD1_PIN) || (pin == PSPI_CSN_PC0_PIN) ||
(pin == PSPI_CSN_PD0_PIN) || (pin == PSPI_MOSI_IO0_PB7_PIN) || (pin == PSPI_MOSI_IO0_PD3_PIN) ||
(pin == PSPI_MISO_IO1_PB6_PIN) || (pin == PSPI_MISO_IO1_PD2_PIN)) {
val = 1 << (start_bit); // function 1
}
reg_gpio_func_mux(pin) = (reg_gpio_func_mux(pin) & mask) | val;
@@ -257,8 +255,8 @@ void pspi_set_pin(pspi_pin_config_t *config)
*/
void spi_slave_set_pin(void)
{
reg_gpio_pa_fuc_l = (reg_gpio_pb_fuc_l & 0x03); //set PA1 as csn,PA2 as clk,PA3 as mosi_io0,
reg_gpio_pa_fuc_h = (reg_gpio_pb_fuc_l & 0xfc); //set PA4 slave miso_io1
reg_gpio_pa_fuc_l = (reg_gpio_pb_fuc_l & 0x03); // set PA1 as csn,PA2 as clk,PA3 as mosi_io0,
reg_gpio_pa_fuc_h = (reg_gpio_pb_fuc_l & 0xfc); // set PA4 slave miso_io1
gpio_function_dis(GPIO_PA1 | GPIO_PA2 | GPIO_PA3 | GPIO_PA4);
gpio_input_en(GPIO_PA1 | GPIO_PA2 | GPIO_PA3 | GPIO_PA4);
}
@@ -279,7 +277,7 @@ void spi_slave_set_pin(void)
void spi_master_init(spi_sel_e spi_sel, unsigned char div_clock, spi_mode_type_e mode)
{
reg_spi_mode1(spi_sel) = div_clock;
reg_spi_mode0(spi_sel) |= FLD_SPI_MASTER_MODE; //master
reg_spi_mode0(spi_sel) |= FLD_SPI_MASTER_MODE; // master
reg_spi_mode0(spi_sel) &= (~FLD_SPI_MODE_WORK_MODE); // clear spi working mode
reg_spi_mode0(spi_sel) |= (mode << 5); // select SPI mode, support four modes
}
@@ -298,7 +296,7 @@ void spi_master_init(spi_sel_e spi_sel, unsigned char div_clock, spi_mode_type_e
*/
void spi_slave_init(spi_sel_e spi_sel, spi_mode_type_e mode)
{
reg_spi_mode0(spi_sel) &= (~FLD_SPI_MASTER_MODE); //slave
reg_spi_mode0(spi_sel) &= (~FLD_SPI_MASTER_MODE); // slave
reg_spi_mode0(spi_sel) &= (~FLD_SPI_MODE_WORK_MODE); // clear spi working mode
reg_spi_mode0(spi_sel) |= (mode << 5); // select SPI mode, support four modes
}
@@ -348,7 +346,7 @@ void spi_set_normal_mode(spi_sel_e spi_sel)
*/
void spi_set_dual_mode(spi_sel_e spi_sel)
{
spi_dual_mode_en(spi_sel); //quad precede over dual
spi_dual_mode_en(spi_sel); // quad precede over dual
spi_3line_mode_dis(spi_sel);
if (HSPI_MODULE == spi_sel) {
hspi_quad_mode_dis(spi_sel);
@@ -359,7 +357,7 @@ void spi_set_dual_mode(spi_sel_e spi_sel)
* @brief This function servers to set quad mode.
* @return none
*/
void hspi_set_quad_mode()
void hspi_set_quad_mode(void)
{
hspi_quad_mode_en();
spi_dual_mode_dis(HSPI_MODULE);
@@ -373,7 +371,7 @@ void hspi_set_quad_mode()
*/
void spi_set_3line_mode(spi_sel_e spi_sel)
{
/*must disable dual and quad*/
/* must disable dual and quad */
spi_3line_mode_en(spi_sel);
spi_dual_mode_dis(spi_sel);
if (HSPI_MODULE == spi_sel) {
@@ -492,8 +490,8 @@ void hspi_set_address(unsigned int addr)
void spi_write(spi_sel_e spi_sel, unsigned char *data, unsigned int len)
{
for (unsigned int i = 0; i < len; i++) {
while (reg_spi_fifo_state(spi_sel) & FLD_SPI_TXF_FULL)
;
while (reg_spi_fifo_state(spi_sel) & FLD_SPI_TXF_FULL) {
}
reg_spi_wr_rd_data(spi_sel, i % 4) = data[i];
}
}
@@ -508,8 +506,8 @@ void spi_write(spi_sel_e spi_sel, unsigned char *data, unsigned int len)
void spi_read(spi_sel_e spi_sel, unsigned char *data, unsigned int len)
{
for (unsigned int i = 0; i < len; i++) {
while (reg_spi_fifo_state(spi_sel) & FLD_SPI_RXF_EMPTY)
;
while (reg_spi_fifo_state(spi_sel) & FLD_SPI_RXF_EMPTY) {
}
data[i] = reg_spi_wr_rd_data(spi_sel, i % 4);
}
}
@@ -526,10 +524,10 @@ void spi_master_write(spi_sel_e spi_sel, unsigned char *data, unsigned int len)
spi_tx_fifo_clr(spi_sel);
spi_tx_cnt(spi_sel, len);
spi_set_transmode(spi_sel, SPI_MODE_WRITE_ONLY);
spi_set_cmd(spi_sel, 0x00); //when cmd disable that will not sent cmd,just trigger spi send .
spi_set_cmd(spi_sel, 0x00); // when cmd disable that will not sent cmd,just trigger spi send .
spi_write(spi_sel, (unsigned char *)data, len);
while (spi_is_busy(spi_sel))
;
while (spi_is_busy(spi_sel)) {
}
}
/**
@@ -549,11 +547,11 @@ void spi_master_write_read(spi_sel_e spi_sel, unsigned char *wr_data, unsigned i
spi_tx_cnt(spi_sel, wr_len);
spi_rx_cnt(spi_sel, rd_len);
spi_set_transmode(spi_sel, SPI_MODE_WRITE_READ);
spi_set_cmd(spi_sel, 0x00); //when cmd disable that will not sent cmd,just trigger spi send .
spi_set_cmd(spi_sel, 0x00); // when cmd disable that will not sent cmd,just trigger spi send .
spi_write(spi_sel, (unsigned char *)wr_data, wr_len);
spi_read(spi_sel, (unsigned char *)rd_data, rd_len);
while (spi_is_busy(spi_sel))
;
while (spi_is_busy(spi_sel)) {
}
}
/**
@@ -578,8 +576,8 @@ void spi_master_write_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned int ad
spi_tx_cnt(spi_sel, data_len);
spi_set_cmd(spi_sel, cmd);
spi_write(spi_sel, (unsigned char *)data, data_len);
while (spi_is_busy(spi_sel))
;
while (spi_is_busy(spi_sel)) {
}
}
/**
@@ -603,8 +601,8 @@ void spi_master_read_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned int add
spi_rx_cnt(spi_sel, data_len);
spi_set_cmd(spi_sel, cmd);
spi_read(spi_sel, (unsigned char *)data, data_len);
while (spi_is_busy(spi_sel))
;
while (spi_is_busy(spi_sel)) {
}
}
/**
@@ -630,8 +628,8 @@ void spi_master_write_read_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned c
spi_set_cmd(spi_sel, cmd);
spi_write(spi_sel, (unsigned char *)addrs, addr_len);
spi_read(spi_sel, (unsigned char *)data, data_len);
while (spi_is_busy(spi_sel))
;
while (spi_is_busy(spi_sel)) {
}
}
/**
@@ -706,7 +704,7 @@ void spi_set_tx_dma(spi_sel_e spi_sel, unsigned char *src_addr, unsigned int len
} else {
tx_dma_chn = s_pspi_tx_dma_chn;
}
spi_rx_tx_irq_trig_cnt(spi_sel, 4); //recover trigger level to 4.
spi_rx_tx_irq_trig_cnt(spi_sel, 4); // recover trigger level to 4.
spi_tx_cnt(spi_sel, len);
dma_set_address(tx_dma_chn, (unsigned int)convert_ram_addr_cpu2bus(src_addr), reg_spi_data_buf_adr(spi_sel));
dma_set_size(tx_dma_chn, len, DMA_WORD_WIDTH);
@@ -728,7 +726,7 @@ void spi_set_rx_dma(spi_sel_e spi_sel, unsigned char *dst_addr, unsigned int len
rx_dma_chn = s_pspi_rx_dma_chn;
}
spi_rx_tx_irq_trig_cnt(
spi_sel, 5); //setting only for fixing the bug that slave receive number of bytes in multiples of 4 will fail.
spi_sel, 5); // setting only for fixing the bug that slave receive number of bytes in multiples of 4 will fail.
dma_set_address(rx_dma_chn, reg_spi_data_buf_adr(spi_sel), (unsigned int)convert_ram_addr_cpu2bus(dst_addr));
dma_set_size(rx_dma_chn, len, DMA_WORD_WIDTH);
dma_chn_en(rx_dma_chn);
@@ -786,7 +784,7 @@ void spi_master_write_read_dma(spi_sel_e spi_sel, unsigned char *addr, unsigned
}
spi_set_dma(tx_dma_chn, (unsigned int)convert_ram_addr_cpu2bus(addr), reg_spi_data_buf_adr(spi_sel), addr_len);
spi_set_dma(rx_dma_chn, reg_spi_data_buf_adr(spi_sel), (unsigned int)convert_ram_addr_cpu2bus(data), data_len);
spi_set_cmd(spi_sel, 0x00); //when cmd disable that will not sent cmd,just trigger spi send .
spi_set_cmd(spi_sel, 0x00); // when cmd disable that will not sent cmd,just trigger spi send .
}
/**
@@ -857,7 +855,7 @@ void spi_master_read_dma_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned int
* @return none
*/
void spi_master_write_read_dma_plus(spi_sel_e spi_sel, unsigned char cmd, unsigned char *addr, unsigned int addr_len,
unsigned char *dst_addr, unsigned int rd_len, spi_rd_tans_mode_e rd_mode)
unsigned char *rd_data, unsigned int rd_len, spi_rd_tans_mode_e rd_mode)
{
unsigned char tx_dma_chn, rx_dma_chn;
spi_tx_fifo_clr(spi_sel);
@@ -875,8 +873,8 @@ void spi_master_write_read_dma_plus(spi_sel_e spi_sel, unsigned char cmd, unsign
rx_dma_chn = s_pspi_rx_dma_chn;
}
spi_set_dma(tx_dma_chn, (unsigned int)convert_ram_addr_cpu2bus(addr), reg_spi_data_buf_adr(spi_sel), addr_len);
spi_set_dma(rx_dma_chn, reg_spi_data_buf_adr(spi_sel), (unsigned int)convert_ram_addr_cpu2bus(dst_addr), rd_len);
spi_set_cmd(spi_sel, cmd); //when cmd disable that will not sent cmd,just trigger spi send .
spi_set_dma(rx_dma_chn, reg_spi_data_buf_adr(spi_sel), (unsigned int)convert_ram_addr_cpu2bus(rd_data), rd_len);
spi_set_cmd(spi_sel, cmd); // when cmd disable that will not sent cmd,just trigger spi send .
}
/**
b91/b91_ble_sdk/drivers/B91/spi.h
+33 -41
View File
@@ -83,50 +83,48 @@ typedef enum { HSPI_SINGLE = 0, HSPI_DUAL = 1, HSPI_QUAD = 2, HSPI_3LINE = 3 } h
* @brief Define the SPI command & translate mode.
*/
typedef enum {
SPI_MODE_WRITE_AND_READ = 0, //write and read at the same.must enbale CmdEn
SPI_MODE_WRITE_ONLY, //write
SPI_MODE_WRITE_AND_READ = 0, // write and read at the same.must enbale CmdEn
SPI_MODE_WRITE_ONLY, // write
SPI_MODE_READ_ONLY, // read must enbale CmdEn
SPI_MODE_WRITE_READ, //write_ read
SPI_MODE_READ_WRITE, //read_write
SPI_MODE_WRITE_DUMMY_READ, //write_dummy_read
SPI_MODE_READ_DUMMY_WRITE, //read_ dummy_write must enbale CmdEn
SPI_MODE_NONE_DATA, //must enbale CmdEn
SPI_MODE_DUMMY_WRITE, //dummy_write
SPI_MODE_DUMMY_READ, //dummy_read
SPI_MODE_WRITE_READ, // write_ read
SPI_MODE_READ_WRITE, // read_write
SPI_MODE_WRITE_DUMMY_READ, // write_dummy_read
SPI_MODE_READ_DUMMY_WRITE, // read_ dummy_write must enbale CmdEn
SPI_MODE_NONE_DATA, // must enbale CmdEn
SPI_MODE_DUMMY_WRITE, // dummy_write
SPI_MODE_DUMMY_READ, // dummy_read
SPI_MODE_RESERVED,
} spi_tans_mode_e;
typedef enum {
SPI_MODE_WR_WRITE_ONLY = 1, //write
SPI_MODE_WR_DUMMY_WRITE = 8, //dummy_write
SPI_MODE_WR_WRITE_ONLY = 1, // write
SPI_MODE_WR_DUMMY_WRITE = 8, // dummy_write
} spi_wr_tans_mode_e;
typedef enum {
SPI_MODE_RD_READ_ONLY = 2, //must enbale CmdEn
SPI_MODE_RD_DUMMY_READ = 9, //dummy_read
SPI_MODE_RD_READ_ONLY = 2, // must enbale CmdEn
SPI_MODE_RD_DUMMY_READ = 9, // dummy_read
} spi_rd_tans_mode_e;
typedef enum {
SPI_MODE_WR_RD = 3, //must enbale CmdEn
SPI_MODE_WR_DUMMY_RD = 5, //write_dummy_read
SPI_MODE_WR_RD = 3, // must enbale CmdEn
SPI_MODE_WR_DUMMY_RD = 5, // write_dummy_read
} spi_wr_rd_tans_mode_e;
typedef struct
{
hspi_single_dual_quad_mode_e hspi_io_mode; //set spi interface mode
unsigned char hspi_dummy_cnt; //set dummy cnt if tans_mode have dummy .
unsigned char hspi_cmd_en; //enable cmd phase
unsigned char hspi_addr_en; //enable address phase
unsigned char hspi_addr_len; //enable address phase
unsigned char hspi_cmd_fmt_en; //if cmd_en enable cmd fmt will follow the interface (dual/quad)
unsigned char hspi_addr_fmt_en; //if addr_en enable addr fmt will follow the interface (dual/quad)
typedef struct {
hspi_single_dual_quad_mode_e hspi_io_mode; // set spi interface mode
unsigned char hspi_dummy_cnt; // set dummy cnt if tans_mode have dummy .
unsigned char hspi_cmd_en; // enable cmd phase
unsigned char hspi_addr_en; // enable address phase
unsigned char hspi_addr_len; // enable address phase
unsigned char hspi_cmd_fmt_en; // if cmd_en enable cmd fmt will follow the interface (dual/quad)
unsigned char hspi_addr_fmt_en; // if addr_en enable addr fmt will follow the interface (dual/quad)
} hspi_config_t;
typedef struct
{
pspi_single_dual_mode_e pspi_io_mode; //set spi interface mode
unsigned char pspi_dummy_cnt; //set dummy cnt if tans_mode have dummy .
_Bool pspi_cmd_en; //enable cmd phase
typedef struct {
pspi_single_dual_mode_e pspi_io_mode; // set spi interface mode
unsigned char pspi_dummy_cnt; // set dummy cnt if tans_mode have dummy .
_Bool pspi_cmd_en; // enable cmd phase
} pspi_config_t;
typedef enum {
@@ -150,7 +148,6 @@ typedef enum {
SPI_SLAVE_READ_DATA_AND_ADDR_DUL_4CYC_CMD =
FLD_SPI_CMD_RD_EN | FLD_SPI_CMD_ADDR_DUAL | FLD_SPI_CMD_DATA_DUAL | FLD_SPI_CMD_RD_DUMMY_4CYCLE,
} spi_slave_read_cmd_e;
typedef enum {
@@ -187,7 +184,6 @@ typedef enum {
PSRAM_REST_CMD = 0x99,
PSRAM_BURST_LENGTH_TOGGLE_CMD = 0xC0,
PSRAM_READ_ID_CMD = 0x95,
} spi_xip_cmd_e;
/**
@@ -249,8 +245,7 @@ typedef enum {
HSPI_NONE_PIN = 0xfff,
} hspi_pin_def_e;
typedef struct
{
typedef struct {
hspi_clk_pin_def_e hspi_clk_pin;
hspi_csn_pin_def_e hspi_csn_pin;
hspi_mosi_io0_pin_def_e hspi_mosi_io0_pin;
@@ -302,8 +297,7 @@ typedef enum {
PSPI_NONE_PIN = 0xfff,
} pspi_pin_def_e;
typedef struct
{
typedef struct {
pspi_clk_pin_def_e pspi_clk_pin;
pspi_csn_pin_def_e pspi_csn_pin;
pspi_mosi_io0_pin_def_e pspi_mosi_io0_pin;
@@ -423,7 +417,6 @@ static inline void spi_cmd_en(spi_sel_e spi_sel)
*/
static inline void spi_cmd_dis(spi_sel_e spi_sel)
{
BM_CLR(reg_spi_mode2(spi_sel), FLD_SPI_CMD_EN);
}
@@ -431,7 +424,7 @@ static inline void spi_cmd_dis(spi_sel_e spi_sel)
* @brief This function servers enable cmd format,the format of cmd phase is the same as the data phase(Dual/Quad).
* @return none
*/
static inline void hspi_cmd_fmt_en()
static inline void hspi_cmd_fmt_en(void)
{
BM_SET(reg_spi_mode2(HSPI_MODULE), FLD_HSPI_CMD_FMT);
}
@@ -440,7 +433,7 @@ static inline void hspi_cmd_fmt_en()
* @brief This function servers disable cmd format.
* @return none
*/
static inline void hspi_cmd_fmt_dis()
static inline void hspi_cmd_fmt_dis(void)
{
BM_CLR(reg_spi_mode2(HSPI_MODULE), FLD_HSPI_CMD_FMT);
}
@@ -449,7 +442,7 @@ static inline void hspi_cmd_fmt_dis()
* @brief This function servers to enable hspi quad mode.
* @return none
*/
static inline void hspi_quad_mode_en()
static inline void hspi_quad_mode_en(void)
{
BM_SET(reg_spi_mode2(HSPI_MODULE), FLD_HSPI_QUAD);
}
@@ -589,7 +582,6 @@ static inline void hspi_xip_set_wr_cmd(unsigned char wr_cmd)
*/
static inline void hspi_xip_set_rd_cmd(unsigned char rd_cmd)
{
reg_hspi_xip_rd_cmd = rd_cmd;
}
@@ -1001,7 +993,7 @@ void spi_set_dual_mode(spi_sel_e spi_sel);
* @brief This function servers to set quad mode.
* @return none
*/
void hspi_set_quad_mode();
void hspi_set_quad_mode(void);
/**
* @brief This function servers to set 3line mode.
b91/b91_ble_sdk/drivers/B91/stimer.h
+3 -3
View File
@@ -41,6 +41,7 @@
/**********************************************************************************************************************
* global data type *
*********************************************************************************************************************/
/**********************************************************************************************************************
* global variable declaration *
*********************************************************************************************************************/
@@ -56,8 +57,8 @@ enum {
SYSTEM_TIMER_TICK_1MS = 16000,
SYSTEM_TIMER_TICK_1S = 16000000,
SYSTEM_TIMER_TICK_625US = 10000, //625*16
SYSTEM_TIMER_TICK_1250US = 20000, //1250*16
SYSTEM_TIMER_TICK_625US = 10000, // 625*16
SYSTEM_TIMER_TICK_1250US = 20000, // 1250*16
};
/**
@@ -144,7 +145,6 @@ static inline void stimer_disable(void)
**/
static inline unsigned int stimer_get_tick(void)
{
return reg_system_tick;
}
b91/b91_ble_sdk/drivers/B91/sys.h
+17 -11
View File
@@ -29,7 +29,6 @@
#ifndef SYS_H_
#define SYS_H_
#include "bit.h"
#include "reg_include/stimer_reg.h"
/**********************************************************************************************************************
* global constants *
@@ -139,12 +138,17 @@
#define TCMD_WRITE 0x3
#define TCMD_WAIT 0x7
#define TCMD_WAREG 0x8
//#if 1 //optimize
#define OPTIMIZE_CONVERT_CPU2BUS_ENABLE 1
#if OPTIMIZE_CONVERT_CPU2BUS_ENABLE // optimize
/*
* IRAM area:0x00000~0x1FFFF BIT(19) is 0,BIT(16~0) 128K is address offset
* DRAM area:0x80000~0x9FFFF BIT(19) is 1,BIT(16~0) 128K is address offset
* ILM area:0xc0000000~0xc0020000 BIT(31~19) is 3,BIT(21) is 0, BIT(20~17) do not care BIT(16~0) 128K is address offset 128K is address offset
* DLM area:0xc0200000~0xc0220000 BIT(31~19) is 3,BIT(21) is 1, BIT(20~17) do not care BIT(16~0) 128K is address offset 128K is address offset
* ILM area:0xc0000000~0xc0020000 BIT(31~19) is 3,BIT(21) is 0,
* BIT(20~17) do not care BIT(16~0) 128K is address offset 128K is address offset
* DLM area:0xc0200000~0xc0220000 BIT(31~19) is 3,BIT(21) is 1,
* BIT(20~17) do not care BIT(16~0) 128K is address offset 128K is address offset
* BIT(19) is used to distinguish from IRAM to DRAM, BIT(21) is used to distinguish from ILM to DLM.
* so we can write it as follow
* #define convert_ram_addr_cpu2bus (((((addr))&0x80000)? ((addr)| 0xc0200000) : ((addr)|0xc0000000)))
@@ -154,9 +158,12 @@
* #define convert(addr) ((addr)+0xc0180000)
* */
#define convert_ram_addr_cpu2bus(addr) ((unsigned int)(addr) + 0xc0180000)
//#else //no optimize
//#define convert_ram_addr_cpu2bus (((((unsigned int)(addr)) >=0x80000)?(((unsigned int)(addr))-0x80000+0xc0200000) : (((unsigned int)(addr)) + 0xc0000000)))
//#endif
#else // no optimize
#define convert_ram_addr_cpu2bus (( \
(((unsigned int)(addr)) >=0x80000) ? \
(((unsigned int)(addr))-0x80000+0xc0200000) : \
(((unsigned int)(addr)) + 0xc0000000)))
#endif
#define convert_ram_addr_bus2cpu(addr) \
(((((unsigned int)(addr)) >= 0xc0200000) ? (((unsigned int)(addr)) + 0x80000 - 0xc0200000) \
@@ -183,15 +190,14 @@ typedef enum {
* the bypass is closed, and the vbat voltage passes through an LDO to supply power to the chip.
*/
typedef enum {
VBAT_MAX_VALUE_GREATER_THAN_3V6 = 0x00, /*VBAT may be greater than 3.6V. */
VBAT_MAX_VALUE_LESS_THAN_3V6 = BIT(3), /*VBAT must be below 3.6V. */
VBAT_MAX_VALUE_GREATER_THAN_3V6 = 0x00, /* VBAT may be greater than 3.6V. */
VBAT_MAX_VALUE_LESS_THAN_3V6 = BIT(3), /* VBAT must be below 3.6V. */
} vbat_type_e;
/**
* @brief command table for special registers
*/
typedef struct tbl_cmd_set_t
{
typedef struct tbl_cmd_set_t {
unsigned int adr;
unsigned char dat;
unsigned char cmd;
b91/b91_ble_sdk/drivers/B91/timer.c
+4 -4
View File
@@ -70,12 +70,12 @@ void timer_set_mode(timer_type_e type, timer_mode_e mode)
{
switch (type) {
case TIMER0:
reg_tmr_sta = FLD_TMR_STA_TMR0; //clear irq status
reg_tmr_sta = FLD_TMR_STA_TMR0; // clear irq status
reg_tmr_ctrl0 &= (~FLD_TMR0_MODE);
reg_tmr_ctrl0 |= mode;
break;
case TIMER1:
reg_tmr_sta = FLD_TMR_STA_TMR1; //clear irq status
reg_tmr_sta = FLD_TMR_STA_TMR1; // clear irq status
reg_tmr_ctrl0 &= (~FLD_TMR1_MODE);
reg_tmr_ctrl0 |= (mode << 4);
break;
@@ -94,8 +94,8 @@ void timer_set_mode(timer_type_e type, timer_mode_e mode)
void timer_gpio_init(timer_type_e type, gpio_pin_e pin, gpio_pol_e pol)
{
gpio_function_en(pin);
gpio_output_dis(pin); //disable output
gpio_input_en(pin); //enable input
gpio_output_dis(pin); // disable output
gpio_input_en(pin); // enable input
switch (type) {
case TIMER0:
if (pol == POL_FALLING) {
b91/b91_ble_sdk/drivers/B91/trng.h
+2 -1
View File
@@ -63,6 +63,7 @@ void trng_init(void);
* @brief This function performs to get one random number.
* @return the value of one random number
**/
/*unsigned*/ int trng_rand(void);
/* unsigned */
int trng_rand(void);
#endif
b91/b91_ble_sdk/drivers/B91/uart.c
+116 -105
View File
@@ -21,6 +21,8 @@
* local constants *
*********************************************************************************************************************/
#define UART_HW_FIFO_SIZE 8
/**********************************************************************************************************************
* local macro *
*********************************************************************************************************************/
@@ -32,66 +34,72 @@
/**********************************************************************************************************************
* global variable *
*********************************************************************************************************************/
dma_config_t uart_tx_dma_config[2] = {{
.dst_req_sel = DMA_REQ_UART0_TX, //tx req
.src_req_sel = 0,
.dst_addr_ctrl = DMA_ADDR_FIX,
.src_addr_ctrl = DMA_ADDR_INCREMENT, //increment
.dstmode = DMA_HANDSHAKE_MODE, //handshake
.srcmode = DMA_NORMAL_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must be word
.srcwidth = DMA_CTR_WORD_WIDTH, //must be word
.src_burst_size = 0, //must be 0
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must be 0
},
{
.dst_req_sel = DMA_REQ_UART1_TX, //tx req
.src_req_sel = 0,
.dst_addr_ctrl = DMA_ADDR_FIX,
.src_addr_ctrl = DMA_ADDR_INCREMENT, //increment
.dstmode = DMA_HANDSHAKE_MODE, //handshake
.srcmode = DMA_NORMAL_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must be word
.srcwidth = DMA_CTR_WORD_WIDTH, //must be word
.src_burst_size = 0, //must be 0
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must be 0
}};
dma_config_t uart_rx_dma_config[2] = {{
.dst_req_sel = 0, //tx req
.src_req_sel = DMA_REQ_UART0_RX,
.dst_addr_ctrl = DMA_ADDR_INCREMENT,
.src_addr_ctrl = DMA_ADDR_FIX,
.dstmode = DMA_NORMAL_MODE,
.srcmode = DMA_HANDSHAKE_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must be word
.srcwidth = DMA_CTR_WORD_WIDTH, ////must be word
.src_burst_size = 0,
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must be 0
},
{
.dst_req_sel = 0, //tx req
.src_req_sel = DMA_REQ_UART1_RX,
.dst_addr_ctrl = DMA_ADDR_INCREMENT,
.src_addr_ctrl = DMA_ADDR_FIX,
.dstmode = DMA_NORMAL_MODE,
.srcmode = DMA_HANDSHAKE_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, //must be word
.srcwidth = DMA_CTR_WORD_WIDTH, ////must be word
.src_burst_size = 0,
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, //must be 0
}};
dma_config_t uart_tx_dma_config[2] = {
{
.dst_req_sel = DMA_REQ_UART0_TX, // tx req
.src_req_sel = 0,
.dst_addr_ctrl = DMA_ADDR_FIX,
.src_addr_ctrl = DMA_ADDR_INCREMENT, // increment
.dstmode = DMA_HANDSHAKE_MODE, // handshake
.srcmode = DMA_NORMAL_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, // must be word
.srcwidth = DMA_CTR_WORD_WIDTH, // must be word
.src_burst_size = 0, // must be 0
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, // must be 0
},
{
.dst_req_sel = DMA_REQ_UART1_TX, // tx req
.src_req_sel = 0,
.dst_addr_ctrl = DMA_ADDR_FIX,
.src_addr_ctrl = DMA_ADDR_INCREMENT, // increment
.dstmode = DMA_HANDSHAKE_MODE, // handshake
.srcmode = DMA_NORMAL_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, // must be word
.srcwidth = DMA_CTR_WORD_WIDTH, // must be word
.src_burst_size = 0, // must be 0
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, // must be 0
}
};
dma_config_t uart_rx_dma_config[2] = {
{
.dst_req_sel = 0, // tx req
.src_req_sel = DMA_REQ_UART0_RX,
.dst_addr_ctrl = DMA_ADDR_INCREMENT,
.src_addr_ctrl = DMA_ADDR_FIX,
.dstmode = DMA_NORMAL_MODE,
.srcmode = DMA_HANDSHAKE_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, // must be word
.srcwidth = DMA_CTR_WORD_WIDTH, // must be word
.src_burst_size = 0,
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, // must be 0
},
{
.dst_req_sel = 0, // tx req
.src_req_sel = DMA_REQ_UART1_RX,
.dst_addr_ctrl = DMA_ADDR_INCREMENT,
.src_addr_ctrl = DMA_ADDR_FIX,
.dstmode = DMA_NORMAL_MODE,
.srcmode = DMA_HANDSHAKE_MODE,
.dstwidth = DMA_CTR_WORD_WIDTH, // must be word
.srcwidth = DMA_CTR_WORD_WIDTH, // must be word
.src_burst_size = 0,
.read_num_en = 0,
.priority = 0,
.write_num_en = 0,
.auto_en = 0, // must be 0
}
};
/**********************************************************************************************************************
* local variable *
*********************************************************************************************************************/
@@ -145,26 +153,26 @@ static void uart_set_fuc_pin(uart_tx_pin_e tx_pin, uart_rx_pin_e rx_pin);
* 19200 249 9
* 115200 25 15
*/
void telink_b91_uart_init(uart_num_e uart_num, unsigned short div, unsigned char bwpc, uart_parity_e parity,
uart_stop_bit_e stop_bit)
void telink_b91_uart_init(
uart_num_e uart_num, unsigned short div, unsigned char bwpc, uart_parity_e parity, uart_stop_bit_e stop_bit)
{
reg_uart_ctrl0(uart_num) &= ~(FLD_UART_BPWC_O);
reg_uart_ctrl0(uart_num) |= bwpc; //set bwpc
reg_uart_clk_div(uart_num) = (div | FLD_UART_CLK_DIV_EN); //set div_clock
reg_uart_ctrl0(uart_num) |= bwpc; // set bwpc
reg_uart_clk_div(uart_num) = (div | FLD_UART_CLK_DIV_EN); // set div_clock
//parity config
// parity config
if (parity) {
reg_uart_ctrl1(uart_num) |= FLD_UART_PARITY_ENABLE; //enable parity function
reg_uart_ctrl1(uart_num) |= FLD_UART_PARITY_ENABLE; // enable parity function
if (UART_PARITY_EVEN == parity) {
reg_uart_ctrl1(uart_num) &= (~FLD_UART_PARITY_POLARITY); //enable even parity
reg_uart_ctrl1(uart_num) &= (~FLD_UART_PARITY_POLARITY); // enable even parity
} else if (UART_PARITY_ODD == parity) {
reg_uart_ctrl1(uart_num) |= FLD_UART_PARITY_POLARITY; //enable odd parity
reg_uart_ctrl1(uart_num) |= FLD_UART_PARITY_POLARITY; // enable odd parity
}
} else {
reg_uart_ctrl1(uart_num) &= (~FLD_UART_PARITY_ENABLE); //disable parity function
reg_uart_ctrl1(uart_num) &= (~FLD_UART_PARITY_ENABLE); // disable parity function
}
//stop bit config
// stop bit config
reg_uart_ctrl1(uart_num) &= (~FLD_UART_STOP_SEL);
reg_uart_ctrl1(uart_num) |= stop_bit;
}
@@ -172,7 +180,7 @@ void telink_b91_uart_init(uart_num_e uart_num, unsigned short div, unsigned char
/***********************************************************
* @brief This function serves to calculate the best bwpc(bit width) .i.e reg0x96.
* @param[in] baudrate - baut rate of UART.
* @param[in] pclk - system clock.
* @param[in] sysclk - system clock.
* @param[out] div - uart clock divider.
* @param[out] bwpc - bitwidth, should be set to larger than 2.
* @return none
@@ -180,7 +188,7 @@ void telink_b91_uart_init(uart_num_e uart_num, unsigned short div, unsigned char
* simplify the expression: div*bwpc = constant(z)
* bwpc range from 3 to 15.so loop and get the minimum one decimal point
*/
void uart_cal_div_and_bwpc(unsigned int baudrate, unsigned int pclk, unsigned short *div, unsigned char *bwpc)
void uart_cal_div_and_bwpc(unsigned int baudrate, unsigned int sysclk, unsigned short *div, unsigned char *bwpc)
{
unsigned char i = 0, j = 0;
unsigned int primeInt = 0;
@@ -188,11 +196,11 @@ void uart_cal_div_and_bwpc(unsigned int baudrate, unsigned int pclk, unsigned sh
unsigned int D_intdec[13], D_int[13];
unsigned char D_dec[13];
primeInt = pclk / baudrate;
primeDec = 10 * pclk / baudrate - 10 * primeInt;
primeInt = sysclk / baudrate;
primeDec = 10 * sysclk / baudrate - 10 * primeInt;
if (uart_is_prime(primeInt)) { // primeInt is prime
primeInt += 1; //+1 must be not prime. and primeInt must be larger than 2.
primeInt += 1; // +1 must be not prime. and primeInt must be larger than 2.
} else {
if (primeDec > 5) { // >5
primeInt += 1;
@@ -203,12 +211,12 @@ void uart_cal_div_and_bwpc(unsigned int baudrate, unsigned int pclk, unsigned sh
}
for (i = 3; i <= 15; i++) {
D_intdec[i - 3] = (10 * primeInt) / (i + 1); ////get the LSB
D_dec[i - 3] = D_intdec[i - 3] - 10 * (D_intdec[i - 3] / 10); ///get the decimal section
D_int[i - 3] = D_intdec[i - 3] / 10; ///get the integer section
D_intdec[i - 3] = (10 * primeInt) / (i + 1); // get the LSB
D_dec[i - 3] = D_intdec[i - 3] - 10 * (D_intdec[i - 3] / 10); // get the decimal section
D_int[i - 3] = D_intdec[i - 3] / 10; // get the integer section
}
//find the max and min one decimation point
// find the max and min one decimation point
unsigned char position_min = 0, position_max = 0;
unsigned int min = 0xffffffff, max = 0x00;
for (j = 0; j < 13; j++) {
@@ -251,9 +259,9 @@ void uart_cal_div_and_bwpc(unsigned int baudrate, unsigned int pclk, unsigned sh
*/
void uart_set_dma_rx_timeout(uart_num_e uart_num, unsigned char bwpc, unsigned char bit_cnt, uart_timeout_mul_e mul)
{
reg_uart_rx_timeout0(uart_num) = (bwpc + 1) * bit_cnt; //one byte includes 12 bits at most
reg_uart_rx_timeout0(uart_num) = (bwpc + 1) * bit_cnt; // one byte includes 12 bits at most
reg_uart_rx_timeout1(uart_num) &= (~FLD_UART_TIMEOUT_MUL);
reg_uart_rx_timeout1(uart_num) |= mul; //if over 2*(tmp_bwpc+1),one transaction end.
reg_uart_rx_timeout1(uart_num) |= mul; // if over 2*(tmp_bwpc+1),one transaction end.
}
unsigned char uart_tx_byte_index[2] = {0};
@@ -265,8 +273,8 @@ unsigned char uart_tx_byte_index[2] = {0};
*/
void uart_send_byte(uart_num_e uart_num, unsigned char tx_data)
{
while (uart_get_txfifo_num(uart_num) > 7)
;
while (uart_get_txfifo_num(uart_num) > (UART_HW_FIFO_SIZE - sizeof(tx_data))) {
}
reg_uart_data_buf(uart_num, uart_tx_byte_index[uart_num]) = tx_data;
uart_tx_byte_index[uart_num]++;
@@ -308,8 +316,8 @@ void uart_send_hword(uart_num_e uart_num, unsigned short data)
{
static unsigned char uart_tx_hword_index[2] = {0};
while (uart_get_txfifo_num(uart_num) > 6)
;
while (uart_get_txfifo_num(uart_num) > (UART_HW_FIFO_SIZE - sizeof(data))) {
}
reg_uart_data_hword_buf(uart_num, uart_tx_hword_index[uart_num]) = data;
uart_tx_hword_index[uart_num]++;
@@ -324,8 +332,8 @@ void uart_send_hword(uart_num_e uart_num, unsigned short data)
*/
void uart_send_word(uart_num_e uart_num, unsigned int data)
{
while (uart_get_txfifo_num(uart_num) > 4)
;
while (uart_get_txfifo_num(uart_num) > (UART_HW_FIFO_SIZE - sizeof(data))) {
}
reg_uart_data_word_buf(uart_num) = data;
}
@@ -422,7 +430,7 @@ void uart_set_pin(uart_tx_pin_e tx_pin, uart_rx_pin_e rx_pin)
{
gpio_set_up_down_res(tx_pin, GPIO_PIN_PULLUP_10K);
gpio_set_up_down_res(rx_pin, GPIO_PIN_PULLUP_10K);
uart_set_fuc_pin(tx_pin, rx_pin); //set tx and rx pin
uart_set_fuc_pin(tx_pin, rx_pin); // set tx and rx pin
gpio_input_en(tx_pin);
gpio_input_en(rx_pin);
}
@@ -490,8 +498,8 @@ unsigned char uart_send_dma(uart_num_e uart_num, unsigned char *addr, unsigned i
{
if (len != 0) {
uart_clr_tx_done(uart_num);
dma_set_address(uart_dma_tx_chn[uart_num], (unsigned int)convert_ram_addr_cpu2bus(addr),
reg_uart_data_buf_adr(uart_num));
dma_set_address(
uart_dma_tx_chn[uart_num], (unsigned int)convert_ram_addr_cpu2bus(addr), reg_uart_data_buf_adr(uart_num));
dma_set_size(uart_dma_tx_chn[uart_num], len, DMA_WORD_WIDTH);
dma_chn_en(uart_dma_tx_chn[uart_num]);
return 1;
@@ -501,26 +509,31 @@ unsigned char uart_send_dma(uart_num_e uart_num, unsigned char *addr, unsigned i
}
/**
* @brief This function serves to receive data function by DMA, this function tell the DMA to get data from the uart data fifo.
* @brief This function serves to receive data function by DMA, this function tell the DMA to get data from
* the uart data fifo.
* @param[in] uart_num - UART0 or UART1.
* @param[in] addr - pointer to the buffer receive data.
* @param[in] rev_size - the receive length of DMA,The maximum transmission length of DMA is 0xFFFFFC bytes, so dont'n over this length.
* @param[in] rev_size - the receive length of DMA,The maximum transmission length of DMA is 0xFFFFFC bytes,
* so dont'n over this length.
* @note The DMA version of A0 has some limitians.
* 0:We should know the real receive length-len.
* 1:If the data length we receive isn't the multiple of 4(the DMA carry 4-byte one time),like 5,it will carry 8 byte,
* while the last 3-byte data is random.
* 2:The receive buff length sholud be equal to rec_size.The relation of the receive buff length and rec_size and
* the real receive data length-len : REC_BUFF_LEN=rec_size= ((len%4)==0 ? len : ((len/4)+1)*4).
* 1:If the data length we receive isn't the multiple of 4(the DMA carry 4-byte one time),
* like 5, it will carry 8 byte, while the last 3-byte data is random.
* 2:The receive buff length sholud be equal to rec_size.The relation of the receive buff length and
* rec_size and the real receive data length-len :
* REC_BUFF_LEN=rec_size= ((len%4)==0 ? len : ((len/4)+1)*4).
* The DMA version of A1 can receive any length of data,the rev_size is useless.
* @return none
*/
void uart_receive_dma(uart_num_e uart_num, unsigned char *addr, unsigned int rev_size)
{
dma_chn_dis(uart_dma_rx_chn[uart_num]);
/*In order to be able to receive data of unknown length(A0 doesn't suppport),the DMA SIZE is set to the longest value 0xffffffff.After entering suspend and wake up, and then continue to receive,
DMA will no longer move data from uart fifo, because DMA thinks that the last transmission was not completed and must disable dma_chn first.modified by minghai,confirmed qiangkai 2020.11.26.*/
dma_set_address(uart_dma_rx_chn[uart_num], reg_uart_data_buf_adr(uart_num),
(unsigned int)convert_ram_addr_cpu2bus(addr));
/* In order to be able to receive data of unknown length(A0 doesn't suppport),the DMA SIZE is set to the longest
* value 0xffffffff.After entering suspend and wake up, and then continue to receive,
* DMA will no longer move data from uart fifo, because DMA thinks that the last transmission was not completed
* and must disable dma_chn first.modified by minghai,confirmed qiangkai 2020.11.26. */
dma_set_address(
uart_dma_rx_chn[uart_num], reg_uart_data_buf_adr(uart_num), (unsigned int)convert_ram_addr_cpu2bus(addr));
if (0xff == g_chip_version) {
dma_set_size(uart_dma_rx_chn[uart_num], rev_size, DMA_WORD_WIDTH);
} else {
@@ -565,7 +578,7 @@ void uart_cts_config(uart_num_e uart_num, uart_cts_pin_e cts_pin, unsigned char
{
uart_set_cts_pin(cts_pin);
gpio_input_en(cts_pin); //enable input
gpio_input_en(cts_pin); // enable input
if (cts_parity) {
reg_uart_ctrl1(uart_num) |= FLD_UART_TX_CTS_POLARITY;
@@ -611,7 +624,7 @@ static unsigned char uart_is_prime(unsigned int n)
{
unsigned int i = 5;
if (n <= 3) {
return 1; //althought n is prime, the bwpc must be larger than 2.
return 1; // althought n is prime, the bwpc must be larger than 2.
} else if ((n % 2 == 0) || (n % 3 == 0)) {
return 0;
} else {
@@ -654,7 +667,6 @@ static void uart_set_fuc_pin(uart_tx_pin_e tx_pin, uart_rx_pin_e rx_pin)
val = 0;
} else if (tx_pin == UART1_TX_PE0) {
mask = (unsigned char)~(BIT(1) | BIT(0));
;
val = BIT(0);
}
reg_gpio_func_mux(tx_pin) = (reg_gpio_func_mux(tx_pin) & mask) | val;
@@ -662,7 +674,6 @@ static void uart_set_fuc_pin(uart_tx_pin_e tx_pin, uart_rx_pin_e rx_pin)
if (rx_pin == UART0_RX_PA4) {
mask = (unsigned char)~(BIT(1) | BIT(0));
val = BIT(0);
} else if (rx_pin == UART0_RX_PB3) {
mask = (unsigned char)~(BIT(7) | BIT(6));
val = BIT(7);
@@ -681,7 +692,7 @@ static void uart_set_fuc_pin(uart_tx_pin_e tx_pin, uart_rx_pin_e rx_pin)
mask = (unsigned char)~(BIT(5) | BIT(4));
val = BIT(4);
}
//note: setting pad the function must before setting no_gpio function, cause it will lead to uart transmit extra one byte data at begin.(confirmed by minghai&sunpeng)
// note: setting pad the function must before setting no_gpio function, cause it will lead to uart transmit extra one byte data at begin.(confirmed by minghai&sunpeng)
reg_gpio_func_mux(rx_pin) = (reg_gpio_func_mux(rx_pin) & mask) | val;
gpio_function_dis(tx_pin);
b91/b91_ble_sdk/drivers/B91/uart.h
+9 -10
View File
@@ -149,11 +149,11 @@ typedef enum {
* @brief Define UART IRQ MASK.The enumeration variable is just a index, and actually needs to be operated registers behind.
*/
typedef enum {
UART_RX_IRQ_MASK = BIT(0), //reg_uart_ctrl0(uart_num) BIT(6)
UART_TX_IRQ_MASK = BIT(1), //reg_uart_ctrl0(uart_num) BIT(7)
UART_RXDONE_MASK = BIT(2), //reg_uart_rx_timeout1(uart_num) BIT(2)
UART_TXDONE_MASK = BIT(3), //reg_uart_rx_timeout1(uart_num) BIT(6)
UART_ERR_IRQ_MASK = BIT(4), //reg_uart_rx_timeout1(uart_num) BIT(7)
UART_RX_IRQ_MASK = BIT(0), // reg_uart_ctrl0(uart_num) BIT(6)
UART_TX_IRQ_MASK = BIT(1), // reg_uart_ctrl0(uart_num) BIT(7)
UART_RXDONE_MASK = BIT(2), // reg_uart_rx_timeout1(uart_num) BIT(2)
UART_TXDONE_MASK = BIT(3), // reg_uart_rx_timeout1(uart_num) BIT(6)
UART_ERR_IRQ_MASK = BIT(4), // reg_uart_rx_timeout1(uart_num) BIT(7)
} uart_irq_mask_e;
/**
@@ -209,7 +209,6 @@ static inline unsigned char uart_get_txfifo_num(uart_num_e uart_num)
*/
static inline void uart_reset(uart_num_e uart_num)
{
reg_rst0 &= (~((uart_num) ? FLD_RST0_UART1 : FLD_RST0_UART0));
reg_rst0 |= ((uart_num) ? FLD_RST0_UART1 : FLD_RST0_UART0);
}
@@ -495,7 +494,7 @@ static inline void uart_clr_irq_status(uart_num_e uart_num, uart_irq_status_clr_
*/
static inline void uart_set_rts_en(uart_num_e uart_num)
{
reg_uart_ctrl2(uart_num) |= FLD_UART_RTS_EN; //enable RTS function
reg_uart_ctrl2(uart_num) |= FLD_UART_RTS_EN; // enable RTS function
}
/**
@@ -505,7 +504,7 @@ static inline void uart_set_rts_en(uart_num_e uart_num)
*/
static inline void uart_set_rts_dis(uart_num_e uart_num)
{
reg_uart_ctrl2(uart_num) &= (~FLD_UART_RTS_EN); //disable RTS function
reg_uart_ctrl2(uart_num) &= (~FLD_UART_RTS_EN); // disable RTS function
}
/**
@@ -515,7 +514,7 @@ static inline void uart_set_rts_dis(uart_num_e uart_num)
*/
static inline void uart_set_cts_en(uart_num_e uart_num)
{
reg_uart_ctrl1(uart_num) |= FLD_UART_TX_CTS_ENABLE; //enable CTS function
reg_uart_ctrl1(uart_num) |= FLD_UART_TX_CTS_ENABLE; // enable CTS function
}
/**
@@ -525,7 +524,7 @@ static inline void uart_set_cts_en(uart_num_e uart_num)
*/
static inline void uart_set_cts_dis(uart_num_e uart_num)
{
reg_uart_ctrl1(uart_num) &= (~FLD_UART_TX_CTS_ENABLE); //disable CTS function
reg_uart_ctrl1(uart_num) &= (~FLD_UART_TX_CTS_ENABLE); // disable CTS function
}
/**
b91/b91_ble_sdk/drivers/B91/usbhw.h
+5 -3
View File
@@ -25,8 +25,8 @@
* ===============
* Header File: usbhw.h
*/
#pragma once
#ifndef B91_B91_BLE_SDK_DRIVERS_B91_USBHW_H
#define B91_B91_BLE_SDK_DRIVERS_B91_USBHW_H
#include "analog.h"
#include "gpio.h"
@@ -411,6 +411,8 @@ static inline void usb_set_pin_en(void)
gpio_function_dis(GPIO_PA5);
reg_gpio_func_mux(GPIO_PA6) = reg_gpio_func_mux(GPIO_PA6) & (~BIT_RNG(4, 5));
gpio_function_dis(GPIO_PA6);
gpio_input_en(GPIO_PA5 | GPIO_PA6); //DP/DM must set input enable
gpio_input_en(GPIO_PA5 | GPIO_PA6); // DP/DM must set input enable
usb_dp_pullup_en(1);
}
#endif // B91_B91_BLE_SDK_DRIVERS_B91_USBHW_H
b91/b91_ble_sdk/drivers/B91/watchdog.h
-1
View File
@@ -26,7 +26,6 @@
*/
static inline void wd_start(void)
{
BM_SET(reg_tmr_ctrl2, FLD_TMR_WD_EN);
}
b91/b91_ble_sdk/stack/ble/ble_common.h
+63 -64
View File
@@ -97,7 +97,7 @@ typedef enum {
///////////////////////// TELINK define status /////////////////////////////
//LL status
// LL status
LL_ERR_CONNECTION_NOT_ESTABLISH = 0x80,
LL_ERR_TX_FIFO_NOT_ENOUGH,
LL_ERR_ENCRYPTION_BUSY,
@@ -108,7 +108,7 @@ typedef enum {
LL_ERR_CIS_SYNC_FAIL,
LL_ERR_CIS_DISCONNECT,
//L2CAP status
// L2CAP status
L2CAP_ERR_INVALID_PARAMETER = 0x90,
L2CAP_ERR_INVALID_HANDLE,
L2CAP_ERR_INSUFFICIENT_RESOURCES,
@@ -116,11 +116,11 @@ typedef enum {
L2CAP_ERR_CONTROL_NOT_READY,
L2CAP_ERR_PSM_HAVE_ESTABLISH,
//SMP status
// SMP status
SMP_ERR_INVALID_PARAMETER = 0xA0,
SMP_ERR_PAIRING_BUSY,
//GATT status
// GATT status
GATT_ERR_INVALID_PARAMETER = 0xB0,
GATT_ERR_PREVIOUS_INDICATE_DATA_HAS_NOT_CONFIRMED,
GATT_ERR_SERVICE_DISCOVERY_TIEMOUT,
@@ -128,18 +128,18 @@ typedef enum {
GATT_ERR_DATA_PENDING_DUE_TO_SERVICE_DISCOVERY_BUSY,
GATT_ERR_DATA_LENGTH_EXCEED_MTU_SIZE,
//GAP status
// GAP status
GAP_ERR_INVALID_PARAMETER = 0xC0,
//IAL
// IAL
IAL_ERR_SDU_LEN_EXCEED_SDU_MAX,
IAL_ERR_LOSS_SDU_INTRVEL,
IAL_ERR_ISO_TX_FIFO_NOT_ENOUGH,
IAL_ERR_SDU_BUFF_INVALID,
//Service status
// Service status
SERVICE_ERR_INVALID_PARAMETER = 0xD0,
//Application buffer check error code
// Application buffer check error code
LL_ACL_RX_BUF_NO_INIT = 0xE0,
LL_ACL_RX_BUF_PARAM_INVALID,
LL_ACL_RX_BUF_SIZE_NOT_MEET_MAX_RX_OCT,
@@ -147,7 +147,6 @@ typedef enum {
LL_ACL_TX_BUF_PARAM_INVALID,
LL_ACL_TX_BUF_SIZE_MUL_NUM_EXCEED_4K,
LL_ACL_TX_BUF_SIZE_NOT_MEET_MAX_TX_OCT,
} ble_sts_t;
/////////////////////////////// BLE MAC ADDRESS //////////////////////////////////////////////
@@ -156,7 +155,7 @@ typedef enum {
#define BLE_ADDR_INVALID 0xff
#define BLE_ADDR_LEN 6
//Definition for BLE Common Address Type
// Definition for BLE Common Address Type
/*
*
* |--public ..................................................... BLE_DEVICE_ADDRESS_PUBLIC
@@ -175,15 +174,15 @@ typedef enum {
#define BLE_DEVICE_ADDRESS_NON_RESOLVABLE_PRIVATE 3
#define BLE_DEVICE_ADDRESS_RESOLVABLE_PRIVATE 4
#define IS_PUBLIC_ADDR(Type, Addr) ( (Type)==BLE_ADDR_PUBLIC) )
#define IS_RANDOM_STATIC_ADDR(Type, Addr) ((Type) == BLE_ADDR_RANDOM && (Addr[5] & 0xC0) == 0xC0)
#define IS_NON_RESOLVABLE_PRIVATE_ADDR(Type, Addr) ((Type) == BLE_ADDR_RANDOM && (Addr[5] & 0xC0) == 0x00)
#define IS_RESOLVABLE_PRIVATE_ADDR(Type, Addr) ((Type) == BLE_ADDR_RANDOM && (Addr[5] & 0xC0) == 0x40)
#define IS_PUBLIC_ADDR(Type, Addr) ((Type) == BLE_ADDR_PUBLIC)
#define IS_RANDOM_STATIC_ADDR(Type, Addr) ((Type) == BLE_ADDR_RANDOM && ((Addr)[5] & 0xC0) == 0xC0)
#define IS_NON_RESOLVABLE_PRIVATE_ADDR(Type, Addr) ((Type) == BLE_ADDR_RANDOM && ((Addr)[5] & 0xC0) == 0x00)
#define IS_RESOLVABLE_PRIVATE_ADDR(Type, Addr) ((Type) == BLE_ADDR_RANDOM && ((Addr)[5] & 0xC0) == 0x40)
#define MAC_MATCH8(md, ms) \
(md[0] == ms[0] && md[1] == ms[1] && md[2] == ms[2] && md[3] == ms[3] && md[4] == ms[4] && md[5] == ms[5])
#define MAC_MATCH16(md, ms) (md[0] == ms[0] && md[1] == ms[1] && md[2] == ms[2])
#define MAC_MATCH32(md, ms) (md[0] == ms[0] && md[1] == ms[1])
((md)[0] == (ms)[0] && (md)[1] == (ms)[1] && (md)[2] == (ms)[2] && (md)[3] == (ms)[3] && (md)[4] == (ms)[4] && (md)[5] == (ms)[5])
#define MAC_MATCH16(md, ms) ((md)[0] == (ms)[0] && (md)[1] == (ms)[1] && (md)[2] == (ms)[2])
#define MAC_MATCH32(md, ms) ((md)[0] == (ms)[0] && (md)[1] == (ms)[1])
/////////////////////////////////////////////////////////////////////////////
/******************************************** ATT ***************************************************************/
@@ -224,9 +223,9 @@ typedef enum {
ATT_OP_HANDLE_VALUE_IND = 0x1D,
ATT_OP_HANDLE_VALUE_CFM = 0x1E,
ATT_OP_READ_MULTIPLE_VARIABLE_REQ = 0x20, //core_5.2
ATT_OP_READ_MULTIPLE_VARIABLE_RSP = 0x21, //core_5.2
ATT_OP_MULTIPLE_HANDLE_VALUE_NTF = 0x23, //core_5.2
ATT_OP_READ_MULTIPLE_VARIABLE_REQ = 0x20, // core_5.2
ATT_OP_READ_MULTIPLE_VARIABLE_RSP = 0x21, // core_5.2
ATT_OP_MULTIPLE_HANDLE_VALUE_NTF = 0x23, // core_5.2
ATT_OP_WRITE_CMD = 0x52,
ATT_OP_SIGNED_WRITE_CMD = 0xD2,
@@ -272,20 +271,20 @@ typedef enum {
L2CAP_LE_CREDIT_BASED_CONNECTION_REQ = 0x14,
L2CAP_LE_CREDIT_BASED_CONNECTION_RSP = 0x15,
L2CAP_FLOW_CONTROL_CREDIT_IND = 0x16,
L2CAP_CREDIT_BASED_CONNECTION_REQ = 0x17, //core_5.2
L2CAP_CREDIT_BASED_CONNECTION_RSP = 0x18, //core_5.2
L2CAP_CREDIT_BASED_RECONFIGURE_REQ = 0x19, //core_5.2
L2CAP_CREDIT_BASED_RECONFIGURE_RSP = 0x1A, //core_5.2
L2CAP_CREDIT_BASED_CONNECTION_REQ = 0x17, // core_5.2
L2CAP_CREDIT_BASED_CONNECTION_RSP = 0x18, // core_5.2
L2CAP_CREDIT_BASED_RECONFIGURE_REQ = 0x19, // core_5.2
L2CAP_CREDIT_BASED_RECONFIGURE_RSP = 0x1A, // core_5.2
} l2cap_sig_pkt_format;
/******************************************** LINKLAYER ***************************************************************/
/**
* @brief Definition for LL Control PDU Opcode
*/ // rf_len without MIC
*/ // rf_len without MIC
#define LL_CONNECTION_UPDATE_REQ 0x00 // 12
#define LL_CHANNEL_MAP_REQ 0x01 // 8
#define LL_TERMINATE_IND 0x02 // 2
#define LL_CHANNEL_MAP_REQ 0x01 // 8
#define LL_TERMINATE_IND 0x02 // 2
#define LL_ENC_REQ 0x03 // encryption // 23
#define LL_ENC_RSP 0x04 // encryption // 13
@@ -301,32 +300,32 @@ typedef enum {
#define LL_VERSION_IND 0x0C // 6
#define LL_REJECT_IND 0x0D // 2
#define LL_SLAVE_FEATURE_REQ 0x0E //core_4.1 // 9
#define LL_CONNECTION_PARAM_REQ 0x0F //core_4.1 // 24
#define LL_CONNECTION_PARAM_RSP 0x10 //core_4.1 // 24
#define LL_REJECT_IND_EXT 0x11 //core_4.1 // 3
#define LL_PING_REQ 0x12 //core_4.1 // 1
#define LL_PING_RSP 0x13 //core_4.1 // 1
#define LL_LENGTH_REQ 0x14 //core_4.2 // 9
#define LL_LENGTH_RSP 0x15 //core_4.2 // 9
#define LL_PHY_REQ 0x16 //core_5.0 // 3
#define LL_PHY_RSP 0x17 //core_5.0 // 3
#define LL_PHY_UPDATE_IND 0x18 //core_5.0 // 5
#define LL_MIN_USED_CHN_IND 0x19 //core_5.0 // 3
#define LL_SLAVE_FEATURE_REQ 0x0E // core_4.1 // 9
#define LL_CONNECTION_PARAM_REQ 0x0F // core_4.1 // 24
#define LL_CONNECTION_PARAM_RSP 0x10 // core_4.1 // 24
#define LL_REJECT_IND_EXT 0x11 // core_4.1 // 3
#define LL_PING_REQ 0x12 // core_4.1 // 1
#define LL_PING_RSP 0x13 // core_4.1 // 1
#define LL_LENGTH_REQ 0x14 // core_4.2 // 9
#define LL_LENGTH_RSP 0x15 // core_4.2 // 9
#define LL_PHY_REQ 0x16 // core_5.0 // 3
#define LL_PHY_RSP 0x17 // core_5.0 // 3
#define LL_PHY_UPDATE_IND 0x18 // core_5.0 // 5
#define LL_MIN_USED_CHN_IND 0x19 // core_5.0 // 3
#define LL_CTE_REQ 0x1A //core_5.1 // 2
#define LL_CTE_RSP 0x1B //core_5.1 // 2
#define LL_PERIODIC_SYNC_IND 0x1C //core_5.1 // 35
#define LL_CLOCK_ACCURACY_REQ 0x1D //core_5.1 // 2
#define LL_CLOCK_ACCURACY_RSP 0x1E //core_5.1 // 2
#define LL_CTE_REQ 0x1A // core_5.1 // 2
#define LL_CTE_RSP 0x1B // core_5.1 // 2
#define LL_PERIODIC_SYNC_IND 0x1C // core_5.1 // 35
#define LL_CLOCK_ACCURACY_REQ 0x1D // core_5.1 // 2
#define LL_CLOCK_ACCURACY_RSP 0x1E // core_5.1 // 2
#define LL_CIS_REQ 0x1F //core_5.2 // 36
#define LL_CIS_RSP 0x20 //core_5.2 // 9
#define LL_CIS_IND 0x21 //core_5.2 // 16
#define LL_CIS_TERMINATE_IND 0x22 //core_5.2 // 4
#define LL_POWER_CONTROL_REQ 0x23 //core_5.2 // 4
#define LL_POWER_CONTROL_RSP 0x24 //core_5.2 // 5
#define LL_POWER_CHANGE_IND 0x25 //core_5.2 // 5
#define LL_CIS_REQ 0x1F // core_5.2 // 36
#define LL_CIS_RSP 0x20 // core_5.2 // 9
#define LL_CIS_IND 0x21 // core_5.2 // 16
#define LL_CIS_TERMINATE_IND 0x22 // core_5.2 // 4
#define LL_POWER_CONTROL_REQ 0x23 // core_5.2 // 4
#define LL_POWER_CONTROL_RSP 0x24 // core_5.2 // 5
#define LL_POWER_CHANGE_IND 0x25 // core_5.2 // 5
/******************************************** GAP ***************************************************************/
@@ -334,26 +333,26 @@ typedef enum {
// EIR Data Type, Advertising Data Type (AD Type) and OOB Data Type Definitions
typedef enum {
DT_FLAGS = 0x01, // Flag
DT_INCOMPLT_LIST_16BIT_SERVICE_UUID = 0x02, // Incomplete List of 16-bit Service Class UUIDs
DT_COMPLETE_LIST_16BIT_SERVICE_UUID = 0x03, // Complete List of 16-bit Service Class UUIDs
DT_INCOMPLT_LIST_32BIT_SERVICE_UUID = 0x04, // Incomplete List of 32-bit Service Class UUIDs
DT_COMPLETE_LIST_32BIT_SERVICE_UUID = 0x05, // Complete List of 32-bit Service Class UUIDs
DT_INCOMPLT_LIST_128BIT_SERVICE_UUID = 0x06, // Incomplete List of 128-bit Service Class UUIDs
DT_COMPLETE_LIST_128BIT_SERVICE_UUID = 0x07, // Complete List of 128-bit Service Class UUIDs
DT_SHORTENED_LOCAL_NAME = 0x08, // Shortened Local Name
DT_COMPLETE_LOCAL_NAME = 0x09, // Complete Local Name
DT_TX_POWER_LEVEL = 0x0A, // Tx Power Level
DT_FLAGS = 0x01, // Flag
DT_INCOMPLT_LIST_16BIT_SERVICE_UUID = 0x02, // Incomplete List of 16-bit Service Class UUIDs
DT_COMPLETE_LIST_16BIT_SERVICE_UUID = 0x03, // Complete List of 16-bit Service Class UUIDs
DT_INCOMPLT_LIST_32BIT_SERVICE_UUID = 0x04, // Incomplete List of 32-bit Service Class UUIDs
DT_COMPLETE_LIST_32BIT_SERVICE_UUID = 0x05, // Complete List of 32-bit Service Class UUIDs
DT_INCOMPLT_LIST_128BIT_SERVICE_UUID = 0x06, // Incomplete List of 128-bit Service Class UUIDs
DT_COMPLETE_LIST_128BIT_SERVICE_UUID = 0x07, // Complete List of 128-bit Service Class UUIDs
DT_SHORTENED_LOCAL_NAME = 0x08, // Shortened Local Name
DT_COMPLETE_LOCAL_NAME = 0x09, // Complete Local Name
DT_TX_POWER_LEVEL = 0x0A, // Tx Power Level
DT_CLASS_OF_DEVICE = 0x0D, // Class of Device
DT_CLASS_OF_DEVICE = 0x0D, // Class of Device
DT_APPEARANCE = 0x19, // Appearance
DT_APPEARANCE = 0x19, // Appearance
DT_BIGINFO = 0x2C, // BIGInfo
DT_BROADCAST_CODE = 0x2D, // Broadcast_Code
DT_3D_INFORMATION_DATA = 0x3D, // 3D Information Data
DATA_TYPE_MANUFACTURER_SPECIFIC_DATA = 0xFF, // Manufacturer Specific Data
DATA_TYPE_MANUFACTURER_SPECIFIC_DATA = 0xFF, // Manufacturer Specific Data
} data_type_t;
#endif
b91/b91_ble_sdk/stack/ble/ble_config.h
+2 -4
View File
@@ -15,8 +15,6 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef BLE_CONFIG_H
#define BLE_CONFIG_H
@@ -47,7 +45,7 @@
#define BLS_BLE_RF_IRQ_TIMING_EXTREMELY_SHORT_EN 0
//conn param update/map update
// conn param update/map update
#ifndef BLS_PROC_MASTER_UPDATE_REQ_IN_IRQ_ENABLE
#define BLS_PROC_MASTER_UPDATE_REQ_IN_IRQ_ENABLE 1
#endif
@@ -60,7 +58,7 @@
#define HOST_CONTROLLER_DATA_FLOW_IMPROVE_EN 1
#endif
//Link layer feature enable flag default setting
// Link layer feature enable flag default setting
#ifndef BLE_CORE42_DATA_LENGTH_EXTENSION_ENABLE
#define BLE_CORE42_DATA_LENGTH_EXTENSION_ENABLE 1
#endif
b91/b91_ble_sdk/stack/ble/ble_format.h
+101 -164
View File
@@ -22,14 +22,12 @@
/******************************************** Link Layer **************************************************************/
typedef struct
{
typedef struct {
u8 type;
u8 address[BLE_ADDR_LEN];
} addr_t;
typedef struct
{
typedef struct {
u8 llid : 2;
u8 nesn : 1;
u8 sn : 1;
@@ -37,8 +35,7 @@ typedef struct
u8 rfu1 : 3;
} rf_data_head_t;
typedef struct
{
typedef struct {
u8 llid : 2;
u8 nesn : 1;
u8 sn : 1;
@@ -47,8 +44,7 @@ typedef struct
u8 rf_len;
} rf_acl_data_head_t;
typedef struct
{
typedef struct {
u8 llid : 2;
u8 nesn : 1;
u8 sn : 1;
@@ -59,8 +55,7 @@ typedef struct
u8 rf_len;
} rf_cis_data_hdr_t;
typedef struct
{
typedef struct {
u8 llid : 2;
u8 cssn : 3;
u8 cstf : 1;
@@ -68,8 +63,7 @@ typedef struct
u8 rf_len;
} rf_bis_data_hdr_t;
typedef struct
{
typedef struct {
u32 dma_len;
u8 type : 4;
@@ -78,14 +72,13 @@ typedef struct
u8 txAddr : 1;
u8 rxAddr : 1;
u8 rf_len; //LEN(6)_RFU(2)
u8 rf_len; // LEN(6)_RFU(2)
u8 advA[6]; //address
u8 advA[6]; // address
u8 data[31];
} rf_packet_adv_t;
typedef struct
{
typedef struct {
u32 dma_len;
u8 type : 4;
@@ -94,14 +87,13 @@ typedef struct
u8 txAddr : 1;
u8 rxAddr : 1;
u8 rf_len; //LEN(6)_RFU(2)
u8 rf_len; // LEN(6)_RFU(2)
u8 scanA[6]; //
u8 advA[6]; //
u8 scanA[6];
u8 advA[6];
} rf_packet_scan_req_t;
typedef struct
{
typedef struct {
u32 dma_len;
u8 type : 4;
@@ -110,14 +102,13 @@ typedef struct
u8 txAddr : 1;
u8 rxAddr : 1;
u8 rf_len; //LEN(6)_RFU(2)
u8 rf_len; // LEN(6)_RFU(2)
u8 advA[6]; //address
u8 data[31]; //0-31 byte
u8 advA[6]; // address
u8 data[31]; // 0-31 byte
} rf_packet_scan_rsp_t;
typedef struct
{
typedef struct {
u32 dma_len;
u8 type : 4;
@@ -126,10 +117,10 @@ typedef struct
u8 txAddr : 1;
u8 rxAddr : 1;
u8 rf_len; //LEN(6)_RFU(2)
u8 initA[6]; //scanA
u8 advA[6]; //
u8 accessCode[4]; // access code
u8 rf_len; // LEN(6)_RFU(2)
u8 initA[6]; // scanA
u8 advA[6];
u8 accessCode[4]; // access code
u8 crcinit[3];
u8 winSize;
u16 winOffset;
@@ -137,11 +128,10 @@ typedef struct
u16 latency;
u16 timeout;
u8 chm[5];
u8 hop; //sca(3)_hop(5)
u8 hop; // sca(3)_hop(5)
} rf_packet_connect_t;
typedef struct
{
typedef struct {
u32 dma_len;
u8 type : 4;
@@ -150,10 +140,10 @@ typedef struct
u8 txAddr : 1;
u8 rxAddr : 1;
u8 rf_len; //LEN(6)_RFU(2)
u8 scanA[6]; //
u8 advA[6]; //
u8 aa[4]; // access code
u8 rf_len; // LEN(6)_RFU(2)
u8 scanA[6];
u8 advA[6];
u8 aa[4]; // access code
u8 crcinit[3];
u8 wsize;
u16 woffset;
@@ -161,11 +151,10 @@ typedef struct
u16 latency;
u16 timeout;
u8 chm[5];
u8 hop; //sca(3)_hop(5)
u8 hop; // sca(3)_hop(5)
} rf_packet_ll_init_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
@@ -177,8 +166,7 @@ typedef struct
u16 instant;
} rf_packet_ll_updateConnPara_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
@@ -190,8 +178,7 @@ typedef struct
u16 instant;
} rf_packet_connect_upd_req_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
@@ -199,8 +186,7 @@ typedef struct
u16 instant;
} rf_packet_chm_upd_req_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
@@ -210,8 +196,7 @@ typedef struct
u8 ivm[4];
} rf_packet_ll_enc_req_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
@@ -219,24 +204,21 @@ typedef struct
u8 ivs[4];
} rf_packet_ll_enc_rsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
u8 unknownType;
} rf_packet_ll_unknown_rsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
u8 featureSet[8];
} rf_packet_ll_feature_exg_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
@@ -245,16 +227,14 @@ typedef struct
u16 subVersNr;
} rf_packet_version_ind_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
u8 errCode;
} rf_packet_ll_reject_ind_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
@@ -262,16 +242,14 @@ typedef struct
u8 errCode;
} rf_packet_ll_reject_ext_ind_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
u8 reason;
} rf_packet_ll_terminate_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
@@ -286,50 +264,46 @@ typedef struct
u32 maxSduS2M : 12;
u32 rfu1 : 4;
u8 sduIntvlM2S[3]; //SDU_Interval_M_To_S(20 bits) + RFU(4 bits)
u8 sduIntvlS2M[3]; //SDU_Interval_S_To_M(20 bits) + RFU(4 bits)
u8 sduIntvlM2S[3]; // SDU_Interval_M_To_S(20 bits) + RFU(4 bits)
u8 sduIntvlS2M[3]; // SDU_Interval_S_To_M(20 bits) + RFU(4 bits)
u16 maxPduM2S;
u16 maxPduS2M;
u8 nse;
u8 subIntvl[3]; //unit: uS
u8 subIntvl[3]; // unit: uS
u8 bnM2S : 4;
u8 bnS2M : 4;
u8 ftM2S;
u8 ftS2M;
u16 isoIntvl; //unit: 1.25 mS
u16 isoIntvl; // unit: 1.25 mS
u8 cisOffsetMin[3];
u8 cisOffsetMax[3];
u16 connEventCnt; //similar to instant
u16 connEventCnt; // similar to instant
} rf_packet_ll_cis_req_t;
typedef struct
{
u8 type; //RA(1)_TA(1)_RFU(2)_TYPE(4)
u8 rf_len; //LEN(6)_RFU(2)
typedef struct {
u8 type; // RA(1)_TA(1)_RFU(2)_TYPE(4)
u8 rf_len; // LEN(6)_RFU(2)
u8 opcode;
u8 cisOffsetMin[3];
u8 cisOffsetMax[3];
u16 connEventCnt;
} rf_packet_ll_cis_rsp_t;
typedef struct
{
u8 type; //RA(1)_TA(1)_RFU(2)_TYPE(4)
u8 rf_len; //LEN(6)_RFU(2)
typedef struct {
u8 type; // RA(1)_TA(1)_RFU(2)_TYPE(4)
u8 rf_len; // LEN(6)_RFU(2)
u8 opcode;
u32 cisAccessAddr; //Access Address of the CIS
u32 cisAccessAddr; // Access Address of the CIS
u8 cisOffset[3];
u8 cigSyncDly[3];
u8 cisSyncDly[3];
u16 connEventCnt;
} rf_packet_ll_cis_ind_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode;
@@ -338,24 +312,20 @@ typedef struct
u8 errorCode;
} rf_packet_ll_cis_terminate_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u8 opcode; //
u8 dat[1]; //
u8 opcode;
u8 dat[1];
} rf_packet_ll_control_t;
typedef struct
{
union
{
typedef struct {
union {
rf_bis_data_hdr_t bisPduHdr;
rf_cis_data_hdr_t cisPduHdr;
rf_acl_data_head_t aclPduHdr;
struct
{
struct {
u8 type;
u8 rf_len;
} pduHdr;
@@ -363,15 +333,13 @@ typedef struct
u8 llPayload[1]; /* Max LL Payload length: 251 */
} llPhysChnPdu_t;
typedef struct
{
typedef struct {
u32 dma_len;
llPhysChnPdu_t llPhysChnPdu;
} rf_packet_ll_data_t;
//AuxPrt
typedef struct
{
// AuxPrt
typedef struct {
u8 chn_index : 6;
u8 ca : 1;
u8 offset_unit : 1;
@@ -379,8 +347,7 @@ typedef struct
u16 aux_phy : 3;
} aux_ptr_t;
typedef struct
{
typedef struct {
u32 dma_len;
u8 type : 4;
@@ -394,13 +361,12 @@ typedef struct
u8 adv_mode : 2;
u8 ext_hdr_flg;
u8 data[253]; //Extended Header + AdvData
u8 data[253]; // Extended Header + AdvData
} rf_pkt_ext_adv_t;
/******************************************** L2CAP **************************************************************/
typedef struct
{
typedef struct {
rf_data_head_t header;
u8 rf_len;
u16 l2capLen;
@@ -409,8 +375,7 @@ typedef struct
u8 data[1];
} rf_packet_l2cap_t;
typedef struct
{
typedef struct {
rf_data_head_t header;
u8 rf_len;
u16 l2capLen;
@@ -420,8 +385,7 @@ typedef struct
u8 dat[20];
} rf_packet_att_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -430,8 +394,7 @@ typedef struct
u8 data[1];
} rf_packet_l2cap_req_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -442,8 +405,7 @@ typedef struct
u16 result;
} rf_pkt_l2cap_sig_connParaUpRsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -457,8 +419,8 @@ typedef struct
u16 init_credits;
u16 scid[5];
} rf_pkt_l2cap_credit_based_connection_req_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -472,8 +434,8 @@ typedef struct
u16 result;
u16 dcid[5];
} rf_pkt_l2cap_credit_based_connection_rsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -485,8 +447,8 @@ typedef struct
u16 mps;
u16 dcid[5];
} rf_pkt_l2cap_credit_based_reconfigure_req_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -497,8 +459,7 @@ typedef struct
u16 result;
} rf_pkt_l2cap_credit_based_reconfigure_rsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -507,8 +468,7 @@ typedef struct
u8 data[1];
} rf_pkt_l2cap_req_t;
typedef struct
{
typedef struct {
u8 llid;
u8 rf_len;
u16 l2capLen;
@@ -521,8 +481,8 @@ typedef struct
u16 latency;
u16 timeout;
} rf_packet_l2cap_connParaUpReq_t;
typedef struct
{
typedef struct {
u8 llid;
u8 rf_len;
u16 l2capLen;
@@ -537,8 +497,7 @@ typedef struct
u16 scid[5];
} rf_packet_l2cap_credit_based_connection_req_t;
typedef struct
{
typedef struct {
u8 llid;
u8 rf_len;
u16 l2capLen;
@@ -550,8 +509,7 @@ typedef struct
} rf_packet_l2cap_connParaUpRsp_t;
/******************************************** ATT **************************************************************/
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2cap;
@@ -562,11 +520,9 @@ typedef struct
u8 hh;
u8 dat[20];
} rf_packet_att_data_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -577,8 +533,7 @@ typedef struct
u8 errReason;
} rf_packet_att_errRsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
@@ -592,8 +547,7 @@ typedef struct
u8 attType[2]; //
} rf_packet_att_readByType_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
@@ -608,8 +562,7 @@ typedef struct
u8 attValue[2];
} rf_packet_att_findByTypeReq_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
@@ -619,8 +572,7 @@ typedef struct
u16 data[1];
} rf_packet_att_findByTypeRsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -630,8 +582,7 @@ typedef struct
u8 handle1;
} rf_packet_att_read_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -643,8 +594,7 @@ typedef struct
u8 offset1;
} rf_packet_att_readBlob_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -653,8 +603,7 @@ typedef struct
u8 value[22];
} rf_packet_att_readRsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -664,8 +613,7 @@ typedef struct
u8 data[1]; // character_handle / property / value_handle / value
} rf_pkt_att_readByTypeRsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -675,8 +623,7 @@ typedef struct
u8 data[1]; // character_handle / property / value_handle / value
} rf_packet_att_readByTypeRsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -686,8 +633,7 @@ typedef struct
u8 data[3];
} rf_packet_att_readByGroupTypeRsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -697,8 +643,7 @@ typedef struct
u8 data[1]; // character_handle / property / value_handle / value
} rf_packet_att_findInfoReq_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -707,8 +652,7 @@ typedef struct
u8 flags;
} rf_packet_att_executeWriteReq_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -719,8 +663,7 @@ typedef struct
u8 value;
} rf_packet_att_write_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -730,8 +673,7 @@ typedef struct
u8 data;
} rf_packet_att_notification_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -740,8 +682,7 @@ typedef struct
u8 mtu[2];
} rf_packet_att_mtu_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -750,8 +691,7 @@ typedef struct
u8 mtu[2];
} rf_packet_att_mtu_exchange_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -759,8 +699,7 @@ typedef struct
u8 opcode;
} rf_packet_att_writeRsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -770,8 +709,7 @@ typedef struct
u8 data[1]; // character_handle / property / value_handle / value
} att_readByTypeRsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
@@ -781,8 +719,7 @@ typedef struct
u8 data[1]; // character_handle / property / value_handle / value
} att_findInfoRsp_t;
typedef struct
{
typedef struct {
u8 type;
u8 rf_len;
u16 l2capLen;
b91/b91_ble_sdk/stack/ble/controller/ble_controller.h
+1 -1
View File
@@ -44,7 +44,7 @@
#include "algorithm/ecc/ecc_ll.h"
/*********************************************************/
//Remove when file merge to SDK //
// Remove when file merge to SDK //
/*********************************************************/
b91/b91_ble_sdk/stack/ble/controller/ll/ll.h
+2 -3
View File
@@ -62,8 +62,7 @@ typedef int (*blc_main_loop_phyTest_callback_t)(void);
#define BLT_EV_FLAG_SUSPEND_ENTER 14
#define BLT_EV_FLAG_SUSPEND_EXIT 15
typedef struct
{
typedef struct {
u16 connEffectiveMaxRxOctets;
u16 connEffectiveMaxTxOctets;
u16 connMaxRxOctets;
@@ -73,7 +72,7 @@ typedef struct
u16 supportedMaxRxOctets;
u16 supportedMaxTxOctets;
u8 connInitialMaxTxOctets; //u8 is enough
u8 connInitialMaxTxOctets; // u8 is enough
u8 connMaxTxRxOctets_req;
u8 connRxDiff100;
u8 connTxDiff100;
b91/b91_ble_sdk/stack/ble/controller/ll/ll_adv.h
+5 -3
View File
@@ -84,10 +84,12 @@ ble_sts_t bls_ll_setAdvDuration(u32 duration_us, u8 duration_en);
*/
void blc_ll_setAdvCustomedChannel(u8 chn0, u8 chn1, u8 chn2);
extern u8
blc_continue_adv_en; //default stop sending legacy advertising packets when receiving scan request in the current adv interval.
/* default stop sending legacy advertising packets when receiving scan request in the current adv interval. */
extern u8 blc_continue_adv_en;
/**
* @brief this function is used to set whether to continue sending legacy advertising packets when receiving scan request in the current adv interval.
* @brief this function is used to set whether to continue sending legacy advertising packets .
* when receiving scan request in the current adv interval
* @param[in] enable - enable:continue sending broadcast packets when receiving scan request.
* @return none.
*/
b91/b91_ble_sdk/stack/ble/controller/ll/ll_ext_adv.h
+15 -17
View File
@@ -23,18 +23,17 @@
/**
* @brief Primary channel advertising packet data buffer size
*/
#define MAX_LENGTH_PRIMARY_ADV_PKT 44 //sizeof(rf_pkt_pri_adv_t) = 43
#define MAX_LENGTH_PRIMARY_ADV_PKT 44 // sizeof(rf_pkt_pri_adv_t) = 43
/**
* @brief Secondary channel advertising packet data buffer size
*/
#define MAX_LENGTH_SECOND_ADV_PKT 264 //sizeof(rf_pkt_ext_adv_t) = 261
#define MAX_LENGTH_SECOND_ADV_PKT 264 // sizeof(rf_pkt_ext_adv_t) = 261
/**
* @brief Primary advertising packet format
*/
typedef struct
{
typedef struct {
u32 dma_len;
u8 type : 4;
@@ -44,13 +43,12 @@ typedef struct
u8 rxAddr : 1;
u8 rf_len;
u8 advA[6]; //address
u8 data[31]; //0-31 byte
u8 advA[6]; // address
u8 data[31]; // 0-31 byte
} rf_pkt_pri_adv_t;
//NOTE: this data structure must 4 bytes aligned
typedef struct
{
// NOTE: this data structure must 4 bytes aligned
typedef struct {
u8 adv_handle;
u8 extAdv_en;
u8 adv_chn_mask;
@@ -68,32 +66,32 @@ typedef struct
u8 adv_filterPolicy;
u8 scan_req_noti_en;
u8 coding_ind; //s2 or s8
u8 coding_ind; // s2 or s8
u8 param_update_flag;
u8 with_aux_adv_ind; //ADV_EXT_IND with AUX_ADV_IND
u8 with_aux_adv_ind; // ADV_EXT_IND with AUX_ADV_IND
u8 with_aux_chain_ind;
u8 rand_adr_flg;
u8 adv_sid;
u16 adv_did; // BIT<11:0>
u16 adv_did; // BIT<11:0>
u16 evt_props;
u16 advInt_use;
u16 send_dataLen;
u16 maxLen_advData; //for each ADV sets, this value can be different to save SRAM
u16 maxLen_advData; // for each ADV sets, this value can be different to save SRAM
u16 curLen_advData;
u16 maxLen_scanRsp; //for each ADV sets, this value can be different to save SRAM
u16 maxLen_scanRsp; // for each ADV sets, this value can be different to save SRAM
u16 curLen_scanRsp;
u16 send_dataLenBackup;
u16 rsvd_16_1;
u32 adv_duration_tick;
u32 adv_begin_tick; //24
u32 adv_begin_tick; // 24
u32 adv_event_tick;
u8 *dat_extAdv;
u8 *dat_scanRsp; //Scan response data.
u8 *dat_scanRsp; // Scan response data.
rf_pkt_pri_adv_t *primary_adv;
rf_pkt_ext_adv_t *secondary_adv;
@@ -101,7 +99,7 @@ typedef struct
u8 peer_addr[6];
} ll_ext_adv_t;
#define ADV_SET_PARAM_LENGTH (sizeof(ll_ext_adv_t)) //sizeof(ll_ext_adv_t) = , must 4 byte aligned
#define ADV_SET_PARAM_LENGTH (sizeof(ll_ext_adv_t)) // sizeof(ll_ext_adv_t) = , must 4 byte aligned
/**
* @brief this function is used to initialize extended advertising module
b91/b91_ble_sdk/stack/ble/controller/ll/ll_pm.h
+1 -1
View File
@@ -85,7 +85,7 @@ u32 bls_pm_getNexteventWakeupTick(void);
* @param latency - bltPm.user_latency
* @return none
*/
void bls_pm_setManualLatency(u16 latency); //manual set latency to save power
void bls_pm_setManualLatency(u16 latency);
/**
* @brief for user to set application wake up low power mode
b91/b91_ble_sdk/stack/ble/controller/phy/phy_test.h
+3 -3
View File
@@ -28,15 +28,15 @@
#endif
#ifndef PHYTEST_MODE_THROUGH_2_WIRE_UART
#define PHYTEST_MODE_THROUGH_2_WIRE_UART 1 //Direct Test Mode through a 2-wire UART interface
#define PHYTEST_MODE_THROUGH_2_WIRE_UART 1 // Direct Test Mode through a 2-wire UART interface
#endif
#ifndef PHYTEST_MODE_OVER_HCI_WITH_USB
#define PHYTEST_MODE_OVER_HCI_WITH_USB 2 //Direct Test Mode over HCI(UART hardware interface)
#define PHYTEST_MODE_OVER_HCI_WITH_USB 2 // Direct Test Mode over HCI(UART hardware interface)
#endif
#ifndef PHYTEST_MODE_OVER_HCI_WITH_UART
#define PHYTEST_MODE_OVER_HCI_WITH_UART 3 //Direct Test Mode over HCI(USB hardware interface)
#define PHYTEST_MODE_OVER_HCI_WITH_UART 3 // Direct Test Mode over HCI(USB hardware interface)
#endif
/**
b91/b91_ble_sdk/stack/ble/hci/hci.h
+22 -20
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_STACK_BLE_HCI_HCI_H
#define B91_B91_BLE_SDK_STACK_BLE_HCI_HCI_H
#include <stack/ble/ble_common.h>
@@ -42,8 +43,7 @@ typedef int (*blc_hci_app_handler_t)(unsigned char *p);
extern my_fifo_t hci_tx_iso_fifo;
typedef struct
{
typedef struct {
u32 size;
u8 num;
u8 mask;
@@ -66,35 +66,35 @@ typedef enum {
HCI_TYPE_ACL_DATA = 0x02,
HCI_TYPE_SCO_DATA = 0x03,
HCI_TYPE_EVENT = 0x04,
HCI_TYPE_ISO_DATA = 0x05, //core_5.2
HCI_TYPE_ISO_DATA = 0x05, // core_5.2
} hci_type_t;
/**
* @brief Definition for HCI ACL Data packets Packet_Boundary_Flag
*/
typedef enum {
HCI_FIRST_NAF_PACKET = 0x00, //LE Host to Controller
HCI_CONTINUING_PACKET = 0x01, //LE Host to Controller / Controller to Host
HCI_FIRST_AF_PACKET = 0x02, //LE Controller to Host
HCI_FIRST_NAF_PACKET = 0x00, // LE Host to Controller
HCI_CONTINUING_PACKET = 0x01, // LE Host to Controller / Controller to Host
HCI_FIRST_AF_PACKET = 0x02, // LE Controller to Host
} acl_pb_flag_t;
/**
* @brief Definition for HCI ISO Data packets PB_Flag
*/
typedef enum {
HCI_ISO_SDU_FIRST_FRAG = 0x00, //The ISO_Data_Load field contains the first fragment of a fragmented SDU
HCI_ISO_SDU_CONTINUE_FRAG = 0x01, //The ISO_Data_Load field contains a continuation fragment of an SDU
HCI_ISO_SDU_COMPLETE = 0x02, //The ISO_Data_Load field contains a complete SDU
HCI_ISO_SDU_LAST_FRAG = 0x03, //The ISO_Data_Load field contains the last fragment of an SDU.
HCI_ISO_SDU_FIRST_FRAG = 0x00, // The ISO_Data_Load field contains the first fragment of a fragmented SDU
HCI_ISO_SDU_CONTINUE_FRAG = 0x01, // The ISO_Data_Load field contains a continuation fragment of an SDU
HCI_ISO_SDU_COMPLETE = 0x02, // The ISO_Data_Load field contains a complete SDU
HCI_ISO_SDU_LAST_FRAG = 0x03, // The ISO_Data_Load field contains the last fragment of an SDU.
} iso_pb_flag_t;
/**
* @brief Definition for HCI ISO Data packets Packet_Status_Flag
*/
typedef enum {
HCI_ISO_VALID_DATA = 0x00, //Valid data. The complete ISO_SDU was received correctly
HCI_ISO_POSSIBLE_VALID_DATA = 0x01, //Possibly invalid data
HCI_ISO_LOST_DATA = 0x02, //Part(s) of the ISO_SDU were not received correctly. This is reported as "lost data"
HCI_ISO_VALID_DATA = 0x00, // Valid data. The complete ISO_SDU was received correctly
HCI_ISO_POSSIBLE_VALID_DATA = 0x01, // Possibly invalid data
HCI_ISO_LOST_DATA = 0x02, // Part(s) of the ISO_SDU were not received correctly. This is reported as "lost data"
} iso_ps_flag_t;
// hci event
@@ -174,24 +174,24 @@ int blc_hci_proc(void);
/******************************* User Interface Begin *****************************************************************/
/**
* @brief this function is used to set HCI EVENT mask
* @param[in] evtMask - HCI¡¡EVENT¡¡mask
* @param[in] evtMask - HCI��EVENT��mask
* @return 0
*/
ble_sts_t blc_hci_setEventMask_cmd(u32 evtMask); //eventMask: BT/EDR
ble_sts_t blc_hci_setEventMask_cmd(u32 evtMask); // eventMask: BT/EDR
/**
* @brief this function is used to set HCI LE EVENT mask
* @param[in] evtMask - HCI¡¡LE EVENT¡¡mask(BIT<0-31>)
* @param[in] evtMask - HCI��LE EVENT��mask(BIT<0-31>)
* @return 0
*/
ble_sts_t blc_hci_le_setEventMask_cmd(u32 evtMask); //eventMask: LE event 0~31
ble_sts_t blc_hci_le_setEventMask_cmd(u32 evtMask); // eventMask: LE event 0~31
/**
* @brief this function is used to set HCI LE EVENT mask
* @param[in] evtMask - HCI¡¡LE EVENT¡¡mask(BIT<32-63>)
* @param[in] evtMask - HCI��LE EVENT��mask(BIT<32-63>)
* @return 0
*/
ble_sts_t blc_hci_le_setEventMask_2_cmd(u32 evtMask_2); //eventMask: LE event 32~63
ble_sts_t blc_hci_le_setEventMask_2_cmd(u32 evtMask_2); // eventMask: LE event 32~63
/**
* @brief this function is used to register HCI event handler callback function
@@ -225,3 +225,5 @@ int blc_hci_sendACLData2Host(u16 handle, u8 *p);
*/
int blc_hci_send_data(u32 h, u8 *para, int n);
/******************************* User Interface End ******************************************************************/
#endif // B91_B91_BLE_SDK_STACK_BLE_HCI_HCI_H
b91/b91_ble_sdk/stack/ble/hci/hci_cmd.h
+50 -90
View File
@@ -24,8 +24,7 @@
* @brief Command Parameters for "7.8.5 LE Set Advertising Parameters command"
*/
/* Advertising Parameters structure */
typedef struct
{
typedef struct {
u16 intervalMin; // Minimum advertising interval for non-directed advertising, time = N * 0.625ms
u16 intervalMax; // Maximum advertising interval for non-directed advertising, time = N * 0.625ms
u8 advType; // Advertising
@@ -103,14 +102,14 @@ typedef enum {
typedef enum {
ADV_FP_ALLOW_SCAN_ANY_ALLOW_CONN_ANY = 0x00, // Process scan and connection requests from all devices
ADV_FP_ALLOW_SCAN_WL_ALLOW_CONN_ANY =
0x01, // Process connection requests from all devices and only scan requests from devices that are in the White List.
0x01, // Process connection requests from all devices and only scan requests from devices in the White List.
ADV_FP_ALLOW_SCAN_ANY_ALLOW_CONN_WL =
0x02, // Process scan requests from all devices and only connection requests from devices that are in the White List..
0x02, // Process scan requests from all devices and only connection requests from devices in the White List.
ADV_FP_ALLOW_SCAN_WL_ALLOW_CONN_WL =
0x03, // Process scan and connection requests only from devices in the White List.
ADV_FP_NONE = ADV_FP_ALLOW_SCAN_ANY_ALLOW_CONN_ANY, //adv filter policy set to zero, not use whitelist
} adv_fp_type_t; //adv_filterPolicy_type_t
ADV_FP_NONE = ADV_FP_ALLOW_SCAN_ANY_ALLOW_CONN_ANY, // adv filter policy set to zero, not use whitelist
} adv_fp_type_t; // adv_filterPolicy_type_t
#define ALLOW_SCAN_WL BIT(0)
#define ALLOW_CONN_WL BIT(1)
@@ -189,11 +188,10 @@ typedef enum {
/* Scanning_Filter_Policy */
typedef enum {
SCAN_FP_ALLOW_ADV_ANY = 0x00, //except direct adv address not match
SCAN_FP_ALLOW_ADV_WL = 0x01, //except direct adv address not match
SCAN_FP_ALLOW_UNDIRECT_ADV = 0x02, //and direct adv address match initiator's resolvable private MAC
SCAN_FP_ALLOW_ADV_WL_DIRECT_ADV_MACTH = 0x03, //and direct adv address match initiator's resolvable private MAC
SCAN_FP_ALLOW_ADV_ANY = 0x00, // except direct adv address not match
SCAN_FP_ALLOW_ADV_WL = 0x01, // except direct adv address not match
SCAN_FP_ALLOW_UNDIRECT_ADV = 0x02, // and direct adv address match initiator's resolvable private MAC
SCAN_FP_ALLOW_ADV_WL_DIRECT_ADV_MACTH = 0x03, // and direct adv address match initiator's resolvable private MAC
} scan_fp_type_t;
/**
@@ -217,8 +215,8 @@ typedef enum {
/* Initiator_Filter_Policy */
typedef enum {
INITIATE_FP_ADV_SPECIFY = 0x00, //connect ADV specified by host
INITIATE_FP_ADV_WL = 0x01, //connect ADV in whiteList
INITIATE_FP_ADV_SPECIFY = 0x00, // connect ADV specified by host
INITIATE_FP_ADV_WL = 0x01, // connect ADV in whiteList
} init_fp_t;
/* Connection_Interval, Time = N * 1.25 ms,
@@ -305,8 +303,7 @@ typedef enum {
/**
* @brief Return Parameters for "7.8.46 LE Read Maximum Data Length command"
*/
typedef struct
{
typedef struct {
u8 status;
u16 support_max_tx_oct;
u16 support_max_tx_time;
@@ -317,8 +314,7 @@ typedef struct
/**
* @brief Return Parameters for "7.8.47 LE Read PHY command"
*/
typedef struct
{
typedef struct {
u8 status;
u8 handle[2];
u8 tx_phy;
@@ -333,8 +329,7 @@ typedef struct
* @brief Command Parameters for "7.8.49 LE Set PHY command"
*/
typedef struct
{
typedef struct {
u16 connHandle;
u8 all_phys;
u8 tx_phys;
@@ -355,23 +350,22 @@ typedef enum {
} le_phy_prefer_type_t;
typedef enum {
PHY_TRX_PREFER = 0, //has preference among TX & RX PHYs
PHY_TX_NO_PREFER = BIT(0), //has no preference among TX PHYs
PHY_RX_NO_PREFER = BIT(1), //has no preference among RX PHYs
PHY_TRX_NO_PREFER = (BIT(0) | BIT(1)), //has no preference among TX & RX PHYs
PHY_TRX_PREFER = 0, // has preference among TX & RX PHYs
PHY_TX_NO_PREFER = BIT(0), // has no preference among TX PHYs
PHY_RX_NO_PREFER = BIT(1), // has no preference among RX PHYs
PHY_TRX_NO_PREFER = (BIT(0) | BIT(1)), // has no preference among TX & RX PHYs
} le_phy_prefer_mask_t;
typedef enum {
CODED_PHY_PREFER_NONE = 0,
CODED_PHY_PREFER_S2 = 1,
CODED_PHY_PREFER_S8 = 2,
} le_ci_prefer_t; //LE coding indication prefer
} le_ci_prefer_t; // LE coding indication prefer
/**
* @brief Command Parameters for "7.8.53 LE Set Extended Advertising Parameters command"
*/
typedef struct
{
typedef struct {
u8 adv_handle;
u16 advEvt_props;
u8 pri_advIntMin[3];
@@ -396,7 +390,7 @@ typedef enum {
ADV_HANDLE2 = 0x02,
} adv_handle_t;
/* Advertising Event Properties mask*/
/* Advertising Event Properties mask */
typedef enum {
ADVEVT_PROP_MASK_CONNECTABLE = BIT(0),
ADVEVT_PROP_MASK_SCANNABLE = BIT(1),
@@ -414,7 +408,7 @@ typedef enum {
#define ADVEVT_PROP_MASK_LEGACY_CONNECTABLE_SCANNABLE \
(0x0013) // ADVEVT_PROP_MASK_LEGACY | ADVEVT_PROP_MASK_CONNECTABLE | ADVEVT_PROP_MASK_SCANNABLE
/* Advertising Event Properties type*/
/* Advertising Event Properties type */
typedef enum {
ADV_EVT_PROP_LEGACY_CONNECTABLE_SCANNABLE_UNDIRECTED = 0x0013, // 0001 0011'b ADV_IND
ADV_EVT_PROP_LEGACY_CONNECTABLE_DIRECTED_LOW_DUTY = 0x0015, // 0001 0101'b ADV_DIRECT_IND(low duty cycle)
@@ -432,10 +426,9 @@ typedef enum {
ADV_EVT_PROP_EXTENDED_SCANNABLE_DIRECTED = 0x0006, // 0000 0110'b ADV_EXT_IND + AUX_ADV_IND/AUX_CHAIN_IND
ADV_EVT_PROP_EXTENDED_MASK_ANONYMOUS_ADV =
0x0020, //if this mask on(only extended ADV event can mask it), anonymous advertising
0x0020, // if this mask on(only extended ADV event can mask it), anonymous advertising
ADV_EVT_PROP_EXTENDED_MASK_TX_POWER_INCLUDE =
0x0040, //if this mask on(only extended ADV event can mask it), TX power include
0x0040, // if this mask on(only extended ADV event can mask it), TX power include
} advEvtProp_type_t;
/* Advertising_TX_Power */
@@ -484,15 +477,13 @@ typedef enum {
* @brief Command Parameters for "7.8.56 LE Set Extended Advertising Enable command"
*/
typedef struct
{
typedef struct {
u8 adv_handle;
u16 duration;
u8 max_ext_adv_evts;
} extAdvEn_Cfg_t;
typedef struct
{
typedef struct {
u8 enable;
u8 num_sets;
extAdvEn_Cfg_t cisCfg[3]; // ADV_SETS_NUMBER_MAX
@@ -502,29 +493,25 @@ typedef struct
* @brief Command Parameters for "7.8.61 LE Set Periodic Advertising Parameters command"
*/
typedef enum {
PERD_ADV_PROP_MASK_NONE = 0,
PERD_ADV_PROP_MASK_TX_POWER_INCLUDE = BIT(6),
} perd_adv_prop_t;
/**
* @brief Command Parameters for "7.8.64 LE Set Extended Scan Parameters command"
*/
typedef struct
{
typedef struct {
u8 scan_type;
u16 scan_interval;
u16 scan_window;
} ext_scan_cfg_t;
typedef struct
{
typedef struct {
u8 ownAddress_type;
u8 scan_filter_policy;
u8 scan_PHYs;
ext_scan_cfg_t scanCfg[2]; //at most 2 kind of PHY: 1M and Coded
ext_scan_cfg_t scanCfg[2]; // at most 2 kind of PHY: 1M and Coded
} hci_le_setExtScan_cmdParam_t;
/* Scanning_PHYs */
@@ -568,8 +555,7 @@ typedef enum {
/**
* @brief Command Parameters for "7.8.66 LE Extended Create Connection command"
*/
typedef struct
{
typedef struct {
u16 scan_interval;
u16 scan_window;
u16 connInter_min;
@@ -580,8 +566,7 @@ typedef struct
u16 ceLen_max;
} ext_init_cfg_t;
typedef struct
{
typedef struct {
u8 init_filter_policy;
u8 ownAddr_type;
u8 peerAddr_type;
@@ -606,21 +591,18 @@ typedef enum {
*/
/* Options */
typedef enum {
/* BIT(0)
* 0: Use the adv_sid, adv_addr_type, and adv_address parameters to determine which advertiser to listen to.
* 1: Use the Periodic Advertiser List to determine which advertiser to listen to. */
SYNC_ADV_SPECIFY = 0,
SYNC_ADV_FROM_LIST = BIT(0),
/* BIT(1) ~ BIT(7) reserved */
} option_msk_t;
/**
* @brief Command Parameters for "7.8.97 LE Set CIG Parameters command"
*/
typedef struct
{
typedef struct {
u8 cig_id;
u8 sdu_int_m2s[3];
u8 sdu_int_s2m[3];
@@ -633,8 +615,7 @@ typedef struct
u8 *restparam;
} hci_le_setCigParam_cmdParam_t;
typedef struct
{
typedef struct {
u8 cis_id;
u8 nse;
u16 max_sdu_m2s;
@@ -674,8 +655,7 @@ typedef enum {
/**
* @brief Command Parameters for "7.8.98 LE Set CIG Parameters Test command"
*/
typedef struct
{
typedef struct {
u8 cig_id;
u8 sdu_int_m2s[3];
u8 sdu_int_s2m[3];
@@ -685,19 +665,18 @@ typedef struct
u8 sca;
u8 packing;
u8 framing;
u8 cis_count; //15 B above
cigParamTest_cisCfg_t cisCfg[1]; //14 B for one CIS configuration
u8 cis_count; // 15 B above
cigParamTest_cisCfg_t cisCfg[1]; // 14 B for one CIS configuration
} hci_le_setCigParamTest_cmdParam_t;
/**
* @brief Return Parameters for "LE Set CIG Parameters command" and "LE Set CIG Parameters Test command"
*/
typedef struct
{
typedef struct {
u8 status;
u8 cig_id;
u8 cis_count;
u16 cis_connHandle[LL_CIS_IN_CIG_NUM_MAX]; //not 4 byte aligned, but no problem
u16 cis_connHandle[LL_CIS_IN_CIG_NUM_MAX]; // not 4 byte aligned, but no problem
} hci_le_setCigParam_retParam_t;
/* ISO_Interval, Time = N * 1.25 ms,
@@ -727,34 +706,20 @@ typedef enum {
/**
* @brief Command Parameters for "7.8.99 LE Create CIS command"
*/
typedef struct
{
typedef struct {
u16 cis_handle;
u16 acl_handle;
} cisConnParams_t;
typedef struct
{
typedef struct {
u8 cis_count;
cisConnParams_t cisConn[1];
} hci_le_CreateCisParams_t;
#if 0
/**
* @brief Command Parameters for "7.8.102 LE Reject CIS Request command"
*/
typedef struct
{
u16 cis_handle;
u8 reason;
} hci_le_rejectCisReqParams_t;
#endif
/**
* @brief Command Parameters for "7.8.103 LE Create BIG command"
*/
typedef struct
{
typedef struct {
u8 big_handle; /* Used to identify the BIG */
u8 adv_handle; /* Used to identify the periodic advertising train */
u8 num_bis; /* Total number of BISes in the BIG */
@@ -763,8 +728,8 @@ typedef struct
u16 max_trans_lat; /* Maximum time, in milliseconds, for transmitting an SDU */
u8 rtn; /* The maximum number of times that every BIS Data PDU should be retransmitted */
u8 phy; /* The transmitter PHY of packets */
packing_type_t packing; //type same as u8
framing_t framing; //type same as u8
packing_type_t packing; /* type same as u8 */
framing_t framing; /* type same as u8 */
u8 enc; /* Encryption flag */
u8 broadcast_code
[16]; /* The code used to derive the session key that is used to encrypt and decrypt BIS payloads */
@@ -773,8 +738,7 @@ typedef struct
/**
* @brief Command Parameters for "7.8.104 LE Create BIG Test command"
*/
typedef struct
{
typedef struct {
u8 big_handle; /* Used to identify the BIG */
u8 adv_handle; /* Used to identify the periodic advertising train */
u8 num_bis; /* Total number of BISes in the BIG */
@@ -784,10 +748,10 @@ typedef struct
u16 max_sdu; /* Maximum size of an SDU, in octets */
u16 max_pdu; /* Maximum size, in octets, of payload */
u8 phy; /* The transmitter PHY of packets */
packing_type_t packing; //type same as u8
framing_t framing; //type same as u8
packing_type_t packing; /* type same as u8 */
framing_t framing; /* type same as u8 */
u8 bn; /* The number of new payloads in each interval for each BIS */
u8 irc; /* The number of times the scheduled payload(s) are transmitted in a given event*/
u8 irc; /* The number of times the scheduled payload(s) are transmitted in a given event */
u8 pto; /* Offset used for pre-transmissions */
u8 enc; /* Encryption flag */
u8 broadcast_code
@@ -797,14 +761,12 @@ typedef struct
/**
* @brief Command Parameters for "7.8.105 LE Terminate BIG command"
*/
typedef struct
{
typedef struct {
u8 big_handle;
u8 reason;
} hci_le_terminateBigParams_t;
typedef struct
{
typedef struct {
u8 big_handle; /* Used to identify the BIG */
u16 sync_handle; /* Identifier of the periodic advertising train */
u8 enc; /* Encryption flag */
@@ -820,8 +782,7 @@ typedef struct
/**
* @brief Command Parameters for "7.8.109 LE Setup ISO Data Path command"
*/
typedef struct
{
typedef struct {
u16 conn_handle;
u8 data_path_direction;
u8 data_path_id;
@@ -831,7 +792,6 @@ typedef struct
u32 codec_configration_length : 8;
u8 codec_config[1];
} hci_le_setupIsoDataPathCmdParams_t;
/**
b91/b91_ble_sdk/stack/ble/hci/hci_const.h
+152 -150
View File
@@ -20,11 +20,12 @@
#define HCI_CONST_H_
/****HCI INFO****/
#define HCI_VERSION 0x09 //Bluetooth Core Specification 5.0
#define HCI_REVISION 0x0002 //Revision of the Current HCI in the BR/EDR Controller
#define HCI_LMP_VERSION 0x09 //Version of the Current LMP or PAL in the Controller, Bluetooth Core Specification 5.0
#define HCI_MANUFACTURER_NAME VENDOR_ID //Manufacturer Name of the BR/EDR Controller
#define HCI_LMP_SUBVERSION 0x0001 //Subversion of the Current LMP or PAL in the Controller
#define HCI_VERSION 0x09 // Bluetooth Core Specification 5.0
#define HCI_REVISION 0x0002 // Revision of the Current HCI in the BR/EDR Controller
#define HCI_LMP_VERSION \
0x09 // Version of the Current LMP or PAL in the Controller, Bluetooth Core Specification 5.0
#define HCI_MANUFACTURER_NAME VENDOR_ID // Manufacturer Name of the BR/EDR Controller
#define HCI_LMP_SUBVERSION 0x0001 // Subversion of the Current LMP or PAL in the Controller
#define LMP_FEATURES 0x0000000000000000
@@ -45,66 +46,67 @@
#define HCI_EVT_CERT_VS 0xF0
// LE Meta Event Codes
#define HCI_SUB_EVT_LE_CONNECTION_COMPLETE 0x01 //core_4.0
#define HCI_SUB_EVT_LE_CONNECTION_COMPLETE 0x01 // core_4.0
#define HCI_SUB_EVT_LE_ADVERTISING_REPORT 0x02
#define HCI_SUB_EVT_LE_CONNECTION_UPDATE_COMPLETE 0x03
#define HCI_SUB_EVT_LE_READ_REMOTE_USED_FEATURES_COMPLETE 0x04
#define HCI_SUB_EVT_LE_LONG_TERM_KEY_REQUESTED 0x05 //core_4.0
#define HCI_SUB_EVT_LE_REMOTE_CONNECTION_PARAM_REQUEST 0x06 //core_4.1
#define HCI_SUB_EVT_LE_DATA_LENGTH_CHANGE 0x07 //core_4.2
#define HCI_SUB_EVT_LE_LONG_TERM_KEY_REQUESTED 0x05 // core_4.0
#define HCI_SUB_EVT_LE_REMOTE_CONNECTION_PARAM_REQUEST 0x06 // core_4.1
#define HCI_SUB_EVT_LE_DATA_LENGTH_CHANGE 0x07 // core_4.2
#define HCI_SUB_EVT_LE_READ_LOCAL_P256_KEY_COMPLETE 0x08
#define HCI_SUB_EVT_LE_GENERATE_DHKEY_COMPLETE 0x09
#define HCI_SUB_EVT_LE_ENHANCED_CONNECTION_COMPLETE 0x0A
#define HCI_SUB_EVT_LE_DIRECT_ADVERTISE_REPORT 0x0B //core_4.2
#define HCI_SUB_EVT_LE_DIRECT_ADVERTISE_REPORT 0x0B // core_4.2
#define HCI_SUB_EVT_LE_PHY_UPDATE_COMPLETE 0x0C //core_5.0
#define HCI_SUB_EVT_LE_PHY_UPDATE_COMPLETE 0x0C // core_5.0
#define HCI_SUB_EVT_LE_EXTENDED_ADVERTISING_REPORT \
0x0D //core_5.0 - LE Extended Advertising Report Event - [5] 7.7.65.13
0x0D // core_5.0 - LE Extended Advertising Report Event - [5] 7.7.65.13
#define HCI_SUB_EVT_LE_PERIODIC_ADVERTISING_SYNC_ESTABLISHED \
0x0E //core_5.0 - LE Periodic Advertising Sync Established Event - [5] 7.7.65.14
0x0E // core_5.0 - LE Periodic Advertising Sync Established Event - [5] 7.7.65.14
#define HCI_SUB_EVT_LE_PERIODIC_ADVERTISING_REPORT \
0x0F //core_5.0 - LE Periodic Advertising Report Event- [5] 7.7.65.15
0x0F // core_5.0 - LE Periodic Advertising Report Event- [5] 7.7.65.15
#define HCI_SUB_EVT_LE_PERIODIC_ADVERTISING_SYNC_LOST \
0x10 //core_5.0 - LE Periodic Advertising Sync Lost Event - [5] 7.7.65.16
#define HCI_SUB_EVT_LE_SCAN_TIMEOUT 0x11 //core_5.0 - LE Scan Timeout Event - [5] 7.7.65.17
#define HCI_SUB_EVT_LE_ADVERTISING_SET_TERMINATED 0x12 //core_5.0 - LE Advertising Set Terminated Event - [5]7.7.65.18
#define HCI_SUB_EVT_LE_SCAN_REQUEST_RECEIVED 0x13 //core_5.0 - LE Scan Request Received Event - [5]7.7.65.19
0x10 // core_5.0 - LE Periodic Advertising Sync Lost Event - [5] 7.7.65.16
#define HCI_SUB_EVT_LE_SCAN_TIMEOUT 0x11 // core_5.0 - LE Scan Timeout Event - [5] 7.7.65.17
#define HCI_SUB_EVT_LE_ADVERTISING_SET_TERMINATED \
0x12 // core_5.0 - LE Advertising Set Terminated Event - [5]7.7.65.18
#define HCI_SUB_EVT_LE_SCAN_REQUEST_RECEIVED 0x13 // core_5.0 - LE Scan Request Received Event - [5]7.7.65.19
#define HCI_SUB_EVT_LE_CHANNEL_SELECTION_ALGORITHM \
0x14 //core_5.0 - LE Channel Selection Algorithm Event - [5]7.7.65.20
0x14 // core_5.0 - LE Channel Selection Algorithm Event - [5]7.7.65.20
#define HCI_SUB_EVT_LE_CONNECTIONLESS_IQ_REPORT 0x15 //core_5.1 7.7.65.21 LE Connectionless IQ Report event
#define HCI_SUB_EVT_LE_CONNECTION_IQ_REPORT 0x16 //core_5.1 7.7.65.22 LE Connection IQ Report event
#define HCI_SUB_EVT_LE_CTE_REQUEST_FAILED 0x17 //core_5.1 7.7.65.23 LE CTE Request Failed event
#define HCI_SUB_EVT_LE_CONNECTIONLESS_IQ_REPORT 0x15 // core_5.1 7.7.65.21 LE Connectionless IQ Report event
#define HCI_SUB_EVT_LE_CONNECTION_IQ_REPORT 0x16 // core_5.1 7.7.65.22 LE Connection IQ Report event
#define HCI_SUB_EVT_LE_CTE_REQUEST_FAILED 0x17 // core_5.1 7.7.65.23 LE CTE Request Failed event
#define HCI_SUB_EVT_LE_PERIODIC_ADVERTISING_SYNC_TRANSFOR_RECEIVED \
0x18 //core_5.1 7.7.65.24 LE Periodic Advertising Sync Transfer Received event
0x18 // core_5.1 7.7.65.24 LE Periodic Advertising Sync Transfer Received event
#define HCI_SUB_EVT_LE_CIS_ESTABLISHED 0x19 //core_5.2 7.7.65.25 LE CIS Established event
#define HCI_SUB_EVT_LE_CIS_REQUESTED 0x1A //core_5.2 7.7.65.26 LE CIS Request event
#define HCI_SUB_EVT_LE_CREATE_BIG_COMPLETE 0x1B //core_5.2 7.7.65.27 LE Create BIG Complete event
#define HCI_SUB_EVT_LE_TERMINATE_BIG_COMPLETE 0x1C //core_5.2 7.7.65.28 LE Terminate BIG Complete event
#define HCI_SUB_EVT_LE_BIG_SYNC_ESTABLILSHED 0x1D //core_5.2 7.7.65.29 LE BIG Sync Established event
#define HCI_SUB_EVT_LE_BIG_SYNC_LOST 0x1E //core_5.2 7.7.65.30 LE BIG Sync Lost event
#define HCI_SUB_EVT_LE_REQUEST_PEER_SCA_COMPLETE 0x1F //core_5.2 7.7.65.31 LE Request Peer SCA Complete event
#define HCI_SUB_EVT_LE_PATH_LOSS_THRESHOLD 0x20 //core_5.2 7.7.65.32 LE Path Loss Threshold event
#define HCI_SUB_EVT_LE_TRANSMIT_POWER_REPORTING 0x21 //core_5.2 7.7.65.33 LE Transmit Power Reporting event
#define HCI_SUB_EVT_LE_BIGINFO_ADVERTISING_REPORT 0x22 //core_5.2 7.7.65.34 LE BIGInfo Advertising Report event
#define HCI_SUB_EVT_LE_CIS_ESTABLISHED 0x19 // core_5.2 7.7.65.25 LE CIS Established event
#define HCI_SUB_EVT_LE_CIS_REQUESTED 0x1A // core_5.2 7.7.65.26 LE CIS Request event
#define HCI_SUB_EVT_LE_CREATE_BIG_COMPLETE 0x1B // core_5.2 7.7.65.27 LE Create BIG Complete event
#define HCI_SUB_EVT_LE_TERMINATE_BIG_COMPLETE 0x1C // core_5.2 7.7.65.28 LE Terminate BIG Complete event
#define HCI_SUB_EVT_LE_BIG_SYNC_ESTABLILSHED 0x1D // core_5.2 7.7.65.29 LE BIG Sync Established event
#define HCI_SUB_EVT_LE_BIG_SYNC_LOST 0x1E // core_5.2 7.7.65.30 LE BIG Sync Lost event
#define HCI_SUB_EVT_LE_REQUEST_PEER_SCA_COMPLETE 0x1F // core_5.2 7.7.65.31 LE Request Peer SCA Complete event
#define HCI_SUB_EVT_LE_PATH_LOSS_THRESHOLD 0x20 // core_5.2 7.7.65.32 LE Path Loss Threshold event
#define HCI_SUB_EVT_LE_TRANSMIT_POWER_REPORTING 0x21 // core_5.2 7.7.65.33 LE Transmit Power Reporting event
#define HCI_SUB_EVT_LE_BIGINFO_ADVERTISING_REPORT 0x22 // core_5.2 7.7.65.34 LE BIGInfo Advertising Report event
#define HCI_SUB_EVT_LE_CONNECTION_ESTABLISH 0xFF //private
#define HCI_SUB_EVT_LE_CONNECTION_ESTABLISH 0xFF // private
//Event mask - last octet
// Event mask - last octet
#define HCI_EVT_MASK_NONE 0x0000000000
#define HCI_EVT_MASK_INQUIRY_COMPLETE 0x0000000001
#define HCI_EVT_MASK_INQUIRY_RESULT 0x0000000002
#define HCI_EVT_MASK_CONNECTION_COMPELETE 0x0000000004
#define HCI_EVT_MASK_CONNECTION_REQUEST 0x0000000008
#define HCI_EVT_MASK_DISCONNECTION_COMPLETE 0x0000000010 //
#define HCI_EVT_MASK_DISCONNECTION_COMPLETE 0x0000000010
#define HCI_EVT_MASK_AUTHENTICATION_COMPLETE 0x0000000020
#define HCI_EVT_MASK_REMOTE_NAME_REQUEST_COMPLETE 0x0000000040
#define HCI_EVT_MASK_ENCRYPTION_CHANGE 0x0000000080
#define HCI_EVT_MASK_CHANGE_CONECTION_LINK_KEY_COMPLETE 0x0000000100
#define HCI_EVT_MASK_MASTER_LINK_KEY_COMPLETE 0x0000000200
#define HCI_EVT_MASK_READ_REMOTE_SUPPORTED_FEATURES_COMPLETE 0x0000000400
#define HCI_EVT_MASK_READ_REMOTE_VERSION_INFORMATION_COMPLETE 0x0000000800 //
#define HCI_EVT_MASK_READ_REMOTE_VERSION_INFORMATION_COMPLETE 0x0000000800
#define HCI_EVT_MASK_DEFAULT HCI_EVT_MASK_DISCONNECTION_COMPLETE
@@ -148,23 +150,23 @@
#define HCI_LE_EVT_MASK_2_TRANSMIT_POWER_REPORTING 0x00000001 // core5.2 - bit32
#define HCI_LE_EVT_MASK_2_BIGINFO_ADVERTISING_REPORT 0x00000002 // core5.2 - bit33
#define HCI_LE_EVT_MASK_CONNECTION_ESTABLISH 0x80000000 //private
#define HCI_LE_EVT_MASK_CONNECTION_ESTABLISH 0x80000000 // private
#define HCI_LE_EVT_MASK_DEFAULT HCI_LE_EVT_MASK_NONE
//Link Control Command
//-- OGF --
#define HCI_CMD_LINK_CTRL_OPCODE_OGF 0x04 //0x01 <<2 = 0x04
//-- OCF --
// Link Control Command
// -- OGF --
#define HCI_CMD_LINK_CTRL_OPCODE_OGF 0x04 // 0x01 <<2 = 0x04
// -- OCF --
#define HCI_CMD_INQUIRY 0x01
#define HCI_CMD_DISCONNECT 0x06
#define HCI_CMD_READ_REMOTE_NAME_REQ 0x19
#define HCI_CMD_READ_REMOTE_VER_INFO 0x1D
//Controller & Baseband Commands
//-- OGF --
#define HCI_CMD_CBC_OPCODE_OGF 0x0C //0x03 <<2, controller & baseband control
//-- OCF --
// Controller & Baseband Commands
// -- OGF --
#define HCI_CMD_CBC_OPCODE_OGF 0x0C // 0x03 <<2, controller & baseband control
// -- OCF --
#define HCI_CMD_SET_EVENT_MASK 0x01
#define HCI_CMD_RESET 0x03
#define HCI_CMD_SET_EVENT_FILTER 0x05
@@ -194,10 +196,10 @@
#define HCI_CMD_WRITE_INQUIRY_MODE 0x45
#define HCI_CMD_WRITE_PAGE_SCAN_TYPE 0x47
//Informational Parameters
//-- OGF --
#define HCI_CMD_IP_OPCODE_OGF 0x10 //0x04 <<2, information parameter
//-- OCF --
// Informational Parameters
// -- OGF --
#define HCI_CMD_IP_OPCODE_OGF 0x10 // 0x04 <<2, information parameter
// -- OCF --
#define HCI_CMD_READ_LOCAL_VER_INFO 0x01
#define HCI_CMD_READ_LOCAL_SUPPORTED_CMDS 0x02
#define HCI_CMD_READ_LOCAL_SUPPORTED_FEATURES 0x03
@@ -206,18 +208,18 @@
#define HCI_CMD_READ_BD_ADDR 0x09
// Status Parameters
//-- OGF --
#define HCI_CMD_STATUS_PARAM_OPCODE_OGF 0x14 //0x05 <<2
//-- OCF --
// -- OGF --
#define HCI_CMD_STATUS_PARAM_OPCODE_OGF 0x14 // 0x05 <<2
// -- OCF --
#define HCI_CMD_READ_RSSI 0x05
#define HCI_EVT_CMDSTATUS(n, c, g, s) ((s) | (n << 8) | (c << 16) | (g << 24))
#define HCI_EVT_CMD_COMPLETE_STATUS(n, c, g, s) ((n << 0) | (c << 8) | (g << 16) | (s << 24))
#define HCI_EVT_CMDSTATUS(n, c, g, s) ((s) | ((n) << 8) | ((c) << 16) | ((g) << 24))
#define HCI_EVT_CMD_COMPLETE_STATUS(n, c, g, s) (((n) << 0) | ((c) << 8) | ((g) << 16) | ((s) << 24))
// LE Controller Commands
//-- OGF --
#define HCI_CMD_LE_OPCODE_OGF 0x20 //0x08 <<2 = 0x20
//-- OCF --
// -- OGF --
#define HCI_CMD_LE_OPCODE_OGF 0x20 // 0x08 <<2 = 0x20
// -- OCF --
#define HCI_CMD_LE_SET_EVENT_MASK 0x01
#define HCI_CMD_LE_READ_BUF_SIZE 0x02
#define HCI_CMD_LE_READ_LOCAL_SUPPORTED_FEATURES 0x03
@@ -249,12 +251,12 @@
#define HCI_CMD_LE_RECEIVER_TEST_V1 (HCI_CMD_LE_RECEIVER_TEST)
#define HCI_CMD_LE_TRANSMITTER_TEST 0x1E
#define HCI_CMD_LE_TEST_END 0x1F
//core_4.0 end
//core_4.2 begin
// core_4.0 end
// core_4.2 begin
#define HCI_CMD_LE_REMOTE_CONNECTION_PARAM_REQ_REPLY 0x20
#define HCI_CMD_LE_REMOTE_CONNECTION_PARAM_REQ_NEGATIVE_REPLY 0x21
//core_4.1 end
//core_4.2 begin
// core_4.1 end
// core_4.2 begin
#define HCI_CMD_LE_SET_DATA_LENGTH 0x22
#define HCI_CMD_LE_READ_SUGGESTED_DEFAULT_DATA_LENGTH 0x23
#define HCI_CMD_LE_WRITE_SUGGESTED_DEFAULT_DATA_LENGTH 0x24
@@ -269,118 +271,118 @@
#define HCI_CMD_LE_SET_ADDRESS_RESOLUTION_ENABLE 0x2D
#define HCI_CMD_LE_SET_RESOLVABLE_PRIVATE_ADDRESS_TIMEOUT 0x2E
#define HCI_CMD_LE_READ_MAX_DATA_LENGTH 0x2F
//core_4.2 end
//core_5.0 begin
#define HCI_CMD_LE_READ_PHY 0x30 //LE Read PHY Command - [5] 7.8.47
#define HCI_CMD_LE_SET_DEFAULT_PHY 0x31 //LE Set Default PHY Command - [5] 7.8.48
#define HCI_CMD_LE_SET_PHY 0x32 //LE Set PHY Command - [5] 7.8.49
#define HCI_CMD_LE_ENHANCED_RECEIVER_TEST 0x33 //LE Enhanced Receiver Test Command - [5] 7.8.50
#define HCI_CMD_LE_RECEIVER_TEST_V2 HCI_CMD_LE_ENHANCED_RECEIVER_TEST //LE Receiver Test command - [5] 7.8.28
#define HCI_CMD_LE_ENHANCED_TRANSMITTER_TEST 0x34 //LE Enhanced Transmitter Test Command - [5] 7.8.51
// core_4.2 end
// core_5.0 begin
#define HCI_CMD_LE_READ_PHY 0x30 // LE Read PHY Command - [5] 7.8.47
#define HCI_CMD_LE_SET_DEFAULT_PHY 0x31 // LE Set Default PHY Command - [5] 7.8.48
#define HCI_CMD_LE_SET_PHY 0x32 // LE Set PHY Command - [5] 7.8.49
#define HCI_CMD_LE_ENHANCED_RECEIVER_TEST 0x33 // LE Enhanced Receiver Test Command - [5] 7.8.50
#define HCI_CMD_LE_RECEIVER_TEST_V2 HCI_CMD_LE_ENHANCED_RECEIVER_TEST // LE Receiver Test command - [5] 7.8.28
#define HCI_CMD_LE_ENHANCED_TRANSMITTER_TEST 0x34 // LE Enhanced Transmitter Test Command - [5] 7.8.51
#define HCI_CMD_LE_SET_ADVERTISING_SET_RANDOM_ADDRESS \
0x35 //LE Set Advertising Set Random Address Command - [5] 7.8.52
0x35 // LE Set Advertising Set Random Address Command - [5] 7.8.52
#define HCI_CMD_LE_SET_EXTENDED_ADVERTISING_PARAMETERS \
0x36 //LE Set Extended Advertising Parameters Command - [5] 7.8.53
#define HCI_CMD_LE_SET_EXTENDED_ADVERTISING_DATA 0x37 //LE Set Extended Advertising Data Command - [5] 7.8.54
#define HCI_CMD_LE_SET_EXTENDED_SCAN_RESPONSE_DATA 0x38 //LE Set Extended Scan Response Data Command - [5] 7.8.55
#define HCI_CMD_LE_SET_EXTENDED_ADVERTISING_ENABLE 0x39 //LE Set Extended Advertising Enable Command - [5] 7.8.56
0x36 // LE Set Extended Advertising Parameters Command - [5] 7.8.53
#define HCI_CMD_LE_SET_EXTENDED_ADVERTISING_DATA 0x37 // LE Set Extended Advertising Data Command - [5] 7.8.54
#define HCI_CMD_LE_SET_EXTENDED_SCAN_RESPONSE_DATA 0x38 // LE Set Extended Scan Response Data Command - [5] 7.8.55
#define HCI_CMD_LE_SET_EXTENDED_ADVERTISING_ENABLE 0x39 // LE Set Extended Advertising Enable Command - [5] 7.8.56
#define HCI_CMD_LE_READ_MAXIMUM_ADVERTISING_DATA_LENGTH \
0x3A //LE Read Maximum Advertising Data Length Command - [5] 7.8.57
0x3A // LE Read Maximum Advertising Data Length Command - [5] 7.8.57
#define HCI_CMD_LE_READ_NUMBER_OF_SUPPORTED_ADVERTISING_SETS \
0x3B //LE Read Number of Supported Advertising Sets Command - [5] 7.8.58
#define HCI_CMD_LE_REMOVE_ADVERTISING_SET 0x3C //LE Remove Advertising Set Command - [5] 7.8.59
#define HCI_CMD_LE_CLEAR_ADVERTISING_SETS 0x3D //LE Clear Advertising Sets Command - [5] 7.8.60
0x3B // LE Read Number of Supported Advertising Sets Command - [5] 7.8.58
#define HCI_CMD_LE_REMOVE_ADVERTISING_SET 0x3C // LE Remove Advertising Set Command - [5] 7.8.59
#define HCI_CMD_LE_CLEAR_ADVERTISING_SETS 0x3D // LE Clear Advertising Sets Command - [5] 7.8.60
#define HCI_CMD_LE_SET_PERIODIC_ADVERTISING_PARAMETERS \
0x3E //LE Set Periodic Advertising Parameters Command - [5] 7.8.61
#define HCI_CMD_LE_SET_PERIODIC_ADVERTISING_DATA 0x3F //LE Set Periodic Advertising Data Command - [5] 7.8.62
#define HCI_CMD_LE_SET_PERIODIC_ADVERTISING_ENABLE 0x40 //LE Set Periodic Advertising Enable Command - [5] 7.8.63
#define HCI_CMD_LE_SET_EXTENDED_SCAN_PARAMETERS 0x41 //LE Set Extended Scan Parameters Command - [5] 7.8.64
#define HCI_CMD_LE_SET_EXTENDED_SCAN_ENABLE 0x42 //LE Set Extended Scan Enable Command - [5] 7.8.65
#define HCI_CMD_LE_EXTENDED_CREATE_CONNECTION 0x43 //LE Extended Create Connection Command - [5] 7.8.66
#define HCI_CMD_LE_PERIODIC_ADVERTISING_CREATE_SYNC 0x44 //LE Periodic Advertising Create Sync Command- [5] 7.8.67
0x3E // LE Set Periodic Advertising Parameters Command - [5] 7.8.61
#define HCI_CMD_LE_SET_PERIODIC_ADVERTISING_DATA 0x3F // LE Set Periodic Advertising Data Command - [5] 7.8.62
#define HCI_CMD_LE_SET_PERIODIC_ADVERTISING_ENABLE 0x40 // LE Set Periodic Advertising Enable Command - [5] 7.8.63
#define HCI_CMD_LE_SET_EXTENDED_SCAN_PARAMETERS 0x41 // LE Set Extended Scan Parameters Command - [5] 7.8.64
#define HCI_CMD_LE_SET_EXTENDED_SCAN_ENABLE 0x42 // LE Set Extended Scan Enable Command - [5] 7.8.65
#define HCI_CMD_LE_EXTENDED_CREATE_CONNECTION 0x43 // LE Extended Create Connection Command - [5] 7.8.66
#define HCI_CMD_LE_PERIODIC_ADVERTISING_CREATE_SYNC 0x44 // LE Periodic Advertising Create Sync Command- [5] 7.8.67
#define HCI_CMD_LE_PERIODIC_ADVERTISING_CREATE_SYNC_CANCEL \
0x45 //LE Periodic Advertising Create Sync Cancel Command - [5] 7.8.68
0x45 // LE Periodic Advertising Create Sync Cancel Command - [5] 7.8.68
#define HCI_CMD_LE_PERIODIC_ADVERTISING_TERMINATE_SYNC \
0x46 //LE Periodic Advertising Terminate Sync Command - [5] 7.8.69
0x46 // LE Periodic Advertising Terminate Sync Command - [5] 7.8.69
#define HCI_CMD_LE_ADD_DEVICE_TO_PERIODIC_ADVERTISER_LIST \
0x47 //LE Add Device To Periodic Advertiser List Command - [5] 7.8.70
0x47 // LE Add Device To Periodic Advertiser List Command - [5] 7.8.70
#define HCI_CMD_LE_REMOVE_DEVICE_FROM_PERIODIC_ADVERTISER_LIST \
0x48 //LE Remove Device From Periodic Advertiser List Command - [5] 7.8.71
#define HCI_CMD_LE_CLEAR_PERIODIC_ADVERTISER_LIST 0x49 //LE Clear Periodic Advertiser List Command - [5] 7.8.72
0x48 // LE Remove Device From Periodic Advertiser List Command - [5] 7.8.71
#define HCI_CMD_LE_CLEAR_PERIODIC_ADVERTISER_LIST 0x49 // LE Clear Periodic Advertiser List Command - [5] 7.8.72
#define HCI_CMD_LE_READ_PERIODIC_ADVERTISER_LIST_SIZE \
0x4A //LE Read Periodic Advertiser List Size Command - [5] 7.8.73
#define HCI_CMD_LE_READ_TRANSMIT_POWER 0x4B //LE Read Transmit Power Command - [5] 7.8.74
#define HCI_CMD_LE_READ_RF_PATH_COMPENSATION 0x4C //LE Read RF Path Compensation Command - [5] 7.8.75
#define HCI_CMD_LE_WRITE_RF_PATH_COMPENSATION 0x4D //LE Write RF Path Compensation Command - [5] 7.8.76
#define HCI_CMD_LE_SET_PRIVACY_MODE 0x4E //LE Set Privacy Mode Command - [5] 7.8.77
//core_5.0 end
0x4A // LE Read Periodic Advertiser List Size Command - [5] 7.8.73
#define HCI_CMD_LE_READ_TRANSMIT_POWER 0x4B // LE Read Transmit Power Command - [5] 7.8.74
#define HCI_CMD_LE_READ_RF_PATH_COMPENSATION 0x4C // LE Read RF Path Compensation Command - [5] 7.8.75
#define HCI_CMD_LE_WRITE_RF_PATH_COMPENSATION 0x4D // LE Write RF Path Compensation Command - [5] 7.8.76
#define HCI_CMD_LE_SET_PRIVACY_MODE 0x4E // LE Set Privacy Mode Command - [5] 7.8.77
// core_5.0 end
//core_5.1 begin
#define HCI_CMD_LE_RECEIVER_TEST_V3 0x4F //7.8.78 LE Receiver Test command [v3]
#define HCI_CMD_LE_TRANSMITTER_TEST_V3 0x50 //7.8.79 LE Transmitter Test command [v3]
// core_5.1 begin
#define HCI_CMD_LE_RECEIVER_TEST_V3 0x4F // 7.8.78 LE Receiver Test command [v3]
#define HCI_CMD_LE_TRANSMITTER_TEST_V3 0x50 // 7.8.79 LE Transmitter Test command [v3]
#define HCI_CMD_LE_SET_CONNECTIONLESS_CTE_TRANSMIT_PARAMETERS \
0x51 //7.8.80 LE Set Connectionless CTE Transmit Parameters command
0x51 // 7.8.80 LE Set Connectionless CTE Transmit Parameters command
#define HCI_CMD_LE_SET_CONNECTIONLESS_CTE_TRANSMIT_ENABLE \
0x52 //7.8.81 LE Set Connectionless CTE Transmit Enable command
0x52 // 7.8.81 LE Set Connectionless CTE Transmit Enable command
#define HCI_CMD_LE_SET_CONNECTIONLESS_IQ_SAMPLING_ENABLE \
0x53 //7.8.82 LE Set Connectionless IQ Sampling Enable command
0x53 // 7.8.82 LE Set Connectionless IQ Sampling Enable command
#define HCI_CMD_LE_SET_CONNECTION_CTE_RECEIVE_PARAMETERS \
0x54 //7.8.83 LE Set Connection CTE Receive Parameters command
0x54 // 7.8.83 LE Set Connection CTE Receive Parameters command
#define HCI_CMD_LE_SET_CONNECTION_CTE_TRANSMIT_PARAMETERS \
0x55 //7.8.84 LE Set Connection CTE Transmit Parameters command
#define HCI_CMD_LE_CONNECTION_REQUEST_ENABLE 0x56 //7.8.85 LE Connection CTE Request Enable command
#define HCI_CMD_LE_CONNECTION_RESPONSE_ENABLE 0x57 //7.8.86 LE Connection CTE Response Enable command
#define HCI_CMD_LE_READ_ANTENNA_INFORMATION 0x58 //7.8.87 LE Read Antenna Information command
0x55 // 7.8.84 LE Set Connection CTE Transmit Parameters command
#define HCI_CMD_LE_CONNECTION_REQUEST_ENABLE 0x56 // 7.8.85 LE Connection CTE Request Enable command
#define HCI_CMD_LE_CONNECTION_RESPONSE_ENABLE 0x57 // 7.8.86 LE Connection CTE Response Enable command
#define HCI_CMD_LE_READ_ANTENNA_INFORMATION 0x58 // 7.8.87 LE Read Antenna Information command
#define HCI_CMD_LE_SET_PERIODIC_ADVERTISING_RECEIVE_ENABLE \
0x59 //7.8.88 LE Set Periodic Advertising Receive Enable command
#define HCI_CMD_LE_PERIODIC_ADVERTISING_SYNC_TRANSFOR 0x5A //7.8.89 LE Periodic Advertising Sync Transfer command
0x59 // 7.8.88 LE Set Periodic Advertising Receive Enable command
#define HCI_CMD_LE_PERIODIC_ADVERTISING_SYNC_TRANSFOR 0x5A // 7.8.89 LE Periodic Advertising Sync Transfer command
#define HCI_CMD_LE_PERIODIC_ADVERTISING_SET_INFO_TRANSFOR \
0x5B //7.8.90 LE Periodic Advertising Set Info Transfer command
0x5B // 7.8.90 LE Periodic Advertising Set Info Transfer command
#define HCI_CMD_LE_SET_PERIODIC_ADV_SYNC_TRANSFOR_PARAMETERS \
0x5C //7.8.91 LE Set Periodic Advertising Sync Transfer Parameters command
0x5C // 7.8.91 LE Set Periodic Advertising Sync Transfer Parameters command
#define HCI_CMD_LE_SET_DEFAULT_PERIODIC_ADV_SYNC_TRANSFOR_PARAMS \
0x5D //7.8.92 LE Set Default Periodic Advertising Sync Transfer Parameters command
#define HCI_CMD_LE_GENERATE_DHKEY_V2 0x5E //7.8.93 LE Generate DHKey command [v2]
#define HCI_CMD_LE_MODIFY_SLEEP_CLOCK_ACCURACY 0x5F //7.8.94 LE Modify Sleep Clock Accuracy command
//core_5.1 end
0x5D // 7.8.92 LE Set Default Periodic Advertising Sync Transfer Parameters command
#define HCI_CMD_LE_GENERATE_DHKEY_V2 0x5E // 7.8.93 LE Generate DHKey command [v2]
#define HCI_CMD_LE_MODIFY_SLEEP_CLOCK_ACCURACY 0x5F // 7.8.94 LE Modify Sleep Clock Accuracy command
// core_5.1 end
//core_5.2 begin
#define HCI_CMD_LE_READ_BUFFER_SIZE_V2 0x60 //7.8.2 LE Read Buffer Size command
#define HCI_CMD_LE_READ_ISO_TX_SYNC 0x61 //7.8.96 LE Read ISO TX Sync command
#define HCI_CMD_LE_SET_CIG_PARAMETERS 0x62 //7.8.97 LE Set CIG Parameters command
#define HCI_CMD_LE_SET_CIG_PARAMETERS_TEST 0x63 //7.8.98 LE Set CIG Parameters Test command
#define HCI_CMD_LE_CREATE_CIS 0x64 //7.8.99 LE Create CIS command
#define HCI_CMD_LE_REMOVE_CIG 0x65 //7.8.100 LE Remove CIG command
#define HCI_CMD_LE_ACCEPT_CIS_REQUEST 0x66 //7.8.101 LE Accept CIS Request command
#define HCI_CMD_LE_REJECT_CIS_REQUEST 0x67 //7.8.102 LE Reject CIS Request command
#define HCI_CMD_LE_CREATE_BIG 0x68 //7.8.103 LE Create BIG command
#define HCI_CMD_LE_CREATE_BIG_TEST 0x69 //7.8.104 LE Create BIG Test command
#define HCI_CMD_LE_TERMINATE_BIG 0x6A //7.8.105 LE Terminate BIG command
#define HCI_CMD_LE_BIG_CREATE_SYNC 0x6B //7.8.106 LE BIG Create Sync command
#define HCI_CMD_LE_BIG_TERMINATE_SYNC 0x6C //7.8.107 LE BIG Terminate Sync command
#define HCI_CMD_LE_REQUEST_PEER_SCA 0x6D //7.8.108 LE Request Peer SCA command
#define HCI_CMD_LE_SETUP_ISO_DATA_PATH 0x6E //7.8.109 LE Setup ISO Data Path command
#define HCI_CMD_LE_REMOVE_ISO_DARA_PATH 0x6F //7.8.110 LE Remove ISO Data Path command
#define HCI_CMD_LE_ISO_TRTANSMIT_TEST 0x70 //7.8.111 LE ISO Transmit Test command
#define HCI_CMD_LE_ISO_RECEIVE_TEST 0x71 //7.8.112 LE ISO Receive Test command
#define HCI_CMD_LE_ISO_READ_TEST_COUNTERS 0x72 //7.8.113 LE ISO Read Test Counters command
#define HCI_CMD_LE_ISO_TEST_END 0x73 //7.8.114 LE ISO Test End command
#define HCI_CMD_LE_SET_HOST_FEATURE 0x74 //7.8.115 LE Set Host Feature Command
#define HCI_CMD_LE_READ_ISO_LINK_QUALITY 0x75 //7.8.116 LE Read ISO Link Quality command
#define HCI_CMD_LE_ENHANCED_READ_TRANSMIT_POWER_LEVEL 0x76 //7.8.117 LE Enhanced Read Transmit Power Level command
#define HCI_CMD_LE_READ_REMOTE_TRANSMIT_POWER_LEVEL 0x77 //7.8.118 LE Read Remote Transmit Power Level command
#define HCI_CMD_LE_SET_PATH_LOSS_REPORTING_PARAMETERS 0x78 //7.8.119 LE Set Path Loss Reporting Parameters command
#define HCI_CMD_LE_SET_PATH_LOSS_REPORTING_ENABLE 0x79 //7.8.120 LE Set Path Loss Reporting Enable command
#define HCI_CMD_LE_SET_TRANSMIT_POWER_REPORTING_ENABLE 0x7A //7.8.121 LE Set Transmit Power Reporting Enable command
//core_5.2 end
// core_5.2 begin
#define HCI_CMD_LE_READ_BUFFER_SIZE_V2 0x60 // 7.8.2 LE Read Buffer Size command
#define HCI_CMD_LE_READ_ISO_TX_SYNC 0x61 // 7.8.96 LE Read ISO TX Sync command
#define HCI_CMD_LE_SET_CIG_PARAMETERS 0x62 // 7.8.97 LE Set CIG Parameters command
#define HCI_CMD_LE_SET_CIG_PARAMETERS_TEST 0x63 // 7.8.98 LE Set CIG Parameters Test command
#define HCI_CMD_LE_CREATE_CIS 0x64 // 7.8.99 LE Create CIS command
#define HCI_CMD_LE_REMOVE_CIG 0x65 // 7.8.100 LE Remove CIG command
#define HCI_CMD_LE_ACCEPT_CIS_REQUEST 0x66 // 7.8.101 LE Accept CIS Request command
#define HCI_CMD_LE_REJECT_CIS_REQUEST 0x67 // 7.8.102 LE Reject CIS Request command
#define HCI_CMD_LE_CREATE_BIG 0x68 // 7.8.103 LE Create BIG command
#define HCI_CMD_LE_CREATE_BIG_TEST 0x69 // 7.8.104 LE Create BIG Test command
#define HCI_CMD_LE_TERMINATE_BIG 0x6A // 7.8.105 LE Terminate BIG command
#define HCI_CMD_LE_BIG_CREATE_SYNC 0x6B // 7.8.106 LE BIG Create Sync command
#define HCI_CMD_LE_BIG_TERMINATE_SYNC 0x6C // 7.8.107 LE BIG Terminate Sync command
#define HCI_CMD_LE_REQUEST_PEER_SCA 0x6D // 7.8.108 LE Request Peer SCA command
#define HCI_CMD_LE_SETUP_ISO_DATA_PATH 0x6E // 7.8.109 LE Setup ISO Data Path command
#define HCI_CMD_LE_REMOVE_ISO_DARA_PATH 0x6F // 7.8.110 LE Remove ISO Data Path command
#define HCI_CMD_LE_ISO_TRTANSMIT_TEST 0x70 // 7.8.111 LE ISO Transmit Test command
#define HCI_CMD_LE_ISO_RECEIVE_TEST 0x71 // 7.8.112 LE ISO Receive Test command
#define HCI_CMD_LE_ISO_READ_TEST_COUNTERS 0x72 // 7.8.113 LE ISO Read Test Counters command
#define HCI_CMD_LE_ISO_TEST_END 0x73 // 7.8.114 LE ISO Test End command
#define HCI_CMD_LE_SET_HOST_FEATURE 0x74 // 7.8.115 LE Set Host Feature Command
#define HCI_CMD_LE_READ_ISO_LINK_QUALITY 0x75 // 7.8.116 LE Read ISO Link Quality command
#define HCI_CMD_LE_ENHANCED_READ_TRANSMIT_POWER_LEVEL 0x76 // 7.8.117 LE Enhanced Read Transmit Power Level command
#define HCI_CMD_LE_READ_REMOTE_TRANSMIT_POWER_LEVEL 0x77 // 7.8.118 LE Read Remote Transmit Power Level command
#define HCI_CMD_LE_SET_PATH_LOSS_REPORTING_PARAMETERS 0x78 // 7.8.119 LE Set Path Loss Reporting Parameters command
#define HCI_CMD_LE_SET_PATH_LOSS_REPORTING_ENABLE 0x79 // 7.8.120 LE Set Path Loss Reporting Enable command
#define HCI_CMD_LE_SET_TRANSMIT_POWER_REPORTING_ENABLE 0x7A // 7.8.121 LE Set Transmit Power Reporting Enable command
// core_5.2 end
#define HCI_CMD_LINK_POLICY_OPCODE_OGF 0x08 //0x02<<2 = 0x08
#define HCI_CMD_TEST_OPCODE_OGF 0x18 //0x06<<2 = 0x18
#define HCI_CMD_LINK_POLICY_OPCODE_OGF 0x08 // 0x02<<2 = 0x08
#define HCI_CMD_TEST_OPCODE_OGF 0x18 // 0x06<<2 = 0x18
// Vendor specific Commands
//-- OGF --
#define HCI_CMD_VENDOR_OPCODE_OGF 0xFC //0x3f <<2 = 0xFC
//-- OCF --
// -- OGF --
#define HCI_CMD_VENDOR_OPCODE_OGF 0xFC // 0x3f <<2 = 0xFC
// -- OCF --
#define HCI_TELINK_READ_REG 0x01
#define HCI_TELINK_WRITE_REG 0x02
#define HCI_TELINK_SET_TX_PWR 0x03
b91/b91_ble_sdk/stack/ble/hci/hci_event.h
+45 -90
View File
@@ -18,51 +18,45 @@
#ifndef HCI_EVENT_H_
#define HCI_EVENT_H_
#include "stack/ble/ble_common.h"
#include "stack/ble/ble_config.h"
#include <stack/ble/ble_common.h>
#include <stack/ble/ble_config.h>
#include <stack/ble/hci/hci.h>
/**
* @brief Definition for general HCI event packet
*/
typedef struct
{
typedef struct {
hci_type_t type;
u8 eventCode;
u8 paraLen;
u8 parameters[1];
} hci_event_t;
typedef struct
{
typedef struct {
u8 numHciCmds;
u8 opCode_OCF;
u8 opCode_OGF;
u8 returnParas[1];
} hci_cmdCompleteEvt_t;
typedef struct
{
typedef struct {
u8 status;
u8 numHciCmds;
u8 opCode_OCF;
u8 opCode_OGF;
} hci_cmdStatusEvt_t;
typedef struct
{
typedef struct {
u16 connHandle;
u16 numOfCmpPkts;
} numCmpPktParamRet_t;
typedef struct
{
typedef struct {
u8 numHandles;
numCmpPktParamRet_t retParams[1]; //TODO
numCmpPktParamRet_t retParams[1];
} hci_numOfCmpPktEvt_t;
typedef struct
{
typedef struct {
hci_type_t type;
u8 eventCode;
u8 paraLen;
@@ -73,15 +67,13 @@ typedef struct
/**
* @brief Event Parameters for "7.7.5 Disconnection Complete event"
*/
typedef struct
{
typedef struct {
u8 status;
u16 connHandle;
u8 reason;
} event_disconnection_t;
typedef struct
{
typedef struct {
u8 status;
u16 connHandle;
u8 reason;
@@ -90,15 +82,13 @@ typedef struct
/**
* @brief Event Parameters for "7.7.8 Encryption Change event"
*/
typedef struct
{
typedef struct {
u8 status;
u16 handle;
u8 enc_enable;
} event_enc_change_t;
typedef struct
{
typedef struct {
u8 status;
u16 connHandle;
u8 encryption_enable;
@@ -107,14 +97,12 @@ typedef struct
/**
* @brief Event Parameters for "7.7.39 Encryption Key Refresh Complete event"
*/
typedef struct
{
typedef struct {
u8 status;
u16 handle;
} event_enc_refresh_t;
typedef struct
{
typedef struct {
u8 status;
u16 connHandle;
} hci_le_encryptKeyRefreshEvt_t;
@@ -122,8 +110,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.1 LE Connection Complete event"
*/
typedef struct
{
typedef struct {
u8 subcode;
u8 status;
u16 handle;
@@ -136,8 +123,7 @@ typedef struct
u8 accuracy;
} event_connection_complete_t;
typedef struct
{
typedef struct {
u8 subEventCode;
u8 status;
u16 connHandle;
@@ -153,8 +139,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.2 LE Advertising Report event"
*/
typedef struct
{
typedef struct {
u8 subcode;
u8 nreport;
u8 event_type;
@@ -176,8 +161,7 @@ typedef enum {
/**
* @brief Event Parameters for "7.7.65.3 LE Connection Update Complete event"
*/
typedef struct
{
typedef struct {
u8 subcode;
u8 status;
u16 handle;
@@ -186,8 +170,7 @@ typedef struct
u16 timeout;
} event_connection_update_t;
typedef struct
{
typedef struct {
u8 subEventCode;
u8 status;
u16 connHandle;
@@ -200,8 +183,7 @@ typedef struct
* @brief Event Parameters for "7.7.65.4 LE Read Remote Features Complete event"
*/
#define LL_FEATURE_SIZE 8
typedef struct
{
typedef struct {
u8 subEventCode;
u8 status;
u16 connHandle;
@@ -211,8 +193,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.5 LE Long Term Key Request event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u16 connHandle;
u8 random[8];
@@ -222,8 +203,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.6 LE Remote Connection Parameter Request event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u16 connHandle;
u16 IntervalMin;
@@ -235,10 +215,9 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.7 LE Data Length Change event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u16 connHandle; //no aligned, can not be used as pointer
u16 connHandle; // no aligned, can not be used as pointer
u16 maxTxOct;
u16 maxTxtime;
u16 maxRxOct;
@@ -248,8 +227,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.8 LE Read Local P-256 Public Key Complete event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u8 status;
u8 localP256Key[64];
@@ -258,8 +236,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.9 LE Generate DHKey Complete event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u8 status;
u8 DHKey[32];
@@ -268,8 +245,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.10 LE Enhanced Connection Complete event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u8 status;
u16 connHandle;
@@ -287,8 +263,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.12 LE PHY Update Complete event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u8 status;
u16 connHandle;
@@ -300,12 +275,10 @@ typedef struct
* @brief Event Parameters for "7.7.65.13 LE Extended Advertising Report event"
*/
typedef struct
{
//TODO
typedef struct {
} hci_le_extAdvReportEvt_t;
/* Extended Advertising Report Event Event_Type mask*/
/* Extended Advertising Report Event Event_Type mask */
typedef enum {
AEXT_ADV_RPT_EVT_MASK_CONNECTABLE = BIT(0),
EXT_ADV_RPT_EVT_MASK_SCANNABLE = BIT(1),
@@ -323,14 +296,12 @@ typedef enum {
EXT_ADV_RPT_EVT_TYPE_ADV_NONCONN_IND = 0x0010, // 0001 0000'b
EXT_ADV_RPT_EVT_TYPE_SCAN_RSP_2_ADV_IND = 0x001B, // 0001 1011'b
EXT_ADV_RPT_EVT_TYPE_SCAN_RSP_2_ADV_SCAN_IND = 0x001A, // 0001 1010'b
} extAdvRptEvtType_t; //extended advertising report event type
} extAdvRptEvtType_t; // extended advertising report event type
/**
* @brief Event Parameters for "7.7.65.14 LE Periodic Advertising Sync Established event"
*/
typedef struct
{
//TODO
typedef struct {
} hci_le_PeriodicAdvSyncEstablishedEvt_t;
/**
@@ -340,29 +311,22 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.15 LE Periodic Advertising Report event"
*/
typedef struct
{
//TODO
typedef struct {
} hci_le_periodicAdvReportEvt_t;
/**
* @brief Event Parameters for "7.7.65.16 LE Periodic Advertising Sync Lost event"
*/
typedef struct
{
//TODO
typedef struct {
} hci_le_periodicAdvSyncLostEvt_t;
typedef struct
{
//TODO
typedef struct {
} hci_le_scanTimeoutEvt_t;
/**
* @brief Event Parameters for "7.7.65.18 LE Advertising Set Terminated event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u8 status;
u8 advHandle;
@@ -373,16 +337,13 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.19 LE Scan Request Received event"
*/
typedef struct
{
//TODO
typedef struct {
} hci_le_scanReqRcvdEvt_t;
/**
* @brief Event Parameters for "7.7.65.20 LE Channel Selection Algorithm event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u16 connHandle;
u8 channel_selection_algotihm;
@@ -391,8 +352,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.25 LE CIS Established event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u8 status;
u16 cisHandle;
@@ -415,8 +375,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.26 LE CIS Request event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u16 aclHandle;
u16 cisHandle;
@@ -427,8 +386,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.27 LE Create BIG Complete event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u8 staus;
u8 bigHandle;
@@ -448,8 +406,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.28 LE Terminate BIG Complete event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u8 bigHandle;
u8 reason;
@@ -458,8 +415,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.20 LE Channel Selection Algorithm event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u8 staus;
u8 bigHandle;
@@ -477,8 +433,7 @@ typedef struct
/**
* @brief Event Parameters for "7.7.65.29 LE BIG Sync Established event"
*/
typedef struct
{
typedef struct {
u8 subEventCode;
u8 bigHandle;
u8 reason;
b91/b91_ble_sdk/stack/ble/host/attr/att.h
+36 -35
View File
@@ -15,79 +15,78 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_STACK_BLE_HOST_ATTR_ATT_H
#define B91_B91_BLE_SDK_STACK_BLE_HOST_ATTR_ATT_H
#include "tl_common.h"
/** @defgroup ATT_PERMISSIONS_BITMAPS GAP ATT Attribute Access Permissions Bit Fields
* @{
* (See the Core_v5.0(Vol 3/Part C/10.3.1/Table 10.2) for more information)
*/
#define ATT_PERMISSIONS_AUTHOR 0x10 //Attribute access(Read & Write) requires Authorization
#define ATT_PERMISSIONS_ENCRYPT 0x20 //Attribute access(Read & Write) requires Encryption
#define ATT_PERMISSIONS_AUTHEN 0x40 //Attribute access(Read & Write) requires Authentication(MITM protection)
#define ATT_PERMISSIONS_SECURE_CONN 0x80 //Attribute access(Read & Write) requires Secure_Connection
#define ATT_PERMISSIONS_AUTHOR 0x10 // Attribute access(Read & Write) requires Authorization
#define ATT_PERMISSIONS_ENCRYPT 0x20 // Attribute access(Read & Write) requires Encryption
#define ATT_PERMISSIONS_AUTHEN 0x40 // Attribute access(Read & Write) requires Authentication(MITM protection)
#define ATT_PERMISSIONS_SECURE_CONN 0x80 // Attribute access(Read & Write) requires Secure_Connection
#define ATT_PERMISSIONS_SECURITY \
(ATT_PERMISSIONS_AUTHOR | ATT_PERMISSIONS_ENCRYPT | ATT_PERMISSIONS_AUTHEN | ATT_PERMISSIONS_SECURE_CONN)
//user can choose permission below
#define ATT_PERMISSIONS_READ 0x01 //!< Attribute is Readable
#define ATT_PERMISSIONS_WRITE 0x02 //!< Attribute is Writable
#define ATT_PERMISSIONS_RDWR (ATT_PERMISSIONS_READ | ATT_PERMISSIONS_WRITE) //!< Attribute is Readable & Writable
// user can choose permission below
#define ATT_PERMISSIONS_READ 0x01 // !< Attribute is Readable
#define ATT_PERMISSIONS_WRITE 0x02 // !< Attribute is Writable
#define ATT_PERMISSIONS_RDWR (ATT_PERMISSIONS_READ | ATT_PERMISSIONS_WRITE) // !< Attribute is Readable & Writable
#define ATT_PERMISSIONS_ENCRYPT_READ (ATT_PERMISSIONS_READ | ATT_PERMISSIONS_ENCRYPT) //!< Read requires Encryption
#define ATT_PERMISSIONS_ENCRYPT_WRITE (ATT_PERMISSIONS_WRITE | ATT_PERMISSIONS_ENCRYPT) //!< Write requires Encryption
#define ATT_PERMISSIONS_ENCRYPT_READ (ATT_PERMISSIONS_READ | ATT_PERMISSIONS_ENCRYPT) // !< Read requires Encryption
#define ATT_PERMISSIONS_ENCRYPT_WRITE \
(ATT_PERMISSIONS_WRITE | ATT_PERMISSIONS_ENCRYPT) // !< Write requires Encryption
#define ATT_PERMISSIONS_ENCRYPT_RDWR \
(ATT_PERMISSIONS_RDWR | ATT_PERMISSIONS_ENCRYPT) //!< Read & Write requires Encryption
(ATT_PERMISSIONS_RDWR | ATT_PERMISSIONS_ENCRYPT) // !< Read & Write requires Encryption
#define ATT_PERMISSIONS_AUTHEN_READ \
(ATT_PERMISSIONS_READ | ATT_PERMISSIONS_ENCRYPT | ATT_PERMISSIONS_AUTHEN) //!< Read requires Authentication
(ATT_PERMISSIONS_READ | ATT_PERMISSIONS_ENCRYPT | ATT_PERMISSIONS_AUTHEN) // !< Read requires Authentication
#define ATT_PERMISSIONS_AUTHEN_WRITE \
(ATT_PERMISSIONS_WRITE | ATT_PERMISSIONS_ENCRYPT | ATT_PERMISSIONS_AUTHEN) //!< Write requires Authentication
(ATT_PERMISSIONS_WRITE | ATT_PERMISSIONS_ENCRYPT | ATT_PERMISSIONS_AUTHEN) // !< Write requires Authentication
#define ATT_PERMISSIONS_AUTHEN_RDWR \
(ATT_PERMISSIONS_RDWR | ATT_PERMISSIONS_ENCRYPT | \
ATT_PERMISSIONS_AUTHEN) //!< Read & Write requires Authentication
ATT_PERMISSIONS_AUTHEN) // !< Read & Write requires Authentication
#define ATT_PERMISSIONS_SECURE_CONN_READ \
(ATT_PERMISSIONS_READ | ATT_PERMISSIONS_SECURE_CONN | ATT_PERMISSIONS_ENCRYPT | \
ATT_PERMISSIONS_AUTHEN) //!< Read requires Secure_Connection
ATT_PERMISSIONS_AUTHEN) // !< Read requires Secure_Connection
#define ATT_PERMISSIONS_SECURE_CONN_WRITE \
(ATT_PERMISSIONS_WRITE | ATT_PERMISSIONS_SECURE_CONN | ATT_PERMISSIONS_ENCRYPT | \
ATT_PERMISSIONS_AUTHEN) //!< Write requires Secure_Connection
ATT_PERMISSIONS_AUTHEN) // !< Write requires Secure_Connection
#define ATT_PERMISSIONS_SECURE_CONN_RDWR \
(ATT_PERMISSIONS_RDWR | ATT_PERMISSIONS_SECURE_CONN | ATT_PERMISSIONS_ENCRYPT | \
ATT_PERMISSIONS_AUTHEN) //!< Read & Write requires Secure_Connection
ATT_PERMISSIONS_AUTHEN) // !< Read & Write requires Secure_Connection
#define ATT_PERMISSIONS_AUTHOR_READ (ATT_PERMISSIONS_READ | ATT_PERMISSIONS_AUTHOR) //!< Read requires Authorization
#define ATT_PERMISSIONS_AUTHOR_READ (ATT_PERMISSIONS_READ | ATT_PERMISSIONS_AUTHOR) // !< Read requires Authorization
#define ATT_PERMISSIONS_AUTHOR_WRITE \
(ATT_PERMISSIONS_WRITE | ATT_PERMISSIONS_AUTHEN) //!< Write requires Authorization
(ATT_PERMISSIONS_WRITE | ATT_PERMISSIONS_AUTHEN) // !< Write requires Authorization
#define ATT_PERMISSIONS_AUTHOR_RDWR \
(ATT_PERMISSIONS_RDWR | ATT_PERMISSIONS_AUTHOR) //!< Read & Write requires Authorization
(ATT_PERMISSIONS_RDWR | ATT_PERMISSIONS_AUTHOR) // !< Read & Write requires Authorization
/** @} End GAP_ATT_PERMISSIONS_BITMAPS */
/** @ add to group GATT_Characteristic_Property GATT characteristic properties
* @{
*/
#define CHAR_PROP_BROADCAST 0x01 //!< permit broadcasts of the Characteristic Value
#define CHAR_PROP_READ 0x02 //!< permit reads of the Characteristic Value
#define CHAR_PROP_WRITE_WITHOUT_RSP 0x04 //!< Permit writes of the Characteristic Value without response
#define CHAR_PROP_WRITE 0x08 //!< Permit writes of the Characteristic Value with response
#define CHAR_PROP_NOTIFY 0x10 //!< Permit notifications of a Characteristic Value without acknowledgement
#define CHAR_PROP_INDICATE 0x20 //!< Permit indications of a Characteristic Value with acknowledgement
#define CHAR_PROP_AUTHEN 0x40 //!< permit signed writes to the Characteristic Value
#define CHAR_PROP_EXTENDED 0x80 //!< additional characteristic properties are defined
#define CHAR_PROP_BROADCAST 0x01 // !< permit broadcasts of the Characteristic Value
#define CHAR_PROP_READ 0x02 // !< permit reads of the Characteristic Value
#define CHAR_PROP_WRITE_WITHOUT_RSP 0x04 // !< Permit writes of the Characteristic Value without response
#define CHAR_PROP_WRITE 0x08 // !< Permit writes of the Characteristic Value with response
#define CHAR_PROP_NOTIFY 0x10 // !< Permit notifications of a Characteristic Value without acknowledgement
#define CHAR_PROP_INDICATE 0x20 // !< Permit indications of a Characteristic Value with acknowledgement
#define CHAR_PROP_AUTHEN 0x40 // !< permit signed writes to the Characteristic Value
#define CHAR_PROP_EXTENDED 0x80 // !< additional characteristic properties are defined
/** @} end of group GATT_Characteristic_Property */
//typedef int (*att_readwrite_callback_t)(void* p);
typedef int (*att_readwrite_callback_t)(u16 connHandle, void *p);
typedef struct attribute
{
typedef struct attribute {
u16 attNum;
u8 perm;
u8 uuidLen;
u32 attrLen; //4 bytes aligned
u32 attrLen; // 4 bytes aligned
u8 *uuid;
u8 *pAttrValue;
att_readwrite_callback_t w;
@@ -111,7 +110,7 @@ typedef int (*att_handleValueConfirm_callback_t)(void);
*/
void bls_att_setAttributeTable(u8 *p);
//mtu size
// mtu size
/**
* @brief This function is used to set RX MTU size
* @param mtu_size - ATT MTU size
@@ -144,3 +143,5 @@ ble_sts_t blc_att_responseMtuSizeExchange(u16 connHandle, u16 mtu_size);
* @return none.
*/
void blc_att_setPrepareWriteBuffer(u8 *p, u16 len);
#endif // B91_B91_BLE_SDK_STACK_BLE_HOST_ATTR_ATT_H
b91/b91_ble_sdk/stack/ble/host/ble_host.h
+1 -3
View File
@@ -36,11 +36,9 @@
#include "stack/ble/host/gap/gap_event.h"
/*********************************************************/
//Remove when file merge to SDK //
// Remove when file merge to SDK //
#include "stack/ble/ble_config.h"
//#include "stack/ble/debug.h"
//#include "stack/ble/host/gap/gap_stack.h"
/*********************************************************/
#endif /* STACK_BLE_HOST_BLE_HOST_H_ */
b91/b91_ble_sdk/stack/ble/host/gap/gap.h
+7 -4
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_STACK_BLE_HOST_GAP_GAP_H
#define B91_B91_BLE_SDK_STACK_BLE_HOST_GAP_GAP_H
#define GAP_ADTYPE_FLAGS 0x01 //!< Discovery Mode: @ref GAP_ADTYPE_FLAGS_MODES
#define GAP_ADTYPE_16BIT_INCOMPLETE 0x02 //!< Incomplete List of 16-bit Service Class UUIDs
@@ -34,7 +35,7 @@
#define GAP_ADTYPE_SM_TK 0x10 //!< Security Manager TK Value
#define GAP_ADTYPE_SM_OOB_FLAG 0x11 //!< Secutiry Manager OOB Flags
#define GAP_ADTYPE_SLAVE_CONN_INTERVAL_RANGE \
0x12 //!< Min and Max values of the connection interval (2 octets Min, 2 octets Max) (0xFFFF indicates no conn interval min or max)
0x12 // !< Min and Max conn interval values (2 octets Min, 2 octets Max, 0xFFFF - no conn interval min or max)
#define GAP_ADTYPE_SERVICES_LIST_16BIT 0x14 //!< Service Solicitation: list of 16-bit Service UUIDs
#define GAP_ADTYPE_SERVICES_LIST_32BIT 0x1F //!< Service Solicitation: list of 32-bit Service UUIDs
#define GAP_ADTYPE_SERVICES_LIST_128BIT 0x15 //!< Service Solicitation: list of 128-bit Service UUIDs
@@ -52,8 +53,8 @@
#define GAP_ADTYPE_SIMPLE_PAIRING_RAND_R256 0x1E //!< Simple Pairing Randomizer R-256
#define GAP_ADTYPE_3D_INFORMATION_DATA 0x3D //!< 3D Synchronization Profile, v1.0 or later
#define GAP_ADTYPE_MANUFACTURER_SPECIFIC \
0xFF //!< Manufacturer Specific Data: first 2 octets contain the Company Identifier Code followed by the additional manufacturer specific data
0xFF // !< Manufacturer Specific Data:
// first 2 octets contain the Company Identifier Code followed by the additional manufacturer specific data
#define GAP_ADTYPE_LE_LIMITED_DISCOVERABLE_MODE_BIT 0x01
#define GAP_ADTYPE_LE_GENERAL_DISCOVERABLE_MODE_BIT 0x02
#define GAP_ADTYPE_LMP_BIT37_BIT 0x04
@@ -66,3 +67,5 @@
* @return none
*/
void blc_gap_peripheral_init(void);
#endif // B91_B91_BLE_SDK_STACK_BLE_HOST_GAP_GAP_H
b91/b91_ble_sdk/stack/ble/host/gap/gap_event.h
+10 -18
View File
@@ -159,51 +159,43 @@ Situation 2: SMP Fast Connect |
/**
* @brief data structure of GAP event callback data
*/
typedef struct
{
typedef struct {
u16 connHandle;
u8 secure_conn;
u8 tk_method;
} gap_smp_paringBeginEvt_t;
typedef struct
{
typedef struct {
u16 connHandle;
u8 bonding;
u8 bonding_result;
} gap_smp_paringSuccessEvt_t;
typedef struct
{
typedef struct {
u16 connHandle;
u8 reason;
} gap_smp_paringFailEvt_t;
typedef struct
{
typedef struct {
u16 connHandle;
u8 re_connect; //1: re_connect, encrypt with previous distributed LTK; 0: paring , encrypt with STK
u8 re_connect; // 1: re_connect, encrypt with previous distributed LTK; 0: paring , encrypt with STK
} gap_smp_connEncDoneEvt_t;
typedef struct
{
typedef struct {
u16 connHandle;
u8 re_connect; //1: re_connect, encrypt with previous distributed LTK; 0: paring , encrypt with STK
u8 re_connect; // 1: re_connect, encrypt with previous distributed LTK; 0: paring , encrypt with STK
} gap_smp_securityProcessDoneEvt_t;
typedef struct
{
typedef struct {
u16 connHandle;
u32 tk_pincode;
} gap_smp_TkDisplayEvt_t;
typedef struct
{
typedef struct {
u16 connHandle;
} gap_smp_TkReqPassKeyEvt_t;
typedef struct
{
typedef struct {
u16 connHandle;
u16 peer_MTU;
u16 effective_MTU;
b91/b91_ble_sdk/stack/ble/host/l2cap/l2cap.h
+5 -5
View File
@@ -18,9 +18,9 @@
#ifndef STACK_BLE_L2CAP_L2CAP_H_
#define STACK_BLE_L2CAP_L2CAP_H_
//header(2)+l2cap_len(2)+cid(2)+Attribute_data[ATT_MTU]
#define ATT_RX_MTU_SIZE_MAX (250) //dft ATT_MTU_MAX: 250
//l2cap buffer max: header(2)+l2cap_len(2)+cid(2)+ATT_MTU_MAX(250).
// header(2)+l2cap_len(2)+cid(2)+Attribute_data[ATT_MTU]
#define ATT_RX_MTU_SIZE_MAX (250) // dft ATT_MTU_MAX: 250
// l2cap buffer max: header(2)+l2cap_len(2)+cid(2)+ATT_MTU_MAX(250).
#define L2CAP_RX_BUFF_LEN_MAX (256)
/**
@@ -41,7 +41,7 @@ typedef enum {
* @param timeout - connect timeout
* @return none.
*/
void bls_l2cap_requestConnParamUpdate(u16 min_interval, u16 max_interval, u16 latency, u16 timeout); //Slave
void bls_l2cap_requestConnParamUpdate(u16 min_interval, u16 max_interval, u16 latency, u16 timeout); // Slave
/**
* @brief This function is used to set the minimal time for send connect parameter update request after connect created
@@ -70,7 +70,7 @@ int blc_l2cap_packet_receive(u16 connHandle, u8 *p);
* @param *p - the pointer of l2cap data
* @return none.
*/
void blc_l2cap_reg_att_sig_hander(void *p); //signaling pkt proc
void blc_l2cap_reg_att_sig_hander(void *p); // signaling pkt proc
/**
* @brief This function is used to register the function to process L2CAP ATTRIBUTE PROCTOCOL packet
b91/b91_ble_sdk/stack/ble/host/smp/smp.h
+13 -12
View File
@@ -36,7 +36,7 @@
#define PAIRING_FAIL_REASON_CONFIRM_FAILED 0x04
#define PAIRING_FAIL_REASON_PAIRING_NOT_SUPPORTED 0x05
#define PAIRING_FAIL_REASON_ENCRYPT_KEY_SIZE 0x06
#define PAIRING_FAIL_REASON_CMD_NOT_SUPPORT 0x07 //-- core 4.2
#define PAIRING_FAIL_REASON_CMD_NOT_SUPPORT 0x07 // -- core 4.2
#define PAIRING_FAIL_REASON_UNSPECIFIED_REASON 0x08
#define PAIRING_FAIL_REASON_REPEATED_ATTEMPT 0x09
#define PAIRING_FAIL_REASON_INVAILD_PARAMETER 0x0A
@@ -44,21 +44,22 @@
#define PAIRING_FAIL_REASON_NUMUERIC_FAILED 0x0C
#define PAIRING_FAIL_REASON_BREDR_PAIRING 0x0D
#define PAIRING_FAIL_REASON_CROSS_TRANSKEY_NOT_ALLOW 0x0E
#define PAIRING_FAIL_REASON_PAIRING_TIEMOUT 0x80 //TLK defined
#define PAIRING_FAIL_REASON_CONN_DISCONNECT 0x81 //TLK defined
#define PAIRING_FAIL_REASON_SUPPORT_NC_ONLY 0x82 //TLK defined
#define PAIRING_FAIL_REASON_PAIRING_TIEMOUT 0x80 // TLK defined
#define PAIRING_FAIL_REASON_CONN_DISCONNECT 0x81 // TLK defined
#define PAIRING_FAIL_REASON_SUPPORT_NC_ONLY 0x82 // TLK defined
/** @} end of group SMP pairing fail reasone */
// "SecReq" refer to "security request"
typedef enum {
SecReq_NOT_SEND = 0, // do not send "security request" after link layer connection established
SecReq_IMM_SEND = BIT(
0), //"IMM" refer to immediate, send "security request" immediately after link layer connection established
0), // "IMM" refer to immediate, send "security request" immediately after link layer connection established
SecReq_PEND_SEND = BIT(
1), //"PEND" refer to pending, pending "security request" for some time after link layer connection established, when pending time arrived. send it
1), // "PEND" refer to pending, pending "security request"
// for some time after link layer connection established, when pending time arrived. send it
} secReq_cfg;
//See the Core_v5.0(Vol 3/Part C/10.2, Page 2067) for more information.
// See the Core_v5.0(Vol 3/Part C/10.2, Page 2067) for more information.
typedef enum {
LE_Security_Mode_1_Level_1 = BIT(0),
No_Authentication_No_Encryption = BIT(0),
@@ -89,8 +90,8 @@ typedef enum {
Bondable_Mode = 1,
} bonding_mode_t;
//Paring Methods select
//See the Core_v5.0(Vol 3/Part H/2.3) for more information.
// Paring Methods select
// See the Core_v5.0(Vol 3/Part H/2.3) for more information.
typedef enum {
LE_Legacy_Paring = 0, // BLE 4.0/4.2
LE_Secure_Connection = 1, // BLE 4.2/5.0/5.1
@@ -134,7 +135,7 @@ void blc_smp_preMakeEcdhKeysEnable(u8 enable);
* 1: LE secure connection
* @return none.
*/
void blc_smp_setParingMethods(paring_methods_t method); //select paring methods
void blc_smp_setParingMethods(paring_methods_t method); // select paring methods
/**
* @brief This function is used to set whether the device uses the ECDH DEBUG key.
@@ -152,7 +153,7 @@ void blc_smp_setEcdhDebugMode(ecdh_keys_mode_t mode);
* 1: bondable mode.
* @return none.
*/
void blc_smp_setBondingMode(bonding_mode_t mode); //set bonding_mode
void blc_smp_setBondingMode(bonding_mode_t mode); // set bonding_mode
/**
* @brief This function is used to set if enable authentication MITM protection.
@@ -168,7 +169,7 @@ void blc_smp_enableAuthMITM(int MITM_en);
* 1: Enable OOB authentication.
* @return none.
*/
void blc_smp_enableOobAuthentication(int OOB_en); //enable OOB authentication
void blc_smp_enableOobAuthentication(int OOB_en); // enable OOB authentication
/**
* @brief This function is used to set device's IO capability.
b91/b91_ble_sdk/stack/ble/host/smp/smp_storage.h
+5 -7
View File
@@ -19,27 +19,25 @@
#define SMP_STORAGE_H_
typedef enum {
Index_Update_by_Pairing_Order = 0, //default value
Index_Update_by_Pairing_Order = 0, // default value
Index_Update_by_Connect_Order = 1,
} index_updateMethod_t;
/*
* smp parameter need save to flash.
* */
typedef struct
{ //82
typedef struct { // 82
u8 flag;
u8 peer_addr_type; //address used in link layer connection
u8 peer_addr_type; // address used in link layer connection
u8 peer_addr[6];
u8 peer_key_size;
u8 peer_id_adrType; //peer identity address information in key distribution, used to identify
u8 peer_id_adrType; // peer identity address information in key distribution, used to identify
u8 peer_id_addr[6];
u8 own_ltk[16]; //own_ltk[16]
u8 own_ltk[16]; // own_ltk[16]
u8 peer_irk[16];
u8 peer_csrk[16];
} smp_param_save_t;
/**
b91/b91_ble_sdk/stack/ble/service/device_information.h
+3 -5
View File
@@ -15,10 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef DEVICE_INFORMATION_H
#define DEVICE_INFORMATION_H
#ifndef B91_B91_BLE_SDK_STACK_BLE_SERVICE_DEVICE_INFORMATION_H
#define B91_B91_BLE_SDK_STACK_BLE_SERVICE_DEVICE_INFORMATION_H
/**
* @brief device_char_uuid Device Information Characteristic UUID
@@ -33,4 +31,4 @@
#define CHARACTERISTIC_UUID_IEEE_11073_CERT_LIST 0x2A2A
#define CHARACTERISTIC_UUID_PNP_ID 0x2A50
#endif // DEVICE_INFORMATION_H
#endif // B91_B91_BLE_SDK_STACK_BLE_SERVICE_DEVICE_INFORMATION_H
b91/b91_ble_sdk/stack/ble/service/hids.h
+7 -4
View File
@@ -15,7 +15,8 @@
* limitations under the License.
*
*****************************************************************************/
#pragma once
#ifndef B91_B91_BLE_SDK_STACK_BLE_SERVICE_HIDS_H
#define B91_B91_BLE_SDK_STACK_BLE_SERVICE_HIDS_H
/**
* @brief hids_uuid Hids Characteristic UUID
@@ -41,9 +42,9 @@
#define HID_REPORT_ID_CTRL_VOICE 9
#define HID_REPORT_ID_AUDIO_FIRST_INPUT 10 //250
#define HID_REPORT_ID_AUDIO_SECND_INPUT 11 //251
#define HID_REPORT_ID_AUDIO_THIRD_INPUT 12 //247
#define HID_REPORT_ID_AUDIO_FIRST_INPUT 10 // 250
#define HID_REPORT_ID_AUDIO_SECND_INPUT 11 // 251
#define HID_REPORT_ID_AUDIO_THIRD_INPUT 12 // 247
/**
* @brief HID Report type
@@ -65,3 +66,5 @@
*/
#define HID_FLAGS_REMOTE_WAKE 0x01 // RemoteWake
#define HID_FLAGS_NORMALLY_CONNECTABLE 0x02 // NormallyConnectable
#endif // B91_B91_BLE_SDK_STACK_BLE_SERVICE_HIDS_H
b91/b91_ble_sdk/stack/ble/service/ota/ota.h
+41 -45
View File
@@ -18,75 +18,74 @@
#ifndef OTA_H_
#define OTA_H_
#define CMD_OTA_VERSION 0xFF00 //client -> server
#define CMD_OTA_START 0xFF01 //client -> server
#define CMD_OTA_END 0xFF02 //client -> server
#define CMD_OTA_VERSION 0xFF00 // client -> server
#define CMD_OTA_START 0xFF01 // client -> server
#define CMD_OTA_END 0xFF02 // client -> server
#define CMD_OTA_START_EXT 0xFF03 //client -> server
#define CMD_OTA_START_EXT 0xFF03 // client -> server
#define CMD_OTA_FW_VERSION_REQ 0xFF04
#define CMD_OTA_FW_VERSION_RSP 0xFF05
#define CMD_OTA_RESULT 0xFF06 //server -> client
#define CMD_OTA_RESULT 0xFF06 // server -> client
/**
* @brief Multiple boot address enumarion
*/
typedef enum {
MULTI_BOOT_ADDR_0x20000 = 0x20000, //128 K
MULTI_BOOT_ADDR_0x40000 = 0x40000, //256 K
MULTI_BOOT_ADDR_0x80000 = 0x80000, //512 K
MULTI_BOOT_ADDR_0x20000 = 0x20000, // 128 K
MULTI_BOOT_ADDR_0x40000 = 0x40000, // 256 K
MULTI_BOOT_ADDR_0x80000 = 0x80000, // 512 K
} multi_boot_addr_e;
/**
* @brief OTA result
*/
enum {
//0x00
OTA_SUCCESS = 0, //success
OTA_DATA_PACKET_SEQ_ERR, //OTA data packet sequence number error: repeated OTA PDU or lost some OTA PDU
OTA_PACKET_INVALID, //invalid OTA packet: 1. invalid OTA command; 2. addr_index out of range; 3.not standard OTA PDU length
OTA_DATA_CRC_ERR, //packet PDU CRC err
// 0x00
OTA_SUCCESS = 0, // success
OTA_DATA_PACKET_SEQ_ERR, // OTA data packet sequence number error: repeated OTA PDU or lost some OTA PDU
OTA_PACKET_INVALID, // invalid OTA packet: 1. invalid OTA command;
// 2. addr_index out of range; 3.not standard OTA PDU length
OTA_DATA_CRC_ERR, // packet PDU CRC err
//0x04
OTA_WRITE_FLASH_ERR, //write OTA data to flash ERR
OTA_DATA_UNCOMPLETE, //lost last one or more OTA PDU
OTA_FLOW_ERR, //peer device send OTA command or OTA data not in correct flow
OTA_FW_CHECK_ERR, //firmware CRC check error
// 0x04
OTA_WRITE_FLASH_ERR, // write OTA data to flash ERR
OTA_DATA_UNCOMPLETE, // lost last one or more OTA PDU
OTA_FLOW_ERR, // peer device send OTA command or OTA data not in correct flow
OTA_FW_CHECK_ERR, // firmware CRC check error
//0x08
OTA_VERSION_COMPARE_ERR, //the version number to be update is lower than the current version
OTA_PDU_LEN_ERR, //PDU length error: not 16*n, or not equal to the value it declare in "CMD_OTA_START_EXT" packet
OTA_FIRMWARE_MARK_ERR, //firmware mark error: not generated by telink's BLE SDK
OTA_FW_SIZE_ERR, //firmware size error: no firmware_size; firmware size too small or too big
// 0x08
OTA_VERSION_COMPARE_ERR, // the version number to be update is lower than the current version
OTA_PDU_LEN_ERR, // PDU length error: not 16*n, or not equal to the value it declare in "CMD_OTA_START_EXT" packet
OTA_FIRMWARE_MARK_ERR, // firmware mark error: not generated by telink's BLE SDK
OTA_FW_SIZE_ERR, // firmware size error: no firmware_size; firmware size too small or too big
//0x0C
OTA_DATA_PACKET_TIMEOUT, //time interval between two consequent packet exceed a value(user can adjust this value)
OTA_TIMEOUT, //OTA flow total timeout
OTA_FAIL_DUE_TO_CONNECTION_TERMIANTE, //OTA fail due to current connection terminate(maybe connection timeout or local/peer device terminate connection)
// 0x0C
OTA_DATA_PACKET_TIMEOUT, // time interval between two consequent packet exceed a value(user can adjust this value)
OTA_TIMEOUT, // OTA flow total timeout
OTA_FAIL_DUE_TO_CONNECTION_TERMIANTE, // OTA fail due to current connection terminate
// (maybe connection timeout or local/peer device terminate connection)
};
/**
* @brief data structure of OTA command "CMD_OTA_START"
*/
typedef struct
{
typedef struct {
u16 ota_cmd;
} ota_start_t;
/**
* @brief data structure of OTA command "CMD_OTA_START_EXT"
*/
typedef struct
{
typedef struct {
u16 ota_cmd;
u8 pdu_length; //must be: 16*n(n is in range of 1 ~ 15); pdu_length: 16,32,48,...240
u8 version_compare; //0: no version compare; 1: only higher version can replace lower version
u8 pdu_length; // must be: 16*n(n is in range of 1 ~ 15); pdu_length: 16,32,48,...240
u8 version_compare; // 0: no version compare; 1: only higher version can replace lower version
} ota_startExt_t;
/**
* @brief data structure of OTA command "CMD_OTA_END"
*/
typedef struct
{
typedef struct {
u16 ota_cmd;
u16 adr_index_max;
u16 adr_index_max_xor;
@@ -95,8 +94,7 @@ typedef struct
/**
* @brief data structure of OTA command "CMD_OTA_RESULT"
*/
typedef struct
{
typedef struct {
u16 ota_cmd;
u8 result;
} ota_result_t;
@@ -104,25 +102,23 @@ typedef struct
/**
* @brief data structure of OTA command "CMD_OTA_FW_VERSION_REQ"
*/
typedef struct
{
typedef struct {
u16 ota_cmd;
u16 version_num;
u8 version_compare; //1: only higher version can replace lower version
u8 version_compare; // 1: only higher version can replace lower version
} ota_versionReq_t;
/**
* @brief data structure of OTA command "CMD_OTA_FW_VERSION_RSP"
*/
typedef struct
{
typedef struct {
u16 ota_cmd;
u16 version_num;
u8 version_accept; //1: accept firmware update; 0: reject firmware update(version compare enable, and compare result: fail)
u8 version_accept; // 1: accept firmware update;
// 0: reject firmware update(version compare enable, and compare result: fail)
} ota_versionRsp_t;
typedef struct
{
typedef struct {
u16 adr_index;
u8 data[16];
u16 crc_16;
b91/b91_ble_sdk/vendor/common/blt_common.c
Vendored
+11 -14
View File
@@ -21,8 +21,8 @@
#include "stack/ble/ble.h"
#include "tl_common.h"
_attribute_data_retention_ u32 flash_sector_mac_address = CFG_ADR_MAC_1M_FLASH; //default flash is 1M
_attribute_data_retention_ u32 flash_sector_calibration = CFG_ADR_CALIBRATION_1M_FLASH; //default flash is 1M
_attribute_data_retention_ u32 flash_sector_mac_address = CFG_ADR_MAC_1M_FLASH; // default flash is 1M
_attribute_data_retention_ u32 flash_sector_calibration = CFG_ADR_CALIBRATION_1M_FLASH; // default flash is 1M
/**
* @brief This function can automatically recognize the flash size,
@@ -47,8 +47,8 @@ _attribute_no_inline_ void blc_readFlashSize_autoConfigCustomFlashSector(void)
flash_sector_mac_address = CFG_ADR_MAC_2M_FLASH;
flash_sector_calibration = CFG_ADR_CALIBRATION_2M_FLASH;
} else {
//This SDK do not support flash size other than 1M/2M
//If code stop here, please check your Flash
// This SDK do not support flash size other than 1M/2M
// If code stop here, please check your Flash
while (1) {
}
}
@@ -57,9 +57,9 @@ _attribute_no_inline_ void blc_readFlashSize_autoConfigCustomFlashSector(void)
}
/*
*Kite: VVWWXX38C1A4YYZZ
*Vulture: VVWWXXD119C4YYZZ
*Eagle: VVWWXX
* Kite: VVWWXX38C1A4YYZZ
* Vulture: VVWWXXD119C4YYZZ
* Eagle: VVWWXX
* public_mac:
* Kite : VVWWXX 38C1A4
* Vulture : VVWWXX D119C4
@@ -87,15 +87,12 @@ void blc_initMacAddress(int flash_addr, u8 *mac_public, u8 *mac_random_static)
u8 ff_six_byte[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
if (memcmp(mac_read, ff_six_byte, 6)) {
memcpy(mac_public, mac_read, 6); //copy public address from flash
} else { //no public address on flash
memcpy(mac_public, mac_read, 6); // copy public address from flash
} else { // no public address on flash
mac_public[0] = value_rand[0];
mac_public[1] = value_rand[1];
mac_public[2] = value_rand[2];
//TODO
//company id:
mac_public[3] = 0xD1; //company id: 0xC119D1
mac_public[3] = 0xD1; // company id: 0xC119D1
mac_public[4] = 0x19;
mac_public[5] = 0xC4;
@@ -105,7 +102,7 @@ void blc_initMacAddress(int flash_addr, u8 *mac_public, u8 *mac_random_static)
mac_random_static[0] = mac_public[0];
mac_random_static[1] = mac_public[1];
mac_random_static[2] = mac_public[2];
mac_random_static[5] = 0xC0; //for random static
mac_random_static[5] = 0xC0; // for random static
u16 high_2_byte = (mac_read[6] | mac_read[7] << 8);
if (high_2_byte != 0xFFFF) {
b91/b91_ble_sdk/vendor/common/blt_common.h
Vendored
+5 -5
View File
@@ -33,11 +33,11 @@
/**************************** 512 K Flash *****************************/
#ifndef CFG_ADR_MAC_512K_FLASH
#define CFG_ADR_MAC_512K_FLASH 0x7F000 //Eagle and later IC
#define CFG_ADR_MAC_512K_FLASH 0x7F000 // Eagle and later IC
#endif
#ifndef CFG_ADR_CALIBRATION_512K_FLASH
#define CFG_ADR_CALIBRATION_512K_FLASH 0x7E000 //Eagle and later IC
#define CFG_ADR_CALIBRATION_512K_FLASH 0x7E000 // Eagle and later IC
#endif
/**************************** 1 M Flash *******************************/
@@ -78,7 +78,7 @@ static inline void blc_app_setExternalCrystalCapEnable(u8 en)
{
blt_miscParam.ext_cap_en = en;
analog_write_reg8(0x8a, analog_read_reg8(0x8a) | 0x80); //close internal cap
analog_write_reg8(0x8a, analog_read_reg8(0x8a) | 0x80); // close internal cap
}
/**
@@ -89,8 +89,8 @@ static inline void blc_app_setExternalCrystalCapEnable(u8 en)
static inline void blc_app_loadCustomizedParameters(void)
{
if (!blt_miscParam.ext_cap_en) {
//customize freq_offset adjust cap value, if not customized, default ana_8A is 0x60
//for 1M Flash, flash_sector_calibration equals to 0xFE000
// customize freq_offset adjust cap value, if not customized, default ana_8A is 0x60
// for 1M Flash, flash_sector_calibration equals to 0xFE000
if (flash_sector_calibration) {
u8 cap_frqoft;
flash_read_page(flash_sector_calibration + CALIB_OFFSET_CAP_INFO, 1, &cap_frqoft);
b91/b91_ble_sdk/vendor/common/blt_led.c
Vendored
+6 -7
View File
@@ -41,8 +41,7 @@ void device_led_on_off(u8 on)
* @return none
*/
void device_led_init(u32 gpio, u8 polarity)
{ //polarity: 1 for high led on, 0 for low led on
{ // polarity: 1 for high led on, 0 for low led on
#if (BLT_APP_LED_ENABLE)
device_led.gpio_led = gpio;
device_led.polar = !polarity;
@@ -60,17 +59,17 @@ int device_led_setup(led_cfg_t led_cfg)
{
#if (BLT_APP_LED_ENABLE)
if (device_led.repeatCount && device_led.priority >= led_cfg.priority) {
return 0; //new led event priority not higher than the not ongoing one
return 0; // new led event priority not higher than the not ongoing one
} else {
device_led.onTime_ms = led_cfg.onTime_ms;
device_led.offTime_ms = led_cfg.offTime_ms;
device_led.repeatCount = led_cfg.repeatCount;
device_led.priority = led_cfg.priority;
if (led_cfg.repeatCount == 0xff) { //for long on/long off
if (led_cfg.repeatCount == 0xff) { // for long on/long off
device_led.repeatCount = 0;
} else { //process one of on/off Time is zero situation
if (!device_led.onTime_ms) { //onTime is zero
} else { // process one of on/off Time is zero situation
if (!device_led.onTime_ms) { // onTime is zero
device_led.offTime_ms *= device_led.repeatCount;
device_led.repeatCount = 1;
} else if (!device_led.offTime_ms) {
@@ -100,7 +99,7 @@ void led_proc(void)
if (device_led.isOn) {
if (clock_time_exceed(device_led.startTick, device_led.onTime_ms * 1000)) {
device_led_on_off(0);
if (device_led.offTime_ms) { //offTime not zero
if (device_led.offTime_ms) { // offTime not zero
device_led.startTick += device_led.onTime_ms * SYSTEM_TIMER_TICK_1MS;
} else {
device_led.repeatCount = 0;
b91/b91_ble_sdk/vendor/common/blt_led.h
Vendored
+5 -7
View File
@@ -31,24 +31,22 @@
#define BLT_APP_LED_ENABLE 0
#endif
//led management
// led management
/**
* @brief Configure the parameters for led event
*/
typedef struct
{
typedef struct {
unsigned short onTime_ms;
unsigned short offTime_ms;
unsigned char repeatCount; //0xff special for long on(offTime_ms=0)/long off(onTime_ms=0)
unsigned char priority; //0x00 < 0x01 < 0x02 < 0x04 < 0x08 < 0x10 < 0x20 < 0x40 < 0x80
unsigned char repeatCount; // 0xff special for long on(offTime_ms=0)/long off(onTime_ms=0)
unsigned char priority; // 0x00 < 0x01 < 0x02 < 0x04 < 0x08 < 0x10 < 0x20 < 0x40 < 0x80
} led_cfg_t;
/**
* @brief the status of led event
*/
typedef struct
{
typedef struct {
unsigned char isOn;
unsigned char polar;
unsigned char repeatCount;
b91/b91_ble_sdk/vendor/common/blt_soft_timer.c
Vendored
+24 -30
View File
@@ -38,19 +38,19 @@ int blt_soft_timer_sort(void)
{
if (blt_timer.currentNum < 1 || blt_timer.currentNum > MAX_TIMER_NUM) {
return 0;
} else {
//BubbleSort
int n = blt_timer.currentNum;
u8 temp[sizeof(blt_time_event_t)];
for (int i = 0; i < n - 1; i++) {
for (int j = 0; j < n - i - 1; j++) {
if (TIME_COMPARE_BIG(blt_timer.timer[j].t, blt_timer.timer[j + 1].t)) {
//swap
memcpy(temp, &blt_timer.timer[j], sizeof(blt_time_event_t));
memcpy(&blt_timer.timer[j], &blt_timer.timer[j + 1], sizeof(blt_time_event_t));
memcpy(&blt_timer.timer[j + 1], temp, sizeof(blt_time_event_t));
}
}
// BubbleSort
int n = blt_timer.currentNum;
u8 temp[sizeof(blt_time_event_t)];
for (int i = 0; i < n - 1; i++) {
for (int j = 0; j < n - i - 1; j++) {
if (TIME_COMPARE_BIG(blt_timer.timer[j].t, blt_timer.timer[j + 1].t)) {
// swap
memcpy(temp, &blt_timer.timer[j], sizeof(blt_time_event_t));
memcpy(&blt_timer.timer[j], &blt_timer.timer[j + 1], sizeof(blt_time_event_t));
memcpy(&blt_timer.timer[j + 1], temp, sizeof(blt_time_event_t));
}
}
}
@@ -69,7 +69,7 @@ int blt_soft_timer_add(blt_timer_callback_t func, u32 interval_us)
{
u32 now = clock_time();
if (blt_timer.currentNum >= MAX_TIMER_NUM) { //timer full
if (blt_timer.currentNum >= MAX_TIMER_NUM) { // timer full
return 0;
} else {
blt_timer.timer[blt_timer.currentNum].cb = func;
@@ -116,17 +116,15 @@ int blt_soft_timer_delete_by_index(u8 index)
*/
int blt_soft_timer_delete(blt_timer_callback_t func)
{
for (int i = 0; i < blt_timer.currentNum; i++) {
if (blt_timer.timer[i].cb == func) {
blt_soft_timer_delete_by_index(i);
if (i == 0) { //The most recent timer is deleted, and the time needs to be updated
if (i == 0) { // The most recent timer is deleted, and the time needs to be updated
if ((u32)(blt_timer.timer[0].t - clock_time()) < 3000 * SYSTEM_TIMER_TICK_1MS) {
bls_pm_setAppWakeupLowPower(blt_timer.timer[0].t, 1);
} else {
bls_pm_setAppWakeupLowPower(0, 0); //disable
bls_pm_setAppWakeupLowPower(0, 0); // disable
}
}
@@ -144,12 +142,12 @@ int blt_soft_timer_delete(blt_timer_callback_t func)
*/
void blt_soft_timer_process(int type)
{
if (type == CALLBACK_ENTRY) { //callback trigger
if (type == CALLBACK_ENTRY) { // callback trigger
}
u32 now = clock_time();
if (!blt_timer.currentNum) {
bls_pm_setAppWakeupLowPower(0, 0); //disable
bls_pm_setAppWakeupLowPower(0, 0); // disable
return;
}
@@ -160,19 +158,16 @@ void blt_soft_timer_process(int type)
int change_flg = 0;
int result;
for (int i = 0; i < blt_timer.currentNum; i++) {
if (blt_is_timer_expired(blt_timer.timer[i].t, now)) { //timer trigger
if (blt_is_timer_expired(blt_timer.timer[i].t, now)) { // timer trigger
if (blt_timer.timer[i].cb == NULL) {
} else {
result = blt_timer.timer[i].cb();
if (result < 0) {
blt_soft_timer_delete_by_index(i);
} else if (result == 0) {
change_flg = 1;
blt_timer.timer[i].t = now + blt_timer.timer[i].interval;
} else { //set new timer interval
} else { // set new timer interval
change_flg = 1;
blt_timer.timer[i].interval = result * SYSTEM_TIMER_TICK_1US;
blt_timer.timer[i].t = now + blt_timer.timer[i].interval;
@@ -181,7 +176,7 @@ void blt_soft_timer_process(int type)
}
}
if (blt_timer.currentNum) { //timer table not empty
if (blt_timer.currentNum) { // timer table not empty
if (change_flg) {
blt_soft_timer_sort();
}
@@ -189,11 +184,10 @@ void blt_soft_timer_process(int type)
if ((u32)(blt_timer.timer[0].t - now) < 3000 * SYSTEM_TIMER_TICK_1MS) {
bls_pm_setAppWakeupLowPower(blt_timer.timer[0].t, 1);
} else {
bls_pm_setAppWakeupLowPower(0, 0); //disable
bls_pm_setAppWakeupLowPower(0, 0); // disable
}
} else {
bls_pm_setAppWakeupLowPower(0, 0); //disable
bls_pm_setAppWakeupLowPower(0, 0); // disable
}
}
@@ -207,5 +201,5 @@ void blt_soft_timer_init(void)
bls_pm_registerAppWakeupLowPowerCb(blt_soft_timer_process);
}
#endif //end of BLT_SOFTWARE_TIMER_ENABLE
#endif // end of BLT_SOFTWARE_TIMER_ENABLE
#endif
b91/b91_ble_sdk/vendor/common/blt_soft_timer.h
Vendored
+10 -12
View File
@@ -20,23 +20,23 @@
#include "vendor/common/user_config.h"
//user define
// user define
#ifndef BLT_SOFTWARE_TIMER_ENABLE
#define BLT_SOFTWARE_TIMER_ENABLE 0 //enable or disable
#define BLT_SOFTWARE_TIMER_ENABLE 0 // enable or disable
#endif
#define MAX_TIMER_NUM 4 //timer max number
#define MAX_TIMER_NUM 4 // timer max number
#define MAINLOOP_ENTRY 0
#define CALLBACK_ENTRY 1
//if t1 < t2 return 1
// if t1 < t2 return 1
#define TIME_COMPARE_SMALL(t1, t2) ((u32)((t2) - (t1)) < BIT(30))
// if t1 > t2 return 1
#define TIME_COMPARE_BIG(t1, t2) ((u32)((t1) - (t2)) < BIT(30))
#define BLT_TIMER_SAFE_MARGIN_PRE (SYSTEM_TIMER_TICK_1US << 7) //128 us
#define BLT_TIMER_SAFE_MARGIN_PRE (SYSTEM_TIMER_TICK_1US << 7) // 128 us
#define BLT_TIMER_SAFE_MARGIN_POST (SYSTEM_TIMER_TICK_1S << 2) // 4S
/**
@@ -56,22 +56,20 @@ static int inline blt_is_timer_expired(u32 t, u32 now)
*/
typedef int (*blt_timer_callback_t)(void);
typedef struct blt_time_event_t
{
typedef struct blt_time_event_t {
blt_timer_callback_t cb;
u32 t;
u32 interval;
} blt_time_event_t;
// timer table managemnt
typedef struct blt_soft_timer_t
{
blt_time_event_t timer[MAX_TIMER_NUM]; //timer0 - timer3
u8 currentNum; //total valid timer num
typedef struct blt_soft_timer_t {
blt_time_event_t timer[MAX_TIMER_NUM]; // timer0 - timer3
u8 currentNum; // total valid timer num
} blt_soft_timer_t;
//////////////////////// USER INTERFACE ///////////////////////////////////
//return 0 means Fail, others OK
// return 0 means Fail, others OK
/**
* @brief This function is used to add new software timer task
* @param[in] func - callback function for software timer task

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