mirror of
https://github.com/openharmony/third_party_cmsis.git
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Description: 更新cmsis 版本到6.0.0版本
IssueNo: https://gitee.com/openharmony/third_party_cmsis/issues/I9FAWT Feature Or Bugfix: Feature Binary Source: No Signed-off-by: hw_llm <liu.limin@huawei.com>
This commit is contained in:
hw_llm
@@ -0,0 +1,775 @@
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/*
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* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/*
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* CMSIS-Core(A) Compiler ARMClang (Arm Compiler 6) Header File
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*/
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#ifndef __CMSIS_ARMCLANG_A_H
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#define __CMSIS_ARMCLANG_A_H
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#pragma clang system_header /* treat file as system include file */
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/* CMSIS compiler specific defines */
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#ifndef __ASM
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#define __ASM __asm
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#endif
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#ifndef __INLINE
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#define __INLINE __inline
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#endif
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#ifndef __FORCEINLINE
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#define __FORCEINLINE __attribute__((always_inline))
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#endif
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#ifndef __STATIC_INLINE
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#define __STATIC_INLINE static __inline
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#endif
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#ifndef __STATIC_FORCEINLINE
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#define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
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#endif
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#ifndef __NO_RETURN
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#define __NO_RETURN __attribute__((__noreturn__))
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#endif
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#ifndef CMSIS_DEPRECATED
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#define CMSIS_DEPRECATED __attribute__((deprecated))
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#endif
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#ifndef __USED
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#define __USED __attribute__((used))
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#endif
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#ifndef __WEAK
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#define __WEAK __attribute__((weak))
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed, aligned(1)))
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#endif
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#ifndef __PACKED_STRUCT
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#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
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#endif
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#ifndef __UNALIGNED_UINT16_WRITE
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wpacked"
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/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
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__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
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#pragma clang diagnostic pop
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#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT16_READ
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wpacked"
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/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
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__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
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#pragma clang diagnostic pop
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#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __UNALIGNED_UINT32_WRITE
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wpacked"
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/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
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__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
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#pragma clang diagnostic pop
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#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
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#endif
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#ifndef __UNALIGNED_UINT32_READ
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wpacked"
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__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
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#pragma clang diagnostic pop
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#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
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#endif
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#ifndef __ALIGNED
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#define __ALIGNED(x) __attribute__((aligned(x)))
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#endif
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#ifndef __PACKED
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#define __PACKED __attribute__((packed))
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#endif
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#ifndef __COMPILER_BARRIER
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#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
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#endif
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/* ########################## Core Instruction Access ######################### */
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/**
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\brief No Operation
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\details No Operation does nothing. This instruction can be used for code alignment purposes.
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*/
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#define __NOP __builtin_arm_nop
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/**
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\brief Wait For Interrupt
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\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
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*/
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#define __WFI __builtin_arm_wfi
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/**
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\brief Wait For Event
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\details Wait For Event is a hint instruction that permits the processor to enter
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a low-power state until one of a number of events occurs.
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*/
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#define __WFE __builtin_arm_wfe
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/**
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\brief Send Event
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\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
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*/
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#define __SEV __builtin_arm_sev
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/**
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\brief Instruction Synchronization Barrier
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\details Instruction Synchronization Barrier flushes the pipeline in the processor,
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so that all instructions following the ISB are fetched from cache or memory,
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after the instruction has been completed.
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*/
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#define __ISB() __builtin_arm_isb(0xF)
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/**
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\brief Data Synchronization Barrier
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\details Acts as a special kind of Data Memory Barrier.
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It completes when all explicit memory accesses before this instruction complete.
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*/
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#define __DSB() __builtin_arm_dsb(0xF)
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/**
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\brief Data Memory Barrier
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\details Ensures the apparent order of the explicit memory operations before
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and after the instruction, without ensuring their completion.
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*/
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#define __DMB() __builtin_arm_dmb(0xF)
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/**
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\brief Reverse byte order (32 bit)
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\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REV(value) __builtin_bswap32(value)
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REV16(value) __ROR(__REV(value), 16)
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/**
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\brief Reverse byte order (16 bit)
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\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __REVSH(value) (int16_t)__builtin_bswap16(value)
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/**
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\brief Rotate Right in unsigned value (32 bit)
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\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
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\param [in] op1 Value to rotate
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\param [in] op2 Number of Bits to rotate
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\return Rotated value
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*/
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__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
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{
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op2 %= 32U;
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if (op2 == 0U)
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{
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return op1;
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}
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return (op1 >> op2) | (op1 << (32U - op2));
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}
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/**
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\brief Breakpoint
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\details Causes the processor to enter Debug state.
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Debug tools can use this to investigate system state when the instruction at a particular address is reached.
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\param [in] value is ignored by the processor.
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If required, a debugger can use it to store additional information about the breakpoint.
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*/
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#define __BKPT(value) __ASM volatile ("bkpt "#value)
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/**
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\brief Reverse bit order of value
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\details Reverses the bit order of the given value.
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\param [in] value Value to reverse
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\return Reversed value
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*/
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#define __RBIT __builtin_arm_rbit
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/**
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\brief Count leading zeros
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\details Counts the number of leading zeros of a data value.
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\param [in] value Value to count the leading zeros
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\return number of leading zeros in value
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*/
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__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
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{
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/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
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__builtin_clz(0) is undefined behaviour, so handle this case specially.
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This guarantees ARM-compatible results if happening to compile on a non-ARM
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target, and ensures the compiler doesn't decide to activate any
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optimisations using the logic "value was passed to __builtin_clz, so it
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is non-zero".
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ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
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single CLZ instruction.
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*/
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if (value == 0U)
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{
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return 32U;
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}
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return __builtin_clz(value);
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}
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/**
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\brief LDR Exclusive (8 bit)
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\details Executes a exclusive LDR instruction for 8 bit value.
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\param [in] ptr Pointer to data
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\return value of type uint8_t at (*ptr)
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*/
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#define __LDREXB (uint8_t)__builtin_arm_ldrex
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/**
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\brief LDR Exclusive (16 bit)
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\details Executes a exclusive LDR instruction for 16 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint16_t at (*ptr)
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*/
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#define __LDREXH (uint16_t)__builtin_arm_ldrex
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/**
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\brief LDR Exclusive (32 bit)
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\details Executes a exclusive LDR instruction for 32 bit values.
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\param [in] ptr Pointer to data
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\return value of type uint32_t at (*ptr)
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*/
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#define __LDREXW (uint32_t)__builtin_arm_ldrex
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/**
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\brief STR Exclusive (8 bit)
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\details Executes a exclusive STR instruction for 8 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXB (uint32_t)__builtin_arm_strex
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/**
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\brief STR Exclusive (16 bit)
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\details Executes a exclusive STR instruction for 16 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXH (uint32_t)__builtin_arm_strex
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/**
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\brief STR Exclusive (32 bit)
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\details Executes a exclusive STR instruction for 32 bit values.
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\param [in] value Value to store
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\param [in] ptr Pointer to location
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\return 0 Function succeeded
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\return 1 Function failed
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*/
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#define __STREXW (uint32_t)__builtin_arm_strex
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/**
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\brief Remove the exclusive lock
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\details Removes the exclusive lock which is created by LDREX.
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*/
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#define __CLREX __builtin_arm_clrex
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/**
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\brief Signed Saturate
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\details Saturates a signed value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (1..32)
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\return Saturated value
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*/
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#define __SSAT __builtin_arm_ssat
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/**
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\brief Unsigned Saturate
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\details Saturates an unsigned value.
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\param [in] value Value to be saturated
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\param [in] sat Bit position to saturate to (0..31)
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\return Saturated value
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*/
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#define __USAT __builtin_arm_usat
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/**
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\brief Rotate Right with Extend (32 bit)
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\details Moves each bit of a bitstring right by one bit.
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The carry input is shifted in at the left end of the bitstring.
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\param [in] value Value to rotate
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\return Rotated value
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*/
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__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
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{
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uint32_t result;
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__ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value));
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return (result);
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}
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/**
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\brief LDRT Unprivileged (8 bit)
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\details Executes a Unprivileged LDRT instruction for 8 bit value.
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\param [in] ptr Pointer to data
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\return value of type uint8_t at (*ptr)
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*/
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__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
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{
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uint32_t result;
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__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
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return ((uint8_t)result); /* Add explicit type cast here */
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}
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|
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|
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/**
|
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\brief LDRT Unprivileged (16 bit)
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\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
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\param [in] ptr Pointer to data
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\return value of type uint16_t at (*ptr)
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*/
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__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
|
||||
{
|
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uint32_t result;
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|
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__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
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return ((uint16_t)result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
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\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
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||||
return (result);
|
||||
}
|
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|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
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\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) );
|
||||
}
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
|
||||
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
|
||||
|
||||
#define __SADD8 __builtin_arm_sadd8
|
||||
#define __QADD8 __builtin_arm_qadd8
|
||||
#define __SHADD8 __builtin_arm_shadd8
|
||||
#define __UADD8 __builtin_arm_uadd8
|
||||
#define __UQADD8 __builtin_arm_uqadd8
|
||||
#define __UHADD8 __builtin_arm_uhadd8
|
||||
#define __SSUB8 __builtin_arm_ssub8
|
||||
#define __QSUB8 __builtin_arm_qsub8
|
||||
#define __SHSUB8 __builtin_arm_shsub8
|
||||
#define __USUB8 __builtin_arm_usub8
|
||||
#define __UQSUB8 __builtin_arm_uqsub8
|
||||
#define __UHSUB8 __builtin_arm_uhsub8
|
||||
#define __SADD16 __builtin_arm_sadd16
|
||||
#define __QADD16 __builtin_arm_qadd16
|
||||
#define __SHADD16 __builtin_arm_shadd16
|
||||
#define __UADD16 __builtin_arm_uadd16
|
||||
#define __UQADD16 __builtin_arm_uqadd16
|
||||
#define __UHADD16 __builtin_arm_uhadd16
|
||||
#define __SSUB16 __builtin_arm_ssub16
|
||||
#define __QSUB16 __builtin_arm_qsub16
|
||||
#define __SHSUB16 __builtin_arm_shsub16
|
||||
#define __USUB16 __builtin_arm_usub16
|
||||
#define __UQSUB16 __builtin_arm_uqsub16
|
||||
#define __UHSUB16 __builtin_arm_uhsub16
|
||||
#define __SASX __builtin_arm_sasx
|
||||
#define __QASX __builtin_arm_qasx
|
||||
#define __SHASX __builtin_arm_shasx
|
||||
#define __UASX __builtin_arm_uasx
|
||||
#define __UQASX __builtin_arm_uqasx
|
||||
#define __UHASX __builtin_arm_uhasx
|
||||
#define __SSAX __builtin_arm_ssax
|
||||
#define __QSAX __builtin_arm_qsax
|
||||
#define __SHSAX __builtin_arm_shsax
|
||||
#define __USAX __builtin_arm_usax
|
||||
#define __UQSAX __builtin_arm_uqsax
|
||||
#define __UHSAX __builtin_arm_uhsax
|
||||
#define __USAD8 __builtin_arm_usad8
|
||||
#define __USADA8 __builtin_arm_usada8
|
||||
#define __SSAT16 __builtin_arm_ssat16
|
||||
#define __USAT16 __builtin_arm_usat16
|
||||
#define __UXTB16 __builtin_arm_uxtb16
|
||||
#define __UXTAB16 __builtin_arm_uxtab16
|
||||
#define __SXTB16 __builtin_arm_sxtb16
|
||||
#define __SXTAB16 __builtin_arm_sxtab16
|
||||
#define __SMUAD __builtin_arm_smuad
|
||||
#define __SMUADX __builtin_arm_smuadx
|
||||
#define __SMLAD __builtin_arm_smlad
|
||||
#define __SMLADX __builtin_arm_smladx
|
||||
#define __SMLALD __builtin_arm_smlald
|
||||
#define __SMLALDX __builtin_arm_smlaldx
|
||||
#define __SMUSD __builtin_arm_smusd
|
||||
#define __SMUSDX __builtin_arm_smusdx
|
||||
#define __SMLSD __builtin_arm_smlsd
|
||||
#define __SMLSDX __builtin_arm_smlsdx
|
||||
#define __SMLSLD __builtin_arm_smlsld
|
||||
#define __SMLSLDX __builtin_arm_smlsldx
|
||||
#define __SEL __builtin_arm_sel
|
||||
#define __QADD __builtin_arm_qadd
|
||||
#define __QSUB __builtin_arm_qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
|
||||
|
||||
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
#endif /* (__ARM_FEATURE_DSP == 1) */
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i" : : : "memory");
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i" : : : "memory");
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__ARM_FP >= 1)
|
||||
return __builtin_arm_get_fpscr();
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__ARM_FP >= 1)
|
||||
__builtin_arm_set_fpscr(fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get CPSR Register
|
||||
\return CPSR Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief Set CPSR Register
|
||||
\param [in] cpsr CPSR value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
|
||||
{
|
||||
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
|
||||
}
|
||||
|
||||
/** \brief Get Mode
|
||||
\return Processor Mode
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_mode(void)
|
||||
{
|
||||
return (__get_CPSR() & 0x1FU);
|
||||
}
|
||||
|
||||
/** \brief Set Mode
|
||||
\param [in] mode Mode value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
|
||||
{
|
||||
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
|
||||
}
|
||||
|
||||
/** \brief Get Stack Pointer
|
||||
\return Stack Pointer value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_SP(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set Stack Pointer
|
||||
\param [in] stack Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
|
||||
{
|
||||
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
|
||||
}
|
||||
|
||||
/** \brief Get USR/SYS Stack Pointer
|
||||
\return USR/SYS Stack Pointer value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
|
||||
{
|
||||
uint32_t cpsr;
|
||||
uint32_t result;
|
||||
__ASM volatile(
|
||||
"MRS %0, cpsr \n"
|
||||
"CPS #0x1F \n" // no effect in USR mode
|
||||
"MOV %1, sp \n"
|
||||
"MSR cpsr_c, %0 \n" // no effect in USR mode
|
||||
"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
|
||||
);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set USR/SYS Stack Pointer
|
||||
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
|
||||
{
|
||||
uint32_t cpsr;
|
||||
__ASM volatile(
|
||||
"MRS %0, cpsr \n"
|
||||
"CPS #0x1F \n" // no effect in USR mode
|
||||
"MOV sp, %1 \n"
|
||||
"MSR cpsr_c, %0 \n" // no effect in USR mode
|
||||
"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
|
||||
);
|
||||
}
|
||||
|
||||
/** \brief Get FPEXC
|
||||
\return Floating Point Exception Control register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
uint32_t result;
|
||||
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** \brief Set FPEXC
|
||||
\param [in] fpexc Floating Point Exception Control value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Include common core functions to access Coprocessor 15 registers
|
||||
*/
|
||||
|
||||
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
|
||||
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
|
||||
|
||||
#include "cmsis_cp15.h"
|
||||
|
||||
/** \brief Enable Floating Point Unit
|
||||
|
||||
Critical section, called from undef handler, so systick is disabled
|
||||
*/
|
||||
__STATIC_INLINE void __FPU_Enable(void)
|
||||
{
|
||||
__ASM volatile(
|
||||
// Permit access to VFP/NEON, registers by modifying CPACR
|
||||
" MRC p15,0,R1,c1,c0,2 \n"
|
||||
" ORR R1,R1,#0x00F00000 \n"
|
||||
" MCR p15,0,R1,c1,c0,2 \n"
|
||||
|
||||
// Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
|
||||
" ISB \n"
|
||||
|
||||
// Enable VFP/NEON
|
||||
" VMRS R1,FPEXC \n"
|
||||
" ORR R1,R1,#0x40000000 \n"
|
||||
" VMSR FPEXC,R1 \n"
|
||||
|
||||
// Initialise VFP/NEON registers to 0
|
||||
" MOV R2,#0 \n"
|
||||
|
||||
// Initialise D16 registers to 0
|
||||
" VMOV D0, R2,R2 \n"
|
||||
" VMOV D1, R2,R2 \n"
|
||||
" VMOV D2, R2,R2 \n"
|
||||
" VMOV D3, R2,R2 \n"
|
||||
" VMOV D4, R2,R2 \n"
|
||||
" VMOV D5, R2,R2 \n"
|
||||
" VMOV D6, R2,R2 \n"
|
||||
" VMOV D7, R2,R2 \n"
|
||||
" VMOV D8, R2,R2 \n"
|
||||
" VMOV D9, R2,R2 \n"
|
||||
" VMOV D10,R2,R2 \n"
|
||||
" VMOV D11,R2,R2 \n"
|
||||
" VMOV D12,R2,R2 \n"
|
||||
" VMOV D13,R2,R2 \n"
|
||||
" VMOV D14,R2,R2 \n"
|
||||
" VMOV D15,R2,R2 \n"
|
||||
|
||||
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
|
||||
// Initialise D32 registers to 0
|
||||
" VMOV D16,R2,R2 \n"
|
||||
" VMOV D17,R2,R2 \n"
|
||||
" VMOV D18,R2,R2 \n"
|
||||
" VMOV D19,R2,R2 \n"
|
||||
" VMOV D20,R2,R2 \n"
|
||||
" VMOV D21,R2,R2 \n"
|
||||
" VMOV D22,R2,R2 \n"
|
||||
" VMOV D23,R2,R2 \n"
|
||||
" VMOV D24,R2,R2 \n"
|
||||
" VMOV D25,R2,R2 \n"
|
||||
" VMOV D26,R2,R2 \n"
|
||||
" VMOV D27,R2,R2 \n"
|
||||
" VMOV D28,R2,R2 \n"
|
||||
" VMOV D29,R2,R2 \n"
|
||||
" VMOV D30,R2,R2 \n"
|
||||
" VMOV D31,R2,R2 \n"
|
||||
#endif
|
||||
|
||||
// Initialise FPSCR to a known state
|
||||
" VMRS R1,FPSCR \n"
|
||||
" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
||||
" AND R1,R1,R2 \n"
|
||||
" VMSR FPSCR,R1 "
|
||||
: : : "cc", "r1", "r2"
|
||||
);
|
||||
}
|
||||
|
||||
#endif /* __CMSIS_ARMCLANG_A_H */
|
||||
@@ -0,0 +1,913 @@
|
||||
/*
|
||||
* Copyright (c) 2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(A) Compiler LLVM/Clang Header File
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_CLANG_A_H
|
||||
#define __CMSIS_CLANG_A_H
|
||||
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
|
||||
#if (__ARM_ACLE >= 200)
|
||||
#include <arm_acle.h>
|
||||
#else
|
||||
#error Compiler must support ACLE V2.0
|
||||
#endif /* (__ARM_ACLE >= 200) */
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE __attribute__((always_inline))
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#endif
|
||||
#ifndef CMSIS_DEPRECATED
|
||||
#define CMSIS_DEPRECATED __attribute__((deprecated))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wpacked"
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#pragma clang diagnostic pop
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wpacked"
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#pragma clang diagnostic pop
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wpacked"
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#pragma clang diagnostic pop
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wpacked"
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#pragma clang diagnostic pop
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
|
||||
#endif
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP() __ASM volatile ("nop")
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI() __ASM volatile ("wfi":::"memory")
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE() __ASM volatile ("wfe":::"memory")
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV() __ASM volatile ("sev")
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||||
return __builtin_bswap32(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return result;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM ("rev16 %0, %1" : "=r" (result) : "r" (value));
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
return (int16_t)__builtin_bswap16(value);
|
||||
#else
|
||||
int16_t result;
|
||||
|
||||
__ASM ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return result;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
op2 %= 32U;
|
||||
if (op2 == 0U)
|
||||
{
|
||||
return op1;
|
||||
}
|
||||
return (op1 >> op2) | (op1 << (32U - op2));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
|
||||
__builtin_clz(0) is undefined behaviour, so handle this case specially.
|
||||
This guarantees ARM-compatible results if happening to compile on a non-ARM
|
||||
target, and ensures the compiler doesn't decide to activate any
|
||||
optimisations using the logic "value was passed to __builtin_clz, so it
|
||||
is non-zero".
|
||||
*/
|
||||
if (value == 0U)
|
||||
{
|
||||
return 32U;
|
||||
}
|
||||
return __builtin_clz(value);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex" ::: "memory");
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] ARG1 Value to be saturated
|
||||
\param [in] ARG2 Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1, ARG2) \
|
||||
__extension__ \
|
||||
({ \
|
||||
int32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] ARG1 Value to be saturated
|
||||
\param [in] ARG2 Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1, ARG2) \
|
||||
__extension__ \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value));
|
||||
return (result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return ((uint8_t)result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return ((uint16_t)result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strbt %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strht %1, %0, #0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strt %1, %0, #0" : "=Q" (*ptr) : "r" (value) );
|
||||
}
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i" : : : "memory");
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f" : : : "memory");
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__ARM_FP >= 1)
|
||||
return __builtin_arm_get_fpscr();
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__ARM_FP >= 1)
|
||||
__builtin_arm_set_fpscr(fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
|
||||
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
|
||||
|
||||
#define __SADD8 __builtin_arm_sadd8
|
||||
#define __QADD8 __builtin_arm_qadd8
|
||||
#define __SHADD8 __builtin_arm_shadd8
|
||||
#define __UADD8 __builtin_arm_uadd8
|
||||
#define __UQADD8 __builtin_arm_uqadd8
|
||||
#define __UHADD8 __builtin_arm_uhadd8
|
||||
#define __SSUB8 __builtin_arm_ssub8
|
||||
#define __QSUB8 __builtin_arm_qsub8
|
||||
#define __SHSUB8 __builtin_arm_shsub8
|
||||
#define __USUB8 __builtin_arm_usub8
|
||||
#define __UQSUB8 __builtin_arm_uqsub8
|
||||
#define __UHSUB8 __builtin_arm_uhsub8
|
||||
#define __SADD16 __builtin_arm_sadd16
|
||||
#define __QADD16 __builtin_arm_qadd16
|
||||
#define __SHADD16 __builtin_arm_shadd16
|
||||
#define __UADD16 __builtin_arm_uadd16
|
||||
#define __UQADD16 __builtin_arm_uqadd16
|
||||
#define __UHADD16 __builtin_arm_uhadd16
|
||||
#define __SSUB16 __builtin_arm_ssub16
|
||||
#define __QSUB16 __builtin_arm_qsub16
|
||||
#define __SHSUB16 __builtin_arm_shsub16
|
||||
#define __USUB16 __builtin_arm_usub16
|
||||
#define __UQSUB16 __builtin_arm_uqsub16
|
||||
#define __UHSUB16 __builtin_arm_uhsub16
|
||||
#define __SASX __builtin_arm_sasx
|
||||
#define __QASX __builtin_arm_qasx
|
||||
#define __SHASX __builtin_arm_shasx
|
||||
#define __UASX __builtin_arm_uasx
|
||||
#define __UQASX __builtin_arm_uqasx
|
||||
#define __UHASX __builtin_arm_uhasx
|
||||
#define __SSAX __builtin_arm_ssax
|
||||
#define __QSAX __builtin_arm_qsax
|
||||
#define __SHSAX __builtin_arm_shsax
|
||||
#define __USAX __builtin_arm_usax
|
||||
#define __UQSAX __builtin_arm_uqsax
|
||||
#define __UHSAX __builtin_arm_uhsax
|
||||
#define __USAD8 __builtin_arm_usad8
|
||||
#define __USADA8 __builtin_arm_usada8
|
||||
#define __SSAT16 __builtin_arm_ssat16
|
||||
#define __USAT16 __builtin_arm_usat16
|
||||
#define __UXTB16 __builtin_arm_uxtb16
|
||||
#define __UXTAB16 __builtin_arm_uxtab16
|
||||
#define __SXTB16 __builtin_arm_sxtb16
|
||||
#define __SXTAB16 __builtin_arm_sxtab16
|
||||
#define __SMUAD __builtin_arm_smuad
|
||||
#define __SMUADX __builtin_arm_smuadx
|
||||
#define __SMLAD __builtin_arm_smlad
|
||||
#define __SMLADX __builtin_arm_smladx
|
||||
#define __SMLALD __builtin_arm_smlald
|
||||
#define __SMLALDX __builtin_arm_smlaldx
|
||||
#define __SMUSD __builtin_arm_smusd
|
||||
#define __SMUSDX __builtin_arm_smusdx
|
||||
#define __SMLSD __builtin_arm_smlsd
|
||||
#define __SMLSDX __builtin_arm_smlsdx
|
||||
#define __SMLSLD __builtin_arm_smlsld
|
||||
#define __SMLSLDX __builtin_arm_smlsldx
|
||||
#define __SEL __builtin_arm_sel
|
||||
#define __QADD __builtin_arm_qadd
|
||||
#define __QSUB __builtin_arm_qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||
__extension__ \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||
__extension__ \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
if (ARG3 == 0) \
|
||||
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||
else \
|
||||
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
|
||||
{
|
||||
uint32_t result;
|
||||
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
|
||||
{
|
||||
__ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate));
|
||||
}
|
||||
else
|
||||
{
|
||||
result = __SXTB16(__ROR(op1, rotate));
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
|
||||
{
|
||||
uint32_t result;
|
||||
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
|
||||
{
|
||||
__ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate));
|
||||
}
|
||||
else
|
||||
{
|
||||
result = __SXTAB16(op1, __ROR(op2, rotate));
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
#endif /* (__ARM_FEATURE_DSP == 1) */
|
||||
/** @} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Get CPSR Register
|
||||
\return CPSR Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief Set CPSR Register
|
||||
\param [in] cpsr CPSR value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
|
||||
{
|
||||
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
|
||||
}
|
||||
|
||||
/** \brief Get Mode
|
||||
\return Processor Mode
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_mode(void)
|
||||
{
|
||||
return (__get_CPSR() & 0x1FU);
|
||||
}
|
||||
|
||||
/** \brief Set Mode
|
||||
\param [in] mode Mode value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
|
||||
{
|
||||
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
|
||||
}
|
||||
|
||||
/** \brief Get Stack Pointer
|
||||
\return Stack Pointer value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_SP(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set Stack Pointer
|
||||
\param [in] stack Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
|
||||
{
|
||||
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
|
||||
}
|
||||
|
||||
/** \brief Get USR/SYS Stack Pointer
|
||||
\return USR/SYS Stack Pointer value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
|
||||
{
|
||||
uint32_t cpsr = __get_CPSR();
|
||||
uint32_t result;
|
||||
__ASM volatile(
|
||||
"CPS #0x1F \n"
|
||||
"MOV %0, sp " : "=r"(result) : : "memory"
|
||||
);
|
||||
__set_CPSR(cpsr);
|
||||
__ISB();
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set USR/SYS Stack Pointer
|
||||
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
|
||||
{
|
||||
uint32_t cpsr = __get_CPSR();
|
||||
__ASM volatile(
|
||||
"CPS #0x1F \n"
|
||||
"MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
|
||||
);
|
||||
__set_CPSR(cpsr);
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** \brief Get FPEXC
|
||||
\return Floating Point Exception Control register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
uint32_t result;
|
||||
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** \brief Set FPEXC
|
||||
\param [in] fpexc Floating Point Exception Control value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Include common core functions to access Coprocessor 15 registers
|
||||
*/
|
||||
|
||||
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
|
||||
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
|
||||
|
||||
#include "cmsis_cp15.h"
|
||||
|
||||
/** \brief Enable Floating Point Unit
|
||||
|
||||
Critical section, called from undef handler, so systick is disabled
|
||||
*/
|
||||
__STATIC_INLINE void __FPU_Enable(void)
|
||||
{
|
||||
// Permit access to VFP/NEON, registers by modifying CPACR
|
||||
const uint32_t cpacr = __get_CPACR();
|
||||
__set_CPACR(cpacr | 0x00F00000ul);
|
||||
__ISB();
|
||||
|
||||
// Enable VFP/NEON
|
||||
const uint32_t fpexc = __get_FPEXC();
|
||||
__set_FPEXC(fpexc | 0x40000000ul);
|
||||
|
||||
__ASM volatile(
|
||||
// Initialise VFP/NEON registers to 0
|
||||
" MOV R2,#0 \n"
|
||||
|
||||
// Initialise D16 registers to 0
|
||||
" VMOV D0, R2,R2 \n"
|
||||
" VMOV D1, R2,R2 \n"
|
||||
" VMOV D2, R2,R2 \n"
|
||||
" VMOV D3, R2,R2 \n"
|
||||
" VMOV D4, R2,R2 \n"
|
||||
" VMOV D5, R2,R2 \n"
|
||||
" VMOV D6, R2,R2 \n"
|
||||
" VMOV D7, R2,R2 \n"
|
||||
" VMOV D8, R2,R2 \n"
|
||||
" VMOV D9, R2,R2 \n"
|
||||
" VMOV D10,R2,R2 \n"
|
||||
" VMOV D11,R2,R2 \n"
|
||||
" VMOV D12,R2,R2 \n"
|
||||
" VMOV D13,R2,R2 \n"
|
||||
" VMOV D14,R2,R2 \n"
|
||||
" VMOV D15,R2,R2 \n"
|
||||
|
||||
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
|
||||
// Initialise D32 registers to 0
|
||||
" VMOV D16,R2,R2 \n"
|
||||
" VMOV D17,R2,R2 \n"
|
||||
" VMOV D18,R2,R2 \n"
|
||||
" VMOV D19,R2,R2 \n"
|
||||
" VMOV D20,R2,R2 \n"
|
||||
" VMOV D21,R2,R2 \n"
|
||||
" VMOV D22,R2,R2 \n"
|
||||
" VMOV D23,R2,R2 \n"
|
||||
" VMOV D24,R2,R2 \n"
|
||||
" VMOV D25,R2,R2 \n"
|
||||
" VMOV D26,R2,R2 \n"
|
||||
" VMOV D27,R2,R2 \n"
|
||||
" VMOV D28,R2,R2 \n"
|
||||
" VMOV D29,R2,R2 \n"
|
||||
" VMOV D30,R2,R2 \n"
|
||||
" VMOV D31,R2,R2 \n"
|
||||
#endif
|
||||
: : : "cc", "r2"
|
||||
);
|
||||
|
||||
// Initialise FPSCR to a known state
|
||||
const uint32_t fpscr = __get_FPSCR();
|
||||
__set_FPSCR(fpscr & 0x00086060ul);
|
||||
}
|
||||
|
||||
/*@} end of group CMSIS_Core_intrinsics */
|
||||
|
||||
#pragma clang diagnostic pop
|
||||
|
||||
#endif /* __CMSIS_CLANG_A_H */
|
||||
@@ -0,0 +1,486 @@
|
||||
/*
|
||||
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(A) Compiler Specific Macros, Functions, Instructions
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_CP15_H
|
||||
#define __CMSIS_CP15_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
/** \brief Get ACTLR
|
||||
\return Auxiliary Control register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 1, 0, 1);
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief Set ACTLR
|
||||
\param [in] actlr Auxiliary Control value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
|
||||
{
|
||||
__set_CP(15, 0, actlr, 1, 0, 1);
|
||||
}
|
||||
|
||||
/** \brief Get CPACR
|
||||
\return Coprocessor Access Control register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 1, 0, 2);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set CPACR
|
||||
\param [in] cpacr Coprocessor Access Control value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
|
||||
{
|
||||
__set_CP(15, 0, cpacr, 1, 0, 2);
|
||||
}
|
||||
|
||||
/** \brief Get DFSR
|
||||
\return Data Fault Status Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 5, 0, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set DFSR
|
||||
\param [in] dfsr Data Fault Status value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
|
||||
{
|
||||
__set_CP(15, 0, dfsr, 5, 0, 0);
|
||||
}
|
||||
|
||||
/** \brief Get IFSR
|
||||
\return Instruction Fault Status Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 5, 0, 1);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set IFSR
|
||||
\param [in] ifsr Instruction Fault Status value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
|
||||
{
|
||||
__set_CP(15, 0, ifsr, 5, 0, 1);
|
||||
}
|
||||
|
||||
/** \brief Get ISR
|
||||
\return Interrupt Status Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_ISR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 12, 1, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Get CBAR
|
||||
\return Configuration Base Address register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 4, result, 15, 0, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Get TTBR0
|
||||
|
||||
This function returns the value of the Translation Table Base Register 0.
|
||||
|
||||
\return Translation Table Base Register 0 value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 2, 0, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set TTBR0
|
||||
|
||||
This function assigns the given value to the Translation Table Base Register 0.
|
||||
|
||||
\param [in] ttbr0 Translation Table Base Register 0 value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
|
||||
{
|
||||
__set_CP(15, 0, ttbr0, 2, 0, 0);
|
||||
}
|
||||
|
||||
/** \brief Get DACR
|
||||
|
||||
This function returns the value of the Domain Access Control Register.
|
||||
|
||||
\return Domain Access Control Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_DACR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 3, 0, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set DACR
|
||||
|
||||
This function assigns the given value to the Domain Access Control Register.
|
||||
|
||||
\param [in] dacr Domain Access Control Register value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
|
||||
{
|
||||
__set_CP(15, 0, dacr, 3, 0, 0);
|
||||
}
|
||||
|
||||
/** \brief Set SCTLR
|
||||
|
||||
This function assigns the given value to the System Control Register.
|
||||
|
||||
\param [in] sctlr System Control Register value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
|
||||
{
|
||||
__set_CP(15, 0, sctlr, 1, 0, 0);
|
||||
}
|
||||
|
||||
/** \brief Get SCTLR
|
||||
\return System Control Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 1, 0, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Get MPIDR
|
||||
|
||||
This function returns the value of the Multiprocessor Affinity Register.
|
||||
|
||||
\return Multiprocessor Affinity Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 0, 0, 5);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Get VBAR
|
||||
|
||||
This function returns the value of the Vector Base Address Register.
|
||||
|
||||
\return Vector Base Address Register
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 12, 0, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set VBAR
|
||||
|
||||
This function assigns the given value to the Vector Base Address Register.
|
||||
|
||||
\param [in] vbar Vector Base Address Register value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
|
||||
{
|
||||
__set_CP(15, 0, vbar, 12, 0, 0);
|
||||
}
|
||||
|
||||
/** \brief Get MVBAR
|
||||
|
||||
This function returns the value of the Monitor Vector Base Address Register.
|
||||
|
||||
\return Monitor Vector Base Address Register
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 12, 0, 1);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set MVBAR
|
||||
|
||||
This function assigns the given value to the Monitor Vector Base Address Register.
|
||||
|
||||
\param [in] mvbar Monitor Vector Base Address Register value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
|
||||
{
|
||||
__set_CP(15, 0, mvbar, 12, 0, 1);
|
||||
}
|
||||
|
||||
#if (defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
|
||||
defined(DOXYGEN)
|
||||
|
||||
/** \brief Set CNTFRQ
|
||||
|
||||
This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
|
||||
|
||||
\param [in] value CNTFRQ Register value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 14, 0, 0);
|
||||
}
|
||||
|
||||
/** \brief Get CNTFRQ
|
||||
|
||||
This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
|
||||
|
||||
\return CNTFRQ Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 14, 0 , 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set CNTP_TVAL
|
||||
|
||||
This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
|
||||
|
||||
\param [in] value CNTP_TVAL Register value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 14, 2, 0);
|
||||
}
|
||||
|
||||
/** \brief Get CNTP_TVAL
|
||||
|
||||
This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
|
||||
|
||||
\return CNTP_TVAL Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 14, 2, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Get CNTPCT
|
||||
|
||||
This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
|
||||
|
||||
\return CNTPCT Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
|
||||
{
|
||||
uint64_t result;
|
||||
__get_CP64(15, 0, result, 14);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set CNTP_CVAL
|
||||
|
||||
This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
|
||||
|
||||
\param [in] value CNTP_CVAL Register value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
|
||||
{
|
||||
__set_CP64(15, 2, value, 14);
|
||||
}
|
||||
|
||||
/** \brief Get CNTP_CVAL
|
||||
|
||||
This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
|
||||
|
||||
\return CNTP_CVAL Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
|
||||
{
|
||||
uint64_t result;
|
||||
__get_CP64(15, 2, result, 14);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set CNTP_CTL
|
||||
|
||||
This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
|
||||
|
||||
\param [in] value CNTP_CTL Register value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 14, 2, 1);
|
||||
}
|
||||
|
||||
/** \brief Get CNTP_CTL register
|
||||
\return CNTP_CTL Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 0, result, 14, 2, 1);
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/** \brief Set TLBIALL
|
||||
|
||||
TLB Invalidate All
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 8, 7, 0);
|
||||
}
|
||||
|
||||
/** \brief Set BPIALL.
|
||||
|
||||
Branch Predictor Invalidate All
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 7, 5, 6);
|
||||
}
|
||||
|
||||
/** \brief Set ICIALLU
|
||||
|
||||
Instruction Cache Invalidate All
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 7, 5, 0);
|
||||
}
|
||||
|
||||
/** \brief Set ICIMVAC
|
||||
|
||||
Instruction Cache Invalidate
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_ICIMVAC(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 7, 5, 1);
|
||||
}
|
||||
|
||||
/** \brief Set DCCMVAC
|
||||
|
||||
Data cache clean
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 7, 10, 1);
|
||||
}
|
||||
|
||||
/** \brief Set DCIMVAC
|
||||
|
||||
Data cache invalidate
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 7, 6, 1);
|
||||
}
|
||||
|
||||
/** \brief Set DCCIMVAC
|
||||
|
||||
Data cache clean and invalidate
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 7, 14, 1);
|
||||
}
|
||||
|
||||
/** \brief Set CSSELR
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 2, value, 0, 0, 0);
|
||||
}
|
||||
|
||||
/** \brief Get CSSELR
|
||||
\return CSSELR Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 2, result, 0, 0, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Get CCSIDR
|
||||
\return CCSIDR Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 1, result, 0, 0, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Get CLIDR
|
||||
\return CLIDR Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__get_CP(15, 1, result, 0, 0, 1);
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set DCISW
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 7, 6, 2);
|
||||
}
|
||||
|
||||
/** \brief Set DCCSW
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 7, 10, 2);
|
||||
}
|
||||
|
||||
/** \brief Set DCCISW
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
|
||||
{
|
||||
__set_CP(15, 0, value, 7, 14, 2);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,936 @@
|
||||
/*
|
||||
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(A) Compiler GCC Header File
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_GCC_A_H
|
||||
#define __CMSIS_GCC_A_H
|
||||
|
||||
/* ignore some GCC warnings */
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wsign-conversion"
|
||||
#pragma GCC diagnostic ignored "-Wconversion"
|
||||
#pragma GCC diagnostic ignored "-Wunused-parameter"
|
||||
|
||||
/* Fallback for __has_builtin */
|
||||
#ifndef __has_builtin
|
||||
#define __has_builtin(x) (0)
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE __attribute__((always_inline))
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#endif
|
||||
#ifndef CMSIS_DEPRECATED
|
||||
#define CMSIS_DEPRECATED __attribute__((deprecated))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpacked"
|
||||
#pragma GCC diagnostic ignored "-Wattributes"
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#pragma GCC diagnostic pop
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpacked"
|
||||
#pragma GCC diagnostic ignored "-Wattributes"
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#pragma GCC diagnostic pop
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpacked"
|
||||
#pragma GCC diagnostic ignored "-Wattributes"
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#pragma GCC diagnostic pop
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wpacked"
|
||||
#pragma GCC diagnostic ignored "-Wattributes"
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#pragma GCC diagnostic pop
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
|
||||
#endif
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP() __ASM volatile ("nop")
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI() __ASM volatile ("wfi":::"memory")
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE() __ASM volatile ("wfe":::"memory")
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV() __ASM volatile ("sev")
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb 0xF":::"memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
|
||||
return __builtin_bswap32(value);
|
||||
#else
|
||||
uint32_t result;
|
||||
|
||||
__ASM ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return result;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM ("rev16 %0, %1" : "=r" (result) : "r" (value));
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
|
||||
{
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
return (int16_t)__builtin_bswap16(value);
|
||||
#else
|
||||
int16_t result;
|
||||
|
||||
__ASM ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return result;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
op2 %= 32U;
|
||||
if (op2 == 0U)
|
||||
{
|
||||
return op1;
|
||||
}
|
||||
return (op1 >> op2) | (op1 << (32U - op2));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __ASM volatile ("bkpt "#value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
|
||||
__builtin_clz(0) is undefined behaviour, so handle this case specially.
|
||||
This guarantees ARM-compatible results if happening to compile on a non-ARM
|
||||
target, and ensures the compiler doesn't decide to activate any
|
||||
optimisations using the logic "value was passed to __builtin_clz, so it
|
||||
is non-zero".
|
||||
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
|
||||
single CLZ instruction.
|
||||
*/
|
||||
if (value == 0U)
|
||||
{
|
||||
return 32U;
|
||||
}
|
||||
return __builtin_clz(value);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint8_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
|
||||
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
#else
|
||||
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
|
||||
accepted by assembler. So has to use following less efficient pattern.
|
||||
*/
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
|
||||
#endif
|
||||
return ((uint16_t) result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex" ::: "memory");
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] ARG1 Value to be saturated
|
||||
\param [in] ARG2 Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1, ARG2) \
|
||||
__extension__ \
|
||||
({ \
|
||||
int32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] ARG1 Value to be saturated
|
||||
\param [in] ARG2 Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1, ARG2) \
|
||||
__extension__ \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rrx %0, %1" : "=r" (result) : "r" (value));
|
||||
return (result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return ((uint8_t)result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return ((uint16_t)result); /* Add explicit type cast here */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
__ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
|
||||
}
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i" : : : "memory");
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f" : : : "memory");
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f" : : : "memory");
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__ARM_FP >= 1)
|
||||
return __builtin_arm_get_fpscr();
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__ARM_FP >= 1)
|
||||
__builtin_arm_set_fpscr(fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
|
||||
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
|
||||
|
||||
#define __SADD8 __builtin_arm_sadd8
|
||||
#define __QADD8 __builtin_arm_qadd8
|
||||
#define __SHADD8 __builtin_arm_shadd8
|
||||
#define __UADD8 __builtin_arm_uadd8
|
||||
#define __UQADD8 __builtin_arm_uqadd8
|
||||
#define __UHADD8 __builtin_arm_uhadd8
|
||||
#define __SSUB8 __builtin_arm_ssub8
|
||||
#define __QSUB8 __builtin_arm_qsub8
|
||||
#define __SHSUB8 __builtin_arm_shsub8
|
||||
#define __USUB8 __builtin_arm_usub8
|
||||
#define __UQSUB8 __builtin_arm_uqsub8
|
||||
#define __UHSUB8 __builtin_arm_uhsub8
|
||||
#define __SADD16 __builtin_arm_sadd16
|
||||
#define __QADD16 __builtin_arm_qadd16
|
||||
#define __SHADD16 __builtin_arm_shadd16
|
||||
#define __UADD16 __builtin_arm_uadd16
|
||||
#define __UQADD16 __builtin_arm_uqadd16
|
||||
#define __UHADD16 __builtin_arm_uhadd16
|
||||
#define __SSUB16 __builtin_arm_ssub16
|
||||
#define __QSUB16 __builtin_arm_qsub16
|
||||
#define __SHSUB16 __builtin_arm_shsub16
|
||||
#define __USUB16 __builtin_arm_usub16
|
||||
#define __UQSUB16 __builtin_arm_uqsub16
|
||||
#define __UHSUB16 __builtin_arm_uhsub16
|
||||
#define __SASX __builtin_arm_sasx
|
||||
#define __QASX __builtin_arm_qasx
|
||||
#define __SHASX __builtin_arm_shasx
|
||||
#define __UASX __builtin_arm_uasx
|
||||
#define __UQASX __builtin_arm_uqasx
|
||||
#define __UHASX __builtin_arm_uhasx
|
||||
#define __SSAX __builtin_arm_ssax
|
||||
#define __QSAX __builtin_arm_qsax
|
||||
#define __SHSAX __builtin_arm_shsax
|
||||
#define __USAX __builtin_arm_usax
|
||||
#define __UQSAX __builtin_arm_uqsax
|
||||
#define __UHSAX __builtin_arm_uhsax
|
||||
#define __USAD8 __builtin_arm_usad8
|
||||
#define __USADA8 __builtin_arm_usada8
|
||||
#define __SSAT16 __builtin_arm_ssat16
|
||||
#define __USAT16 __builtin_arm_usat16
|
||||
#define __UXTB16 __builtin_arm_uxtb16
|
||||
#define __UXTAB16 __builtin_arm_uxtab16
|
||||
#define __SXTB16 __builtin_arm_sxtb16
|
||||
#define __SXTAB16 __builtin_arm_sxtab16
|
||||
#define __SMUAD __builtin_arm_smuad
|
||||
#define __SMUADX __builtin_arm_smuadx
|
||||
#define __SMLAD __builtin_arm_smlad
|
||||
#define __SMLADX __builtin_arm_smladx
|
||||
#define __SMLALD __builtin_arm_smlald
|
||||
#define __SMLALDX __builtin_arm_smlaldx
|
||||
#define __SMUSD __builtin_arm_smusd
|
||||
#define __SMUSDX __builtin_arm_smusdx
|
||||
#define __SMLSD __builtin_arm_smlsd
|
||||
#define __SMLSDX __builtin_arm_smlsdx
|
||||
#define __SMLSLD __builtin_arm_smlsld
|
||||
#define __SMLSLDX __builtin_arm_smlsldx
|
||||
#define __SEL __builtin_arm_sel
|
||||
#define __QADD __builtin_arm_qadd
|
||||
#define __QSUB __builtin_arm_qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) \
|
||||
__extension__ \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
__ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) \
|
||||
__extension__ \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
|
||||
if (ARG3 == 0) \
|
||||
__ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
|
||||
else \
|
||||
__ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
|
||||
{
|
||||
uint32_t result;
|
||||
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
|
||||
{
|
||||
__ASM volatile("sxtb16 %0, %1, ROR %2" : "=r"(result) : "r"(op1), "i"(rotate));
|
||||
}
|
||||
else
|
||||
{
|
||||
result = __SXTB16(__ROR(op1, rotate));
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate)
|
||||
{
|
||||
uint32_t result;
|
||||
if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U)))
|
||||
{
|
||||
__ASM volatile("sxtab16 %0, %1, %2, ROR %3" : "=r"(result) : "r"(op1), "r"(op2), "i"(rotate));
|
||||
}
|
||||
else
|
||||
{
|
||||
result = __SXTAB16(op1, __ROR(op2, rotate));
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
#endif /* (__ARM_FEATURE_DSP == 1) */
|
||||
/** @} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
/** \defgroup CMSIS_Core_intrinsics CMSIS Core Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Get CPSR Register
|
||||
\return CPSR Register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
/** \brief Set CPSR Register
|
||||
\param [in] cpsr CPSR value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
|
||||
{
|
||||
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc", "memory");
|
||||
}
|
||||
|
||||
/** \brief Get Mode
|
||||
\return Processor Mode
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_mode(void)
|
||||
{
|
||||
return (__get_CPSR() & 0x1FU);
|
||||
}
|
||||
|
||||
/** \brief Set Mode
|
||||
\param [in] mode Mode value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
|
||||
{
|
||||
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
|
||||
}
|
||||
|
||||
/** \brief Get Stack Pointer
|
||||
\return Stack Pointer value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_SP(void)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set Stack Pointer
|
||||
\param [in] stack Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
|
||||
{
|
||||
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
|
||||
}
|
||||
|
||||
/** \brief Get USR/SYS Stack Pointer
|
||||
\return USR/SYS Stack Pointer value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
|
||||
{
|
||||
uint32_t cpsr = __get_CPSR();
|
||||
uint32_t result;
|
||||
__ASM volatile(
|
||||
"CPS #0x1F \n"
|
||||
"MOV %0, sp " : "=r"(result) : : "memory"
|
||||
);
|
||||
__set_CPSR(cpsr);
|
||||
__ISB();
|
||||
return result;
|
||||
}
|
||||
|
||||
/** \brief Set USR/SYS Stack Pointer
|
||||
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
|
||||
{
|
||||
uint32_t cpsr = __get_CPSR();
|
||||
__ASM volatile(
|
||||
"CPS #0x1F \n"
|
||||
"MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
|
||||
);
|
||||
__set_CPSR(cpsr);
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** \brief Get FPEXC
|
||||
\return Floating Point Exception Control register value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
uint32_t result;
|
||||
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** \brief Set FPEXC
|
||||
\param [in] fpexc Floating Point Exception Control value to set
|
||||
*/
|
||||
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1)
|
||||
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Include common core functions to access Coprocessor 15 registers
|
||||
*/
|
||||
|
||||
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
|
||||
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
|
||||
|
||||
#include "cmsis_cp15.h"
|
||||
|
||||
/** \brief Enable Floating Point Unit
|
||||
|
||||
Critical section, called from undef handler, so systick is disabled
|
||||
*/
|
||||
__STATIC_INLINE void __FPU_Enable(void)
|
||||
{
|
||||
// Permit access to VFP/NEON, registers by modifying CPACR
|
||||
const uint32_t cpacr = __get_CPACR();
|
||||
__set_CPACR(cpacr | 0x00F00000ul);
|
||||
__ISB();
|
||||
|
||||
// Enable VFP/NEON
|
||||
const uint32_t fpexc = __get_FPEXC();
|
||||
__set_FPEXC(fpexc | 0x40000000ul);
|
||||
|
||||
__ASM volatile(
|
||||
// Initialise VFP/NEON registers to 0
|
||||
" MOV R2,#0 \n"
|
||||
|
||||
// Initialise D16 registers to 0
|
||||
" VMOV D0, R2,R2 \n"
|
||||
" VMOV D1, R2,R2 \n"
|
||||
" VMOV D2, R2,R2 \n"
|
||||
" VMOV D3, R2,R2 \n"
|
||||
" VMOV D4, R2,R2 \n"
|
||||
" VMOV D5, R2,R2 \n"
|
||||
" VMOV D6, R2,R2 \n"
|
||||
" VMOV D7, R2,R2 \n"
|
||||
" VMOV D8, R2,R2 \n"
|
||||
" VMOV D9, R2,R2 \n"
|
||||
" VMOV D10,R2,R2 \n"
|
||||
" VMOV D11,R2,R2 \n"
|
||||
" VMOV D12,R2,R2 \n"
|
||||
" VMOV D13,R2,R2 \n"
|
||||
" VMOV D14,R2,R2 \n"
|
||||
" VMOV D15,R2,R2 \n"
|
||||
|
||||
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
|
||||
// Initialise D32 registers to 0
|
||||
" VMOV D16,R2,R2 \n"
|
||||
" VMOV D17,R2,R2 \n"
|
||||
" VMOV D18,R2,R2 \n"
|
||||
" VMOV D19,R2,R2 \n"
|
||||
" VMOV D20,R2,R2 \n"
|
||||
" VMOV D21,R2,R2 \n"
|
||||
" VMOV D22,R2,R2 \n"
|
||||
" VMOV D23,R2,R2 \n"
|
||||
" VMOV D24,R2,R2 \n"
|
||||
" VMOV D25,R2,R2 \n"
|
||||
" VMOV D26,R2,R2 \n"
|
||||
" VMOV D27,R2,R2 \n"
|
||||
" VMOV D28,R2,R2 \n"
|
||||
" VMOV D29,R2,R2 \n"
|
||||
" VMOV D30,R2,R2 \n"
|
||||
" VMOV D31,R2,R2 \n"
|
||||
#endif
|
||||
: : : "cc", "r2"
|
||||
);
|
||||
|
||||
// Initialise FPSCR to a known state
|
||||
const uint32_t fpscr = __get_FPSCR();
|
||||
__set_FPSCR(fpscr & 0x00086060ul);
|
||||
}
|
||||
|
||||
/*@} end of group CMSIS_Core_intrinsics */
|
||||
|
||||
#pragma GCC diagnostic pop
|
||||
|
||||
#endif /* __CMSIS_GCC_A_H */
|
||||
@@ -0,0 +1,558 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2018 IAR Systems
|
||||
* Copyright (c) 2018-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(A) Compiler ICCARM (IAR Compiler for Arm) Header File
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ICCARM_A_H__
|
||||
#define __CMSIS_ICCARM_A_H__
|
||||
|
||||
#ifndef __ICCARM__
|
||||
#error This file should only be compiled by ICCARM
|
||||
#endif
|
||||
|
||||
#pragma system_include
|
||||
|
||||
#define __IAR_FT _Pragma("inline=forced") __intrinsic
|
||||
|
||||
#if (__VER__ >= 8000000)
|
||||
#define __ICCARM_V8 1
|
||||
#else
|
||||
#define __ICCARM_V8 0
|
||||
#endif
|
||||
|
||||
#pragma language=extended
|
||||
|
||||
#ifndef __ALIGNED
|
||||
#if __ICCARM_V8
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#elif (__VER__ >= 7080000)
|
||||
/* Needs IAR language extensions */
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#else
|
||||
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/
|
||||
#if __ARM_ARCH_7A__
|
||||
/* Macro already defined */
|
||||
#else
|
||||
#if defined(__ARM7A__)
|
||||
#define __ARM_ARCH_7A__ 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
|
||||
#endif
|
||||
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if __ICCARM_V8
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#else
|
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED __packed
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_STRUCT
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __PACKED_UNION
|
||||
#if __ICCARM_V8
|
||||
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __RESTRICT
|
||||
#if __ICCARM_V8
|
||||
#define __RESTRICT __restrict
|
||||
#else
|
||||
/* Needs IAR language extensions */
|
||||
#define __RESTRICT restrict
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
|
||||
#ifndef __FORCEINLINE
|
||||
#define __FORCEINLINE _Pragma("inline=forced")
|
||||
#endif
|
||||
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
|
||||
#ifndef CMSIS_DEPRECATED
|
||||
#define CMSIS_DEPRECATED __attribute__((deprecated))
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint16_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
|
||||
{
|
||||
*(__packed uint16_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
|
||||
{
|
||||
return *(__packed uint32_t*)(ptr);
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
|
||||
#endif
|
||||
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#pragma language=save
|
||||
#pragma language=extended
|
||||
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
|
||||
{
|
||||
*(__packed uint32_t*)(ptr) = val;;
|
||||
}
|
||||
#pragma language=restore
|
||||
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
|
||||
#endif
|
||||
|
||||
#ifndef __USED
|
||||
#if __ICCARM_V8
|
||||
#define __USED __attribute__((used))
|
||||
#else
|
||||
#define __USED _Pragma("__root")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __WEAK
|
||||
#if __ICCARM_V8
|
||||
#define __WEAK __attribute__((weak))
|
||||
#else
|
||||
#define __WEAK _Pragma("__weak")
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __ICCARM_INTRINSICS_VERSION__
|
||||
#define __ICCARM_INTRINSICS_VERSION__ 0
|
||||
#endif
|
||||
|
||||
#if __ICCARM_INTRINSICS_VERSION__ == 2
|
||||
|
||||
#if defined(__CLZ)
|
||||
#undef __CLZ
|
||||
#endif
|
||||
#if defined(__REVSH)
|
||||
#undef __REVSH
|
||||
#endif
|
||||
#if defined(__RBIT)
|
||||
#undef __RBIT
|
||||
#endif
|
||||
#if defined(__SSAT)
|
||||
#undef __SSAT
|
||||
#endif
|
||||
#if defined(__USAT)
|
||||
#undef __USAT
|
||||
#endif
|
||||
|
||||
#include "iccarm_builtin.h"
|
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||
#define __disable_irq __iar_builtin_disable_interrupt
|
||||
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||
#define __enable_irq __iar_builtin_enable_interrupt
|
||||
#define __arm_rsr __iar_builtin_rsr
|
||||
#define __arm_wsr __iar_builtin_wsr
|
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))
|
||||
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||
#else
|
||||
#define __get_FPSCR() ( 0 )
|
||||
#define __set_FPSCR(VALUE) ((void)VALUE)
|
||||
#endif
|
||||
|
||||
#define __get_CPSR() (__arm_rsr("CPSR"))
|
||||
#define __get_mode() (__get_CPSR() & 0x1FU)
|
||||
|
||||
#define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE)))
|
||||
#define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE)))
|
||||
|
||||
|
||||
#define __get_FPEXC() (__arm_rsr("FPEXC"))
|
||||
#define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE))
|
||||
|
||||
#define __get_CP(cp, op1, RT, CRn, CRm, op2) \
|
||||
((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
|
||||
|
||||
#define __set_CP(cp, op1, RT, CRn, CRm, op2) \
|
||||
(__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
|
||||
|
||||
#define __get_CP64(cp, op1, Rt, CRm) \
|
||||
__ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
|
||||
|
||||
#define __set_CP64(cp, op1, Rt, CRm) \
|
||||
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
|
||||
|
||||
#include "cmsis_cp15.h"
|
||||
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
#define __DSB __iar_builtin_DSB
|
||||
#define __ISB __iar_builtin_ISB
|
||||
|
||||
#define __LDREXB __iar_builtin_LDREXB
|
||||
#define __LDREXH __iar_builtin_LDREXH
|
||||
#define __LDREXW __iar_builtin_LDREX
|
||||
|
||||
#define __RBIT __iar_builtin_RBIT
|
||||
#define __REV __iar_builtin_REV
|
||||
#define __REV16 __iar_builtin_REV16
|
||||
|
||||
__IAR_FT int16_t __REVSH(int16_t val)
|
||||
{
|
||||
return (int16_t) __iar_builtin_REVSH(val);
|
||||
}
|
||||
|
||||
#define __ROR __iar_builtin_ROR
|
||||
#define __RRX __iar_builtin_RRX
|
||||
|
||||
#define __SEV __iar_builtin_SEV
|
||||
|
||||
#define __SSAT __iar_builtin_SSAT
|
||||
|
||||
#define __STREXB __iar_builtin_STREXB
|
||||
#define __STREXH __iar_builtin_STREXH
|
||||
#define __STREXW __iar_builtin_STREX
|
||||
|
||||
#define __USAT __iar_builtin_USAT
|
||||
|
||||
#define __WFE __iar_builtin_WFE
|
||||
#define __WFI __iar_builtin_WFI
|
||||
|
||||
#define __SADD8 __iar_builtin_SADD8
|
||||
#define __QADD8 __iar_builtin_QADD8
|
||||
#define __SHADD8 __iar_builtin_SHADD8
|
||||
#define __UADD8 __iar_builtin_UADD8
|
||||
#define __UQADD8 __iar_builtin_UQADD8
|
||||
#define __UHADD8 __iar_builtin_UHADD8
|
||||
#define __SSUB8 __iar_builtin_SSUB8
|
||||
#define __QSUB8 __iar_builtin_QSUB8
|
||||
#define __SHSUB8 __iar_builtin_SHSUB8
|
||||
#define __USUB8 __iar_builtin_USUB8
|
||||
#define __UQSUB8 __iar_builtin_UQSUB8
|
||||
#define __UHSUB8 __iar_builtin_UHSUB8
|
||||
#define __SADD16 __iar_builtin_SADD16
|
||||
#define __QADD16 __iar_builtin_QADD16
|
||||
#define __SHADD16 __iar_builtin_SHADD16
|
||||
#define __UADD16 __iar_builtin_UADD16
|
||||
#define __UQADD16 __iar_builtin_UQADD16
|
||||
#define __UHADD16 __iar_builtin_UHADD16
|
||||
#define __SSUB16 __iar_builtin_SSUB16
|
||||
#define __QSUB16 __iar_builtin_QSUB16
|
||||
#define __SHSUB16 __iar_builtin_SHSUB16
|
||||
#define __USUB16 __iar_builtin_USUB16
|
||||
#define __UQSUB16 __iar_builtin_UQSUB16
|
||||
#define __UHSUB16 __iar_builtin_UHSUB16
|
||||
#define __SASX __iar_builtin_SASX
|
||||
#define __QASX __iar_builtin_QASX
|
||||
#define __SHASX __iar_builtin_SHASX
|
||||
#define __UASX __iar_builtin_UASX
|
||||
#define __UQASX __iar_builtin_UQASX
|
||||
#define __UHASX __iar_builtin_UHASX
|
||||
#define __SSAX __iar_builtin_SSAX
|
||||
#define __QSAX __iar_builtin_QSAX
|
||||
#define __SHSAX __iar_builtin_SHSAX
|
||||
#define __USAX __iar_builtin_USAX
|
||||
#define __UQSAX __iar_builtin_UQSAX
|
||||
#define __UHSAX __iar_builtin_UHSAX
|
||||
#define __USAD8 __iar_builtin_USAD8
|
||||
#define __USADA8 __iar_builtin_USADA8
|
||||
#define __SSAT16 __iar_builtin_SSAT16
|
||||
#define __USAT16 __iar_builtin_USAT16
|
||||
#define __UXTB16 __iar_builtin_UXTB16
|
||||
#define __UXTAB16 __iar_builtin_UXTAB16
|
||||
#define __SXTB16 __iar_builtin_SXTB16
|
||||
#define __SXTAB16 __iar_builtin_SXTAB16
|
||||
#define __SMUAD __iar_builtin_SMUAD
|
||||
#define __SMUADX __iar_builtin_SMUADX
|
||||
#define __SMMLA __iar_builtin_SMMLA
|
||||
#define __SMLAD __iar_builtin_SMLAD
|
||||
#define __SMLADX __iar_builtin_SMLADX
|
||||
#define __SMLALD __iar_builtin_SMLALD
|
||||
#define __SMLALDX __iar_builtin_SMLALDX
|
||||
#define __SMUSD __iar_builtin_SMUSD
|
||||
#define __SMUSDX __iar_builtin_SMUSDX
|
||||
#define __SMLSD __iar_builtin_SMLSD
|
||||
#define __SMLSDX __iar_builtin_SMLSDX
|
||||
#define __SMLSLD __iar_builtin_SMLSLD
|
||||
#define __SMLSLDX __iar_builtin_SMLSLDX
|
||||
#define __SEL __iar_builtin_SEL
|
||||
#define __QADD __iar_builtin_QADD
|
||||
#define __QSUB __iar_builtin_QSUB
|
||||
#define __PKHBT __iar_builtin_PKHBT
|
||||
#define __PKHTB __iar_builtin_PKHTB
|
||||
|
||||
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))
|
||||
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
|
||||
#endif
|
||||
|
||||
#ifdef __INTRINSICS_INCLUDED
|
||||
#error intrinsics.h is already included previously!
|
||||
#endif
|
||||
|
||||
#include <intrinsics.h>
|
||||
|
||||
#if !((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))
|
||||
#define __get_FPSCR() (0)
|
||||
#endif
|
||||
|
||||
#pragma diag_suppress=Pe940
|
||||
#pragma diag_suppress=Pe177
|
||||
|
||||
#define __enable_irq __enable_interrupt
|
||||
#define __disable_irq __disable_interrupt
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
#define __NOP __no_operation
|
||||
|
||||
#define __get_xPSR __get_PSR
|
||||
|
||||
__IAR_FT void __set_mode(uint32_t mode)
|
||||
{
|
||||
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
|
||||
{
|
||||
return __LDREX((unsigned long *)ptr);
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
|
||||
{
|
||||
return __STREX(value, (unsigned long *)ptr);
|
||||
}
|
||||
|
||||
|
||||
__IAR_FT uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __get_FPEXC(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))
|
||||
uint32_t result;
|
||||
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
__IAR_FT void __set_FPEXC(uint32_t fpexc)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)))
|
||||
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
|
||||
__ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
|
||||
__ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
|
||||
#define __get_CP64(cp, op1, Rt, CRm) \
|
||||
__ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
|
||||
#define __set_CP64(cp, op1, Rt, CRm) \
|
||||
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
|
||||
|
||||
#include "cmsis_cp15.h"
|
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
|
||||
|
||||
|
||||
__IAR_FT uint32_t __get_SP_usr(void)
|
||||
{
|
||||
uint32_t cpsr;
|
||||
uint32_t result;
|
||||
__ASM volatile(
|
||||
"MRS %0, cpsr \n"
|
||||
"CPS #0x1F \n" // no effect in USR mode
|
||||
"MOV %1, sp \n"
|
||||
"MSR cpsr_c, %2 \n" // no effect in USR mode
|
||||
"ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
|
||||
);
|
||||
return result;
|
||||
}
|
||||
|
||||
__IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
|
||||
{
|
||||
uint32_t cpsr;
|
||||
__ASM volatile(
|
||||
"MRS %0, cpsr \n"
|
||||
"CPS #0x1F \n" // no effect in USR mode
|
||||
"MOV sp, %1 \n"
|
||||
"MSR cpsr_c, %2 \n" // no effect in USR mode
|
||||
"ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
|
||||
);
|
||||
}
|
||||
|
||||
#define __get_mode() (__get_CPSR() & 0x1FU)
|
||||
|
||||
__STATIC_INLINE
|
||||
void __FPU_Enable(void)
|
||||
{
|
||||
__ASM volatile(
|
||||
//Permit access to VFP/NEON, registers by modifying CPACR
|
||||
" MRC p15,0,R1,c1,c0,2 \n"
|
||||
" ORR R1,R1,#0x00F00000 \n"
|
||||
" MCR p15,0,R1,c1,c0,2 \n"
|
||||
|
||||
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
|
||||
" ISB \n"
|
||||
|
||||
//Enable VFP/NEON
|
||||
" VMRS R1,FPEXC \n"
|
||||
" ORR R1,R1,#0x40000000 \n"
|
||||
" VMSR FPEXC,R1 \n"
|
||||
|
||||
//Initialise VFP/NEON registers to 0
|
||||
" MOV R2,#0 \n"
|
||||
|
||||
//Initialise D16 registers to 0
|
||||
" VMOV D0, R2,R2 \n"
|
||||
" VMOV D1, R2,R2 \n"
|
||||
" VMOV D2, R2,R2 \n"
|
||||
" VMOV D3, R2,R2 \n"
|
||||
" VMOV D4, R2,R2 \n"
|
||||
" VMOV D5, R2,R2 \n"
|
||||
" VMOV D6, R2,R2 \n"
|
||||
" VMOV D7, R2,R2 \n"
|
||||
" VMOV D8, R2,R2 \n"
|
||||
" VMOV D9, R2,R2 \n"
|
||||
" VMOV D10,R2,R2 \n"
|
||||
" VMOV D11,R2,R2 \n"
|
||||
" VMOV D12,R2,R2 \n"
|
||||
" VMOV D13,R2,R2 \n"
|
||||
" VMOV D14,R2,R2 \n"
|
||||
" VMOV D15,R2,R2 \n"
|
||||
|
||||
#ifdef __ARM_ADVANCED_SIMD__
|
||||
//Initialise D32 registers to 0
|
||||
" VMOV D16,R2,R2 \n"
|
||||
" VMOV D17,R2,R2 \n"
|
||||
" VMOV D18,R2,R2 \n"
|
||||
" VMOV D19,R2,R2 \n"
|
||||
" VMOV D20,R2,R2 \n"
|
||||
" VMOV D21,R2,R2 \n"
|
||||
" VMOV D22,R2,R2 \n"
|
||||
" VMOV D23,R2,R2 \n"
|
||||
" VMOV D24,R2,R2 \n"
|
||||
" VMOV D25,R2,R2 \n"
|
||||
" VMOV D26,R2,R2 \n"
|
||||
" VMOV D27,R2,R2 \n"
|
||||
" VMOV D28,R2,R2 \n"
|
||||
" VMOV D29,R2,R2 \n"
|
||||
" VMOV D30,R2,R2 \n"
|
||||
" VMOV D31,R2,R2 \n"
|
||||
#endif
|
||||
|
||||
//Initialise FPSCR to a known state
|
||||
" VMRS R1,FPSCR \n"
|
||||
" MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
|
||||
" AND R1,R1,R2 \n"
|
||||
" VMSR FPSCR,R1 \n"
|
||||
: : : "cc", "r1", "r2"
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
|
||||
#undef __IAR_FT
|
||||
#undef __ICCARM_V8
|
||||
|
||||
#pragma diag_default=Pe940
|
||||
#pragma diag_default=Pe177
|
||||
|
||||
#endif /* __CMSIS_ICCARM_A_H__ */
|
||||
@@ -0,0 +1,190 @@
|
||||
/*
|
||||
* Copyright (c) 2017-2020 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(A) Interrupt Controller API Header File
|
||||
*/
|
||||
|
||||
#ifndef IRQ_CTRL_H_
|
||||
#define IRQ_CTRL_H_
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifndef IRQHANDLER_T
|
||||
#define IRQHANDLER_T
|
||||
/// Interrupt handler data type
|
||||
typedef void (*IRQHandler_t) (void);
|
||||
#endif
|
||||
|
||||
#ifndef IRQN_ID_T
|
||||
#define IRQN_ID_T
|
||||
/// Interrupt ID number data type
|
||||
typedef int32_t IRQn_ID_t;
|
||||
#endif
|
||||
|
||||
/* Interrupt mode bit-masks */
|
||||
#define IRQ_MODE_TRIG_Pos (0U)
|
||||
#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
|
||||
#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
|
||||
#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
|
||||
#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
|
||||
#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
|
||||
#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
|
||||
#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
|
||||
#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
|
||||
|
||||
#define IRQ_MODE_TYPE_Pos (3U)
|
||||
#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
|
||||
#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line
|
||||
#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line
|
||||
|
||||
#define IRQ_MODE_DOMAIN_Pos (4U)
|
||||
#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
|
||||
#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain
|
||||
#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain
|
||||
|
||||
#define IRQ_MODE_CPU_Pos (5U)
|
||||
#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
|
||||
#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs
|
||||
#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0
|
||||
#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1
|
||||
#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2
|
||||
#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3
|
||||
#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4
|
||||
#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5
|
||||
#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6
|
||||
#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7
|
||||
|
||||
// Encoding in some early GIC implementations
|
||||
#define IRQ_MODE_MODEL_Pos (13U)
|
||||
#define IRQ_MODE_MODEL_Msk (0x1UL << IRQ_MODE_MODEL_Pos)
|
||||
#define IRQ_MODE_MODEL_NN (0x0UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the N-N model
|
||||
#define IRQ_MODE_MODEL_1N (0x1UL << IRQ_MODE_MODEL_Pos) ///< Corresponding interrupt is handled using the 1-N model
|
||||
|
||||
#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error
|
||||
|
||||
/* Interrupt priority bit-masks */
|
||||
#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask
|
||||
#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error
|
||||
|
||||
/// Initialize interrupt controller.
|
||||
/// \return 0 on success, -1 on error.
|
||||
int32_t IRQ_Initialize (void);
|
||||
|
||||
/// Register interrupt handler.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \param[in] handler interrupt handler function address
|
||||
/// \return 0 on success, -1 on error.
|
||||
int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
|
||||
|
||||
/// Get the registered interrupt handler.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \return registered interrupt handler function address.
|
||||
IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
|
||||
|
||||
/// Enable interrupt.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \return 0 on success, -1 on error.
|
||||
int32_t IRQ_Enable (IRQn_ID_t irqn);
|
||||
|
||||
/// Disable interrupt.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \return 0 on success, -1 on error.
|
||||
int32_t IRQ_Disable (IRQn_ID_t irqn);
|
||||
|
||||
/// Get interrupt enable state.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
|
||||
uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
|
||||
|
||||
/// Configure interrupt request mode.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \param[in] mode mode configuration
|
||||
/// \return 0 on success, -1 on error.
|
||||
int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
|
||||
|
||||
/// Get interrupt mode configuration.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
|
||||
uint32_t IRQ_GetMode (IRQn_ID_t irqn);
|
||||
|
||||
/// Get ID number of current interrupt request (IRQ).
|
||||
/// \return interrupt ID number.
|
||||
IRQn_ID_t IRQ_GetActiveIRQ (void);
|
||||
|
||||
/// Get ID number of current fast interrupt request (FIQ).
|
||||
/// \return interrupt ID number.
|
||||
IRQn_ID_t IRQ_GetActiveFIQ (void);
|
||||
|
||||
/// Signal end of interrupt processing.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \return 0 on success, -1 on error.
|
||||
int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
|
||||
|
||||
/// Set interrupt pending flag.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \return 0 on success, -1 on error.
|
||||
int32_t IRQ_SetPending (IRQn_ID_t irqn);
|
||||
|
||||
/// Get interrupt pending flag.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \return 0 - interrupt is not pending, 1 - interrupt is pending.
|
||||
uint32_t IRQ_GetPending (IRQn_ID_t irqn);
|
||||
|
||||
/// Clear interrupt pending flag.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \return 0 on success, -1 on error.
|
||||
int32_t IRQ_ClearPending (IRQn_ID_t irqn);
|
||||
|
||||
/// Set interrupt priority value.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \param[in] priority interrupt priority value
|
||||
/// \return 0 on success, -1 on error.
|
||||
int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
|
||||
|
||||
/// Get interrupt priority.
|
||||
/// \param[in] irqn interrupt ID number
|
||||
/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
|
||||
uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
|
||||
|
||||
/// Set priority masking threshold.
|
||||
/// \param[in] priority priority masking threshold value
|
||||
/// \return 0 on success, -1 on error.
|
||||
int32_t IRQ_SetPriorityMask (uint32_t priority);
|
||||
|
||||
/// Get priority masking threshold
|
||||
/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
|
||||
uint32_t IRQ_GetPriorityMask (void);
|
||||
|
||||
/// Set priority grouping field split point
|
||||
/// \param[in] bits number of MSB bits included in the group priority field comparison
|
||||
/// \return 0 on success, -1 on error.
|
||||
int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
|
||||
|
||||
/// Get priority grouping field split point
|
||||
/// \return current number of MSB bits included in the group priority field comparison with
|
||||
/// optional IRQ_PRIORITY_ERROR bit set.
|
||||
uint32_t IRQ_GetPriorityGroupBits (void);
|
||||
|
||||
#endif // IRQ_CTRL_H_
|
||||
@@ -1,894 +0,0 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.4.0
|
||||
* @date 20. January 2023
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
|
||||
|
||||
/* CMSIS compiler control DSP macros */
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __ARM_FEATURE_DSP 1
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __memory_changed()
|
||||
#endif
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__ ((section (".bss.noinit"), zero_init))
|
||||
#endif
|
||||
#ifndef __ALIAS
|
||||
#define __ALIAS(x) __attribute__ ((alias(x)))
|
||||
#endif
|
||||
|
||||
/* ######################### Startup and Lowlevel Init ######################## */
|
||||
|
||||
#ifndef __PROGRAM_START
|
||||
#define __PROGRAM_START __main
|
||||
#endif
|
||||
|
||||
#ifndef __INITIAL_SP
|
||||
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||
#endif
|
||||
|
||||
#ifndef __STACK_LIMIT
|
||||
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE
|
||||
#define __VECTOR_TABLE __Vectors
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
|
||||
#endif
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
__ISB();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
@@ -1,9 +1,3 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.3.0
|
||||
* @date 04. April 2023
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
@@ -22,48 +16,87 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS Compiler Generic Header File
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#if __ARM_ARCH_PROFILE == 'A'
|
||||
#include "./a-profile/cmsis_armclang_a.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'R'
|
||||
#include "./r-profile/cmsis_armclang_r.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'M'
|
||||
#include "./m-profile/cmsis_armclang_m.h"
|
||||
#else
|
||||
#error "Unknown Arm architecture profile"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* TI Arm Clang Compiler (tiarmclang)
|
||||
*/
|
||||
#elif defined (__ti__)
|
||||
#include "cmsis_tiarmclang.h"
|
||||
#if __ARM_ARCH_PROFILE == 'A'
|
||||
#error "Core-A is not supported for this compiler"
|
||||
#elif __ARM_ARCH_PROFILE == 'R'
|
||||
#error "Core-R is not supported for this compiler"
|
||||
#elif __ARM_ARCH_PROFILE == 'M'
|
||||
#include "m-profile/cmsis_tiarmclang_m.h"
|
||||
#else
|
||||
#error "Unknown Arm architecture profile"
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* LLVM/Clang Compiler
|
||||
*/
|
||||
#elif defined ( __clang__ )
|
||||
#if __ARM_ARCH_PROFILE == 'A'
|
||||
#include "a-profile/cmsis_clang_a.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'R'
|
||||
#include "r-profile/cmsis_clang_r.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'M'
|
||||
#include "m-profile/cmsis_clang_m.h"
|
||||
#else
|
||||
#error "Unknown Arm architecture profile"
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
#if __ARM_ARCH_PROFILE == 'A'
|
||||
#include "a-profile/cmsis_gcc_a.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'R'
|
||||
#include "r-profile/cmsis_gcc_r.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'M'
|
||||
#include "m-profile/cmsis_gcc_m.h"
|
||||
#else
|
||||
#error "Unknown Arm architecture profile"
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
#if __ARM_ARCH_PROFILE == 'A'
|
||||
#include "a-profile/cmsis_iccarm_a.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'R'
|
||||
#include "r-profile/cmsis_iccarm_r.h"
|
||||
#elif __ARM_ARCH_PROFILE == 'M'
|
||||
#include "m-profile/cmsis_iccarm_m.h"
|
||||
#else
|
||||
#error "Unknown Arm architecture profile"
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
@@ -102,10 +135,6 @@
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
@@ -133,7 +162,7 @@
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__ ((section (".bss.noinit")))
|
||||
#define __NO_INIT __attribute__ ((section (".noinit")))
|
||||
#endif
|
||||
#ifndef __ALIAS
|
||||
#define __ALIAS(x) __attribute__ ((alias(x)))
|
||||
@@ -179,10 +208,6 @@
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
@@ -200,7 +225,7 @@
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
@@ -211,7 +236,7 @@
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__ ((section (".bss.noinit")))
|
||||
#define __NO_INIT __attribute__ ((section (".noinit")))
|
||||
#endif
|
||||
#ifndef __ALIAS
|
||||
#define __ALIAS(x) __attribute__ ((alias(x)))
|
||||
@@ -255,10 +280,6 @@
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
@@ -288,7 +309,7 @@
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
#ifndef __NO_INIT
|
||||
#define __NO_INIT __attribute__ ((section (".bss.noinit")))
|
||||
#define __NO_INIT __attribute__ ((section (".noinit")))
|
||||
#endif
|
||||
#ifndef __ALIAS
|
||||
#define __ALIAS(x) __attribute__ ((alias(x)))
|
||||
|
||||
@@ -1,11 +1,5 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.5
|
||||
* @date 02. February 2022
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
|
||||
* Copyright (c) 2009-2023 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -22,6 +16,10 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS Core Version Definitions
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
@@ -31,9 +29,16 @@
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
/* CMSIS-Core(M) Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< \brief [15:0] CMSIS-Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< \brief CMSIS Core(M) version number */
|
||||
|
||||
/* CMSIS-Core(A) Version definitions */
|
||||
#define __CA_CMSIS_VERSION_MAIN ( 6U) /*!< \brief [31:16] CMSIS-Core(A) main version */
|
||||
#define __CA_CMSIS_VERSION_SUB ( 0U) /*!< \brief [15:0] CMSIS-Core(A) sub version */
|
||||
#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CA_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */
|
||||
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,9 +1,3 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V5.1.0
|
||||
* @date 04. April 2023
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
@@ -22,10 +16,16 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
@@ -61,14 +61,10 @@
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
/* CMSIS CM0 definitions */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
@@ -76,17 +72,17 @@
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#if defined (__TARGET_FPU_VFP)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#if defined (__ARM_FP)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ti__)
|
||||
#if defined __ARM_FP
|
||||
#if defined (__ARM_FP)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
@@ -96,17 +92,17 @@
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#if defined (__ARMVFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#if defined (__TI_VFP_SUPPORT__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#if defined (__FPU_VFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
@@ -214,7 +210,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
/** \brief APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
@@ -241,7 +237,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
/** \brief IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
@@ -265,7 +261,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
/** \brief xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
@@ -299,7 +295,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
/** \brief CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
@@ -327,7 +323,7 @@ typedef struct
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
__IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
@@ -352,11 +348,11 @@ typedef struct
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
/** \brief SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
@@ -372,7 +368,7 @@ typedef struct
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
/** \brief SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
@@ -400,7 +396,7 @@ typedef struct
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
/** \brief SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
@@ -416,7 +412,7 @@ typedef struct
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
/** \brief SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
@@ -426,14 +422,14 @@ typedef struct
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
/** \brief SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
/** \brief SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
@@ -458,7 +454,7 @@ typedef struct
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
/** \brief SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
@@ -471,15 +467,15 @@ typedef struct
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
/** \brief SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
/** \brief SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
/** \brief SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
@@ -549,6 +545,15 @@ typedef struct
|
||||
/*@} */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
|
||||
\brief Register alias definitions for backwards compatibility.
|
||||
@{
|
||||
*/
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
@@ -585,7 +590,7 @@ typedef struct
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
/* NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
@@ -738,12 +743,12 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
@@ -763,11 +768,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
@@ -824,7 +829,6 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
|
||||
@@ -1,9 +1,3 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0plus.h
|
||||
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
||||
* @version V5.1.0
|
||||
* @date 04. April 2023
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
@@ -22,10 +16,16 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_GENERIC
|
||||
@@ -61,14 +61,10 @@
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0+ definitions */
|
||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
/* CMSIS CM0+ definitions */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
@@ -76,17 +72,17 @@
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#if defined (__TARGET_FPU_VFP)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#if defined (__ARM_FP)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ti__)
|
||||
#if defined __ARM_FP
|
||||
#if defined (__ARM_FP)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
@@ -96,17 +92,17 @@
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#if defined (__ARMVFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#if defined (__TI_VFP_SUPPORT__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#if defined (__FPU_VFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
@@ -225,7 +221,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
/** \brief APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
@@ -252,7 +248,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
/** \brief IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
@@ -276,7 +272,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
/** \brief xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
@@ -310,7 +306,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
/** \brief CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
@@ -341,7 +337,7 @@ typedef struct
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
__IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
@@ -370,11 +366,11 @@ typedef struct
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
/** \brief SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
@@ -390,7 +386,7 @@ typedef struct
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
/** \brief SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
@@ -419,12 +415,12 @@ typedef struct
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
/** \brief SCB Vector Table Offset Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
#endif
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
/** \brief SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
@@ -440,7 +436,7 @@ typedef struct
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
/** \brief SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
@@ -450,14 +446,14 @@ typedef struct
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
/** \brief SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
/** \brief SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
@@ -482,7 +478,7 @@ typedef struct
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
/** \brief SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
@@ -495,15 +491,15 @@ typedef struct
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
/** \brief SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
/** \brief SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
/** \brief SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
@@ -530,14 +526,14 @@ typedef struct
|
||||
{
|
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
|
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||
} MPU_Type;
|
||||
|
||||
#define MPU_TYPE_RALIASES 1U
|
||||
|
||||
/* MPU Type Register Definitions */
|
||||
/** \brief MPU Type Register Definitions */
|
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||
|
||||
@@ -547,7 +543,7 @@ typedef struct
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
||||
|
||||
/* MPU Control Register Definitions */
|
||||
/** \brief MPU Control Register Definitions */
|
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||
|
||||
@@ -557,11 +553,11 @@ typedef struct
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
||||
|
||||
/* MPU Region Number Register Definitions */
|
||||
/** \brief MPU Region Number Register Definitions */
|
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
||||
|
||||
/* MPU Region Base Address Register Definitions */
|
||||
/** \brief MPU Region Base Address Register Definitions */
|
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
|
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||
|
||||
@@ -571,7 +567,7 @@ typedef struct
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */
|
||||
/** \brief MPU Region Attribute and Size Register Definitions */
|
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||
|
||||
@@ -667,6 +663,15 @@ typedef struct
|
||||
/*@} */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
|
||||
\brief Register alias definitions for backwards compatibility.
|
||||
@{
|
||||
*/
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
@@ -703,7 +708,7 @@ typedef struct
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */
|
||||
/* NVIC_GetActive not available for Cortex-M0+ */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
@@ -856,12 +861,12 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
@@ -881,11 +886,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
@@ -955,7 +960,7 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||
uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
#else
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
@@ -976,7 +981,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||
uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
#else
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
@@ -1009,7 +1014,7 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
|
||||
#include "mpu_armv7.h"
|
||||
#include "m-profile/armv7m_mpu.h"
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -1,9 +1,3 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm1.h
|
||||
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||
* @version V1.1.0
|
||||
* @date 04. April 2023
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
@@ -22,10 +16,16 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS Cortex-M1 Core Peripheral Access Layer Header File
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM1_H_GENERIC
|
||||
@@ -61,14 +61,10 @@
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM1 definitions */
|
||||
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||
/* CMSIS CM1 definitions */
|
||||
|
||||
#define __CORTEX_M (1U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
@@ -76,17 +72,17 @@
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#if defined (__TARGET_FPU_VFP)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#if defined (__ARM_FP)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ti__)
|
||||
#if defined __ARM_FP
|
||||
#if defined (__ARM_FP)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
@@ -96,17 +92,17 @@
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#if defined (__ARMVFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#if defined (__TI_VFP_SUPPORT__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#if defined (__FPU_VFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
@@ -214,7 +210,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
/** \brief APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
@@ -241,7 +237,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
/** \brief IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
@@ -265,7 +261,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
/** \brief xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
@@ -299,7 +295,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
/** \brief CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
@@ -321,13 +317,13 @@ typedef struct
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
uint32_t RESERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
__IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
@@ -352,11 +348,11 @@ typedef struct
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
/** \brief SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
@@ -372,7 +368,7 @@ typedef struct
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
/** \brief SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
@@ -400,7 +396,7 @@ typedef struct
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
/** \brief SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
@@ -416,7 +412,7 @@ typedef struct
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
/** \brief SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
@@ -426,14 +422,14 @@ typedef struct
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
/** \brief SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
/** \brief SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
@@ -456,7 +452,7 @@ typedef struct
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
/** \brief SCnSCB Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
|
||||
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
|
||||
|
||||
@@ -484,7 +480,7 @@ typedef struct
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
/** \brief SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
@@ -497,15 +493,15 @@ typedef struct
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
/** \brief SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
/** \brief SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
/** \brief SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
@@ -576,6 +572,15 @@ typedef struct
|
||||
/*@} */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
|
||||
\brief Register alias definitions for backwards compatibility.
|
||||
@{
|
||||
*/
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
@@ -765,12 +770,12 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
@@ -790,11 +795,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
@@ -851,7 +856,6 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
@@ -926,11 +930,9 @@ __STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
|
||||
+207
-365
File diff suppressed because it is too large
Load Diff
+262
-295
File diff suppressed because it is too large
Load Diff
+321
-509
File diff suppressed because it is too large
Load Diff
+320
-508
File diff suppressed because it is too large
Load Diff
+299
-333
File diff suppressed because it is too large
Load Diff
+481
-668
File diff suppressed because it is too large
Load Diff
+307
-347
File diff suppressed because it is too large
Load Diff
+592
-604
File diff suppressed because it is too large
Load Diff
@@ -1,9 +1,3 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_sc000.h
|
||||
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
|
||||
* @version V5.1.0
|
||||
* @date 04. April 2023
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
@@ -22,10 +16,16 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS SC000 Core Peripheral Access Layer Header File
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_SC000_H_GENERIC
|
||||
@@ -63,12 +63,8 @@
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS SC000 definitions */
|
||||
#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_SC (000U) /*!< Cortex secure core */
|
||||
#define __CORTEX_SC (000U) /*!< Cortex Secure Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
@@ -76,12 +72,12 @@
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#if defined (__TARGET_FPU_VFP)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#if defined (__ARM_FP)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
@@ -96,17 +92,17 @@
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#if defined (__ARMVFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#if defined (__TI_VFP_SUPPORT__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#if defined (__FPU_VFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
@@ -148,10 +144,10 @@
|
||||
#endif
|
||||
|
||||
#ifndef __VTOR_PRESENT
|
||||
#define __VTOR_PRESENT 0U
|
||||
#define __VTOR_PRESENT 0U
|
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
@@ -225,7 +221,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
/** \brief APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
@@ -252,7 +248,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
/** \brief IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
@@ -276,7 +272,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
/** \brief xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
@@ -310,7 +306,7 @@ typedef union
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
/** \brief CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
@@ -332,13 +328,13 @@ typedef struct
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
uint32_t RESERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
__IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
@@ -363,13 +359,13 @@ typedef struct
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED0[1U];
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
uint32_t RESERVED1[154U];
|
||||
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
/** \brief SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
@@ -385,7 +381,7 @@ typedef struct
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
/** \brief SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
@@ -413,11 +409,11 @@ typedef struct
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
/** \brief SCB Vector Table Offset Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
/** \brief SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
@@ -433,7 +429,7 @@ typedef struct
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
/** \brief SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
@@ -443,14 +439,14 @@ typedef struct
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
/** \brief SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
/** \brief SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
@@ -473,7 +469,7 @@ typedef struct
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
/** \brief SCnSCB Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
|
||||
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
|
||||
|
||||
@@ -498,7 +494,7 @@ typedef struct
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
/** \brief SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
@@ -511,15 +507,15 @@ typedef struct
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
/** \brief SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
/** \brief SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
/** \brief SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
@@ -546,12 +542,14 @@ typedef struct
|
||||
{
|
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
|
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||
} MPU_Type;
|
||||
|
||||
/* MPU Type Register Definitions */
|
||||
#define MPU_TYPE_RALIASES 1U
|
||||
|
||||
/** \brief MPU Type Register Definitions */
|
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||
|
||||
@@ -561,7 +559,7 @@ typedef struct
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
||||
|
||||
/* MPU Control Register Definitions */
|
||||
/** \brief MPU Control Register Definitions */
|
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||
|
||||
@@ -571,11 +569,11 @@ typedef struct
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
||||
|
||||
/* MPU Region Number Register Definitions */
|
||||
/** \brief MPU Region Number Register Definitions */
|
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
||||
|
||||
/* MPU Region Base Address Register Definitions */
|
||||
/** \brief MPU Region Base Address Register Definitions */
|
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
|
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||
|
||||
@@ -585,7 +583,7 @@ typedef struct
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */
|
||||
/** \brief MPU Region Attribute and Size Register Definitions */
|
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||
|
||||
@@ -682,6 +680,15 @@ typedef struct
|
||||
/*@} */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_register_aliases Backwards Compatibility Aliases
|
||||
\brief Register alias definitions for backwards compatibility.
|
||||
@{
|
||||
*/
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
@@ -869,12 +876,12 @@ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
@@ -894,11 +901,11 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
@@ -914,7 +921,7 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||
uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
|
||||
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||
/* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */
|
||||
}
|
||||
@@ -930,7 +937,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||
uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
|
||||
@@ -955,6 +962,13 @@ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
/* ########################## MPU functions #################################### */
|
||||
|
||||
#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
|
||||
|
||||
#include "m-profile/armv7m_mpu.h"
|
||||
|
||||
#endif
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
|
||||
+269
-293
File diff suppressed because it is too large
Load Diff
+323
-331
File diff suppressed because it is too large
Load Diff
@@ -1,9 +1,3 @@
|
||||
/******************************************************************************
|
||||
* @file cachel1_armv7.h
|
||||
* @brief CMSIS Level 1 Cache API for Armv7-M and later
|
||||
* @version V1.0.3
|
||||
* @date 17. March 2023
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
@@ -22,15 +16,19 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) Level 1 Cache API for Armv7-M and later
|
||||
*/
|
||||
|
||||
#ifndef ARM_ARMV7M_CACHEL1_H
|
||||
#define ARM_ARMV7M_CACHEL1_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_CACHEL1_ARMV7_H
|
||||
#define ARM_CACHEL1_ARMV7_H
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_CacheFunctions Cache Functions
|
||||
@@ -438,4 +436,4 @@ __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr
|
||||
|
||||
/*@} end of CMSIS_Core_CacheFunctions */
|
||||
|
||||
#endif /* ARM_CACHEL1_ARMV7_H */
|
||||
#endif /* ARM_ARMV7M_CACHEL1_H */
|
||||
@@ -1,9 +1,3 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.2
|
||||
* @date 25. May 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
@@ -21,15 +15,19 @@
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) MPU API for Armv7-M MPU
|
||||
*/
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
@@ -79,12 +77,12 @@
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
@@ -93,7 +91,7 @@
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
@@ -110,7 +108,7 @@
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
@@ -119,7 +117,7 @@
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
@@ -129,7 +127,7 @@
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
@@ -140,7 +138,7 @@
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
@@ -153,7 +151,7 @@
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
@@ -184,7 +182,7 @@ typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
@@ -224,7 +222,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
@@ -235,7 +233,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
@@ -251,7 +249,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t r
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
@@ -261,7 +259,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
@@ -1,9 +1,3 @@
|
||||
/******************************************************************************
|
||||
* @file pac_armv81.h
|
||||
* @brief CMSIS PAC key functions for Armv8.1-M PAC extension
|
||||
* @version V1.0.0
|
||||
* @date 23. March 2022
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2022 Arm Limited. All rights reserved.
|
||||
*
|
||||
@@ -22,16 +16,19 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) PAC key functions for Armv8.1-M PAC extension
|
||||
*/
|
||||
|
||||
#ifndef PAC_ARMV81_H
|
||||
#define PAC_ARMV81_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef PAC_ARMV81_H
|
||||
#define PAC_ARMV81_H
|
||||
|
||||
|
||||
/* ################### PAC Key functions ########################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
@@ -1,9 +1,3 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.9.0
|
||||
* @date 11. April 2023
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2022 Arm Limited. All rights reserved.
|
||||
*
|
||||
@@ -22,15 +16,19 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) MPU API for Armv8-M and Armv8.1-M MPU
|
||||
*/
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
@@ -95,7 +93,7 @@
|
||||
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||
|
||||
/* \brief Specifies MAIR_ATTR number */
|
||||
#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x)
|
||||
#define MAIR_ATTR(x) ((x > 7 || x < 0) ? 0 : x)
|
||||
|
||||
/**
|
||||
* Shareability
|
||||
@@ -164,7 +162,7 @@
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
@@ -175,7 +173,7 @@
|
||||
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
@@ -194,7 +192,7 @@ __STATIC_INLINE uint32_t ARM_MPU_TYPE()
|
||||
{
|
||||
return ((MPU->TYPE) >> 8);
|
||||
}
|
||||
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
@@ -261,11 +259,11 @@ __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t at
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
@@ -312,7 +310,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
@@ -322,7 +320,7 @@ __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
@@ -334,7 +332,7 @@ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t r
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
@@ -345,10 +343,10 @@ __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rla
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -360,7 +358,7 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
@@ -372,7 +370,7 @@ __STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
@@ -381,7 +379,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
@@ -392,7 +390,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
@@ -402,7 +400,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
@@ -413,7 +411,7 @@ __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, u
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
@@ -1,9 +1,3 @@
|
||||
/******************************************************************************
|
||||
* @file pmu_armv8.h
|
||||
* @brief CMSIS PMU API for Armv8.1-M PMU
|
||||
* @version V1.0.1
|
||||
* @date 15. April 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
@@ -22,15 +16,19 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS-Core(M) PMU API for Armv8.1-M PMU
|
||||
*/
|
||||
|
||||
#ifndef ARM_PMU_ARMV8_H
|
||||
#define ARM_PMU_ARMV8_H
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_PMU_ARMV8_H
|
||||
#define ARM_PMU_ARMV8_H
|
||||
|
||||
/**
|
||||
* \brief PMU Events
|
||||
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
|
||||
@@ -192,23 +190,23 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||
|
||||
/**
|
||||
/**
|
||||
\brief Enable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
\brief Disable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||
{
|
||||
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
\brief Set event to count for PMU eventer counter
|
||||
\param [in] num Event counter (0-30) to configure
|
||||
\param [in] type Event to count
|
||||
@@ -218,7 +216,7 @@ __STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
|
||||
PMU->EVTYPER[num] = type;
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
\brief Reset cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||
@@ -226,7 +224,7 @@ __STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
\brief Reset all event counters
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||
@@ -234,8 +232,8 @@ __STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counters
|
||||
/**
|
||||
\brief Enable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Enables one or more of the following:
|
||||
- event counters (0-30)
|
||||
@@ -246,7 +244,7 @@ __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
|
||||
PMU->CNTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
\brief Disable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Disables one or more of the following:
|
||||
@@ -258,7 +256,7 @@ __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
|
||||
PMU->CNTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
\brief Read cycle counter
|
||||
\return Cycle count
|
||||
*/
|
||||
@@ -267,7 +265,7 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
|
||||
return PMU->CCNTR;
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
\brief Read event counter
|
||||
\param [in] num Event counter (0-30) to read
|
||||
\return Event count
|
||||
@@ -277,7 +275,7 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
\brief Read counter overflow status
|
||||
\return Counter overflow status bits for the following:
|
||||
- event counters (0-30)
|
||||
@@ -285,10 +283,10 @@ __STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
|
||||
{
|
||||
return PMU->OVSSET;
|
||||
return PMU->OVSSET;
|
||||
}
|
||||
|
||||
/**
|
||||
/**
|
||||
\brief Clear counter overflow status
|
||||
\param [in] mask Counter overflow status bits to clear
|
||||
\note Clears overflow status bits for one or more of the following:
|
||||
@@ -300,8 +298,8 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
|
||||
PMU->OVSCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counter overflow interrupt request
|
||||
/**
|
||||
\brief Enable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to set
|
||||
\note Sets overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
@@ -312,8 +310,8 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
|
||||
PMU->INTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counter overflow interrupt request
|
||||
/**
|
||||
\brief Disable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to clear
|
||||
\note Clears overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
@@ -324,8 +322,8 @@ __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
|
||||
PMU->INTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Software increment event counter
|
||||
/**
|
||||
\brief Software increment event counter
|
||||
\param [in] mask Counters to increment
|
||||
\note Software increment bits for one or more event counters (0-30)
|
||||
*/
|
||||
+316
-362
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
+534
-780
File diff suppressed because it is too large
Load Diff
@@ -1,33 +1,28 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_iccarm.h
|
||||
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
|
||||
* @version V5.4.0
|
||||
* @date 20. January 2023
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2021 IAR Systems
|
||||
* Copyright (c) 2017-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright (c) 2017-2021 IAR Systems
|
||||
// Copyright (c) 2017-2023 Arm Limited. All rights reserved.
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License")
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//
|
||||
//------------------------------------------------------------------------------
|
||||
/*
|
||||
* CMSIS-Core(M) Compiler ICCARM (IAR Compiler for Arm) Header File
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __CMSIS_ICCARM_H__
|
||||
#define __CMSIS_ICCARM_H__
|
||||
#ifndef __CMSIS_ICCARM_M_H__
|
||||
#define __CMSIS_ICCARM_M_H__
|
||||
|
||||
#ifndef __ICCARM__
|
||||
#error This file should only be compiled by ICCARM
|
||||
@@ -58,7 +53,7 @@
|
||||
|
||||
/* Define compiler macros for CPU architecture, used in CMSIS 5.
|
||||
*/
|
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
|
||||
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ || __ARM_ARCH_8_1M_MAIN__
|
||||
/* Macros already defined */
|
||||
#else
|
||||
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
|
||||
@@ -74,6 +69,8 @@
|
||||
#else
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
#elif __ARM_ARCH == 801
|
||||
#define __ARM_ARCH_8_1M_MAIN__ 1
|
||||
#endif /* __ARM_ARCH */
|
||||
#endif /* __ARM_ARCH_PROFILE == 'M' */
|
||||
#endif
|
||||
@@ -128,8 +125,10 @@
|
||||
#endif
|
||||
|
||||
#ifndef __NO_RETURN
|
||||
#if __ICCARM_V8
|
||||
#define __NO_RETURN __attribute__((__noreturn__))
|
||||
#if defined(__cplusplus) && __cplusplus >= 201103L
|
||||
#define __NO_RETURN [[noreturn]]
|
||||
#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
|
||||
#define __NO_RETURN _Noreturn
|
||||
#else
|
||||
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
|
||||
#endif
|
||||
@@ -315,21 +314,31 @@ __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
|
||||
|
||||
#include "iccarm_builtin.h"
|
||||
|
||||
#define __disable_fault_irq __iar_builtin_disable_fiq
|
||||
#define __disable_irq __iar_builtin_disable_interrupt
|
||||
#define __enable_fault_irq __iar_builtin_enable_fiq
|
||||
#define __enable_irq __iar_builtin_enable_interrupt
|
||||
#define __arm_rsr __iar_builtin_rsr
|
||||
#define __arm_wsr __iar_builtin_wsr
|
||||
|
||||
|
||||
#if (defined(__ARM_ARCH_ISA_THUMB) && __ARM_ARCH_ISA_THUMB >= 2)
|
||||
__IAR_FT void __disable_fault_irq()
|
||||
{
|
||||
__ASM volatile ("CPSID F" ::: "memory");
|
||||
}
|
||||
|
||||
__IAR_FT void __enable_fault_irq()
|
||||
{
|
||||
__ASM volatile ("CPSIE F" ::: "memory");
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#define __get_APSR() (__arm_rsr("APSR"))
|
||||
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
|
||||
#define __get_CONTROL() (__arm_rsr("CONTROL"))
|
||||
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
|
||||
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
#if (defined (__ARM_FP) && (__ARM_FP >= 1))
|
||||
#define __get_FPSCR() (__arm_rsr("FPSCR"))
|
||||
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
|
||||
#else
|
||||
@@ -340,6 +349,7 @@ __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
|
||||
#define __get_IPSR() (__arm_rsr("IPSR"))
|
||||
#define __get_MSP() (__arm_rsr("MSP"))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __get_MSPLIM() (0U)
|
||||
@@ -350,6 +360,7 @@ __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
|
||||
#define __get_PSP() (__arm_rsr("PSP"))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __get_PSPLIM() (0U)
|
||||
@@ -372,6 +383,7 @@ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
|
||||
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
#define __set_MSPLIM(VALUE) ((void)(VALUE))
|
||||
@@ -381,6 +393,7 @@ __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
|
||||
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
|
||||
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __set_PSPLIM(VALUE) ((void)(VALUE))
|
||||
@@ -410,6 +423,7 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
#define __TZ_get_PSPLIM_NS() (0U)
|
||||
@@ -425,7 +439,13 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
#define __NOP __iar_builtin_no_operation
|
||||
|
||||
#define __CLZ __iar_builtin_CLZ
|
||||
#define __CLREX __iar_builtin_CLREX
|
||||
|
||||
/*
|
||||
* __iar_builtin_CLREX can be reordered w.r.t. STREX during high optimizations.
|
||||
* As a workaround we use inline assembly and a memory barrier.
|
||||
* (IAR issue EWARM-11901)
|
||||
*/
|
||||
#define __CLREX() (__ASM volatile ("CLREX" ::: "memory"))
|
||||
|
||||
#define __DMB __iar_builtin_DMB
|
||||
#define __DSB __iar_builtin_DSB
|
||||
@@ -598,8 +618,7 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
|
||||
#endif
|
||||
|
||||
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
|
||||
#if !((defined (__ARM_FP) && (__ARM_FP >= 1))
|
||||
#undef __get_FPSCR
|
||||
#undef __set_FPSCR
|
||||
#define __get_FPSCR() (0)
|
||||
@@ -644,9 +663,15 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
|
||||
}
|
||||
|
||||
__IAR_FT void __disable_fault_irq()
|
||||
{
|
||||
__ASM volatile ("CPSID F" ::: "memory");
|
||||
}
|
||||
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
__IAR_FT void __enable_fault_irq()
|
||||
{
|
||||
__ASM volatile ("CPSIE F" ::: "memory");
|
||||
}
|
||||
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
@@ -657,14 +682,16 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
}
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
__IAR_FT uint32_t __get_MSPLIM(void)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
// without main extension and secure, there is no stack limit check.
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
|
||||
@@ -675,8 +702,9 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
__IAR_FT void __set_MSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
// without main extensions and secure, there is no stack limit check.
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
|
||||
@@ -687,8 +715,9 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
// without main extensions and secure, there is no stack limit check.
|
||||
res = 0U;
|
||||
#else
|
||||
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
|
||||
@@ -699,8 +728,9 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
__IAR_FT void __set_PSPLIM(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
// without main extensions and secure, there is no stack limit check.
|
||||
(void)value;
|
||||
#else
|
||||
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
|
||||
@@ -795,6 +825,7 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
{
|
||||
uint32_t res;
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
res = 0U;
|
||||
@@ -807,6 +838,7 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
|
||||
{
|
||||
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
(void)value;
|
||||
@@ -827,7 +859,7 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
|
||||
}
|
||||
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
|
||||
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ or __ARM_ARCH_8_1M_MAIN__ */
|
||||
|
||||
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
|
||||
|
||||
@@ -910,7 +942,8 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
|
||||
@@ -974,21 +1007,21 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
__ASM volatile ("STLEXB %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
__ASM volatile ("STLEXH %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
||||
{
|
||||
uint32_t res;
|
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
__ASM volatile ("STLEX %0, %2, [%1]" : "=&r" (res) : "r" (ptr), "r" (value) : "memory");
|
||||
return res;
|
||||
}
|
||||
|
||||
@@ -1005,4 +1038,4 @@ __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
|
||||
|
||||
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
|
||||
|
||||
#endif /* __CMSIS_ICCARM_H__ */
|
||||
#endif /* __CMSIS_ICCARM_M_H__ */
|
||||
+293
-352
File diff suppressed because it is too large
Load Diff
@@ -1,11 +1,5 @@
|
||||
/******************************************************************************
|
||||
* @file tz_context.h
|
||||
* @brief Context Management for Armv8-M TrustZone
|
||||
* @version V1.0.1
|
||||
* @date 10. January 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
|
||||
* Copyright (c) 2017-2023 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
@@ -22,6 +16,10 @@
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* CMSIS Core(M) Context Management for Armv8-M TrustZone
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
@@ -30,41 +28,41 @@
|
||||
|
||||
#ifndef TZ_CONTEXT_H
|
||||
#define TZ_CONTEXT_H
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
#ifndef TZ_MODULEID_T
|
||||
#define TZ_MODULEID_T
|
||||
/// \details Data type that identifies secure software modules called by a process.
|
||||
typedef uint32_t TZ_ModuleId_t;
|
||||
#endif
|
||||
|
||||
|
||||
/// \details TZ Memory ID identifies an allocated memory slot.
|
||||
typedef uint32_t TZ_MemoryId_t;
|
||||
|
||||
|
||||
/// Initialize secure context memory system
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
|
||||
/// Allocate context memory for calling secure software modules in TrustZone
|
||||
/// \param[in] module identifies software modules called from non-secure mode
|
||||
/// \return value != 0 id TrustZone memory slot identifier
|
||||
/// \return value 0 no memory available or internal error
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
|
||||
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
|
||||
/// Load secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
|
||||
/// Store secure context (called on RTOS thread context switch)
|
||||
/// \param[in] id TrustZone memory slot identifier
|
||||
/// \return execution status (1: success, 0: error)
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
|
||||
#endif // TZ_CONTEXT_H
|
||||
|
||||
@@ -1,318 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "dsp/fast_math_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Double Precision Float CFFT twiddles */
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_16[32];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_32[64];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_64[128];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_128[256];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_256[512];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_512[1024];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_1024[2048];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_2048[4096];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_4096[8192];
|
||||
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
|
||||
/* Q31 */
|
||||
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
|
||||
/* Double Precision Float RFFT twiddles */
|
||||
extern const uint64_t twiddleCoefF64_rfft_32[32];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_rfft_64[64];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_rfft_128[128];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_rfft_256[256];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_rfft_512[512];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_rfft_1024[1024];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_rfft_2048[2048];
|
||||
|
||||
extern const uint64_t twiddleCoefF64_rfft_4096[4096];
|
||||
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
|
||||
/* Double precision floating-point bit reversal tables */
|
||||
|
||||
#define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12)
|
||||
extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24)
|
||||
extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112)
|
||||
extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240)
|
||||
extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480)
|
||||
extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH];
|
||||
/* floating-point bit reversal tables */
|
||||
|
||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
|
||||
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
|
||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
|
||||
extern const float32_t realCoefA[8192];
|
||||
extern const float32_t realCoefB[8192];
|
||||
|
||||
extern const q31_t realCoefAQ31[8192];
|
||||
extern const q31_t realCoefBQ31[8192];
|
||||
|
||||
extern const q15_t realCoefAQ15[8192];
|
||||
extern const q15_t realCoefBQ15[8192];
|
||||
|
||||
extern const float32_t Weights_128[256];
|
||||
extern const float32_t cos_factors_128[128];
|
||||
|
||||
extern const float32_t Weights_512[1024];
|
||||
extern const float32_t cos_factors_512[512];
|
||||
|
||||
extern const float32_t Weights_2048[4096];
|
||||
extern const float32_t cos_factors_2048[2048];
|
||||
|
||||
extern const float32_t Weights_8192[16384];
|
||||
extern const float32_t cos_factors_8192[8192];
|
||||
|
||||
extern const q15_t WeightsQ15_128[256];
|
||||
extern const q15_t cos_factorsQ15_128[128];
|
||||
|
||||
extern const q15_t WeightsQ15_512[1024];
|
||||
extern const q15_t cos_factorsQ15_512[512];
|
||||
|
||||
extern const q15_t WeightsQ15_2048[4096];
|
||||
extern const q15_t cos_factorsQ15_2048[2048];
|
||||
|
||||
extern const q15_t WeightsQ15_8192[16384];
|
||||
extern const q15_t cos_factorsQ15_8192[8192];
|
||||
|
||||
extern const q31_t WeightsQ31_128[256];
|
||||
extern const q31_t cos_factorsQ31_128[128];
|
||||
|
||||
extern const q31_t WeightsQ31_512[1024];
|
||||
extern const q31_t cos_factorsQ31_512[512];
|
||||
|
||||
extern const q31_t WeightsQ31_2048[4096];
|
||||
extern const q31_t cos_factorsQ31_2048[2048];
|
||||
|
||||
extern const q31_t WeightsQ31_8192[16384];
|
||||
extern const q31_t cos_factorsQ31_8192[8192];
|
||||
|
||||
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
|
||||
/* Accurate scalar sqrt */
|
||||
extern const q31_t sqrt_initial_lut_q31[32];
|
||||
|
||||
extern const q15_t sqrt_initial_lut_q15[16];
|
||||
|
||||
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
extern const q15_t sqrtTable_Q15[256];
|
||||
extern const q31_t sqrtTable_Q31[256];
|
||||
extern const unsigned char hwLUT[256];
|
||||
#endif
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
extern const float32_t exp_tab[8];
|
||||
extern const float32_t __logf_lut_f32[8];
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
|
||||
@@ -1,95 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables_f16.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_F16_H
|
||||
#define _ARM_COMMON_TABLES_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/* F16 */
|
||||
#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
|
||||
extern const float16_t twiddleCoefF16_16[32];
|
||||
|
||||
extern const float16_t twiddleCoefF16_32[64];
|
||||
|
||||
extern const float16_t twiddleCoefF16_64[128];
|
||||
|
||||
extern const float16_t twiddleCoefF16_128[256];
|
||||
|
||||
extern const float16_t twiddleCoefF16_256[512];
|
||||
|
||||
extern const float16_t twiddleCoefF16_512[1024];
|
||||
|
||||
extern const float16_t twiddleCoefF16_1024[2048];
|
||||
|
||||
extern const float16_t twiddleCoefF16_2048[4096];
|
||||
|
||||
extern const float16_t twiddleCoefF16_4096[8192];
|
||||
#define twiddleCoefF16 twiddleCoefF16_4096
|
||||
|
||||
|
||||
extern const float16_t twiddleCoefF16_rfft_32[32];
|
||||
|
||||
extern const float16_t twiddleCoefF16_rfft_64[64];
|
||||
|
||||
extern const float16_t twiddleCoefF16_rfft_128[128];
|
||||
|
||||
extern const float16_t twiddleCoefF16_rfft_256[256];
|
||||
|
||||
extern const float16_t twiddleCoefF16_rfft_512[512];
|
||||
|
||||
extern const float16_t twiddleCoefF16_rfft_1024[1024];
|
||||
|
||||
extern const float16_t twiddleCoefF16_rfft_2048[2048];
|
||||
|
||||
extern const float16_t twiddleCoefF16_rfft_4096[4096];
|
||||
|
||||
#endif /* ARMAC5 */
|
||||
|
||||
|
||||
#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
extern const float16_t exp_tab_f16[8];
|
||||
extern const float16_t __logf_lut_f16[8];
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_COMMON_TABLES_F16_H */
|
||||
|
||||
|
||||
@@ -1,86 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_common_tables.h"
|
||||
#include "dsp/transform_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096;
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,59 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs_f16.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f16() function.
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_F16_H
|
||||
#define _ARM_CONST_STRUCTS_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_common_tables.h"
|
||||
#include "arm_common_tables_f16.h"
|
||||
#include "dsp/transform_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len16;
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len32;
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len64;
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len128;
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len256;
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len512;
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024;
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048;
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,749 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_helium_utils.h
|
||||
* Description: Utility functions for Helium development
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_UTILS_HELIUM_H_
|
||||
#define _ARM_UTILS_HELIUM_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEF and MVEI
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define INACTIVELANE 0 /* inactive lane content */
|
||||
|
||||
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEF only
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in)
|
||||
{
|
||||
float32_t acc;
|
||||
|
||||
acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) +
|
||||
vgetq_lane(in, 2) + vgetq_lane(in, 3);
|
||||
|
||||
return acc;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* newton initial guess */
|
||||
#define INVSQRT_MAGIC_F32 0x5f3759df
|
||||
#define INV_NEWTON_INIT_F32 0x7EF127EA
|
||||
|
||||
|
||||
#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\
|
||||
{ \
|
||||
float32x4_t tmp; \
|
||||
\
|
||||
/* tmp = xhalf * x * x */ \
|
||||
tmp = vmulq(xStart, xStart); \
|
||||
tmp = vmulq(tmp, xHalf); \
|
||||
/* (1.5f - xhalf * x * x) */ \
|
||||
tmp = vsubq(vdupq_n_f32(1.5f), tmp); \
|
||||
/* x = x*(1.5f-xhalf*x*x); */ \
|
||||
invSqrt = vmulq(tmp, xStart); \
|
||||
}
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */
|
||||
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for f16 datatype with HW acceleration only
|
||||
|
||||
***************************************/
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
#if defined (ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
__STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in)
|
||||
{
|
||||
float16x8_t tmpVec;
|
||||
_Float16 acc;
|
||||
|
||||
tmpVec = (float16x8_t) vrev32q_s16((int16x8_t) in);
|
||||
in = vaddq_f16(tmpVec, in);
|
||||
tmpVec = (float16x8_t) vrev64q_s32((int32x4_t) in);
|
||||
in = vaddq_f16(tmpVec, in);
|
||||
acc = (_Float16)vgetq_lane_f16(in, 0) + (_Float16)vgetq_lane_f16(in, 4);
|
||||
|
||||
return acc;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16(
|
||||
float16x8_t vecIn)
|
||||
{
|
||||
float16x8_t vecTmp, vecOut;
|
||||
uint32_t tmp = 0;
|
||||
|
||||
vecTmp = (float16x8_t) vrev64q_s32((int32x4_t) vecIn);
|
||||
// TO TRACK : using canonical addition leads to unefficient code generation for f16
|
||||
// vecTmp = vecTmp + vecAccCpx0;
|
||||
/*
|
||||
* Compute
|
||||
* re0+re1 | im0+im1 | re0+re1 | im0+im1
|
||||
* re2+re3 | im2+im3 | re2+re3 | im2+im3
|
||||
*/
|
||||
vecTmp = vaddq_f16(vecTmp, vecIn);
|
||||
vecOut = vecTmp;
|
||||
/*
|
||||
* shift left, random tmp insertion in bottom
|
||||
*/
|
||||
vecOut = vreinterpretq_f16_s32(vshlcq_s32(vreinterpretq_s32_f16(vecOut) , &tmp, 32));
|
||||
/*
|
||||
* Compute:
|
||||
* DONTCARE | DONTCARE | re0+re1+re0+re1 |im0+im1+im0+im1
|
||||
* re0+re1+re2+re3 | im0+im1+im2+im3 | re2+re3+re2+re3 |im2+im3+im2+im3
|
||||
*/
|
||||
vecOut = vaddq_f16(vecOut, vecTmp);
|
||||
/*
|
||||
* Cmplx sum is in 4rd & 5th f16 elt
|
||||
* return full vector
|
||||
*/
|
||||
return vecOut;
|
||||
}
|
||||
|
||||
|
||||
#define mve_cmplx_sum_intra_r_i_f16(vec, Re, Im) \
|
||||
{ \
|
||||
float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vec); \
|
||||
Re = vgetq_lane(vecOut, 4); \
|
||||
Im = vgetq_lane(vecOut, 5); \
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE void mve_cmplx_sum_intra_vec_f16(
|
||||
float16x8_t vecIn,
|
||||
float16_t *pOut)
|
||||
{
|
||||
float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vecIn);
|
||||
/*
|
||||
* Cmplx sum is in 4rd & 5th f16 elt
|
||||
* use 32-bit extraction
|
||||
*/
|
||||
*(float32_t *) pOut = ((float32x4_t) vecOut)[2];
|
||||
}
|
||||
|
||||
|
||||
#define INVSQRT_MAGIC_F16 0x59ba /* ( 0x1ba = 0x3759df >> 13) */
|
||||
|
||||
/* canonical version of INVSQRT_NEWTON_MVE_F16 leads to bad performance */
|
||||
#define INVSQRT_NEWTON_MVE_F16(invSqrt, xHalf, xStart) \
|
||||
{ \
|
||||
float16x8_t tmp; \
|
||||
\
|
||||
/* tmp = xhalf * x * x */ \
|
||||
tmp = vmulq(xStart, xStart); \
|
||||
tmp = vmulq(tmp, xHalf); \
|
||||
/* (1.5f - xhalf * x * x) */ \
|
||||
tmp = vsubq(vdupq_n_f16((float16_t)1.5), tmp); \
|
||||
/* x = x*(1.5f-xhalf*x*x); */ \
|
||||
invSqrt = vmulq(tmp, xStart); \
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEI and MVEF only
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
/* Following functions are used to transpose matrix in f32 and q31 cases */
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
static const uint32x4_t vecOffs = { 0, 2, 1, 3 };
|
||||
/*
|
||||
*
|
||||
* | 0 1 | => | 0 2 |
|
||||
* | 2 3 | | 1 3 |
|
||||
*
|
||||
*/
|
||||
uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc);
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
|
||||
const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
|
||||
/*
|
||||
*
|
||||
* | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 |
|
||||
* | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 |
|
||||
* | 6 7 8 | | 2 5 8 | (row major) | 8 . . . |
|
||||
*
|
||||
*/
|
||||
uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc);
|
||||
uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]);
|
||||
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1);
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2);
|
||||
|
||||
pDataDest[8] = pDataSrc[8];
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest)
|
||||
{
|
||||
/*
|
||||
* 4x4 Matrix transposition
|
||||
* is 4 x de-interleave operation
|
||||
*
|
||||
* 0 1 2 3 0 4 8 12
|
||||
* 4 5 6 7 1 5 9 13
|
||||
* 8 9 10 11 2 6 10 14
|
||||
* 12 13 14 15 3 7 11 15
|
||||
*/
|
||||
|
||||
uint32x4x4_t vecIn;
|
||||
|
||||
vecIn = vld4q((uint32_t const *) pDataSrc);
|
||||
vstrwq(pDataDest, vecIn.val[0]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[1]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[2]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[3]);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
uint32x4_t vecOffs;
|
||||
uint32_t i;
|
||||
uint32_t blkCnt;
|
||||
uint32_t const *pDataC;
|
||||
uint32_t *pDataDestR;
|
||||
uint32x4_t vecIn;
|
||||
|
||||
vecOffs = vidupq_u32((uint32_t)0, 1);
|
||||
vecOffs = vecOffs * srcCols;
|
||||
|
||||
i = srcCols;
|
||||
do
|
||||
{
|
||||
pDataC = (uint32_t const *) pDataSrc;
|
||||
pDataDestR = pDataDest;
|
||||
|
||||
blkCnt = srcRows >> 2;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
|
||||
vstrwq(pDataDestR, vecIn);
|
||||
pDataDestR += 4;
|
||||
pDataC = pDataC + srcCols * 4;
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/*
|
||||
* tail
|
||||
*/
|
||||
blkCnt = srcRows & 3;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp32q(blkCnt);
|
||||
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
|
||||
vstrwq_p(pDataDestR, vecIn, p0);
|
||||
}
|
||||
|
||||
pDataSrc += 1;
|
||||
pDataDest += srcRows;
|
||||
}
|
||||
while (--i);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint32_t *pDataSrc,
|
||||
uint16_t dstRows,
|
||||
uint16_t dstCols,
|
||||
uint32_t *pDataDest)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t const *pDataC;
|
||||
uint32_t *pDataRow;
|
||||
uint32_t *pDataDestR, *pDataDestRow;
|
||||
uint32x4_t vecOffsRef, vecOffsCur;
|
||||
uint32_t blkCnt;
|
||||
uint32x4_t vecIn;
|
||||
|
||||
#ifdef ARM_MATH_MATRIX_CHECK
|
||||
/*
|
||||
* Check for matrix mismatch condition
|
||||
*/
|
||||
if ((srcRows != dstCols) || (srcCols != dstRows))
|
||||
{
|
||||
/*
|
||||
* Set status as ARM_MATH_SIZE_MISMATCH
|
||||
*/
|
||||
return ARM_MATH_SIZE_MISMATCH;
|
||||
}
|
||||
#else
|
||||
(void)dstRows;
|
||||
(void)dstCols;
|
||||
#endif
|
||||
|
||||
/* 2x2, 3x3 and 4x4 specialization to be added */
|
||||
|
||||
vecOffsRef[0] = 0;
|
||||
vecOffsRef[1] = 1;
|
||||
vecOffsRef[2] = srcCols << 1;
|
||||
vecOffsRef[3] = (srcCols << 1) + 1;
|
||||
|
||||
pDataRow = pDataSrc;
|
||||
pDataDestRow = pDataDest;
|
||||
i = srcCols;
|
||||
do
|
||||
{
|
||||
pDataC = (uint32_t const *) pDataRow;
|
||||
pDataDestR = pDataDestRow;
|
||||
vecOffsCur = vecOffsRef;
|
||||
|
||||
blkCnt = (srcRows * CMPLX_DIM) >> 2;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrwq(pDataDestR, vecIn);
|
||||
pDataDestR += 4;
|
||||
vecOffsCur = vaddq(vecOffsCur, (srcCols << 2));
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
/*
|
||||
* tail
|
||||
* (will be merged thru tail predication)
|
||||
*/
|
||||
blkCnt = (srcRows * CMPLX_DIM) & 3;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp32q(blkCnt);
|
||||
vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrwq_p(pDataDestR, vecIn, p0);
|
||||
}
|
||||
|
||||
pDataRow += CMPLX_DIM;
|
||||
pDataDestRow += (srcRows * CMPLX_DIM);
|
||||
}
|
||||
while (--i);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t * pDataDest)
|
||||
{
|
||||
pDataDest[0] = pDataSrc[0];
|
||||
pDataDest[3] = pDataSrc[3];
|
||||
pDataDest[2] = pDataSrc[1];
|
||||
pDataDest[1] = pDataSrc[2];
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
|
||||
{
|
||||
static const uint16_t stridesTr33[8] = { 0, 3, 6, 1, 4, 7, 2, 5 };
|
||||
uint16x8_t vecOffs1;
|
||||
uint16x8_t vecIn1;
|
||||
/*
|
||||
*
|
||||
* | 0 1 2 | | 0 3 6 | 8 x 16 flattened version | 0 3 6 1 4 7 2 5 |
|
||||
* | 3 4 5 | => | 1 4 7 | => | 8 . . . . . . . |
|
||||
* | 6 7 8 | | 2 5 8 | (row major)
|
||||
*
|
||||
*/
|
||||
vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr33);
|
||||
vecIn1 = vldrhq_u16((uint16_t const *) pDataSrc);
|
||||
|
||||
vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1);
|
||||
|
||||
pDataDest[8] = pDataSrc[8];
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
|
||||
{
|
||||
static const uint16_t stridesTr44_1[8] = { 0, 4, 8, 12, 1, 5, 9, 13 };
|
||||
static const uint16_t stridesTr44_2[8] = { 2, 6, 10, 14, 3, 7, 11, 15 };
|
||||
uint16x8_t vecOffs1, vecOffs2;
|
||||
uint16x8_t vecIn1, vecIn2;
|
||||
uint16_t const * pDataSrcVec = (uint16_t const *) pDataSrc;
|
||||
|
||||
/*
|
||||
* 4x4 Matrix transposition
|
||||
*
|
||||
* | 0 1 2 3 | | 0 4 8 12 | 8 x 16 flattened version
|
||||
* | 4 5 6 7 | => | 1 5 9 13 | => [0 4 8 12 1 5 9 13]
|
||||
* | 8 9 10 11 | | 2 6 10 14 | [2 6 10 14 3 7 11 15]
|
||||
* | 12 13 14 15 | | 3 7 11 15 |
|
||||
*/
|
||||
|
||||
vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr44_1);
|
||||
vecOffs2 = vldrhq_u16((uint16_t const *) stridesTr44_2);
|
||||
vecIn1 = vldrhq_u16(pDataSrcVec);
|
||||
pDataSrcVec += 8;
|
||||
vecIn2 = vldrhq_u16(pDataSrcVec);
|
||||
|
||||
vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1);
|
||||
vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs2, vecIn2);
|
||||
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_generic(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint16_t * pDataSrc,
|
||||
uint16_t * pDataDest)
|
||||
{
|
||||
uint16x8_t vecOffs;
|
||||
uint32_t i;
|
||||
uint32_t blkCnt;
|
||||
uint16_t const *pDataC;
|
||||
uint16_t *pDataDestR;
|
||||
uint16x8_t vecIn;
|
||||
|
||||
vecOffs = vidupq_u16((uint32_t)0, 1);
|
||||
vecOffs = vecOffs * srcCols;
|
||||
|
||||
i = srcCols;
|
||||
while(i > 0U)
|
||||
{
|
||||
pDataC = (uint16_t const *) pDataSrc;
|
||||
pDataDestR = pDataDest;
|
||||
|
||||
blkCnt = srcRows >> 3;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
|
||||
vstrhq_u16(pDataDestR, vecIn);
|
||||
pDataDestR += 8;
|
||||
pDataC = pDataC + srcCols * 8;
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/*
|
||||
* tail
|
||||
*/
|
||||
blkCnt = srcRows & 7;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp16q(blkCnt);
|
||||
vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
|
||||
vstrhq_p_u16(pDataDestR, vecIn, p0);
|
||||
}
|
||||
pDataSrc += 1;
|
||||
pDataDest += srcRows;
|
||||
i--;
|
||||
}
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint16_t *pDataSrc,
|
||||
uint16_t dstRows,
|
||||
uint16_t dstCols,
|
||||
uint16_t *pDataDest)
|
||||
{
|
||||
static const uint16_t loadCmplxCol[8] = { 0, 0, 1, 1, 2, 2, 3, 3 };
|
||||
int i;
|
||||
uint16x8_t vecOffsRef, vecOffsCur;
|
||||
uint16_t const *pDataC;
|
||||
uint16_t *pDataRow;
|
||||
uint16_t *pDataDestR, *pDataDestRow;
|
||||
uint32_t blkCnt;
|
||||
uint16x8_t vecIn;
|
||||
|
||||
#ifdef ARM_MATH_MATRIX_CHECK
|
||||
/*
|
||||
* Check for matrix mismatch condition
|
||||
*/
|
||||
if ((srcRows != dstCols) || (srcCols != dstRows))
|
||||
{
|
||||
/*
|
||||
* Set status as ARM_MATH_SIZE_MISMATCH
|
||||
*/
|
||||
return ARM_MATH_SIZE_MISMATCH;
|
||||
}
|
||||
#else
|
||||
(void)dstRows;
|
||||
(void)dstCols;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 2x2, 3x3 and 4x4 specialization to be added
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* build [0, 1, 2xcol, 2xcol+1, 4xcol, 4xcol+1, 6xcol, 6xcol+1]
|
||||
*/
|
||||
vecOffsRef = vldrhq_u16((uint16_t const *) loadCmplxCol);
|
||||
vecOffsRef = vmulq(vecOffsRef, (uint16_t) (srcCols * CMPLX_DIM))
|
||||
+ viwdupq_u16((uint32_t)0, (uint16_t) 2, 1);
|
||||
|
||||
pDataRow = pDataSrc;
|
||||
pDataDestRow = pDataDest;
|
||||
i = srcCols;
|
||||
do
|
||||
{
|
||||
pDataC = (uint16_t const *) pDataRow;
|
||||
pDataDestR = pDataDestRow;
|
||||
vecOffsCur = vecOffsRef;
|
||||
|
||||
blkCnt = (srcRows * CMPLX_DIM) >> 3;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrhq(pDataDestR, vecIn);
|
||||
pDataDestR+= 8; // VEC_LANES_U16
|
||||
vecOffsCur = vaddq(vecOffsCur, (srcCols << 3));
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
/*
|
||||
* tail
|
||||
* (will be merged thru tail predication)
|
||||
*/
|
||||
blkCnt = (srcRows * CMPLX_DIM) & 0x7;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp16q(blkCnt);
|
||||
vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrhq_p(pDataDestR, vecIn, p0);
|
||||
}
|
||||
|
||||
pDataRow += CMPLX_DIM;
|
||||
pDataDestRow += (srcRows * CMPLX_DIM);
|
||||
}
|
||||
while (--i);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
#endif /* MVEF and MVEI */
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEI only
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff)
|
||||
#define MVE_ASRL_SAT32(acc, shift) ((sqrshrl(acc, -(32-shift)) >> 32) & 0xffffffff)
|
||||
|
||||
|
||||
__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn)
|
||||
{
|
||||
q63x2_t vecTmpLL;
|
||||
q31x4_t vecTmp0, vecTmp1;
|
||||
q31_t scale;
|
||||
q63_t tmp64;
|
||||
q31x4_t vecNrm, vecDst, vecIdx, vecSignBits;
|
||||
|
||||
|
||||
vecSignBits = vclsq(vecIn);
|
||||
vecSignBits = vbicq_n_s32(vecSignBits, 1);
|
||||
/*
|
||||
* in = in << no_of_sign_bits;
|
||||
*/
|
||||
vecNrm = vshlq(vecIn, vecSignBits);
|
||||
/*
|
||||
* index = in >> 24;
|
||||
*/
|
||||
vecIdx = vecNrm >> 24;
|
||||
vecIdx = vecIdx << 1;
|
||||
|
||||
vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx);
|
||||
|
||||
vecIdx = vecIdx + 1;
|
||||
|
||||
vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx);
|
||||
|
||||
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
|
||||
vecTmp0 = vecTmp0 - vecTmp1;
|
||||
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
|
||||
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
|
||||
vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1;
|
||||
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
|
||||
vecTmpLL = vmullbq_int(vecNrm, vecTmp0);
|
||||
|
||||
/*
|
||||
* scale elements 0, 2
|
||||
*/
|
||||
scale = 26 + (vecSignBits[0] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[0], scale);
|
||||
vecDst[0] = (q31_t) tmp64;
|
||||
|
||||
scale = 26 + (vecSignBits[2] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[1], scale);
|
||||
vecDst[2] = (q31_t) tmp64;
|
||||
|
||||
vecTmpLL = vmulltq_int(vecNrm, vecTmp0);
|
||||
|
||||
/*
|
||||
* scale elements 1, 3
|
||||
*/
|
||||
scale = 26 + (vecSignBits[1] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[0], scale);
|
||||
vecDst[1] = (q31_t) tmp64;
|
||||
|
||||
scale = 26 + (vecSignBits[3] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[1], scale);
|
||||
vecDst[3] = (q31_t) tmp64;
|
||||
/*
|
||||
* set negative values to 0
|
||||
*/
|
||||
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0));
|
||||
|
||||
return vecDst;
|
||||
}
|
||||
|
||||
__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn)
|
||||
{
|
||||
q31x4_t vecTmpLev, vecTmpLodd, vecSignL;
|
||||
q15x8_t vecTmp0, vecTmp1;
|
||||
q15x8_t vecNrm, vecDst, vecIdx, vecSignBits;
|
||||
|
||||
vecDst = vuninitializedq_s16();
|
||||
|
||||
vecSignBits = vclsq(vecIn);
|
||||
vecSignBits = vbicq_n_s16(vecSignBits, 1);
|
||||
/*
|
||||
* in = in << no_of_sign_bits;
|
||||
*/
|
||||
vecNrm = vshlq(vecIn, vecSignBits);
|
||||
|
||||
vecIdx = vecNrm >> 8;
|
||||
vecIdx = vecIdx << 1;
|
||||
|
||||
vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx);
|
||||
|
||||
vecIdx = vecIdx + 1;
|
||||
|
||||
vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx);
|
||||
|
||||
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
|
||||
vecTmp0 = vecTmp0 - vecTmp1;
|
||||
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
|
||||
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
|
||||
vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1;
|
||||
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
|
||||
|
||||
vecSignBits = vecSignBits >> 1;
|
||||
|
||||
vecTmpLev = vmullbq_int(vecNrm, vecTmp0);
|
||||
vecTmpLodd = vmulltq_int(vecNrm, vecTmp0);
|
||||
|
||||
vecTmp0 = vecSignBits + 10;
|
||||
/*
|
||||
* negate sign to apply register based vshl
|
||||
*/
|
||||
vecTmp0 = -vecTmp0;
|
||||
|
||||
/*
|
||||
* shift even elements
|
||||
*/
|
||||
vecSignL = vmovlbq(vecTmp0);
|
||||
vecTmpLev = vshlq(vecTmpLev, vecSignL);
|
||||
/*
|
||||
* shift odd elements
|
||||
*/
|
||||
vecSignL = vmovltq(vecTmp0);
|
||||
vecTmpLodd = vshlq(vecTmpLodd, vecSignL);
|
||||
/*
|
||||
* merge and narrow odd and even parts
|
||||
*/
|
||||
vecDst = vmovnbq_s32(vecDst, vecTmpLev);
|
||||
vecDst = vmovntq_s32(vecDst, vecTmpLodd);
|
||||
/*
|
||||
* set negative values to 0
|
||||
*/
|
||||
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0));
|
||||
|
||||
return vecDst;
|
||||
}
|
||||
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,233 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file arm_math.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
\mainpage CMSIS DSP Software Library
|
||||
*
|
||||
* \section intro Introduction
|
||||
*
|
||||
* This user manual describes the CMSIS DSP software library,
|
||||
* a suite of common compute processing functions for use on Cortex-M and Cortex-A processor
|
||||
* based devices.
|
||||
*
|
||||
* The library is divided into a number of functions each covering a specific category:
|
||||
* - \ref groupMath "Basic math functions"
|
||||
* - \ref groupFastMath "Fast math functions"
|
||||
* - \ref groupCmplxMath "Complex math functions"
|
||||
* - \ref groupFilters "Filtering functions"
|
||||
* - \ref groupMatrix "Matrix functions"
|
||||
* - \ref groupTransforms "Transform functions"
|
||||
* - \ref groupController "Motor control functions"
|
||||
* - \ref groupStats "Statistical functions"
|
||||
* - \ref groupSupport "Support functions"
|
||||
* - \ref groupInterpolation "Interpolation functions"
|
||||
* - \ref groupSVM "Support Vector Machine functions (SVM)"
|
||||
* - \ref groupBayes "Bayes classifier functions"
|
||||
* - \ref groupDistance "Distance functions"
|
||||
* - \ref groupQuaternionMath "Quaternion functions"
|
||||
* - \ref groupWindow "Window functions"
|
||||
*
|
||||
* The library has generally separate functions for operating on 8-bit integers, 16-bit integers,
|
||||
* 32-bit integer and 32-bit floating-point values and 64-bit floating-point values.
|
||||
*
|
||||
* The library is providing vectorized versions of most algorithms for Helium
|
||||
* and of most f32 algorithms for Neon.
|
||||
*
|
||||
* When using a vectorized version, provide a little bit of padding after the end of
|
||||
* a buffer (3 words) because the vectorized code may read a little bit after the end
|
||||
* of a buffer. You don't have to modify your buffers but just ensure that the
|
||||
* end of buffer + padding is not outside of a memory region.
|
||||
*
|
||||
* A Python wrapper is also available with a Python API as close as possible
|
||||
* to the C one. It can be used to start developing and testing an algorithm with NumPy and
|
||||
* SciPy before writing the C version. Is is available on <a href="https://pypi.org/project/cmsisdsp/">PyPI.org</a>.
|
||||
* It can be installed with : pip install cmsisdsp
|
||||
*
|
||||
*
|
||||
* \section using Using the Library
|
||||
*
|
||||
* The library is released in source form. It is strongly advised to compile the library using -Ofast to
|
||||
* have the best performances.
|
||||
*
|
||||
* The library functions are declared in the public file `arm_math.h` which is placed in the `Include` folder.
|
||||
* Simply include this file. If you don't want to include everything, you can also rely
|
||||
* on headers in `Include/dsp` folder and use only what you need.
|
||||
*
|
||||
* \section example Examples
|
||||
*
|
||||
* The library ships with a number of examples which demonstrate how to use the library functions. Please refer to \ref groupExamples.
|
||||
*
|
||||
* \section toolchain Toolchain Support
|
||||
*
|
||||
* The library is now tested on Fast Models building with cmake.
|
||||
* Core M0, M4, M7, M33, M55, A32 are tested.
|
||||
*
|
||||
*
|
||||
* \section preprocessor Preprocessor Macros
|
||||
*
|
||||
* Each library project has different preprocessor macros.
|
||||
*
|
||||
* - `ARM_MATH_BIG_ENDIAN`:
|
||||
* - Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
|
||||
* .
|
||||
* - `ARM_MATH_MATRIX_CHECK`:
|
||||
* - Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
|
||||
* .
|
||||
* - `ARM_MATH_ROUNDING`:
|
||||
* - Define macro ARM_MATH_ROUNDING for rounding on support functions
|
||||
* .
|
||||
* - `ARM_MATH_LOOPUNROLL`:
|
||||
* - Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions
|
||||
* .
|
||||
* - `ARM_MATH_NEON`:
|
||||
* - Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions.
|
||||
* It is not enabled by default when Neon is available because performances are
|
||||
* dependent on the compiler and target architecture.
|
||||
* .
|
||||
* - `ARM_MATH_NEON_EXPERIMENTAL`:
|
||||
* - Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of
|
||||
* of some DSP functions. Experimental Neon versions currently do not have better
|
||||
* performances than the scalar versions.
|
||||
* .
|
||||
* - `ARM_MATH_HELIUM`:
|
||||
* - It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_MVE_FLOAT16.
|
||||
* .
|
||||
* - `ARM_MATH_HELIUM_EXPERIMENTAL`:
|
||||
* - Only taken into account when ARM_MATH_MVEF, ARM_MATH_MVEI or ARM_MATH_MVE_FLOAT16 are defined.
|
||||
* Enable some vector versions which may have worse performance than scalar
|
||||
* depending on the core / compiler configuration.
|
||||
* .
|
||||
* - `ARM_MATH_MVEF`:
|
||||
* - Select Helium versions of the f32 algorithms.
|
||||
* It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI.
|
||||
* .
|
||||
* - `ARM_MATH_MVEI`:
|
||||
* - Select Helium versions of the int and fixed point algorithms.
|
||||
* .
|
||||
* - `ARM_MATH_MVE_FLOAT16`:
|
||||
* - MVE Float16 implementations of some algorithms (Requires MVE extension).
|
||||
* .
|
||||
* - `DISABLEFLOAT16`:
|
||||
* - Disable float16 algorithms when __fp16 is not supported for a
|
||||
* specific compiler / core configuration.
|
||||
* This is only valid for scalar. When vector architecture is
|
||||
* supporting f16 then it can't be disabled.
|
||||
* .
|
||||
* - `ARM_MATH_AUTOVECTORIZE`:
|
||||
* - With Helium or Neon, disable the use of vectorized code with C intrinsics
|
||||
* and use pure C instead. The vectorization is then done by the compiler.
|
||||
*
|
||||
* \section pack CMSIS-DSP in ARM::CMSIS Pack
|
||||
*
|
||||
* The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
|
||||
* |File/Folder |Content |
|
||||
* |---------------------------------|------------------------------------------------------------------------|
|
||||
* |\b CMSIS\\Documentation\\DSP | This documentation |
|
||||
* |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions |
|
||||
* |\b CMSIS\\DSP\\ComputeLibrary | Small Neon kernels when building on Cortex-A
|
||||
* |\b CMSIS\\DSP\\Include | include files for using and building the lib
|
||||
* |\b CMSIS\\DSP\\PrivateInclude | private include files for building the lib |
|
||||
* |\b CMSIS\\DSP\\Source | source files |
|
||||
*
|
||||
* \section rev Revision History of CMSIS-DSP
|
||||
* Please refer to \ref ChangeLog_pg.
|
||||
*
|
||||
* \section license License
|
||||
*
|
||||
* The CMSIS-DSP is provided free of charge under the <a href="LICENSE">Apache 2.0 License</a>.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup groupExamples Examples
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _ARM_MATH_H
|
||||
#define _ARM_MATH_H
|
||||
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
#include "dsp/interpolation_functions.h"
|
||||
#include "dsp/bayes_functions.h"
|
||||
#include "dsp/matrix_functions.h"
|
||||
#include "dsp/complex_math_functions.h"
|
||||
#include "dsp/statistics_functions.h"
|
||||
#include "dsp/controller_functions.h"
|
||||
#include "dsp/support_functions.h"
|
||||
#include "dsp/distance_functions.h"
|
||||
#include "dsp/svm_functions.h"
|
||||
#include "dsp/fast_math_functions.h"
|
||||
#include "dsp/transform_functions.h"
|
||||
#include "dsp/filtering_functions.h"
|
||||
#include "dsp/quaternion_math_functions.h"
|
||||
#include "dsp/window_functions.h"
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
//#define TABLE_SPACING_Q31 0x400000
|
||||
//#define TABLE_SPACING_Q15 0x80
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _ARM_MATH_H */
|
||||
|
||||
/**
|
||||
*
|
||||
* End of file.
|
||||
*/
|
||||
@@ -1,59 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file arm_math_f16.h
|
||||
* @brief Public header file for f16 function of the CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_F16_H
|
||||
#define _ARM_MATH_F16_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
#include "dsp/basic_math_functions_f16.h"
|
||||
#include "dsp/interpolation_functions_f16.h"
|
||||
#include "dsp/bayes_functions_f16.h"
|
||||
#include "dsp/matrix_functions_f16.h"
|
||||
#include "dsp/complex_math_functions_f16.h"
|
||||
#include "dsp/statistics_functions_f16.h"
|
||||
#include "dsp/controller_functions_f16.h"
|
||||
#include "dsp/support_functions_f16.h"
|
||||
#include "dsp/distance_functions_f16.h"
|
||||
#include "dsp/svm_functions_f16.h"
|
||||
#include "dsp/fast_math_functions_f16.h"
|
||||
#include "dsp/transform_functions_f16.h"
|
||||
#include "dsp/filtering_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_MATH_F16_H */
|
||||
|
||||
|
||||
@@ -1,206 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file arm_math_memory.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_MEMORY_H_
|
||||
|
||||
#define _ARM_MATH_MEMORY_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
@brief definition to read/write two 16 bit values.
|
||||
@deprecated
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#define __SIMD32_TYPE int32_t __packed
|
||||
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __SIMD32_TYPE int32_t __packed
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __SIMD32_TYPE __un(aligned) int32_t
|
||||
#elif defined(_MSC_VER )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
|
||||
#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
|
||||
#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
|
||||
#define __SIMD64(addr) (*( int64_t **) & (addr))
|
||||
|
||||
|
||||
/* SIMD replacement */
|
||||
|
||||
|
||||
/**
|
||||
@brief Read 2 Q15 from Q15 pointer.
|
||||
@param[in] pQ15 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
__STATIC_FORCEINLINE q31_t read_q15x2 (
|
||||
q15_t const * pQ15)
|
||||
{
|
||||
q31_t val;
|
||||
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (&val, pQ15, 4);
|
||||
#else
|
||||
val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
|
||||
#endif
|
||||
|
||||
return (val);
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
|
||||
@param[in] pQ15 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q15x2_ia(pQ15) read_q15x2((*(pQ15) += 2) - 2)
|
||||
|
||||
/**
|
||||
@brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
|
||||
@param[in] pQ15 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q15x2_da(pQ15) read_q15x2((*(pQ15) -= 2) + 2)
|
||||
|
||||
/**
|
||||
@brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
|
||||
@param[in] pQ15 points to input value
|
||||
@param[in] value Q31 value
|
||||
@return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void write_q15x2_ia (
|
||||
q15_t ** pQ15,
|
||||
q31_t value)
|
||||
{
|
||||
q31_t val = value;
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (*pQ15, &val, 4);
|
||||
#else
|
||||
(*pQ15)[0] = (q15_t)(val & 0x0FFFF);
|
||||
(*pQ15)[1] = (q15_t)((val >> 16) & 0x0FFFF);
|
||||
#endif
|
||||
|
||||
*pQ15 += 2;
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Write 2 Q15 to Q15 pointer.
|
||||
@param[in] pQ15 points to input value
|
||||
@param[in] value Q31 value
|
||||
@return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void write_q15x2 (
|
||||
q15_t * pQ15,
|
||||
q31_t value)
|
||||
{
|
||||
q31_t val = value;
|
||||
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (pQ15, &val, 4);
|
||||
#else
|
||||
pQ15[0] = (q15_t)(val & 0x0FFFF);
|
||||
pQ15[1] = (q15_t)(val >> 16);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Read 4 Q7 from Q7 pointer
|
||||
@param[in] pQ7 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
__STATIC_FORCEINLINE q31_t read_q7x4 (
|
||||
q7_t const * pQ7)
|
||||
{
|
||||
q31_t val;
|
||||
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (&val, pQ7, 4);
|
||||
#else
|
||||
val =((pQ7[3] & 0x0FF) << 24) | ((pQ7[2] & 0x0FF) << 16) | ((pQ7[1] & 0x0FF) << 8) | (pQ7[0] & 0x0FF);
|
||||
#endif
|
||||
return (val);
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
|
||||
@param[in] pQ7 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q7x4_ia(pQ7) read_q7x4((*(pQ7) += 4) - 4)
|
||||
|
||||
/**
|
||||
@brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
|
||||
@param[in] pQ7 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q7x4_da(pQ7) read_q7x4((*(pQ7) -= 4) + 4)
|
||||
|
||||
/**
|
||||
@brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
|
||||
@param[in] pQ7 points to input value
|
||||
@param[in] value Q31 value
|
||||
@return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void write_q7x4_ia (
|
||||
q7_t ** pQ7,
|
||||
q31_t value)
|
||||
{
|
||||
q31_t val = value;
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (*pQ7, &val, 4);
|
||||
#else
|
||||
(*pQ7)[0] = (q7_t)(val & 0x0FF);
|
||||
(*pQ7)[1] = (q7_t)((val >> 8) & 0x0FF);
|
||||
(*pQ7)[2] = (q7_t)((val >> 16) & 0x0FF);
|
||||
(*pQ7)[3] = (q7_t)((val >> 24) & 0x0FF);
|
||||
|
||||
#endif
|
||||
*pQ7 += 4;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*ifndef _ARM_MATH_MEMORY_H_ */
|
||||
@@ -1,622 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file arm_math_types.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_TYPES_H_
|
||||
|
||||
#define _ARM_MATH_TYPES_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Compiler specific diagnostic adjustment */
|
||||
#if defined ( __CC_ARM )
|
||||
|
||||
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
#pragma GCC diagnostic ignored "-Wold-style-cast"
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wsign-conversion"
|
||||
#pragma GCC diagnostic ignored "-Wconversion"
|
||||
#pragma GCC diagnostic ignored "-Wunused-parameter"
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
|
||||
#elif defined ( _MSC_VER )
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
|
||||
/* Included for instrinsics definitions */
|
||||
#if defined (_MSC_VER )
|
||||
#include <stdint.h>
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#define __STATIC_INLINE static __inline
|
||||
#define __ALIGNED(x) __declspec(align(x))
|
||||
#define __WEAK
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
#include <stdint.h>
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#define __STATIC_FORCEINLINE static inline __attribute__((always_inline))
|
||||
#define __STATIC_INLINE static inline
|
||||
#define __WEAK
|
||||
#elif defined (__GNUC_PYTHON__)
|
||||
#include <stdint.h>
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#define __STATIC_FORCEINLINE static inline __attribute__((always_inline))
|
||||
#define __STATIC_INLINE static inline
|
||||
#define __WEAK
|
||||
#else
|
||||
#include "cmsis_compiler.h"
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#include <float.h>
|
||||
#include <limits.h>
|
||||
|
||||
/* evaluate ARM DSP feature */
|
||||
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
|
||||
#define ARM_MATH_DSP 1
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON)
|
||||
#if defined(_MSC_VER) && defined(_M_ARM64EC)
|
||||
#include <arm64_neon.h>
|
||||
#else
|
||||
#include <arm_neon.h>
|
||||
#endif
|
||||
#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
|
||||
#if !defined(ARM_MATH_NEON_FLOAT16)
|
||||
#define ARM_MATH_NEON_FLOAT16
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
|
||||
#if defined(__ARM_FEATURE_MVE)
|
||||
#if __ARM_FEATURE_MVE
|
||||
#if !defined(ARM_MATH_MVEI)
|
||||
#define ARM_MATH_MVEI
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (__ARM_FEATURE_MVE & 2)
|
||||
#if !defined(ARM_MATH_MVEF)
|
||||
#define ARM_MATH_MVEF
|
||||
#endif
|
||||
#if !defined(ARM_MATH_MVE_FLOAT16)
|
||||
#define ARM_MATH_MVE_FLOAT16
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /*defined(__ARM_FEATURE_MVE)*/
|
||||
#endif /*!defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
|
||||
#if defined (ARM_MATH_HELIUM)
|
||||
#if !defined(ARM_MATH_MVEF)
|
||||
#define ARM_MATH_MVEF
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_MATH_MVEI)
|
||||
#define ARM_MATH_MVEI
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_MATH_MVE_FLOAT16)
|
||||
#define ARM_MATH_MVE_FLOAT16
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#if defined( __ARM_ARCH_7EM__ )
|
||||
#define LOW_OPTIMIZATION_ENTER \
|
||||
_Pragma ("push") \
|
||||
_Pragma ("O1")
|
||||
#else
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#endif
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#if defined ( __ARM_ARCH_7EM__ )
|
||||
#define LOW_OPTIMIZATION_EXIT \
|
||||
_Pragma ("pop")
|
||||
#else
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#endif
|
||||
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define LOW_OPTIMIZATION_ENTER \
|
||||
__attribute__(( optimize("-O1") ))
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#if defined ( __ARM_ARCH_7EM__ )
|
||||
#define LOW_OPTIMIZATION_ENTER \
|
||||
_Pragma ("optimize=low")
|
||||
#else
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#endif
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#if defined ( __ARM_ARCH_7EM__ )
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
|
||||
_Pragma ("optimize=low")
|
||||
#else
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#endif
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Compiler specific diagnostic adjustment */
|
||||
#if defined ( __CC_ARM )
|
||||
|
||||
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
|
||||
#elif defined ( _MSC_VER )
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__ARM_FEATURE_MVE) && __ARM_FEATURE_MVE
|
||||
#include <arm_mve.h>
|
||||
#endif
|
||||
|
||||
#if defined(ARM_DSP_CONFIG_TABLES)
|
||||
#error("-DARM_DSP_CONFIG_TABLES no more supported. Use the new initialization functions to let the linker optimize the code size.")
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional data type in 1.7 format.
|
||||
*/
|
||||
typedef int8_t q7_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional data type in 1.15 format.
|
||||
*/
|
||||
typedef int16_t q15_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional data type in 1.31 format.
|
||||
*/
|
||||
typedef int32_t q31_t;
|
||||
|
||||
/**
|
||||
* @brief 64-bit fractional data type in 1.63 format.
|
||||
*/
|
||||
typedef int64_t q63_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point type definition.
|
||||
*/
|
||||
#if !defined(__ICCARM__) || !(__ARM_FEATURE_MVE & 2)
|
||||
typedef float float32_t;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief 64-bit floating-point type definition.
|
||||
*/
|
||||
typedef double float64_t;
|
||||
|
||||
/**
|
||||
* @brief vector types
|
||||
*/
|
||||
#if defined(ARM_MATH_NEON) || (defined (ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE))
|
||||
/**
|
||||
* @brief 64-bit fractional 128-bit vector data type in 1.63 format
|
||||
*/
|
||||
typedef int64x2_t q63x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x4_t q31x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector data type with 16-bit alignment in 1.15 format.
|
||||
*/
|
||||
typedef __ALIGNED(2) int16x8_t q15x8_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector data type with 8-bit alignment in 1.7 format.
|
||||
*/
|
||||
typedef __ALIGNED(1) int8x16_t q7x16_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector pair data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x4x2_t q31x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x4x4_t q31x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector pair data type in 1.15 format.
|
||||
*/
|
||||
typedef int16x8x2_t q15x8x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format.
|
||||
*/
|
||||
typedef int16x8x4_t q15x8x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector pair data type in 1.7 format.
|
||||
*/
|
||||
typedef int8x16x2_t q7x16x2_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format.
|
||||
*/
|
||||
typedef int8x16x4_t q7x16x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional data type in 9.23 format.
|
||||
*/
|
||||
typedef int32_t q23_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector data type in 9.23 format.
|
||||
*/
|
||||
typedef int32x4_t q23x4_t;
|
||||
|
||||
/**
|
||||
* @brief 64-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int64x2_t status64x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int32x4_t status32x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int16x8_t status16x8_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int8x16_t status8x16_t;
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector type
|
||||
*/
|
||||
typedef float32x4_t f32x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector pair data type
|
||||
*/
|
||||
typedef float32x4x2_t f32x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float32x4x4_t f32x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit ubiquitous 128-bit vector data type
|
||||
*/
|
||||
typedef union _any32x4_t
|
||||
{
|
||||
float32x4_t f;
|
||||
int32x4_t i;
|
||||
} any32x4_t;
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON)
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x2_t q31x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector data type in 1.15 format.
|
||||
*/
|
||||
typedef __ALIGNED(2) int16x4_t q15x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector data type in 1.7 format.
|
||||
*/
|
||||
typedef __ALIGNED(1) int8x8_t q7x8_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit float 64-bit vector data type.
|
||||
*/
|
||||
typedef float32x2_t f32x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector triplet data type
|
||||
*/
|
||||
typedef float32x4x3_t f32x4x3_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format
|
||||
*/
|
||||
typedef int32x4x3_t q31x4x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format
|
||||
*/
|
||||
typedef int16x8x3_t q15x8x3_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format
|
||||
*/
|
||||
typedef int8x16x3_t q7x16x3_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 64-bit vector pair data type
|
||||
*/
|
||||
typedef float32x2x2_t f32x2x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 64-bit vector triplet data type
|
||||
*/
|
||||
typedef float32x2x3_t f32x2x3_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 64-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float32x2x4_t f32x2x4_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector pair data type in 1.31 format
|
||||
*/
|
||||
typedef int32x2x2_t q31x2x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format
|
||||
*/
|
||||
typedef int32x2x3_t q31x2x3_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format
|
||||
*/
|
||||
typedef int32x4x3_t q31x2x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector pair data type in 1.15 format
|
||||
*/
|
||||
typedef int16x4x2_t q15x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format
|
||||
*/
|
||||
typedef int16x4x2_t q15x4x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format
|
||||
*/
|
||||
typedef int16x4x3_t q15x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector pair data type in 1.7 format
|
||||
*/
|
||||
typedef int8x8x2_t q7x8x2_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format
|
||||
*/
|
||||
typedef int8x8x3_t q7x8x3_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format
|
||||
*/
|
||||
typedef int8x8x4_t q7x8x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit ubiquitous 64-bit vector data type
|
||||
*/
|
||||
typedef union _any32x2_t
|
||||
{
|
||||
float32x2_t f;
|
||||
int32x2_t i;
|
||||
} any32x2_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief 32-bit status 64-bit vector data type.
|
||||
*/
|
||||
typedef int32x4_t status32x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit status 64-bit vector data type.
|
||||
*/
|
||||
typedef int16x8_t status16x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit status 64-bit vector data type.
|
||||
*/
|
||||
typedef int8x16_t status8x8_t;
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define F64_MAX ((float64_t)DBL_MAX)
|
||||
#define F32_MAX ((float32_t)FLT_MAX)
|
||||
|
||||
|
||||
|
||||
#define F64_MIN (-DBL_MAX)
|
||||
#define F32_MIN (-FLT_MAX)
|
||||
|
||||
|
||||
|
||||
#define F64_ABSMAX ((float64_t)DBL_MAX)
|
||||
#define F32_ABSMAX ((float32_t)FLT_MAX)
|
||||
|
||||
|
||||
|
||||
#define F64_ABSMIN ((float64_t)0.0)
|
||||
#define F32_ABSMIN ((float32_t)0.0)
|
||||
|
||||
|
||||
#define Q31_MAX ((q31_t)(0x7FFFFFFFL))
|
||||
#define Q15_MAX ((q15_t)(0x7FFF))
|
||||
#define Q7_MAX ((q7_t)(0x7F))
|
||||
#define Q31_MIN ((q31_t)(0x80000000L))
|
||||
#define Q15_MIN ((q15_t)(0x8000))
|
||||
#define Q7_MIN ((q7_t)(0x80))
|
||||
|
||||
#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL))
|
||||
#define Q15_ABSMAX ((q15_t)(0x7FFF))
|
||||
#define Q7_ABSMAX ((q7_t)(0x7F))
|
||||
#define Q31_ABSMIN ((q31_t)0)
|
||||
#define Q15_ABSMIN ((q15_t)0)
|
||||
#define Q7_ABSMIN ((q7_t)0)
|
||||
|
||||
/* Dimension C vector space */
|
||||
#define CMPLX_DIM 2
|
||||
|
||||
/**
|
||||
* @brief Error status returned by some functions in the library.
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ARM_MATH_SUCCESS = 0, /**< No error */
|
||||
ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
|
||||
ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
|
||||
ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */
|
||||
ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
|
||||
ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */
|
||||
ARM_MATH_TEST_FAILURE = -6, /**< Test Failed */
|
||||
ARM_MATH_DECOMPOSITION_FAILURE = -7 /**< Decomposition Failed */
|
||||
} arm_status;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*ifndef _ARM_MATH_TYPES_H_ */
|
||||
@@ -1,163 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file arm_math_types_f16.h
|
||||
* @brief Public header file for f16 function of the CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_TYPES_F16_H
|
||||
#define _ARM_MATH_TYPES_F16_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if !defined( __CC_ARM )
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point type definition.
|
||||
* This is already defined in arm_mve.h
|
||||
*
|
||||
* This is not fully supported on ARM AC5.
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
Check if the type __fp16 is available.
|
||||
If it is not available, f16 version of the kernels
|
||||
won't be built.
|
||||
|
||||
*/
|
||||
#if !(__ARM_FEATURE_MVE & 2)
|
||||
#if !defined(DISABLEFLOAT16)
|
||||
#if defined(__ARM_FP16_FORMAT_IEEE) || defined(__ARM_FP16_FORMAT_ALTERNATIVE)
|
||||
typedef __fp16 float16_t;
|
||||
#define ARM_FLOAT16_SUPPORTED
|
||||
#endif
|
||||
#endif
|
||||
#else
|
||||
/* When Vector float16, this flag is always defined and can't be disabled */
|
||||
#define ARM_FLOAT16_SUPPORTED
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/
|
||||
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_NEON_FLOAT16)
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector data type
|
||||
*/
|
||||
typedef __ALIGNED(2) float16x8_t f16x8_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector pair data type
|
||||
*/
|
||||
typedef float16x8x2_t f16x8x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float16x8x4_t f16x8x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit ubiquitous 128-bit vector data type
|
||||
*/
|
||||
typedef union _any16x8_t
|
||||
{
|
||||
float16x8_t f;
|
||||
int16x8_t i;
|
||||
} any16x8_t;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON)
|
||||
|
||||
|
||||
#if defined(ARM_MATH_NEON_FLOAT16)
|
||||
/**
|
||||
* @brief 16-bit float 64-bit vector data type.
|
||||
*/
|
||||
typedef __ALIGNED(2) float16x4_t f16x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector triplet data type
|
||||
*/
|
||||
typedef float16x8x3_t f16x8x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 64-bit vector pair data type
|
||||
*/
|
||||
typedef float16x4x2_t f16x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 64-bit vector triplet data type
|
||||
*/
|
||||
typedef float16x4x3_t f16x4x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 64-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float16x4x4_t f16x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit ubiquitous 64-bit vector data type
|
||||
*/
|
||||
typedef union _any16x4_t
|
||||
{
|
||||
float16x4_t f;
|
||||
int16x4_t i;
|
||||
} any16x4_t;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
|
||||
#define F16INFINITY ((float16_t) INFINITY)
|
||||
|
||||
#else
|
||||
|
||||
#define F16INFINITY ((float16_t)__builtin_inf())
|
||||
|
||||
#endif
|
||||
|
||||
#define F16_MAX ((float16_t)__FLT16_MAX__)
|
||||
#define F16_MIN (-(_Float16)__FLT16_MAX__)
|
||||
|
||||
#define F16_ABSMAX ((float16_t)__FLT16_MAX__)
|
||||
#define F16_ABSMIN ((float16_t)0.0f16)
|
||||
|
||||
#endif /* ARM_FLOAT16_SUPPORTED*/
|
||||
#endif /* !defined( __CC_ARM ) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_MATH_F16_H */
|
||||
@@ -1,193 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_mve_tables.h
|
||||
* Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
|
||||
* used for MVE implementation only
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 04 October 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MVE_TABLES_H
|
||||
#define _ARM_MVE_TABLES_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
|
||||
extern const float32_t rearranged_twiddle_stride1_16_f32[8];
|
||||
extern const float32_t rearranged_twiddle_stride2_16_f32[8];
|
||||
extern const float32_t rearranged_twiddle_stride3_16_f32[8];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
|
||||
extern const float32_t rearranged_twiddle_stride1_64_f32[40];
|
||||
extern const float32_t rearranged_twiddle_stride2_64_f32[40];
|
||||
extern const float32_t rearranged_twiddle_stride3_64_f32[40];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
|
||||
extern const float32_t rearranged_twiddle_stride1_256_f32[168];
|
||||
extern const float32_t rearranged_twiddle_stride2_256_f32[168];
|
||||
extern const float32_t rearranged_twiddle_stride3_256_f32[168];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
|
||||
extern const float32_t rearranged_twiddle_stride1_1024_f32[680];
|
||||
extern const float32_t rearranged_twiddle_stride2_1024_f32[680];
|
||||
extern const float32_t rearranged_twiddle_stride3_1024_f32[680];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
|
||||
extern const float32_t rearranged_twiddle_stride1_4096_f32[2728];
|
||||
extern const float32_t rearranged_twiddle_stride2_4096_f32[2728];
|
||||
extern const float32_t rearranged_twiddle_stride3_4096_f32[2728];
|
||||
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
|
||||
extern const q31_t rearranged_twiddle_stride1_16_q31[8];
|
||||
extern const q31_t rearranged_twiddle_stride2_16_q31[8];
|
||||
extern const q31_t rearranged_twiddle_stride3_16_q31[8];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
|
||||
extern const q31_t rearranged_twiddle_stride1_64_q31[40];
|
||||
extern const q31_t rearranged_twiddle_stride2_64_q31[40];
|
||||
extern const q31_t rearranged_twiddle_stride3_64_q31[40];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
|
||||
extern const q31_t rearranged_twiddle_stride1_256_q31[168];
|
||||
extern const q31_t rearranged_twiddle_stride2_256_q31[168];
|
||||
extern const q31_t rearranged_twiddle_stride3_256_q31[168];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
|
||||
extern const q31_t rearranged_twiddle_stride1_1024_q31[680];
|
||||
extern const q31_t rearranged_twiddle_stride2_1024_q31[680];
|
||||
extern const q31_t rearranged_twiddle_stride3_1024_q31[680];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
|
||||
extern const q31_t rearranged_twiddle_stride1_4096_q31[2728];
|
||||
extern const q31_t rearranged_twiddle_stride2_4096_q31[2728];
|
||||
extern const q31_t rearranged_twiddle_stride3_4096_q31[2728];
|
||||
|
||||
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
|
||||
extern const q15_t rearranged_twiddle_stride1_16_q15[8];
|
||||
extern const q15_t rearranged_twiddle_stride2_16_q15[8];
|
||||
extern const q15_t rearranged_twiddle_stride3_16_q15[8];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
|
||||
extern const q15_t rearranged_twiddle_stride1_64_q15[40];
|
||||
extern const q15_t rearranged_twiddle_stride2_64_q15[40];
|
||||
extern const q15_t rearranged_twiddle_stride3_64_q15[40];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
|
||||
extern const q15_t rearranged_twiddle_stride1_256_q15[168];
|
||||
extern const q15_t rearranged_twiddle_stride2_256_q15[168];
|
||||
extern const q15_t rearranged_twiddle_stride3_256_q15[168];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
|
||||
extern const q15_t rearranged_twiddle_stride1_1024_q15[680];
|
||||
extern const q15_t rearranged_twiddle_stride2_1024_q15[680];
|
||||
extern const q15_t rearranged_twiddle_stride3_1024_q15[680];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
|
||||
extern const q15_t rearranged_twiddle_stride1_4096_q15[2728];
|
||||
extern const q15_t rearranged_twiddle_stride2_4096_q15[2728];
|
||||
extern const q15_t rearranged_twiddle_stride3_4096_q15[2728];
|
||||
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*_ARM_MVE_TABLES_H*/
|
||||
|
||||
@@ -1,97 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_mve_tables_f16.h
|
||||
* Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
|
||||
* used for MVE implementation only
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 04 October 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MVE_TABLES_F16_H
|
||||
#define _ARM_MVE_TABLES_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2];
|
||||
extern const float16_t rearranged_twiddle_stride1_16_f16[8];
|
||||
extern const float16_t rearranged_twiddle_stride2_16_f16[8];
|
||||
extern const float16_t rearranged_twiddle_stride3_16_f16[8];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3];
|
||||
extern const float16_t rearranged_twiddle_stride1_64_f16[40];
|
||||
extern const float16_t rearranged_twiddle_stride2_64_f16[40];
|
||||
extern const float16_t rearranged_twiddle_stride3_64_f16[40];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4];
|
||||
extern const float16_t rearranged_twiddle_stride1_256_f16[168];
|
||||
extern const float16_t rearranged_twiddle_stride2_256_f16[168];
|
||||
extern const float16_t rearranged_twiddle_stride3_256_f16[168];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5];
|
||||
extern const float16_t rearranged_twiddle_stride1_1024_f16[680];
|
||||
extern const float16_t rearranged_twiddle_stride2_1024_f16[680];
|
||||
extern const float16_t rearranged_twiddle_stride3_1024_f16[680];
|
||||
|
||||
|
||||
extern const uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6];
|
||||
extern const uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6];
|
||||
extern const float16_t rearranged_twiddle_stride1_4096_f16[2728];
|
||||
extern const float16_t rearranged_twiddle_stride2_4096_f16[2728];
|
||||
extern const float16_t rearranged_twiddle_stride3_4096_f16[2728];
|
||||
|
||||
|
||||
|
||||
#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*_ARM_MVE_TABLES_F16_H*/
|
||||
|
||||
@@ -1,373 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file arm_vec_math.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_VEC_MATH_H
|
||||
#define _ARM_VEC_MATH_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_common_tables.h"
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define INV_NEWTON_INIT_F32 0x7EF127EA
|
||||
|
||||
static const float32_t __logf_rng_f32=0.693147180f;
|
||||
|
||||
|
||||
/* fast inverse approximation (3x newton) */
|
||||
__STATIC_INLINE f32x4_t vrecip_medprec_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
q31x4_t m;
|
||||
f32x4_t b;
|
||||
any32x4_t xinv;
|
||||
f32x4_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
m = 0x3F800000 - (xinv.i & 0x7F800000);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
/* fast inverse approximation (4x newton) */
|
||||
__STATIC_INLINE f32x4_t vrecip_hiprec_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
q31x4_t m;
|
||||
f32x4_t b;
|
||||
any32x4_t xinv;
|
||||
f32x4_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
|
||||
m = 0x3F800000 - (xinv.i & 0x7F800000);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vdiv_f32(
|
||||
f32x4_t num, f32x4_t den)
|
||||
{
|
||||
return vmulq(num, vrecip_hiprec_f32(den));
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Single-precision taylor dev.
|
||||
@param[in] x f32 quad vector input
|
||||
@param[in] coeffs f32 quad vector coeffs
|
||||
@return destination f32 quad vector
|
||||
*/
|
||||
|
||||
__STATIC_INLINE f32x4_t vtaylor_polyq_f32(
|
||||
f32x4_t x,
|
||||
const float32_t * coeffs)
|
||||
{
|
||||
f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]);
|
||||
f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]);
|
||||
f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]);
|
||||
f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]);
|
||||
f32x4_t x2 = vmulq(x, x);
|
||||
f32x4_t x4 = vmulq(x2, x2);
|
||||
f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vmant_exp_f32(
|
||||
f32x4_t x,
|
||||
int32x4_t * e)
|
||||
{
|
||||
any32x4_t r;
|
||||
int32x4_t n;
|
||||
|
||||
r.f = x;
|
||||
n = r.i >> 23;
|
||||
n = n - 127;
|
||||
r.i = r.i - (n << 23);
|
||||
|
||||
*e = n;
|
||||
return r.f;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
|
||||
{
|
||||
q31x4_t vecExpUnBiased;
|
||||
f32x4_t vecTmpFlt0, vecTmpFlt1;
|
||||
f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
|
||||
f32x4_t vecExpUnBiasedFlt;
|
||||
|
||||
/*
|
||||
* extract exponent
|
||||
*/
|
||||
vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased);
|
||||
|
||||
vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
|
||||
/*
|
||||
* a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]);
|
||||
*/
|
||||
vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]);
|
||||
vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]);
|
||||
/*
|
||||
* b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]);
|
||||
*/
|
||||
vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]);
|
||||
vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]);
|
||||
/*
|
||||
* c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]);
|
||||
*/
|
||||
vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]);
|
||||
vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]);
|
||||
/*
|
||||
* d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]);
|
||||
*/
|
||||
vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]);
|
||||
vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]);
|
||||
/*
|
||||
* a = a + b * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
|
||||
/*
|
||||
* c = c + d * xx;
|
||||
*/
|
||||
vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
|
||||
/*
|
||||
* xx = xx * xx;
|
||||
*/
|
||||
vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
|
||||
vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased);
|
||||
/*
|
||||
* r.f = a + c * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
|
||||
/*
|
||||
* add exponent
|
||||
* r.f = r.f + ((float32_t) m) * __logf_rng_f32;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32);
|
||||
// set log0 down to -inf
|
||||
vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f));
|
||||
return vecAcc0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vexpq_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
// Perform range reduction [-log(2),log(2)]
|
||||
int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f));
|
||||
f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f));
|
||||
|
||||
// Polynomial Approximation
|
||||
f32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
|
||||
|
||||
// Reconstruct
|
||||
poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23)));
|
||||
|
||||
poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126));
|
||||
return poly;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
|
||||
{
|
||||
f32x4_t r = x;
|
||||
nb--;
|
||||
while (nb > 0) {
|
||||
r = vmulq(r, x);
|
||||
nb--;
|
||||
}
|
||||
return (r);
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
|
||||
{
|
||||
f32x4_t vecSx, vecW, vecTmp;
|
||||
any32x4_t v;
|
||||
|
||||
vecSx = vabsq(vecIn);
|
||||
|
||||
v.f = vecIn;
|
||||
v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i);
|
||||
|
||||
vecW = vmulq(vecSx, v.f);
|
||||
|
||||
// v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
|
||||
vecTmp = vsubq(vdupq_n_f32(8.0f), vecW);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -70.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 8.0f);
|
||||
v.f = vmulq(v.f, vecTmp);
|
||||
|
||||
v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f));
|
||||
return v.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vtanhq_f32(
|
||||
f32x4_t val)
|
||||
{
|
||||
f32x4_t x =
|
||||
vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f));
|
||||
f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f));
|
||||
f32x4_t num = vsubq_n_f32(exp2x, 1.f);
|
||||
f32x4_t den = vaddq_n_f32(exp2x, 1.f);
|
||||
f32x4_t tanh = vmulq_f32(num, vrecip_f32(den));
|
||||
return tanh;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vpowq_f32(
|
||||
f32x4_t val,
|
||||
f32x4_t n)
|
||||
{
|
||||
return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
|
||||
}
|
||||
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
|
||||
|
||||
#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "NEMath.h"
|
||||
/**
|
||||
* @brief Vectorized integer exponentiation
|
||||
* @param[in] x value
|
||||
* @param[in] nb integer exponent >= 1
|
||||
* @return x^nb
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
|
||||
{
|
||||
float32x4_t r = x;
|
||||
nb --;
|
||||
while(nb > 0)
|
||||
{
|
||||
r = vmulq_f32(r , x);
|
||||
nb--;
|
||||
}
|
||||
return(r);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x)
|
||||
{
|
||||
float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
|
||||
float32x4_t e = vrsqrteq_f32(x1);
|
||||
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
|
||||
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
|
||||
return vmulq_f32(x, e);
|
||||
}
|
||||
|
||||
__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
|
||||
{
|
||||
float32x4_t tempF;
|
||||
int32x4_t tempHI,tempLO;
|
||||
|
||||
tempLO = vmovl_s16(vget_low_s16(vec));
|
||||
tempF = vcvtq_n_f32_s32(tempLO,15);
|
||||
tempF = __arm_vec_sqrt_f32_neon(tempF);
|
||||
tempLO = vcvtq_n_s32_f32(tempF,15);
|
||||
|
||||
tempHI = vmovl_s16(vget_high_s16(vec));
|
||||
tempF = vcvtq_n_f32_s32(tempHI,15);
|
||||
tempF = __arm_vec_sqrt_f32_neon(tempF);
|
||||
tempHI = vcvtq_n_s32_f32(tempF,15);
|
||||
|
||||
return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI)));
|
||||
}
|
||||
|
||||
__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec)
|
||||
{
|
||||
float32x4_t temp;
|
||||
|
||||
temp = vcvtq_n_f32_s32(vec,31);
|
||||
temp = __arm_vec_sqrt_f32_neon(temp);
|
||||
return(vcvtq_n_s32_f32(temp,31));
|
||||
}
|
||||
|
||||
#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _ARM_VEC_MATH_H */
|
||||
|
||||
/**
|
||||
*
|
||||
* End of file.
|
||||
*/
|
||||
@@ -1,312 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file arm_vec_math_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_VEC_MATH_F16_H
|
||||
#define _ARM_VEC_MATH_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_common_tables_f16.h"
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
|
||||
static const float16_t __logf_rng_f16=0.693147180f16;
|
||||
|
||||
/* fast inverse approximation (3x newton) */
|
||||
__STATIC_INLINE f16x8_t vrecip_medprec_f16(
|
||||
f16x8_t x)
|
||||
{
|
||||
q15x8_t m;
|
||||
f16x8_t b;
|
||||
any16x8_t xinv;
|
||||
f16x8_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
|
||||
m = 0x03c00 - (xinv.i & 0x07c00);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
/* fast inverse approximation (4x newton) */
|
||||
__STATIC_INLINE f16x8_t vrecip_hiprec_f16(
|
||||
f16x8_t x)
|
||||
{
|
||||
q15x8_t m;
|
||||
f16x8_t b;
|
||||
any16x8_t xinv;
|
||||
f16x8_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
|
||||
m = 0x03c00 - (xinv.i & 0x07c00);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f16x8_t vdiv_f16(
|
||||
f16x8_t num, f16x8_t den)
|
||||
{
|
||||
return vmulq(num, vrecip_hiprec_f16(den));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Single-precision taylor dev.
|
||||
@param[in] x f16 vector input
|
||||
@param[in] coeffs f16 vector coeffs
|
||||
@return destination f16 vector
|
||||
*/
|
||||
|
||||
__STATIC_INLINE float16x8_t vtaylor_polyq_f16(
|
||||
float16x8_t x,
|
||||
const float16_t * coeffs)
|
||||
{
|
||||
float16x8_t A = vfmasq(vdupq_n_f16(coeffs[4]), x, coeffs[0]);
|
||||
float16x8_t B = vfmasq(vdupq_n_f16(coeffs[6]), x, coeffs[2]);
|
||||
float16x8_t C = vfmasq(vdupq_n_f16(coeffs[5]), x, coeffs[1]);
|
||||
float16x8_t D = vfmasq(vdupq_n_f16(coeffs[7]), x, coeffs[3]);
|
||||
float16x8_t x2 = vmulq(x, x);
|
||||
float16x8_t x4 = vmulq(x2, x2);
|
||||
float16x8_t res = vfmaq(vfmaq_f16(A, B, x2), vfmaq_f16(C, D, x2), x4);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
#define VMANT_EXP_F16(x) \
|
||||
any16x8_t r; \
|
||||
int16x8_t n; \
|
||||
\
|
||||
r.f = x; \
|
||||
n = r.i >> 10; \
|
||||
n = n - 15; \
|
||||
r.i = r.i - (n << 10);\
|
||||
\
|
||||
vecExpUnBiased = n; \
|
||||
vecTmpFlt1 = r.f;
|
||||
|
||||
__STATIC_INLINE float16x8_t vlogq_f16(float16x8_t vecIn)
|
||||
{
|
||||
q15x8_t vecExpUnBiased;
|
||||
float16x8_t vecTmpFlt0, vecTmpFlt1;
|
||||
float16x8_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
|
||||
float16x8_t vecExpUnBiasedFlt;
|
||||
|
||||
/*
|
||||
* extract exponent
|
||||
*/
|
||||
VMANT_EXP_F16(vecIn);
|
||||
|
||||
vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
|
||||
/*
|
||||
* a = (__logf_lut_f16[4] * r.f) + (__logf_lut_f16[0]);
|
||||
*/
|
||||
vecAcc0 = vdupq_n_f16(__logf_lut_f16[0]);
|
||||
vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f16[4]);
|
||||
/*
|
||||
* b = (__logf_lut_f16[6] * r.f) + (__logf_lut_f16[2]);
|
||||
*/
|
||||
vecAcc1 = vdupq_n_f16(__logf_lut_f16[2]);
|
||||
vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f16[6]);
|
||||
/*
|
||||
* c = (__logf_lut_f16[5] * r.f) + (__logf_lut_f16[1]);
|
||||
*/
|
||||
vecAcc2 = vdupq_n_f16(__logf_lut_f16[1]);
|
||||
vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f16[5]);
|
||||
/*
|
||||
* d = (__logf_lut_f16[7] * r.f) + (__logf_lut_f16[3]);
|
||||
*/
|
||||
vecAcc3 = vdupq_n_f16(__logf_lut_f16[3]);
|
||||
vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f16[7]);
|
||||
/*
|
||||
* a = a + b * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
|
||||
/*
|
||||
* c = c + d * xx;
|
||||
*/
|
||||
vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
|
||||
/*
|
||||
* xx = xx * xx;
|
||||
*/
|
||||
vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
|
||||
vecExpUnBiasedFlt = vcvtq_f16_s16(vecExpUnBiased);
|
||||
/*
|
||||
* r.f = a + c * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
|
||||
/*
|
||||
* add exponent
|
||||
* r.f = r.f + ((float32_t) m) * __logf_rng_f16;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f16);
|
||||
// set log0 down to -inf
|
||||
vecAcc0 = vdupq_m_n_f16(vecAcc0, -(_Float16)F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f));
|
||||
return vecAcc0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE float16x8_t vexpq_f16(
|
||||
float16x8_t x)
|
||||
{
|
||||
// Perform range reduction [-log(2),log(2)]
|
||||
int16x8_t m = vcvtq_s16_f16(vmulq_n_f16(x, 1.4426950408f16));
|
||||
float16x8_t val = vfmsq_f16(x, vcvtq_f16_s16(m), vdupq_n_f16(0.6931471805f16));
|
||||
|
||||
// Polynomial Approximation
|
||||
float16x8_t poly = vtaylor_polyq_f16(val, exp_tab_f16);
|
||||
|
||||
// Reconstruct
|
||||
poly = (float16x8_t) (vqaddq_s16((int16x8_t) (poly), vqshlq_n_s16(m, 10)));
|
||||
|
||||
poly = vdupq_m_n_f16(poly, 0.0f16, vcmpltq_n_s16(m, -14));
|
||||
return poly;
|
||||
}
|
||||
|
||||
__STATIC_INLINE float16x8_t arm_vec_exponent_f16(float16x8_t x, int16_t nb)
|
||||
{
|
||||
float16x8_t r = x;
|
||||
nb--;
|
||||
while (nb > 0) {
|
||||
r = vmulq(r, x);
|
||||
nb--;
|
||||
}
|
||||
return (r);
|
||||
}
|
||||
|
||||
__STATIC_INLINE f16x8_t vpowq_f16(
|
||||
f16x8_t val,
|
||||
f16x8_t n)
|
||||
{
|
||||
return vexpq_f16(vmulq_f16(n, vlogq_f16(val)));
|
||||
}
|
||||
|
||||
#define INV_NEWTON_INIT_F16 0x7773
|
||||
|
||||
__STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn)
|
||||
{
|
||||
f16x8_t vecSx, vecW, vecTmp;
|
||||
any16x8_t v;
|
||||
|
||||
vecSx = vabsq(vecIn);
|
||||
|
||||
v.f = vecIn;
|
||||
v.i = vsubq(vdupq_n_s16(INV_NEWTON_INIT_F16), v.i);
|
||||
|
||||
vecW = vmulq(vecSx, v.f);
|
||||
|
||||
// v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
|
||||
vecTmp = vsubq(vdupq_n_f16(8.0f16), vecW);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, -70.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, 8.0f16);
|
||||
v.f = vmulq(v.f, vecTmp);
|
||||
|
||||
v.f = vdupq_m_n_f16(v.f, F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
v.f = vnegq_m(v.f, v.f, vcmpltq_n_f16(vecIn, 0.0f));
|
||||
return v.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f16x8_t vtanhq_f16(
|
||||
f16x8_t val)
|
||||
{
|
||||
f16x8_t x =
|
||||
vminnmq_f16(vmaxnmq_f16(val, vdupq_n_f16(-10.f16)), vdupq_n_f16(10.0f16));
|
||||
f16x8_t exp2x = vexpq_f16(vmulq_n_f16(x, 2.f16));
|
||||
f16x8_t num = vsubq_n_f16(exp2x, 1.f16);
|
||||
f16x8_t den = vaddq_n_f16(exp2x, 1.f16);
|
||||
f16x8_t tanh = vmulq_f16(num, vrecip_f16(den));
|
||||
return tanh;
|
||||
}
|
||||
|
||||
#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ARM FLOAT16 SUPPORTED */
|
||||
|
||||
#endif /* _ARM_VEC_MATH_F16_H */
|
||||
|
||||
/**
|
||||
*
|
||||
* End of file.
|
||||
*/
|
||||
@@ -1,880 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file basic_math_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BASIC_MATH_FUNCTIONS_H_
|
||||
#define _BASIC_MATH_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup groupMath Basic Math Functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Q7 vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_q7(
|
||||
const q7_t * pSrcA,
|
||||
const q7_t * pSrcB,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q7 vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_q7(
|
||||
const q7_t * pSrcA,
|
||||
const q7_t * pSrcB,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q7 vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_q7(
|
||||
const q7_t * pSrcA,
|
||||
const q7_t * pSrcB,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Multiplies a floating-point vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scale scale factor to be applied
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t scale,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Multiplies a floating-point vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scale scale factor to be applied
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t scale,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Multiplies a Q7 vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scaleFract fractional portion of the scale value
|
||||
* @param[in] shift number of bits to shift the result by
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t scaleFract,
|
||||
int8_t shift,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Multiplies a Q15 vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scaleFract fractional portion of the scale value
|
||||
* @param[in] shift number of bits to shift the result by
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t scaleFract,
|
||||
int8_t shift,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Multiplies a Q31 vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scaleFract fractional portion of the scale value
|
||||
* @param[in] shift number of bits to shift the result by
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t scaleFract,
|
||||
int8_t shift,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q7 vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Dot product of floating-point vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float32_t * result);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Dot product of floating-point vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float64_t * result);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Dot product of Q7 vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_q7(
|
||||
const q7_t * pSrcA,
|
||||
const q7_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
q31_t * result);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Dot product of Q15 vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
q63_t * result);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Dot product of Q31 vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
q63_t * result);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Shifts the elements of a Q7 vector a specified number of bits.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_shift_q7(
|
||||
const q7_t * pSrc,
|
||||
int8_t shiftBits,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Shifts the elements of a Q15 vector a specified number of bits.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_shift_q15(
|
||||
const q15_t * pSrc,
|
||||
int8_t shiftBits,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Shifts the elements of a Q31 vector a specified number of bits.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_shift_q31(
|
||||
const q31_t * pSrc,
|
||||
int8_t shiftBits,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t offset,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t offset,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a Q7 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t offset,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a Q15 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t offset,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a Q31 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t offset,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a Q7 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a Q15 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a Q31 vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise AND of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_and_u16(
|
||||
const uint16_t * pSrcA,
|
||||
const uint16_t * pSrcB,
|
||||
uint16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise AND of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_and_u32(
|
||||
const uint32_t * pSrcA,
|
||||
const uint32_t * pSrcB,
|
||||
uint32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise AND of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_and_u8(
|
||||
const uint8_t * pSrcA,
|
||||
const uint8_t * pSrcB,
|
||||
uint8_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise OR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_or_u16(
|
||||
const uint16_t * pSrcA,
|
||||
const uint16_t * pSrcB,
|
||||
uint16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise OR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_or_u32(
|
||||
const uint32_t * pSrcA,
|
||||
const uint32_t * pSrcB,
|
||||
uint32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise OR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_or_u8(
|
||||
const uint8_t * pSrcA,
|
||||
const uint8_t * pSrcB,
|
||||
uint8_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise NOT of a fixed-point vector.
|
||||
* @param[in] pSrc points to input vector
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_not_u16(
|
||||
const uint16_t * pSrc,
|
||||
uint16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise NOT of a fixed-point vector.
|
||||
* @param[in] pSrc points to input vector
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_not_u32(
|
||||
const uint32_t * pSrc,
|
||||
uint32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise NOT of a fixed-point vector.
|
||||
* @param[in] pSrc points to input vector
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_not_u8(
|
||||
const uint8_t * pSrc,
|
||||
uint8_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise XOR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_xor_u16(
|
||||
const uint16_t * pSrcA,
|
||||
const uint16_t * pSrcB,
|
||||
uint16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise XOR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_xor_u32(
|
||||
const uint32_t * pSrcA,
|
||||
const uint32_t * pSrcB,
|
||||
uint32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Compute the logical bitwise XOR of two fixed-point vectors.
|
||||
* @param[in] pSrcA points to input vector A
|
||||
* @param[in] pSrcB points to input vector B
|
||||
* @param[out] pDst points to output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_xor_u8(
|
||||
const uint8_t * pSrcA,
|
||||
const uint8_t * pSrcB,
|
||||
uint8_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Elementwise floating-point clipping
|
||||
@param[in] pSrc points to input values
|
||||
@param[out] pDst points to output clipped values
|
||||
@param[in] low lower bound
|
||||
@param[in] high higher bound
|
||||
@param[in] numSamples number of samples to clip
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_clip_f32(const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
float32_t low,
|
||||
float32_t high,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
@brief Elementwise fixed-point clipping
|
||||
@param[in] pSrc points to input values
|
||||
@param[out] pDst points to output clipped values
|
||||
@param[in] low lower bound
|
||||
@param[in] high higher bound
|
||||
@param[in] numSamples number of samples to clip
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_clip_q31(const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
q31_t low,
|
||||
q31_t high,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
@brief Elementwise fixed-point clipping
|
||||
@param[in] pSrc points to input values
|
||||
@param[out] pDst points to output clipped values
|
||||
@param[in] low lower bound
|
||||
@param[in] high higher bound
|
||||
@param[in] numSamples number of samples to clip
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_clip_q15(const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
q15_t low,
|
||||
q15_t high,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
@brief Elementwise fixed-point clipping
|
||||
@param[in] pSrc points to input values
|
||||
@param[out] pDst points to output clipped values
|
||||
@param[in] low lower bound
|
||||
@param[in] high higher bound
|
||||
@param[in] numSamples number of samples to clip
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_clip_q7(const q7_t * pSrc,
|
||||
q7_t * pDst,
|
||||
q7_t low,
|
||||
q7_t high,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _BASIC_MATH_FUNCTIONS_H_ */
|
||||
@@ -1,167 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file basic_math_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BASIC_MATH_FUNCTIONS_F16_H_
|
||||
#define _BASIC_MATH_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector addition.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_add_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector subtraction.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_sub_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Multiplies a floating-point vector by a scalar.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] scale scale factor to be applied
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_scale_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t scale,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector absolute value.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[out] pDst points to the output buffer
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_abs_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Adds a constant offset to a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[in] offset is the offset to be added
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_offset_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t offset,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Dot product of floating-point vectors.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[out] result output result returned here
|
||||
*/
|
||||
void arm_dot_prod_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float16_t * result);
|
||||
|
||||
/**
|
||||
* @brief Floating-point vector multiplication.
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
*/
|
||||
void arm_mult_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Negates the elements of a floating-point vector.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] blockSize number of samples in the vector
|
||||
*/
|
||||
void arm_negate_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Elementwise floating-point clipping
|
||||
@param[in] pSrc points to input values
|
||||
@param[out] pDst points to output clipped values
|
||||
@param[in] low lower bound
|
||||
@param[in] high higher bound
|
||||
@param[in] numSamples number of samples to clip
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_clip_f16(const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
float16_t low,
|
||||
float16_t high,
|
||||
uint32_t numSamples);
|
||||
|
||||
#endif /* defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _BASIC_MATH_FUNCTIONS_F16_H_ */
|
||||
@@ -1,89 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file bayes_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BAYES_FUNCTIONS_H_
|
||||
#define _BAYES_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/statistics_functions.h"
|
||||
|
||||
/**
|
||||
* @defgroup groupBayes Bayesian estimators
|
||||
*
|
||||
* Implement the naive gaussian Bayes estimator.
|
||||
* The training must be done from scikit-learn.
|
||||
*
|
||||
* The parameters can be easily
|
||||
* generated from the scikit-learn object. Some examples are given in
|
||||
* DSP/Testing/PatternGeneration/Bayes.py
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Instance structure for Naive Gaussian Bayesian estimator.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
uint32_t numberOfClasses; /**< Number of different classes */
|
||||
const float32_t *theta; /**< Mean values for the Gaussians */
|
||||
const float32_t *sigma; /**< Variances for the Gaussians */
|
||||
const float32_t *classPriors; /**< Class prior probabilities */
|
||||
float32_t epsilon; /**< Additive value to variances */
|
||||
} arm_gaussian_naive_bayes_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Naive Gaussian Bayesian Estimator
|
||||
*
|
||||
* @param[in] S points to a naive bayes instance structure
|
||||
* @param[in] in points to the elements of the input vector.
|
||||
* @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities
|
||||
* @param[out] *pBufferB points to a temporary buffer of length numberOfClasses
|
||||
* @return The predicted class
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S,
|
||||
const float32_t * in,
|
||||
float32_t *pOutputProbabilities,
|
||||
float32_t *pBufferB);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _BAYES_FUNCTIONS_H_ */
|
||||
@@ -1,80 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file bayes_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _BAYES_FUNCTIONS_F16_H_
|
||||
#define _BAYES_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/statistics_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Instance structure for Naive Gaussian Bayesian estimator.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
uint32_t numberOfClasses; /**< Number of different classes */
|
||||
const float16_t *theta; /**< Mean values for the Gaussians */
|
||||
const float16_t *sigma; /**< Variances for the Gaussians */
|
||||
const float16_t *classPriors; /**< Class prior probabilities */
|
||||
float16_t epsilon; /**< Additive value to variances */
|
||||
} arm_gaussian_naive_bayes_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Naive Gaussian Bayesian Estimator
|
||||
*
|
||||
* @param[in] S points to a naive bayes instance structure
|
||||
* @param[in] in points to the elements of the input vector.
|
||||
* @param[out] *pOutputProbabilities points to a buffer of length numberOfClasses containing estimated probabilities
|
||||
* @param[out] *pBufferB points to a temporary buffer of length numberOfClasses
|
||||
* @return The predicted class
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
uint32_t arm_gaussian_naive_bayes_predict_f16(const arm_gaussian_naive_bayes_instance_f16 *S,
|
||||
const float16_t * in,
|
||||
float16_t *pOutputProbabilities,
|
||||
float16_t *pBufferB);
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _BAYES_FUNCTIONS_F16_H_ */
|
||||
@@ -1,345 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file complex_math_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _COMPLEX_MATH_FUNCTIONS_H_
|
||||
#define _COMPLEX_MATH_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
#include "dsp/fast_math_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup groupCmplxMath Complex Math Functions
|
||||
* This set of functions operates on complex data vectors.
|
||||
* The data in the complex arrays is stored in an interleaved fashion
|
||||
* (real, imag, real, imag, ...).
|
||||
* In the API functions, the number of samples in a complex array refers
|
||||
* to the number of complex values; the array contains twice this number of
|
||||
* real values.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex conjugate.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_conj_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Q31 complex conjugate.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_conj_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 complex conjugate.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_conj_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude squared
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_squared_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude squared
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_squared_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 complex magnitude squared
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_squared_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 complex magnitude squared
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_squared_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Q15 complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_fast_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 complex dot product
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
* @param[out] realResult real part of the result returned here
|
||||
* @param[out] imagResult imaginary part of the result returned here
|
||||
*/
|
||||
void arm_cmplx_dot_prod_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
uint32_t numSamples,
|
||||
q31_t * realResult,
|
||||
q31_t * imagResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 complex dot product
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
* @param[out] realResult real part of the result returned here
|
||||
* @param[out] imagResult imaginary part of the result returned here
|
||||
*/
|
||||
void arm_cmplx_dot_prod_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
uint32_t numSamples,
|
||||
q63_t * realResult,
|
||||
q63_t * imagResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex dot product
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
* @param[out] realResult real part of the result returned here
|
||||
* @param[out] imagResult imaginary part of the result returned here
|
||||
*/
|
||||
void arm_cmplx_dot_prod_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
uint32_t numSamples,
|
||||
float32_t * realResult,
|
||||
float32_t * imagResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 complex-by-real multiplication
|
||||
* @param[in] pSrcCmplx points to the complex input vector
|
||||
* @param[in] pSrcReal points to the real input vector
|
||||
* @param[out] pCmplxDst points to the complex output vector
|
||||
* @param[in] numSamples number of samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_real_q15(
|
||||
const q15_t * pSrcCmplx,
|
||||
const q15_t * pSrcReal,
|
||||
q15_t * pCmplxDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 complex-by-real multiplication
|
||||
* @param[in] pSrcCmplx points to the complex input vector
|
||||
* @param[in] pSrcReal points to the real input vector
|
||||
* @param[out] pCmplxDst points to the complex output vector
|
||||
* @param[in] numSamples number of samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_real_q31(
|
||||
const q31_t * pSrcCmplx,
|
||||
const q31_t * pSrcReal,
|
||||
q31_t * pCmplxDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex-by-real multiplication
|
||||
* @param[in] pSrcCmplx points to the complex input vector
|
||||
* @param[in] pSrcReal points to the real input vector
|
||||
* @param[out] pCmplxDst points to the complex output vector
|
||||
* @param[in] numSamples number of samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_real_f32(
|
||||
const float32_t * pSrcCmplx,
|
||||
const float32_t * pSrcReal,
|
||||
float32_t * pCmplxDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Q15 complex-by-complex multiplication
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_cmplx_q15(
|
||||
const q15_t * pSrcA,
|
||||
const q15_t * pSrcB,
|
||||
q15_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 complex-by-complex multiplication
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_cmplx_q31(
|
||||
const q31_t * pSrcA,
|
||||
const q31_t * pSrcB,
|
||||
q31_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex-by-complex multiplication
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_cmplx_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
float32_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex-by-complex multiplication
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_cmplx_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
float64_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_H_ */
|
||||
@@ -1,123 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file complex_math_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_
|
||||
#define _COMPLEX_MATH_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
#include "dsp/fast_math_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex conjugate.
|
||||
* @param[in] pSrc points to the input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_conj_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude squared
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_squared_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex magnitude
|
||||
* @param[in] pSrc points to the complex input vector
|
||||
* @param[out] pDst points to the real output vector
|
||||
* @param[in] numSamples number of complex samples in the input vector
|
||||
*/
|
||||
void arm_cmplx_mag_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex dot product
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
* @param[out] realResult real part of the result returned here
|
||||
* @param[out] imagResult imaginary part of the result returned here
|
||||
*/
|
||||
void arm_cmplx_dot_prod_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
uint32_t numSamples,
|
||||
float16_t * realResult,
|
||||
float16_t * imagResult);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex-by-real multiplication
|
||||
* @param[in] pSrcCmplx points to the complex input vector
|
||||
* @param[in] pSrcReal points to the real input vector
|
||||
* @param[out] pCmplxDst points to the complex output vector
|
||||
* @param[in] numSamples number of samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_real_f16(
|
||||
const float16_t * pSrcCmplx,
|
||||
const float16_t * pSrcReal,
|
||||
float16_t * pCmplxDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex-by-complex multiplication
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[out] pDst points to the output vector
|
||||
* @param[in] numSamples number of complex samples in each vector
|
||||
*/
|
||||
void arm_cmplx_mult_cmplx_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
float16_t * pDst,
|
||||
uint32_t numSamples);
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _COMPLEX_MATH_FUNCTIONS_F16_H_ */
|
||||
@@ -1,793 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file controller_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CONTROLLER_FUNCTIONS_H_
|
||||
#define _CONTROLLER_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Macros required for SINE and COSINE Controller functions
|
||||
*/
|
||||
|
||||
#define CONTROLLER_Q31_SHIFT (32 - 9)
|
||||
/* 1.31(q31) Fixed value of 2/360 */
|
||||
/* -1 to +1 is divided into 360 values so total spacing is (2/360) */
|
||||
#define INPUT_SPACING 0xB60B61
|
||||
|
||||
/**
|
||||
* @defgroup groupController Controller Functions
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
@ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
@defgroup SinCos Sine Cosine
|
||||
|
||||
Computes the trigonometric sine and cosine values using a combination of table lookup
|
||||
and linear interpolation.
|
||||
There are separate functions for Q31 and floating-point data types.
|
||||
The input to the floating-point version is in degrees while the
|
||||
fixed-point Q31 have a scaled input with the range
|
||||
[-1 0.9999] mapping to [-180 +180] degrees.
|
||||
|
||||
The floating point function also allows values that are out of the usual range. When this happens, the function will
|
||||
take extra time to adjust the input value to the range of [-180 180].
|
||||
|
||||
The result is accurate to 5 digits after the decimal point.
|
||||
|
||||
The implementation is based on table lookup using 360 values together with linear interpolation.
|
||||
The steps used are:
|
||||
-# Calculation of the nearest integer table index.
|
||||
-# Compute the fractional portion (fract) of the input.
|
||||
-# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.
|
||||
-# Sine value is computed as <code> *psinVal = y0 + (fract * (y1 - y0))</code>.
|
||||
-# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.
|
||||
-# Cosine value is computed as <code> *pcosVal = y0 + (fract * (y1 - y0))</code>.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Floating-point sin_cos function.
|
||||
* @param[in] theta input value in degrees
|
||||
* @param[out] pSinVal points to the processed sine output.
|
||||
* @param[out] pCosVal points to the processed cos output.
|
||||
*/
|
||||
void arm_sin_cos_f32(
|
||||
float32_t theta,
|
||||
float32_t * pSinVal,
|
||||
float32_t * pCosVal);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q31 sin_cos function.
|
||||
* @param[in] theta scaled input value in degrees
|
||||
* @param[out] pSinVal points to the processed sine output.
|
||||
* @param[out] pCosVal points to the processed cosine output.
|
||||
*/
|
||||
void arm_sin_cos_q31(
|
||||
q31_t theta,
|
||||
q31_t * pSinVal,
|
||||
q31_t * pCosVal);
|
||||
|
||||
|
||||
/**
|
||||
@ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup PID PID Motor Control
|
||||
*
|
||||
* A Proportional Integral Derivative (PID) controller is a generic feedback control
|
||||
* loop mechanism widely used in industrial control systems.
|
||||
* A PID controller is the most commonly used type of feedback controller.
|
||||
*
|
||||
* This set of functions implements (PID) controllers
|
||||
* for Q15, Q31, and floating-point data types. The functions operate on a single sample
|
||||
* of data and each call to the function returns a single processed value.
|
||||
* <code>S</code> points to an instance of the PID control data structure. <code>in</code>
|
||||
* is the input sample value. The functions return the output value.
|
||||
*
|
||||
* \par Algorithm:
|
||||
* <pre>
|
||||
* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
|
||||
* A0 = Kp + Ki + Kd
|
||||
* A1 = (-Kp ) - (2 * Kd )
|
||||
* A2 = Kd
|
||||
* </pre>
|
||||
*
|
||||
* \par
|
||||
* where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
|
||||
*
|
||||
* \par
|
||||
* \image html PID.gif "Proportional Integral Derivative Controller"
|
||||
*
|
||||
* \par
|
||||
* The PID controller calculates an "error" value as the difference between
|
||||
* the measured output and the reference input.
|
||||
* The controller attempts to minimize the error by adjusting the process control inputs.
|
||||
* The proportional value determines the reaction to the current error,
|
||||
* the integral value determines the reaction based on the sum of recent errors,
|
||||
* and the derivative value determines the reaction based on the rate at which the error has been changing.
|
||||
*
|
||||
* \par Instance Structure
|
||||
* The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
|
||||
* A separate instance structure must be defined for each PID Controller.
|
||||
* There are separate instance structure declarations for each of the 3 supported data types.
|
||||
*
|
||||
* \par Reset Functions
|
||||
* There is also an associated reset function for each data type which clears the state array.
|
||||
*
|
||||
* \par Initialization Functions
|
||||
* There is also an associated initialization function for each data type.
|
||||
* The initialization function performs the following operations:
|
||||
* - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
|
||||
* - Zeros out the values in the state buffer.
|
||||
*
|
||||
* \par
|
||||
* Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
|
||||
*
|
||||
* \par Fixed-Point Behavior
|
||||
* Care must be taken when using the fixed-point versions of the PID Controller functions.
|
||||
* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
|
||||
* Refer to the function specific documentation below for usage guidelines.
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup PID
|
||||
* @brief Instance structure for the Q15 PID Control.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
|
||||
#if !defined (ARM_MATH_DSP)
|
||||
q15_t A1; /**< The derived gain A1 = -Kp - 2Kd */
|
||||
q15_t A2; /**< The derived gain A1 = Kd. */
|
||||
#else
|
||||
q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
|
||||
#endif
|
||||
q15_t state[3]; /**< The state array of length 3. */
|
||||
q15_t Kp; /**< The proportional gain. */
|
||||
q15_t Ki; /**< The integral gain. */
|
||||
q15_t Kd; /**< The derivative gain. */
|
||||
} arm_pid_instance_q15;
|
||||
|
||||
/**
|
||||
* @ingroup PID
|
||||
* @brief Instance structure for the Q31 PID Control.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
|
||||
q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
|
||||
q31_t A2; /**< The derived gain, A2 = Kd . */
|
||||
q31_t state[3]; /**< The state array of length 3. */
|
||||
q31_t Kp; /**< The proportional gain. */
|
||||
q31_t Ki; /**< The integral gain. */
|
||||
q31_t Kd; /**< The derivative gain. */
|
||||
} arm_pid_instance_q31;
|
||||
|
||||
/**
|
||||
* @ingroup PID
|
||||
* @brief Instance structure for the floating-point PID Control.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
|
||||
float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
|
||||
float32_t A2; /**< The derived gain, A2 = Kd . */
|
||||
float32_t state[3]; /**< The state array of length 3. */
|
||||
float32_t Kp; /**< The proportional gain. */
|
||||
float32_t Ki; /**< The integral gain. */
|
||||
float32_t Kd; /**< The derivative gain. */
|
||||
} arm_pid_instance_f32;
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the floating-point PID Control.
|
||||
* @param[in,out] S points to an instance of the PID structure.
|
||||
* @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
|
||||
*/
|
||||
void arm_pid_init_f32(
|
||||
arm_pid_instance_f32 * S,
|
||||
int32_t resetStateFlag);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Reset function for the floating-point PID Control.
|
||||
* @param[in,out] S is an instance of the floating-point PID Control structure
|
||||
*/
|
||||
void arm_pid_reset_f32(
|
||||
arm_pid_instance_f32 * S);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the Q31 PID Control.
|
||||
* @param[in,out] S points to an instance of the Q15 PID structure.
|
||||
* @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
|
||||
*/
|
||||
void arm_pid_init_q31(
|
||||
arm_pid_instance_q31 * S,
|
||||
int32_t resetStateFlag);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Reset function for the Q31 PID Control.
|
||||
* @param[in,out] S points to an instance of the Q31 PID Control structure
|
||||
*/
|
||||
|
||||
void arm_pid_reset_q31(
|
||||
arm_pid_instance_q31 * S);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the Q15 PID Control.
|
||||
* @param[in,out] S points to an instance of the Q15 PID structure.
|
||||
* @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
|
||||
*/
|
||||
void arm_pid_init_q15(
|
||||
arm_pid_instance_q15 * S,
|
||||
int32_t resetStateFlag);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Reset function for the Q15 PID Control.
|
||||
* @param[in,out] S points to an instance of the q15 PID Control structure
|
||||
*/
|
||||
void arm_pid_reset_q15(
|
||||
arm_pid_instance_q15 * S);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup PID
|
||||
* @brief Process function for the floating-point PID Control.
|
||||
* @param[in,out] S is an instance of the floating-point PID Control structure
|
||||
* @param[in] in input sample to process
|
||||
* @return processed output sample.
|
||||
*/
|
||||
__STATIC_FORCEINLINE float32_t arm_pid_f32(
|
||||
arm_pid_instance_f32 * S,
|
||||
float32_t in)
|
||||
{
|
||||
float32_t out;
|
||||
|
||||
/* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
|
||||
out = (S->A0 * in) +
|
||||
(S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
|
||||
|
||||
/* Update state */
|
||||
S->state[1] = S->state[0];
|
||||
S->state[0] = in;
|
||||
S->state[2] = out;
|
||||
|
||||
/* return to application */
|
||||
return (out);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
@ingroup PID
|
||||
@brief Process function for the Q31 PID Control.
|
||||
@param[in,out] S points to an instance of the Q31 PID Control structure
|
||||
@param[in] in input sample to process
|
||||
@return processed output sample.
|
||||
|
||||
\par Scaling and Overflow Behavior
|
||||
The function is implemented using an internal 64-bit accumulator.
|
||||
The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
|
||||
Thus, if the accumulator result overflows it wraps around rather than clip.
|
||||
In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
|
||||
After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q31_t arm_pid_q31(
|
||||
arm_pid_instance_q31 * S,
|
||||
q31_t in)
|
||||
{
|
||||
q63_t acc;
|
||||
q31_t out;
|
||||
|
||||
/* acc = A0 * x[n] */
|
||||
acc = (q63_t) S->A0 * in;
|
||||
|
||||
/* acc += A1 * x[n-1] */
|
||||
acc += (q63_t) S->A1 * S->state[0];
|
||||
|
||||
/* acc += A2 * x[n-2] */
|
||||
acc += (q63_t) S->A2 * S->state[1];
|
||||
|
||||
/* convert output to 1.31 format to add y[n-1] */
|
||||
out = (q31_t) (acc >> 31U);
|
||||
|
||||
/* out += y[n-1] */
|
||||
out += S->state[2];
|
||||
|
||||
/* Update state */
|
||||
S->state[1] = S->state[0];
|
||||
S->state[0] = in;
|
||||
S->state[2] = out;
|
||||
|
||||
/* return to application */
|
||||
return (out);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@ingroup PID
|
||||
@brief Process function for the Q15 PID Control.
|
||||
@param[in,out] S points to an instance of the Q15 PID Control structure
|
||||
@param[in] in input sample to process
|
||||
@return processed output sample.
|
||||
|
||||
\par Scaling and Overflow Behavior
|
||||
The function is implemented using a 64-bit internal accumulator.
|
||||
Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
|
||||
The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
|
||||
There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
|
||||
After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
|
||||
Lastly, the accumulator is saturated to yield a result in 1.15 format.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q15_t arm_pid_q15(
|
||||
arm_pid_instance_q15 * S,
|
||||
q15_t in)
|
||||
{
|
||||
q63_t acc;
|
||||
q15_t out;
|
||||
|
||||
#if defined (ARM_MATH_DSP)
|
||||
/* Implementation of PID controller */
|
||||
|
||||
/* acc = A0 * x[n] */
|
||||
acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in);
|
||||
|
||||
/* acc += A1 * x[n-1] + A2 * x[n-2] */
|
||||
acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc);
|
||||
#else
|
||||
/* acc = A0 * x[n] */
|
||||
acc = ((q31_t) S->A0) * in;
|
||||
|
||||
/* acc += A1 * x[n-1] + A2 * x[n-2] */
|
||||
acc += (q31_t) S->A1 * S->state[0];
|
||||
acc += (q31_t) S->A2 * S->state[1];
|
||||
#endif
|
||||
|
||||
/* acc += y[n-1] */
|
||||
acc += (q31_t) S->state[2] << 15;
|
||||
|
||||
/* saturate the output */
|
||||
out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16));
|
||||
|
||||
/* Update state */
|
||||
S->state[1] = S->state[0];
|
||||
S->state[0] = in;
|
||||
S->state[2] = out;
|
||||
|
||||
/* return to application */
|
||||
return (out);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup park Vector Park Transform
|
||||
*
|
||||
* Forward Park transform converts the input two-coordinate vector to flux and torque components.
|
||||
* The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
|
||||
* from the stationary to the moving reference frame and control the spatial relationship between
|
||||
* the stator vector current and rotor flux vector.
|
||||
* If we consider the d axis aligned with the rotor flux, the diagram below shows the
|
||||
* current vector and the relationship from the two reference frames:
|
||||
* \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
|
||||
*
|
||||
* The function operates on a single sample of data and each call to the function returns the processed output.
|
||||
* The library provides separate functions for Q31 and floating-point data types.
|
||||
* \par Algorithm
|
||||
* \image html parkFormula.gif
|
||||
* where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
|
||||
* <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
|
||||
* cosine and sine values of theta (rotor flux position).
|
||||
* \par Fixed-Point Behavior
|
||||
* Care must be taken when using the Q31 version of the Park transform.
|
||||
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
|
||||
* Refer to the function specific documentation below for usage guidelines.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup park
|
||||
* @brief Floating-point Park transform
|
||||
* @param[in] Ialpha input two-phase vector coordinate alpha
|
||||
* @param[in] Ibeta input two-phase vector coordinate beta
|
||||
* @param[out] pId points to output rotor reference frame d
|
||||
* @param[out] pIq points to output rotor reference frame q
|
||||
* @param[in] sinVal sine value of rotation angle theta
|
||||
* @param[in] cosVal cosine value of rotation angle theta
|
||||
* @return none
|
||||
*
|
||||
* The function implements the forward Park transform.
|
||||
*
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_park_f32(
|
||||
float32_t Ialpha,
|
||||
float32_t Ibeta,
|
||||
float32_t * pId,
|
||||
float32_t * pIq,
|
||||
float32_t sinVal,
|
||||
float32_t cosVal)
|
||||
{
|
||||
/* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
|
||||
*pId = Ialpha * cosVal + Ibeta * sinVal;
|
||||
|
||||
/* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
|
||||
*pIq = -Ialpha * sinVal + Ibeta * cosVal;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@ingroup park
|
||||
@brief Park transform for Q31 version
|
||||
@param[in] Ialpha input two-phase vector coordinate alpha
|
||||
@param[in] Ibeta input two-phase vector coordinate beta
|
||||
@param[out] pId points to output rotor reference frame d
|
||||
@param[out] pIq points to output rotor reference frame q
|
||||
@param[in] sinVal sine value of rotation angle theta
|
||||
@param[in] cosVal cosine value of rotation angle theta
|
||||
@return none
|
||||
|
||||
\par Scaling and Overflow Behavior
|
||||
The function is implemented using an internal 32-bit accumulator.
|
||||
The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
|
||||
There is saturation on the addition and subtraction, hence there is no risk of overflow.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_park_q31(
|
||||
q31_t Ialpha,
|
||||
q31_t Ibeta,
|
||||
q31_t * pId,
|
||||
q31_t * pIq,
|
||||
q31_t sinVal,
|
||||
q31_t cosVal)
|
||||
{
|
||||
q31_t product1, product2; /* Temporary variables used to store intermediate results */
|
||||
q31_t product3, product4; /* Temporary variables used to store intermediate results */
|
||||
|
||||
/* Intermediate product is calculated by (Ialpha * cosVal) */
|
||||
product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
|
||||
|
||||
/* Intermediate product is calculated by (Ibeta * sinVal) */
|
||||
product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
|
||||
|
||||
|
||||
/* Intermediate product is calculated by (Ialpha * sinVal) */
|
||||
product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
|
||||
|
||||
/* Intermediate product is calculated by (Ibeta * cosVal) */
|
||||
product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
|
||||
|
||||
/* Calculate pId by adding the two intermediate products 1 and 2 */
|
||||
*pId = __QADD(product1, product2);
|
||||
|
||||
/* Calculate pIq by subtracting the two intermediate products 3 from 4 */
|
||||
*pIq = __QSUB(product4, product3);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup inv_park Vector Inverse Park transform
|
||||
* Inverse Park transform converts the input flux and torque components to two-coordinate vector.
|
||||
*
|
||||
* The function operates on a single sample of data and each call to the function returns the processed output.
|
||||
* The library provides separate functions for Q31 and floating-point data types.
|
||||
* \par Algorithm
|
||||
* \image html parkInvFormula.gif
|
||||
* where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
|
||||
* <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
|
||||
* cosine and sine values of theta (rotor flux position).
|
||||
* \par Fixed-Point Behavior
|
||||
* Care must be taken when using the Q31 version of the Park transform.
|
||||
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
|
||||
* Refer to the function specific documentation below for usage guidelines.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup inv_park
|
||||
* @brief Floating-point Inverse Park transform
|
||||
* @param[in] Id input coordinate of rotor reference frame d
|
||||
* @param[in] Iq input coordinate of rotor reference frame q
|
||||
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
|
||||
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
|
||||
* @param[in] sinVal sine value of rotation angle theta
|
||||
* @param[in] cosVal cosine value of rotation angle theta
|
||||
* @return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_inv_park_f32(
|
||||
float32_t Id,
|
||||
float32_t Iq,
|
||||
float32_t * pIalpha,
|
||||
float32_t * pIbeta,
|
||||
float32_t sinVal,
|
||||
float32_t cosVal)
|
||||
{
|
||||
/* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
|
||||
*pIalpha = Id * cosVal - Iq * sinVal;
|
||||
|
||||
/* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
|
||||
*pIbeta = Id * sinVal + Iq * cosVal;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@ingroup inv_park
|
||||
@brief Inverse Park transform for Q31 version
|
||||
@param[in] Id input coordinate of rotor reference frame d
|
||||
@param[in] Iq input coordinate of rotor reference frame q
|
||||
@param[out] pIalpha points to output two-phase orthogonal vector axis alpha
|
||||
@param[out] pIbeta points to output two-phase orthogonal vector axis beta
|
||||
@param[in] sinVal sine value of rotation angle theta
|
||||
@param[in] cosVal cosine value of rotation angle theta
|
||||
@return none
|
||||
|
||||
@par Scaling and Overflow Behavior
|
||||
The function is implemented using an internal 32-bit accumulator.
|
||||
The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
|
||||
There is saturation on the addition, hence there is no risk of overflow.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_inv_park_q31(
|
||||
q31_t Id,
|
||||
q31_t Iq,
|
||||
q31_t * pIalpha,
|
||||
q31_t * pIbeta,
|
||||
q31_t sinVal,
|
||||
q31_t cosVal)
|
||||
{
|
||||
q31_t product1, product2; /* Temporary variables used to store intermediate results */
|
||||
q31_t product3, product4; /* Temporary variables used to store intermediate results */
|
||||
|
||||
/* Intermediate product is calculated by (Id * cosVal) */
|
||||
product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
|
||||
|
||||
/* Intermediate product is calculated by (Iq * sinVal) */
|
||||
product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
|
||||
|
||||
|
||||
/* Intermediate product is calculated by (Id * sinVal) */
|
||||
product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
|
||||
|
||||
/* Intermediate product is calculated by (Iq * cosVal) */
|
||||
product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
|
||||
|
||||
/* Calculate pIalpha by using the two intermediate products 1 and 2 */
|
||||
*pIalpha = __QSUB(product1, product2);
|
||||
|
||||
/* Calculate pIbeta by using the two intermediate products 3 and 4 */
|
||||
*pIbeta = __QADD(product4, product3);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup clarke Vector Clarke Transform
|
||||
* Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
|
||||
* Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
|
||||
* in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
|
||||
* When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
|
||||
* \image html clarke.gif Stator current space vector and its components in (a,b).
|
||||
* and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
|
||||
* can be calculated using only <code>Ia</code> and <code>Ib</code>.
|
||||
*
|
||||
* The function operates on a single sample of data and each call to the function returns the processed output.
|
||||
* The library provides separate functions for Q31 and floating-point data types.
|
||||
* \par Algorithm
|
||||
* \image html clarkeFormula.gif
|
||||
* where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
|
||||
* <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
|
||||
* \par Fixed-Point Behavior
|
||||
* Care must be taken when using the Q31 version of the Clarke transform.
|
||||
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
|
||||
* Refer to the function specific documentation below for usage guidelines.
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
*
|
||||
* @ingroup clarke
|
||||
* @brief Floating-point Clarke transform
|
||||
* @param[in] Ia input three-phase coordinate <code>a</code>
|
||||
* @param[in] Ib input three-phase coordinate <code>b</code>
|
||||
* @param[out] pIalpha points to output two-phase orthogonal vector axis alpha
|
||||
* @param[out] pIbeta points to output two-phase orthogonal vector axis beta
|
||||
* @return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_clarke_f32(
|
||||
float32_t Ia,
|
||||
float32_t Ib,
|
||||
float32_t * pIalpha,
|
||||
float32_t * pIbeta)
|
||||
{
|
||||
/* Calculate pIalpha using the equation, pIalpha = Ia */
|
||||
*pIalpha = Ia;
|
||||
|
||||
/* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
|
||||
*pIbeta = (0.57735026919f * Ia + 1.15470053838f * Ib);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@ingroup clarke
|
||||
@brief Clarke transform for Q31 version
|
||||
@param[in] Ia input three-phase coordinate <code>a</code>
|
||||
@param[in] Ib input three-phase coordinate <code>b</code>
|
||||
@param[out] pIalpha points to output two-phase orthogonal vector axis alpha
|
||||
@param[out] pIbeta points to output two-phase orthogonal vector axis beta
|
||||
@return none
|
||||
|
||||
\par Scaling and Overflow Behavior
|
||||
The function is implemented using an internal 32-bit accumulator.
|
||||
The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
|
||||
There is saturation on the addition, hence there is no risk of overflow.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_clarke_q31(
|
||||
q31_t Ia,
|
||||
q31_t Ib,
|
||||
q31_t * pIalpha,
|
||||
q31_t * pIbeta)
|
||||
{
|
||||
q31_t product1, product2; /* Temporary variables used to store intermediate results */
|
||||
|
||||
/* Calculating pIalpha from Ia by equation pIalpha = Ia */
|
||||
*pIalpha = Ia;
|
||||
|
||||
/* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
|
||||
product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
|
||||
|
||||
/* Intermediate product is calculated by (2/sqrt(3) * Ib) */
|
||||
product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
|
||||
|
||||
/* pIbeta is calculated by adding the intermediate products */
|
||||
*pIbeta = __QADD(product1, product2);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup groupController
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup inv_clarke Vector Inverse Clarke Transform
|
||||
* Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
|
||||
*
|
||||
* The function operates on a single sample of data and each call to the function returns the processed output.
|
||||
* The library provides separate functions for Q31 and floating-point data types.
|
||||
* \par Algorithm
|
||||
* \image html clarkeInvFormula.gif
|
||||
* where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
|
||||
* <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
|
||||
* \par Fixed-Point Behavior
|
||||
* Care must be taken when using the Q31 version of the Clarke transform.
|
||||
* In particular, the overflow and saturation behavior of the accumulator used must be considered.
|
||||
* Refer to the function specific documentation below for usage guidelines.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @ingroup inv_clarke
|
||||
* @brief Floating-point Inverse Clarke transform
|
||||
* @param[in] Ialpha input two-phase orthogonal vector axis alpha
|
||||
* @param[in] Ibeta input two-phase orthogonal vector axis beta
|
||||
* @param[out] pIa points to output three-phase coordinate <code>a</code>
|
||||
* @param[out] pIb points to output three-phase coordinate <code>b</code>
|
||||
* @return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_inv_clarke_f32(
|
||||
float32_t Ialpha,
|
||||
float32_t Ibeta,
|
||||
float32_t * pIa,
|
||||
float32_t * pIb)
|
||||
{
|
||||
/* Calculating pIa from Ialpha by equation pIa = Ialpha */
|
||||
*pIa = Ialpha;
|
||||
|
||||
/* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
|
||||
*pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@ingroup inv_clarke
|
||||
@brief Inverse Clarke transform for Q31 version
|
||||
@param[in] Ialpha input two-phase orthogonal vector axis alpha
|
||||
@param[in] Ibeta input two-phase orthogonal vector axis beta
|
||||
@param[out] pIa points to output three-phase coordinate <code>a</code>
|
||||
@param[out] pIb points to output three-phase coordinate <code>b</code>
|
||||
@return none
|
||||
|
||||
\par Scaling and Overflow Behavior
|
||||
The function is implemented using an internal 32-bit accumulator.
|
||||
The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
|
||||
There is saturation on the subtraction, hence there is no risk of overflow.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void arm_inv_clarke_q31(
|
||||
q31_t Ialpha,
|
||||
q31_t Ibeta,
|
||||
q31_t * pIa,
|
||||
q31_t * pIb)
|
||||
{
|
||||
q31_t product1, product2; /* Temporary variables used to store intermediate results */
|
||||
|
||||
/* Calculating pIa from Ialpha by equation pIa = Ialpha */
|
||||
*pIa = Ialpha;
|
||||
|
||||
/* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
|
||||
product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
|
||||
|
||||
/* Intermediate product is calculated by (1/sqrt(3) * pIb) */
|
||||
product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
|
||||
|
||||
/* pIb is calculated by subtracting the products */
|
||||
*pIb = __QSUB(product2, product1);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _CONTROLLER_FUNCTIONS_H_ */
|
||||
@@ -1,41 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file controller_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _CONTROLLER_FUNCTIONS_F16_H_
|
||||
#define _CONTROLLER_FUNCTIONS_F16_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _CONTROLLER_FUNCTIONS_F16_H_ */
|
||||
@@ -1,146 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file basic_math_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _DEBUG_FUNCTIONS_H_
|
||||
#define _DEBUG_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/matrix_functions.h"
|
||||
#include "dsp/matrix_functions_f16.h"
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
#define PROW_f16(S,NB) \
|
||||
{ \
|
||||
printf("{%f",(double)(S)[0]); \
|
||||
for(unsigned int i=1;i<(NB) ;i++) \
|
||||
{ \
|
||||
printf(",%f",(double)(S)[i]);\
|
||||
} \
|
||||
printf("}"); \
|
||||
};
|
||||
|
||||
#define PV_f16(S,V,NB)\
|
||||
{ \
|
||||
printf("%s=",(S)); \
|
||||
PROW_f16((V),(NB)); \
|
||||
printf(";\n"); \
|
||||
};
|
||||
|
||||
#define PM_f16(S,M) \
|
||||
{ \
|
||||
printf("%s={",(S)); \
|
||||
for(unsigned int row=0;row<(M)->numRows;row++) \
|
||||
{ \
|
||||
if (row != 0) \
|
||||
{ \
|
||||
printf("\n,"); \
|
||||
} \
|
||||
PROW_f16((M)->pData + row * (M)->numCols, (M)->numCols);\
|
||||
} \
|
||||
printf("};\n"); \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#define PROW_f32(S,NB) \
|
||||
{ \
|
||||
printf("{%f",(double)(S)[0]); \
|
||||
for(unsigned int i=1;i<(NB) ;i++) \
|
||||
{ \
|
||||
printf(",%f",(double)(S)[i]);\
|
||||
} \
|
||||
printf("}"); \
|
||||
};
|
||||
|
||||
#define PV_f32(S,V,NB)\
|
||||
{ \
|
||||
printf("%s=",(S)); \
|
||||
PROW_f32((V),(NB)); \
|
||||
printf(";\n"); \
|
||||
};
|
||||
|
||||
#define PM_f32(S,M) \
|
||||
{ \
|
||||
printf("%s={",(S)); \
|
||||
for(unsigned int row=0;row<(M)->numRows;row++) \
|
||||
{ \
|
||||
if (row != 0) \
|
||||
{ \
|
||||
printf("\n,"); \
|
||||
} \
|
||||
PROW_f32((M)->pData + row * (M)->numCols, (M)->numCols);\
|
||||
} \
|
||||
printf("};\n"); \
|
||||
}
|
||||
|
||||
#define PROW_f64(S,NB) \
|
||||
{ \
|
||||
printf("{%.20g",(double)(S)[0]); \
|
||||
for(unsigned int i=1;i<(NB) ;i++) \
|
||||
{ \
|
||||
printf(",%.20g",(double)(S)[i]);\
|
||||
} \
|
||||
printf("}"); \
|
||||
};
|
||||
|
||||
#define PV_f64(S,V,NB) \
|
||||
{ \
|
||||
printf("%s=",(S)); \
|
||||
PROW_f64((V),(NB));\
|
||||
printf(";\n"); \
|
||||
};
|
||||
|
||||
#define PM_f64(S,M) \
|
||||
{ \
|
||||
printf("%s={",(S)); \
|
||||
for(unsigned int row=0;row<(M)->numRows;row++) \
|
||||
{ \
|
||||
if (row != 0) \
|
||||
{ \
|
||||
printf("\n,"); \
|
||||
} \
|
||||
PROW_f64((M)->pData + row * (M)->numCols, (M)->numCols);\
|
||||
} \
|
||||
printf("};\n"); \
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _DEBUG_FUNCTIONS_H_ */
|
||||
@@ -1,387 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file distance_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _DISTANCE_FUNCTIONS_H_
|
||||
#define _DISTANCE_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/statistics_functions.h"
|
||||
#include "dsp/basic_math_functions.h"
|
||||
#include "dsp/fast_math_functions.h"
|
||||
#include "dsp/matrix_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup groupDistance Distance functions
|
||||
*
|
||||
* Distance functions for use with clustering algorithms.
|
||||
* There are distance functions for float vectors and boolean vectors.
|
||||
*
|
||||
*/
|
||||
|
||||
/* 6.14 bug */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001)
|
||||
|
||||
__attribute__((weak)) float __powisf2(float a, int b);
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Euclidean distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Euclidean distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float64_t arm_euclidean_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Bray-Curtis distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Canberra distance between two vectors
|
||||
*
|
||||
* This function may divide by zero when samples pA[i] and pB[i] are both zero.
|
||||
* The result of the computation will be correct. So the division per zero may be
|
||||
* ignored.
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Chebyshev distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Chebyshev distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float64_t arm_chebyshev_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Cityblock (Manhattan) distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Cityblock (Manhattan) distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float64_t arm_cityblock_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Correlation distance between two vectors
|
||||
*
|
||||
* The input vectors are modified in place !
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Cosine distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Cosine distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float64_t arm_cosine_distance_f64(const float64_t *pA,const float64_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Jensen-Shannon distance between two vectors
|
||||
*
|
||||
* This function is assuming that elements of second vector are > 0
|
||||
* and 0 only when the corresponding element of first vector is 0.
|
||||
* Otherwise the result of the computation does not make sense
|
||||
* and for speed reasons, the cases returning NaN or Infinity are not
|
||||
* managed.
|
||||
*
|
||||
* When the function is computing x log (x / y) with x 0 and y 0,
|
||||
* it will compute the right value (0) but a division per zero will occur
|
||||
* and shoudl be ignored in client code.
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Minkowski distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] n Norm order (>= 2)
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
|
||||
float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Dice distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] order Distance order
|
||||
* @param[in] blockSize Number of samples
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Hamming distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Jaccard distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Kulsinski distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Roger Stanimoto distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Russell-Rao distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Sokal-Michener distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Sokal-Sneath distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
/**
|
||||
* @brief Yule distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector of packed booleans
|
||||
* @param[in] pB Second vector of packed booleans
|
||||
* @param[in] numberOfBools Number of booleans
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools);
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ARM_DTW_SAKOE_CHIBA_WINDOW = 1,
|
||||
/*ARM_DTW_ITAKURA_WINDOW = 2,*/
|
||||
ARM_DTW_SLANTED_BAND_WINDOW = 3
|
||||
} arm_dtw_window;
|
||||
|
||||
/**
|
||||
* @brief Window for dynamic time warping computation
|
||||
* @param[in] windowType Type of window
|
||||
* @param[in] windowSize Window size
|
||||
* @param[in,out] pWindow Window
|
||||
* @return Error if window type not recognized
|
||||
*
|
||||
*/
|
||||
arm_status arm_dtw_init_window_q7(const arm_dtw_window windowType,
|
||||
const int32_t windowSize,
|
||||
arm_matrix_instance_q7 *pWindow);
|
||||
|
||||
/**
|
||||
* @brief Dynamic Time Warping distance
|
||||
* @param[in] pDistance Distance matrix (Query rows * Template columns)
|
||||
* @param[in] pWindow Windowing (can be NULL if no windowing used)
|
||||
* @param[out] pDTW Temporary cost buffer (same size)
|
||||
* @param[out] distance Distance
|
||||
* @return Error in case no path can be found with window constraint
|
||||
*
|
||||
*/
|
||||
|
||||
arm_status arm_dtw_distance_f32(const arm_matrix_instance_f32 *pDistance,
|
||||
const arm_matrix_instance_q7 *pWindow,
|
||||
arm_matrix_instance_f32 *pDTW,
|
||||
float32_t *distance);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Mapping between query and template
|
||||
* @param[in] pDTW Cost matrix (Query rows * Template columns)
|
||||
* @param[out] pPath Warping path in cost matrix 2*(nb rows + nb columns)
|
||||
* @param[out] pathLength Length of path in number of points
|
||||
* @return none
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_dtw_path_f32(const arm_matrix_instance_f32 *pDTW,
|
||||
int16_t *pPath,
|
||||
uint32_t *pathLength);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _DISTANCE_FUNCTIONS_H_ */
|
||||
@@ -1,180 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file distance_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _DISTANCE_FUNCTIONS_F16_H_
|
||||
#define _DISTANCE_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
/* 6.14 bug */
|
||||
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) && (__ARMCC_VERSION < 6150001)
|
||||
/* Defined in minkowski_f32 */
|
||||
__attribute__((weak)) float __powisf2(float a, int b);
|
||||
#endif
|
||||
|
||||
#include "dsp/statistics_functions_f16.h"
|
||||
#include "dsp/basic_math_functions_f16.h"
|
||||
|
||||
#include "dsp/fast_math_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Euclidean distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float16_t arm_euclidean_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Bray-Curtis distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float16_t arm_braycurtis_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Canberra distance between two vectors
|
||||
*
|
||||
* This function may divide by zero when samples pA[i] and pB[i] are both zero.
|
||||
* The result of the computation will be correct. So the division per zero may be
|
||||
* ignored.
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float16_t arm_canberra_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Chebyshev distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float16_t arm_chebyshev_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Cityblock (Manhattan) distance between two vectors
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float16_t arm_cityblock_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Correlation distance between two vectors
|
||||
*
|
||||
* The input vectors are modified in place !
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
float16_t arm_correlation_distance_f16(float16_t *pA,float16_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Cosine distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float16_t arm_cosine_distance_f16(const float16_t *pA,const float16_t *pB, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Jensen-Shannon distance between two vectors
|
||||
*
|
||||
* This function is assuming that elements of second vector are > 0
|
||||
* and 0 only when the corresponding element of first vector is 0.
|
||||
* Otherwise the result of the computation does not make sense
|
||||
* and for speed reasons, the cases returning NaN or Infinity are not
|
||||
* managed.
|
||||
*
|
||||
* When the function is computing x log (x / y) with x 0 and y 0,
|
||||
* it will compute the right value (0) but a division per zero will occur
|
||||
* and shoudl be ignored in client code.
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
float16_t arm_jensenshannon_distance_f16(const float16_t *pA,const float16_t *pB,uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Minkowski distance between two vectors
|
||||
*
|
||||
* @param[in] pA First vector
|
||||
* @param[in] pB Second vector
|
||||
* @param[in] n Norm order (>= 2)
|
||||
* @param[in] blockSize vector length
|
||||
* @return distance
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
|
||||
float16_t arm_minkowski_distance_f16(const float16_t *pA,const float16_t *pB, int32_t order, uint32_t blockSize);
|
||||
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _DISTANCE_FUNCTIONS_F16_H_ */
|
||||
@@ -1,383 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file fast_math_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FAST_MATH_FUNCTIONS_H_
|
||||
#define _FAST_MATH_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
|
||||
#include <math.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Macros required for SINE and COSINE Fast math approximations
|
||||
*/
|
||||
|
||||
#define FAST_MATH_TABLE_SIZE 512
|
||||
#define FAST_MATH_Q31_SHIFT (32 - 10)
|
||||
#define FAST_MATH_Q15_SHIFT (16 - 10)
|
||||
|
||||
#ifndef PI
|
||||
#define PI 3.14159265358979f
|
||||
#endif
|
||||
|
||||
#ifndef PI_F64
|
||||
#define PI_F64 3.14159265358979323846
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup groupFastMath Fast Math Functions
|
||||
* This set of functions provides a fast approximation to sine, cosine, and square root.
|
||||
* As compared to most of the other functions in the CMSIS math library, the fast math functions
|
||||
* operate on individual values and not arrays.
|
||||
* There are separate functions for Q15, Q31, and floating-point data.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric sine function for floating-point data.
|
||||
* @param[in] x input value in radians.
|
||||
* @return sin(x).
|
||||
*/
|
||||
float32_t arm_sin_f32(
|
||||
float32_t x);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric sine function for Q31 data.
|
||||
* @param[in] x Scaled input value in radians.
|
||||
* @return sin(x).
|
||||
*/
|
||||
q31_t arm_sin_q31(
|
||||
q31_t x);
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric sine function for Q15 data.
|
||||
* @param[in] x Scaled input value in radians.
|
||||
* @return sin(x).
|
||||
*/
|
||||
q15_t arm_sin_q15(
|
||||
q15_t x);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric cosine function for floating-point data.
|
||||
* @param[in] x input value in radians.
|
||||
* @return cos(x).
|
||||
*/
|
||||
float32_t arm_cos_f32(
|
||||
float32_t x);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric cosine function for Q31 data.
|
||||
* @param[in] x Scaled input value in radians.
|
||||
* @return cos(x).
|
||||
*/
|
||||
q31_t arm_cos_q31(
|
||||
q31_t x);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fast approximation to the trigonometric cosine function for Q15 data.
|
||||
* @param[in] x Scaled input value in radians.
|
||||
* @return cos(x).
|
||||
*/
|
||||
q15_t arm_cos_q15(
|
||||
q15_t x);
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of log values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vlog_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of log values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vlog_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief q31 vector of log values.
|
||||
* @param[in] pSrc points to the input vector in q31
|
||||
* @param[out] pDst points to the output vector in q5.26
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_vlog_q31(const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief q15 vector of log values.
|
||||
* @param[in] pSrc points to the input vector in q15
|
||||
* @param[out] pDst points to the output vector in q4.11
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @return none
|
||||
*/
|
||||
void arm_vlog_q15(const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of exp values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vexp_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of exp values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vexp_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup SQRT Square Root
|
||||
*
|
||||
* Computes the square root of a number.
|
||||
* There are separate functions for Q15, Q31, and floating-point data types.
|
||||
* The square root function is computed using the Newton-Raphson algorithm.
|
||||
* This is an iterative algorithm of the form:
|
||||
* <pre>
|
||||
* x1 = x0 - f(x0)/f'(x0)
|
||||
* </pre>
|
||||
* where <code>x1</code> is the current estimate,
|
||||
* <code>x0</code> is the previous estimate, and
|
||||
* <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
|
||||
* For the square root function, the algorithm reduces to:
|
||||
* <pre>
|
||||
* x0 = in/2 [initial guess]
|
||||
* x1 = 1/2 * ( x0 + in / x0) [each iteration]
|
||||
* </pre>
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @addtogroup SQRT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point square root function.
|
||||
@param[in] in input value
|
||||
@param[out] pOut square root of input value
|
||||
@return execution status
|
||||
- \ref ARM_MATH_SUCCESS : input value is positive
|
||||
- \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
|
||||
*/
|
||||
__STATIC_FORCEINLINE arm_status arm_sqrt_f32(
|
||||
const float32_t in,
|
||||
float32_t * pOut)
|
||||
{
|
||||
if (in >= 0.0f)
|
||||
{
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
*pOut = __sqrtf(in);
|
||||
#else
|
||||
*pOut = sqrtf(in);
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
__ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
|
||||
#else
|
||||
*pOut = sqrtf(in);
|
||||
#endif
|
||||
|
||||
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
*pOut = _sqrtf(in);
|
||||
#elif defined(__GNUC_PYTHON__)
|
||||
*pOut = sqrtf(in);
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
__ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in));
|
||||
#else
|
||||
*pOut = sqrtf(in);
|
||||
#endif
|
||||
#else
|
||||
*pOut = sqrtf(in);
|
||||
#endif
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
else
|
||||
{
|
||||
*pOut = 0.0f;
|
||||
return (ARM_MATH_ARGUMENT_ERROR);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Q31 square root function.
|
||||
@param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
|
||||
@param[out] pOut points to square root of input value
|
||||
@return execution status
|
||||
- \ref ARM_MATH_SUCCESS : input value is positive
|
||||
- \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
|
||||
*/
|
||||
arm_status arm_sqrt_q31(
|
||||
q31_t in,
|
||||
q31_t * pOut);
|
||||
|
||||
|
||||
/**
|
||||
@brief Q15 square root function.
|
||||
@param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF
|
||||
@param[out] pOut points to square root of input value
|
||||
@return execution status
|
||||
- \ref ARM_MATH_SUCCESS : input value is positive
|
||||
- \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
|
||||
*/
|
||||
arm_status arm_sqrt_q15(
|
||||
q15_t in,
|
||||
q15_t * pOut);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @} end of SQRT group
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Fixed point division
|
||||
@param[in] numerator Numerator
|
||||
@param[in] denominator Denominator
|
||||
@param[out] quotient Quotient value normalized between -1.0 and 1.0
|
||||
@param[out] shift Shift left value to get the unnormalized quotient
|
||||
@return error status
|
||||
|
||||
When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced
|
||||
to the saturated negative or positive value.
|
||||
*/
|
||||
|
||||
arm_status arm_divide_q15(q15_t numerator,
|
||||
q15_t denominator,
|
||||
q15_t *quotient,
|
||||
int16_t *shift);
|
||||
|
||||
/**
|
||||
@brief Fixed point division
|
||||
@param[in] numerator Numerator
|
||||
@param[in] denominator Denominator
|
||||
@param[out] quotient Quotient value normalized between -1.0 and 1.0
|
||||
@param[out] shift Shift left value to get the unnormalized quotient
|
||||
@return error status
|
||||
|
||||
When dividing by 0, an error ARM_MATH_NANINF is returned. And the quotient is forced
|
||||
to the saturated negative or positive value.
|
||||
*/
|
||||
|
||||
arm_status arm_divide_q31(q31_t numerator,
|
||||
q31_t denominator,
|
||||
q31_t *quotient,
|
||||
int16_t *shift);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
|
||||
@param[in] y y coordinate
|
||||
@param[in] x x coordinate
|
||||
@param[out] result Result
|
||||
@return error status.
|
||||
*/
|
||||
arm_status arm_atan2_f32(float32_t y,float32_t x,float32_t *result);
|
||||
|
||||
|
||||
/**
|
||||
@brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
|
||||
@param[in] y y coordinate
|
||||
@param[in] x x coordinate
|
||||
@param[out] result Result in Q2.29
|
||||
@return error status.
|
||||
*/
|
||||
arm_status arm_atan2_q31(q31_t y,q31_t x,q31_t *result);
|
||||
|
||||
/**
|
||||
@brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
|
||||
@param[in] y y coordinate
|
||||
@param[in] x x coordinate
|
||||
@param[out] result Result in Q2.13
|
||||
@return error status.
|
||||
*/
|
||||
arm_status arm_atan2_q15(q15_t y,q15_t x,q15_t *result);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _FAST_MATH_FUNCTIONS_H_ */
|
||||
@@ -1,125 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file fast_math_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FAST_MATH_FUNCTIONS_F16_H_
|
||||
#define _FAST_MATH_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
/* For sqrt_f32 */
|
||||
#include "dsp/fast_math_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @addtogroup SQRT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point square root function.
|
||||
@param[in] in input value
|
||||
@param[out] pOut square root of input value
|
||||
@return execution status
|
||||
- \ref ARM_MATH_SUCCESS : input value is positive
|
||||
- \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
|
||||
*/
|
||||
__STATIC_FORCEINLINE arm_status arm_sqrt_f16(
|
||||
float16_t in,
|
||||
float16_t * pOut)
|
||||
{
|
||||
float32_t r;
|
||||
arm_status status;
|
||||
status=arm_sqrt_f32((float32_t)in,&r);
|
||||
*pOut=(float16_t)r;
|
||||
return(status);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@} end of SQRT group
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of log values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vlog_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of exp values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vexp_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Floating-point vector of inverse values.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_vinverse_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Arc tangent in radian of y/x using sign of x and y to determine right quadrant.
|
||||
@param[in] y y coordinate
|
||||
@param[in] x x coordinate
|
||||
@param[out] result Result
|
||||
@return error status.
|
||||
*/
|
||||
arm_status arm_atan2_f16(float16_t y,float16_t x,float16_t *result);
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _FAST_MATH_FUNCTIONS_F16_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,237 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file filtering_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _FILTERING_FUNCTIONS_F16_H_
|
||||
#define _FILTERING_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point FIR filter.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numTaps; /**< number of filter coefficients in the filter. */
|
||||
float16_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
|
||||
const float16_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
|
||||
} arm_fir_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the floating-point FIR filter.
|
||||
* @param[in,out] S points to an instance of the floating-point FIR filter structure.
|
||||
* @param[in] numTaps Number of filter coefficients in the filter.
|
||||
* @param[in] pCoeffs points to the filter coefficients.
|
||||
* @param[in] pState points to the state buffer.
|
||||
* @param[in] blockSize number of samples that are processed at a time.
|
||||
*/
|
||||
void arm_fir_init_f16(
|
||||
arm_fir_instance_f16 * S,
|
||||
uint16_t numTaps,
|
||||
const float16_t * pCoeffs,
|
||||
float16_t * pState,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Processing function for the floating-point FIR filter.
|
||||
* @param[in] S points to an instance of the floating-point FIR structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data.
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_fir_f16(
|
||||
const arm_fir_instance_f16 * S,
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point Biquad cascade filter.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
|
||||
float16_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
|
||||
const float16_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
|
||||
} arm_biquad_casd_df1_inst_f16;
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
/**
|
||||
* @brief Instance structure for the modified Biquad coefs required by vectorized code.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
float16_t coeffs[12][8]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */
|
||||
} arm_biquad_mod_coef_f16;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Processing function for the floating-point Biquad cascade filter.
|
||||
* @param[in] S points to an instance of the floating-point Biquad cascade structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data.
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_biquad_cascade_df1_f16(
|
||||
const arm_biquad_casd_df1_inst_f16 * S,
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
void arm_biquad_cascade_df1_mve_init_f16(
|
||||
arm_biquad_casd_df1_inst_f16 * S,
|
||||
uint8_t numStages,
|
||||
const float16_t * pCoeffs,
|
||||
arm_biquad_mod_coef_f16 * pCoeffsMod,
|
||||
float16_t * pState);
|
||||
#endif
|
||||
|
||||
void arm_biquad_cascade_df1_init_f16(
|
||||
arm_biquad_casd_df1_inst_f16 * S,
|
||||
uint8_t numStages,
|
||||
const float16_t * pCoeffs,
|
||||
float16_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
|
||||
float16_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
|
||||
const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
|
||||
} arm_biquad_cascade_df2T_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
|
||||
float16_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
|
||||
const float16_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
|
||||
} arm_biquad_cascade_stereo_df2T_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
|
||||
* @param[in] S points to an instance of the filter data structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_biquad_cascade_df2T_f16(
|
||||
const arm_biquad_cascade_df2T_instance_f16 * S,
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
|
||||
* @param[in] S points to an instance of the filter data structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_biquad_cascade_stereo_df2T_f16(
|
||||
const arm_biquad_cascade_stereo_df2T_instance_f16 * S,
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
|
||||
* @param[in,out] S points to an instance of the filter data structure.
|
||||
* @param[in] numStages number of 2nd order stages in the filter.
|
||||
* @param[in] pCoeffs points to the filter coefficients.
|
||||
* @param[in] pState points to the state buffer.
|
||||
*/
|
||||
void arm_biquad_cascade_df2T_init_f16(
|
||||
arm_biquad_cascade_df2T_instance_f16 * S,
|
||||
uint8_t numStages,
|
||||
const float16_t * pCoeffs,
|
||||
float16_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
|
||||
* @param[in,out] S points to an instance of the filter data structure.
|
||||
* @param[in] numStages number of 2nd order stages in the filter.
|
||||
* @param[in] pCoeffs points to the filter coefficients.
|
||||
* @param[in] pState points to the state buffer.
|
||||
*/
|
||||
void arm_biquad_cascade_stereo_df2T_init_f16(
|
||||
arm_biquad_cascade_stereo_df2T_instance_f16 * S,
|
||||
uint8_t numStages,
|
||||
const float16_t * pCoeffs,
|
||||
float16_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Correlation of floating-point sequences.
|
||||
* @param[in] pSrcA points to the first input sequence.
|
||||
* @param[in] srcALen length of the first input sequence.
|
||||
* @param[in] pSrcB points to the second input sequence.
|
||||
* @param[in] srcBLen length of the second input sequence.
|
||||
* @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
|
||||
*/
|
||||
void arm_correlate_f16(
|
||||
const float16_t * pSrcA,
|
||||
uint32_t srcALen,
|
||||
const float16_t * pSrcB,
|
||||
uint32_t srcBLen,
|
||||
float16_t * pDst);
|
||||
|
||||
|
||||
/**
|
||||
@brief Levinson Durbin
|
||||
@param[in] phi autocovariance vector starting with lag 0 (length is nbCoefs + 1)
|
||||
@param[out] a autoregressive coefficients
|
||||
@param[out] err prediction error (variance)
|
||||
@param[in] nbCoefs number of autoregressive coefficients
|
||||
@return none
|
||||
*/
|
||||
void arm_levinson_durbin_f16(const float16_t *phi,
|
||||
float16_t *a,
|
||||
float16_t *err,
|
||||
int nbCoefs);
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _FILTERING_FUNCTIONS_F16_H_ */
|
||||
@@ -1,275 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file interpolation_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _INTERPOLATION_FUNCTIONS_H_
|
||||
#define _INTERPOLATION_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup groupInterpolation Interpolation Functions
|
||||
* These functions perform 1- and 2-dimensional interpolation of data.
|
||||
* Linear interpolation is used for 1-dimensional data and
|
||||
* bilinear interpolation is used for 2-dimensional data.
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point Linear Interpolate function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nValues; /**< nValues */
|
||||
float32_t x1; /**< x1 */
|
||||
float32_t xSpacing; /**< xSpacing */
|
||||
const float32_t *pYData; /**< pointer to the table of Y values */
|
||||
} arm_linear_interp_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point bilinear interpolation function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows in the data table. */
|
||||
uint16_t numCols; /**< number of columns in the data table. */
|
||||
const float32_t *pData; /**< points to the data table. */
|
||||
} arm_bilinear_interp_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q31 bilinear interpolation function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows in the data table. */
|
||||
uint16_t numCols; /**< number of columns in the data table. */
|
||||
const q31_t *pData; /**< points to the data table. */
|
||||
} arm_bilinear_interp_instance_q31;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q15 bilinear interpolation function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows in the data table. */
|
||||
uint16_t numCols; /**< number of columns in the data table. */
|
||||
const q15_t *pData; /**< points to the data table. */
|
||||
} arm_bilinear_interp_instance_q15;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q15 bilinear interpolation function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows in the data table. */
|
||||
uint16_t numCols; /**< number of columns in the data table. */
|
||||
const q7_t *pData; /**< points to the data table. */
|
||||
} arm_bilinear_interp_instance_q7;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Struct for specifying cubic spline type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ARM_SPLINE_NATURAL = 0, /**< Natural spline */
|
||||
ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */
|
||||
} arm_spline_type;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point cubic spline interpolation.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
arm_spline_type type; /**< Type (boundary conditions) */
|
||||
const float32_t * x; /**< x values */
|
||||
const float32_t * y; /**< y values */
|
||||
uint32_t n_x; /**< Number of known data points */
|
||||
float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */
|
||||
} arm_spline_instance_f32;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Processing function for the floating-point cubic spline interpolation.
|
||||
* @param[in] S points to an instance of the floating-point spline structure.
|
||||
* @param[in] xq points to the x values ot the interpolated data points.
|
||||
* @param[out] pDst points to the block of output data.
|
||||
* @param[in] blockSize number of samples of output data.
|
||||
*/
|
||||
void arm_spline_f32(
|
||||
arm_spline_instance_f32 * S,
|
||||
const float32_t * xq,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Initialization function for the floating-point cubic spline interpolation.
|
||||
* @param[in,out] S points to an instance of the floating-point spline structure.
|
||||
* @param[in] type type of cubic spline interpolation (boundary conditions)
|
||||
* @param[in] x points to the x values of the known data points.
|
||||
* @param[in] y points to the y values of the known data points.
|
||||
* @param[in] n number of known data points.
|
||||
* @param[in] coeffs coefficients array for b, c, and d
|
||||
* @param[in] tempBuffer buffer array for internal computations
|
||||
*/
|
||||
void arm_spline_init_f32(
|
||||
arm_spline_instance_f32 * S,
|
||||
arm_spline_type type,
|
||||
const float32_t * x,
|
||||
const float32_t * y,
|
||||
uint32_t n,
|
||||
float32_t * coeffs,
|
||||
float32_t * tempBuffer);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Process function for the floating-point Linear Interpolation Function.
|
||||
* @param[in,out] S is an instance of the floating-point Linear Interpolation structure
|
||||
* @param[in] x input sample to process
|
||||
* @return y processed output sample.
|
||||
*
|
||||
*/
|
||||
float32_t arm_linear_interp_f32(
|
||||
arm_linear_interp_instance_f32 * S,
|
||||
float32_t x);
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Process function for the Q31 Linear Interpolation Function.
|
||||
* @param[in] pYData pointer to Q31 Linear Interpolation table
|
||||
* @param[in] x input sample to process
|
||||
* @param[in] nValues number of table values
|
||||
* @return y processed output sample.
|
||||
*
|
||||
* \par
|
||||
* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
|
||||
* This function can support maximum of table size 2^12.
|
||||
*
|
||||
*/
|
||||
q31_t arm_linear_interp_q31(
|
||||
const q31_t * pYData,
|
||||
q31_t x,
|
||||
uint32_t nValues);
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Process function for the Q15 Linear Interpolation Function.
|
||||
* @param[in] pYData pointer to Q15 Linear Interpolation table
|
||||
* @param[in] x input sample to process
|
||||
* @param[in] nValues number of table values
|
||||
* @return y processed output sample.
|
||||
*
|
||||
* \par
|
||||
* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
|
||||
* This function can support maximum of table size 2^12.
|
||||
*
|
||||
*/
|
||||
q15_t arm_linear_interp_q15(
|
||||
const q15_t * pYData,
|
||||
q31_t x,
|
||||
uint32_t nValues);
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Process function for the Q7 Linear Interpolation Function.
|
||||
* @param[in] pYData pointer to Q7 Linear Interpolation table
|
||||
* @param[in] x input sample to process
|
||||
* @param[in] nValues number of table values
|
||||
* @return y processed output sample.
|
||||
*
|
||||
* \par
|
||||
* Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
|
||||
* This function can support maximum of table size 2^12.
|
||||
*/
|
||||
q7_t arm_linear_interp_q7(
|
||||
const q7_t * pYData,
|
||||
q31_t x,
|
||||
uint32_t nValues);
|
||||
|
||||
/**
|
||||
* @brief Floating-point bilinear interpolation.
|
||||
* @param[in,out] S points to an instance of the interpolation structure.
|
||||
* @param[in] X interpolation coordinate.
|
||||
* @param[in] Y interpolation coordinate.
|
||||
* @return out interpolated value.
|
||||
*/
|
||||
float32_t arm_bilinear_interp_f32(
|
||||
const arm_bilinear_interp_instance_f32 * S,
|
||||
float32_t X,
|
||||
float32_t Y);
|
||||
|
||||
/**
|
||||
* @brief Q31 bilinear interpolation.
|
||||
* @param[in,out] S points to an instance of the interpolation structure.
|
||||
* @param[in] X interpolation coordinate in 12.20 format.
|
||||
* @param[in] Y interpolation coordinate in 12.20 format.
|
||||
* @return out interpolated value.
|
||||
*/
|
||||
q31_t arm_bilinear_interp_q31(
|
||||
arm_bilinear_interp_instance_q31 * S,
|
||||
q31_t X,
|
||||
q31_t Y);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 bilinear interpolation.
|
||||
* @param[in,out] S points to an instance of the interpolation structure.
|
||||
* @param[in] X interpolation coordinate in 12.20 format.
|
||||
* @param[in] Y interpolation coordinate in 12.20 format.
|
||||
* @return out interpolated value.
|
||||
*/
|
||||
q15_t arm_bilinear_interp_q15(
|
||||
arm_bilinear_interp_instance_q15 * S,
|
||||
q31_t X,
|
||||
q31_t Y);
|
||||
|
||||
/**
|
||||
* @brief Q7 bilinear interpolation.
|
||||
* @param[in,out] S points to an instance of the interpolation structure.
|
||||
* @param[in] X interpolation coordinate in 12.20 format.
|
||||
* @param[in] Y interpolation coordinate in 12.20 format.
|
||||
* @return out interpolated value.
|
||||
*/
|
||||
q7_t arm_bilinear_interp_q7(
|
||||
arm_bilinear_interp_instance_q7 * S,
|
||||
q31_t X,
|
||||
q31_t Y);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _INTERPOLATION_FUNCTIONS_H_ */
|
||||
@@ -1,107 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file interpolation_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _INTERPOLATION_FUNCTIONS_F16_H_
|
||||
#define _INTERPOLATION_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nValues; /**< nValues */
|
||||
float16_t x1; /**< x1 */
|
||||
float16_t xSpacing; /**< xSpacing */
|
||||
const float16_t *pYData; /**< pointer to the table of Y values */
|
||||
} arm_linear_interp_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point bilinear interpolation function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows;/**< number of rows in the data table. */
|
||||
uint16_t numCols;/**< number of columns in the data table. */
|
||||
const float16_t *pData; /**< points to the data table. */
|
||||
} arm_bilinear_interp_instance_f16;
|
||||
|
||||
/**
|
||||
* @addtogroup LinearInterpolate
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Process function for the floating-point Linear Interpolation Function.
|
||||
* @param[in,out] S is an instance of the floating-point Linear Interpolation structure
|
||||
* @param[in] x input sample to process
|
||||
* @return y processed output sample.
|
||||
*
|
||||
*/
|
||||
float16_t arm_linear_interp_f16(
|
||||
arm_linear_interp_instance_f16 * S,
|
||||
float16_t x);
|
||||
|
||||
/**
|
||||
* @} end of LinearInterpolate group
|
||||
*/
|
||||
|
||||
/**
|
||||
* @addtogroup BilinearInterpolate
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Floating-point bilinear interpolation.
|
||||
* @param[in,out] S points to an instance of the interpolation structure.
|
||||
* @param[in] X interpolation coordinate.
|
||||
* @param[in] Y interpolation coordinate.
|
||||
* @return out interpolated value.
|
||||
*/
|
||||
float16_t arm_bilinear_interp_f16(
|
||||
const arm_bilinear_interp_instance_f16 * S,
|
||||
float16_t X,
|
||||
float16_t Y);
|
||||
|
||||
|
||||
/**
|
||||
* @} end of BilinearInterpolate group
|
||||
*/
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _INTERPOLATION_FUNCTIONS_F16_H_ */
|
||||
@@ -1,856 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file matrix_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.1
|
||||
* @date 10 August 2022
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MATRIX_FUNCTIONS_H_
|
||||
#define _MATRIX_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup groupMatrix Matrix Functions
|
||||
*
|
||||
* This set of functions provides basic matrix math operations.
|
||||
* The functions operate on matrix data structures. For example,
|
||||
* the type
|
||||
* definition for the floating-point matrix structure is shown
|
||||
* below:
|
||||
* <pre>
|
||||
* typedef struct
|
||||
* {
|
||||
* uint16_t numRows; // number of rows of the matrix.
|
||||
* uint16_t numCols; // number of columns of the matrix.
|
||||
* float32_t *pData; // points to the data of the matrix.
|
||||
* } arm_matrix_instance_f32;
|
||||
* </pre>
|
||||
* There are similar definitions for Q15 and Q31 data types.
|
||||
*
|
||||
* The structure specifies the size of the matrix and then points to
|
||||
* an array of data. The array is of size <code>numRows X numCols</code>
|
||||
* and the values are arranged in row order. That is, the
|
||||
* matrix element (i, j) is stored at:
|
||||
* <pre>
|
||||
* pData[i*numCols + j]
|
||||
* </pre>
|
||||
*
|
||||
* \par Init Functions
|
||||
* There is an associated initialization function for each type of matrix
|
||||
* data structure.
|
||||
* The initialization function sets the values of the internal structure fields.
|
||||
* Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15()
|
||||
* for floating-point, Q31 and Q15 types, respectively.
|
||||
*
|
||||
* \par
|
||||
* Use of the initialization function is optional. However, if initialization function is used
|
||||
* then the instance structure cannot be placed into a const data section.
|
||||
* To place the instance structure in a const data
|
||||
* section, manually initialize the data structure. For example:
|
||||
* <pre>
|
||||
* <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
|
||||
* <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
|
||||
* <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
|
||||
* </pre>
|
||||
* where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
|
||||
* specifies the number of columns, and <code>pData</code> points to the
|
||||
* data array.
|
||||
*
|
||||
* \par Size Checking
|
||||
* By default all of the matrix functions perform size checking on the input and
|
||||
* output matrices. For example, the matrix addition function verifies that the
|
||||
* two input matrices and the output matrix all have the same number of rows and
|
||||
* columns. If the size check fails the functions return:
|
||||
* <pre>
|
||||
* ARM_MATH_SIZE_MISMATCH
|
||||
* </pre>
|
||||
* Otherwise the functions return
|
||||
* <pre>
|
||||
* ARM_MATH_SUCCESS
|
||||
* </pre>
|
||||
* There is some overhead associated with this matrix size checking.
|
||||
* The matrix size checking is enabled via the \#define
|
||||
* <pre>
|
||||
* ARM_MATH_MATRIX_CHECK
|
||||
* </pre>
|
||||
* within the library project settings. By default this macro is defined
|
||||
* and size checking is enabled. By changing the project settings and
|
||||
* undefining this macro size checking is eliminated and the functions
|
||||
* run a bit faster. With size checking disabled the functions always
|
||||
* return <code>ARM_MATH_SUCCESS</code>.
|
||||
*/
|
||||
|
||||
#define DEFAULT_HOUSEHOLDER_THRESHOLD_F64 (1.0e-16)
|
||||
#define DEFAULT_HOUSEHOLDER_THRESHOLD_F32 (1.0e-12f)
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
float32_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
float64_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_f64;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q7 matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
q7_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_q7;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q15 matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
q15_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_q15;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Q31 matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
q31_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_q31;
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix addition.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_add_f32(
|
||||
const arm_matrix_instance_f32 * pSrcA,
|
||||
const arm_matrix_instance_f32 * pSrcB,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix addition.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_add_q15(
|
||||
const arm_matrix_instance_q15 * pSrcA,
|
||||
const arm_matrix_instance_q15 * pSrcB,
|
||||
arm_matrix_instance_q15 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix addition.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_add_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point, complex, matrix multiplication.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_mult_f32(
|
||||
const arm_matrix_instance_f32 * pSrcA,
|
||||
const arm_matrix_instance_f32 * pSrcB,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15, complex, matrix multiplication.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_mult_q15(
|
||||
const arm_matrix_instance_q15 * pSrcA,
|
||||
const arm_matrix_instance_q15 * pSrcB,
|
||||
arm_matrix_instance_q15 * pDst,
|
||||
q15_t * pScratch);
|
||||
|
||||
/**
|
||||
* @brief Q31, complex, matrix multiplication.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_mult_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_f32(
|
||||
const arm_matrix_instance_f32 * pSrc,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_f64(
|
||||
const arm_matrix_instance_f64 * pSrc,
|
||||
arm_matrix_instance_f64 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_trans_f32(
|
||||
const arm_matrix_instance_f32 * pSrc,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_q15(
|
||||
const arm_matrix_instance_q15 * pSrc,
|
||||
arm_matrix_instance_q15 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 complex matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_trans_q15(
|
||||
const arm_matrix_instance_q15 * pSrc,
|
||||
arm_matrix_instance_q15 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q7 matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_q7(
|
||||
const arm_matrix_instance_q7 * pSrc,
|
||||
arm_matrix_instance_q7 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_q31(
|
||||
const arm_matrix_instance_q31 * pSrc,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 complex matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_trans_q31(
|
||||
const arm_matrix_instance_q31 * pSrc,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_f32(
|
||||
const arm_matrix_instance_f32 * pSrcA,
|
||||
const arm_matrix_instance_f32 * pSrcB,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_f64(
|
||||
const arm_matrix_instance_f64 * pSrcA,
|
||||
const arm_matrix_instance_f64 * pSrcB,
|
||||
arm_matrix_instance_f64 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix and vector multiplication
|
||||
* @param[in] pSrcMat points to the input matrix structure
|
||||
* @param[in] pVec points to vector
|
||||
* @param[out] pDst points to output vector
|
||||
*/
|
||||
void arm_mat_vec_mult_f32(
|
||||
const arm_matrix_instance_f32 *pSrcMat,
|
||||
const float32_t *pVec,
|
||||
float32_t *pDst);
|
||||
|
||||
/**
|
||||
* @brief Q7 matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @param[in] pState points to the array for storing intermediate results
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_q7(
|
||||
const arm_matrix_instance_q7 * pSrcA,
|
||||
const arm_matrix_instance_q7 * pSrcB,
|
||||
arm_matrix_instance_q7 * pDst,
|
||||
q7_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Q7 matrix and vector multiplication
|
||||
* @param[in] pSrcMat points to the input matrix structure
|
||||
* @param[in] pVec points to vector
|
||||
* @param[out] pDst points to output vector
|
||||
*/
|
||||
void arm_mat_vec_mult_q7(
|
||||
const arm_matrix_instance_q7 *pSrcMat,
|
||||
const q7_t *pVec,
|
||||
q7_t *pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @param[in] pState points to the array for storing intermediate results
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_q15(
|
||||
const arm_matrix_instance_q15 * pSrcA,
|
||||
const arm_matrix_instance_q15 * pSrcB,
|
||||
arm_matrix_instance_q15 * pDst,
|
||||
q15_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix and vector multiplication
|
||||
* @param[in] pSrcMat points to the input matrix structure
|
||||
* @param[in] pVec points to vector
|
||||
* @param[out] pDst points to output vector
|
||||
*/
|
||||
void arm_mat_vec_mult_q15(
|
||||
const arm_matrix_instance_q15 *pSrcMat,
|
||||
const q15_t *pVec,
|
||||
q15_t *pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @param[in] pState points to the array for storing intermediate results
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_fast_q15(
|
||||
const arm_matrix_instance_q15 * pSrcA,
|
||||
const arm_matrix_instance_q15 * pSrcB,
|
||||
arm_matrix_instance_q15 * pDst,
|
||||
q15_t * pState);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @param[in] pState points to the array for storing intermediate results
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_opt_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst,
|
||||
q31_t *pState);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix and vector multiplication
|
||||
* @param[in] pSrcMat points to the input matrix structure
|
||||
* @param[in] pVec points to vector
|
||||
* @param[out] pDst points to output vector
|
||||
*/
|
||||
void arm_mat_vec_mult_q31(
|
||||
const arm_matrix_instance_q31 *pSrcMat,
|
||||
const q31_t *pVec,
|
||||
q31_t *pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_fast_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix subtraction
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_sub_f32(
|
||||
const arm_matrix_instance_f32 * pSrcA,
|
||||
const arm_matrix_instance_f32 * pSrcB,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix subtraction
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_sub_f64(
|
||||
const arm_matrix_instance_f64 * pSrcA,
|
||||
const arm_matrix_instance_f64 * pSrcB,
|
||||
arm_matrix_instance_f64 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix subtraction
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_sub_q15(
|
||||
const arm_matrix_instance_q15 * pSrcA,
|
||||
const arm_matrix_instance_q15 * pSrcB,
|
||||
arm_matrix_instance_q15 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix subtraction
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_sub_q31(
|
||||
const arm_matrix_instance_q31 * pSrcA,
|
||||
const arm_matrix_instance_q31 * pSrcB,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix scaling.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[in] scale scale factor
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_scale_f32(
|
||||
const arm_matrix_instance_f32 * pSrc,
|
||||
float32_t scale,
|
||||
arm_matrix_instance_f32 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix scaling.
|
||||
* @param[in] pSrc points to input matrix
|
||||
* @param[in] scaleFract fractional portion of the scale factor
|
||||
* @param[in] shift number of bits to shift the result by
|
||||
* @param[out] pDst points to output matrix
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_scale_q15(
|
||||
const arm_matrix_instance_q15 * pSrc,
|
||||
q15_t scaleFract,
|
||||
int32_t shift,
|
||||
arm_matrix_instance_q15 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix scaling.
|
||||
* @param[in] pSrc points to input matrix
|
||||
* @param[in] scaleFract fractional portion of the scale factor
|
||||
* @param[in] shift number of bits to shift the result by
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_scale_q31(
|
||||
const arm_matrix_instance_q31 * pSrc,
|
||||
q31_t scaleFract,
|
||||
int32_t shift,
|
||||
arm_matrix_instance_q31 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Q31 matrix initialization.
|
||||
* @param[in,out] S points to an instance of the floating-point matrix structure.
|
||||
* @param[in] nRows number of rows in the matrix.
|
||||
* @param[in] nColumns number of columns in the matrix.
|
||||
* @param[in] pData points to the matrix data array.
|
||||
*/
|
||||
void arm_mat_init_q31(
|
||||
arm_matrix_instance_q31 * S,
|
||||
uint16_t nRows,
|
||||
uint16_t nColumns,
|
||||
q31_t * pData);
|
||||
|
||||
/**
|
||||
* @brief Q15 matrix initialization.
|
||||
* @param[in,out] S points to an instance of the floating-point matrix structure.
|
||||
* @param[in] nRows number of rows in the matrix.
|
||||
* @param[in] nColumns number of columns in the matrix.
|
||||
* @param[in] pData points to the matrix data array.
|
||||
*/
|
||||
void arm_mat_init_q15(
|
||||
arm_matrix_instance_q15 * S,
|
||||
uint16_t nRows,
|
||||
uint16_t nColumns,
|
||||
q15_t * pData);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix initialization.
|
||||
* @param[in,out] S points to an instance of the floating-point matrix structure.
|
||||
* @param[in] nRows number of rows in the matrix.
|
||||
* @param[in] nColumns number of columns in the matrix.
|
||||
* @param[in] pData points to the matrix data array.
|
||||
*/
|
||||
void arm_mat_init_f32(
|
||||
arm_matrix_instance_f32 * S,
|
||||
uint16_t nRows,
|
||||
uint16_t nColumns,
|
||||
float32_t * pData);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix initialization.
|
||||
* @param[in,out] S points to an instance of the floating-point matrix structure.
|
||||
* @param[in] nRows number of rows in the matrix.
|
||||
* @param[in] nColumns number of columns in the matrix.
|
||||
* @param[in] pData points to the matrix data array.
|
||||
*/
|
||||
void arm_mat_init_f64(
|
||||
arm_matrix_instance_f64 * S,
|
||||
uint16_t nRows,
|
||||
uint16_t nColumns,
|
||||
float64_t * pData);
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix inverse.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
|
||||
*/
|
||||
arm_status arm_mat_inverse_f32(
|
||||
const arm_matrix_instance_f32 * src,
|
||||
arm_matrix_instance_f32 * dst);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix inverse.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
|
||||
*/
|
||||
arm_status arm_mat_inverse_f64(
|
||||
const arm_matrix_instance_f64 * src,
|
||||
arm_matrix_instance_f64 * dst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
|
||||
* If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition.
|
||||
* The decomposition is returning a lower triangular matrix.
|
||||
*/
|
||||
arm_status arm_mat_cholesky_f64(
|
||||
const arm_matrix_instance_f64 * src,
|
||||
arm_matrix_instance_f64 * dst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
|
||||
* If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition.
|
||||
* The decomposition is returning a lower triangular matrix.
|
||||
*/
|
||||
arm_status arm_mat_cholesky_f32(
|
||||
const arm_matrix_instance_f32 * src,
|
||||
arm_matrix_instance_f32 * dst);
|
||||
|
||||
/**
|
||||
* @brief Solve UT . X = A where UT is an upper triangular matrix
|
||||
* @param[in] ut The upper triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of UT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_upper_triangular_f32(
|
||||
const arm_matrix_instance_f32 * ut,
|
||||
const arm_matrix_instance_f32 * a,
|
||||
arm_matrix_instance_f32 * dst);
|
||||
|
||||
/**
|
||||
* @brief Solve LT . X = A where LT is a lower triangular matrix
|
||||
* @param[in] lt The lower triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of LT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_lower_triangular_f32(
|
||||
const arm_matrix_instance_f32 * lt,
|
||||
const arm_matrix_instance_f32 * a,
|
||||
arm_matrix_instance_f32 * dst);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Solve UT . X = A where UT is an upper triangular matrix
|
||||
* @param[in] ut The upper triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of UT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_upper_triangular_f64(
|
||||
const arm_matrix_instance_f64 * ut,
|
||||
const arm_matrix_instance_f64 * a,
|
||||
arm_matrix_instance_f64 * dst);
|
||||
|
||||
/**
|
||||
* @brief Solve LT . X = A where LT is a lower triangular matrix
|
||||
* @param[in] lt The lower triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of LT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_lower_triangular_f64(
|
||||
const arm_matrix_instance_f64 * lt,
|
||||
const arm_matrix_instance_f64 * a,
|
||||
arm_matrix_instance_f64 * dst);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] l points to the instance of the output floating-point triangular matrix structure.
|
||||
* @param[out] d points to the instance of the output floating-point diagonal matrix structure.
|
||||
* @param[out] p points to the instance of the output floating-point permutation vector.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
|
||||
* The decomposition is returning a lower triangular matrix.
|
||||
*/
|
||||
arm_status arm_mat_ldlt_f32(
|
||||
const arm_matrix_instance_f32 * src,
|
||||
arm_matrix_instance_f32 * l,
|
||||
arm_matrix_instance_f32 * d,
|
||||
uint16_t * pp);
|
||||
|
||||
/**
|
||||
* @brief Floating-point LDL decomposition of Symmetric Positive Semi-Definite Matrix.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] l points to the instance of the output floating-point triangular matrix structure.
|
||||
* @param[out] d points to the instance of the output floating-point diagonal matrix structure.
|
||||
* @param[out] p points to the instance of the output floating-point permutation vector.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
|
||||
* The decomposition is returning a lower triangular matrix.
|
||||
*/
|
||||
arm_status arm_mat_ldlt_f64(
|
||||
const arm_matrix_instance_f64 * src,
|
||||
arm_matrix_instance_f64 * l,
|
||||
arm_matrix_instance_f64 * d,
|
||||
uint16_t * pp);
|
||||
|
||||
/**
|
||||
@brief QR decomposition of a m x n floating point matrix with m >= n.
|
||||
@param[in] pSrc points to input matrix structure. The source matrix is modified by the function.
|
||||
@param[in] threshold norm2 threshold.
|
||||
@param[out] pOutR points to output R matrix structure of dimension m x n
|
||||
@param[out] pOutQ points to output Q matrix structure of dimension m x m
|
||||
@param[out] pOutTau points to Householder scaling factors of dimension n
|
||||
@param[inout] pTmpA points to a temporary vector of dimension m.
|
||||
@param[inout] pTmpB points to a temporary vector of dimension n.
|
||||
@return execution status
|
||||
- \ref ARM_MATH_SUCCESS : Operation successful
|
||||
- \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
|
||||
- \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible)
|
||||
*/
|
||||
|
||||
arm_status arm_mat_qr_f32(
|
||||
const arm_matrix_instance_f32 * pSrc,
|
||||
const float32_t threshold,
|
||||
arm_matrix_instance_f32 * pOutR,
|
||||
arm_matrix_instance_f32 * pOutQ,
|
||||
float32_t * pOutTau,
|
||||
float32_t *pTmpA,
|
||||
float32_t *pTmpB
|
||||
);
|
||||
|
||||
/**
|
||||
@brief QR decomposition of a m x n floating point matrix with m >= n.
|
||||
@param[in] pSrc points to input matrix structure. The source matrix is modified by the function.
|
||||
@param[in] threshold norm2 threshold.
|
||||
@param[out] pOutR points to output R matrix structure of dimension m x n
|
||||
@param[out] pOutQ points to output Q matrix structure of dimension m x m
|
||||
@param[out] pOutTau points to Householder scaling factors of dimension n
|
||||
@param[inout] pTmpA points to a temporary vector of dimension m.
|
||||
@param[inout] pTmpB points to a temporary vector of dimension n.
|
||||
@return execution status
|
||||
- \ref ARM_MATH_SUCCESS : Operation successful
|
||||
- \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
|
||||
- \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible)
|
||||
*/
|
||||
|
||||
arm_status arm_mat_qr_f64(
|
||||
const arm_matrix_instance_f64 * pSrc,
|
||||
const float64_t threshold,
|
||||
arm_matrix_instance_f64 * pOutR,
|
||||
arm_matrix_instance_f64 * pOutQ,
|
||||
float64_t * pOutTau,
|
||||
float64_t *pTmpA,
|
||||
float64_t *pTmpB
|
||||
);
|
||||
|
||||
/**
|
||||
@brief Householder transform of a floating point vector.
|
||||
@param[in] pSrc points to the input vector.
|
||||
@param[in] threshold norm2 threshold.
|
||||
@param[in] blockSize dimension of the vector space.
|
||||
@param[outQ] pOut points to the output vector.
|
||||
@return beta return the scaling factor beta
|
||||
*/
|
||||
|
||||
float32_t arm_householder_f32(
|
||||
const float32_t * pSrc,
|
||||
const float32_t threshold,
|
||||
uint32_t blockSize,
|
||||
float32_t * pOut
|
||||
);
|
||||
|
||||
/**
|
||||
@brief Householder transform of a double floating point vector.
|
||||
@param[in] pSrc points to the input vector.
|
||||
@param[in] threshold norm2 threshold.
|
||||
@param[in] blockSize dimension of the vector space.
|
||||
@param[outQ] pOut points to the output vector.
|
||||
@return beta return the scaling factor beta
|
||||
*/
|
||||
|
||||
float64_t arm_householder_f64(
|
||||
const float64_t * pSrc,
|
||||
const float64_t threshold,
|
||||
uint32_t blockSize,
|
||||
float64_t * pOut
|
||||
);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _MATRIX_FUNCTIONS_H_ */
|
||||
@@ -1,263 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file matrix_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MATRIX_FUNCTIONS_F16_H_
|
||||
#define _MATRIX_FUNCTIONS_F16_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
#define DEFAULT_HOUSEHOLDER_THRESHOLD_F16 (1.0e-3f)
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point matrix structure.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t numRows; /**< number of rows of the matrix. */
|
||||
uint16_t numCols; /**< number of columns of the matrix. */
|
||||
float16_t *pData; /**< points to the data of the matrix. */
|
||||
} arm_matrix_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix addition.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_add_f16(
|
||||
const arm_matrix_instance_f16 * pSrcA,
|
||||
const arm_matrix_instance_f16 * pSrcB,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point, complex, matrix multiplication.
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_mult_f16(
|
||||
const arm_matrix_instance_f16 * pSrcA,
|
||||
const arm_matrix_instance_f16 * pSrcB,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_trans_f16(
|
||||
const arm_matrix_instance_f16 * pSrc,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point complex matrix transpose.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
|
||||
* or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_cmplx_trans_f16(
|
||||
const arm_matrix_instance_f16 * pSrc,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix multiplication
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_mult_f16(
|
||||
const arm_matrix_instance_f16 * pSrcA,
|
||||
const arm_matrix_instance_f16 * pSrcB,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
/**
|
||||
* @brief Floating-point matrix and vector multiplication
|
||||
* @param[in] pSrcMat points to the input matrix structure
|
||||
* @param[in] pVec points to vector
|
||||
* @param[out] pDst points to output vector
|
||||
*/
|
||||
void arm_mat_vec_mult_f16(
|
||||
const arm_matrix_instance_f16 *pSrcMat,
|
||||
const float16_t *pVec,
|
||||
float16_t *pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix subtraction
|
||||
* @param[in] pSrcA points to the first input matrix structure
|
||||
* @param[in] pSrcB points to the second input matrix structure
|
||||
* @param[out] pDst points to output matrix structure
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_sub_f16(
|
||||
const arm_matrix_instance_f16 * pSrcA,
|
||||
const arm_matrix_instance_f16 * pSrcB,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix scaling.
|
||||
* @param[in] pSrc points to the input matrix
|
||||
* @param[in] scale scale factor
|
||||
* @param[out] pDst points to the output matrix
|
||||
* @return The function returns either
|
||||
* <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
|
||||
*/
|
||||
arm_status arm_mat_scale_f16(
|
||||
const arm_matrix_instance_f16 * pSrc,
|
||||
float16_t scale,
|
||||
arm_matrix_instance_f16 * pDst);
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix initialization.
|
||||
* @param[in,out] S points to an instance of the floating-point matrix structure.
|
||||
* @param[in] nRows number of rows in the matrix.
|
||||
* @param[in] nColumns number of columns in the matrix.
|
||||
* @param[in] pData points to the matrix data array.
|
||||
*/
|
||||
void arm_mat_init_f16(
|
||||
arm_matrix_instance_f16 * S,
|
||||
uint16_t nRows,
|
||||
uint16_t nColumns,
|
||||
float16_t * pData);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point matrix inverse.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
|
||||
*/
|
||||
arm_status arm_mat_inverse_f16(
|
||||
const arm_matrix_instance_f16 * src,
|
||||
arm_matrix_instance_f16 * dst);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Floating-point Cholesky decomposition of Symmetric Positive Definite Matrix.
|
||||
* @param[in] src points to the instance of the input floating-point matrix structure.
|
||||
* @param[out] dst points to the instance of the output floating-point matrix structure.
|
||||
* @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
|
||||
* If the input matrix does not have a decomposition, then the algorithm terminates and returns error status ARM_MATH_DECOMPOSITION_FAILURE.
|
||||
* If the matrix is ill conditioned or only semi-definite, then it is better using the LDL^t decomposition.
|
||||
* The decomposition is returning a lower triangular matrix.
|
||||
*/
|
||||
arm_status arm_mat_cholesky_f16(
|
||||
const arm_matrix_instance_f16 * src,
|
||||
arm_matrix_instance_f16 * dst);
|
||||
|
||||
/**
|
||||
* @brief Solve UT . X = A where UT is an upper triangular matrix
|
||||
* @param[in] ut The upper triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of UT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_upper_triangular_f16(
|
||||
const arm_matrix_instance_f16 * ut,
|
||||
const arm_matrix_instance_f16 * a,
|
||||
arm_matrix_instance_f16 * dst);
|
||||
|
||||
/**
|
||||
* @brief Solve LT . X = A where LT is a lower triangular matrix
|
||||
* @param[in] lt The lower triangular matrix
|
||||
* @param[in] a The matrix a
|
||||
* @param[out] dst The solution X of LT . X = A
|
||||
* @return The function returns ARM_MATH_SINGULAR, if the system can't be solved.
|
||||
*/
|
||||
arm_status arm_mat_solve_lower_triangular_f16(
|
||||
const arm_matrix_instance_f16 * lt,
|
||||
const arm_matrix_instance_f16 * a,
|
||||
arm_matrix_instance_f16 * dst);
|
||||
|
||||
|
||||
/**
|
||||
@brief QR decomposition of a m x n floating point matrix with m >= n.
|
||||
@param[in] pSrc points to input matrix structure. The source matrix is modified by the function.
|
||||
@param[in] threshold norm2 threshold.
|
||||
@param[out] pOutR points to output R matrix structure of dimension m x n
|
||||
@param[out] pOutQ points to output Q matrix structure of dimension m x m
|
||||
@param[out] pOutTau points to Householder scaling factors of dimension n
|
||||
@param[inout] pTmpA points to a temporary vector of dimension m.
|
||||
@param[inout] pTmpB points to a temporary vector of dimension n.
|
||||
@return execution status
|
||||
- \ref ARM_MATH_SUCCESS : Operation successful
|
||||
- \ref ARM_MATH_SIZE_MISMATCH : Matrix size check failed
|
||||
- \ref ARM_MATH_SINGULAR : Input matrix is found to be singular (non-invertible)
|
||||
*/
|
||||
|
||||
arm_status arm_mat_qr_f16(
|
||||
const arm_matrix_instance_f16 * pSrc,
|
||||
const float16_t threshold,
|
||||
arm_matrix_instance_f16 * pOutR,
|
||||
arm_matrix_instance_f16 * pOutQ,
|
||||
float16_t * pOutTau,
|
||||
float16_t *pTmpA,
|
||||
float16_t *pTmpB
|
||||
);
|
||||
|
||||
/**
|
||||
@brief Householder transform of a half floating point vector.
|
||||
@param[in] pSrc points to the input vector.
|
||||
@param[in] threshold norm2 threshold.
|
||||
@param[in] blockSize dimension of the vector space.
|
||||
@param[outQ] pOut points to the output vector.
|
||||
@return beta return the scaling factor beta
|
||||
*/
|
||||
|
||||
float16_t arm_householder_f16(
|
||||
const float16_t * pSrc,
|
||||
const float16_t threshold,
|
||||
uint32_t blockSize,
|
||||
float16_t * pOut
|
||||
);
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _MATRIX_FUNCTIONS_F16_H_ */
|
||||
@@ -1,640 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file matrix_utils.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.11.0
|
||||
* @date 30 May 2022
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MATRIX_UTILS_H_
|
||||
#define _MATRIX_UTILS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define ELEM(A,ROW,COL) &((A)->pData[(A)->numCols* (ROW) + (COL)])
|
||||
|
||||
#define SCALE_COL_T(T,CAST,A,ROW,v,i) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
T *data = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
const int32_t nb = (A)->numRows - ROW;\
|
||||
\
|
||||
data += i + _numCols * (ROW); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
*data *= CAST v; \
|
||||
data += _numCols; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define COPY_COL_T(T,A,ROW,COL,DST) \
|
||||
{ \
|
||||
uint32_t _row; \
|
||||
T *_pb=DST; \
|
||||
T *_pa = (A)->pData + ROW * (A)->numCols + COL;\
|
||||
for(_row = ROW; _row < (A)->numRows; _row ++) \
|
||||
{ \
|
||||
*_pb++ = *_pa; \
|
||||
_pa += (A)->numCols; \
|
||||
} \
|
||||
}
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define SWAP_ROWS_F16(A,COL,i,j) \
|
||||
{ \
|
||||
int cnt = ((A)->numCols)-(COL); \
|
||||
int32_t _w; \
|
||||
float16_t *data = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
\
|
||||
for(_w=(COL);_w < _numCols; _w+=8) \
|
||||
{ \
|
||||
f16x8_t tmpa,tmpb; \
|
||||
mve_pred16_t p0 = vctp16q(cnt); \
|
||||
\
|
||||
tmpa=vldrhq_z_f16(&data[i*_numCols + _w],p0);\
|
||||
tmpb=vldrhq_z_f16(&data[j*_numCols + _w],p0);\
|
||||
\
|
||||
vstrhq_p(&data[i*_numCols + _w], tmpb, p0); \
|
||||
vstrhq_p(&data[j*_numCols + _w], tmpa, p0); \
|
||||
\
|
||||
cnt -= 8; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SCALE_ROW_F16(A,COL,v,i) \
|
||||
{ \
|
||||
int cnt = ((A)->numCols)-(COL); \
|
||||
int32_t _w; \
|
||||
float16_t *data = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
\
|
||||
for(_w=(COL);_w < _numCols; _w+=8) \
|
||||
{ \
|
||||
f16x8_t tmpa; \
|
||||
mve_pred16_t p0 = vctp16q(cnt); \
|
||||
tmpa = vldrhq_z_f16(&data[i*_numCols + _w],p0);\
|
||||
tmpa = vmulq_n_f16(tmpa,(_Float16)v); \
|
||||
vstrhq_p(&data[i*_numCols + _w], tmpa, p0); \
|
||||
cnt -= 8; \
|
||||
} \
|
||||
\
|
||||
}
|
||||
|
||||
#define MAC_ROW_F16(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
int cnt = ((A)->numCols)-(COL); \
|
||||
int32_t _w; \
|
||||
float16_t *dataA = (A)->pData; \
|
||||
float16_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
\
|
||||
for(_w=(COL);_w < _numCols; _w+=8) \
|
||||
{ \
|
||||
f16x8_t tmpa,tmpb; \
|
||||
mve_pred16_t p0 = vctp16q(cnt); \
|
||||
tmpa = vldrhq_z_f16(&dataA[i*_numCols + _w],p0);\
|
||||
tmpb = vldrhq_z_f16(&dataB[j*_numCols + _w],p0);\
|
||||
tmpa = vfmaq_n_f16(tmpa,tmpb,v); \
|
||||
vstrhq_p(&dataA[i*_numCols + _w], tmpa, p0); \
|
||||
cnt -= 8; \
|
||||
} \
|
||||
\
|
||||
}
|
||||
|
||||
#define MAS_ROW_F16(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
int cnt = ((A)->numCols)-(COL); \
|
||||
int32_t _w; \
|
||||
float16_t *dataA = (A)->pData; \
|
||||
float16_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
f16x8_t vec=vdupq_n_f16(v); \
|
||||
\
|
||||
for(_w=(COL);_w < _numCols; _w+=8) \
|
||||
{ \
|
||||
f16x8_t tmpa,tmpb; \
|
||||
mve_pred16_t p0 = vctp16q(cnt); \
|
||||
tmpa = vldrhq_z_f16(&dataA[i*_numCols + _w],p0);\
|
||||
tmpb = vldrhq_z_f16(&dataB[j*_numCols + _w],p0);\
|
||||
tmpa = vfmsq_f16(tmpa,tmpb,vec); \
|
||||
vstrhq_p(&dataA[i*_numCols + _w], tmpa, p0); \
|
||||
cnt -= 8; \
|
||||
} \
|
||||
\
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
|
||||
#define SWAP_ROWS_F16(A,COL,i,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float16_t *dataI = (A)->pData; \
|
||||
float16_t *dataJ = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols-(COL); \
|
||||
\
|
||||
dataI += i*_numCols + (COL); \
|
||||
dataJ += j*_numCols + (COL); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
float16_t tmp; \
|
||||
tmp = *dataI; \
|
||||
*dataI++ = *dataJ; \
|
||||
*dataJ++ = tmp; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SCALE_ROW_F16(A,COL,v,i) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float16_t *data = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols-(COL); \
|
||||
\
|
||||
data += i*_numCols + (COL); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
*data++ *= (_Float16)v; \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
#define MAC_ROW_F16(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float16_t *dataA = (A)->pData; \
|
||||
float16_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
const int32_t nb = _numCols-(COL); \
|
||||
\
|
||||
dataA += i*_numCols + (COL); \
|
||||
dataB += j*_numCols + (COL); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
*dataA++ += (_Float16)v * (_Float16)*dataB++;\
|
||||
} \
|
||||
}
|
||||
|
||||
#define MAS_ROW_F16(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float16_t *dataA = (A)->pData; \
|
||||
float16_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
const int32_t nb = _numCols-(COL); \
|
||||
\
|
||||
dataA += i*_numCols + (COL); \
|
||||
dataB += j*_numCols + (COL); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
*dataA++ -= (_Float16)v * (_Float16)*dataB++;\
|
||||
} \
|
||||
}
|
||||
|
||||
#endif /*defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
/* Functions with only a scalar version */
|
||||
#define COPY_COL_F16(A,ROW,COL,DST) \
|
||||
COPY_COL_T(float16_t,A,ROW,COL,DST)
|
||||
|
||||
#define SCALE_COL_F16(A,ROW,v,i) \
|
||||
SCALE_COL_T(float16_t,(_Float16),A,ROW,v,i)
|
||||
|
||||
#endif /* defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define SWAP_ROWS_F32(A,COL,i,j) \
|
||||
{ \
|
||||
int cnt = ((A)->numCols)-(COL); \
|
||||
float32_t *data = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
int32_t _w; \
|
||||
\
|
||||
for(_w=(COL);_w < _numCols; _w+=4) \
|
||||
{ \
|
||||
f32x4_t tmpa,tmpb; \
|
||||
mve_pred16_t p0 = vctp32q(cnt); \
|
||||
\
|
||||
tmpa=vldrwq_z_f32(&data[i*_numCols + _w],p0);\
|
||||
tmpb=vldrwq_z_f32(&data[j*_numCols + _w],p0);\
|
||||
\
|
||||
vstrwq_p(&data[i*_numCols + _w], tmpb, p0); \
|
||||
vstrwq_p(&data[j*_numCols + _w], tmpa, p0); \
|
||||
\
|
||||
cnt -= 4; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define MAC_ROW_F32(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
int cnt = ((A)->numCols)-(COL); \
|
||||
float32_t *dataA = (A)->pData; \
|
||||
float32_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
int32_t _w; \
|
||||
\
|
||||
for(_w=(COL);_w < _numCols; _w+=4) \
|
||||
{ \
|
||||
f32x4_t tmpa,tmpb; \
|
||||
mve_pred16_t p0 = vctp32q(cnt); \
|
||||
tmpa = vldrwq_z_f32(&dataA[i*_numCols + _w],p0);\
|
||||
tmpb = vldrwq_z_f32(&dataB[j*_numCols + _w],p0);\
|
||||
tmpa = vfmaq_n_f32(tmpa,tmpb,v); \
|
||||
vstrwq_p(&dataA[i*_numCols + _w], tmpa, p0); \
|
||||
cnt -= 4; \
|
||||
} \
|
||||
\
|
||||
}
|
||||
|
||||
#define MAS_ROW_F32(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
int cnt = ((A)->numCols)-(COL); \
|
||||
float32_t *dataA = (A)->pData; \
|
||||
float32_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
int32_t _w; \
|
||||
f32x4_t vec=vdupq_n_f32(v); \
|
||||
\
|
||||
for(_w=(COL);_w < _numCols; _w+=4) \
|
||||
{ \
|
||||
f32x4_t tmpa,tmpb; \
|
||||
mve_pred16_t p0 = vctp32q(cnt); \
|
||||
tmpa = vldrwq_z_f32(&dataA[i*_numCols + _w],p0);\
|
||||
tmpb = vldrwq_z_f32(&dataB[j*_numCols + _w],p0);\
|
||||
tmpa = vfmsq_f32(tmpa,tmpb,vec); \
|
||||
vstrwq_p(&dataA[i*_numCols + _w], tmpa, p0); \
|
||||
cnt -= 4; \
|
||||
} \
|
||||
\
|
||||
}
|
||||
|
||||
#define SCALE_ROW_F32(A,COL,v,i) \
|
||||
{ \
|
||||
int cnt = ((A)->numCols)-(COL); \
|
||||
float32_t *data = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
int32_t _w; \
|
||||
\
|
||||
for(_w=(COL);_w < _numCols; _w+=4) \
|
||||
{ \
|
||||
f32x4_t tmpa; \
|
||||
mve_pred16_t p0 = vctp32q(cnt); \
|
||||
tmpa = vldrwq_z_f32(&data[i*_numCols + _w],p0);\
|
||||
tmpa = vmulq_n_f32(tmpa,v); \
|
||||
vstrwq_p(&data[i*_numCols + _w], tmpa, p0); \
|
||||
cnt -= 4; \
|
||||
} \
|
||||
\
|
||||
}
|
||||
|
||||
#elif defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define SWAP_ROWS_F32(A,COL,i,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float32_t *dataI = (A)->pData; \
|
||||
float32_t *dataJ = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols - COL; \
|
||||
\
|
||||
dataI += i*_numCols + (COL); \
|
||||
dataJ += j*_numCols + (COL); \
|
||||
\
|
||||
float32_t tmp; \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
tmp = *dataI; \
|
||||
*dataI++ = *dataJ; \
|
||||
*dataJ++ = tmp; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define MAC_ROW_F32(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
float32_t *dataA = (A)->pData; \
|
||||
float32_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols - (COL); \
|
||||
int32_t nbElems; \
|
||||
f32x4_t vec = vdupq_n_f32(v); \
|
||||
\
|
||||
nbElems = nb >> 2; \
|
||||
\
|
||||
dataA += i*_numCols + (COL); \
|
||||
dataB += j*_numCols + (COL); \
|
||||
\
|
||||
while(nbElems>0) \
|
||||
{ \
|
||||
f32x4_t tmpa,tmpb; \
|
||||
tmpa = vld1q_f32(dataA,p0); \
|
||||
tmpb = vld1q_f32(dataB,p0); \
|
||||
tmpa = vmlaq_f32(tmpa,tmpb,vec);\
|
||||
vst1q_f32(dataA, tmpa, p0); \
|
||||
nbElems--; \
|
||||
dataA += 4; \
|
||||
dataB += 4; \
|
||||
} \
|
||||
\
|
||||
nbElems = nb & 3; \
|
||||
while(nbElems > 0) \
|
||||
{ \
|
||||
*dataA++ += v* *dataB++; \
|
||||
nbElems--; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define MAS_ROW_F32(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
float32_t *dataA = (A)->pData; \
|
||||
float32_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols - (COL); \
|
||||
int32_t nbElems; \
|
||||
f32x4_t vec = vdupq_n_f32(v); \
|
||||
\
|
||||
nbElems = nb >> 2; \
|
||||
\
|
||||
dataA += i*_numCols + (COL); \
|
||||
dataB += j*_numCols + (COL); \
|
||||
\
|
||||
while(nbElems>0) \
|
||||
{ \
|
||||
f32x4_t tmpa,tmpb; \
|
||||
tmpa = vld1q_f32(dataA); \
|
||||
tmpb = vld1q_f32(dataB); \
|
||||
tmpa = vmlsq_f32(tmpa,tmpb,vec);\
|
||||
vst1q_f32(dataA, tmpa); \
|
||||
nbElems--; \
|
||||
dataA += 4; \
|
||||
dataB += 4; \
|
||||
} \
|
||||
\
|
||||
nbElems = nb & 3; \
|
||||
while(nbElems > 0) \
|
||||
{ \
|
||||
*dataA++ -= v* *dataB++; \
|
||||
nbElems--; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SCALE_ROW_F32(A,COL,v,i) \
|
||||
{ \
|
||||
float32_t *data = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
const int32_t nb = _numCols - (COL); \
|
||||
int32_t nbElems; \
|
||||
f32x4_t vec = vdupq_n_f32(v); \
|
||||
\
|
||||
nbElems = nb >> 2; \
|
||||
\
|
||||
data += i*_numCols + (COL); \
|
||||
while(nbElems>0) \
|
||||
{ \
|
||||
f32x4_t tmpa; \
|
||||
tmpa = vld1q_f32(data); \
|
||||
tmpa = vmulq_f32(tmpa,vec); \
|
||||
vst1q_f32(data, tmpa); \
|
||||
data += 4; \
|
||||
nbElems --; \
|
||||
} \
|
||||
\
|
||||
nbElems = nb & 3; \
|
||||
while(nbElems > 0) \
|
||||
{ \
|
||||
*data++ *= v; \
|
||||
nbElems--; \
|
||||
} \
|
||||
\
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
#define SWAP_ROWS_F32(A,COL,i,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float32_t tmp; \
|
||||
float32_t *dataI = (A)->pData; \
|
||||
float32_t *dataJ = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols - COL; \
|
||||
\
|
||||
dataI += i*_numCols + (COL); \
|
||||
dataJ += j*_numCols + (COL); \
|
||||
\
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
tmp = *dataI; \
|
||||
*dataI++ = *dataJ; \
|
||||
*dataJ++ = tmp; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SCALE_ROW_F32(A,COL,v,i) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float32_t *data = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols - COL; \
|
||||
\
|
||||
data += i*_numCols + (COL); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
*data++ *= v; \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
#define MAC_ROW_F32(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float32_t *dataA = (A)->pData; \
|
||||
float32_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols-(COL); \
|
||||
\
|
||||
dataA = dataA + i*_numCols + (COL); \
|
||||
dataB = dataB + j*_numCols + (COL); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
*dataA++ += v* *dataB++; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define MAS_ROW_F32(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float32_t *dataA = (A)->pData; \
|
||||
float32_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols-(COL); \
|
||||
\
|
||||
dataA = dataA + i*_numCols + (COL); \
|
||||
dataB = dataB + j*_numCols + (COL); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
*dataA++ -= v* *dataB++; \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
|
||||
/* Functions _with only a scalar version */
|
||||
|
||||
#define COPY_COL_F32(A,ROW,COL,DST) \
|
||||
COPY_COL_T(float32_t,A,ROW,COL,DST)
|
||||
|
||||
#define COPY_COL_F64(A,ROW,COL,DST) \
|
||||
COPY_COL_T(float64_t,A,ROW,COL,DST)
|
||||
|
||||
#define SWAP_COLS_F32(A,COL,i,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float32_t *data = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
for(_w=(COL);_w < _numCols; _w++) \
|
||||
{ \
|
||||
float32_t tmp; \
|
||||
tmp = data[_w*_numCols + i]; \
|
||||
data[_w*_numCols + i] = data[_w*_numCols + j];\
|
||||
data[_w*_numCols + j] = tmp; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SCALE_COL_F32(A,ROW,v,i) \
|
||||
SCALE_COL_T(float32_t,,A,ROW,v,i)
|
||||
|
||||
#define SWAP_ROWS_F64(A,COL,i,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float64_t *dataI = (A)->pData; \
|
||||
float64_t *dataJ = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols-(COL); \
|
||||
\
|
||||
dataI += i*_numCols + (COL); \
|
||||
dataJ += j*_numCols + (COL); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
float64_t tmp; \
|
||||
tmp = *dataI; \
|
||||
*dataI++ = *dataJ; \
|
||||
*dataJ++ = tmp; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SWAP_COLS_F64(A,COL,i,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float64_t *data = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols; \
|
||||
for(_w=(COL);_w < _numCols; _w++) \
|
||||
{ \
|
||||
float64_t tmp; \
|
||||
tmp = data[_w*_numCols + i]; \
|
||||
data[_w*_numCols + i] = data[_w*_numCols + j];\
|
||||
data[_w*_numCols + j] = tmp; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SCALE_ROW_F64(A,COL,v,i) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float64_t *data = (A)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols-(COL); \
|
||||
\
|
||||
data += i*_numCols + (COL); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
*data++ *= v; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define SCALE_COL_F64(A,ROW,v,i) \
|
||||
SCALE_COL_T(float64_t,,A,ROW,v,i)
|
||||
|
||||
#define MAC_ROW_F64(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float64_t *dataA = (A)->pData; \
|
||||
float64_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols-(COL); \
|
||||
\
|
||||
dataA += i*_numCols + (COL); \
|
||||
dataB += j*_numCols + (COL); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
*dataA++ += v* *dataB++; \
|
||||
} \
|
||||
}
|
||||
|
||||
#define MAS_ROW_F64(COL,A,i,v,B,j) \
|
||||
{ \
|
||||
int32_t _w; \
|
||||
float64_t *dataA = (A)->pData; \
|
||||
float64_t *dataB = (B)->pData; \
|
||||
const int32_t _numCols = (A)->numCols;\
|
||||
const int32_t nb = _numCols-(COL); \
|
||||
\
|
||||
dataA += i*_numCols + (COL); \
|
||||
dataB += j*_numCols + (COL); \
|
||||
\
|
||||
for(_w=0;_w < nb; _w++) \
|
||||
{ \
|
||||
*dataA++ -= v* *dataB++; \
|
||||
} \
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _MATRIX_UTILS_H_ */
|
||||
@@ -1,576 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file none.h
|
||||
* @brief Intrinsincs when no DSP extension available
|
||||
* @version V1.9.0
|
||||
* @date 20. July 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
Definitions in this file are allowing to reuse some versions of the
|
||||
CMSIS-DSP to build on a core (M0 for instance) or a host where
|
||||
DSP extension are not available.
|
||||
|
||||
Ideally a pure C version should have been used instead.
|
||||
But those are not always available or use a restricted set
|
||||
of intrinsics.
|
||||
|
||||
*/
|
||||
|
||||
#ifndef _NONE_H_
|
||||
#define _NONE_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*
|
||||
|
||||
Normally those kind of definitions are in a compiler file
|
||||
in Core or Core_A.
|
||||
|
||||
But for MSVC compiler it is a bit special. The goal is very specific
|
||||
to CMSIS-DSP and only to allow the use of this library from other
|
||||
systems like Python or Matlab.
|
||||
|
||||
MSVC is not going to be used to cross-compile to ARM. So, having a MSVC
|
||||
compiler file in Core or Core_A would not make sense.
|
||||
|
||||
*/
|
||||
#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) || defined(__APPLE_CC__)
|
||||
__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data)
|
||||
{
|
||||
if (data == 0U) { return 32U; }
|
||||
|
||||
uint32_t count = 0U;
|
||||
uint32_t mask = 0x80000000U;
|
||||
|
||||
while ((data & mask) == 0U)
|
||||
{
|
||||
count += 1U;
|
||||
mask = mask >> 1U;
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
op2 %= 32U;
|
||||
if (op2 == 0U)
|
||||
{
|
||||
return op1;
|
||||
}
|
||||
return (op1 >> op2) | (op1 << (32U - op2));
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Clips Q63 to Q31 values.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q31_t clip_q63_to_q31(
|
||||
q63_t x)
|
||||
{
|
||||
return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
|
||||
((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clips Q63 to Q15 values.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q15_t clip_q63_to_q15(
|
||||
q63_t x)
|
||||
{
|
||||
return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
|
||||
((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clips Q31 to Q7 values.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q7_t clip_q31_to_q7(
|
||||
q31_t x)
|
||||
{
|
||||
return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
|
||||
((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clips Q31 to Q15 values.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q15_t clip_q31_to_q15(
|
||||
q31_t x)
|
||||
{
|
||||
return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
|
||||
((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
|
||||
*/
|
||||
__STATIC_FORCEINLINE q63_t mult32x64(
|
||||
q63_t x,
|
||||
q31_t y)
|
||||
{
|
||||
return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
|
||||
(((q63_t) (x >> 32) * y) ) );
|
||||
}
|
||||
|
||||
/* SMMLAR */
|
||||
#define multAcc_32x32_keep32_R(a, x, y) \
|
||||
a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
|
||||
|
||||
/* SMMLSR */
|
||||
#define multSub_32x32_keep32_R(a, x, y) \
|
||||
a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
|
||||
|
||||
/* SMMULR */
|
||||
#define mult_32x32_keep32_R(a, x, y) \
|
||||
a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
|
||||
|
||||
/* SMMLA */
|
||||
#define multAcc_32x32_keep32(a, x, y) \
|
||||
a += (q31_t) (((q63_t) x * y) >> 32)
|
||||
|
||||
/* SMMLS */
|
||||
#define multSub_32x32_keep32(a, x, y) \
|
||||
a -= (q31_t) (((q63_t) x * y) >> 32)
|
||||
|
||||
/* SMMUL */
|
||||
#define mult_32x32_keep32(a, x, y) \
|
||||
a = (q31_t) (((q63_t) x * y ) >> 32)
|
||||
|
||||
#ifndef ARM_MATH_DSP
|
||||
/**
|
||||
* @brief definition to pack two 16 bit values.
|
||||
*/
|
||||
#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
|
||||
(((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
|
||||
#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
|
||||
(((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief definition to pack four 8 bit values.
|
||||
*/
|
||||
#ifndef ARM_MATH_BIG_ENDIAN
|
||||
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
|
||||
(((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
|
||||
(((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
|
||||
(((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
|
||||
#else
|
||||
#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
|
||||
(((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
|
||||
(((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
|
||||
(((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined intrinsic functions
|
||||
*/
|
||||
#if !defined (ARM_MATH_DSP)
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QADD8
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QADD8(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s, t, u;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
|
||||
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QSUB8
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QSUB8(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s, t, u;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF;
|
||||
|
||||
return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QADD16
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QADD16(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */
|
||||
q31_t r = 0, s = 0;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SHADD16
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SHADD16(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QSUB16
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QSUB16(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SHSUB16
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SHSUB16(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QASX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QASX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SHASX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SHASX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QSAX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __QSAX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SHSAX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SHSAX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
q31_t r, s;
|
||||
|
||||
r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF;
|
||||
|
||||
return ((uint32_t)((s << 16) | (r )));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMUSDX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMUSDX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMUADX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMUADX(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QADD
|
||||
*/
|
||||
__STATIC_FORCEINLINE int32_t __QADD(
|
||||
int32_t x,
|
||||
int32_t y)
|
||||
{
|
||||
return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y)));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined QSUB
|
||||
*/
|
||||
__STATIC_FORCEINLINE int32_t __QSUB(
|
||||
int32_t x,
|
||||
int32_t y)
|
||||
{
|
||||
return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y)));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMLAD
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMLAD(
|
||||
uint32_t x,
|
||||
uint32_t y,
|
||||
uint32_t sum)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
|
||||
( ((q31_t)sum ) ) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMLADX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMLADX(
|
||||
uint32_t x,
|
||||
uint32_t y,
|
||||
uint32_t sum)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
( ((q31_t)sum ) ) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMLSDX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMLSDX(
|
||||
uint32_t x,
|
||||
uint32_t y,
|
||||
uint32_t sum)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) -
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
( ((q31_t)sum ) ) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMLALD
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint64_t __SMLALD(
|
||||
uint32_t x,
|
||||
uint32_t y,
|
||||
uint64_t sum)
|
||||
{
|
||||
/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */
|
||||
return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) +
|
||||
( ((q63_t)sum ) ) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMLALDX
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint64_t __SMLALDX(
|
||||
uint32_t x,
|
||||
uint32_t y,
|
||||
uint64_t sum)
|
||||
{
|
||||
/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */
|
||||
return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
( ((q63_t)sum ) ) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMUAD
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMUAD(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) +
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMUSD
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SMUSD(
|
||||
uint32_t x,
|
||||
uint32_t y)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) -
|
||||
((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) ));
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* @brief C custom defined SXTB16
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t __SXTB16(
|
||||
uint32_t x)
|
||||
{
|
||||
return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) |
|
||||
((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) ));
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief C custom defined SMMLA
|
||||
*/
|
||||
__STATIC_FORCEINLINE int32_t __SMMLA(
|
||||
int32_t x,
|
||||
int32_t y,
|
||||
int32_t sum)
|
||||
{
|
||||
return (sum + (int32_t) (((int64_t) x * y) >> 32));
|
||||
}
|
||||
|
||||
#endif /* !defined (ARM_MATH_DSP) */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _TRANSFORM_FUNCTIONS_H_ */
|
||||
@@ -1,159 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file quaternion_math_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _QUATERNION_MATH_FUNCTIONS_H_
|
||||
#define _QUATERNION_MATH_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup groupQuaternionMath Quaternion Math Functions
|
||||
* Functions to operates on quaternions and convert between a
|
||||
* rotation and quaternion representation.
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point quaternion Norm.
|
||||
@param[in] pInputQuaternions points to the input vector of quaternions
|
||||
@param[out] pNorms points to the output vector of norms
|
||||
@param[in] nbQuaternions number of quaternions in each vector
|
||||
@return none
|
||||
*/
|
||||
|
||||
|
||||
|
||||
void arm_quaternion_norm_f32(const float32_t *pInputQuaternions,
|
||||
float32_t *pNorms,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point quaternion inverse.
|
||||
@param[in] pInputQuaternions points to the input vector of quaternions
|
||||
@param[out] pInverseQuaternions points to the output vector of inverse quaternions
|
||||
@param[in] nbQuaternions number of quaternions in each vector
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_quaternion_inverse_f32(const float32_t *pInputQuaternions,
|
||||
float32_t *pInverseQuaternions,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
/**
|
||||
@brief Floating-point quaternion conjugates.
|
||||
@param[in] pInputQuaternions points to the input vector of quaternions
|
||||
@param[out] pConjugateQuaternions points to the output vector of conjugate quaternions
|
||||
@param[in] nbQuaternions number of quaternions in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_quaternion_conjugate_f32(const float32_t *inputQuaternions,
|
||||
float32_t *pConjugateQuaternions,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
/**
|
||||
@brief Floating-point normalization of quaternions.
|
||||
@param[in] pInputQuaternions points to the input vector of quaternions
|
||||
@param[out] pNormalizedQuaternions points to the output vector of normalized quaternions
|
||||
@param[in] nbQuaternions number of quaternions in each vector
|
||||
@return none
|
||||
*/
|
||||
void arm_quaternion_normalize_f32(const float32_t *inputQuaternions,
|
||||
float32_t *pNormalizedQuaternions,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
|
||||
/**
|
||||
@brief Floating-point product of two quaternions.
|
||||
@param[in] qa First quaternion
|
||||
@param[in] qb Second quaternion
|
||||
@param[out] r Product of two quaternions
|
||||
@return none
|
||||
*/
|
||||
void arm_quaternion_product_single_f32(const float32_t *qa,
|
||||
const float32_t *qb,
|
||||
float32_t *r);
|
||||
|
||||
/**
|
||||
@brief Floating-point elementwise product two quaternions.
|
||||
@param[in] qa First array of quaternions
|
||||
@param[in] qb Second array of quaternions
|
||||
@param[out] r Elementwise product of quaternions
|
||||
@param[in] nbQuaternions Number of quaternions in the array
|
||||
@return none
|
||||
*/
|
||||
void arm_quaternion_product_f32(const float32_t *qa,
|
||||
const float32_t *qb,
|
||||
float32_t *r,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
/**
|
||||
* @brief Conversion of quaternion to equivalent rotation matrix.
|
||||
* @param[in] pInputQuaternions points to an array of normalized quaternions
|
||||
* @param[out] pOutputRotations points to an array of 3x3 rotations (in row order)
|
||||
* @param[in] nbQuaternions in the array
|
||||
* @return none.
|
||||
*
|
||||
* <b>Format of rotation matrix</b>
|
||||
* \par
|
||||
* The quaternion a + ib + jc + kd is converted into rotation matrix:
|
||||
* a^2 + b^2 - c^2 - d^2 2bc - 2ad 2bd + 2ac
|
||||
* 2bc + 2ad a^2 - b^2 + c^2 - d^2 2cd - 2ab
|
||||
* 2bd - 2ac 2cd + 2ab a^2 - b^2 - c^2 + d^2
|
||||
*
|
||||
* Rotation matrix is saved in row order : R00 R01 R02 R10 R11 R12 R20 R21 R22
|
||||
*/
|
||||
void arm_quaternion2rotation_f32(const float32_t *pInputQuaternions,
|
||||
float32_t *pOutputRotations,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
/**
|
||||
* @brief Conversion of a rotation matrix to equivalent quaternion.
|
||||
* @param[in] pInputRotations points to an array 3x3 rotation matrix (in row order)
|
||||
* @param[out] pOutputQuaternions points to an array of quaternions
|
||||
* @param[in] nbQuaternions in the array
|
||||
* @return none.
|
||||
*/
|
||||
void arm_rotation2quaternion_f32(const float32_t *pInputRotations,
|
||||
float32_t *pOutputQuaternions,
|
||||
uint32_t nbQuaternions);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _QUATERNION_MATH_FUNCTIONS_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,279 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file statistics_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.1
|
||||
* @date 14 July 2022
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _STATISTICS_FUNCTIONS_F16_H_
|
||||
#define _STATISTICS_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/basic_math_functions_f16.h"
|
||||
#include "dsp/fast_math_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Sum of the squares of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_power_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Mean value of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_mean_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Variance of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_var_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Root Mean Square of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_rms_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Standard deviation of the elements of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_std_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[out] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_min_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
* @param[out] pIndex is the array index of the minimum value in the input buffer.
|
||||
*/
|
||||
void arm_absmin_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_max_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
* @param[out] pIndex index of maximum value returned here
|
||||
*/
|
||||
void arm_absmax_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult,
|
||||
uint32_t * pIndex);
|
||||
|
||||
/**
|
||||
* @brief Minimum value of absolute values of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output pointer
|
||||
*/
|
||||
void arm_absmin_no_idx_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief Maximum value of a floating-point vector.
|
||||
* @param[in] pSrc points to the input buffer
|
||||
* @param[in] blockSize length of the input vector
|
||||
* @param[out] pResult maximum value returned here
|
||||
*/
|
||||
void arm_absmax_no_idx_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Entropy
|
||||
*
|
||||
* @param[in] pSrcA Array of input values.
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Entropy -Sum(p ln p)
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
float16_t arm_entropy_f16(const float16_t * pSrcA,uint32_t blockSize);
|
||||
|
||||
float16_t arm_logsumexp_f16(const float16_t *in, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Dot product with log arithmetic
|
||||
*
|
||||
* Vectors are containing the log of the samples
|
||||
*
|
||||
* @param[in] pSrcA points to the first input vector
|
||||
* @param[in] pSrcB points to the second input vector
|
||||
* @param[in] blockSize number of samples in each vector
|
||||
* @param[in] pTmpBuffer temporary buffer of length blockSize
|
||||
* @return The log of the dot product .
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
float16_t arm_logsumexp_dot_prod_f16(const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float16_t *pTmpBuffer);
|
||||
|
||||
/**
|
||||
* @brief Kullback-Leibler
|
||||
*
|
||||
* @param[in] pSrcA Pointer to an array of input values for probability distribution A.
|
||||
* @param[in] pSrcB Pointer to an array of input values for probability distribution B.
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Kullback-Leibler Divergence D(A || B)
|
||||
*
|
||||
*/
|
||||
float16_t arm_kullback_leibler_f16(const float16_t * pSrcA
|
||||
,const float16_t * pSrcB
|
||||
,uint32_t blockSize);
|
||||
|
||||
/**
|
||||
@brief Maximum value of a floating-point vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult maximum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_max_no_idx_f16(
|
||||
const float16_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Minimum value of a floating-point vector.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult minimum value returned here
|
||||
@return none
|
||||
*/
|
||||
void arm_min_no_idx_f16(
|
||||
const float16_t *pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t *pResult);
|
||||
|
||||
/**
|
||||
@brief Mean square error between two half precision float vectors.
|
||||
@param[in] pSrcA points to the first input vector
|
||||
@param[in] pSrcB points to the second input vector
|
||||
@param[in] blockSize number of samples in input vector
|
||||
@param[out] pResult mean square error
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_mse_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sum value of a floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
* @param[out] pResult is output value.
|
||||
*/
|
||||
void arm_accumulate_f16(
|
||||
const float16_t * pSrc,
|
||||
uint32_t blockSize,
|
||||
float16_t * pResult);
|
||||
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _STATISTICS_FUNCTIONS_F16_H_ */
|
||||
@@ -1,540 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file support_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.1
|
||||
* @date 18 August 2022
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SUPPORT_FUNCTIONS_H_
|
||||
#define _SUPPORT_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup groupSupport Support Functions
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the 64 bit floating-point vector to floating-point vector.
|
||||
* @param[in] pSrc points to the floating-point 64 input vector
|
||||
* @param[out] pDst points to the floating-point output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_f64_to_float(
|
||||
const float64_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the 64 bit floating-point vector to Q31 vector.
|
||||
* @param[in] pSrc points to the floating-point 64 input vector
|
||||
* @param[out] pDst points to the Q31 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_f64_to_q31(
|
||||
const float64_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the 64 bit floating-point vector to Q15 vector.
|
||||
* @param[in] pSrc points to the floating-point 64 input vector
|
||||
* @param[out] pDst points to the Q15 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_f64_to_q15(
|
||||
const float64_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the 64 bit floating-point vector to Q7 vector.
|
||||
* @param[in] pSrc points to the floating-point 64 input vector
|
||||
* @param[out] pDst points to the Q7 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_f64_to_q7(
|
||||
const float64_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to 64 bit floating-point vector.
|
||||
* @param[in] pSrc points to the floating-point input vector
|
||||
* @param[out] pDst points to the 64 bit floating-point output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_float_to_f64(
|
||||
const float32_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q31 vector.
|
||||
* @param[in] pSrc points to the floating-point input vector
|
||||
* @param[out] pDst points to the Q31 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_float_to_q31(
|
||||
const float32_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q15 vector.
|
||||
* @param[in] pSrc points to the floating-point input vector
|
||||
* @param[out] pDst points to the Q15 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_float_to_q15(
|
||||
const float32_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q7 vector.
|
||||
* @param[in] pSrc points to the floating-point input vector
|
||||
* @param[out] pDst points to the Q7 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_float_to_q7(
|
||||
const float32_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q31 vector to 64 bit floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q31_to_f64(
|
||||
const q31_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q31 vector to floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q31_to_float(
|
||||
const q31_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q31 vector to Q15 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q31_to_q15(
|
||||
const q31_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q31 vector to Q7 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q31_to_q7(
|
||||
const q31_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q15 vector to 64 bit floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q15_to_f64(
|
||||
const q15_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q15 vector to floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q15_to_float(
|
||||
const q15_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q15 vector to Q31 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q15_to_q31(
|
||||
const q15_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q15 vector to Q7 vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q15_to_q7(
|
||||
const q15_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q7 vector to 64 bit floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q7_to_f64(
|
||||
const q7_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q7 vector to floating-point vector.
|
||||
* @param[in] pSrc is input pointer
|
||||
* @param[out] pDst is output pointer
|
||||
* @param[in] blockSize is the number of samples to process
|
||||
*/
|
||||
void arm_q7_to_float(
|
||||
const q7_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q7 vector to Q31 vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_q7_to_q31(
|
||||
const q7_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the Q7 vector to Q15 vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_q7_to_q15(
|
||||
const q7_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Struct for specifying sorting algorithm
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ARM_SORT_BITONIC = 0,
|
||||
/**< Bitonic sort */
|
||||
ARM_SORT_BUBBLE = 1,
|
||||
/**< Bubble sort */
|
||||
ARM_SORT_HEAP = 2,
|
||||
/**< Heap sort */
|
||||
ARM_SORT_INSERTION = 3,
|
||||
/**< Insertion sort */
|
||||
ARM_SORT_QUICK = 4,
|
||||
/**< Quick sort */
|
||||
ARM_SORT_SELECTION = 5
|
||||
/**< Selection sort */
|
||||
} arm_sort_alg;
|
||||
|
||||
/**
|
||||
* @brief Struct for specifying sorting algorithm
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ARM_SORT_DESCENDING = 0,
|
||||
/**< Descending order (9 to 0) */
|
||||
ARM_SORT_ASCENDING = 1
|
||||
/**< Ascending order (0 to 9) */
|
||||
} arm_sort_dir;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the sorting algorithms.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
arm_sort_alg alg; /**< Sorting algorithm selected */
|
||||
arm_sort_dir dir; /**< Sorting order (direction) */
|
||||
} arm_sort_instance_f32;
|
||||
|
||||
/**
|
||||
* @param[in] S points to an instance of the sorting structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data.
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_sort_f32(
|
||||
const arm_sort_instance_f32 * S,
|
||||
float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @param[in,out] S points to an instance of the sorting structure.
|
||||
* @param[in] alg Selected algorithm.
|
||||
* @param[in] dir Sorting order.
|
||||
*/
|
||||
void arm_sort_init_f32(
|
||||
arm_sort_instance_f32 * S,
|
||||
arm_sort_alg alg,
|
||||
arm_sort_dir dir);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the sorting algorithms.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
arm_sort_dir dir; /**< Sorting order (direction) */
|
||||
float32_t * buffer; /**< Working buffer */
|
||||
} arm_merge_sort_instance_f32;
|
||||
|
||||
/**
|
||||
* @param[in] S points to an instance of the sorting structure.
|
||||
* @param[in,out] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_merge_sort_f32(
|
||||
const arm_merge_sort_instance_f32 * S,
|
||||
float32_t *pSrc,
|
||||
float32_t *pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @param[in,out] S points to an instance of the sorting structure.
|
||||
* @param[in] dir Sorting order.
|
||||
* @param[in] buffer Working buffer.
|
||||
*/
|
||||
void arm_merge_sort_init_f32(
|
||||
arm_merge_sort_instance_f32 * S,
|
||||
arm_sort_dir dir,
|
||||
float32_t * buffer);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a floating-point vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a floating-point vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a Q7 vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a Q15 vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a Q31 vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a floating-point vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_f32(
|
||||
float32_t value,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a floating-point vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_f64(
|
||||
float64_t value,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a Q7 vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_q7(
|
||||
q7_t value,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a Q15 vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_q15(
|
||||
q15_t value,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a Q31 vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_q31(
|
||||
q31_t value,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Weighted sum
|
||||
*
|
||||
*
|
||||
* @param[in] *in Array of input values.
|
||||
* @param[in] *weigths Weights
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Weighted sum
|
||||
*
|
||||
*/
|
||||
float32_t arm_weighted_sum_f32(const float32_t *in
|
||||
, const float32_t *weigths
|
||||
, uint32_t blockSize);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Barycenter
|
||||
*
|
||||
*
|
||||
* @param[in] in List of vectors
|
||||
* @param[in] weights Weights of the vectors
|
||||
* @param[out] out Barycenter
|
||||
* @param[in] nbVectors Number of vectors
|
||||
* @param[in] vecDim Dimension of space (vector dimension)
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
void arm_barycenter_f32(const float32_t *in
|
||||
, const float32_t *weights
|
||||
, float32_t *out
|
||||
, uint32_t nbVectors
|
||||
, uint32_t vecDim);
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _SUPPORT_FUNCTIONS_H_ */
|
||||
@@ -1,202 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file support_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.1
|
||||
* @date 18 August 2022
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SUPPORT_FUNCTIONS_F16_H_
|
||||
#define _SUPPORT_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
/**
|
||||
* @brief Copies the elements of a floating-point vector.
|
||||
* @param[in] pSrc input pointer
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_copy_f16(const float16_t * pSrc, float16_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Fills a constant value into a floating-point vector.
|
||||
* @param[in] value input value to be filled
|
||||
* @param[out] pDst output pointer
|
||||
* @param[in] blockSize number of samples to process
|
||||
*/
|
||||
void arm_fill_f16(float16_t value, float16_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q31 vector.
|
||||
* @param[in] pSrc points to the f16 input vector
|
||||
* @param[out] pDst points to the q15 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_f16_to_q15(const float16_t * pSrc, q15_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q31 vector.
|
||||
* @param[in] pSrc points to the q15 input vector
|
||||
* @param[out] pDst points to the f16 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_q15_to_f16(const q15_t * pSrc, float16_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the 64 bit floating-point vector to 16 bit floating-point vector.
|
||||
* @param[in] pSrc points to the f64 input vector
|
||||
* @param[out] pDst points to the f16 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_f64_to_f16(const float64_t * pSrc, float16_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the 16 bit floating-point vector to 64 bit floating-point vector.
|
||||
* @param[in] pSrc points to the f16 input vector
|
||||
* @param[out] pDst points to the f64 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_f16_to_f64(const float16_t * pSrc, float64_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q31 vector.
|
||||
* @param[in] pSrc points to the f32 input vector
|
||||
* @param[out] pDst points to the f16 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_float_to_f16(const float32_t * pSrc, float16_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Converts the elements of the floating-point vector to Q31 vector.
|
||||
* @param[in] pSrc points to the f16 input vector
|
||||
* @param[out] pDst points to the f32 output vector
|
||||
* @param[in] blockSize length of the input vector
|
||||
*/
|
||||
void arm_f16_to_float(const float16_t * pSrc, float32_t * pDst, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Weighted sum
|
||||
*
|
||||
*
|
||||
* @param[in] *in Array of input values.
|
||||
* @param[in] *weigths Weights
|
||||
* @param[in] blockSize Number of samples in the input array.
|
||||
* @return Weighted sum
|
||||
*
|
||||
*/
|
||||
float16_t arm_weighted_sum_f16(const float16_t *in
|
||||
, const float16_t *weigths
|
||||
, uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Barycenter
|
||||
*
|
||||
*
|
||||
* @param[in] in List of vectors
|
||||
* @param[in] weights Weights of the vectors
|
||||
* @param[out] out Barycenter
|
||||
* @param[in] nbVectors Number of vectors
|
||||
* @param[in] vecDim Dimension of space (vector dimension)
|
||||
* @return None
|
||||
*
|
||||
*/
|
||||
void arm_barycenter_f16(const float16_t *in
|
||||
, const float16_t *weights
|
||||
, float16_t *out
|
||||
, uint32_t nbVectors
|
||||
, uint32_t vecDim);
|
||||
|
||||
|
||||
/**
|
||||
@ingroup groupSupport
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup typecast Typecasting
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup typecast
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Interpret a f16 as an s16 value
|
||||
* @param[in] x input value.
|
||||
* @return return value.
|
||||
*
|
||||
* @par Description
|
||||
* It is a typecast. No conversion of the float to int is done.
|
||||
* The memcpy will be optimized out by the compiler.
|
||||
* memcpy is used to prevent type punning issues.
|
||||
* With gcc, -fno-builtins MUST not be used or the
|
||||
* memcpy will not be optimized out.
|
||||
*/
|
||||
__STATIC_INLINE int16_t arm_typecast_s16_f16(float16_t x)
|
||||
{
|
||||
int16_t res;
|
||||
res=*(int16_t*)memcpy((char*)&res,(char*)&x,sizeof(float16_t));
|
||||
return(res);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Interpret an s16 as an f16 value
|
||||
* @param[in] x input value.
|
||||
* @return return value.
|
||||
*
|
||||
* @par Description
|
||||
* It is a typecast. No conversion of the int to float is done.
|
||||
* The memcpy will be optimized out by the compiler.
|
||||
* memcpy is used to prevent type punning issues.
|
||||
* With gcc, -fno-builtins MUST not be used or the
|
||||
* memcpy will not be optimized out.
|
||||
*/
|
||||
__STATIC_INLINE float16_t arm_typecast_f16_s16(int16_t x)
|
||||
{
|
||||
float16_t res;
|
||||
res=*(float16_t*)memcpy((char*)&res,(char*)&x,sizeof(int16_t));
|
||||
return(res);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@} end of typecast group
|
||||
*/
|
||||
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _SUPPORT_FUNCTIONS_F16_H_ */
|
||||
@@ -1,46 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file svm_defines.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SVM_DEFINES_H_
|
||||
#define _SVM_DEFINES_H_
|
||||
|
||||
/**
|
||||
* @brief Struct for specifying SVM Kernel
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ARM_ML_KERNEL_LINEAR = 0,
|
||||
/**< Linear kernel */
|
||||
ARM_ML_KERNEL_POLYNOMIAL = 1,
|
||||
/**< Polynomial kernel */
|
||||
ARM_ML_KERNEL_RBF = 2,
|
||||
/**< Radial Basis Function kernel */
|
||||
ARM_ML_KERNEL_SIGMOID = 3
|
||||
/**< Sigmoid kernel */
|
||||
} arm_ml_kernel_type;
|
||||
|
||||
#endif
|
||||
@@ -1,299 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file svm_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SVM_FUNCTIONS_H_
|
||||
#define _SVM_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
#include "dsp/svm_defines.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define STEP(x) (x) <= 0 ? 0 : 1
|
||||
|
||||
/**
|
||||
* @defgroup groupSVM SVM Functions
|
||||
* This set of functions is implementing SVM classification on 2 classes.
|
||||
* The training must be done from scikit-learn. The parameters can be easily
|
||||
* generated from the scikit-learn object. Some examples are given in
|
||||
* DSP/Testing/PatternGeneration/SVM.py
|
||||
*
|
||||
* If more than 2 classes are needed, the functions in this folder
|
||||
* will have to be used, as building blocks, to do multi-class classification.
|
||||
*
|
||||
* No multi-class classification is provided in this SVM folder.
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Integer exponentiation
|
||||
* @param[in] x value
|
||||
* @param[in] nb integer exponent >= 1
|
||||
* @return x^nb
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb)
|
||||
{
|
||||
float32_t r = x;
|
||||
nb --;
|
||||
while(nb > 0)
|
||||
{
|
||||
r = r * x;
|
||||
nb--;
|
||||
}
|
||||
return(r);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for linear SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float32_t intercept; /**< Intercept */
|
||||
const float32_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float32_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
} arm_svm_linear_instance_f32;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for polynomial SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float32_t intercept; /**< Intercept */
|
||||
const float32_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float32_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
int32_t degree; /**< Polynomial degree */
|
||||
float32_t coef0; /**< Polynomial constant */
|
||||
float32_t gamma; /**< Gamma factor */
|
||||
} arm_svm_polynomial_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for rbf SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float32_t intercept; /**< Intercept */
|
||||
const float32_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float32_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
float32_t gamma; /**< Gamma factor */
|
||||
} arm_svm_rbf_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for sigmoid SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float32_t intercept; /**< Intercept */
|
||||
const float32_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float32_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
float32_t coef0; /**< Independent constant */
|
||||
float32_t gamma; /**< Gamma factor */
|
||||
} arm_svm_sigmoid_instance_f32;
|
||||
|
||||
/**
|
||||
* @brief SVM linear instance init function
|
||||
* @param[in] S Parameters for SVM functions
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float32_t intercept,
|
||||
const float32_t *dualCoefficients,
|
||||
const float32_t *supportVectors,
|
||||
const int32_t *classes);
|
||||
|
||||
/**
|
||||
* @brief SVM linear prediction
|
||||
* @param[in] S Pointer to an instance of the linear SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S,
|
||||
const float32_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief SVM polynomial instance init function
|
||||
* @param[in] S points to an instance of the polynomial SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] degree Polynomial degree
|
||||
* @param[in] coef0 coeff0 (scikit-learn terminology)
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float32_t intercept,
|
||||
const float32_t *dualCoefficients,
|
||||
const float32_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
int32_t degree,
|
||||
float32_t coef0,
|
||||
float32_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM polynomial prediction
|
||||
* @param[in] S Pointer to an instance of the polynomial SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S,
|
||||
const float32_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief SVM radial basis function instance init function
|
||||
* @param[in] S points to an instance of the polynomial SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float32_t intercept,
|
||||
const float32_t *dualCoefficients,
|
||||
const float32_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
float32_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM rbf prediction
|
||||
* @param[in] S Pointer to an instance of the rbf SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S,
|
||||
const float32_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief SVM sigmoid instance init function
|
||||
* @param[in] S points to an instance of the rbf SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] coef0 coeff0 (scikit-learn terminology)
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float32_t intercept,
|
||||
const float32_t *dualCoefficients,
|
||||
const float32_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
float32_t coef0,
|
||||
float32_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM sigmoid prediction
|
||||
* @param[in] S Pointer to an instance of the rbf SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S,
|
||||
const float32_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _SVM_FUNCTIONS_H_ */
|
||||
@@ -1,281 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file svm_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _SVM_FUNCTIONS_F16_H_
|
||||
#define _SVM_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
#include "dsp/svm_defines.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
#define STEP(x) (x) <= 0 ? 0 : 1
|
||||
|
||||
/**
|
||||
* @defgroup groupSVM SVM Functions
|
||||
* This set of functions is implementing SVM classification on 2 classes.
|
||||
* The training must be done from scikit-learn. The parameters can be easily
|
||||
* generated from the scikit-learn object. Some examples are given in
|
||||
* DSP/Testing/PatternGeneration/SVM.py
|
||||
*
|
||||
* If more than 2 classes are needed, the functions in this folder
|
||||
* will have to be used, as building blocks, to do multi-class classification.
|
||||
*
|
||||
* No multi-class classification is provided in this SVM folder.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for linear SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float16_t intercept; /**< Intercept */
|
||||
const float16_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float16_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
} arm_svm_linear_instance_f16;
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for polynomial SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float16_t intercept; /**< Intercept */
|
||||
const float16_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float16_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
int32_t degree; /**< Polynomial degree */
|
||||
float16_t coef0; /**< Polynomial constant */
|
||||
float16_t gamma; /**< Gamma factor */
|
||||
} arm_svm_polynomial_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for rbf SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float16_t intercept; /**< Intercept */
|
||||
const float16_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float16_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
float16_t gamma; /**< Gamma factor */
|
||||
} arm_svm_rbf_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for sigmoid SVM prediction function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nbOfSupportVectors; /**< Number of support vectors */
|
||||
uint32_t vectorDimension; /**< Dimension of vector space */
|
||||
float16_t intercept; /**< Intercept */
|
||||
const float16_t *dualCoefficients; /**< Dual coefficients */
|
||||
const float16_t *supportVectors; /**< Support vectors */
|
||||
const int32_t *classes; /**< The two SVM classes */
|
||||
float16_t coef0; /**< Independent constant */
|
||||
float16_t gamma; /**< Gamma factor */
|
||||
} arm_svm_sigmoid_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief SVM linear instance init function
|
||||
* @param[in] S Parameters for SVM functions
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
void arm_svm_linear_init_f16(arm_svm_linear_instance_f16 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float16_t intercept,
|
||||
const float16_t *dualCoefficients,
|
||||
const float16_t *supportVectors,
|
||||
const int32_t *classes);
|
||||
|
||||
/**
|
||||
* @brief SVM linear prediction
|
||||
* @param[in] S Pointer to an instance of the linear SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_linear_predict_f16(const arm_svm_linear_instance_f16 *S,
|
||||
const float16_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief SVM polynomial instance init function
|
||||
* @param[in] S points to an instance of the polynomial SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] degree Polynomial degree
|
||||
* @param[in] coef0 coeff0 (scikit-learn terminology)
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
void arm_svm_polynomial_init_f16(arm_svm_polynomial_instance_f16 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float16_t intercept,
|
||||
const float16_t *dualCoefficients,
|
||||
const float16_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
int32_t degree,
|
||||
float16_t coef0,
|
||||
float16_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM polynomial prediction
|
||||
* @param[in] S Pointer to an instance of the polynomial SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_polynomial_predict_f16(const arm_svm_polynomial_instance_f16 *S,
|
||||
const float16_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
/**
|
||||
* @brief SVM radial basis function instance init function
|
||||
* @param[in] S points to an instance of the polynomial SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_rbf_init_f16(arm_svm_rbf_instance_f16 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float16_t intercept,
|
||||
const float16_t *dualCoefficients,
|
||||
const float16_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
float16_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM rbf prediction
|
||||
* @param[in] S Pointer to an instance of the rbf SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_rbf_predict_f16(const arm_svm_rbf_instance_f16 *S,
|
||||
const float16_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
/**
|
||||
* @brief SVM sigmoid instance init function
|
||||
* @param[in] S points to an instance of the rbf SVM structure.
|
||||
* @param[in] nbOfSupportVectors Number of support vectors
|
||||
* @param[in] vectorDimension Dimension of vector space
|
||||
* @param[in] intercept Intercept
|
||||
* @param[in] dualCoefficients Array of dual coefficients
|
||||
* @param[in] supportVectors Array of support vectors
|
||||
* @param[in] classes Array of 2 classes ID
|
||||
* @param[in] coef0 coeff0 (scikit-learn terminology)
|
||||
* @param[in] gamma gamma (scikit-learn terminology)
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
|
||||
void arm_svm_sigmoid_init_f16(arm_svm_sigmoid_instance_f16 *S,
|
||||
uint32_t nbOfSupportVectors,
|
||||
uint32_t vectorDimension,
|
||||
float16_t intercept,
|
||||
const float16_t *dualCoefficients,
|
||||
const float16_t *supportVectors,
|
||||
const int32_t *classes,
|
||||
float16_t coef0,
|
||||
float16_t gamma
|
||||
);
|
||||
|
||||
/**
|
||||
* @brief SVM sigmoid prediction
|
||||
* @param[in] S Pointer to an instance of the rbf SVM structure.
|
||||
* @param[in] in Pointer to input vector
|
||||
* @param[out] pResult Decision value
|
||||
* @return none.
|
||||
*
|
||||
*/
|
||||
void arm_svm_sigmoid_predict_f16(const arm_svm_sigmoid_instance_f16 *S,
|
||||
const float16_t * in,
|
||||
int32_t * pResult);
|
||||
|
||||
|
||||
|
||||
#endif /*defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _SVM_FUNCTIONS_F16_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,317 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file transform_functions_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _TRANSFORM_FUNCTIONS_F16_H_
|
||||
#define _TRANSFORM_FUNCTIONS_F16_H_
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
|
||||
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
|
||||
const float16_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
|
||||
float16_t onebyfftLen; /**< value of 1/fftLen. */
|
||||
} arm_cfft_radix2_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
|
||||
uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
|
||||
const float16_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
|
||||
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
|
||||
float16_t onebyfftLen; /**< value of 1/fftLen. */
|
||||
} arm_cfft_radix4_instance_f16;
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point CFFT/CIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t fftLen; /**< length of the FFT. */
|
||||
const float16_t *pTwiddle; /**< points to the Twiddle factor table. */
|
||||
const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
|
||||
uint16_t bitRevLength; /**< bit reversal table length. */
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \
|
||||
const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \
|
||||
const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \
|
||||
const float16_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \
|
||||
const float16_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \
|
||||
const float16_t *rearranged_twiddle_stride3;
|
||||
#endif
|
||||
} arm_cfft_instance_f16;
|
||||
|
||||
|
||||
arm_status arm_cfft_init_4096_f16(arm_cfft_instance_f16 * S);
|
||||
arm_status arm_cfft_init_2048_f16(arm_cfft_instance_f16 * S);
|
||||
arm_status arm_cfft_init_1024_f16(arm_cfft_instance_f16 * S);
|
||||
arm_status arm_cfft_init_512_f16(arm_cfft_instance_f16 * S);
|
||||
arm_status arm_cfft_init_256_f16(arm_cfft_instance_f16 * S);
|
||||
arm_status arm_cfft_init_128_f16(arm_cfft_instance_f16 * S);
|
||||
arm_status arm_cfft_init_64_f16(arm_cfft_instance_f16 * S);
|
||||
arm_status arm_cfft_init_32_f16(arm_cfft_instance_f16 * S);
|
||||
arm_status arm_cfft_init_16_f16(arm_cfft_instance_f16 * S);
|
||||
|
||||
|
||||
arm_status arm_cfft_init_f16(
|
||||
arm_cfft_instance_f16 * S,
|
||||
uint16_t fftLen);
|
||||
|
||||
void arm_cfft_f16(
|
||||
const arm_cfft_instance_f16 * S,
|
||||
float16_t * p1,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the floating-point RFFT/RIFFT function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
arm_cfft_instance_f16 Sint; /**< Internal CFFT structure. */
|
||||
uint16_t fftLenRFFT; /**< length of the real sequence */
|
||||
const float16_t * pTwiddleRFFT; /**< Twiddle factors real stage */
|
||||
} arm_rfft_fast_instance_f16 ;
|
||||
|
||||
arm_status arm_rfft_fast_init_32_f16( arm_rfft_fast_instance_f16 * S );
|
||||
arm_status arm_rfft_fast_init_64_f16( arm_rfft_fast_instance_f16 * S );
|
||||
arm_status arm_rfft_fast_init_128_f16( arm_rfft_fast_instance_f16 * S );
|
||||
arm_status arm_rfft_fast_init_256_f16( arm_rfft_fast_instance_f16 * S );
|
||||
arm_status arm_rfft_fast_init_512_f16( arm_rfft_fast_instance_f16 * S );
|
||||
arm_status arm_rfft_fast_init_1024_f16( arm_rfft_fast_instance_f16 * S );
|
||||
arm_status arm_rfft_fast_init_2048_f16( arm_rfft_fast_instance_f16 * S );
|
||||
arm_status arm_rfft_fast_init_4096_f16( arm_rfft_fast_instance_f16 * S );
|
||||
|
||||
arm_status arm_rfft_fast_init_f16 (
|
||||
arm_rfft_fast_instance_f16 * S,
|
||||
uint16_t fftLen);
|
||||
|
||||
|
||||
void arm_rfft_fast_f16(
|
||||
const arm_rfft_fast_instance_f16 * S,
|
||||
float16_t * p, float16_t * pOut,
|
||||
uint8_t ifftFlag);
|
||||
|
||||
/* Deprecated */
|
||||
arm_status arm_cfft_radix4_init_f16(
|
||||
arm_cfft_radix4_instance_f16 * S,
|
||||
uint16_t fftLen,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/* Deprecated */
|
||||
void arm_cfft_radix4_f16(
|
||||
const arm_cfft_radix4_instance_f16 * S,
|
||||
float16_t * pSrc);
|
||||
|
||||
|
||||
/* Deprecated */
|
||||
arm_status arm_cfft_radix2_init_f16(
|
||||
arm_cfft_radix2_instance_f16 * S,
|
||||
uint16_t fftLen,
|
||||
uint8_t ifftFlag,
|
||||
uint8_t bitReverseFlag);
|
||||
|
||||
/* Deprecated */
|
||||
void arm_cfft_radix2_f16(
|
||||
const arm_cfft_radix2_instance_f16 * S,
|
||||
float16_t * pSrc);
|
||||
|
||||
/**
|
||||
* @brief Instance structure for the Floating-point MFCC function.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
const float16_t *dctCoefs; /**< Internal DCT coefficients */
|
||||
const float16_t *filterCoefs; /**< Internal Mel filter coefficients */
|
||||
const float16_t *windowCoefs; /**< Windowing coefficients */
|
||||
const uint32_t *filterPos; /**< Internal Mel filter positions in spectrum */
|
||||
const uint32_t *filterLengths; /**< Internal Mel filter lengths */
|
||||
uint32_t fftLen; /**< FFT length */
|
||||
uint32_t nbMelFilters; /**< Number of Mel filters */
|
||||
uint32_t nbDctOutputs; /**< Number of DCT outputs */
|
||||
#if defined(ARM_MFCC_CFFT_BASED)
|
||||
/* Implementation of the MFCC is using a CFFT */
|
||||
arm_cfft_instance_f16 cfft; /**< Internal CFFT instance */
|
||||
#else
|
||||
/* Implementation of the MFCC is using a RFFT (default) */
|
||||
arm_rfft_fast_instance_f16 rfft;
|
||||
#endif
|
||||
} arm_mfcc_instance_f16 ;
|
||||
|
||||
arm_status arm_mfcc_init_32_f16(
|
||||
arm_mfcc_instance_f16 * S,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const float16_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const float16_t *filterCoefs,
|
||||
const float16_t *windowCoefs
|
||||
);
|
||||
|
||||
arm_status arm_mfcc_init_64_f16(
|
||||
arm_mfcc_instance_f16 * S,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const float16_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const float16_t *filterCoefs,
|
||||
const float16_t *windowCoefs
|
||||
);
|
||||
|
||||
arm_status arm_mfcc_init_128_f16(
|
||||
arm_mfcc_instance_f16 * S,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const float16_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const float16_t *filterCoefs,
|
||||
const float16_t *windowCoefs
|
||||
);
|
||||
|
||||
arm_status arm_mfcc_init_256_f16(
|
||||
arm_mfcc_instance_f16 * S,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const float16_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const float16_t *filterCoefs,
|
||||
const float16_t *windowCoefs
|
||||
);
|
||||
|
||||
arm_status arm_mfcc_init_512_f16(
|
||||
arm_mfcc_instance_f16 * S,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const float16_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const float16_t *filterCoefs,
|
||||
const float16_t *windowCoefs
|
||||
);
|
||||
|
||||
arm_status arm_mfcc_init_1024_f16(
|
||||
arm_mfcc_instance_f16 * S,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const float16_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const float16_t *filterCoefs,
|
||||
const float16_t *windowCoefs
|
||||
);
|
||||
|
||||
arm_status arm_mfcc_init_2048_f16(
|
||||
arm_mfcc_instance_f16 * S,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const float16_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const float16_t *filterCoefs,
|
||||
const float16_t *windowCoefs
|
||||
);
|
||||
|
||||
arm_status arm_mfcc_init_4096_f16(
|
||||
arm_mfcc_instance_f16 * S,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const float16_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const float16_t *filterCoefs,
|
||||
const float16_t *windowCoefs
|
||||
);
|
||||
|
||||
arm_status arm_mfcc_init_f16(
|
||||
arm_mfcc_instance_f16 * S,
|
||||
uint32_t fftLen,
|
||||
uint32_t nbMelFilters,
|
||||
uint32_t nbDctOutputs,
|
||||
const float16_t *dctCoefs,
|
||||
const uint32_t *filterPos,
|
||||
const uint32_t *filterLengths,
|
||||
const float16_t *filterCoefs,
|
||||
const float16_t *windowCoefs
|
||||
);
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@brief MFCC F16
|
||||
@param[in] S points to the mfcc instance structure
|
||||
@param[in] pSrc points to the input samples
|
||||
@param[out] pDst points to the output MFCC values
|
||||
@param[inout] pTmp points to a temporary buffer of complex
|
||||
@return none
|
||||
*/
|
||||
void arm_mfcc_f16(
|
||||
const arm_mfcc_instance_f16 * S,
|
||||
float16_t *pSrc,
|
||||
float16_t *pDst,
|
||||
float16_t *pTmp
|
||||
);
|
||||
|
||||
|
||||
#endif /* defined(ARM_FLOAT16_SUPPORTED)*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _TRANSFORM_FUNCTIONS_F16_H_ */
|
||||
@@ -1,262 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file arm_math_utils.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.9.0
|
||||
* @date 20. July 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_UTILS_H_
|
||||
|
||||
#define _ARM_MATH_UTILS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include <limits.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Macros required for reciprocal calculation in Normalized LMS
|
||||
*/
|
||||
|
||||
#define INDEX_MASK 0x0000003F
|
||||
|
||||
#ifndef MIN
|
||||
#define MIN(x,y) ((x) < (y) ? (x) : (y))
|
||||
#endif
|
||||
|
||||
#ifndef MAX
|
||||
#define MAX(x,y) ((x) > (y) ? (x) : (y))
|
||||
#endif
|
||||
|
||||
#ifndef ARM_SQ
|
||||
#define ARM_SQ(x) ((x) * (x))
|
||||
#endif
|
||||
|
||||
#ifndef ARM_ROUND_UP
|
||||
#define ARM_ROUND_UP(N, S) ((((N) + (S) - 1) / (S)) * (S))
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
|
||||
It should not be used with negative values.
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t arm_recip_q31(
|
||||
q31_t in,
|
||||
q31_t * dst,
|
||||
const q31_t * pRecipTable)
|
||||
{
|
||||
q31_t out;
|
||||
uint32_t tempVal;
|
||||
uint32_t index, i;
|
||||
uint32_t signBits;
|
||||
|
||||
if (in > 0)
|
||||
{
|
||||
signBits = ((uint32_t) (__CLZ( (uint32_t)in) - 1));
|
||||
}
|
||||
else
|
||||
{
|
||||
signBits = ((uint32_t) (__CLZ((uint32_t)(-in)) - 1));
|
||||
}
|
||||
|
||||
/* Convert input sample to 1.31 format */
|
||||
in = (in << signBits);
|
||||
|
||||
/* calculation of index for initial approximated Val */
|
||||
index = (uint32_t)(in >> 24);
|
||||
index = (index & INDEX_MASK);
|
||||
|
||||
/* 1.31 with exp 1 */
|
||||
out = pRecipTable[index];
|
||||
|
||||
/* calculation of reciprocal value */
|
||||
/* running approximation for two iterations */
|
||||
for (i = 0U; i < 2U; i++)
|
||||
{
|
||||
tempVal = (uint32_t) (((q63_t) in * out) >> 31);
|
||||
tempVal = 0x7FFFFFFFu - tempVal;
|
||||
/* 1.31 with exp 1 */
|
||||
/* out = (q31_t) (((q63_t) out * tempVal) >> 30); */
|
||||
out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30);
|
||||
}
|
||||
|
||||
/* write output */
|
||||
*dst = out;
|
||||
|
||||
/* return num of signbits of out = 1/in value */
|
||||
return (signBits + 1U);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
|
||||
It should not be used with negative values.
|
||||
*/
|
||||
__STATIC_FORCEINLINE uint32_t arm_recip_q15(
|
||||
q15_t in,
|
||||
q15_t * dst,
|
||||
const q15_t * pRecipTable)
|
||||
{
|
||||
q15_t out = 0;
|
||||
int32_t tempVal = 0;
|
||||
uint32_t index = 0, i = 0;
|
||||
uint32_t signBits = 0;
|
||||
|
||||
if (in > 0)
|
||||
{
|
||||
signBits = ((uint32_t)(__CLZ( (uint32_t)in) - 17));
|
||||
}
|
||||
else
|
||||
{
|
||||
signBits = ((uint32_t)(__CLZ((uint32_t)(-in)) - 17));
|
||||
}
|
||||
|
||||
/* Convert input sample to 1.15 format */
|
||||
in = (q15_t)(in << signBits);
|
||||
|
||||
/* calculation of index for initial approximated Val */
|
||||
index = (uint32_t)(in >> 8);
|
||||
index = (index & INDEX_MASK);
|
||||
|
||||
/* 1.15 with exp 1 */
|
||||
out = pRecipTable[index];
|
||||
|
||||
/* calculation of reciprocal value */
|
||||
/* running approximation for two iterations */
|
||||
for (i = 0U; i < 2U; i++)
|
||||
{
|
||||
tempVal = (((q31_t) in * out) >> 15);
|
||||
tempVal = 0x7FFF - tempVal;
|
||||
/* 1.15 with exp 1 */
|
||||
out = (q15_t) (((q31_t) out * tempVal) >> 14);
|
||||
/* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */
|
||||
}
|
||||
|
||||
/* write output */
|
||||
*dst = out;
|
||||
|
||||
/* return num of signbits of out = 1/in value */
|
||||
return (signBits + 1);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief 64-bit to 32-bit unsigned normalization
|
||||
* @param[in] in is input unsigned long long value
|
||||
* @param[out] normalized is the 32-bit normalized value
|
||||
* @param[out] norm is norm scale
|
||||
*/
|
||||
__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm)
|
||||
{
|
||||
int32_t n1;
|
||||
int32_t hi = (int32_t) (in >> 32);
|
||||
int32_t lo = (int32_t) ((in << 32) >> 32);
|
||||
|
||||
n1 = __CLZ((uint32_t)hi) - 32;
|
||||
if (!n1)
|
||||
{
|
||||
/*
|
||||
* input fits in 32-bit
|
||||
*/
|
||||
n1 = __CLZ((uint32_t)lo);
|
||||
if (!n1)
|
||||
{
|
||||
/*
|
||||
* MSB set, need to scale down by 1
|
||||
*/
|
||||
*norm = -1;
|
||||
*normalized = (((uint32_t) lo) >> 1);
|
||||
} else
|
||||
{
|
||||
if (n1 == 32)
|
||||
{
|
||||
/*
|
||||
* input is zero
|
||||
*/
|
||||
*norm = 0;
|
||||
*normalized = 0;
|
||||
} else
|
||||
{
|
||||
/*
|
||||
* 32-bit normalization
|
||||
*/
|
||||
*norm = n1 - 1;
|
||||
*normalized = lo << *norm;
|
||||
}
|
||||
}
|
||||
} else
|
||||
{
|
||||
/*
|
||||
* input fits in 64-bit
|
||||
*/
|
||||
n1 = 1 - n1;
|
||||
*norm = -n1;
|
||||
/*
|
||||
* 64 bit normalization
|
||||
*/
|
||||
*normalized = (int32_t)(((uint32_t)lo) >> n1) | (hi << (32 - n1));
|
||||
}
|
||||
}
|
||||
|
||||
__STATIC_INLINE int32_t arm_div_int64_to_int32(int64_t num, int32_t den)
|
||||
{
|
||||
int32_t result;
|
||||
uint64_t absNum;
|
||||
int32_t normalized;
|
||||
int32_t norm;
|
||||
|
||||
/*
|
||||
* if sum fits in 32bits
|
||||
* avoid costly 64-bit division
|
||||
*/
|
||||
if (num == (int64_t)LONG_MIN)
|
||||
{
|
||||
absNum = LONG_MAX;
|
||||
}
|
||||
else
|
||||
{
|
||||
absNum = (uint64_t) (num > 0 ? num : -num);
|
||||
}
|
||||
arm_norm_64_to_32u(absNum, &normalized, &norm);
|
||||
if (norm > 0)
|
||||
/*
|
||||
* 32-bit division
|
||||
*/
|
||||
result = (int32_t) num / den;
|
||||
else
|
||||
/*
|
||||
* 64-bit division
|
||||
*/
|
||||
result = (int32_t) (num / den);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#undef INDEX_MASK
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*ifndef _ARM_MATH_UTILS_H_ */
|
||||
@@ -1,812 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file window_functions.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version v1.15.0
|
||||
* @date 15 December 2022
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _WINDOW_FUNCTIONS_H_
|
||||
#define _WINDOW_FUNCTIONS_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @defgroup groupWindow Window Functions
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Welch window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 21.3 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.2 bins |
|
||||
* | Flatness | -2.2248 dB |
|
||||
* | Recommended overlap | 29.3 % |
|
||||
*
|
||||
*/
|
||||
void arm_welch_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Welch window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 21.3 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.2 bins |
|
||||
* | Flatness | -2.2248 dB |
|
||||
* | Recommended overlap | 29.3 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_welch_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Bartlett window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 26.5 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.3333 bins |
|
||||
* | Flatness | -1.8242 dB |
|
||||
* | Recommended overlap | 50.0 % |
|
||||
*
|
||||
*/
|
||||
void arm_bartlett_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Bartlett window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 26.5 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.3333 bins |
|
||||
* | Flatness | -1.8242 dB |
|
||||
* | Recommended overlap | 50.0 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_bartlett_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Hamming window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 42.7 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.3628 bins |
|
||||
* | Flatness | -1.7514 dB |
|
||||
* | Recommended overlap | 50 % |
|
||||
*
|
||||
*/
|
||||
void arm_hamming_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Hamming window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 42.7 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.3628 bins |
|
||||
* | Flatness | -1.7514 dB |
|
||||
* | Recommended overlap | 50 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_hamming_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Hanning window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 31.5 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.5 bins |
|
||||
* | Flatness | -1.4236 dB |
|
||||
* | Recommended overlap | 50 % |
|
||||
*
|
||||
*/
|
||||
void arm_hanning_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Hanning window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 31.5 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.5 bins |
|
||||
* | Flatness | -1.4236 dB |
|
||||
* | Recommended overlap | 50 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_hanning_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Nuttall3 window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 46.7 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.9444 bins |
|
||||
* | Flatness | -0.863 dB |
|
||||
* | Recommended overlap | 64.7 % |
|
||||
*
|
||||
*/
|
||||
void arm_nuttall3_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Nuttall3 window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 46.7 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.9444 bins |
|
||||
* | Flatness | -0.863 dB |
|
||||
* | Recommended overlap | 64.7 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_nuttall3_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Nuttall4 window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 60.9 dB |
|
||||
* | Normalized equivalent noise bandwidth | 2.31 bins |
|
||||
* | Flatness | -0.6184 dB |
|
||||
* | Recommended overlap | 70.5 % |
|
||||
*
|
||||
*/
|
||||
void arm_nuttall4_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Nuttall4 window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 60.9 dB |
|
||||
* | Normalized equivalent noise bandwidth | 2.31 bins |
|
||||
* | Flatness | -0.6184 dB |
|
||||
* | Recommended overlap | 70.5 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_nuttall4_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Nuttall3a window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 64.2 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.7721 bins |
|
||||
* | Flatness | -1.0453 dB |
|
||||
* | Recommended overlap | 61.2 % |
|
||||
*
|
||||
*/
|
||||
void arm_nuttall3a_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Nuttall3a window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 64.2 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.7721 bins |
|
||||
* | Flatness | -1.0453 dB |
|
||||
* | Recommended overlap | 61.2 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_nuttall3a_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Nuttall3b window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 71.5 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.7037 bins |
|
||||
* | Flatness | -1.1352 dB |
|
||||
* | Recommended overlap | 59.8 % |
|
||||
*
|
||||
*/
|
||||
void arm_nuttall3b_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Nuttall3b window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 71.5 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.7037 bins |
|
||||
* | Flatness | -1.1352 dB |
|
||||
* | Recommended overlap | 59.8 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_nuttall3b_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Nuttall4a window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 82.6 dB |
|
||||
* | Normalized equivalent noise bandwidth | 2.1253 bins |
|
||||
* | Flatness | -0.7321 dB |
|
||||
* | Recommended overlap | 68.0 % |
|
||||
*
|
||||
*/
|
||||
void arm_nuttall4a_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Nuttall4a window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 82.6 dB |
|
||||
* | Normalized equivalent noise bandwidth | 2.1253 bins |
|
||||
* | Flatness | -0.7321 dB |
|
||||
* | Recommended overlap | 68.0 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_nuttall4a_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief 92 db blackman harris window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 92.0 dB |
|
||||
* | Normalized equivalent noise bandwidth | 2.0044 bins |
|
||||
* | Flatness | -0.8256 dB |
|
||||
* | Recommended overlap | 66.1 % |
|
||||
*
|
||||
*/
|
||||
void arm_blackman_harris_92db_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief 92 db blackman harris window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 92.0 dB |
|
||||
* | Normalized equivalent noise bandwidth | 2.0044 bins |
|
||||
* | Flatness | -0.8256 dB |
|
||||
* | Recommended overlap | 66.1 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_blackman_harris_92db_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Nuttall4b window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 93.3 dB |
|
||||
* | Normalized equivalent noise bandwidth | 2.0212 bins |
|
||||
* | Flatness | -0.8118 dB |
|
||||
* | Recommended overlap | 66.3 % |
|
||||
*
|
||||
*/
|
||||
void arm_nuttall4b_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Nuttall4b window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 93.3 dB |
|
||||
* | Normalized equivalent noise bandwidth | 2.0212 bins |
|
||||
* | Flatness | -0.8118 dB |
|
||||
* | Recommended overlap | 66.3 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_nuttall4b_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Nuttall4c window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 98.1 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.9761 bins |
|
||||
* | Flatness | -0.8506 dB |
|
||||
* | Recommended overlap | 65.6 % |
|
||||
*
|
||||
*/
|
||||
void arm_nuttall4c_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Nuttall4c window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 98.1 dB |
|
||||
* | Normalized equivalent noise bandwidth | 1.9761 bins |
|
||||
* | Flatness | -0.8506 dB |
|
||||
* | Recommended overlap | 65.6 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_nuttall4c_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Hft90d window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 90.2 dB |
|
||||
* | Normalized equivalent noise bandwidth | 3.8832 bins |
|
||||
* | Flatness | -0.0039 dB |
|
||||
* | Recommended overlap | 76.0 % |
|
||||
*
|
||||
*/
|
||||
void arm_hft90d_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Hft90d window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 90.2 dB |
|
||||
* | Normalized equivalent noise bandwidth | 3.8832 bins |
|
||||
* | Flatness | -0.0039 dB |
|
||||
* | Recommended overlap | 76.0 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_hft90d_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Hft95 window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 95.0 dB |
|
||||
* | Normalized equivalent noise bandwidth | 3.8112 bins |
|
||||
* | Flatness | 0.0044 dB |
|
||||
* | Recommended overlap | 75.6 % |
|
||||
*
|
||||
*/
|
||||
void arm_hft95_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Hft95 window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 95.0 dB |
|
||||
* | Normalized equivalent noise bandwidth | 3.8112 bins |
|
||||
* | Flatness | 0.0044 dB |
|
||||
* | Recommended overlap | 75.6 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_hft95_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Hft116d window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 116.8 dB |
|
||||
* | Normalized equivalent noise bandwidth | 4.2186 bins |
|
||||
* | Flatness | -0.0028 dB |
|
||||
* | Recommended overlap | 78.2 % |
|
||||
*
|
||||
*/
|
||||
void arm_hft116d_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Hft116d window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 116.8 dB |
|
||||
* | Normalized equivalent noise bandwidth | 4.2186 bins |
|
||||
* | Flatness | -0.0028 dB |
|
||||
* | Recommended overlap | 78.2 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_hft116d_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Hft144d window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 144.1 dB |
|
||||
* | Normalized equivalent noise bandwidth | 4.5386 bins |
|
||||
* | Flatness | 0.0021 dB |
|
||||
* | Recommended overlap | 79.9 % |
|
||||
*
|
||||
*/
|
||||
void arm_hft144d_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Hft144d window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 144.1 dB |
|
||||
* | Normalized equivalent noise bandwidth | 4.5386 bins |
|
||||
* | Flatness | 0.0021 dB |
|
||||
* | Recommended overlap | 79.9 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_hft144d_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Hft169d window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 169.5 dB |
|
||||
* | Normalized equivalent noise bandwidth | 4.8347 bins |
|
||||
* | Flatness | 0.0017 dB |
|
||||
* | Recommended overlap | 81.2 % |
|
||||
*
|
||||
*/
|
||||
void arm_hft169d_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Hft169d window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 169.5 dB |
|
||||
* | Normalized equivalent noise bandwidth | 4.8347 bins |
|
||||
* | Flatness | 0.0017 dB |
|
||||
* | Recommended overlap | 81.2 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_hft169d_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Hft196d window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 196.2 dB |
|
||||
* | Normalized equivalent noise bandwidth | 5.1134 bins |
|
||||
* | Flatness | 0.0013 dB |
|
||||
* | Recommended overlap | 82.3 % |
|
||||
*
|
||||
*/
|
||||
void arm_hft196d_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Hft196d window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 196.2 dB |
|
||||
* | Normalized equivalent noise bandwidth | 5.1134 bins |
|
||||
* | Flatness | 0.0013 dB |
|
||||
* | Recommended overlap | 82.3 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_hft196d_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Hft223d window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 223.0 dB |
|
||||
* | Normalized equivalent noise bandwidth | 5.3888 bins |
|
||||
* | Flatness | 0.0011 dB |
|
||||
* | Recommended overlap | 83.3 % |
|
||||
*
|
||||
*/
|
||||
void arm_hft223d_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Hft223d window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 223.0 dB |
|
||||
* | Normalized equivalent noise bandwidth | 5.3888 bins |
|
||||
* | Flatness | 0.0011 dB |
|
||||
* | Recommended overlap | 83.3 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_hft223d_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
/**
|
||||
* @brief Hft248d window (double).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 248.4 dB |
|
||||
* | Normalized equivalent noise bandwidth | 5.6512 bins |
|
||||
* | Flatness | 0.0009 dB |
|
||||
* | Recommended overlap | 84.1 % |
|
||||
*
|
||||
*/
|
||||
void arm_hft248d_f64(
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @brief Hft248d window (float).
|
||||
* @param[out] pDst points to the output generated window
|
||||
* @param[in] blockSize number of samples in the window
|
||||
*
|
||||
* @par Parameters of the window
|
||||
*
|
||||
* | Parameter | Value |
|
||||
* | ------------------------------------: | -----------------: |
|
||||
* | Peak sidelobe level | 248.4 dB |
|
||||
* | Normalized equivalent noise bandwidth | 5.6512 bins |
|
||||
* | Flatness | 0.0009 dB |
|
||||
* | Recommended overlap | 84.1 % |
|
||||
*
|
||||
*
|
||||
*/
|
||||
void arm_hft248d_f32(
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ifndef _BASIC_MATH_FUNCTIONS_H_ */
|
||||
@@ -1,200 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file arm_sorting.h
|
||||
* @brief Private header file for CMSIS DSP Library
|
||||
* @version V1.7.0
|
||||
* @date 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_SORTING_H_
|
||||
#define _ARM_SORTING_H_
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @param[in] S points to an instance of the sorting structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data.
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_bubble_sort_f32(
|
||||
const arm_sort_instance_f32 * S,
|
||||
float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @param[in] S points to an instance of the sorting structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data.
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_heap_sort_f32(
|
||||
const arm_sort_instance_f32 * S,
|
||||
float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @param[in] S points to an instance of the sorting structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data.
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_insertion_sort_f32(
|
||||
const arm_sort_instance_f32 * S,
|
||||
float32_t *pSrc,
|
||||
float32_t* pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @param[in] S points to an instance of the sorting structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_quick_sort_f32(
|
||||
const arm_sort_instance_f32 * S,
|
||||
float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @param[in] S points to an instance of the sorting structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_selection_sort_f32(
|
||||
const arm_sort_instance_f32 * S,
|
||||
float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
/**
|
||||
* @param[in] S points to an instance of the sorting structure.
|
||||
* @param[in] pSrc points to the block of input data.
|
||||
* @param[out] pDst points to the block of output data
|
||||
* @param[in] blockSize number of samples to process.
|
||||
*/
|
||||
void arm_bitonic_sort_f32(
|
||||
const arm_sort_instance_f32 * S,
|
||||
float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize);
|
||||
|
||||
#if defined(ARM_MATH_NEON)
|
||||
|
||||
#define vtrn256_128q(a, b) \
|
||||
do { \
|
||||
float32x4_t vtrn128_temp = a.val[1]; \
|
||||
a.val[1] = b.val[0]; \
|
||||
b.val[0] = vtrn128_temp ; \
|
||||
} while (0)
|
||||
|
||||
#define vtrn128_64q(a, b) \
|
||||
do { \
|
||||
float32x2_t ab, cd, ef, gh; \
|
||||
ab = vget_low_f32(a); \
|
||||
ef = vget_low_f32(b); \
|
||||
cd = vget_high_f32(a); \
|
||||
gh = vget_high_f32(b); \
|
||||
a = vcombine_f32(ab, ef); \
|
||||
b = vcombine_f32(cd, gh); \
|
||||
} while (0)
|
||||
|
||||
#define vtrn256_64q(a, b) \
|
||||
do { \
|
||||
float32x2_t a_0, a_1, a_2, a_3; \
|
||||
float32x2_t b_0, b_1, b_2, b_3; \
|
||||
a_0 = vget_low_f32(a.val[0]); \
|
||||
a_1 = vget_high_f32(a.val[0]); \
|
||||
a_2 = vget_low_f32(a.val[1]); \
|
||||
a_3 = vget_high_f32(a.val[1]); \
|
||||
b_0 = vget_low_f32(b.val[0]); \
|
||||
b_1 = vget_high_f32(b.val[0]); \
|
||||
b_2 = vget_low_f32(b.val[1]); \
|
||||
b_3 = vget_high_f32(b.val[1]); \
|
||||
a.val[0] = vcombine_f32(a_0, b_0); \
|
||||
a.val[1] = vcombine_f32(a_2, b_2); \
|
||||
b.val[0] = vcombine_f32(a_1, b_1); \
|
||||
b.val[1] = vcombine_f32(a_3, b_3); \
|
||||
} while (0)
|
||||
|
||||
#define vtrn128_32q(a, b) \
|
||||
do { \
|
||||
float32x4x2_t vtrn32_tmp = vtrnq_f32((a), (b)); \
|
||||
(a) = vtrn32_tmp.val[0]; \
|
||||
(b) = vtrn32_tmp.val[1]; \
|
||||
} while (0)
|
||||
|
||||
#define vtrn256_32q(a, b) \
|
||||
do { \
|
||||
float32x4x2_t vtrn32_tmp_1 = vtrnq_f32((a.val[0]), (b.val[0])); \
|
||||
float32x4x2_t vtrn32_tmp_2 = vtrnq_f32((a.val[1]), (b.val[1])); \
|
||||
a.val[0] = vtrn32_tmp_1.val[0]; \
|
||||
a.val[1] = vtrn32_tmp_2.val[0]; \
|
||||
b.val[0] = vtrn32_tmp_1.val[1]; \
|
||||
b.val[1] = vtrn32_tmp_2.val[1]; \
|
||||
} while (0)
|
||||
|
||||
#define vminmaxq(a, b) \
|
||||
do { \
|
||||
float32x4_t minmax_tmp = (a); \
|
||||
(a) = vminq_f32((a), (b)); \
|
||||
(b) = vmaxq_f32(minmax_tmp, (b)); \
|
||||
} while (0)
|
||||
|
||||
#define vminmax256q(a, b) \
|
||||
do { \
|
||||
float32x4x2_t minmax256_tmp = (a); \
|
||||
a.val[0] = vminq_f32(a.val[0], b.val[0]); \
|
||||
a.val[1] = vminq_f32(a.val[1], b.val[1]); \
|
||||
b.val[0] = vmaxq_f32(minmax256_tmp.val[0], b.val[0]); \
|
||||
b.val[1] = vmaxq_f32(minmax256_tmp.val[1], b.val[1]); \
|
||||
} while (0)
|
||||
|
||||
#define vrev128q_f32(a) \
|
||||
vcombine_f32(vrev64_f32(vget_high_f32(a)), vrev64_f32(vget_low_f32(a)))
|
||||
|
||||
#define vrev256q_f32(a) \
|
||||
do { \
|
||||
float32x4_t rev_tmp = vcombine_f32(vrev64_f32(vget_high_f32(a.val[0])), vrev64_f32(vget_low_f32(a.val[0]))); \
|
||||
a.val[0] = vcombine_f32(vrev64_f32(vget_high_f32(a.val[1])), vrev64_f32(vget_low_f32(a.val[1]))); \
|
||||
a.val[1] = rev_tmp; \
|
||||
} while (0)
|
||||
|
||||
#define vldrev128q_f32(a, p) \
|
||||
do { \
|
||||
a = vld1q_f32(p); \
|
||||
a = vrev128q_f32(a); \
|
||||
} while (0)
|
||||
|
||||
#endif /* ARM_MATH_NEON */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_SORTING_H */
|
||||
@@ -1,325 +0,0 @@
|
||||
/******************************************************************************
|
||||
* @file arm_vec_fft.h
|
||||
* @brief Private header file for CMSIS DSP Library
|
||||
* @version V1.7.0
|
||||
* @date 07. January 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2020 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_VEC_FFT_H_
|
||||
#define _ARM_VEC_FFT_H_
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define MVE_CMPLX_ADD_A_ixB(A, B) vcaddq_rot90(A,B)
|
||||
#define MVE_CMPLX_SUB_A_ixB(A,B) vcaddq_rot270(A,B)
|
||||
#define MVE_CMPLX_MULT_FLT_AxB(A,B) vcmlaq_rot90(vcmulq(A, B), A, B)
|
||||
#define MVE_CMPLX_MULT_FLT_Conj_AxB(A,B) vcmlaq_rot270(vcmulq(A, B), A, B)
|
||||
|
||||
#define MVE_CMPLX_MULT_FX_AxB(A,B,TyA) vqdmladhxq(vqdmlsdhq((TyA)vuninitializedq_s32(), A, B), A, B)
|
||||
#define MVE_CMPLX_MULT_FX_AxConjB(A,B,TyA) vqdmladhq(vqdmlsdhxq((TyA)vuninitializedq_s32(), A, B), A, B)
|
||||
|
||||
#define MVE_CMPLX_ADD_FX_A_ixB(A, B) vhcaddq_rot90(A,B)
|
||||
#define MVE_CMPLX_SUB_FX_A_ixB(A,B) vhcaddq_rot270(A,B)
|
||||
|
||||
|
||||
/**
|
||||
@brief In-place 32 bit reversal function for helium
|
||||
@param[in,out] pSrc points to in-place buffer of unknown 32-bit data type
|
||||
@param[in] bitRevLen bit reversal table length
|
||||
@param[in] pBitRevTab points to bit reversal table
|
||||
@return none
|
||||
*/
|
||||
|
||||
__STATIC_INLINE void arm_bitreversal_32_inpl_mve(
|
||||
uint32_t *pSrc,
|
||||
const uint16_t bitRevLen,
|
||||
const uint16_t *pBitRevTab)
|
||||
|
||||
{
|
||||
uint64_t *src = (uint64_t *) pSrc;
|
||||
int32_t blkCnt; /* loop counters */
|
||||
uint32x4_t bitRevTabOff;
|
||||
uint32x4_t one = vdupq_n_u32(1);
|
||||
uint64x2_t inLow, inHigh;
|
||||
uint64x2_t bitRevOff1Low, bitRevOff0Low;
|
||||
uint64x2_t bitRevOff1High, bitRevOff0High;
|
||||
|
||||
/* load scheduling to increase gather load idx update / gather load distance */
|
||||
bitRevTabOff = vldrhq_u32(pBitRevTab);
|
||||
pBitRevTab += 4;
|
||||
|
||||
bitRevOff0Low = vmullbq_int_u32(bitRevTabOff, one);
|
||||
bitRevOff0High = vmulltq_int_u32(bitRevTabOff, one);
|
||||
|
||||
|
||||
blkCnt = bitRevLen / 8;
|
||||
while (blkCnt > 0) {
|
||||
bitRevTabOff = vldrhq_u32(pBitRevTab);
|
||||
pBitRevTab += 4;
|
||||
|
||||
/* 64-bit index expansion */
|
||||
bitRevOff1Low = vmullbq_int_u32(bitRevTabOff, one);
|
||||
bitRevOff1High = vmulltq_int_u32(bitRevTabOff, one);
|
||||
|
||||
inLow = vldrdq_gather_offset_u64(src, bitRevOff0Low);
|
||||
inHigh = vldrdq_gather_offset_u64(src, bitRevOff0High);
|
||||
|
||||
vstrdq_scatter_offset_u64(src, bitRevOff0Low, inHigh);
|
||||
vstrdq_scatter_offset_u64(src, bitRevOff0High, inLow);
|
||||
|
||||
|
||||
/* unrolled */
|
||||
bitRevTabOff = vldrhq_u32(pBitRevTab);
|
||||
pBitRevTab += 4;
|
||||
|
||||
bitRevOff0Low = vmullbq_int_u32(bitRevTabOff, one);
|
||||
bitRevOff0High = vmulltq_int_u32(bitRevTabOff, one);
|
||||
|
||||
inLow = vldrdq_gather_offset_u64(src, bitRevOff1Low);
|
||||
inHigh = vldrdq_gather_offset_u64(src, bitRevOff1High);
|
||||
|
||||
vstrdq_scatter_offset_u64(src, bitRevOff1Low, inHigh);
|
||||
vstrdq_scatter_offset_u64(src, bitRevOff1High, inLow);
|
||||
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
if (bitRevLen & 7) {
|
||||
/* FFT size = 16 */
|
||||
inLow = vldrdq_gather_offset_u64(src, bitRevOff0Low);
|
||||
inHigh = vldrdq_gather_offset_u64(src, bitRevOff0High);
|
||||
|
||||
vstrdq_scatter_offset_u64(src, bitRevOff0Low, inHigh);
|
||||
vstrdq_scatter_offset_u64(src, bitRevOff0High, inLow);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
@brief In-place 16 bit reversal function for helium
|
||||
@param[in,out] pSrc points to in-place buffer of unknown 16-bit data type
|
||||
@param[in] bitRevLen bit reversal table length
|
||||
@param[in] pBitRevTab points to bit reversal table
|
||||
@return none
|
||||
*/
|
||||
|
||||
__STATIC_INLINE void arm_bitreversal_16_inpl_mve(
|
||||
uint16_t *pSrc,
|
||||
const uint16_t bitRevLen,
|
||||
const uint16_t *pBitRevTab)
|
||||
|
||||
{
|
||||
uint32_t *src = (uint32_t *) pSrc;
|
||||
int32_t blkCnt; /* loop counters */
|
||||
uint32x4_t bitRevTabOff;
|
||||
uint16x8_t one = vdupq_n_u16(1);
|
||||
uint32x4_t bitRevOff1Low, bitRevOff0Low;
|
||||
uint32x4_t bitRevOff1High, bitRevOff0High;
|
||||
uint32x4_t inLow, inHigh;
|
||||
|
||||
/* load scheduling to increase gather load idx update / gather load distance */
|
||||
bitRevTabOff = vldrhq_u16(pBitRevTab);
|
||||
pBitRevTab += 8;
|
||||
|
||||
bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one);
|
||||
bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one);
|
||||
bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3);
|
||||
bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3);
|
||||
|
||||
blkCnt = (bitRevLen / 16);
|
||||
while (blkCnt > 0) {
|
||||
bitRevTabOff = vldrhq_u16(pBitRevTab);
|
||||
pBitRevTab += 8;
|
||||
|
||||
bitRevOff1Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one);
|
||||
bitRevOff1High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one);
|
||||
bitRevOff1Low = vshrq_n_u16((uint16x8_t)bitRevOff1Low, 3);
|
||||
bitRevOff1High = vshrq_n_u16((uint16x8_t)bitRevOff1High, 3);
|
||||
|
||||
inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low);
|
||||
inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High);
|
||||
|
||||
vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh);
|
||||
vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow);
|
||||
|
||||
/* loop unrolling */
|
||||
bitRevTabOff = vldrhq_u16(pBitRevTab);
|
||||
pBitRevTab += 8;
|
||||
|
||||
bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one);
|
||||
bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one);
|
||||
bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3);
|
||||
bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3);
|
||||
|
||||
inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff1Low);
|
||||
inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff1High);
|
||||
|
||||
vstrwq_scatter_shifted_offset_u32(src, bitRevOff1Low, inHigh);
|
||||
vstrwq_scatter_shifted_offset_u32(src, bitRevOff1High, inLow);
|
||||
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* tail handling */
|
||||
blkCnt = bitRevLen & 0xf;
|
||||
if (blkCnt == 8) {
|
||||
inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low);
|
||||
inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High);
|
||||
|
||||
vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh);
|
||||
vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow);
|
||||
} else if (blkCnt == 12) {
|
||||
/* FFT 16 special case */
|
||||
mve_pred16_t p = vctp16q(4);
|
||||
|
||||
bitRevTabOff = vldrhq_z_u16(pBitRevTab, p);
|
||||
|
||||
inLow = vldrwq_gather_shifted_offset_u32(src, bitRevOff0Low);
|
||||
inHigh = vldrwq_gather_shifted_offset_u32(src, bitRevOff0High);
|
||||
|
||||
vstrwq_scatter_shifted_offset_u32(src, bitRevOff0Low, inHigh);
|
||||
vstrwq_scatter_shifted_offset_u32(src, bitRevOff0High, inLow);
|
||||
|
||||
bitRevOff0Low = vmullbq_int_u16((uint16x8_t)bitRevTabOff, one);
|
||||
bitRevOff0High = vmulltq_int_u16((uint16x8_t)bitRevTabOff, one);
|
||||
bitRevOff0Low = vshrq_n_u16((uint16x8_t)bitRevOff0Low, 3);
|
||||
bitRevOff0High = vshrq_n_u16((uint16x8_t)bitRevOff0High, 3);
|
||||
|
||||
inLow = vldrwq_gather_shifted_offset_z_u32(src, bitRevOff0Low, p);
|
||||
inHigh = vldrwq_gather_shifted_offset_z_u32(src, bitRevOff0High, p);
|
||||
|
||||
vstrwq_scatter_shifted_offset_p_u32(src, bitRevOff0Low, inHigh, p);
|
||||
vstrwq_scatter_shifted_offset_p_u32(src, bitRevOff0High, inLow, p);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Out-of-place 32 bit reversal function for helium
|
||||
@param[out] pDst points to destination buffer of unknown 32-bit data type
|
||||
@param[in] pSrc points to input buffer of unknown 32-bit data type
|
||||
@param[in] fftLen FFT length
|
||||
@return none
|
||||
*/
|
||||
__STATIC_INLINE void arm_bitreversal_32_outpl_mve(void *pDst, void *pSrc, uint32_t fftLen)
|
||||
{
|
||||
uint32x4_t idxOffs0, idxOffs1, bitRevOffs0, bitRevOffs1;
|
||||
uint32_t bitRevPos, blkCnt;
|
||||
uint32_t *pDst32 = (uint32_t *) pDst;
|
||||
|
||||
/* fwd indexes */
|
||||
idxOffs0 = vdupq_n_u32(0);
|
||||
idxOffs1 = vdupq_n_u32(0);
|
||||
idxOffs0[0] = 0; idxOffs0[2] = 4;
|
||||
idxOffs1[0] = 8; idxOffs1[2] = 12;
|
||||
|
||||
bitRevPos = (31 - __CLZ(fftLen)) + 5;
|
||||
blkCnt = fftLen >> 2;
|
||||
|
||||
/* issued earlier to increase gather load idx update / gather load distance */
|
||||
/* bit-reverse fwd indexes */
|
||||
bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos);
|
||||
bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos);
|
||||
while (blkCnt > 0) {
|
||||
uint64x2_t vecIn;
|
||||
|
||||
vecIn = vldrdq_gather_offset_u64(pSrc, (uint64x2_t) bitRevOffs0);
|
||||
idxOffs0 = idxOffs0 + 16;
|
||||
vst1q(pDst32, (uint32x4_t) vecIn);
|
||||
pDst32 += 4;
|
||||
bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos);
|
||||
|
||||
vecIn = vldrdq_gather_offset_u64(pSrc, (uint64x2_t) bitRevOffs1);
|
||||
idxOffs1 = idxOffs1 + 16;
|
||||
vst1q(pDst32, (uint32x4_t) vecIn);
|
||||
pDst32 += 4;
|
||||
bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos);
|
||||
|
||||
blkCnt--;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Out-of-place 16 bit reversal function for helium
|
||||
@param[out] pDst points to destination buffer of unknown 16-bit data type
|
||||
@param[in] pSrc points to input buffer of unknown 16-bit data type
|
||||
@param[in] fftLen FFT length
|
||||
@return none
|
||||
*/
|
||||
|
||||
__STATIC_INLINE void arm_bitreversal_16_outpl_mve(void *pDst, void *pSrc, uint32_t fftLen)
|
||||
{
|
||||
uint32x4_t idxOffs0, idxOffs1, bitRevOffs0, bitRevOffs1;
|
||||
uint32_t bitRevPos, blkCnt;
|
||||
uint16_t *pDst16 = (uint16_t *) pDst;
|
||||
uint32_t incrIdx = 0;
|
||||
|
||||
/* fwd indexes */
|
||||
idxOffs0 = vidupq_wb_u32(&incrIdx, 4); // {0, 4, 8, 12}
|
||||
idxOffs1 = vidupq_wb_u32(&incrIdx, 4); // {16, 20, 24, 28}
|
||||
|
||||
bitRevPos = (31 - __CLZ(fftLen)) + 4;
|
||||
blkCnt = fftLen >> 3;
|
||||
|
||||
/* issued earlier to increase gather load idx update / gather load distance */
|
||||
/* bit-reverse fwd indexes */
|
||||
bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos);
|
||||
bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos);
|
||||
while (blkCnt > 0) {
|
||||
uint32x4_t vecIn;
|
||||
|
||||
vecIn = vldrwq_gather_offset_s32(pSrc, bitRevOffs0);
|
||||
idxOffs0 = idxOffs0 + 32;
|
||||
vst1q(pDst16, (uint16x8_t) vecIn);
|
||||
pDst16 += 8;
|
||||
bitRevOffs0 = vbrsrq(idxOffs0, bitRevPos);
|
||||
|
||||
vecIn = vldrwq_gather_offset_s32(pSrc, bitRevOffs1);
|
||||
idxOffs1 = idxOffs1 + 32;
|
||||
vst1q(pDst16, (uint16x8_t) vecIn);
|
||||
pDst16 += 8;
|
||||
bitRevOffs1 = vbrsrq(idxOffs1, bitRevPos);
|
||||
|
||||
blkCnt--;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _ARM_VEC_FFT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,87 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: BasicMathFunctions.c
|
||||
* Description: Combination of all basic math function source files.
|
||||
*
|
||||
* $Date: 16. March 2020
|
||||
* $Revision: V1.1.0
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "arm_abs_f32.c"
|
||||
#include "arm_abs_f64.c"
|
||||
#include "arm_abs_q15.c"
|
||||
#include "arm_abs_q31.c"
|
||||
#include "arm_abs_q7.c"
|
||||
#include "arm_add_f32.c"
|
||||
#include "arm_add_f64.c"
|
||||
#include "arm_add_q15.c"
|
||||
#include "arm_add_q31.c"
|
||||
#include "arm_add_q7.c"
|
||||
#include "arm_and_u16.c"
|
||||
#include "arm_and_u32.c"
|
||||
#include "arm_and_u8.c"
|
||||
#include "arm_dot_prod_f32.c"
|
||||
#include "arm_dot_prod_f64.c"
|
||||
#include "arm_dot_prod_q15.c"
|
||||
#include "arm_dot_prod_q31.c"
|
||||
#include "arm_dot_prod_q7.c"
|
||||
#include "arm_mult_f32.c"
|
||||
#include "arm_mult_f64.c"
|
||||
#include "arm_mult_q15.c"
|
||||
#include "arm_mult_q31.c"
|
||||
#include "arm_mult_q7.c"
|
||||
#include "arm_negate_f32.c"
|
||||
#include "arm_negate_f64.c"
|
||||
#include "arm_negate_q15.c"
|
||||
#include "arm_negate_q31.c"
|
||||
#include "arm_negate_q7.c"
|
||||
#include "arm_not_u16.c"
|
||||
#include "arm_not_u32.c"
|
||||
#include "arm_not_u8.c"
|
||||
#include "arm_offset_f32.c"
|
||||
#include "arm_offset_f64.c"
|
||||
#include "arm_offset_q15.c"
|
||||
#include "arm_offset_q31.c"
|
||||
#include "arm_offset_q7.c"
|
||||
#include "arm_or_u16.c"
|
||||
#include "arm_or_u32.c"
|
||||
#include "arm_or_u8.c"
|
||||
#include "arm_scale_f32.c"
|
||||
#include "arm_scale_f64.c"
|
||||
#include "arm_scale_q15.c"
|
||||
#include "arm_scale_q31.c"
|
||||
#include "arm_scale_q7.c"
|
||||
#include "arm_shift_q15.c"
|
||||
#include "arm_shift_q31.c"
|
||||
#include "arm_shift_q7.c"
|
||||
#include "arm_sub_f32.c"
|
||||
#include "arm_sub_f64.c"
|
||||
#include "arm_sub_q15.c"
|
||||
#include "arm_sub_q31.c"
|
||||
#include "arm_sub_q7.c"
|
||||
#include "arm_xor_u16.c"
|
||||
#include "arm_xor_u32.c"
|
||||
#include "arm_xor_u8.c"
|
||||
#include "arm_clip_f32.c"
|
||||
#include "arm_clip_q31.c"
|
||||
#include "arm_clip_q15.c"
|
||||
#include "arm_clip_q7.c"
|
||||
@@ -1,37 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: BasicMathFunctionsF16.c
|
||||
* Description: Combination of all basic math function f16 source files.
|
||||
*
|
||||
* $Date: 20. April 2020
|
||||
* $Revision: V1.1.0
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2019-2020 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "arm_abs_f16.c"
|
||||
#include "arm_add_f16.c"
|
||||
#include "arm_dot_prod_f16.c"
|
||||
#include "arm_mult_f16.c"
|
||||
#include "arm_negate_f16.c"
|
||||
#include "arm_offset_f16.c"
|
||||
#include "arm_scale_f16.c"
|
||||
#include "arm_sub_f16.c"
|
||||
#include "arm_clip_f16.c"
|
||||
@@ -1,104 +0,0 @@
|
||||
cmake_minimum_required (VERSION 3.14)
|
||||
|
||||
|
||||
set(SRCF64 BasicMathFunctions/arm_abs_f64.c
|
||||
BasicMathFunctions/arm_add_f64.c
|
||||
BasicMathFunctions/arm_dot_prod_f64.c
|
||||
BasicMathFunctions/arm_mult_f64.c
|
||||
BasicMathFunctions/arm_negate_f64.c
|
||||
BasicMathFunctions/arm_offset_f64.c
|
||||
BasicMathFunctions/arm_scale_f64.c
|
||||
BasicMathFunctions/arm_sub_f64.c
|
||||
)
|
||||
|
||||
set(SRCF32 BasicMathFunctions/arm_abs_f32.c
|
||||
BasicMathFunctions/arm_add_f32.c
|
||||
BasicMathFunctions/arm_clip_f32.c
|
||||
BasicMathFunctions/arm_dot_prod_f32.c
|
||||
BasicMathFunctions/arm_mult_f32.c
|
||||
BasicMathFunctions/arm_negate_f32.c
|
||||
BasicMathFunctions/arm_offset_f32.c
|
||||
BasicMathFunctions/arm_scale_f32.c
|
||||
BasicMathFunctions/arm_sub_f32.c
|
||||
)
|
||||
|
||||
set(SRCF16 BasicMathFunctions/arm_abs_f16.c
|
||||
BasicMathFunctions/arm_add_f16.c
|
||||
BasicMathFunctions/arm_clip_f16.c
|
||||
BasicMathFunctions/arm_dot_prod_f16.c
|
||||
BasicMathFunctions/arm_mult_f16.c
|
||||
BasicMathFunctions/arm_negate_f16.c
|
||||
BasicMathFunctions/arm_offset_f16.c
|
||||
BasicMathFunctions/arm_scale_f16.c
|
||||
BasicMathFunctions/arm_sub_f16.c
|
||||
)
|
||||
|
||||
set(SRCQ31 BasicMathFunctions/arm_abs_q31.c
|
||||
BasicMathFunctions/arm_add_q31.c
|
||||
BasicMathFunctions/arm_clip_q31.c
|
||||
BasicMathFunctions/arm_dot_prod_q31.c
|
||||
BasicMathFunctions/arm_mult_q31.c
|
||||
BasicMathFunctions/arm_negate_q31.c
|
||||
BasicMathFunctions/arm_offset_q31.c
|
||||
BasicMathFunctions/arm_scale_q31.c
|
||||
BasicMathFunctions/arm_shift_q31.c
|
||||
BasicMathFunctions/arm_sub_q31.c
|
||||
)
|
||||
|
||||
set(SRCQ15 BasicMathFunctions/arm_abs_q15.c
|
||||
BasicMathFunctions/arm_add_q15.c
|
||||
BasicMathFunctions/arm_clip_q15.c
|
||||
BasicMathFunctions/arm_dot_prod_q15.c
|
||||
BasicMathFunctions/arm_mult_q15.c
|
||||
BasicMathFunctions/arm_negate_q15.c
|
||||
BasicMathFunctions/arm_offset_q15.c
|
||||
BasicMathFunctions/arm_scale_q15.c
|
||||
BasicMathFunctions/arm_shift_q15.c
|
||||
BasicMathFunctions/arm_sub_q15.c
|
||||
)
|
||||
|
||||
set(SRCQ7 BasicMathFunctions/arm_abs_q7.c
|
||||
BasicMathFunctions/arm_add_q7.c
|
||||
BasicMathFunctions/arm_clip_q7.c
|
||||
BasicMathFunctions/arm_dot_prod_q7.c
|
||||
BasicMathFunctions/arm_mult_q7.c
|
||||
BasicMathFunctions/arm_negate_q7.c
|
||||
BasicMathFunctions/arm_offset_q7.c
|
||||
BasicMathFunctions/arm_scale_q7.c
|
||||
BasicMathFunctions/arm_shift_q7.c
|
||||
BasicMathFunctions/arm_sub_q7.c
|
||||
)
|
||||
|
||||
set(SRCU32 BasicMathFunctions/arm_and_u32.c
|
||||
BasicMathFunctions/arm_not_u32.c
|
||||
BasicMathFunctions/arm_or_u32.c
|
||||
BasicMathFunctions/arm_xor_u32.c
|
||||
)
|
||||
|
||||
set(SRCU16 BasicMathFunctions/arm_and_u16.c
|
||||
BasicMathFunctions/arm_not_u16.c
|
||||
BasicMathFunctions/arm_or_u16.c
|
||||
BasicMathFunctions/arm_xor_u16.c
|
||||
)
|
||||
|
||||
set(SRCU8 BasicMathFunctions/arm_and_u8.c
|
||||
BasicMathFunctions/arm_or_u8.c
|
||||
BasicMathFunctions/arm_not_u8.c
|
||||
BasicMathFunctions/arm_xor_u8.c)
|
||||
|
||||
target_sources(CMSISDSP PRIVATE ${SRCF64})
|
||||
target_sources(CMSISDSP PRIVATE ${SRCF32})
|
||||
|
||||
if ((NOT ARMAC5) AND (NOT DISABLEFLOAT16))
|
||||
target_sources(CMSISDSP PRIVATE ${SRCF16})
|
||||
endif()
|
||||
|
||||
target_sources(CMSISDSP PRIVATE ${SRCQ31})
|
||||
target_sources(CMSISDSP PRIVATE ${SRCQ15})
|
||||
target_sources(CMSISDSP PRIVATE ${SRCQ7})
|
||||
|
||||
target_sources(CMSISDSP PRIVATE ${SRCU32})
|
||||
target_sources(CMSISDSP PRIVATE ${SRCU16})
|
||||
target_sources(CMSISDSP PRIVATE ${SRCU8})
|
||||
|
||||
|
||||
@@ -1,185 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_abs_f16.c
|
||||
* Description: Floating-point vector absolute value
|
||||
*
|
||||
* $Date: 23 April 2021
|
||||
* $Revision: V1.9.0
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "dsp/basic_math_functions_f16.h"
|
||||
#include <math.h>
|
||||
|
||||
/**
|
||||
@ingroup groupMath
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
@addtogroup BasicAbs
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point vector absolute value.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
void arm_abs_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
f16x8_t vec1;
|
||||
f16x8_t res;
|
||||
|
||||
|
||||
/* Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 3U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute values and then store the results in the destination buffer. */
|
||||
vec1 = vld1q(pSrc);
|
||||
res = vabsq(vec1);
|
||||
vst1q(pDst, res);
|
||||
|
||||
/* Increment pointers */
|
||||
pSrc += 8;
|
||||
pDst += 8;
|
||||
|
||||
/* Decrement the loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Tail */
|
||||
blkCnt = blockSize & 0x7;
|
||||
|
||||
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
mve_pred16_t p0 = vctp16q(blkCnt);
|
||||
vec1 = vld1q(pSrc);
|
||||
vstrhq_p(pDst, vabsq(vec1), p0);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#else
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
void arm_abs_f16(
|
||||
const float16_t * pSrc,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
|
||||
#if defined(ARM_MATH_NEON_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
f16x8_t vec1;
|
||||
f16x8_t res;
|
||||
|
||||
/* Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute values and then store the results in the destination buffer. */
|
||||
vec1 = vld1q_f16(pSrc);
|
||||
res = vabsq_f16(vec1);
|
||||
vst1q_f16(pDst, res);
|
||||
|
||||
/* Increment pointers */
|
||||
pSrc += 4;
|
||||
pDst += 4;
|
||||
|
||||
/* Decrement the loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Tail */
|
||||
blkCnt = blockSize & 0x3;
|
||||
|
||||
#else
|
||||
#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
/* Loop unrolling: Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute and store result in destination buffer. */
|
||||
*pDst++ = (_Float16)fabsf((float32_t)*pSrc++);
|
||||
|
||||
*pDst++ = (_Float16)fabsf((float32_t)*pSrc++);
|
||||
|
||||
*pDst++ = (_Float16)fabsf((float32_t)*pSrc++);
|
||||
|
||||
*pDst++ = (_Float16)fabsf((float32_t)*pSrc++);
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Loop unrolling: Compute remaining outputs */
|
||||
blkCnt = blockSize % 0x4U;
|
||||
|
||||
#else
|
||||
|
||||
/* Initialize blkCnt with number of samples */
|
||||
blkCnt = blockSize;
|
||||
|
||||
#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
|
||||
#endif /* #if defined(ARM_MATH_NEON) */
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute and store result in destination buffer. */
|
||||
*pDst++ = (_Float16)fabsf((float32_t)*pSrc++);
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* defined(ARM_FLOAT16_SUPPORTED */
|
||||
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
/**
|
||||
@} end of BasicAbs group
|
||||
*/
|
||||
@@ -1,196 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_abs_f32.c
|
||||
* Description: Floating-point vector absolute value
|
||||
*
|
||||
* $Date: 23 April 2021
|
||||
* $Revision: V1.9.0
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
#include <math.h>
|
||||
|
||||
/**
|
||||
@ingroup groupMath
|
||||
*/
|
||||
|
||||
/**
|
||||
@defgroup BasicAbs Vector Absolute Value
|
||||
|
||||
Computes the absolute value of a vector on an element-by-element basis.
|
||||
|
||||
<pre>
|
||||
pDst[n] = abs(pSrc[n]), 0 <= n < blockSize.
|
||||
</pre>
|
||||
|
||||
The functions support in-place computation allowing the source and
|
||||
destination pointers to reference the same memory buffer.
|
||||
There are separate functions for floating-point, Q7, Q15, and Q31 data types.
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup BasicAbs
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point vector absolute value.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
void arm_abs_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
f32x4_t vec1;
|
||||
f32x4_t res;
|
||||
|
||||
|
||||
/* Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute values and then store the results in the destination buffer. */
|
||||
vec1 = vld1q(pSrc);
|
||||
res = vabsq(vec1);
|
||||
vst1q(pDst, res);
|
||||
|
||||
/* Increment pointers */
|
||||
pSrc += 4;
|
||||
pDst += 4;
|
||||
|
||||
/* Decrement the loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Tail */
|
||||
blkCnt = blockSize & 0x3;
|
||||
|
||||
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
mve_pred16_t p0 = vctp32q(blkCnt);
|
||||
vec1 = vld1q(pSrc);
|
||||
vstrwq_p(pDst, vabsq(vec1), p0);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#else
|
||||
void arm_abs_f32(
|
||||
const float32_t * pSrc,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
|
||||
#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
f32x4_t vec1;
|
||||
f32x4_t res;
|
||||
|
||||
/* Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute values and then store the results in the destination buffer. */
|
||||
vec1 = vld1q_f32(pSrc);
|
||||
res = vabsq_f32(vec1);
|
||||
vst1q_f32(pDst, res);
|
||||
|
||||
/* Increment pointers */
|
||||
pSrc += 4;
|
||||
pDst += 4;
|
||||
|
||||
/* Decrement the loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Tail */
|
||||
blkCnt = blockSize & 0x3;
|
||||
|
||||
#else
|
||||
#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
/* Loop unrolling: Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute and store result in destination buffer. */
|
||||
*pDst++ = fabsf(*pSrc++);
|
||||
|
||||
*pDst++ = fabsf(*pSrc++);
|
||||
|
||||
*pDst++ = fabsf(*pSrc++);
|
||||
|
||||
*pDst++ = fabsf(*pSrc++);
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Loop unrolling: Compute remaining outputs */
|
||||
blkCnt = blockSize % 0x4U;
|
||||
|
||||
#else
|
||||
|
||||
/* Initialize blkCnt with number of samples */
|
||||
blkCnt = blockSize;
|
||||
|
||||
#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
|
||||
#endif /* #if defined(ARM_MATH_NEON) */
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute and store result in destination buffer. */
|
||||
*pDst++ = fabsf(*pSrc++);
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
/**
|
||||
@} end of BasicAbs group
|
||||
*/
|
||||
@@ -1,74 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_abs_f64.c
|
||||
* Description: Floating-point vector absolute value
|
||||
*
|
||||
* $Date: 13 September 2021
|
||||
* $Revision: V1.10.0
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
#include <math.h>
|
||||
|
||||
/**
|
||||
@ingroup groupMath
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup BasicAbs
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point vector absolute value.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_abs_f64(
|
||||
const float64_t * pSrc,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
|
||||
/* Initialize blkCnt with number of samples */
|
||||
blkCnt = blockSize;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute and store result in destination buffer. */
|
||||
*pDst++ = fabs(*pSrc++);
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
@} end of BasicAbs group
|
||||
*/
|
||||
@@ -1,178 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_abs_q15.c
|
||||
* Description: Q15 vector absolute value
|
||||
*
|
||||
* $Date: 23 April 2021
|
||||
* $Revision: V1.9.0
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
|
||||
/**
|
||||
@ingroup groupMath
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup BasicAbs
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Q15 vector absolute value.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
|
||||
@par Scaling and Overflow Behavior
|
||||
The function uses saturating arithmetic.
|
||||
The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
|
||||
*/
|
||||
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
void arm_abs_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* loop counters */
|
||||
q15x8_t vecSrc;
|
||||
|
||||
/* Compute 8 outputs at a time */
|
||||
blkCnt = blockSize >> 3;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/*
|
||||
* C = |A|
|
||||
* Calculate absolute and then store the results in the destination buffer.
|
||||
*/
|
||||
vecSrc = vld1q(pSrc);
|
||||
vst1q(pDst, vqabsq(vecSrc));
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
/*
|
||||
* advance vector source and destination pointers
|
||||
*/
|
||||
pSrc += 8;
|
||||
pDst += 8;
|
||||
}
|
||||
/*
|
||||
* tail
|
||||
*/
|
||||
blkCnt = blockSize & 7;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp16q(blkCnt);
|
||||
vecSrc = vld1q(pSrc);
|
||||
vstrhq_p(pDst, vqabsq(vecSrc), p0);
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
void arm_abs_q15(
|
||||
const q15_t * pSrc,
|
||||
q15_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
q15_t in; /* Temporary input variable */
|
||||
|
||||
#if defined (ARM_MATH_LOOPUNROLL)
|
||||
|
||||
/* Loop unrolling: Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
|
||||
#endif
|
||||
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
|
||||
#endif
|
||||
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
|
||||
#endif
|
||||
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
|
||||
#endif
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Loop unrolling: Compute remaining outputs */
|
||||
blkCnt = blockSize % 0x4U;
|
||||
|
||||
#else
|
||||
|
||||
/* Initialize blkCnt with number of samples */
|
||||
blkCnt = blockSize;
|
||||
|
||||
#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute of input (if -1 then saturated to 0x7fff) and store result in destination buffer. */
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q15_t)__QSUB16(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
|
||||
#endif
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
/**
|
||||
@} end of BasicAbs group
|
||||
*/
|
||||
@@ -1,208 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_abs_q31.c
|
||||
* Description: Q31 vector absolute value
|
||||
*
|
||||
* $Date: 23 April 2021
|
||||
* $Revision: V1.9.0
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
|
||||
/**
|
||||
@ingroup groupMath
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup BasicAbs
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Q31 vector absolute value.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
|
||||
@par Scaling and Overflow Behavior
|
||||
The function uses saturating arithmetic.
|
||||
The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
|
||||
*/
|
||||
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
void arm_abs_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counters */
|
||||
q31x4_t vecSrc;
|
||||
|
||||
/* Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/*
|
||||
* C = |A|
|
||||
* Calculate absolute and then store the results in the destination buffer.
|
||||
*/
|
||||
vecSrc = vld1q(pSrc);
|
||||
vst1q(pDst, vqabsq(vecSrc));
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
/*
|
||||
* Advance vector source and destination pointers
|
||||
*/
|
||||
pSrc += 4;
|
||||
pDst += 4;
|
||||
}
|
||||
/*
|
||||
* Tail
|
||||
*/
|
||||
blkCnt = blockSize & 3;
|
||||
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp32q(blkCnt);
|
||||
vecSrc = vld1q(pSrc);
|
||||
vstrwq_p(pDst, vqabsq(vecSrc), p0);
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
void arm_abs_q31(
|
||||
const q31_t * pSrc,
|
||||
q31_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
q31_t in; /* Temporary variable */
|
||||
|
||||
#if defined(ARM_MATH_NEON)
|
||||
int32x4_t vec1;
|
||||
int32x4_t res;
|
||||
|
||||
/* Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
/* Calculate absolute and then store the results in the destination buffer. */
|
||||
|
||||
vec1 = vld1q_s32(pSrc);
|
||||
res = vqabsq_s32(vec1);
|
||||
vst1q_s32(pDst, res);
|
||||
|
||||
/* Increment pointers */
|
||||
pSrc += 4;
|
||||
pDst += 4;
|
||||
|
||||
/* Decrement the blockSize loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Tail */
|
||||
blkCnt = blockSize & 0x3;
|
||||
|
||||
#else
|
||||
#if defined (ARM_MATH_LOOPUNROLL)
|
||||
|
||||
/* Loop unrolling: Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
|
||||
#endif
|
||||
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
|
||||
#endif
|
||||
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
|
||||
#endif
|
||||
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
|
||||
#endif
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Loop unrolling: Compute remaining outputs */
|
||||
blkCnt = blockSize % 0x4U;
|
||||
|
||||
#else
|
||||
|
||||
/* Initialize blkCnt with number of samples */
|
||||
blkCnt = blockSize;
|
||||
|
||||
#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
|
||||
#endif /* #if defined (ARM_MATH_NEON) */
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and store result in destination buffer. */
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q31_t)__QSUB(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
|
||||
#endif
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* #if defined (ARM_MATH_MVEI) */
|
||||
/**
|
||||
@} end of BasicAbs group
|
||||
*/
|
||||
@@ -1,180 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_abs_q7.c
|
||||
* Description: Q7 vector absolute value
|
||||
*
|
||||
* $Date: 23 April 2021
|
||||
* $Revision: V1.9.0
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
|
||||
/**
|
||||
@ingroup groupMath
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup BasicAbs
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Q7 vector absolute value.
|
||||
@param[in] pSrc points to the input vector
|
||||
@param[out] pDst points to the output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
|
||||
@par Conditions for optimum performance
|
||||
Input and output buffers should be aligned by 32-bit
|
||||
@par Scaling and Overflow Behavior
|
||||
The function uses saturating arithmetic.
|
||||
The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
|
||||
*/
|
||||
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
void arm_abs_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* loop counters */
|
||||
q7x16_t vecSrc;
|
||||
|
||||
/* Compute 16 outputs at a time */
|
||||
blkCnt = blockSize >> 4;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/*
|
||||
* C = |A|
|
||||
* Calculate absolute and then store the results in the destination buffer.
|
||||
*/
|
||||
vecSrc = vld1q(pSrc);
|
||||
vst1q(pDst, vqabsq(vecSrc));
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
/*
|
||||
* advance vector source and destination pointers
|
||||
*/
|
||||
pSrc += 16;
|
||||
pDst += 16;
|
||||
}
|
||||
/*
|
||||
* tail
|
||||
*/
|
||||
blkCnt = blockSize & 0xF;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp8q(blkCnt);
|
||||
vecSrc = vld1q(pSrc);
|
||||
vstrbq_p(pDst, vqabsq(vecSrc), p0);
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
void arm_abs_q7(
|
||||
const q7_t * pSrc,
|
||||
q7_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
q7_t in; /* Temporary input variable */
|
||||
|
||||
#if defined (ARM_MATH_LOOPUNROLL)
|
||||
|
||||
/* Loop unrolling: Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in);
|
||||
#endif
|
||||
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in);
|
||||
#endif
|
||||
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in);
|
||||
#endif
|
||||
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q7_t)__QSUB8(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in);
|
||||
#endif
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Loop unrolling: Compute remaining outputs */
|
||||
blkCnt = blockSize % 0x4U;
|
||||
|
||||
#else
|
||||
|
||||
/* Initialize blkCnt with number of samples */
|
||||
blkCnt = blockSize;
|
||||
|
||||
#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = |A| */
|
||||
|
||||
/* Calculate absolute of input (if -1 then saturated to 0x7f) and store result in destination buffer. */
|
||||
in = *pSrc++;
|
||||
#if defined (ARM_MATH_DSP)
|
||||
*pDst++ = (in > 0) ? in : (q7_t) __QSUB8(0, in);
|
||||
#else
|
||||
*pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? (q7_t) 0x7f : -in);
|
||||
#endif
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
/**
|
||||
@} end of BasicAbs group
|
||||
*/
|
||||
@@ -1,158 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_add_f16.c
|
||||
* Description: Floating-point vector addition
|
||||
*
|
||||
* $Date: 23 April 2021
|
||||
* $Revision: V1.9.0
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "dsp/basic_math_functions_f16.h"
|
||||
|
||||
/**
|
||||
@ingroup groupMath
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
@addtogroup BasicAdd
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point vector addition.
|
||||
@param[in] pSrcA points to first input vector
|
||||
@param[in] pSrcB points to second input vector
|
||||
@param[out] pDst points to output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
void arm_add_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
|
||||
f16x8_t vec1;
|
||||
f16x8_t vec2;
|
||||
f16x8_t res;
|
||||
|
||||
/* Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 3U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = A + B */
|
||||
|
||||
/* Add and then store the results in the destination buffer. */
|
||||
vec1 = vld1q(pSrcA);
|
||||
vec2 = vld1q(pSrcB);
|
||||
res = vaddq(vec1, vec2);
|
||||
vst1q(pDst, res);
|
||||
|
||||
/* Increment pointers */
|
||||
pSrcA += 8;
|
||||
pSrcB += 8;
|
||||
pDst += 8;
|
||||
|
||||
/* Decrement the loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Tail */
|
||||
blkCnt = blockSize & 0x7;
|
||||
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
/* C = A + B */
|
||||
mve_pred16_t p0 = vctp16q(blkCnt);
|
||||
vec1 = vld1q(pSrcA);
|
||||
vec2 = vld1q(pSrcB);
|
||||
vstrhq_p(pDst, vaddq(vec1,vec2), p0);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#else
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
void arm_add_f16(
|
||||
const float16_t * pSrcA,
|
||||
const float16_t * pSrcB,
|
||||
float16_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
|
||||
#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
/* Loop unrolling: Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = A + B */
|
||||
|
||||
/* Add and store result in destination buffer. */
|
||||
*pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++);
|
||||
*pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++);
|
||||
*pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++);
|
||||
*pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++);
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Loop unrolling: Compute remaining outputs */
|
||||
blkCnt = blockSize % 0x4U;
|
||||
|
||||
#else
|
||||
|
||||
/* Initialize blkCnt with number of samples */
|
||||
blkCnt = blockSize;
|
||||
|
||||
#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = A + B */
|
||||
|
||||
/* Add and store result in destination buffer. */
|
||||
*pDst++ = (_Float16)(*pSrcA++) + (_Float16)(*pSrcB++);
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* defined(ARM_FLOAT16_SUPPORTED) */
|
||||
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
/**
|
||||
@} end of BasicAdd group
|
||||
*/
|
||||
@@ -1,199 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_add_f32.c
|
||||
* Description: Floating-point vector addition
|
||||
*
|
||||
* $Date: 23 April 2021
|
||||
* $Revision: V1.9.0
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
|
||||
/**
|
||||
@ingroup groupMath
|
||||
*/
|
||||
|
||||
/**
|
||||
@defgroup BasicAdd Vector Addition
|
||||
|
||||
Element-by-element addition of two vectors.
|
||||
|
||||
<pre>
|
||||
pDst[n] = pSrcA[n] + pSrcB[n], 0 <= n < blockSize.
|
||||
</pre>
|
||||
|
||||
There are separate functions for floating-point, Q7, Q15, and Q31 data types.
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup BasicAdd
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point vector addition.
|
||||
@param[in] pSrcA points to first input vector
|
||||
@param[in] pSrcB points to second input vector
|
||||
@param[out] pDst points to output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
void arm_add_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
|
||||
f32x4_t vec1;
|
||||
f32x4_t vec2;
|
||||
f32x4_t res;
|
||||
|
||||
/* Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = A + B */
|
||||
|
||||
/* Add and then store the results in the destination buffer. */
|
||||
vec1 = vld1q(pSrcA);
|
||||
vec2 = vld1q(pSrcB);
|
||||
res = vaddq(vec1, vec2);
|
||||
vst1q(pDst, res);
|
||||
|
||||
/* Increment pointers */
|
||||
pSrcA += 4;
|
||||
pSrcB += 4;
|
||||
pDst += 4;
|
||||
|
||||
/* Decrement the loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Tail */
|
||||
blkCnt = blockSize & 0x3;
|
||||
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
/* C = A + B */
|
||||
mve_pred16_t p0 = vctp32q(blkCnt);
|
||||
vec1 = vld1q(pSrcA);
|
||||
vec2 = vld1q(pSrcB);
|
||||
vstrwq_p(pDst, vaddq(vec1,vec2), p0);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#else
|
||||
void arm_add_f32(
|
||||
const float32_t * pSrcA,
|
||||
const float32_t * pSrcB,
|
||||
float32_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
|
||||
#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
f32x4_t vec1;
|
||||
f32x4_t vec2;
|
||||
f32x4_t res;
|
||||
|
||||
/* Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = A + B */
|
||||
|
||||
/* Add and then store the results in the destination buffer. */
|
||||
vec1 = vld1q_f32(pSrcA);
|
||||
vec2 = vld1q_f32(pSrcB);
|
||||
res = vaddq_f32(vec1, vec2);
|
||||
vst1q_f32(pDst, res);
|
||||
|
||||
/* Increment pointers */
|
||||
pSrcA += 4;
|
||||
pSrcB += 4;
|
||||
pDst += 4;
|
||||
|
||||
/* Decrement the loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Tail */
|
||||
blkCnt = blockSize & 0x3;
|
||||
|
||||
#else
|
||||
#if defined (ARM_MATH_LOOPUNROLL) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
/* Loop unrolling: Compute 4 outputs at a time */
|
||||
blkCnt = blockSize >> 2U;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = A + B */
|
||||
|
||||
/* Add and store result in destination buffer. */
|
||||
*pDst++ = (*pSrcA++) + (*pSrcB++);
|
||||
*pDst++ = (*pSrcA++) + (*pSrcB++);
|
||||
*pDst++ = (*pSrcA++) + (*pSrcB++);
|
||||
*pDst++ = (*pSrcA++) + (*pSrcB++);
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/* Loop unrolling: Compute remaining outputs */
|
||||
blkCnt = blockSize % 0x4U;
|
||||
|
||||
#else
|
||||
|
||||
/* Initialize blkCnt with number of samples */
|
||||
blkCnt = blockSize;
|
||||
|
||||
#endif /* #if defined (ARM_MATH_LOOPUNROLL) */
|
||||
#endif /* #if defined(ARM_MATH_NEON) */
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = A + B */
|
||||
|
||||
/* Add and store result in destination buffer. */
|
||||
*pDst++ = (*pSrcA++) + (*pSrcB++);
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
}
|
||||
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
/**
|
||||
@} end of BasicAdd group
|
||||
*/
|
||||
@@ -1,75 +0,0 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_add_f64.c
|
||||
* Description: Floating-point vector addition
|
||||
*
|
||||
* $Date: 13 September 2021
|
||||
* $Revision: V1.10.0
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
|
||||
/**
|
||||
@ingroup groupMath
|
||||
*/
|
||||
|
||||
/**
|
||||
@addtogroup BasicAdd
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
@brief Floating-point vector addition.
|
||||
@param[in] pSrcA points to first input vector
|
||||
@param[in] pSrcB points to second input vector
|
||||
@param[out] pDst points to output vector
|
||||
@param[in] blockSize number of samples in each vector
|
||||
@return none
|
||||
*/
|
||||
|
||||
void arm_add_f64(
|
||||
const float64_t * pSrcA,
|
||||
const float64_t * pSrcB,
|
||||
float64_t * pDst,
|
||||
uint32_t blockSize)
|
||||
{
|
||||
uint32_t blkCnt; /* Loop counter */
|
||||
|
||||
/* Initialize blkCnt with number of samples */
|
||||
blkCnt = blockSize;
|
||||
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
/* C = A + B */
|
||||
|
||||
/* Add and store result in destination buffer. */
|
||||
*pDst++ = (*pSrcA++) + (*pSrcB++);
|
||||
|
||||
/* Decrement loop counter */
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
@} end of BasicAdd group
|
||||
*/
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user