Commit Graph

99416 Commits

Author SHA1 Message Date
Bas Nieuwenhuizen
d956e0bdf5 radv: Fix ordering issue in meta memory allocation failure path.
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-01-22 00:07:03 +01:00
Lucas Stach
29a0ea699a etnaviv: dirty TS state when framebuffer has changed
When switching between framebuffers with and without TS, the TS state
needs to be flushed to the command stream even if the derived state
isn't changed.

Fixes: 4ee7c2c284 ("etnaviv: enable TS, but disable autodisable")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-01-21 12:58:02 +01:00
Vinson Lee
e03c880971 broadcom/vc5: Fix source file name.
Fixes: c9b2cb7897 ("vc5: add missing files to the tarball")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-01-21 11:13:16 +08:00
Vinson Lee
14abbe604b broadcom/vc5: Add missing include paths.
Fixes: 954a704da3 ("broadcom/vc5: Port the RCL setup to V3D4.1.")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-01-21 11:05:33 +08:00
Eric Anholt
f398aa6aef mesa: Only require independent blending for GLES 3.2.
We've been requiring this since GLES 3.0 was introduced, but the GLES 3.2
spec is the one that has "Supporting blending on a per-draw-buffer basis"
in the new features.  V3D 3.3 would require lowering blending to shader
code to implement independent blending.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-01-21 10:48:00 +08:00
Kenneth Graunke
60d8fe9216 i965: Delete completely bogus comment
This hasn't been true in 6+ years, if it was even true then.  Before
we rewrote the compiler and introduced GLSL IR in 2010-2011, i965 used
to have two compiler backends for WM programs, based on Mesa IR.  One
handled flow control and was SIMD8-only, while the other was SIMD16
only and didn't handle flow control.  Or something like that.

Even then, this certainly didn't handle vertex shaders, so "all ...
code generation" is a bit strong.
2018-01-20 01:31:25 -08:00
Dylan Baker
436ed65d38 autotools: include meson build files in tarball
This adds the meson.build, meson_options.txt, and a few scripts that are
used exclusively by the meson build.

v2: - Remove accidentally included changes needed to test make dist with
      LLVM > 3.9

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-19 16:30:51 -08:00
George Kyriazis
9d80ed0862 swr/rast: Fix llvm5 behavior
For some reason llvm5 is picky about accepting a void * type in the
case of building an argument list.

Since we don't care about the type (we ignore the argument for now),
pick another pointer type

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 17:08:30 -06:00
George Kyriazis
d335b32baf swr/rast: Enable early rasterization
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:43 -06:00
George Kyriazis
bacfbe5a32 swr/rast: Implement Early Rasterization optimization
Early Rasterization is an optimization for small triangles.

Scientific workloads often contain very small triangles that has non-zero
area and cannot be trivially rejected as falling between pixel centers,
but does not cover any pixel center. Those triangles can be initially
rasterized as early as in binner and rejected if they cover no pixels The
optimization can be disabled in compilation using KNOB_ENABLE_EARLY_RAST
option in knobs.h

The Early Rast is disabled by default.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:43 -06:00
George Kyriazis
be3cd7add1 swr/rast: Enable simd16 vertex shaders
Flip the switch(es) to enable simd16 vertex shaders:

USE_SIMD16_SHADERS and USE_SIMD16_VS

Both have to be enabled at the same time.  Currently, just setting
USE_SIMD16_SHADERS does not work correctly.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:42 -06:00
George Kyriazis
8c83d2d371 swr: Support simd16 vertex shaders
Supporting simd16 vertex shaders involves packing the output of the
fetch shader appropriately, especially the vertexID buffers that have to
be formatted in one simd16 register, needed by the VS.

As part of this support, we needed to remove the 2nd JitManager, since it
was not accounting for vector width correctly.

USE_SIMD16_SHADERS is also split into two defines.  The additional
one (USE_SIMD16_VS) controls the width of the vertex shader (VS), while
the original one (USE_SIMD16_SHADERS) controls overall front end width.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:42 -06:00
George Kyriazis
1874d95a8e swr/rast: changed jit debug magic number
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:41 -06:00
George Kyriazis
c719f62621 swr/rast: Added ICLAMP builder function
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:41 -06:00
George Kyriazis
f192502001 swr/rast: Jit debug work
Properly validate DLL matches OBJ for jitted function

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:41 -06:00
George Kyriazis
3c405e32b0 swr/rast: silence generated file warnings
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:40 -06:00
George Kyriazis
fe107e3c17 swr/rast: jit shader lib debug work
Create shader_lib during build, link with shaders at DLL generation time

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:40 -06:00
George Kyriazis
0cd9ad98a3 swr/rast: AVX-512 changes to enable 16-wide VS
Add a new define (USE_SIMD16_VS), to denote calling a 16-wide vertex shader.
This is needed because the mesa driver can do 16-wide shaders, but rasty
cannot yet, so we need to distinguish.

Create a new VertexID entry (VertexID16) for the USE_SIMD16_VS case, since
we need to format the vertex id in a way that is digestible by the 16-wide VS

Disabled for now.  To be enabled in a future checkin when driver work
is complete.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:40 -06:00
George Kyriazis
3140e714d2 swr/rast: x86 autogenerated macro work
Add name argument to x86 autogenerated macros.
Add useful variable names for DCL_inputVec implementation.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:39 -06:00
George Kyriazis
4cd6e2ebfd swr/rast: Shorten some filenames
in shader and fetch dump files

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:39 -06:00
George Kyriazis
3936044d07 swr/rast: work supporting optimizations in Debug builds.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:38 -06:00
George Kyriazis
c4a42f5add swr/rast: Add debugging type support for function types.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:38 -06:00
George Kyriazis
e9e7f3ce0a swr/rast: Shader debugging work
- Move debug .ll files to JIT_CACHE_DIR
- Don't link against jitter SRGBLut table, add global data to shader that needs it.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:34 -06:00
George Kyriazis
34bbcb5052 swr/rast: Debug Symbols work
Added support for Fetch / Sample / LD functions
Added DLL link to JitCache implementation

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:30 -06:00
George Kyriazis
01ab218bbc swr/rast: Initial work for debugging support.
Adds ability to step into jitted llvm IR in Visual Studio.
- Updated llvm type generation script to also generate corresponding debug types.
- New module pass inserts debug metadata into the IR for each function

Disabled by default.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:52:22 -06:00
George Kyriazis
4660e13152 swr/rast: Add private state parameter in fetcher
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:48:41 -06:00
George Kyriazis
079ae3c48d swr/rast: Added missing define for Linux/gcc
+ ZeroMemory() macro definition for non win32-compilation in common/os.h

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:48:41 -06:00
George Kyriazis
70f8eac603 swr/rast: Fix one more invalid object format for windows.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:48:41 -06:00
Bas Nieuwenhuizen
61a790409e radv: Always re-emit the sample position offset user SGPR.
The user SGPR location can change between pipelines, so we need to
emit it again to the pottentially changed SGPR index.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 23:35:12 +01:00
Bas Nieuwenhuizen
dbf1e918cd radv: emit pa_sc_mode_cntl_0 with multisample state.
We don't have the meta kludge with 0 viewports anymore,
so we can always enable them.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-01-19 23:35:12 +01:00
Kenneth Graunke
c7dcee58b5 i965: Avoid problems from referencing orphaned BOs after growing.
Growing the batch/state buffer is a lot more dangerous than I thought.

A number of places emit multiple state buffer sections, and then write
data to the returned pointer, or save a pointer to brw->batch.state.bo
and then use it in relocations.  If each call can grow, this can result
in stale map references or stale BO pointers.  Furthermore, fences refer
to the old batch BO, and that reference needs to continue working.

To avoid these woes, we avoid ever swapping the brw->batch.*.bo pointer,
instead exchanging the brw_bo structures in place.  That way, stale BO
references are fine - the GEM handle changes, but the brw_bo pointer
doesn't.  We also defer the memcpy until a quiescent point, so callers
can write to the returned pointer - which may be in either BO - and
we'll sort it out and combine the two properly in the end.

v2/v3:
- Handle stale pointers in the shadow copy case, where realloc may or
  may not move our shadow copy to a new address.
- Track the partial map explicitly, to avoid problems with buffer reuse
  where multiple map modes exist (caught by Chris Wilson).

v4:
- Don't use realloc in the CPU shadow case, it isn't safe.

Fixes: 2dfc119f22 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> [v3]
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2018-01-19 11:30:10 -08:00
Kenneth Graunke
8a5bc304ff i965: Rename 'aux' to 'prog_data' in program cache.
'aux' is a very generic name, suggesting it can be a bunch of things.
However, it's always the brw_*_prog_data structure.  So, call it that.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-01-19 11:29:47 -08:00
Chuck Atkins
a4be2bcee2 swr: allow a single swr architecture to be builtin
Part 2 of 2 (part 1 is autoconf changes, part 2 is C++ changes)

When only a single SWR architecture is being used, this allows that
architecture to be builtin rather than as a separate libswrARCH.so that
gets loaded via dlopen.  Since there are now several different code
paths for each detected CPU architecture, the log output is also
adjusted to convey where the backend is getting loaded from.

This allows SWR to be used for static mesa builds which are still
important for large HPC environments where shared libraries can impose
unacceptable application startup times as hundreds of thousands of copies
of the libs are loaded from a shared parallel filesystem.

Based on an initial implementation by Tim Rowley.

v2: Refactor repetitive preprocessor checks to reduce code duplication
v3: Formatting changes per Bruce C. Also delay screen creation until end
    to avoid leaks when failure conditions are hit.

Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
CC: Tim Rowley <timothy.o.rowley@intel.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 13:16:00 -06:00
Chuck Atkins
2ed8b6f827 swr: (autoconf) allow a single swr architecture to be builtin
Part 1 of 2 (part 1 is autoconf changes, part 2 is C++ changes)

When only a single SWR architecture is being used, this allows that
architecture to be builtin rather than as a separate libswrARCH.so that
gets loaded via dlopen.  Since there are now several different code
paths for each detected CPU architecture, the log output is also
adjusted to convey where the backend is getting loaded from.

This allows SWR to be used for static mesa builds which are still
important for large HPC environments where shared libraries can impose
unacceptable application startup times as hundreds of thousands of copies
of the libs are loaded from a shared parallel filesystem.

Based on an initial implementation by Tim Rowley.

v2: Fix comment placement pointed out by Bruce C.

Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
CC: Tim Rowley <timothy.o.rowley@intel.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 13:15:54 -06:00
Greg V
8ff8c82630 swr: fix clang 5 null cast warning
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2018-01-19 16:15:56 +00:00
Gert Wollny
ea89843b3d mesa/program: Fix -Wunused-param warning
v2: Don't annotate, but remove the unused ctx parameter

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-01-19 15:45:57 +00:00
Gert Wollny
81d8a0f4a4 mesa/program/prog_execute.c: Silence -Wunused-param
v2: Don't annotate, but remove the unused ctx parameter

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-19 15:45:57 +00:00
Gert Wollny
fef4b16523 mesa: Make numSamples an unsigned int
As a followup to the previous patch propagate the change of numSamples
from int to unsigned to gl_config::samples and consequently fix some
-Wsign-compare warnings.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-01-19 15:45:57 +00:00
Gert Wollny
d0e37599ab gallium: Make (num_)samples an unsigned int
According to the ARB_multisample num_samples is a non-negative integer.
Consequently define it as such, fail in glx/choose_visual if a negative
number is given.

v2: split patch into gallium and mesa part

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-19 15:45:57 +00:00
Andres Gomez
7a2c87177a docs: correct a typo in releasing instructions
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-19 15:25:53 +02:00
Andres Gomez
7760566ab7 docs: move untar line in basic testing instructions for coherence
For scons, windows/mingw dealing with LLVM_CONFIG is done before
untarring. This is also more convenient for copy and paste.

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-19 15:25:39 +02:00
Andres Gomez
bd8537fa71 docs: add a notice whenever a release is the final in a series
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-19 15:25:27 +02:00
Andres Gomez
b910eec489 docs: add final release note for 17.2.8
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-19 15:25:20 +02:00
Andres Gomez
4b50cfef44 docs: add final release note for 17.1.10
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-01-19 15:20:57 +02:00
Grazvydas Ignotas
e6abc613e2 st/vdpau: release held lock in error path
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2018-01-19 13:30:22 +02:00
Juan A. Suarez Romero
302ff82434 docs: update calendar, add news and link release notes to 17.3.3
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2018-01-19 10:46:18 +01:00
Juan A. Suarez Romero
059db12097 docs: add sha256 checksums for 17.3.3
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit bc1503b13fcf8190262757ea7f86613e14e25981)
2018-01-19 10:46:18 +01:00
Juan A. Suarez Romero
3205a45fc3 docs: add release notes for 17.3.3
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 80f5f279b3f9fc752ba35b1cb2878a936f8ace90)
2018-01-19 10:46:18 +01:00
Samuel Iglesias Gonsálvez
7109a1fe13 anv: avoid segmentation fault due to vk_error()
vk_error() is a macro that calls __vk_errorf() with instance == NULL.

Then, __vk_errorf() passes a pointer to instance->debug_report_callbacks
to vk_debug_error(), which segfaults as this pointer is invalid but not
NULL.

Fixes: e5b1bd6ab8 "vulkan: move anv VK_EXT_debug_report implementation to common code."

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-01-19 09:39:05 +01:00
Bas Nieuwenhuizen
32170d87e3 ac/nir: Fix vector extraction if source vector has >4 elements.
v2: Add forgotten argument and start offset.

Fixes: 91074bb11b "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-01-19 02:00:28 +01:00