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Auto merge of #99443 - jam1garner:mips-virt-feature, r=nagisa

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Add support for MIPS VZ ISA extension

[Link to relevant LLVM line where virt extension is specified](https://github.com/llvm/llvm-project/blob/83fab8cee9d6b9fa911195c20325b4512a7a22ef/llvm/lib/Target/Mips/Mips.td#L172-L173)

This has been tested on mips-unknown-linux-musl with a target-cpu that is >= MIPS32 5 and `target-features=+virt`. The example was checked in a disassembler to ensure the correct assembly sequence was being generated using the virtualization instructions.

Needed additional work:

* MIPS is missing from [the Rust reference CPU feature lists](https://doc.rust-lang.org/reference/attributes/codegen.html#available-features)

Example docs for later:

```md
#### `mips` or `mips64`

This platform requires that `#[target_feature]` is only applied to [`unsafe`
functions][unsafe function]. This target's feature support is currently unstable
and must be enabled by `#![feature(mips_target_feature)]` ([Issue #44839])

[Issue #44839]: https://github.com/rust-lang/rust/issues/44839

Further documentation on these features can be found in the [MIPS Instruction Set
Reference Manual], or elsewhere on [mips.com].

[MIPS Instruction Set Reference Manual]: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00086-2B-MIPS32BIS-AFP-6.06.pdf
[developer.arm.com]: https://www.mips.com/products/architectures/ase/

Feature        | Implicitly Enables | Description
---------------|--------------------|-------------------
`fp64`         |                    | 64-bit Floating Point
`msa`          |                    | "MIPS SIMD Architecture"
`virt`         |                    | Virtualization instructions (VZ ASE)
```

If the above is good I can also submit a PR for that if there's interest in documenting it while it's still unstable. Otherwise that can be dropped, I just wrote it before realizing it was possibly not a good idea.

Relevant to #44839
This commit is contained in:
bors
2022-09-14 08:21:25 +00:00
parent a0d1df4a5d bec3a545a5
commit c97922dca5
2 changed files with 9 additions and 2 deletions
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compiler/rustc_codegen_llvm/src/llvm_util.rs
+4
View File
@@ -154,6 +154,10 @@ pub fn time_trace_profiler_finish(file_name: &Path) {
//
// To find a list of LLVM's names, check llvm-project/llvm/include/llvm/Support/*TargetParser.def
// where the * matches the architecture's name
//
// For targets not present in the above location, see llvm-project/llvm/lib/Target/{ARCH}/*.td
// where `{ARCH}` is the architecture name. Look for instances of `SubtargetFeature`.
//
// Beware to not use the llvm github project for this, but check the git submodule
// found in src/llvm-project
// Though note that Rust can also be build with an external precompiled version of LLVM
compiler/rustc_codegen_ssa/src/target_features.rs
+5 -2
View File
@@ -210,8 +210,11 @@ const POWERPC_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
("vsx", Some(sym::powerpc_target_feature)),
];
const MIPS_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] =
&[("fp64", Some(sym::mips_target_feature)), ("msa", Some(sym::mips_target_feature))];
const MIPS_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
("fp64", Some(sym::mips_target_feature)),
("msa", Some(sym::mips_target_feature)),
("virt", Some(sym::mips_target_feature)),
];
const RISCV_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
("m", Some(sym::riscv_target_feature)),