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docs: Remove ARM64 HTML files
HTML files are not needed to build Ballistic, only the XML files. Signed-off-by: Ronald Caesar <github43132@proton.me>
This commit is contained in:
Ronald Caesar
@@ -1,539 +0,0 @@
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<title>Signal 0.125</title>
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<title>Sheet.38</title>
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<title>Sheet.39</title>
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<title>Sheet.17</title>
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<title>Sheet.18</title>
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<g id="shape21-73" v:mID="21" v:groupContext="shape" transform="translate(232.981,0.25) rotate(90)">
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<title>Signal 0.125</title>
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<title>Disconnect.22</title>
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<title>Sheet.38</title>
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<title>Sheet.39</title>
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<desc>63</desc>
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<desc>56</desc>
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<title>Sheet.45</title>
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</g>
|
||||
</svg>
|
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Before Width: | Height: | Size: 26 KiB |
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<?xml version="1.0" encoding="utf-8"?>
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
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<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ABS</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ABS</h2><p>Absolute value (predicated)</p><p class="aml">Compute the absolute value of the signed integer in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td class="r">0</td><td class="l">1</td><td class="r">1</td><td class="lr">0</td><td class="l">1</td><td>0</td><td class="r">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="abs_z_p_z_"/><p class="asm-code">ABS <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
integer element = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
|
||||
element = <a href="shared_pseudocode.html#impl-shared.Abs.1" title="function: integer Abs(integer x)">Abs</a>(element);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element<esize-1:0>;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,38 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADCLB</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADCLB</h2><p>Add with carry long (bottom)</p><p class="aml">Add the even-numbered elements of the first source vector and the 1-bit carry from the least-significant bit of the odd-numbered elements of the second source vector to the even-numbered elements of the destination and accumulator vector. The 1-bit carry output is placed in the corresponding odd-numbered element of the destination vector.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">sz</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="l">1</td><td>1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zda</td></tr><tr class="secondrow"><td colspan="8"/><td/><td/><td/><td colspan="5"/><td colspan="5"/><td class="droppedname">T</td><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="adclb_z_zzz_"/><p class="asm-code">ADCLB <a href="#sa_zda" title="Third source and destination scalable vector register (field "Zda")"><Zda></a>.<a href="#sa_t" title="Size specifier (field "sz") [D,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "sz") [D,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "sz") [D,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 32 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zda);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zda></td><td><a id="sa_zda"/><p class="aml">Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>sz</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">sz</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">0</td><td class="symbol">S</td></tr><tr><td class="bitfield">1</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer pairs = VL DIV (esize * 2);
|
||||
bits(VL) operand = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) carries = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
|
||||
|
||||
for p = 0 to pairs-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, 2*p + 0, esize];
|
||||
bits(esize) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*p + 0, esize];
|
||||
bit carry_in = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[carries, 2*p + 1, esize]<0>;
|
||||
|
||||
(res, nzcv) = <a href="shared_pseudocode.html#impl-shared.AddWithCarry.3" title="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(element1, element2, carry_in);
|
||||
carry_out = nzcv<1>;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p + 0, esize] = res;
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p + 1, esize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(carry_out, esize);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,38 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADCLT</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADCLT</h2><p>Add with carry long (top)</p><p class="aml">Add the odd-numbered elements of the first source vector and the 1-bit carry from the least-significant bit of the odd-numbered elements of the second source vector to the even-numbered elements of the destination and accumulator vector. The 1-bit carry output is placed in the corresponding odd-numbered element of the destination vector.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">sz</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="l">1</td><td>1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr">1</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zda</td></tr><tr class="secondrow"><td colspan="8"/><td/><td/><td/><td colspan="5"/><td colspan="5"/><td class="droppedname">T</td><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="adclt_z_zzz_"/><p class="asm-code">ADCLT <a href="#sa_zda" title="Third source and destination scalable vector register (field "Zda")"><Zda></a>.<a href="#sa_t" title="Size specifier (field "sz") [D,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "sz") [D,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "sz") [D,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 32 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zda);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zda></td><td><a id="sa_zda"/><p class="aml">Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>sz</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">sz</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">0</td><td class="symbol">S</td></tr><tr><td class="bitfield">1</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer pairs = VL DIV (esize * 2);
|
||||
bits(VL) operand = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) carries = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
|
||||
|
||||
for p = 0 to pairs-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, 2*p + 0, esize];
|
||||
bits(esize) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*p + 1, esize];
|
||||
bit carry_in = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[carries, 2*p + 1, esize]<0>;
|
||||
|
||||
(res, nzcv) = <a href="shared_pseudocode.html#impl-shared.AddWithCarry.3" title="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(element1, element2, carry_in);
|
||||
carry_out = nzcv<1>;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p + 0, esize] = res;
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p + 1, esize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(carry_out, esize);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,37 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADD (vectors, predicated)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADD (vectors, predicated)</h2><p>Add vectors (predicated)</p><p class="aml">Add active elements of the second source vector to corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>0</td><td class="r">0</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td class="l">0</td><td>0</td><td class="r">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="5">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="add_z_p_zz_"/><p class="asm-code">ADD <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,34 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADD (immediate)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADD (immediate)</h2><p>Add immediate (unpredicated)</p><p class="aml">Add an unsigned immediate to each element of the source vector, and destructively place the results in the corresponding elements of the source vector. This instruction is unpredicated.</p><p class="aml">The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280.</p><p class="aml">The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "#<uimm8>, LSL #8". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "#0, LSL #8".</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="l">1</td><td>0</td><td class="r">0</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td class="l">1</td><td class="r">1</td><td class="lr">sh</td><td class="lr" colspan="8">imm8</td><td class="lr" colspan="5">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="add_z_zi_"/><p class="asm-code">ADD <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, #<a href="#sa_imm" title="Unsigned immediate [0-255] (field "imm8")"><imm></a>{, <a href="#sa_shift" title="Optional left shift to apply to the immediate, default LSL #0 (field "sh") [LSL #0,LSL #8]"><shift></a>}</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size:sh == '001' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(imm8);
|
||||
if sh == '1' then imm = imm << 8;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><imm></td><td><a id="sa_imm"/><p class="aml">Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><shift></td><td><a id="sa_shift"/><p>Is the optional left shift to apply to the immediate, defaulting to LSL #0 and
|
||||
encoded in
|
||||
<q>sh</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">sh</th><th class="symbol"><shift></th></tr></thead><tbody><tr><td class="bitfield">0</td><td class="symbol">LSL #0</td></tr><tr><td class="bitfield">1</td><td class="symbol">LSL #8</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + imm;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,30 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADD (vectors, unpredicated)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADD (vectors, unpredicated)</h2><p>Add vectors (unpredicated)</p><p class="aml">Add all elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. This instruction is unpredicated.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">0</td><td>0</td><td class="r">0</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="add_z_zz_"/><p class="asm-code">ADD <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,46 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADDHA</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADDHA</h2><p>Add horizontally vector elements to ZA tile</p><p class="aml">Add each element of the source vector to the corresponding active element of each horizontal slice of a ZA tile. The tile elements are predicated by a pair of governing predicates. An element of a horizontal slice is considered active if its corresponding element in the second governing predicate is TRUE and the element corresponding to its horizontal slice number in the first governing predicate is TRUE. Inactive elements in the destination tile remain unmodified.</p><p class="aml">ID_AA64SMFR0_EL1.I16I64 indicates whether the 64-bit integer variant is implemented.</p><p class="desc">
|
||||
It has encodings from 2 classes:
|
||||
<a href="#iclass_per_word">32-bit</a>
|
||||
and
|
||||
<a href="#iclass_per_doubleword">64-bit</a></p><h3 class="classheading"><a id="iclass_per_word"/>32-bit<span style="font-size:smaller;"><br/>(FEAT_SME)
|
||||
</span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="l">0</td><td class="r">1</td><td class="l">0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="3">Pm</td><td class="lr" colspan="3">Pn</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="2">ZAda</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="7"/><td/><td colspan="2"/><td colspan="3"/><td class="droppedname">V</td><td colspan="3"/><td colspan="3"/><td colspan="5"/><td/><td/><td/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addha_za_pp_z_32"/><p class="asm-code">ADDHA <a href="#sa_zada" title="ZA tile ZA0-ZA3 (field "ZAda")"><ZAda></a>.S, <a href="#sa_pn" title="First governing scalable predicate register P0-P7 (field "Pn")"><Pn></a>/M, <a href="#sa_pm" title="Second governing scalable predicate register P0-P7 (field "Pm")"><Pm></a>/M, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.S</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 32;
|
||||
integer a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAda);</p><h3 class="classheading"><a id="iclass_per_doubleword"/>64-bit<span style="font-size:smaller;"><br/>(FEAT_SME_I16I64)
|
||||
</span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="l">0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="3">Pm</td><td class="lr" colspan="3">Pn</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">ZAda</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="7"/><td/><td colspan="5"/><td class="droppedname">V</td><td colspan="3"/><td colspan="3"/><td colspan="5"/><td/><td/><td colspan="3"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addha_za_pp_z_64"/><p class="asm-code">ADDHA <a href="#sa_zada_1" title="ZA tile ZA0-ZA7 (field "ZAda")"><ZAda></a>.D, <a href="#sa_pn" title="First governing scalable predicate register P0-P7 (field "Pn")"><Pn></a>/M, <a href="#sa_pm" title="Second governing scalable predicate register P0-P7 (field "Pm")"><Pm></a>/M, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSMEI16I64.0" title="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
|
||||
constant integer esize = 64;
|
||||
integer a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAda);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><ZAda></td><td><a id="sa_zada"/><p class="aml">For the 32-bit variant: is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field.</p></td></tr><tr><td/><td><a id="sa_zada_1"/><p class="aml">For the 64-bit variant: is the name of the ZA tile ZA0-ZA7, encoded in the "ZAda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pn></td><td><a id="sa_pn"/><p class="aml">Is the name of the first governing scalable predicate register P0-P7, encoded in the "Pn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pm></td><td><a id="sa_pm"/><p class="aml">Is the name of the second governing scalable predicate register P0-P7, encoded in the "Pm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckStreamingSVEAndZAEnabled.0" title="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer dim = VL DIV esize;
|
||||
bits(PL) mask1 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[a, PL];
|
||||
bits(PL) mask2 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[b, PL];
|
||||
bits(VL) operand_src = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(dim*dim*esize) operand_acc = <a href="shared_pseudocode.html#impl-aarch64.ZAtile.read.3" title="accessor: bits(width) ZAtile[integer tile, integer esize, integer width]">ZAtile</a>[da, esize, dim*dim*esize];
|
||||
bits(dim*dim*esize) result;
|
||||
|
||||
for col = 0 to dim-1
|
||||
bits(esize) element = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand_src, col, esize];
|
||||
for row = 0 to dim-1
|
||||
bits(esize) res = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand_acc, row*dim+col, esize];
|
||||
if (<a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask1, row, esize) &&
|
||||
<a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask2, col, esize)) then
|
||||
res = res + element;
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, row*dim+col, esize] = res;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.ZAtile.write.3" title="accessor: ZAtile[integer tile, integer esize, integer width] = bits(width) value">ZAtile</a>[da, esize, dim*dim*esize] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate registers contain the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate registers contain the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,37 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADDHNB</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADDHNB</h2><p>Add narrow high part (bottom)</p><p class="aml">Add each vector element of the first source vector to the corresponding vector element of the second source vector, and place the most significant half of the result in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. This instruction is unpredicated.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td colspan="3"/><td class="droppedname">S</td><td class="droppedname">R</td><td class="droppedname">T</td><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addhnb_z_zz_"/><p class="asm-code">ADDHNB <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_tb" title="Size specifier (field "size") [D,H,S]"><Tb></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_tb" title="Size specifier (field "size") [D,H,S]"><Tb></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '00' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">RESERVED</td></tr><tr><td class="bitfield">01</td><td class="symbol">B</td></tr><tr><td class="bitfield">10</td><td class="symbol">H</td></tr><tr><td class="bitfield">11</td><td class="symbol">S</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Tb></td><td><a id="sa_tb"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><Tb></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">RESERVED</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
constant integer halfesize = esize DIV 2;
|
||||
|
||||
for e = 0 to elements-1
|
||||
integer element1 = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
|
||||
integer element2 = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
|
||||
integer res = (element1 + element2) >> halfesize;
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*e + 0, halfesize] = res<halfesize-1:0>;
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*e + 1, halfesize] = <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(halfesize);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,36 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADDHNT</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADDHNT</h2><p>Add narrow high part (top)</p><p class="aml">Add each vector element of the first source vector to the corresponding vector element of the second source vector, and place the most significant half of the result in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. This instruction is unpredicated.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td colspan="3"/><td class="droppedname">S</td><td class="droppedname">R</td><td class="droppedname">T</td><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addhnt_z_zz_"/><p class="asm-code">ADDHNT <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_tb" title="Size specifier (field "size") [D,H,S]"><Tb></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_tb" title="Size specifier (field "size") [D,H,S]"><Tb></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '00' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">RESERVED</td></tr><tr><td class="bitfield">01</td><td class="symbol">B</td></tr><tr><td class="bitfield">10</td><td class="symbol">H</td></tr><tr><td class="bitfield">11</td><td class="symbol">S</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Tb></td><td><a id="sa_tb"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><Tb></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">RESERVED</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
|
||||
constant integer halfesize = esize DIV 2;
|
||||
|
||||
for e = 0 to elements-1
|
||||
integer element1 = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
|
||||
integer element2 = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
|
||||
integer res = (element1 + element2) >> halfesize;
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*e + 1, halfesize] = res<halfesize-1:0>;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,44 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADDP</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADDP</h2><p>Add pairwise</p><p class="aml">Add pairs of adjacent elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr">1</td><td class="l">1</td><td>0</td><td class="r">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="5">Zdn</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td colspan="3"/><td/><td/><td class="droppedname">U</td><td colspan="3"/><td colspan="3"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addp_z_p_zz_"/><p class="asm-code">ADDP <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
integer element1;
|
||||
integer element2;
|
||||
|
||||
for e = 0 to elements-1
|
||||
if !<a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
else
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.IsEven.1" title="function: boolean IsEven(integer val)">IsEven</a>(e) then
|
||||
element1 = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e + 0, esize]);
|
||||
element2 = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e + 1, esize]);
|
||||
else
|
||||
element1 = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e - 1, esize]);
|
||||
element2 = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e + 0, esize]);
|
||||
integer res = element1 + element2;
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = res<esize-1:0>;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,23 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
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<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADDPL</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADDPL</h2><p>Add multiple of predicate register size to scalar register</p><p class="aml">Add the current predicate register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer and place the result in the 64-bit destination general-purpose register or current stack pointer.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="5">Rn</td><td class="l">0</td><td>1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr" colspan="6">imm6</td><td class="lr" colspan="5">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addpl_r_ri_"/><p class="asm-code">ADDPL <a href="#sa_xd_sp" title="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a>, <a href="#sa_xn_sp" title="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a>, #<a href="#sa_imm" title="Signed immediate operand [-32-31] (field "imm6")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(imm6);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xd|SP></td><td><a id="sa_xd_sp"/><p class="aml">Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn|SP></td><td><a id="sa_xn_sp"/><p class="aml">Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><imm></td><td><a id="sa_imm"/><p class="aml">Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
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constant integer PL = VL DIV 8;
|
||||
bits(64) operand1 = if n == 31 then <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[] else <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
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bits(64) result = operand1 + (imm * (PL DIV 8));
|
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|
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if d == 31 then
|
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<a href="shared_pseudocode.html#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(64) value">SP</a>[] = result;
|
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else
|
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<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
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<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
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; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
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</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
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@@ -1,43 +0,0 @@
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<?xml version="1.0" encoding="utf-8"?>
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
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<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADDQV</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADDQV</h2><p>Unsigned add reduction of quadword vector segments</p><p class="aml">Unsigned addition of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as zero.</p><h3 class="classheading"><a id="iclass_sve2"/>SVE2<span style="font-size:smaller;"><br/>(FEAT_SVE2p1)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">1</td><td class="l">0</td><td>0</td><td class="r">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Vd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td colspan="4"/><td/><td class="droppedname">U</td><td colspan="3"/><td colspan="3"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addqv_z_p_z_"/><p class="asm-code">ADDQV <a href="#sa_vd" title="Destination SIMD&FP register (field "Vd")"><Vd></a>.<a href="#sa_t" title="Arrangement specifier (field "size") [2D,4S,8H,16B]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_tb" title="Size specifier (field "size") [B,D,H,S]"><Tb></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2p1.0" title="function: boolean HaveSVE2p1()">HaveSVE2p1</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2p1.0" title="function: boolean HaveSME2p1()">HaveSME2p1</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
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integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
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integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
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integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Vd);
|
||||
boolean unsigned = TRUE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Vd></td><td><a id="sa_vd"/><p class="aml">Is the name of the destination SIMD&FP register, encoded in the "Vd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is an arrangement specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">16B</td></tr><tr><td class="bitfield">01</td><td class="symbol">8H</td></tr><tr><td class="bitfield">10</td><td class="symbol">4S</td></tr><tr><td class="bitfield">11</td><td class="symbol">2D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Tb></td><td><a id="sa_tb"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><Tb></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer segments = VL DIV 128;
|
||||
constant integer elempersegment = 128 DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(128) result = <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(128);
|
||||
bits(128) stmp = <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(128);
|
||||
|
||||
integer dtmp;
|
||||
|
||||
for e = 0 to elempersegment-1
|
||||
dtmp = 0;
|
||||
for s = 0 to segments-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, s * elempersegment + e, esize) then
|
||||
stmp = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, s, 128];
|
||||
dtmp = dtmp + <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[stmp, e, esize]);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = dtmp<esize-1:0>;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,24 +0,0 @@
|
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<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
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<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADDSPL</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADDSPL</h2><p>Add multiple of Streaming SVE predicate register size to scalar register</p><p class="aml">Add the Streaming SVE predicate register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer and place the result in the 64-bit destination general-purpose register or current stack pointer.</p><p class="aml">This instruction does not require the PE to be in Streaming SVE mode.</p><h3 class="classheading"><a id="iclass_mortlach"/>SME<span style="font-size:smaller;"><br/>(FEAT_SME)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="5">Rn</td><td class="l">0</td><td>1</td><td>0</td><td>1</td><td class="r">1</td><td class="lr" colspan="6">imm6</td><td class="lr" colspan="5">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addspl_r_ri_"/><p class="asm-code">ADDSPL <a href="#sa_xd_sp" title="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a>, <a href="#sa_xn_sp" title="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a>, #<a href="#sa_imm" title="Signed immediate operand [-32-31] (field "imm6")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(imm6);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xd|SP></td><td><a id="sa_xd_sp"/><p class="aml">Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn|SP></td><td><a id="sa_xn_sp"/><p class="aml">Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><imm></td><td><a id="sa_imm"/><p class="aml">Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSMEEnabled.0" title="function: CheckSMEEnabled()">CheckSMEEnabled</a>();
|
||||
constant integer SVL = <a href="shared_pseudocode.html#impl-aarch64.CurrentSVL.read.none" title="accessor: integer CurrentSVL">CurrentSVL</a>;
|
||||
integer len = imm * (SVL DIV 64);
|
||||
bits(64) operand1 = if n == 31 then <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[] else <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
bits(64) result = operand1 + len;
|
||||
|
||||
if d == 31 then
|
||||
<a href="shared_pseudocode.html#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(64) value">SP</a>[] = result;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,24 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADDSVL</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADDSVL</h2><p>Add multiple of Streaming SVE vector register size to scalar register</p><p class="aml">Add the Streaming SVE vector register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer, and place the result in the 64-bit destination general-purpose register or current stack pointer.</p><p class="aml">This instruction does not require the PE to be in Streaming SVE mode.</p><h3 class="classheading"><a id="iclass_mortlach"/>SME<span style="font-size:smaller;"><br/>(FEAT_SME)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="5">Rn</td><td class="l">0</td><td>1</td><td>0</td><td>1</td><td class="r">1</td><td class="lr" colspan="6">imm6</td><td class="lr" colspan="5">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addsvl_r_ri_"/><p class="asm-code">ADDSVL <a href="#sa_xd_sp" title="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a>, <a href="#sa_xn_sp" title="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a>, #<a href="#sa_imm" title="Signed immediate operand [-32-31] (field "imm6")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(imm6);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xd|SP></td><td><a id="sa_xd_sp"/><p class="aml">Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn|SP></td><td><a id="sa_xn_sp"/><p class="aml">Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><imm></td><td><a id="sa_imm"/><p class="aml">Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSMEEnabled.0" title="function: CheckSMEEnabled()">CheckSMEEnabled</a>();
|
||||
constant integer SVL = <a href="shared_pseudocode.html#impl-aarch64.CurrentSVL.read.none" title="accessor: integer CurrentSVL">CurrentSVL</a>;
|
||||
integer len = imm * (SVL DIV 8);
|
||||
bits(64) operand1 = if n == 31 then <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[] else <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
bits(64) result = operand1 + len;
|
||||
|
||||
if d == 31 then
|
||||
<a href="shared_pseudocode.html#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(64) value">SP</a>[] = result;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,46 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADDVA</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADDVA</h2><p>Add vertically vector elements to ZA tile</p><p class="aml">Add each element of the source vector to the corresponding active element of each vertical slice of a ZA tile. The tile elements are predicated by a pair of governing predicates. An element of a vertical slice is considered active if its corresponding element in the first governing predicate is TRUE and the element corresponding to its vertical slice number in the second governing predicate is TRUE. Inactive elements in the destination tile remain unmodified.</p><p class="aml">ID_AA64SMFR0_EL1.I16I64 indicates whether the 64-bit integer variant is implemented.</p><p class="desc">
|
||||
It has encodings from 2 classes:
|
||||
<a href="#iclass_per_word">32-bit</a>
|
||||
and
|
||||
<a href="#iclass_per_doubleword">64-bit</a></p><h3 class="classheading"><a id="iclass_per_word"/>32-bit<span style="font-size:smaller;"><br/>(FEAT_SME)
|
||||
</span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="l">0</td><td class="r">1</td><td class="l">0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr" colspan="3">Pm</td><td class="lr" colspan="3">Pn</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="2">ZAda</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="7"/><td/><td colspan="2"/><td colspan="3"/><td class="droppedname">V</td><td colspan="3"/><td colspan="3"/><td colspan="5"/><td/><td/><td/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addva_za_pp_z_32"/><p class="asm-code">ADDVA <a href="#sa_zada" title="ZA tile ZA0-ZA3 (field "ZAda")"><ZAda></a>.S, <a href="#sa_pn" title="First governing scalable predicate register P0-P7 (field "Pn")"><Pn></a>/M, <a href="#sa_pm" title="Second governing scalable predicate register P0-P7 (field "Pm")"><Pm></a>/M, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.S</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 32;
|
||||
integer a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAda);</p><h3 class="classheading"><a id="iclass_per_doubleword"/>64-bit<span style="font-size:smaller;"><br/>(FEAT_SME_I16I64)
|
||||
</span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="l">0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr" colspan="3">Pm</td><td class="lr" colspan="3">Pn</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">ZAda</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="7"/><td/><td colspan="5"/><td class="droppedname">V</td><td colspan="3"/><td colspan="3"/><td colspan="5"/><td/><td/><td colspan="3"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addva_za_pp_z_64"/><p class="asm-code">ADDVA <a href="#sa_zada_1" title="ZA tile ZA0-ZA7 (field "ZAda")"><ZAda></a>.D, <a href="#sa_pn" title="First governing scalable predicate register P0-P7 (field "Pn")"><Pn></a>/M, <a href="#sa_pm" title="Second governing scalable predicate register P0-P7 (field "Pm")"><Pm></a>/M, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSMEI16I64.0" title="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
|
||||
constant integer esize = 64;
|
||||
integer a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAda);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><ZAda></td><td><a id="sa_zada"/><p class="aml">For the 32-bit variant: is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field.</p></td></tr><tr><td/><td><a id="sa_zada_1"/><p class="aml">For the 64-bit variant: is the name of the ZA tile ZA0-ZA7, encoded in the "ZAda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pn></td><td><a id="sa_pn"/><p class="aml">Is the name of the first governing scalable predicate register P0-P7, encoded in the "Pn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pm></td><td><a id="sa_pm"/><p class="aml">Is the name of the second governing scalable predicate register P0-P7, encoded in the "Pm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckStreamingSVEAndZAEnabled.0" title="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer dim = VL DIV esize;
|
||||
bits(PL) mask1 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[a, PL];
|
||||
bits(PL) mask2 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[b, PL];
|
||||
bits(VL) operand_src = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(dim*dim*esize) operand_acc = <a href="shared_pseudocode.html#impl-aarch64.ZAtile.read.3" title="accessor: bits(width) ZAtile[integer tile, integer esize, integer width]">ZAtile</a>[da, esize, dim*dim*esize];
|
||||
bits(dim*dim*esize) result;
|
||||
|
||||
for row = 0 to dim-1
|
||||
bits(esize) element = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand_src, row, esize];
|
||||
for col = 0 to dim-1
|
||||
bits(esize) res = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand_acc, row*dim+col, esize];
|
||||
if (<a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask1, row, esize) &&
|
||||
<a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask2, col, esize)) then
|
||||
res = res + element;
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, row*dim+col, esize] = res;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.ZAtile.write.3" title="accessor: ZAtile[integer tile, integer esize, integer width] = bits(width) value">ZAtile</a>[da, esize, dim*dim*esize] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate registers contain the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate registers contain the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,23 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADDVL</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADDVL</h2><p>Add multiple of vector register size to scalar register</p><p class="aml">Add the current vector register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer, and place the result in the 64-bit destination general-purpose register or current stack pointer.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="5">Rn</td><td class="l">0</td><td>1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr" colspan="6">imm6</td><td class="lr" colspan="5">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addvl_r_ri_"/><p class="asm-code">ADDVL <a href="#sa_xd_sp" title="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a>, <a href="#sa_xn_sp" title="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a>, #<a href="#sa_imm" title="Signed immediate operand [-32-31] (field "imm6")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(imm6);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xd|SP></td><td><a id="sa_xd_sp"/><p class="aml">Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn|SP></td><td><a id="sa_xn_sp"/><p class="aml">Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><imm></td><td><a id="sa_imm"/><p class="aml">Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
bits(64) operand1 = if n == 31 then <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[] else <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
bits(64) result = operand1 + (imm * (VL DIV 8));
|
||||
|
||||
if d == 31 then
|
||||
<a href="shared_pseudocode.html#impl-aarch64.SP.write.0" title="accessor: SP[] = bits(64) value">SP</a>[] = result;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,59 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ADR</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADR</h2><p>Compute vector address</p><p class="aml">Optionally sign or zero-extend the least significant 32-bits of each element from a vector of offsets or indices in the second source vector, scale each index by 2, 4 or 8, add to a vector of base addresses from the first source vector, and place the resulting addresses in the destination vector. This instruction is unpredicated.</p><p class="aml">This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and <ins>enabled.</ins><del>enabled at the current Exception level.</del></p><p class="desc">
|
||||
It has encodings from 3 classes:
|
||||
<a href="#iclass_off_pkd">Packed offsets</a>
|
||||
,
|
||||
<a href="#iclass_off_s_s32">Unpacked 32-bit signed offsets</a>
|
||||
and
|
||||
<a href="#iclass_off_s_u32">Unpacked 32-bit unsigned offsets</a></p><h3 class="classheading"><a id="iclass_off_pkd"/>Packed offsets</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">sz</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr" colspan="2">msz</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="adr_z_az_sd_same_scaled"/><p class="asm-code">ADR <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "sz") [D,S]"><T></a>, [<a href="#sa_zn" title="Base scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "sz") [D,S]"><T></a>, <a href="#sa_zm" title="Offset scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "sz") [D,S]"><T></a>{, <a href="#sa_mod" title="Index extend and shift specifier (field "msz")"><mod></a> <a href="#sa_amount" title="Index shift amount (field "msz")"><amount></a>}]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
|
||||
constant integer esize = 32 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
||||
constant integer osize = esize;
|
||||
boolean unsigned = TRUE;
|
||||
integer mbytes = 1 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(msz);</p><h3 class="classheading"><a id="iclass_off_s_s32"/>Unpacked 32-bit signed offsets</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr" colspan="2">msz</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="adr_z_az_d_s32_scaled"/><p class="asm-code">ADR <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.D, [<a href="#sa_zn" title="Base scalable vector register (field "Zn")"><Zn></a>.D, <a href="#sa_zm" title="Offset scalable vector register (field "Zm")"><Zm></a>.D, SXTW{ <a href="#sa_amount" title="Index shift amount (field "msz")"><amount></a>}]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
|
||||
constant integer esize = 64;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
||||
constant integer osize = 32;
|
||||
boolean unsigned = FALSE;
|
||||
integer mbytes = 1 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(msz);</p><h3 class="classheading"><a id="iclass_off_s_u32"/>Unpacked 32-bit unsigned offsets</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr" colspan="2">msz</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="adr_z_az_d_u32_scaled"/><p class="asm-code">ADR <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.D, [<a href="#sa_zn" title="Base scalable vector register (field "Zn")"><Zn></a>.D, <a href="#sa_zm" title="Offset scalable vector register (field "Zm")"><Zm></a>.D, UXTW{ <a href="#sa_amount" title="Index shift amount (field "msz")"><amount></a>}]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
|
||||
constant integer esize = 64;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
||||
constant integer osize = 32;
|
||||
boolean unsigned = TRUE;
|
||||
integer mbytes = 1 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(msz);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>sz</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">sz</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">0</td><td class="symbol">S</td></tr><tr><td class="bitfield">1</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the base scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the offset scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><mod></td><td><a id="sa_mod"/><p>Is the index extend and shift specifier,
|
||||
encoded in
|
||||
<q>msz</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">msz</th><th class="symbol"><mod></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">[absent]</td></tr><tr><td class="bitfield">x1</td><td class="symbol">LSL</td></tr><tr><td class="bitfield">10</td><td class="symbol">LSL</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><amount></td><td><a id="sa_amount"/><p>Is the index shift amount,
|
||||
encoded in
|
||||
<q>msz</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">msz</th><th class="symbol"><amount></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">[absent]</td></tr><tr><td class="bitfield">01</td><td class="symbol">#1</td></tr><tr><td class="bitfield">10</td><td class="symbol">#2</td></tr><tr><td class="bitfield">11</td><td class="symbol">#3</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckNonStreamingSVEEnabled.0" title="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) base = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) offs = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) addr = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[base, e, esize];
|
||||
integer offset = <a href="shared_pseudocode.html#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[offs, e, esize]<osize-1:0>, unsigned);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = addr + (offset * mbytes);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,25 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AESD</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AESD</h2><p>AES single round decryption</p><p class="aml">The <span class="asm-code">AESD</span> instruction reads a 16-byte state array from each 128-bit segment of the first source vector, together with a round key from the corresponding 128-bit segment of the second source vector. Each state array undergoes a single round of the <span class="arm-defined-word">AddRoundKey()</span>, <span class="arm-defined-word">InvSubBytes()</span> and <span class="arm-defined-word">InvShiftRows()</span> transformations in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.</p><p class="aml">ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.</p><p class="aml">This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and <ins>enabled.</ins><del>enabled at the current Exception level.</del></p><h3 class="classheading"><a id="iclass_sve2"/>SVE2<span style="font-size:smaller;"><br/>(FEAT_SVE_AES)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="5">Zdn</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td colspan="5"/><td/><td colspan="5"/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="aesd_z_zz_"/><p class="asm-code">AESD <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.B, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.B, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.B</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() || !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2AES.0" title="function: boolean HaveSVE2AES()">HaveSVE2AES</a>() then UNDEFINED;
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckNonStreamingSVEEnabled.0" title="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer segments = VL DIV 128;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
result = operand1 EOR operand2;
|
||||
for s = 0 to segments-1
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, s, 128] = <a href="shared_pseudocode.html#impl-shared.AESInvSubBytes.1" title="function: bits(128) AESInvSubBytes(bits(128) op)">AESInvSubBytes</a>(<a href="shared_pseudocode.html#impl-shared.AESInvShiftRows.1" title="function: bits(128) AESInvShiftRows(bits(128) op)">AESInvShiftRows</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, s, 128]));
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,25 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AESE</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AESE</h2><p>AES single round encryption</p><p class="aml">The <span class="asm-code">AESE</span> instruction reads a 16-byte state array from each 128-bit segment of the first source vector together with a round key from the corresponding 128-bit segment of the second source vector. Each state array undergoes a single round of the <span class="arm-defined-word">AddRoundKey()</span>, <span class="arm-defined-word">SubBytes()</span> and <span class="arm-defined-word">ShiftRows()</span> transformations in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.</p><p class="aml">ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.</p><p class="aml">This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and <ins>enabled.</ins><del>enabled at the current Exception level.</del></p><h3 class="classheading"><a id="iclass_sve2"/>SVE2<span style="font-size:smaller;"><br/>(FEAT_SVE_AES)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="5">Zdn</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td colspan="5"/><td/><td colspan="5"/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="aese_z_zz_"/><p class="asm-code">AESE <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.B, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.B, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.B</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() || !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2AES.0" title="function: boolean HaveSVE2AES()">HaveSVE2AES</a>() then UNDEFINED;
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckNonStreamingSVEEnabled.0" title="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer segments = VL DIV 128;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
result = operand1 EOR operand2;
|
||||
for s = 0 to segments-1
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, s, 128] = <a href="shared_pseudocode.html#impl-shared.AESSubBytes.1" title="function: bits(128) AESSubBytes(bits(128) op)">AESSubBytes</a>(<a href="shared_pseudocode.html#impl-shared.AESShiftRows.1" title="function: bits(128) AESShiftRows(bits(128) op)">AESShiftRows</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, s, 128]));
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,21 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AESIMC -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AESIMC</h2><p class="aml">AES inverse mix columns.</p><h3 class="classheading"><a id="iclass_advsimd"/><ins>Advanced SIMD</ins><span style="font-size:smaller;"><br/><ins>(FEAT_AES)
|
||||
</ins></span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td class="r">0</td><td class="l">0</td><td class="r">0</td><td class="l">1</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="l">0</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="l">1</td><td class="r">0</td><td class="lr" colspan="5">Rn</td><td class="lr" colspan="5">Rd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td colspan="5"/><td colspan="4"/><td class="droppedname">D</td><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="AESIMC_B_cryptoaes"/><p class="asm-code">AESIMC <a href="#sa_vd" title="SIMD&FP destination register (field "Rd")"><Vd></a>.16B, <a href="#sa_vn" title="SIMD&FP source register (field "Rn")"><Vn></a>.16B</p></div><p class="pseudocode">integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveAESExt.0" title="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;
|
||||
boolean decrypt = (D == '1');</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Vd></td><td><a id="sa_vd"/><p class="aml">Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Vn></td><td><a id="sa_vn"/><p class="aml">Is the name of the SIMD&FP source register, encoded in the "Rn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
|
||||
|
||||
bits(128) operand = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
|
||||
bits(128) result;
|
||||
if decrypt then
|
||||
result = <a href="shared_pseudocode.html#impl-shared.AESInvMixColumns.1" title="function: bits(128) AESInvMixColumns(bits (128) op)">AESInvMixColumns</a>(operand);
|
||||
else
|
||||
result = <a href="shared_pseudocode.html#impl-shared.AESMixColumns.1" title="function: bits(128) AESMixColumns(bits (128) op)">AESMixColumns</a>(operand);
|
||||
<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</p></div><h3>Operational information</h3><p class="aml">If PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,22 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AESIMC</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AESIMC</h2><p>AES inverse mix columns</p><p class="aml">The <span class="asm-code">AESIMC</span> instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the <span class="arm-defined-word">InvMixColumns()</span> transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.</p><p class="aml">ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.</p><p class="aml">This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and <ins>enabled.</ins><del>enabled at the current Exception level.</del></p><h3 class="classheading"><a id="iclass_sve2"/>SVE2<span style="font-size:smaller;"><br/>(FEAT_SVE_AES)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr" colspan="5">Zdn</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td colspan="11"/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="aesimc_z_z_"/><p class="asm-code">AESIMC <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.B, <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.B</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() || !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2AES.0" title="function: boolean HaveSVE2AES()">HaveSVE2AES</a>() then UNDEFINED;
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckNonStreamingSVEEnabled.0" title="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer segments = VL DIV 128;
|
||||
bits(VL) operand = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for s = 0 to segments-1
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, s, 128] = <a href="shared_pseudocode.html#impl-shared.AESInvMixColumns.1" title="function: bits(128) AESInvMixColumns(bits (128) op)">AESInvMixColumns</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, s, 128]);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,21 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AESMC -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AESMC</h2><p class="aml">AES mix columns.</p><h3 class="classheading"><a id="iclass_advsimd"/><ins>Advanced SIMD</ins><span style="font-size:smaller;"><br/><ins>(FEAT_AES)
|
||||
</ins></span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td class="r">0</td><td class="l">0</td><td class="r">0</td><td class="l">1</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="l">0</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="l">1</td><td class="r">0</td><td class="lr" colspan="5">Rn</td><td class="lr" colspan="5">Rd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td colspan="5"/><td colspan="4"/><td class="droppedname">D</td><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="AESMC_B_cryptoaes"/><p class="asm-code">AESMC <a href="#sa_vd" title="SIMD&FP destination register (field "Rd")"><Vd></a>.16B, <a href="#sa_vn" title="SIMD&FP source register (field "Rn")"><Vn></a>.16B</p></div><p class="pseudocode">integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveAESExt.0" title="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;
|
||||
boolean decrypt = (D == '1');</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Vd></td><td><a id="sa_vd"/><p class="aml">Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Vn></td><td><a id="sa_vn"/><p class="aml">Is the name of the SIMD&FP source register, encoded in the "Rn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#AArch64.CheckFPAdvSIMDEnabled.0" title="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
|
||||
|
||||
bits(128) operand = <a href="shared_pseudocode.html#impl-aarch64.V.read.2" title="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
|
||||
bits(128) result;
|
||||
if decrypt then
|
||||
result = <a href="shared_pseudocode.html#impl-shared.AESInvMixColumns.1" title="function: bits(128) AESInvMixColumns(bits (128) op)">AESInvMixColumns</a>(operand);
|
||||
else
|
||||
result = <a href="shared_pseudocode.html#impl-shared.AESMixColumns.1" title="function: bits(128) AESMixColumns(bits (128) op)">AESMixColumns</a>(operand);
|
||||
<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</p></div><h3>Operational information</h3><p class="aml">If PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,22 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AESMC</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AESMC</h2><p>AES mix columns</p><p class="aml">The <span class="asm-code">AESMC</span> instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the <span class="arm-defined-word">MixColumns()</span> transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.</p><p class="aml">ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.</p><p class="aml">This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and <ins>enabled.</ins><del>enabled at the current Exception level.</del></p><h3 class="classheading"><a id="iclass_sve2"/>SVE2<span style="font-size:smaller;"><br/>(FEAT_SVE_AES)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>1</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr" colspan="5">Zdn</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td colspan="11"/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="aesmc_z_z_"/><p class="asm-code">AESMC <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.B, <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.B</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() || !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2AES.0" title="function: boolean HaveSVE2AES()">HaveSVE2AES</a>() then UNDEFINED;
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckNonStreamingSVEEnabled.0" title="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer segments = VL DIV 128;
|
||||
bits(VL) operand = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for s = 0 to segments-1
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, s, 128] = <a href="shared_pseudocode.html#impl-shared.AESMixColumns.1" title="function: bits(128) AESMixColumns(bits (128) op)">AESMixColumns</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, s, 128]);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,37 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AND (predicates)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AND (predicates)</h2><p>Bitwise AND predicates</p><p class="aml">Bitwise AND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.</p><p class="desc">This instruction is used by the alias <a href="mov_and_p_p_pp.html" title="Move predicates (zeroing)">MOV (predicate, predicated, zeroing)</a>.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="lr" colspan="4">Pm</td><td class="l">0</td><td class="r">1</td><td class="lr" colspan="4">Pg</td><td class="lr">0</td><td class="lr" colspan="4">Pn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td/><td class="droppedname">S</td><td colspan="2"/><td colspan="4"/><td colspan="2"/><td colspan="4"/><td/><td colspan="4"/><td/><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="and_p_p_pp_z"/><p class="asm-code">AND <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.B, <a href="#sa_pg" title="Governing scalable predicate register (field "Pg")"><Pg></a>/Z, <a href="#sa_pn" title="First source scalable predicate register (field "Pn")"><Pn></a>.B, <a href="#sa_pm" title="Second source scalable predicate register (field "Pm")"><Pm></a>.B</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8;
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
boolean setflags = FALSE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pd></td><td><a id="sa_pd"/><p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pn></td><td><a id="sa_pn"/><p class="aml">Is the name of the first source scalable predicate register, encoded in the "Pn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pm></td><td><a id="sa_pm"/><p class="aml">Is the name of the second source scalable predicate register, encoded in the "Pm" field.</p></td></tr></table></div><div class="syntax-notes"/><h3 class="aliastable" id="">Alias Conditions</h3><table class="aliastable"><thead><tr><th>Alias</th><th>Is preferred when</th></tr></thead><tbody><tr><td><a href="mov_and_p_p_pp.html" title="Move predicates (zeroing)">MOV (predicate, predicated, zeroing)</a></td><td class="notfirst"><span class="pseudocode">S == '0' && Pn == Pm</span></td></tr></tbody></table><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(PL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[n, PL];
|
||||
bits(PL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[m, PL];
|
||||
bits(PL) result;
|
||||
constant integer psize = esize DIV 8;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bit element1 = <a href="shared_pseudocode.html#impl-aarch64.PredicateElement.3" title="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand1, e, esize);
|
||||
bit element2 = <a href="shared_pseudocode.html#impl-aarch64.PredicateElement.3" title="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand2, e, esize);
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(element1 AND element2, psize);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', psize);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = <a href="shared_pseudocode.html#impl-aarch64.PredTest.3" title="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</a>(mask, result, esize);
|
||||
<a href="shared_pseudocode.html#impl-aarch64.P.write.2" title="accessor: P[integer n, integer width] = bits(width) value">P</a>[d, PL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,37 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AND (vectors, predicated)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AND (vectors, predicated)</h2><p>Bitwise AND vectors (predicated)</p><p class="aml">Bitwise AND active elements of the second source vector with corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td class="r">1</td><td class="lr">0</td><td class="l">0</td><td>0</td><td class="r">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="5">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="and_z_p_zz_"/><p class="asm-code">AND <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 AND element2;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,30 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AND (immediate)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AND (immediate)</h2><p>Bitwise AND with immediate (unpredicated)</p><p class="aml">Bitwise AND an immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. This instruction is unpredicated.</p><p class="desc">This instruction is used by the pseudo-instruction <a href="bic_and_z_zi.html" title="Bitwise clear bits using immediate (unpredicated)">BIC (immediate)</a>.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="lr">0</td><td class="l">0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr" colspan="13">imm13</td><td class="lr" colspan="5">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="and_z_zi_"/><p class="asm-code">AND <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a>, <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a>, #<a href="#sa_const" title="64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits (field "imm13")"><const></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
bits(64) imm;
|
||||
(imm, -) = <a href="shared_pseudocode.html#impl-aarch64.DecodeBitMasks.5" title="function: (bits(M), bits(M)) DecodeBitMasks(bit immN, bits(6) imms, bits(6) immr, boolean immediate, integer M)">DecodeBitMasks</a>(imm13<12>, imm13<5:0>, imm13<11:6>, TRUE, 64);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>imm13<12>:imm13<5:0></q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">imm13<12></th><th class="bitfield">imm13<5:0></th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">0</td><td class="bitfield">0xxxxx</td><td class="symbol">S</td></tr><tr><td class="bitfield">0</td><td class="bitfield">10xxxx</td><td class="symbol">H</td></tr><tr><td class="bitfield">0</td><td class="bitfield">110xxx</td><td class="symbol">B</td></tr><tr><td class="bitfield">0</td><td class="bitfield">1110xx</td><td class="symbol">B</td></tr><tr><td class="bitfield">0</td><td class="bitfield">11110x</td><td class="symbol">B</td></tr><tr><td class="bitfield">0</td><td class="bitfield">111110</td><td class="symbol">RESERVED</td></tr><tr><td class="bitfield">0</td><td class="bitfield">111111</td><td class="symbol">RESERVED</td></tr><tr><td class="bitfield">1</td><td class="bitfield">xxxxxx</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><const></td><td><a id="sa_const"/><p class="aml">Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV 64;
|
||||
bits(VL) operand = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(64) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 64];
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 64] = element1 AND imm;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,19 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AND (vectors, unpredicated)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AND (vectors, unpredicated)</h2><p>Bitwise AND vectors (unpredicated)</p><p class="aml">Bitwise AND all elements of the second source vector with corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. This instruction is unpredicated.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">0</td><td>0</td><td>1</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="and_z_zz_"/><p class="asm-code">AND <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.D, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.D, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = operand1 AND operand2;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,42 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ANDQV</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ANDQV</h2><p>Bitwise AND reduction of quadword vector segments</p><p class="aml">Bitwise AND of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as all ones.</p><h3 class="classheading"><a id="iclass_sve2"/>SVE2<span style="font-size:smaller;"><br/>(FEAT_SVE2p1)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="lr">0</td><td class="l">0</td><td>0</td><td class="r">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Vd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="andqv_z_p_z_"/><p class="asm-code">ANDQV <a href="#sa_vd" title="Destination SIMD&FP register (field "Vd")"><Vd></a>.<a href="#sa_t" title="Arrangement specifier (field "size") [2D,4S,8H,16B]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_tb" title="Size specifier (field "size") [B,D,H,S]"><Tb></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2p1.0" title="function: boolean HaveSVE2p1()">HaveSVE2p1</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2p1.0" title="function: boolean HaveSME2p1()">HaveSME2p1</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Vd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Vd></td><td><a id="sa_vd"/><p class="aml">Is the name of the destination SIMD&FP register, encoded in the "Vd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is an arrangement specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">16B</td></tr><tr><td class="bitfield">01</td><td class="symbol">8H</td></tr><tr><td class="bitfield">10</td><td class="symbol">4S</td></tr><tr><td class="bitfield">11</td><td class="symbol">2D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Tb></td><td><a id="sa_tb"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><Tb></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer segments = VL DIV 128;
|
||||
constant integer elempersegment = 128 DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(128) result = <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(128);
|
||||
bits(128) stmp = <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(128);
|
||||
|
||||
bits(esize) dtmp;
|
||||
|
||||
for e = 0 to elempersegment-1
|
||||
dtmp = <a href="shared_pseudocode.html#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize);
|
||||
for s = 0 to segments-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, s * elempersegment + e, esize) then
|
||||
stmp = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, s, 128];
|
||||
dtmp = dtmp AND <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[stmp, e, esize];
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = dtmp<esize-1:0>;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,37 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ANDS</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ANDS</h2><p>Bitwise AND predicates, setting the condition flags</p><p class="aml">Bitwise AND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the <span class="arm-defined-word">First</span> (N), <span class="arm-defined-word">None</span> (Z), <span class="arm-defined-word">!Last</span> (C) condition flags based on the predicate result, and the V flag to zero.</p><p class="desc">This instruction is used by the alias <a href="movs_ands_p_p_pp.html" title="Move predicates (zeroing)">MOVS (predicated)</a>.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">1</td><td class="l">0</td><td class="r">0</td><td class="lr" colspan="4">Pm</td><td class="l">0</td><td class="r">1</td><td class="lr" colspan="4">Pg</td><td class="lr">0</td><td class="lr" colspan="4">Pn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td/><td class="droppedname">S</td><td colspan="2"/><td colspan="4"/><td colspan="2"/><td colspan="4"/><td/><td colspan="4"/><td/><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="ands_p_p_pp_z"/><p class="asm-code">ANDS <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.B, <a href="#sa_pg" title="Governing scalable predicate register (field "Pg")"><Pg></a>/Z, <a href="#sa_pn" title="First source scalable predicate register (field "Pn")"><Pn></a>.B, <a href="#sa_pm" title="Second source scalable predicate register (field "Pm")"><Pm></a>.B</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8;
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
boolean setflags = TRUE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pd></td><td><a id="sa_pd"/><p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pn></td><td><a id="sa_pn"/><p class="aml">Is the name of the first source scalable predicate register, encoded in the "Pn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pm></td><td><a id="sa_pm"/><p class="aml">Is the name of the second source scalable predicate register, encoded in the "Pm" field.</p></td></tr></table></div><div class="syntax-notes"/><h3 class="aliastable" id="">Alias Conditions</h3><table class="aliastable"><thead><tr><th>Alias</th><th>Is preferred when</th></tr></thead><tbody><tr><td><a href="movs_ands_p_p_pp.html" title="Move predicates (zeroing)">MOVS (predicated)</a></td><td class="notfirst"><span class="pseudocode">S == '1' && Pn == Pm</span></td></tr></tbody></table><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(PL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[n, PL];
|
||||
bits(PL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[m, PL];
|
||||
bits(PL) result;
|
||||
constant integer psize = esize DIV 8;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bit element1 = <a href="shared_pseudocode.html#impl-aarch64.PredicateElement.3" title="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand1, e, esize);
|
||||
bit element2 = <a href="shared_pseudocode.html#impl-aarch64.PredicateElement.3" title="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand2, e, esize);
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(element1 AND element2, psize);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', psize);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = <a href="shared_pseudocode.html#impl-aarch64.PredTest.3" title="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</a>(mask, result, esize);
|
||||
<a href="shared_pseudocode.html#impl-aarch64.P.write.2" title="accessor: P[integer n, integer width] = bits(width) value">P</a>[d, PL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the NZCV condition flags written by this instruction might be significantly delayed.</p><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,33 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ANDV</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ANDV</h2><p>Bitwise AND reduction to scalar</p><p class="aml">Bitwise AND horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as all ones.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td>1</td><td class="r">0</td><td class="lr">1</td><td class="lr">0</td><td class="l">0</td><td>0</td><td class="r">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Vd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="andv_r_p_z_"/><p class="asm-code">ANDV <a href="#sa_v" title="Width specifier (field "size") [B,D,H,S]"><V></a><a href="#sa_d" title="Destination SIMD&FP register number [0-31] (field "Vd")"><d></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Vd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><V></td><td><a id="sa_v"/><p>Is a width specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><V></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><d></td><td><a id="sa_d"/><p class="aml">Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(esize) result = <a href="shared_pseudocode.html#impl-shared.Ones.1" title="function: bits(N) Ones(integer N)">Ones</a>(esize);
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
result = result AND <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.V.write.2" title="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, esize] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,42 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ASR (immediate, predicated)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ASR (immediate, predicated)</h2><p>Arithmetic shift right by immediate (predicated)</p><p class="aml">Shift right by immediate, preserving the sign bit, each active element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">tszh</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td>0</td><td class="r">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="2">tszl</td><td class="lr" colspan="3">imm3</td><td class="lr" colspan="5">Zdn</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td colspan="2"/><td/><td/><td class="droppedname">L</td><td class="droppedname">U</td><td colspan="3"/><td colspan="3"/><td colspan="2"/><td colspan="3"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="asr_z_p_zi_"/><p class="asm-code">ASR <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a>, #<a href="#sa_const" title="Immediate shift amount [1-number of bits per element] (field "tszh:tszl:imm3")"><const></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
bits(4) tsize = tszh:tszl;
|
||||
integer esize;
|
||||
case tsize of
|
||||
when '0000' UNDEFINED;
|
||||
when '0001' esize = 8;
|
||||
when '001x' esize = 16;
|
||||
when '01xx' esize = 32;
|
||||
when '1xxx' esize = 64;
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer shift = (2 * esize) - <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(tsize:imm3);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>tszh:tszl</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">tszh</th><th class="bitfield">tszl</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="bitfield">00</td><td class="symbol">RESERVED</td></tr><tr><td class="bitfield">00</td><td class="bitfield">01</td><td class="symbol">B</td></tr><tr><td class="bitfield">00</td><td class="bitfield">1x</td><td class="symbol">H</td></tr><tr><td class="bitfield">01</td><td class="bitfield">xx</td><td class="symbol">S</td></tr><tr><td class="bitfield">1x</td><td class="bitfield">xx</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><const></td><td><a id="sa_const"/><p class="aml">Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "<ins>tszh:tszl</ins><del>tsz</del>:imm3".</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
constant integer PL = VL DIV 8;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.ASR.2" title="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element1, shift);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,39 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ASR (wide elements, predicated)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ASR (wide elements, predicated)</h2><p>Arithmetic shift right by 64-bit wide elements (predicated)</p><p class="aml">Shift right, preserving the sign bit, active elements of the first source vector by corresponding overlapping 64-bit elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount is a vector of unsigned 64-bit doubleword elements in which all bits are significant, and not used modulo the destination element size. Inactive elements in the destination vector register remain unmodified.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td>0</td><td class="r">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="5">Zdn</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td colspan="3"/><td class="droppedname">R</td><td class="droppedname">L</td><td class="droppedname">U</td><td colspan="3"/><td colspan="3"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="asr_z_p_zw_"/><p class="asm-code">ASR <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">RESERVED</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(64) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, (e * esize) DIV 64, 64];
|
||||
integer shift = <a href="shared_pseudocode.html#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(<a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2), esize);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.ASR.2" title="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element1, shift);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and destination element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,38 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ASR (vectors)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ASR (vectors)</h2><p>Arithmetic shift right by vector (predicated)</p><p class="aml">Shift right, preserving the sign bit, active elements of the first source vector by corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount operand is a vector of unsigned elements in which all bits are significant, and not used modulo the element size. Inactive elements in the destination vector register remain unmodified.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td>0</td><td class="r">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="5">Zdn</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td colspan="3"/><td class="droppedname">R</td><td class="droppedname">L</td><td class="droppedname">U</td><td colspan="3"/><td colspan="3"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="asr_z_p_zz_"/><p class="asm-code">ASR <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
integer shift = <a href="shared_pseudocode.html#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(<a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2), esize);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.ASR.2" title="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element1, shift);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,35 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ASR (immediate, unpredicated)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ASR (immediate, unpredicated)</h2><p>Arithmetic shift right by immediate (unpredicated)</p><p class="aml">Shift right by immediate, preserving the sign bit, each element of the source vector, and place the results in the corresponding elements of the destination vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">tszh</td><td class="lr">1</td><td class="lr" colspan="2">tszl</td><td class="lr" colspan="3">imm3</td><td class="l">1</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="2"/><td colspan="3"/><td colspan="4"/><td/><td class="droppedname">U</td><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="asr_z_zi_"/><p class="asm-code">ASR <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a>, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a>, #<a href="#sa_const" title="Immediate shift amount [1-number of bits per element] (field "tszh:tszl:imm3")"><const></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
bits(4) tsize = tszh:tszl;
|
||||
integer esize;
|
||||
case tsize of
|
||||
when '0000' UNDEFINED;
|
||||
when '0001' esize = 8;
|
||||
when '001x' esize = 16;
|
||||
when '01xx' esize = 32;
|
||||
when '1xxx' esize = 64;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
||||
integer shift = (2 * esize) - <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(tsize:imm3);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>tszh:tszl</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">tszh</th><th class="bitfield">tszl</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="bitfield">00</td><td class="symbol">RESERVED</td></tr><tr><td class="bitfield">00</td><td class="bitfield">01</td><td class="symbol">B</td></tr><tr><td class="bitfield">00</td><td class="bitfield">1x</td><td class="symbol">H</td></tr><tr><td class="bitfield">01</td><td class="bitfield">xx</td><td class="symbol">S</td></tr><tr><td class="bitfield">1x</td><td class="bitfield">xx</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><const></td><td><a id="sa_const"/><p class="aml">Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "<ins>tszh:tszl</ins><del>tsz</del>:imm3".</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.ASR.2" title="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element1, shift);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,33 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ASR (wide elements, unpredicated)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ASR (wide elements, unpredicated)</h2><p>Arithmetic shift right by 64-bit wide elements (unpredicated)</p><p class="aml">Shift right, preserving the sign bit, all elements of the first source vector by corresponding overlapping 64-bit elements of the second source vector and place the first in the corresponding elements of the destination vector. The shift amount is a vector of unsigned 64-bit doubleword elements in which all bits are significant, and not used modulo the destination element size. This instruction is unpredicated.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td colspan="4"/><td/><td class="droppedname">U</td><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="asr_z_zw_"/><p class="asm-code">ASR <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">RESERVED</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(64) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, (e * esize) DIV 64, 64];
|
||||
integer shift = <a href="shared_pseudocode.html#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(<a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element2), esize);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.ASR.2" title="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element1, shift);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,44 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ASRD</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ASRD</h2><p>Arithmetic shift right for divide by immediate (predicated)</p><p class="aml">Shift right by immediate, preserving the sign bit, each active element of the source vector, and destructively place the results in the corresponding elements of the source vector. The result rounds toward zero as in a signed division. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">tszh</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td>0</td><td class="r">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="2">tszl</td><td class="lr" colspan="3">imm3</td><td class="lr" colspan="5">Zdn</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td colspan="2"/><td/><td/><td class="droppedname">L</td><td class="droppedname">U</td><td colspan="3"/><td colspan="3"/><td colspan="2"/><td colspan="3"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="asrd_z_p_zi_"/><p class="asm-code">ASRD <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a>, #<a href="#sa_const" title="Immediate shift amount [1-number of bits per element] (field "tszh:tszl:imm3")"><const></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
bits(4) tsize = tszh:tszl;
|
||||
integer esize;
|
||||
case tsize of
|
||||
when '0000' UNDEFINED;
|
||||
when '0001' esize = 8;
|
||||
when '001x' esize = 16;
|
||||
when '01xx' esize = 32;
|
||||
when '1xxx' esize = 64;
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer shift = (2 * esize) - <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(tsize:imm3);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>tszh:tszl</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">tszh</th><th class="bitfield">tszl</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="bitfield">00</td><td class="symbol">RESERVED</td></tr><tr><td class="bitfield">00</td><td class="bitfield">01</td><td class="symbol">B</td></tr><tr><td class="bitfield">00</td><td class="bitfield">1x</td><td class="symbol">H</td></tr><tr><td class="bitfield">01</td><td class="bitfield">xx</td><td class="symbol">S</td></tr><tr><td class="bitfield">1x</td><td class="bitfield">xx</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><const></td><td><a id="sa_const"/><p class="aml">Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "<ins>tszh:tszl</ins><del>tsz</del>:imm3".</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
integer element1 = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
|
||||
if element1 < 0 then
|
||||
element1 = element1 + ((1 << shift) - 1);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1 >> shift)<esize-1:0>;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,38 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>ASRR</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ASRR</h2><p>Reversed arithmetic shift right by vector (predicated)</p><p class="aml">Reversed shift right, preserving the sign bit, active elements of the second source vector by corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount operand is a vector of unsigned elements in which all bits are significant, and not used modulo the element size. Inactive elements in the destination vector register remain unmodified.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td class="r">0</td><td class="lr">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td>0</td><td class="r">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="5">Zdn</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td colspan="3"/><td class="droppedname">R</td><td class="droppedname">L</td><td class="droppedname">U</td><td colspan="3"/><td colspan="3"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="asrr_z_p_zz_"/><p class="asm-code">ASRR <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
integer shift = <a href="shared_pseudocode.html#impl-shared.Min.2" title="function: integer Min(integer a, integer b)">Min</a>(<a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(element1), esize);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.ASR.2" title="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element2, shift);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,26 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AUTDA, AUTDZA -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AUTDA, AUTDZA</h2><p class="aml">Authenticate Data address, using key A. This instruction authenticates a data address, using a modifier and key A.</p><p class="aml">The address is in the general-purpose register that is specified by <Xd>.</p><p class="aml">The modifier is:</p><ul><li>In the general-purpose register or stack pointer that is specified by <Xn|SP> for <span class="asm-code">AUTDA</span>.</li><li>The value zero, for <span class="asm-code">AUTDZA</span>.</li></ul><p class="aml">If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. <ins>For</ins><del>If</del> <ins>information</ins><del>the</del> <ins>on</ins><del>authentication</del> <ins>behavior</ins><del>fails,</del> <ins>if</ins><del>the</del> <del>upper bits are corrupted and any subsequent use of </del>the <ins>authentication</ins><del>address</del> <ins>fails,</ins><del>results</del> <ins>see</ins><del>in a Translation fault.</del> <a class="armarm-xref" title="Reference to Armv8 ARM section"><ins>Faulting on pointer authentication</ins></a><ins>.</ins></p><h3 class="classheading"><a id="iclass_general"/>Integer<span style="font-size:smaller;"><br/>(FEAT_PAuth)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">1</td><td class="lr">1</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td class="r">0</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr">Z</td><td class="l">1</td><td>1</td><td class="r">0</td><td class="lr" colspan="5">Rn</td><td class="lr" colspan="5">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding">AUTDA<span class="bitdiff"> (Z == 0)</span></h4><a id="AUTDA_64P_dp_1src"/><p class="asm-code">AUTDA <a href="#sa_xd" title="64-bit general-purpose destination register (field "Rd")"><Xd></a>, <a href="#sa_xn_sp" title="64-bit general-purpose source register or SP (field "Rn")"><Xn|SP></a></p></div><div class="encoding"><h4 class="encoding">AUTDZA<span class="bitdiff"> (Z == 1 && Rn == 11111)</span></h4><a id="AUTDZA_64Z_dp_1src"/><p class="asm-code">AUTDZA <a href="#sa_xd" title="64-bit general-purpose destination register (field "Rd")"><Xd></a></p></div><p class="pseudocode">boolean source_is_sp = FALSE;
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if !<a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
if Z == '0' then // AUTDA
|
||||
if n == 31 then source_is_sp = TRUE;
|
||||
else // AUTDZA
|
||||
if n != 31 then UNDEFINED;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xd></td><td><a id="sa_xd"/><p class="aml">Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn|SP></td><td><a id="sa_xn_sp"/><p class="aml">Is the 64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">auth_then_branch = FALSE;
|
||||
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
if source_is_sp then
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthDA(X[d, 64], SP[], auth_then_branch);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthDA(X[d, 64], X[n, 64], auth_then_branch);</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,26 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AUTDB, AUTDZB -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AUTDB, AUTDZB</h2><p class="aml">Authenticate Data address, using key B. This instruction authenticates a data address, using a modifier and key B.</p><p class="aml">The address is in the general-purpose register that is specified by <Xd>.</p><p class="aml">The modifier is:</p><ul><li>In the general-purpose register or stack pointer that is specified by <Xn|SP> for <span class="asm-code">AUTDB</span>.</li><li>The value zero, for <span class="asm-code">AUTDZB</span>.</li></ul><p class="aml">If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. <ins>For</ins><del>If</del> <ins>information</ins><del>the</del> <ins>on</ins><del>authentication</del> <ins>behavior</ins><del>fails,</del> <ins>if</ins><del>the</del> <del>upper bits are corrupted and any subsequent use of </del>the <ins>authentication</ins><del>address</del> <ins>fails,</ins><del>results</del> <ins>see</ins><del>in a Translation fault.</del> <a class="armarm-xref" title="Reference to Armv8 ARM section"><ins>Faulting on pointer authentication</ins></a><ins>.</ins></p><h3 class="classheading"><a id="iclass_general"/>Integer<span style="font-size:smaller;"><br/>(FEAT_PAuth)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">1</td><td class="lr">1</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td class="r">0</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr">Z</td><td class="l">1</td><td>1</td><td class="r">1</td><td class="lr" colspan="5">Rn</td><td class="lr" colspan="5">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding">AUTDB<span class="bitdiff"> (Z == 0)</span></h4><a id="AUTDB_64P_dp_1src"/><p class="asm-code">AUTDB <a href="#sa_xd" title="64-bit general-purpose destination register (field "Rd")"><Xd></a>, <a href="#sa_xn_sp" title="64-bit general-purpose source register or SP (field "Rn")"><Xn|SP></a></p></div><div class="encoding"><h4 class="encoding">AUTDZB<span class="bitdiff"> (Z == 1 && Rn == 11111)</span></h4><a id="AUTDZB_64Z_dp_1src"/><p class="asm-code">AUTDZB <a href="#sa_xd" title="64-bit general-purpose destination register (field "Rd")"><Xd></a></p></div><p class="pseudocode">boolean source_is_sp = FALSE;
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if !<a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
if Z == '0' then // AUTDB
|
||||
if n == 31 then source_is_sp = TRUE;
|
||||
else // AUTDZB
|
||||
if n != 31 then UNDEFINED;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xd></td><td><a id="sa_xd"/><p class="aml">Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn|SP></td><td><a id="sa_xn_sp"/><p class="aml">Is the 64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">auth_then_branch = FALSE;
|
||||
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
if source_is_sp then
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthDB(X[d, 64], SP[], auth_then_branch);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthDB(X[d, 64], X[n, 64], auth_then_branch);</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,52 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA</h2><p class="aml">Authenticate Instruction address, using key A. This instruction authenticates an instruction address, using a modifier and key A.</p><p class="aml">The address is:</p><ul><li>In the general-purpose register that is specified by <Xd> for <span class="asm-code">AUTIA</span> and <span class="asm-code">AUTIZA</span>.</li><li>In X17, for <span class="asm-code">AUTIA1716</span>.</li><li>In X30, for <span class="asm-code">AUTIASP</span> and <span class="asm-code">AUTIAZ</span>.</li></ul><p class="aml">The modifier is:</p><ul><li>In the general-purpose register or stack pointer that is specified by <Xn|SP> for <span class="asm-code">AUTIA</span>.</li><li>The value zero, for <span class="asm-code">AUTIZA</span> and <span class="asm-code">AUTIAZ</span>.</li><li>In X16, for <span class="asm-code">AUTIA1716</span>.</li><li>In SP, for <span class="asm-code">AUTIASP</span>.</li></ul><p class="aml">If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. <ins>For</ins><del>If</del> <ins>information</ins><del>the</del> <ins>on</ins><del>authentication</del> <ins>behavior</ins><del>fails,</del> <ins>if</ins><del>the</del> <del>upper bits are corrupted and any subsequent use of </del>the <ins>authentication</ins><del>address</del> <ins>fails,</ins><del>results</del> <ins>see</ins><del>in a Translation fault.</del> <a class="armarm-xref" title="Reference to Armv8 ARM section"><ins>Faulting on pointer authentication</ins></a><ins>.</ins></p><p class="desc">
|
||||
It has encodings from 2 classes:
|
||||
<a href="#iclass_general">Integer</a>
|
||||
and
|
||||
<a href="#iclass_system">System</a></p><h3 class="classheading"><a id="iclass_general"/>Integer<span style="font-size:smaller;"><br/>(FEAT_PAuth)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">1</td><td class="lr">1</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td class="r">0</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr">Z</td><td class="l">1</td><td>0</td><td class="r">0</td><td class="lr" colspan="5">Rn</td><td class="lr" colspan="5">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding">AUTIA<span class="bitdiff"> (Z == 0)</span></h4><a id="AUTIA_64P_dp_1src"/><p class="asm-code">AUTIA <a href="#sa_xd" title="64-bit general-purpose destination register (field "Rd")"><Xd></a>, <a href="#sa_xn_sp" title="64-bit general-purpose source register or SP (field "Rn")"><Xn|SP></a></p></div><div class="encoding"><h4 class="encoding">AUTIZA<span class="bitdiff"> (Z == 1 && Rn == 11111)</span></h4><a id="AUTIZA_64Z_dp_1src"/><p class="asm-code">AUTIZA <a href="#sa_xd" title="64-bit general-purpose destination register (field "Rd")"><Xd></a></p></div><p class="pseudocode">boolean source_is_sp = FALSE;
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if !<a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
if Z == '0' then // AUTIA
|
||||
if n == 31 then source_is_sp = TRUE;
|
||||
else // AUTIZA
|
||||
if n != 31 then UNDEFINED;</p><h3 class="classheading"><a id="iclass_system"/>System<span style="font-size:smaller;"><br/>(FEAT_PAuth)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>1</td><td class="r">0</td><td class="l">0</td><td>0</td><td>x</td><td class="r">1</td><td class="l">1</td><td>0</td><td class="r">x</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td></tr><tr class="secondrow"><td colspan="10"/><td/><td colspan="2"/><td colspan="3"/><td colspan="4"/><td class="droppedname" colspan="4">CRm</td><td class="droppedname" colspan="3">op2</td><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">AUTIA1716<span class="bitdiff"> (CRm == 0001 && op2 == 100)</span></h4><a id="AUTIA1716_HI_hints"/><p class="asm-code">AUTIA1716</p></div><div class="encoding"><h4 class="encoding">AUTIASP<span class="bitdiff"> (CRm == 0011 && op2 == 101)</span></h4><a id="AUTIASP_HI_hints"/><p class="asm-code">AUTIASP</p></div><div class="encoding"><h4 class="encoding">AUTIAZ<span class="bitdiff"> (CRm == 0011 && op2 == 100)</span></h4><a id="AUTIAZ_HI_hints"/><p class="asm-code">AUTIAZ</p></div><p class="pseudocode">integer d;
|
||||
integer n;
|
||||
boolean source_is_sp = FALSE;
|
||||
|
||||
case CRm:op2 of
|
||||
when '0011 100' // AUTIAZ
|
||||
d = 30;
|
||||
n = 31;
|
||||
when '0011 101' // AUTIASP
|
||||
d = 30;
|
||||
source_is_sp = TRUE;
|
||||
when '0001 100' // AUTIA1716
|
||||
d = 17;
|
||||
n = 16;
|
||||
when '0001 000' SEE "PACIA";
|
||||
when '0001 010' SEE "PACIB";
|
||||
when '0001 110' SEE "AUTIB";
|
||||
when '0011 00x' SEE "PACIA";
|
||||
when '0011 01x' SEE "PACIB";
|
||||
when '0011 11x' SEE "AUTIB";
|
||||
when '0000 111' SEE "XPACLRI";
|
||||
otherwise SEE "HINT";</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xd></td><td><a id="sa_xd"/><p class="aml">Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn|SP></td><td><a id="sa_xn_sp"/><p class="aml">Is the 64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">auth_then_branch = FALSE;
|
||||
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
if source_is_sp then
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthIA(X[d, 64], SP[], auth_then_branch);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthIA(X[d, 64], X[n, 64], auth_then_branch);</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,52 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB</h2><p class="aml">Authenticate Instruction address, using key B. This instruction authenticates an instruction address, using a modifier and key B.</p><p class="aml">The address is:</p><ul><li>In the general-purpose register that is specified by <Xd> for <span class="asm-code">AUTIB</span> and <span class="asm-code">AUTIZB</span>.</li><li>In X17, for <span class="asm-code">AUTIB1716</span>.</li><li>In X30, for <span class="asm-code">AUTIBSP</span> and <span class="asm-code">AUTIBZ</span>.</li></ul><p class="aml">The modifier is:</p><ul><li>In the general-purpose register or stack pointer that is specified by <Xn|SP> for <span class="asm-code">AUTIB</span>.</li><li>The value zero, for <span class="asm-code">AUTIZB</span> and <span class="asm-code">AUTIBZ</span>.</li><li>In X16, for <span class="asm-code">AUTIB1716</span>.</li><li>In SP, for <span class="asm-code">AUTIBSP</span>.</li></ul><p class="aml">If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. <ins>For</ins><del>If</del> <ins>information</ins><del>the</del> <ins>on</ins><del>authentication</del> <ins>behavior</ins><del>fails,</del> <ins>if</ins><del>the</del> <del>upper bits are corrupted and any subsequent use of </del>the <ins>authentication</ins><del>address</del> <ins>fails,</ins><del>results</del> <ins>see</ins><del>in a Translation fault.</del> <a class="armarm-xref" title="Reference to Armv8 ARM section"><ins>Faulting on pointer authentication</ins></a><ins>.</ins></p><p class="desc">
|
||||
It has encodings from 2 classes:
|
||||
<a href="#iclass_general">Integer</a>
|
||||
and
|
||||
<a href="#iclass_system">System</a></p><h3 class="classheading"><a id="iclass_general"/>Integer<span style="font-size:smaller;"><br/>(FEAT_PAuth)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">1</td><td class="lr">1</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>1</td><td class="r">0</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr">Z</td><td class="l">1</td><td>0</td><td class="r">1</td><td class="lr" colspan="5">Rn</td><td class="lr" colspan="5">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding">AUTIB<span class="bitdiff"> (Z == 0)</span></h4><a id="AUTIB_64P_dp_1src"/><p class="asm-code">AUTIB <a href="#sa_xd" title="64-bit general-purpose destination register (field "Rd")"><Xd></a>, <a href="#sa_xn_sp" title="64-bit general-purpose source register or SP (field "Rn")"><Xn|SP></a></p></div><div class="encoding"><h4 class="encoding">AUTIZB<span class="bitdiff"> (Z == 1 && Rn == 11111)</span></h4><a id="AUTIZB_64Z_dp_1src"/><p class="asm-code">AUTIZB <a href="#sa_xd" title="64-bit general-purpose destination register (field "Rd")"><Xd></a></p></div><p class="pseudocode">boolean source_is_sp = FALSE;
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if !<a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
if Z == '0' then // AUTIB
|
||||
if n == 31 then source_is_sp = TRUE;
|
||||
else // AUTIZB
|
||||
if n != 31 then UNDEFINED;</p><h3 class="classheading"><a id="iclass_system"/>System<span style="font-size:smaller;"><br/>(FEAT_PAuth)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>1</td><td class="r">0</td><td class="l">0</td><td>0</td><td>x</td><td class="r">1</td><td class="l">1</td><td>1</td><td class="r">x</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td></tr><tr class="secondrow"><td colspan="10"/><td/><td colspan="2"/><td colspan="3"/><td colspan="4"/><td class="droppedname" colspan="4">CRm</td><td class="droppedname" colspan="3">op2</td><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">AUTIB1716<span class="bitdiff"> (CRm == 0001 && op2 == 110)</span></h4><a id="AUTIB1716_HI_hints"/><p class="asm-code">AUTIB1716</p></div><div class="encoding"><h4 class="encoding">AUTIBSP<span class="bitdiff"> (CRm == 0011 && op2 == 111)</span></h4><a id="AUTIBSP_HI_hints"/><p class="asm-code">AUTIBSP</p></div><div class="encoding"><h4 class="encoding">AUTIBZ<span class="bitdiff"> (CRm == 0011 && op2 == 110)</span></h4><a id="AUTIBZ_HI_hints"/><p class="asm-code">AUTIBZ</p></div><p class="pseudocode">integer d;
|
||||
integer n;
|
||||
boolean source_is_sp = FALSE;
|
||||
|
||||
case CRm:op2 of
|
||||
when '0011 110' // AUTIBZ
|
||||
d = 30;
|
||||
n = 31;
|
||||
when '0011 111' // AUTIBSP
|
||||
d = 30;
|
||||
source_is_sp = TRUE;
|
||||
when '0001 110' // AUTIB1716
|
||||
d = 17;
|
||||
n = 16;
|
||||
when '0001 000' SEE "PACIA";
|
||||
when '0001 010' SEE "PACIB";
|
||||
when '0001 100' SEE "AUTIA";
|
||||
when '0011 00x' SEE "PACIA";
|
||||
when '0011 01x' SEE "PACIB";
|
||||
when '0011 10x' SEE "AUTIA";
|
||||
when '0000 111' SEE "XPACLRI";
|
||||
otherwise SEE "HINT";</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xd></td><td><a id="sa_xd"/><p class="aml">Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn|SP></td><td><a id="sa_xn_sp"/><p class="aml">Is the 64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">auth_then_branch = FALSE;
|
||||
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
if source_is_sp then
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthIB(X[d, 64], SP[], auth_then_branch);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthIB(X[d, 64], X[n, 64], auth_then_branch);</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,14 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>B.cond -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">B.cond</h2><p class="aml">Branch conditionally to a label at a PC-relative offset, with a hint that this is not a subroutine call or return.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="19">imm19</td><td class="lr">0</td><td class="lr" colspan="4">cond</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="B_only_condbranch"/><p class="asm-code">B.<a href="#sa_cond" title="Standard condition (field "cond")"><cond></a> <a href="#sa_label" title="Label to be conditionally branched to (field imm19)"><label></a></p></div><p class="pseudocode">bits(64) offset = <a href="shared_pseudocode.html#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm19:'00', 64);
|
||||
bits(4) condition = cond;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><cond></td><td><a id="sa_cond"/><p class="aml">Is one of the standard conditions, encoded in the "cond" field in the standard way.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><label></td><td><a id="sa_label"/><p class="aml">Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">boolean branch_conditional = TRUE;
|
||||
if <a href="shared_pseudocode.html#impl-shared.ConditionHolds.1" title="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(condition) then
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchTo.3" title="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + offset, <a href="shared_pseudocode.html#BranchType_DIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a><ins>, branch_conditional);
|
||||
else</ins><del>, branch_conditional);</del>
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchNotTaken.2" title="function: BranchNotTaken(BranchType branchtype, boolean branch_conditional)"><ins>BranchNotTaken</ins></a><ins>(</ins><a href="shared_pseudocode.html#BranchType_DIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}"><ins>BranchType_DIR</ins></a><ins>, branch_conditional);</ins></p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,16 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>B -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">B</h2><p class="aml">Branch causes an unconditional branch to a label at a PC-relative offset, with a hint that this is not a subroutine call or return.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">0</td><td class="l">0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="26">imm26</td></tr><tr class="secondrow"><td class="droppedname">op</td><td colspan="5"/><td colspan="26"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="B_only_branch_imm"/><p class="asm-code">B <a href="#sa_label" title="Label to be unconditionally branched to (field imm26)"><label></a></p></div><p class="pseudocode"><a href="shared_pseudocode.html#BranchType" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type = if op == '1' then <a href="shared_pseudocode.html#BranchType_DIRCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a> else <a href="shared_pseudocode.html#BranchType_DIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>;
|
||||
bits(64) offset = <a href="shared_pseudocode.html#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm26:'00', 64);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><label></td><td><a id="sa_label"/><p class="aml">Is the program label to be unconditionally branched to. Its offset from the address of this instruction, in the range +/-128MB, is encoded as "imm26" times 4.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">if branch_type == <a href="shared_pseudocode.html#BranchType_DIRCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a> <ins>then
|
||||
if</ins><del>then</del> <a href="shared_pseudocode.html#impl-shared.HaveGCS.0" title="function: boolean HaveGCS()"><ins>HaveGCS</ins></a><ins>() && </ins><a href="shared_pseudocode.html#impl-aarch64.GCSPCREnabled.1" title="function: boolean GCSPCREnabled(bits(2) el)"><ins>GCSPCREnabled</ins></a><ins>(PSTATE.EL) then
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.AddGCSRecord.1" title="function: AddGCSRecord(bits(64) vaddress)"><ins>AddGCSRecord</ins></a><ins>(</ins><a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]"><ins>PC</ins></a><ins>[] + 4);
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[30, 64] = <a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + 4;
|
||||
|
||||
boolean branch_conditional = FALSE;
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchTo.3" title="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + offset, branch_type, branch_conditional);</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,16 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BC.cond -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BC.cond</h2><p class="aml">Branch Consistent conditionally to a label at a PC-relative offset, with a hint that this branch will behave very consistently and is very unlikely to change direction.</p><h3 class="classheading"><a id="iclass_br19"/>19-bit signed PC-relative branch offset<span style="font-size:smaller;"><br/>(FEAT_HBC)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="19">imm19</td><td class="lr">1</td><td class="lr" colspan="4">cond</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="BC_only_condbranch"/><p class="asm-code">BC.<a href="#sa_cond" title="Standard condition (field "cond")"><cond></a> <a href="#sa_label" title="Label to be conditionally branched to (field imm19)"><label></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-shared.HaveFeatHBC.0" title="function: boolean HaveFeatHBC()">HaveFeatHBC</a>() then UNDEFINED;
|
||||
bits(64) offset = <a href="shared_pseudocode.html#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm19:'00', 64);
|
||||
bits(4) condition = cond;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><cond></td><td><a id="sa_cond"/><p class="aml">Is one of the standard conditions, encoded in the "cond" field in the standard way.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><label></td><td><a id="sa_label"/><p class="aml">Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">boolean branch_conditional = TRUE;
|
||||
if <a href="shared_pseudocode.html#impl-shared.ConditionHolds.1" title="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(condition) then
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchTo.3" title="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + offset, <a href="shared_pseudocode.html#BranchType_DIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a><ins>, branch_conditional);
|
||||
else</ins><del>, branch_conditional);</del>
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchNotTaken.2" title="function: BranchNotTaken(BranchType branchtype, boolean branch_conditional)"><ins>BranchNotTaken</ins></a><ins>(</ins><a href="shared_pseudocode.html#BranchType_DIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}"><ins>BranchType_DIR</ins></a><ins>, branch_conditional);</ins></p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,22 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BCAX</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BCAX</h2><p>Bitwise clear and exclusive OR</p><p class="aml">Bitwise AND elements of the second source vector with the corresponding inverted elements of the third source vector, then exclusive OR the results with corresponding elements of the first source vector. The final results are destructively placed in the corresponding elements of the destination and first source vector. This instruction is unpredicated.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">0</td><td>0</td><td>1</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="lr" colspan="5">Zk</td><td class="lr" colspan="5">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bcax_z_zzz_"/><p class="asm-code">BCAX <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.D, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.D, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D, <a href="#sa_zk" title="Third source scalable vector register (field "Zk")"><Zk></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer k = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zk);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zk></td><td><a id="sa_zk"/><p class="aml">Is the name of the third source scalable vector register, encoded in the "Zk" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[k, VL];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = operand1 EOR (operand2 AND NOT(operand3));</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,29 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BDEP</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BDEP</h2><p>Scatter lower bits into positions selected by bitmask</p><p class="aml">This instruction scatters the lowest-numbered contiguous bits within each element of the first source vector to the bit positions indicated by non-zero bits in the corresponding mask element of the second source vector, preserving their order, and set the bits corresponding to a zero mask bit to zero. This instruction is unpredicated.</p><p class="aml">ID_AA64ZFR0_EL1.BitPerm indicates whether this instruction is implemented.</p><p class="aml">This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and <ins>enabled.</ins><del>enabled at the current Exception level.</del></p><h3 class="classheading"><a id="iclass_sve2"/>SVE2<span style="font-size:smaller;"><br/>(FEAT_SVE_BitPerm)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="l">1</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bdep_z_zz_"/><p class="asm-code">BDEP <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() || !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2BitPerm.0" title="function: boolean HaveSVE2BitPerm()">HaveSVE2BitPerm</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckNonStreamingSVEEnabled.0" title="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) data = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) mask = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements - 1
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-aarch64.BitDeposit.2" title="function: bits(N) BitDeposit (bits(N) data, bits(N) mask)">BitDeposit</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[data, e, esize], <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[mask, e, esize]);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,29 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BEXT</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BEXT</h2><p>Gather lower bits from positions selected by bitmask</p><p class="aml">This instruction gathers bits in each element of the first source vector from the bit positions indicated by non-zero bits in the corresponding mask element of the second source vector to the lowest-numbered contiguous bits of the corresponding destination element, preserving their order, and sets the remaining higher-numbered bits to zero. This instruction is unpredicated.</p><p class="aml">ID_AA64ZFR0_EL1.BitPerm indicates whether this instruction is implemented.</p><p class="aml">This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and <ins>enabled.</ins><del>enabled at the current Exception level.</del></p><h3 class="classheading"><a id="iclass_sve2"/>SVE2<span style="font-size:smaller;"><br/>(FEAT_SVE_BitPerm)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="l">1</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bext_z_zz_"/><p class="asm-code">BEXT <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() || !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2BitPerm.0" title="function: boolean HaveSVE2BitPerm()">HaveSVE2BitPerm</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckNonStreamingSVEEnabled.0" title="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) data = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) mask = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements - 1
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-aarch64.BitExtract.2" title="function: bits(N) BitExtract (bits(N) data, bits(N) mask)">BitExtract</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[data, e, esize], <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[mask, e, esize]);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
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@@ -1,58 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BFDOT (vectors)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BFDOT (vectors)</h2><p>BFloat16 floating-point dot product</p><p class="aml"><ins>This</ins><del>If</del> <ins>instruction</ins><del>FEAT_EBF16</del> <ins>delimits</ins><del>is</del> <ins>the</ins><del>not</del> <ins>source</ins><del>implemented</del> <ins>vectors</ins><del>or</del> <ins>into</ins><del>FPCR.EBF</del> <ins>pairs</ins><del>is</del> <del>0, irrespective </del>of <ins>BFloat16</ins><del>the</del> <ins>elements.</ins><del>other control bits in the FPCR, this instruction:</del></p><p class="aml"><ins>If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction:</ins></p><ul><li>
|
||||
Performs an unfused sum-of-products of each pair of adjacent BFloat16 elements in the source vectors. The intermediate single-precision products are rounded before they are summed, and the intermediate sum is rounded before accumulation into the single-precision destination element that overlaps with the corresponding pair of BFloat16 elements in the source vectors.
|
||||
</li><li>
|
||||
Uses the non-IEEE 754 Round-to-Odd rounding mode, which forces bit 0 of an inexact result to 1, and rounds an overflow to an appropriately signed Infinity.
|
||||
</li><li><del>
|
||||
Does not modify the cumulative FPSR exception bits (IDC, IXC, UFC, OFC, DZC, and IOC).
|
||||
</del></li><li><del>
|
||||
Disables trapped floating-point exceptions, as if the FPCR trap enable bits (IDE, IXE, UFE, OFE, DZE, and IOE) are all zero.
|
||||
</del></li><li>
|
||||
Flushes denormalized inputs and results to zero, as if FPCR.{FZ, FIZ} is {1, 1}.
|
||||
</li><li>
|
||||
<ins>Disables</ins><del>Generates</del> <ins>alternative</ins><del>only</del> <ins>floating</ins><del>the</del> <ins>point</ins><del>Default</del> <ins>behaviors</ins><del>NaN</del>, as if <ins>FPCR.AH</ins><del>FPCR.DN</del> is <ins>0.</ins><del>1.</del>
|
||||
</li></ul><p class="aml">If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction:</p><ul><li>
|
||||
Performs a fused sum-of-products of each pair of adjacent BFloat16 elements in the source vectors. The intermediate single-precision products are not rounded before they are summed, but the intermediate sum is rounded before accumulation into the single-precision destination element that overlaps with the corresponding pair of BFloat16 elements in the source vectors.
|
||||
</li><li><del>
|
||||
Follows all other floating-point behaviors that apply to single-precision arithmetic, as controlled by the effective value of the FPCR in the current execution mode, and captured in the FPSR.
|
||||
</del></li><li>
|
||||
<ins>Follows</ins><del>Generates</del> <ins>all</ins><del>only</del> <ins>other</ins><del>the</del> <ins>floating-point</ins><del>default</del> <ins>behaviors that apply to single-precision arithmetic</ins><del>NaN</del>, as <ins>governed</ins><del>if</del> <ins>by</ins><del>FPCR.DN</del> <ins>FPCR.RMode,</ins><del>is</del> <ins>FPCR.FZ, FPCR.AH, and FPCR.FIZ.</ins><del>1.</del>
|
||||
</li></ul><p class="aml"><ins>Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction:</ins></p><ul><li><ins>
|
||||
Does not modify the cumulative FPSR exception bits (IDC, IXC, UFC, OFC, DZC, and IOC).
|
||||
</ins></li><li><ins>
|
||||
Disables trapped floating-point exceptions, as if the FPCR trap enable bits (IDE, IXE, UFE, OFE, DZE, and IOE) are all zero.
|
||||
</ins></li><li><ins>
|
||||
Generates only the default NaN, as if FPCR.DN is 1.
|
||||
</ins></li></ul><p class="aml">This instruction is unpredicated.</p><p class="aml">ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.</p><h3 class="classheading"><a id="iclass_sve"/>SVE<span style="font-size:smaller;"><br/>(FEAT_BF16)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">1</td><td class="r">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zda</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bfdot_z_zzz_"/><p class="asm-code">BFDOT <a href="#sa_zda" title="Third source and destination scalable vector register (field "Zda")"><Zda></a>.S, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.H, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.H</p></div><p class="pseudocode">if (!<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>()) || !<a href="shared_pseudocode.html#impl-shared.HaveBF16Ext.0" title="function: boolean HaveBF16Ext()">HaveBF16Ext</a>() then UNDEFINED;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zda);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zda></td><td><a id="sa_zda"/><p class="aml">Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV 32;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(16) elt1_a = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 0, 16];
|
||||
bits(16) elt1_b = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 1, 16];
|
||||
bits(16) elt2_a = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + 0, 16];
|
||||
bits(16) elt2_b = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * e + 1, 16];
|
||||
bits(32) sum = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 32];
|
||||
|
||||
sum = <a href="shared_pseudocode.html#impl-shared.BFDotAdd.6" title="function: bits(32) BFDotAdd(bits(32) addend, bits(16) op1_a, bits(16) op1_b, bits(16) op2_a, bits(16) op2_b, FPCRType fpcr_in)">BFDotAdd</a>(sum, elt1_a, elt1_b, elt2_a, elt2_b, FPCR[]);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = sum;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</p></div><h3>Operational information</h3><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,62 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BFDOT (indexed)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BFDOT (indexed)</h2><p>BFloat16 floating-point indexed dot product</p><p class="aml"><ins>This</ins><del>If</del> <ins>instruction</ins><del>FEAT_EBF16</del> <ins>delimits</ins><del>is</del> <ins>the</ins><del>not</del> <ins>source</ins><del>implemented</del> <ins>vectors</ins><del>or</del> <ins>into</ins><del>FPCR.EBF</del> <ins>pairs</ins><del>is</del> <ins>of</ins><del>0,</del> <ins>BFloat16</ins><del>irrespective</del> <ins>elements.</ins><del>of</del> <ins>The BFloat16 pairs within </ins>the <ins>second</ins><del>other</del> <ins>source</ins><del>control</del> <ins>vector</ins><del>bits</del> <ins>are</ins><del>in</del> <ins>specified using an immediate index which selects </ins>the <ins>same</ins><del>FPCR,</del> <ins>BFloat16</ins><del>this</del> <ins>pair position within each 128-bit vector segment. The index range is from 0 to 3.</ins><del>instruction:</del></p><p class="aml"><ins>If FEAT_EBF16 is not implemented or FPCR.EBF is 0, this instruction:</ins></p><ul><li>
|
||||
Performs an unfused sum-of-products of each pair of adjacent BFloat16 elements in the first source vector with the specified pair of elements in the second vector. The intermediate single-precision products are rounded before they are summed, and the intermediate sum is rounded before accumulation into the single-precision destination element that overlaps with the corresponding pair of BFloat16 elements in the first source vector.
|
||||
</li><li>
|
||||
Uses the non-IEEE 754 Round-to-Odd rounding mode, which forces bit 0 of an inexact result to 1, and rounds an overflow to an appropriately signed Infinity.
|
||||
</li><li><del>
|
||||
Does not modify the cumulative FPSR exception bits (IDC, IXC, UFC, OFC, DZC, and IOC).
|
||||
</del></li><li><del>
|
||||
Disables trapped floating-point exceptions, as if the FPCR trap enable bits (IDE, IXE, UFE, OFE, DZE, and IOE) are all zero.
|
||||
</del></li><li>
|
||||
Flushes denormalized inputs and results to zero, as if FPCR.{FZ, FIZ} is {1, 1}.
|
||||
</li><li>
|
||||
<ins>Disables</ins><del>Generates</del> <ins>alternative</ins><del>only</del> <ins>floating</ins><del>the</del> <ins>point</ins><del>Default</del> <ins>behaviors</ins><del>NaN</del>, as if <ins>FPCR.AH</ins><del>FPCR.DN</del> is <ins>0.</ins><del>1.</del>
|
||||
</li></ul><p class="aml">If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction:</p><ul><li>
|
||||
Performs a fused sum-of-products of each pair of adjacent BFloat16 elements in the first source vector with the specified pair of elements in the second vector. The intermediate single-precision products are not rounded before they are summed, but the intermediate sum is rounded before accumulation into the single-precision destination element that overlaps with the corresponding pair of BFloat16 elements in the first source vector.
|
||||
</li><li><del>
|
||||
Follows all other floating-point behaviors that apply to single-precision arithmetic, as controlled by the effective value of the FPCR in the current execution mode, and captured in the FPSR.
|
||||
</del></li><li>
|
||||
<ins>Follows</ins><del>Generates</del> <ins>all</ins><del>only</del> <ins>other</ins><del>the</del> <ins>floating-point</ins><del>default</del> <ins>behaviors that apply to single-precision arithmetic</ins><del>NaN</del>, as <ins>governed</ins><del>if</del> <ins>by</ins><del>FPCR.DN</del> <ins>FPCR.RMode,</ins><del>is</del> <ins>FPCR.FZ, FPCR.AH, and FPCR.FIZ.</ins><del>1.</del>
|
||||
</li></ul><p class="aml"><ins>Irrespective</ins><del>The</del> <ins>of</ins><del>BFloat16</del> <ins>FEAT_EBF16</ins><del>pairs</del> <ins>and</ins><del>within</del> <ins>FPCR.EBF,</ins><del>the</del> <ins>this</ins><del>second</del> <ins>instruction:</ins><del>source vector are specified using an immediate index which selects the same BFloat16 pair position within each 128-bit vector segment. The index range is from 0 to 3.</del></p><ul><li><ins>
|
||||
Does not modify the cumulative FPSR exception bits (IDC, IXC, UFC, OFC, DZC, and IOC).
|
||||
</ins></li><li><ins>
|
||||
Disables trapped floating-point exceptions, as if the FPCR trap enable bits (IDE, IXE, UFE, OFE, DZE, and IOE) are all zero.
|
||||
</ins></li><li><ins>
|
||||
Generates only the default NaN, as if FPCR.DN is 1.
|
||||
</ins></li></ul><p class="aml">This instruction is unpredicated.</p><p class="aml">ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.</p><h3 class="classheading"><a id="iclass_sve"/>SVE<span style="font-size:smaller;"><br/>(FEAT_BF16)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="2">i2</td><td class="lr" colspan="3">Zm</td><td class="l">0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zda</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bfdot_z_zzzi_"/><p class="asm-code">BFDOT <a href="#sa_zda" title="Third source and destination scalable vector register (field "Zda")"><Zda></a>.S, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.H, <a href="#sa_zm" title="Second source scalable vector register Z0-Z7 (field "Zm")"><Zm></a>.H[<a href="#sa_imm" title="Immediate index [0-3] (field "i2")"><imm></a>]</p></div><p class="pseudocode">if (!<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>()) || !<a href="shared_pseudocode.html#impl-shared.HaveBF16Ext.0" title="function: boolean HaveBF16Ext()">HaveBF16Ext</a>() then UNDEFINED;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zda);
|
||||
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(i2);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zda></td><td><a id="sa_zda"/><p class="aml">Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><imm></td><td><a id="sa_imm"/><p class="aml">Is the immediate index, in the range 0 to 3, encoded in the "i2" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV 32;
|
||||
constant integer eltspersegment = 128 DIV 32;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
integer segmentbase = e - (e MOD eltspersegment);
|
||||
integer s = segmentbase + index;
|
||||
bits(16) elt1_a = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 0, 16];
|
||||
bits(16) elt1_b = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * e + 1, 16];
|
||||
bits(16) elt2_a = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * s + 0, 16];
|
||||
bits(16) elt2_b = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * s + 1, 16];
|
||||
bits(32) sum = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 32];
|
||||
|
||||
sum = <a href="shared_pseudocode.html#impl-shared.BFDotAdd.6" title="function: bits(32) BFDotAdd(bits(32) addend, bits(16) op1_a, bits(16) op1_b, bits(16) op2_a, bits(16) op2_b, FPCRType fpcr_in)">BFDotAdd</a>(sum, elt1_a, elt1_b, elt2_a, elt2_b, FPCR[]);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 32] = sum;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</p></div><h3>Operational information</h3><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
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@@ -1,57 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BFMMLA</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BFMMLA</h2><p>BFloat16 floating-point matrix multiply-accumulate<ins> into 2×2 matrices</ins></p><p class="aml">If FEAT_EBF16 is not implemented or FPCR.EBF is 0, <del>irrespective of the other control bits in the FPCR, </del>this instruction:</p><ul><li>
|
||||
Performs two unfused sums-of-products within each two pairs of adjacent BFloat16 elements while multiplying the 2×4 matrix of BFloat16 values held in each 128-bit segment of the first source vector by the 4×2 matrix of BFloat16 values in the corresponding segment of the second source vector. The intermediate single-precision products are rounded before they are summed and the intermediate sum is rounded before accumulation into the 2×2 single-precision matrix in the corresponding segment of the destination vector. This is equivalent to accumulating two 2-way unfused dot products per destination element.
|
||||
</li><li>
|
||||
Uses the non-IEEE 754 Round-to-Odd rounding mode, which forces bit 0 of an inexact result to 1, and rounds an overflow to an appropriately signed Infinity.
|
||||
</li><li><del>
|
||||
Does not modify the cumulative FPSR exception bits (IDC, IXC, UFC, OFC, DZC, and IOC).
|
||||
</del></li><li><del>
|
||||
Disables trapped floating-point exceptions, as if the FPCR trap enable bits (IDE, IXE, UFE, OFE, DZE, and IOE) are all zero.
|
||||
</del></li><li>
|
||||
Flushes denormalized inputs and results to zero, as if FPCR.{FZ, FIZ} is {1, 1}.
|
||||
</li><li>
|
||||
<ins>Disables</ins><del>Generates</del> <ins>alternative</ins><del>only</del> <ins>floating</ins><del>the</del> <ins>point</ins><del>Default</del> <ins>behaviors</ins><del>NaN</del>, as if <ins>FPCR.AH</ins><del>FPCR.DN</del> is <ins>0.</ins><del>1.</del>
|
||||
</li></ul><p class="aml">If FEAT_EBF16 is implemented and FPCR.EBF is 1, then this instruction:</p><ul><li>
|
||||
Performs two fused sums-of-products within each two pairs of adjacent BFloat16 elements while multiplying the 2×4 matrix of BFloat16 values held in each 128-bit segment of the first source vector by the 4×2 matrix of BFloat16 values in the corresponding segment of the second source vector. The intermediate single-precision products are not rounded before they are summed, but the intermediate sum is rounded before accumulation into the 2×2 single-precision matrix in the corresponding segment of the destination vector. This is equivalent to accumulating two 2-way fused dot products per destination element.
|
||||
</li><li><del>
|
||||
Follows all other floating-point behaviors that apply to single-precision arithmetic, as controlled by the effective value of the FPCR in the current execution mode, and captured in the FPSR.
|
||||
</del></li><li>
|
||||
<ins>Follows</ins><del>Generates</del> <ins>all</ins><del>only</del> <ins>other</ins><del>the</del> <ins>floating-point</ins><del>default</del> <ins>behaviors that apply to single-precision arithmetic</ins><del>NaN</del>, as <ins>governed</ins><del>if</del> <ins>by</ins><del>FPCR.DN</del> <ins>FPCR.RMode,</ins><del>is</del> <ins>FPCR.FZ, FPCR.AH, and FPCR.FIZ.</ins><del>1.</del>
|
||||
</li></ul><p class="aml"><ins>Irrespective of FEAT_EBF16 and FPCR.EBF, this instruction:</ins></p><ul><li><ins>
|
||||
Does not modify the cumulative FPSR exception bits (IDC, IXC, UFC, OFC, DZC, and IOC).
|
||||
</ins></li><li><ins>
|
||||
Disables trapped floating-point exceptions, as if the FPCR trap enable bits (IDE, IXE, UFE, OFE, DZE, and IOE) are all zero.
|
||||
</ins></li><li><ins>
|
||||
Generates only the default NaN, as if FPCR.DN is 1.
|
||||
</ins></li></ul><p class="aml">This instruction is unpredicated and vector length agnostic.</p><p class="aml">ID_AA64ZFR0_EL1.BF16 indicates whether this instruction is implemented.</p><p class="aml">This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and <ins>enabled.</ins><del>enabled at the current Exception level.</del></p><h3 class="classheading"><a id="iclass_sve"/>SVE<span style="font-size:smaller;"><br/>(FEAT_BF16)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">1</td><td>1</td><td>1</td><td>0</td><td>0</td><td class="r">1</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zda</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bfmmla_z_zzz_"/><p class="asm-code">BFMMLA <a href="#sa_zda" title="Third source and destination scalable vector register (field "Zda")"><Zda></a>.S, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.H, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.H</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() || !<a href="shared_pseudocode.html#impl-shared.HaveBF16Ext.0" title="function: boolean HaveBF16Ext()">HaveBF16Ext</a>() then UNDEFINED;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zda);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zda></td><td><a id="sa_zda"/><p class="aml">Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckNonStreamingSVEEnabled.0" title="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer segments = VL DIV 128;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
|
||||
bits(VL) result;
|
||||
bits(128) op1, op2;
|
||||
bits(128) res, addend;
|
||||
|
||||
for s = 0 to segments-1
|
||||
op1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, s, 128];
|
||||
op2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, s, 128];
|
||||
addend = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, s, 128];
|
||||
res = <a href="shared_pseudocode.html#impl-shared.BFMatMulAdd.3" title="function: bits(N) BFMatMulAdd(bits(N) addend, bits(N) op1, bits(N) op2)">BFMatMulAdd</a>(addend, op1, op2);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, s, 128] = res;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</p></div><h3>Operational information</h3><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,29 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BGRP</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BGRP</h2><p>Group bits to right or left as selected by bitmask</p><p class="aml">This instruction separates bits in each element of the first source vector by gathering from the bit positions indicated by non-zero bits in the corresponding mask element of the second source vector to the lowest-numbered contiguous bits of the corresponding destination element, and from positions indicated by zero bits to the highest-numbered bits of the destination element, preserving the bit order within each group. This instruction is unpredicated.</p><p class="aml">ID_AA64ZFR0_EL1.BitPerm indicates whether this instruction is implemented.</p><p class="aml">This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and <ins>enabled.</ins><del>enabled at the current Exception level.</del></p><h3 class="classheading"><a id="iclass_sve2"/>SVE2<span style="font-size:smaller;"><br/>(FEAT_SVE_BitPerm)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="l">1</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="lr">0</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bgrp_z_zz_"/><p class="asm-code">BGRP <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() || !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2BitPerm.0" title="function: boolean HaveSVE2BitPerm()">HaveSVE2BitPerm</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckNonStreamingSVEEnabled.0" title="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) data = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) mask = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements - 1
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-aarch64.BitGroup.2" title="function: bits(N) BitGroup (bits(N) data, bits(N) mask)">BitGroup</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[data, e, esize], <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[mask, e, esize]);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,27 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BIC (immediate)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BIC (immediate)</h2><p>Bitwise clear bits using immediate (unpredicated)</p><p class="aml">Bitwise clear bits using immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. This instruction is unpredicated.</p><p>
|
||||
This is a pseudo-instruction of
|
||||
<a href="and_z_zi.html">AND (immediate)</a>.
|
||||
This means:
|
||||
</p><ul><li>
|
||||
The encodings in this description are named to match the encodings of
|
||||
<a href="and_z_zi.html">AND (immediate)</a>.
|
||||
</li><li>
|
||||
The assembler syntax is used only for assembly, and is not used on disassembly.
|
||||
</li><li>The description of <a href="and_z_zi.html">AND (immediate)</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="lr">0</td><td class="l">0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr" colspan="13">imm13</td><td class="lr" colspan="5">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="BIC_and_z_zi_"/><p class="asm-code">BIC <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a>, <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a>, #<a href="#sa_const" title="64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits (field "imm13")"><const></a></p><p class="equivto">
|
||||
is equivalent to
|
||||
</p><p class="asm-code"><a href="and_z_zi.html#and_z_zi_">AND</a> <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a>, <a href="#sa_zdn" title="Source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a>, #(-<a href="#sa_const" title="64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits (field "imm13")"><const></a> - 1)</p></div><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>imm13<12>:imm13<5:0></q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">imm13<12></th><th class="bitfield">imm13<5:0></th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">0</td><td class="bitfield">0xxxxx</td><td class="symbol">S</td></tr><tr><td class="bitfield">0</td><td class="bitfield">10xxxx</td><td class="symbol">H</td></tr><tr><td class="bitfield">0</td><td class="bitfield">110xxx</td><td class="symbol">B</td></tr><tr><td class="bitfield">0</td><td class="bitfield">1110xx</td><td class="symbol">B</td></tr><tr><td class="bitfield">0</td><td class="bitfield">11110x</td><td class="symbol">B</td></tr><tr><td class="bitfield">0</td><td class="bitfield">111110</td><td class="symbol">RESERVED</td></tr><tr><td class="bitfield">0</td><td class="bitfield">111111</td><td class="symbol">RESERVED</td></tr><tr><td class="bitfield">1</td><td class="bitfield">xxxxxx</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><const></td><td><a id="sa_const"/><p class="aml">Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="and_z_zi.html">AND (immediate)</a> gives the operational pseudocode for this instruction.</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,37 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BIC (predicates)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BIC (predicates)</h2><p>Bitwise clear predicates</p><p class="aml">Bitwise AND inverted active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="lr" colspan="4">Pm</td><td class="l">0</td><td class="r">1</td><td class="lr" colspan="4">Pg</td><td class="lr">0</td><td class="lr" colspan="4">Pn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td/><td class="droppedname">S</td><td colspan="2"/><td colspan="4"/><td colspan="2"/><td colspan="4"/><td/><td colspan="4"/><td/><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bic_p_p_pp_z"/><p class="asm-code">BIC <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.B, <a href="#sa_pg" title="Governing scalable predicate register (field "Pg")"><Pg></a>/Z, <a href="#sa_pn" title="First source scalable predicate register (field "Pn")"><Pn></a>.B, <a href="#sa_pm" title="Second source scalable predicate register (field "Pm")"><Pm></a>.B</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8;
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
boolean setflags = FALSE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pd></td><td><a id="sa_pd"/><p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pn></td><td><a id="sa_pn"/><p class="aml">Is the name of the first source scalable predicate register, encoded in the "Pn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pm></td><td><a id="sa_pm"/><p class="aml">Is the name of the second source scalable predicate register, encoded in the "Pm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(PL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[n, PL];
|
||||
bits(PL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[m, PL];
|
||||
bits(PL) result;
|
||||
constant integer psize = esize DIV 8;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bit element1 = <a href="shared_pseudocode.html#impl-aarch64.PredicateElement.3" title="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand1, e, esize);
|
||||
bit element2 = <a href="shared_pseudocode.html#impl-aarch64.PredicateElement.3" title="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand2, e, esize);
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(element1 AND (NOT element2), psize);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', psize);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = <a href="shared_pseudocode.html#impl-aarch64.PredTest.3" title="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</a>(mask, result, esize);
|
||||
<a href="shared_pseudocode.html#impl-aarch64.P.write.2" title="accessor: P[integer n, integer width] = bits(width) value">P</a>[d, PL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,37 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BIC (vectors, predicated)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BIC (vectors, predicated)</h2><p>Bitwise clear vectors (predicated)</p><p class="aml">Bitwise AND inverted active elements of the second source vector with corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td class="r">1</td><td class="lr">1</td><td class="l">0</td><td>0</td><td class="r">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="5">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bic_z_p_zz_"/><p class="asm-code">BIC <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 AND (NOT element2);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,19 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BIC (vectors, unpredicated)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BIC (vectors, unpredicated)</h2><p>Bitwise clear vectors (unpredicated)</p><p class="aml">Bitwise AND inverted all elements of the second source vector with corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. This instruction is unpredicated.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">0</td><td>0</td><td>1</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bic_z_zz_"/><p class="asm-code">BIC <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.D, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.D, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = operand1 AND (NOT operand2);</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,37 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BICS</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BICS</h2><p>Bitwise clear predicates, setting the condition flags</p><p class="aml">Bitwise AND inverted active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the <span class="arm-defined-word">First</span> (N), <span class="arm-defined-word">None</span> (Z), <span class="arm-defined-word">!Last</span> (C) condition flags based on the predicate result, and the V flag to zero.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr">1</td><td class="l">0</td><td class="r">0</td><td class="lr" colspan="4">Pm</td><td class="l">0</td><td class="r">1</td><td class="lr" colspan="4">Pg</td><td class="lr">0</td><td class="lr" colspan="4">Pn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td/><td class="droppedname">S</td><td colspan="2"/><td colspan="4"/><td colspan="2"/><td colspan="4"/><td/><td colspan="4"/><td/><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bics_p_p_pp_z"/><p class="asm-code">BICS <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.B, <a href="#sa_pg" title="Governing scalable predicate register (field "Pg")"><Pg></a>/Z, <a href="#sa_pn" title="First source scalable predicate register (field "Pn")"><Pn></a>.B, <a href="#sa_pm" title="Second source scalable predicate register (field "Pm")"><Pm></a>.B</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8;
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
boolean setflags = TRUE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pd></td><td><a id="sa_pd"/><p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pn></td><td><a id="sa_pn"/><p class="aml">Is the name of the first source scalable predicate register, encoded in the "Pn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pm></td><td><a id="sa_pm"/><p class="aml">Is the name of the second source scalable predicate register, encoded in the "Pm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(PL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[n, PL];
|
||||
bits(PL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[m, PL];
|
||||
bits(PL) result;
|
||||
constant integer psize = esize DIV 8;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bit element1 = <a href="shared_pseudocode.html#impl-aarch64.PredicateElement.3" title="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand1, e, esize);
|
||||
bit element2 = <a href="shared_pseudocode.html#impl-aarch64.PredicateElement.3" title="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand2, e, esize);
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(element1 AND (NOT element2), psize);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', psize);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = <a href="shared_pseudocode.html#impl-aarch64.PredTest.3" title="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</a>(mask, result, esize);
|
||||
<a href="shared_pseudocode.html#impl-aarch64.P.write.2" title="accessor: P[integer n, integer width] = bits(width) value">P</a>[d, PL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the NZCV condition flags written by this instruction might be significantly delayed.</p><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,16 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BL -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BL</h2><p class="aml">Branch with Link branches to a PC-relative offset, setting the register X30 to PC+4. It provides a hint that this is a subroutine call.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">1</td><td class="l">0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="26">imm26</td></tr><tr class="secondrow"><td class="droppedname">op</td><td colspan="5"/><td colspan="26"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="BL_only_branch_imm"/><p class="asm-code">BL <a href="#sa_label" title="Label to be unconditionally branched to (field imm26)"><label></a></p></div><p class="pseudocode"><a href="shared_pseudocode.html#BranchType" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type = if op == '1' then <a href="shared_pseudocode.html#BranchType_DIRCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a> else <a href="shared_pseudocode.html#BranchType_DIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>;
|
||||
bits(64) offset = <a href="shared_pseudocode.html#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm26:'00', 64);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><label></td><td><a id="sa_label"/><p class="aml">Is the program label to be unconditionally branched to. Its offset from the address of this instruction, in the range +/-128MB, is encoded as "imm26" times 4.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">if branch_type == <a href="shared_pseudocode.html#BranchType_DIRCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a> <ins>then
|
||||
if</ins><del>then</del> <a href="shared_pseudocode.html#impl-shared.HaveGCS.0" title="function: boolean HaveGCS()"><ins>HaveGCS</ins></a><ins>() && </ins><a href="shared_pseudocode.html#impl-aarch64.GCSPCREnabled.1" title="function: boolean GCSPCREnabled(bits(2) el)"><ins>GCSPCREnabled</ins></a><ins>(PSTATE.EL) then
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.AddGCSRecord.1" title="function: AddGCSRecord(bits(64) vaddress)"><ins>AddGCSRecord</ins></a><ins>(</ins><a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]"><ins>PC</ins></a><ins>[] + 4);
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[30, 64] = <a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + 4;
|
||||
|
||||
boolean branch_conditional = FALSE;
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchTo.3" title="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + offset, branch_type, branch_conditional);</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,78 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BLR -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BLR</h2><p class="aml">Branch with Link to Register calls a subroutine at an address in a register, setting register X30 to PC+4.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td class="r">1</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="5">Rn</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td></tr><tr class="secondrow"><td colspan="7"/><td class="droppedname">Z</td><td/><td class="droppedname" colspan="2">op</td><td colspan="5"/><td colspan="4"/><td class="droppedname">A</td><td class="droppedname">M</td><td colspan="5"/><td class="droppedname" colspan="5">Rm</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="BLR_64_branch_reg"/><p class="asm-code">BLR <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field "Rn")"><Xn></a></p></div><p class="pseudocode">integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
<a href="shared_pseudocode.html#BranchType" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type;
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
boolean pac = (A == '1');
|
||||
boolean use_key_a = (M == '0');
|
||||
boolean source_is_sp = ((Z == '1') && (m == 31));
|
||||
|
||||
if !pac && m != 0 then
|
||||
UNDEFINED;
|
||||
elsif pac && !<a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
case op of
|
||||
when '00' branch_type = <a href="shared_pseudocode.html#BranchType_INDIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>;
|
||||
when '01' branch_type = <a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a>;
|
||||
when '10' branch_type = <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a>;
|
||||
otherwise UNDEFINED;
|
||||
|
||||
if pac then
|
||||
if Z == '0' && m != 31 then
|
||||
UNDEFINED;
|
||||
|
||||
if branch_type == <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a> then
|
||||
if n != 31 then UNDEFINED;
|
||||
n = 30;
|
||||
source_is_sp = TRUE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn></td><td><a id="sa_xn"/><p class="aml">Is the 64-bit name of the general-purpose register holding the address to be branched to, encoded in the "Rn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#GCSInstruction" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstruction</ins></a> <ins>inst_type;
|
||||
</ins>bits(64) target = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
boolean auth_then_branch = TRUE;
|
||||
|
||||
if pac then
|
||||
bits(64) modifier = if source_is_sp then <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[] else <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[m, 64];
|
||||
|
||||
if use_key_a then
|
||||
target = <a href="shared_pseudocode.html#impl-aarch64.AuthIA.3" title="function: bits(64) AuthIA(bits(64) x, bits(64) y, boolean is_combined)">AuthIA</a>(target, modifier, auth_then_branch);
|
||||
else
|
||||
target = <a href="shared_pseudocode.html#impl-aarch64.AuthIB.3" title="function: bits(64) AuthIB(bits(64) x, bits(64) y, boolean is_combined)">AuthIB</a>(target, modifier, auth_then_branch);
|
||||
|
||||
if branch_type == <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}"><ins>BranchType_RET</ins></a><ins> && </ins><a href="shared_pseudocode.html#impl-shared.HaveGCS.0" title="function: boolean HaveGCS()"><ins>HaveGCS</ins></a><ins>() && </ins><a href="shared_pseudocode.html#impl-aarch64.GCSPCREnabled.1" title="function: boolean GCSPCREnabled(bits(2) el)"><ins>GCSPCREnabled</ins></a><ins>(PSTATE.EL) then
|
||||
if !pac then
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRET" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRET</ins></a><ins>;
|
||||
else
|
||||
if use_key_a then
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRETAA" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRETAA</ins></a><ins>;
|
||||
else
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRETAB" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRETAB</ins></a><ins>;
|
||||
target = </ins><a href="shared_pseudocode.html#impl-aarch64.LoadCheckGCSRecord.2" title="function: bits(64) LoadCheckGCSRecord(bits(64) vaddress, GCSInstruction gcsinst_type)"><ins>LoadCheckGCSRecord</ins></a><ins>(target, inst_type);
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.SetCurrentGCSPointer.1" title="function: SetCurrentGCSPointer(bits(64) ptr)"><ins>SetCurrentGCSPointer</ins></a><ins>(</ins><a href="shared_pseudocode.html#impl-aarch64.GetCurrentGCSPointer.0" title="function: bits(64) GetCurrentGCSPointer()"><ins>GetCurrentGCSPointer</ins></a><ins>() + 8);
|
||||
|
||||
if branch_type == </ins><a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a><ins> then
|
||||
if </ins><a href="shared_pseudocode.html#impl-shared.HaveGCS.0" title="function: boolean HaveGCS()"><ins>HaveGCS</ins></a><ins>() && </ins><a href="shared_pseudocode.html#impl-aarch64.GCSPCREnabled.1" title="function: boolean GCSPCREnabled(bits(2) el)"><ins>GCSPCREnabled</ins></a><ins>(PSTATE.EL) then
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.AddGCSRecord.1" title="function: AddGCSRecord(bits(64) vaddress)"><ins>AddGCSRecord</ins></a><ins>(</ins><a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]"><ins>PC</ins></a><ins>[] + 4);</ins><del>then</del>
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[30, 64] = <a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + 4;
|
||||
|
||||
// Value in BTypeNext will be used to set PSTATE.BTYPE
|
||||
case branch_type of
|
||||
when <a href="shared_pseudocode.html#BranchType_INDIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a> // BR, BRAA, BRAB, BRAAZ, BRABZ
|
||||
if InGuardedPage then
|
||||
if n == 16 || n == 17 then
|
||||
BTypeNext = '01';
|
||||
else
|
||||
BTypeNext = '11';
|
||||
else
|
||||
BTypeNext = '01';
|
||||
when <a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a> // BLR, BLRAA, BLRAB, BLRAAZ, BLRABZ
|
||||
BTypeNext = '10';
|
||||
when <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a> // RET, RETAA, RETAB
|
||||
BTypeNext = '00';
|
||||
|
||||
boolean branch_conditional = FALSE;
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchTo.3" title="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(target, branch_type, branch_conditional);</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,79 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BLRAA, BLRAAZ, BLRAB, BLRABZ -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BLRAA, BLRAAZ, BLRAB, BLRABZ</h2><p class="aml">Branch with Link to Register, with pointer authentication. This instruction authenticates the address in the general-purpose register that is specified by <Xn>, using a modifier and the specified key, and calls a subroutine at the authenticated address, setting register X30 to PC+4.</p><p class="aml">The modifier is:</p><ul><li>In the general-purpose register or stack pointer that is specified by <Xm|SP> for <span class="asm-code">BLRAA</span> and <span class="asm-code">BLRAB</span>.</li><li>The value zero, for <span class="asm-code">BLRAAZ</span> and <span class="asm-code">BLRABZ</span>.</li></ul><p class="aml">Key A is used for <span class="asm-code">BLRAA</span> and <span class="asm-code">BLRAAZ</span><ins>.</ins><del>,</del> <ins>Key</ins><del>and key</del> B is used for <span class="asm-code">BLRAB</span> and <span class="asm-code">BLRABZ</span>.</p><p class="aml">If the authentication passes, the PE continues execution at the target of the branch. <ins>For</ins><del>If</del> <ins>information on behavior if </ins>the authentication fails, <ins>see</ins><del>a Translation fault is generated.</del> <a class="armarm-xref" title="Reference to Armv8 ARM section"><ins>Faulting on pointer authentication</ins></a><ins>.</ins></p><p class="aml">The authenticated address is not written back to the general-purpose register.</p><h3 class="classheading"><a id="iclass_general"/>Integer<span style="font-size:smaller;"><br/>(FEAT_PAuth)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">Z</td><td class="lr">0</td><td class="l">0</td><td class="r">1</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">M</td><td class="lr" colspan="5">Rn</td><td class="lr" colspan="5">Rm</td></tr><tr class="secondrow"><td colspan="7"/><td/><td/><td class="droppedname" colspan="2">op</td><td colspan="5"/><td colspan="4"/><td class="droppedname">A</td><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">Key A, zero modifier<span class="bitdiff"> (Z == 0 && M == 0 && Rm == 11111)</span></h4><a id="BLRAAZ_64_branch_reg"/><p class="asm-code">BLRAAZ <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field "Rn")"><Xn></a></p></div><div class="encoding"><h4 class="encoding">Key A, register modifier<span class="bitdiff"> (Z == 1 && M == 0)</span></h4><a id="BLRAA_64P_branch_reg"/><p class="asm-code">BLRAA <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field "Rn")"><Xn></a>, <a href="#sa_xm_sp" title="64-bit general-purpose source register or SP holding modifier (field "Rm")"><Xm|SP></a></p></div><div class="encoding"><h4 class="encoding">Key B, zero modifier<span class="bitdiff"> (Z == 0 && M == 1 && Rm == 11111)</span></h4><a id="BLRABZ_64_branch_reg"/><p class="asm-code">BLRABZ <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field "Rn")"><Xn></a></p></div><div class="encoding"><h4 class="encoding">Key B, register modifier<span class="bitdiff"> (Z == 1 && M == 1)</span></h4><a id="BLRAB_64P_branch_reg"/><p class="asm-code">BLRAB <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field "Rn")"><Xn></a>, <a href="#sa_xm_sp" title="64-bit general-purpose source register or SP holding modifier (field "Rm")"><Xm|SP></a></p></div><p class="pseudocode">integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
<a href="shared_pseudocode.html#BranchType" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type;
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
boolean pac = (A == '1');
|
||||
boolean use_key_a = (M == '0');
|
||||
boolean source_is_sp = ((Z == '1') && (m == 31));
|
||||
|
||||
if !pac && m != 0 then
|
||||
UNDEFINED;
|
||||
elsif pac && !<a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
case op of
|
||||
when '00' branch_type = <a href="shared_pseudocode.html#BranchType_INDIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>;
|
||||
when '01' branch_type = <a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a>;
|
||||
when '10' branch_type = <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a>;
|
||||
otherwise UNDEFINED;
|
||||
|
||||
if pac then
|
||||
if Z == '0' && m != 31 then
|
||||
UNDEFINED;
|
||||
|
||||
if branch_type == <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a> then
|
||||
if n != 31 then UNDEFINED;
|
||||
n = 30;
|
||||
source_is_sp = TRUE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn></td><td><a id="sa_xn"/><p class="aml">Is the 64-bit name of the general-purpose register holding the address to be branched to, encoded in the "Rn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xm|SP></td><td><a id="sa_xm_sp"/><p class="aml">Is the 64-bit name of the general-purpose source register or stack pointer holding the modifier, encoded in the "Rm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#GCSInstruction" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstruction</ins></a> <ins>inst_type;
|
||||
</ins>bits(64) target = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
boolean auth_then_branch = TRUE;
|
||||
|
||||
if pac then
|
||||
bits(64) modifier = if source_is_sp then <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[] else <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[m, 64];
|
||||
|
||||
if use_key_a then
|
||||
target = <a href="shared_pseudocode.html#impl-aarch64.AuthIA.3" title="function: bits(64) AuthIA(bits(64) x, bits(64) y, boolean is_combined)">AuthIA</a>(target, modifier, auth_then_branch);
|
||||
else
|
||||
target = <a href="shared_pseudocode.html#impl-aarch64.AuthIB.3" title="function: bits(64) AuthIB(bits(64) x, bits(64) y, boolean is_combined)">AuthIB</a>(target, modifier, auth_then_branch);
|
||||
|
||||
if branch_type == <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}"><ins>BranchType_RET</ins></a><ins> && </ins><a href="shared_pseudocode.html#impl-shared.HaveGCS.0" title="function: boolean HaveGCS()"><ins>HaveGCS</ins></a><ins>() && </ins><a href="shared_pseudocode.html#impl-aarch64.GCSPCREnabled.1" title="function: boolean GCSPCREnabled(bits(2) el)"><ins>GCSPCREnabled</ins></a><ins>(PSTATE.EL) then
|
||||
if !pac then
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRET" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRET</ins></a><ins>;
|
||||
else
|
||||
if use_key_a then
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRETAA" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRETAA</ins></a><ins>;
|
||||
else
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRETAB" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRETAB</ins></a><ins>;
|
||||
target = </ins><a href="shared_pseudocode.html#impl-aarch64.LoadCheckGCSRecord.2" title="function: bits(64) LoadCheckGCSRecord(bits(64) vaddress, GCSInstruction gcsinst_type)"><ins>LoadCheckGCSRecord</ins></a><ins>(target, inst_type);
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.SetCurrentGCSPointer.1" title="function: SetCurrentGCSPointer(bits(64) ptr)"><ins>SetCurrentGCSPointer</ins></a><ins>(</ins><a href="shared_pseudocode.html#impl-aarch64.GetCurrentGCSPointer.0" title="function: bits(64) GetCurrentGCSPointer()"><ins>GetCurrentGCSPointer</ins></a><ins>() + 8);
|
||||
|
||||
if branch_type == </ins><a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a><ins> then
|
||||
if </ins><a href="shared_pseudocode.html#impl-shared.HaveGCS.0" title="function: boolean HaveGCS()"><ins>HaveGCS</ins></a><ins>() && </ins><a href="shared_pseudocode.html#impl-aarch64.GCSPCREnabled.1" title="function: boolean GCSPCREnabled(bits(2) el)"><ins>GCSPCREnabled</ins></a><ins>(PSTATE.EL) then
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.AddGCSRecord.1" title="function: AddGCSRecord(bits(64) vaddress)"><ins>AddGCSRecord</ins></a><ins>(</ins><a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]"><ins>PC</ins></a><ins>[] + 4);</ins><del>then</del>
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[30, 64] = <a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + 4;
|
||||
|
||||
// Value in BTypeNext will be used to set PSTATE.BTYPE
|
||||
case branch_type of
|
||||
when <a href="shared_pseudocode.html#BranchType_INDIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a> // BR, BRAA, BRAB, BRAAZ, BRABZ
|
||||
if InGuardedPage then
|
||||
if n == 16 || n == 17 then
|
||||
BTypeNext = '01';
|
||||
else
|
||||
BTypeNext = '11';
|
||||
else
|
||||
BTypeNext = '01';
|
||||
when <a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a> // BLR, BLRAA, BLRAB, BLRAAZ, BLRABZ
|
||||
BTypeNext = '10';
|
||||
when <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a> // RET, RETAA, RETAB
|
||||
BTypeNext = '00';
|
||||
|
||||
boolean branch_conditional = FALSE;
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchTo.3" title="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(target, branch_type, branch_conditional);</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,42 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BMOPA</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BMOPA</h2><p>Bitwise exclusive NOR population count outer product and accumulate</p><p class="aml">This instruction works with 32-bit element ZA tile. This instruction generates an outer product of the first source SVL<sub>S</sub>×1 vector and the second source 1×SVL<sub>S</sub> vector. Each outer product element is obtained as population count of the bitwise XNOR result of the corresponding 32-bit elements of the first source vector and the second source vector. Each source vector is independently predicated by a corresponding governing predicate. When either source vector element is inactive the corresponding destination tile element remains unmodified. The resulting SVL<sub>S</sub>×SVL<sub>S</sub> product is then destructively added to the destination tile.</p><h3 class="classheading"><a id="iclass_mortlach2"/>SME2<span style="font-size:smaller;"><br/>(FEAT_SME2)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td class="r">0</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="3">Pm</td><td class="lr" colspan="3">Pn</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr">1</td><td class="lr">0</td><td class="lr" colspan="2">ZAda</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="9"/><td colspan="5"/><td colspan="3"/><td colspan="3"/><td colspan="5"/><td class="droppedname">S</td><td/><td/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bmopa_za_pp_zz_32"/><p class="asm-code">BMOPA <a href="#sa_zada" title="ZA tile ZA0-ZA3 (field "ZAda")"><ZAda></a>.S, <a href="#sa_pn" title="First governing scalable predicate register P0-P7 (field "Pn")"><Pn></a>/M, <a href="#sa_pm" title="Second governing scalable predicate register P0-P7 (field "Pm")"><Pm></a>/M, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.S, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.S</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
||||
constant integer esize = 32;
|
||||
integer a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAda);
|
||||
boolean sub_op = FALSE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><ZAda></td><td><a id="sa_zada"/><p class="aml">Is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pn></td><td><a id="sa_pn"/><p class="aml">Is the name of the first governing scalable predicate register P0-P7, encoded in the "Pn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pm></td><td><a id="sa_pm"/><p class="aml">Is the name of the second governing scalable predicate register P0-P7, encoded in the "Pm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckStreamingSVEAndZAEnabled.0" title="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer dim = VL DIV esize;
|
||||
bits(PL) mask1 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[a, PL];
|
||||
bits(PL) mask2 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[b, PL];
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(dim*dim*esize) operand3 = <a href="shared_pseudocode.html#impl-aarch64.ZAtile.read.3" title="accessor: bits(width) ZAtile[integer tile, integer esize, integer width]">ZAtile</a>[da, esize, dim*dim*esize];
|
||||
bits(dim*dim*esize) result;
|
||||
|
||||
for row = 0 to dim-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, row, esize];
|
||||
for col = 0 to dim-1
|
||||
bits(esize) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, col, esize];
|
||||
bits(esize) element3 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, row*dim + col, esize];
|
||||
if (<a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask1, row, esize) &&
|
||||
<a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask2, col, esize)) then
|
||||
integer res = <a href="shared_pseudocode.html#impl-shared.BitCount.1" title="function: integer BitCount(bits(N) x)">BitCount</a>(NOT(element1 EOR element2));
|
||||
if sub_op then res = -res;
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, row*dim + col, esize] = element3 + res;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, row*dim + col, esize] = element3;
|
||||
<a href="shared_pseudocode.html#impl-aarch64.ZAtile.write.3" title="accessor: ZAtile[integer tile, integer esize, integer width] = bits(width) value">ZAtile</a>[da, esize, dim*dim*esize] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate registers contain the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate registers contain the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,42 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BMOPS</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BMOPS</h2><p>Bitwise exclusive NOR population count outer product and subtract</p><p class="aml">This instruction works with 32-bit element ZA tile. This instruction generates an outer product of the first source SVL<sub>S</sub>×1 vector and the second source 1×SVL<sub>S</sub> vector. Each outer product element is obtained as population count of the bitwise XNOR result of the corresponding 32-bit elements of the first source vector and the second source vector. Each source vector is independently predicated by a corresponding governing predicate. When either source vector element is inactive the corresponding destination tile element remains unmodified. The resulting SVL<sub>S</sub>×SVL<sub>S</sub> product is then destructively subtracted from the destination tile.</p><h3 class="classheading"><a id="iclass_mortlach2"/>SME2<span style="font-size:smaller;"><br/>(FEAT_SME2)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td class="r">0</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="3">Pm</td><td class="lr" colspan="3">Pn</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr">1</td><td class="lr">0</td><td class="lr" colspan="2">ZAda</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="9"/><td colspan="5"/><td colspan="3"/><td colspan="3"/><td colspan="5"/><td class="droppedname">S</td><td/><td/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bmops_za_pp_zz_32"/><p class="asm-code">BMOPS <a href="#sa_zada" title="ZA tile ZA0-ZA3 (field "ZAda")"><ZAda></a>.S, <a href="#sa_pn" title="First governing scalable predicate register P0-P7 (field "Pn")"><Pn></a>/M, <a href="#sa_pm" title="Second governing scalable predicate register P0-P7 (field "Pm")"><Pm></a>/M, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.S, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.S</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME2.0" title="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
||||
constant integer esize = 32;
|
||||
integer a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAda);
|
||||
boolean sub_op = TRUE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><ZAda></td><td><a id="sa_zada"/><p class="aml">Is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pn></td><td><a id="sa_pn"/><p class="aml">Is the name of the first governing scalable predicate register P0-P7, encoded in the "Pn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pm></td><td><a id="sa_pm"/><p class="aml">Is the name of the second governing scalable predicate register P0-P7, encoded in the "Pm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckStreamingSVEAndZAEnabled.0" title="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer dim = VL DIV esize;
|
||||
bits(PL) mask1 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[a, PL];
|
||||
bits(PL) mask2 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[b, PL];
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(dim*dim*esize) operand3 = <a href="shared_pseudocode.html#impl-aarch64.ZAtile.read.3" title="accessor: bits(width) ZAtile[integer tile, integer esize, integer width]">ZAtile</a>[da, esize, dim*dim*esize];
|
||||
bits(dim*dim*esize) result;
|
||||
|
||||
for row = 0 to dim-1
|
||||
bits(esize) element1 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, row, esize];
|
||||
for col = 0 to dim-1
|
||||
bits(esize) element2 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, col, esize];
|
||||
bits(esize) element3 = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, row*dim + col, esize];
|
||||
if (<a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask1, row, esize) &&
|
||||
<a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask2, col, esize)) then
|
||||
integer res = <a href="shared_pseudocode.html#impl-shared.BitCount.1" title="function: integer BitCount(bits(N) x)">BitCount</a>(NOT(element1 EOR element2));
|
||||
if sub_op then res = -res;
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, row*dim + col, esize] = element3 + res;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, row*dim + col, esize] = element3;
|
||||
<a href="shared_pseudocode.html#impl-aarch64.ZAtile.write.3" title="accessor: ZAtile[integer tile, integer esize, integer width] = bits(width) value">ZAtile</a>[da, esize, dim*dim*esize] = result;</p></div><h3>Operational information</h3><p class="aml"><ins>If</ins><del>When</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate registers contain the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate registers contain the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,78 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BR -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BR</h2><p class="aml">Branch to Register branches unconditionally to an address in a register, with a hint that this is not a subroutine return.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="5">Rn</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td></tr><tr class="secondrow"><td colspan="7"/><td class="droppedname">Z</td><td/><td class="droppedname" colspan="2">op</td><td colspan="5"/><td colspan="4"/><td class="droppedname">A</td><td class="droppedname">M</td><td colspan="5"/><td class="droppedname" colspan="5">Rm</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="BR_64_branch_reg"/><p class="asm-code">BR <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field "Rn")"><Xn></a></p></div><p class="pseudocode">integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
<a href="shared_pseudocode.html#BranchType" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type;
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
boolean pac = (A == '1');
|
||||
boolean use_key_a = (M == '0');
|
||||
boolean source_is_sp = ((Z == '1') && (m == 31));
|
||||
|
||||
if !pac && m != 0 then
|
||||
UNDEFINED;
|
||||
elsif pac && !<a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
case op of
|
||||
when '00' branch_type = <a href="shared_pseudocode.html#BranchType_INDIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>;
|
||||
when '01' branch_type = <a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a>;
|
||||
when '10' branch_type = <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a>;
|
||||
otherwise UNDEFINED;
|
||||
|
||||
if pac then
|
||||
if Z == '0' && m != 31 then
|
||||
UNDEFINED;
|
||||
|
||||
if branch_type == <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a> then
|
||||
if n != 31 then UNDEFINED;
|
||||
n = 30;
|
||||
source_is_sp = TRUE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn></td><td><a id="sa_xn"/><p class="aml">Is the 64-bit name of the general-purpose register holding the address to be branched to, encoded in the "Rn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#GCSInstruction" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstruction</ins></a> <ins>inst_type;
|
||||
</ins>bits(64) target = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
boolean auth_then_branch = TRUE;
|
||||
|
||||
if pac then
|
||||
bits(64) modifier = if source_is_sp then <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[] else <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[m, 64];
|
||||
|
||||
if use_key_a then
|
||||
target = <a href="shared_pseudocode.html#impl-aarch64.AuthIA.3" title="function: bits(64) AuthIA(bits(64) x, bits(64) y, boolean is_combined)">AuthIA</a>(target, modifier, auth_then_branch);
|
||||
else
|
||||
target = <a href="shared_pseudocode.html#impl-aarch64.AuthIB.3" title="function: bits(64) AuthIB(bits(64) x, bits(64) y, boolean is_combined)">AuthIB</a>(target, modifier, auth_then_branch);
|
||||
|
||||
if branch_type == <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}"><ins>BranchType_RET</ins></a><ins> && </ins><a href="shared_pseudocode.html#impl-shared.HaveGCS.0" title="function: boolean HaveGCS()"><ins>HaveGCS</ins></a><ins>() && </ins><a href="shared_pseudocode.html#impl-aarch64.GCSPCREnabled.1" title="function: boolean GCSPCREnabled(bits(2) el)"><ins>GCSPCREnabled</ins></a><ins>(PSTATE.EL) then
|
||||
if !pac then
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRET" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRET</ins></a><ins>;
|
||||
else
|
||||
if use_key_a then
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRETAA" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRETAA</ins></a><ins>;
|
||||
else
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRETAB" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRETAB</ins></a><ins>;
|
||||
target = </ins><a href="shared_pseudocode.html#impl-aarch64.LoadCheckGCSRecord.2" title="function: bits(64) LoadCheckGCSRecord(bits(64) vaddress, GCSInstruction gcsinst_type)"><ins>LoadCheckGCSRecord</ins></a><ins>(target, inst_type);
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.SetCurrentGCSPointer.1" title="function: SetCurrentGCSPointer(bits(64) ptr)"><ins>SetCurrentGCSPointer</ins></a><ins>(</ins><a href="shared_pseudocode.html#impl-aarch64.GetCurrentGCSPointer.0" title="function: bits(64) GetCurrentGCSPointer()"><ins>GetCurrentGCSPointer</ins></a><ins>() + 8);
|
||||
|
||||
if branch_type == </ins><a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a><ins> then
|
||||
if </ins><a href="shared_pseudocode.html#impl-shared.HaveGCS.0" title="function: boolean HaveGCS()"><ins>HaveGCS</ins></a><ins>() && </ins><a href="shared_pseudocode.html#impl-aarch64.GCSPCREnabled.1" title="function: boolean GCSPCREnabled(bits(2) el)"><ins>GCSPCREnabled</ins></a><ins>(PSTATE.EL) then
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.AddGCSRecord.1" title="function: AddGCSRecord(bits(64) vaddress)"><ins>AddGCSRecord</ins></a><ins>(</ins><a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]"><ins>PC</ins></a><ins>[] + 4);</ins><del>then</del>
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[30, 64] = <a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + 4;
|
||||
|
||||
// Value in BTypeNext will be used to set PSTATE.BTYPE
|
||||
case branch_type of
|
||||
when <a href="shared_pseudocode.html#BranchType_INDIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a> // BR, BRAA, BRAB, BRAAZ, BRABZ
|
||||
if InGuardedPage then
|
||||
if n == 16 || n == 17 then
|
||||
BTypeNext = '01';
|
||||
else
|
||||
BTypeNext = '11';
|
||||
else
|
||||
BTypeNext = '01';
|
||||
when <a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a> // BLR, BLRAA, BLRAB, BLRAAZ, BLRABZ
|
||||
BTypeNext = '10';
|
||||
when <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a> // RET, RETAA, RETAB
|
||||
BTypeNext = '00';
|
||||
|
||||
boolean branch_conditional = FALSE;
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchTo.3" title="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(target, branch_type, branch_conditional);</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,79 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BRAA, BRAAZ, BRAB, BRABZ -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BRAA, BRAAZ, BRAB, BRABZ</h2><p class="aml">Branch to Register, with pointer authentication. This instruction authenticates the address in the general-purpose register that is specified by <Xn>, using a modifier and the specified key, and branches to the authenticated address.</p><p class="aml">The modifier is:</p><ul><li>In the general-purpose register or stack pointer that is specified by <Xm|SP> for <span class="asm-code">BRAA</span> and <span class="asm-code">BRAB</span>.</li><li>The value zero, for <span class="asm-code">BRAAZ</span> and <span class="asm-code">BRABZ</span>.</li></ul><p class="aml">Key A is used for <span class="asm-code">BRAA</span> and <span class="asm-code">BRAAZ</span><ins>.</ins><del>,</del> <ins>Key</ins><del>and key</del> B is used for <span class="asm-code">BRAB</span> and <span class="asm-code">BRABZ</span>.</p><p class="aml">If the authentication passes, the PE continues execution at the target of the branch. <ins>For</ins><del>If</del> <ins>information on behavior if </ins>the authentication fails, <ins>see</ins><del>a Translation fault is generated.</del> <a class="armarm-xref" title="Reference to Armv8 ARM section"><ins>Faulting on pointer authentication</ins></a><ins>.</ins></p><p class="aml">The authenticated address is not written back to the general-purpose register.</p><h3 class="classheading"><a id="iclass_general"/>Integer<span style="font-size:smaller;"><br/>(FEAT_PAuth)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">Z</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">M</td><td class="lr" colspan="5">Rn</td><td class="lr" colspan="5">Rm</td></tr><tr class="secondrow"><td colspan="7"/><td/><td/><td class="droppedname" colspan="2">op</td><td colspan="5"/><td colspan="4"/><td class="droppedname">A</td><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">Key A, zero modifier<span class="bitdiff"> (Z == 0 && M == 0 && Rm == 11111)</span></h4><a id="BRAAZ_64_branch_reg"/><p class="asm-code">BRAAZ <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field "Rn")"><Xn></a></p></div><div class="encoding"><h4 class="encoding">Key A, register modifier<span class="bitdiff"> (Z == 1 && M == 0)</span></h4><a id="BRAA_64P_branch_reg"/><p class="asm-code">BRAA <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field "Rn")"><Xn></a>, <a href="#sa_xm_sp" title="64-bit general-purpose source register or SP holding modifier (field "Rm")"><Xm|SP></a></p></div><div class="encoding"><h4 class="encoding">Key B, zero modifier<span class="bitdiff"> (Z == 0 && M == 1 && Rm == 11111)</span></h4><a id="BRABZ_64_branch_reg"/><p class="asm-code">BRABZ <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field "Rn")"><Xn></a></p></div><div class="encoding"><h4 class="encoding">Key B, register modifier<span class="bitdiff"> (Z == 1 && M == 1)</span></h4><a id="BRAB_64P_branch_reg"/><p class="asm-code">BRAB <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field "Rn")"><Xn></a>, <a href="#sa_xm_sp" title="64-bit general-purpose source register or SP holding modifier (field "Rm")"><Xm|SP></a></p></div><p class="pseudocode">integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
<a href="shared_pseudocode.html#BranchType" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type;
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
boolean pac = (A == '1');
|
||||
boolean use_key_a = (M == '0');
|
||||
boolean source_is_sp = ((Z == '1') && (m == 31));
|
||||
|
||||
if !pac && m != 0 then
|
||||
UNDEFINED;
|
||||
elsif pac && !<a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
case op of
|
||||
when '00' branch_type = <a href="shared_pseudocode.html#BranchType_INDIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>;
|
||||
when '01' branch_type = <a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a>;
|
||||
when '10' branch_type = <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a>;
|
||||
otherwise UNDEFINED;
|
||||
|
||||
if pac then
|
||||
if Z == '0' && m != 31 then
|
||||
UNDEFINED;
|
||||
|
||||
if branch_type == <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a> then
|
||||
if n != 31 then UNDEFINED;
|
||||
n = 30;
|
||||
source_is_sp = TRUE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn></td><td><a id="sa_xn"/><p class="aml">Is the 64-bit name of the general-purpose register holding the address to be branched to, encoded in the "Rn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xm|SP></td><td><a id="sa_xm_sp"/><p class="aml">Is the 64-bit name of the general-purpose source register or stack pointer holding the modifier, encoded in the "Rm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#GCSInstruction" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstruction</ins></a> <ins>inst_type;
|
||||
</ins>bits(64) target = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
boolean auth_then_branch = TRUE;
|
||||
|
||||
if pac then
|
||||
bits(64) modifier = if source_is_sp then <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[] else <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[m, 64];
|
||||
|
||||
if use_key_a then
|
||||
target = <a href="shared_pseudocode.html#impl-aarch64.AuthIA.3" title="function: bits(64) AuthIA(bits(64) x, bits(64) y, boolean is_combined)">AuthIA</a>(target, modifier, auth_then_branch);
|
||||
else
|
||||
target = <a href="shared_pseudocode.html#impl-aarch64.AuthIB.3" title="function: bits(64) AuthIB(bits(64) x, bits(64) y, boolean is_combined)">AuthIB</a>(target, modifier, auth_then_branch);
|
||||
|
||||
if branch_type == <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}"><ins>BranchType_RET</ins></a><ins> && </ins><a href="shared_pseudocode.html#impl-shared.HaveGCS.0" title="function: boolean HaveGCS()"><ins>HaveGCS</ins></a><ins>() && </ins><a href="shared_pseudocode.html#impl-aarch64.GCSPCREnabled.1" title="function: boolean GCSPCREnabled(bits(2) el)"><ins>GCSPCREnabled</ins></a><ins>(PSTATE.EL) then
|
||||
if !pac then
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRET" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRET</ins></a><ins>;
|
||||
else
|
||||
if use_key_a then
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRETAA" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRETAA</ins></a><ins>;
|
||||
else
|
||||
inst_type = </ins><a href="shared_pseudocode.html#GCSInstType_PRETAB" title="enumeration GCSInstruction { GCSInstType_PRET, GCSInstType_POPM, GCSInstType_PRETAA, GCSInstType_PRETAB, GCSInstType_SS1, GCSInstType_SS2, GCSInstType_POPCX, GCSInstType_POPX }"><ins>GCSInstType_PRETAB</ins></a><ins>;
|
||||
target = </ins><a href="shared_pseudocode.html#impl-aarch64.LoadCheckGCSRecord.2" title="function: bits(64) LoadCheckGCSRecord(bits(64) vaddress, GCSInstruction gcsinst_type)"><ins>LoadCheckGCSRecord</ins></a><ins>(target, inst_type);
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.SetCurrentGCSPointer.1" title="function: SetCurrentGCSPointer(bits(64) ptr)"><ins>SetCurrentGCSPointer</ins></a><ins>(</ins><a href="shared_pseudocode.html#impl-aarch64.GetCurrentGCSPointer.0" title="function: bits(64) GetCurrentGCSPointer()"><ins>GetCurrentGCSPointer</ins></a><ins>() + 8);
|
||||
|
||||
if branch_type == </ins><a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a><ins> then
|
||||
if </ins><a href="shared_pseudocode.html#impl-shared.HaveGCS.0" title="function: boolean HaveGCS()"><ins>HaveGCS</ins></a><ins>() && </ins><a href="shared_pseudocode.html#impl-aarch64.GCSPCREnabled.1" title="function: boolean GCSPCREnabled(bits(2) el)"><ins>GCSPCREnabled</ins></a><ins>(PSTATE.EL) then
|
||||
</ins><a href="shared_pseudocode.html#impl-aarch64.AddGCSRecord.1" title="function: AddGCSRecord(bits(64) vaddress)"><ins>AddGCSRecord</ins></a><ins>(</ins><a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]"><ins>PC</ins></a><ins>[] + 4);</ins><del>then</del>
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[30, 64] = <a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + 4;
|
||||
|
||||
// Value in BTypeNext will be used to set PSTATE.BTYPE
|
||||
case branch_type of
|
||||
when <a href="shared_pseudocode.html#BranchType_INDIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a> // BR, BRAA, BRAB, BRAAZ, BRABZ
|
||||
if InGuardedPage then
|
||||
if n == 16 || n == 17 then
|
||||
BTypeNext = '01';
|
||||
else
|
||||
BTypeNext = '11';
|
||||
else
|
||||
BTypeNext = '01';
|
||||
when <a href="shared_pseudocode.html#BranchType_INDCALL" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDCALL</a> // BLR, BLRAA, BLRAB, BLRAAZ, BLRABZ
|
||||
BTypeNext = '10';
|
||||
when <a href="shared_pseudocode.html#BranchType_RET" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_RET</a> // RET, RETAA, RETAB
|
||||
BTypeNext = '00';
|
||||
|
||||
boolean branch_conditional = FALSE;
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchTo.3" title="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(target, branch_type, branch_conditional);</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,22 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BSL1N</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BSL1N</h2><p>Bitwise select with first input inverted</p><p class="aml">Selects bits from the inverted first source vector where the corresponding bit in the third source vector is '1', and from the second source vector where the corresponding bit in the third source vector is '0'. The result is placed destructively in the destination and first source vector. This instruction is unpredicated.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">0</td><td>0</td><td>1</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="lr" colspan="5">Zk</td><td class="lr" colspan="5">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bsl1n_z_zzz_"/><p class="asm-code">BSL1N <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.D, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.D, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D, <a href="#sa_zk" title="Third source scalable vector register (field "Zk")"><Zk></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer k = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zk);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zk></td><td><a id="sa_zk"/><p class="aml">Is the name of the third source scalable vector register, encoded in the "Zk" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[k, VL];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = (NOT(operand1) AND operand3) OR (operand2 AND NOT(operand3));</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,22 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BSL2N</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BSL2N</h2><p>Bitwise select with second input inverted</p><p class="aml">Selects bits from the first source vector where the corresponding bit in the third source vector is '1', and from the inverted second source vector where the corresponding bit in the third source vector is '0'. The result is placed destructively in the destination and first source vector. This instruction is unpredicated.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">0</td><td>0</td><td>1</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="lr" colspan="5">Zk</td><td class="lr" colspan="5">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bsl2n_z_zzz_"/><p class="asm-code">BSL2N <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.D, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.D, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D, <a href="#sa_zk" title="Third source scalable vector register (field "Zk")"><Zk></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer k = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zk);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zk></td><td><a id="sa_zk"/><p class="aml">Is the name of the third source scalable vector register, encoded in the "Zk" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[k, VL];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = (operand1 AND operand3) OR (NOT(operand2) AND NOT(operand3));</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,22 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BSL</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BSL</h2><p>Bitwise select</p><p class="aml">Selects bits from the first source vector where the corresponding bit in the third source vector is '1', and from the second source vector where the corresponding bit in the third source vector is '0'. The result is placed destructively in the destination and first source vector. This instruction is unpredicated.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="5">Zm</td><td class="l">0</td><td>0</td><td>1</td><td>1</td><td class="r">1</td><td class="lr">1</td><td class="lr" colspan="5">Zk</td><td class="lr" colspan="5">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="bsl_z_zzz_"/><p class="asm-code">BSL <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.D, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.D, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D, <a href="#sa_zk" title="Third source scalable vector register (field "Zk")"><Zk></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer k = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zk);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zk></td><td><a id="sa_zk"/><p class="aml">Is the name of the third source scalable vector register, encoded in the "Zk" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[k, VL];
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = (operand1 AND operand3) OR (operand2 AND NOT(operand3));</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,108 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>BTI -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BTI</h2><p class="aml">Branch Target Identification. A <span class="asm-code">BTI</span> instruction is used to guard against the execution of instructions which are not the intended target of a branch.</p><p class="aml">Outside of a guarded memory region, a <span class="asm-code">BTI</span> instruction executes as a <span class="asm-code">NOP</span>. Within a guarded memory region while <a class="armarm-xref" title="Reference to Armv8 ARM section">PSTATE</a>.BTYPE != 0b00, a <span class="asm-code">BTI</span> instruction compatible with the current value of PSTATE.BTYPE will not generate a Branch Target Exception and will allow execution of subsequent instructions within the memory region.</p><p class="aml">The operand <targets> passed to a <span class="asm-code">BTI</span> instruction determines the values of <a class="armarm-xref" title="Reference to Armv8 ARM section">PSTATE</a>.BTYPE which the <span class="asm-code">BTI</span> instruction is compatible with.</p><div class="note"><hr class="note"/><h4>Note</h4><p class="aml">Within a guarded memory region, when <a class="armarm-xref" title="Reference to Armv8 ARM section">PSTATE</a>.BTYPE != 0b00, all instructions will generate a Branch Target Exception, other than <span class="asm-code">BRK</span>, <span class="asm-code">BTI</span>, <span class="asm-code">HLT</span>, <span class="asm-code">PACIASP</span>, and <span class="asm-code">PACIBSP</span>, which might not. See the individual instructions for more information.</p><hr class="note"/></div><h3 class="classheading"><a id="iclass_system"/>System<span style="font-size:smaller;"><br/>(FEAT_BTI)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>1</td><td class="r">0</td><td class="l">0</td><td>1</td><td>0</td><td class="r">0</td><td class="l">x</td><td>x</td><td class="r">0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td></tr><tr class="secondrow"><td colspan="10"/><td/><td colspan="2"/><td colspan="3"/><td colspan="4"/><td class="droppedname" colspan="4">CRm</td><td class="droppedname" colspan="3">op2</td><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="BTI_HB_hints"/><p class="asm-code">BTI {<a href="#sa_targets" title="Type of indirection (field "op2<2:1>") [(omitted),c,j,jc]"><targets></a>}</p></div><p class="pseudocode"><a href="shared_pseudocode.html#SystemHintOp" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp</a> op;
|
||||
|
||||
case CRm:op2 of
|
||||
when '0000 000' op = <a href="shared_pseudocode.html#SystemHintOp_NOP" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_NOP</a>;
|
||||
when '0000 001' op = <a href="shared_pseudocode.html#SystemHintOp_YIELD" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_YIELD</a>;
|
||||
when '0000 010' op = <a href="shared_pseudocode.html#SystemHintOp_WFE" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFE</a>;
|
||||
when '0000 011' op = <a href="shared_pseudocode.html#SystemHintOp_WFI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFI</a>;
|
||||
when '0000 100' op = <a href="shared_pseudocode.html#SystemHintOp_SEV" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEV</a>;
|
||||
when '0000 101' op = <a href="shared_pseudocode.html#SystemHintOp_SEVL" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEVL</a>;
|
||||
when '0000 110'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveDGHExt.0" title="function: boolean HaveDGHExt()">HaveDGHExt</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_DGH" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_DGH</a>;
|
||||
when '0000 111' SEE "XPACLRI";
|
||||
when '0001 xxx'
|
||||
case op2 of
|
||||
when '000' SEE "PACIA1716";
|
||||
when '010' SEE "PACIB1716";
|
||||
when '100' SEE "AUTIA1716";
|
||||
when '110' SEE "AUTIB1716";
|
||||
otherwise <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
when '0010 000'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveRASExt.0" title="function: boolean HaveRASExt()">HaveRASExt</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_ESB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_ESB</a>;
|
||||
when '0010 001'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveStatisticalProfiling.0" title="function: boolean HaveStatisticalProfiling()">HaveStatisticalProfiling</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_PSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_PSB</a>;
|
||||
when '0010 010'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveSelfHostedTrace.0" title="function: boolean HaveSelfHostedTrace()">HaveSelfHostedTrace</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_TSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_TSB</a>;
|
||||
<ins> when '0010 011'
|
||||
if !IsFeatureImplemented(FEAT_GCS) then</ins><del> when '0010 100'
|
||||
op =</del> <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()"><ins>EndOfInstruction</ins></a><ins>(); // Instruction executes as NOP
|
||||
op = </ins><a href="shared_pseudocode.html#SystemHintOp_GCSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }"><ins>SystemHintOp_GCSB</ins></a><ins>;
|
||||
when '0010 100'
|
||||
op = </ins><a href="shared_pseudocode.html#SystemHintOp_CSDB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CSDB</a>;
|
||||
when '0010 110'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveFeatCLRBHB.0" title="function: boolean HaveFeatCLRBHB()">HaveFeatCLRBHB</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_CLRBHB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CLRBHB</a>;
|
||||
when '0011 xxx'
|
||||
case op2 of
|
||||
when '000' SEE "PACIAZ";
|
||||
when '001' SEE "PACIASP";
|
||||
when '010' SEE "PACIBZ";
|
||||
when '011' SEE "PACIBSP";
|
||||
when '100' SEE "AUTIAZ";
|
||||
when '101' SEE "AUTIASP";
|
||||
when '110' SEE "AUTIBZ";
|
||||
when '111' SEE "AUTIBSP";
|
||||
when '0100 xx0'
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_BTI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_BTI</a>;
|
||||
// Check branch target compatibility between BTI instruction and PSTATE.BTYPE
|
||||
<a href="shared_pseudocode.html#impl-aarch64.SetBTypeCompatible.1" title="function: SetBTypeCompatible(boolean x)">SetBTypeCompatible</a>(<a href="shared_pseudocode.html#impl-aarch64.BTypeCompatible_BTI.1" title="function: boolean BTypeCompatible_BTI(bits(2) hintcode)">BTypeCompatible_BTI</a><ins>(op2<2:1>));
|
||||
when '0101 000'
|
||||
if !IsFeatureImplemented(FEAT_CHK) then </ins><a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()"><ins>EndOfInstruction</ins></a><ins>(); // Instruction executes as NOP
|
||||
op = </ins><a href="shared_pseudocode.html#SystemHintOp_CHKFEAT" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }"><ins>SystemHintOp_CHKFEAT</ins></a><ins>;
|
||||
</ins><del>(op2<2:1>));
|
||||
</del> otherwise <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><targets></td><td><a id="sa_targets"/><p>Is the type of indirection,
|
||||
encoded in
|
||||
<q>op2<2:1></q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">op2<2:1></th><th class="symbol"><targets></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">(omitted)</td></tr><tr><td class="bitfield">01</td><td class="symbol">c</td></tr><tr><td class="bitfield">10</td><td class="symbol">j</td></tr><tr><td class="bitfield">11</td><td class="symbol">jc</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">case op of
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_YIELD" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_YIELD</a><a href="shared_pseudocode.html#impl-shared.Hint_Yield.0" title="function: Hint_Yield()">Hint_Yield</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_DGH" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_DGH</a><a href="shared_pseudocode.html#impl-shared.Hint_DGH.0" title="function: Hint_DGH()">Hint_DGH</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_WFE" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFE</a>
|
||||
integer localtimeout = 1 << 64; // No local timeout event is generated
|
||||
<a href="shared_pseudocode.html#impl-shared.Hint_WFE.2" title="function: Hint_WFE(integer localtimeout, WFxType wfxtype)">Hint_WFE</a>(localtimeout, <a href="shared_pseudocode.html#WFxType_WFE" title="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFE</a>);
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_WFI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFI</a>
|
||||
integer localtimeout = 1 << 64; // No local timeout event is generated
|
||||
<a href="shared_pseudocode.html#impl-shared.Hint_WFI.2" title="function: Hint_WFI(integer localtimeout, WFxType wfxtype)">Hint_WFI</a>(localtimeout, <a href="shared_pseudocode.html#WFxType_WFI" title="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFI</a>);
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_SEV" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEV</a><a href="shared_pseudocode.html#impl-shared.SendEvent.0" title="function: SendEvent()">SendEvent</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_SEVL" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEVL</a><a href="shared_pseudocode.html#impl-shared.SendEventLocal.0" title="function: SendEventLocal()">SendEventLocal</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_ESB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_ESB</a>
|
||||
if <a href="shared_pseudocode.html#impl-shared.HaveTME.0" title="function: boolean HaveTME()">HaveTME</a>() && TSTATE.depth > 0 then
|
||||
<a href="shared_pseudocode.html#impl-aarch64.FailTransaction.2" title="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(<a href="shared_pseudocode.html#TMFailure_ERR" title="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_ERR</a>, FALSE);
|
||||
<a href="shared_pseudocode.html#impl-shared.SynchronizeErrors.0" title="function: SynchronizeErrors()">SynchronizeErrors</a>();
|
||||
<a href="shared_pseudocode.html#AArch64.ESBOperation.0" title="function: AArch64.ESBOperation()">AArch64.ESBOperation</a>();
|
||||
if PSTATE.EL IN {<a href="shared_pseudocode.html#EL0" title="constant bits(2) EL0 = '00'">EL0</a>, <a href="shared_pseudocode.html#EL1" title="constant bits(2) EL1 = '01'">EL1</a>} && <a href="shared_pseudocode.html#impl-shared.EL2Enabled.0" title="function: boolean EL2Enabled()">EL2Enabled</a>() then <a href="shared_pseudocode.html#AArch64.vESBOperation.0" title="function: AArch64.vESBOperation()">AArch64.vESBOperation</a>();
|
||||
<a href="shared_pseudocode.html#impl-shared.TakeUnmaskedSErrorInterrupts.0" title="function: TakeUnmaskedSErrorInterrupts()">TakeUnmaskedSErrorInterrupts</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_PSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_PSB</a><a href="shared_pseudocode.html#impl-aarch64.ProfilingSynchronizationBarrier.0" title="function: ProfilingSynchronizationBarrier()">ProfilingSynchronizationBarrier</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_TSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_TSB</a><a href="shared_pseudocode.html#impl-shared.TraceSynchronizationBarrier.0" title="function: TraceSynchronizationBarrier()">TraceSynchronizationBarrier</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_GCSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }"><ins>SystemHintOp_GCSB</ins></a><a href="shared_pseudocode.html#impl-aarch64.GCSSynchronizationBarrier.0" title="function: GCSSynchronizationBarrier()"><ins>GCSSynchronizationBarrier</ins></a><ins>();
|
||||
|
||||
when </ins><a href="shared_pseudocode.html#SystemHintOp_CHKFEAT" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }"><ins>SystemHintOp_CHKFEAT</ins></a><a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value"><ins>X</ins></a><ins>[16, 64] = AArch64.ChkFeat(X[16, 64]);
|
||||
|
||||
when </ins><a href="shared_pseudocode.html#SystemHintOp_CSDB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CSDB</a><a href="shared_pseudocode.html#impl-shared.ConsumptionOfSpeculativeDataBarrier.0" title="function: ConsumptionOfSpeculativeDataBarrier()">ConsumptionOfSpeculativeDataBarrier</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_CLRBHB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CLRBHB</a><a href="shared_pseudocode.html#impl-shared.Hint_CLRBHB.0" title="function: Hint_CLRBHB()">Hint_CLRBHB</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_BTI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_BTI</a><a href="shared_pseudocode.html#impl-aarch64.SetBTypeNext.1" title="function: SetBTypeNext(bits(2) x)">SetBTypeNext</a>('00');
|
||||
|
||||
otherwise // do nothing</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,47 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CADD</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CADD</h2><p>Complex integer add with rotate</p><p class="aml">Add the real and imaginary components of the integral complex numbers from the first source vector to the complex numbers from the second source vector which have first been rotated by 90 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation, equivalent to multiplying the complex numbers in the second source vector by ±<span class="arm-defined-word">j</span> beforehand. Destructively place the results in the corresponding elements of the first source vector. This instruction is unpredicated.</p><p class="aml">Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="l">1</td><td>1</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">rot</td><td class="lr" colspan="5">Zm</td><td class="lr" colspan="5">Zdn</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cadd_z_zz_"/><p class="asm-code">CADD <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zdn" title="First source and destination scalable vector register (field "Zdn")"><Zdn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_const" title="Const specifier (field "rot") [#90,#270]"><const></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer dn = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
boolean sub_i = (rot == '0');
|
||||
boolean sub_r = (rot == '1');</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zdn></td><td><a id="sa_zdn"/><p class="aml">Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><const></td><td><a id="sa_const"/><p>Is the const specifier,
|
||||
encoded in
|
||||
<q>rot</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">rot</th><th class="symbol"><const></th></tr></thead><tbody><tr><td class="bitfield">0</td><td class="symbol">#90</td></tr><tr><td class="bitfield">1</td><td class="symbol">#270</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer pairs = VL DIV (2 * esize);
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for p = 0 to pairs-1
|
||||
integer acc_r = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * p + 0, esize]);
|
||||
integer acc_i = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * p + 1, esize]);
|
||||
integer elt2_r = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * p + 0, esize]);
|
||||
integer elt2_i = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * p + 1, esize]);
|
||||
if sub_i then
|
||||
acc_r = acc_r - elt2_i;
|
||||
acc_i = acc_i + elt2_r;
|
||||
if sub_r then
|
||||
acc_r = acc_r + elt2_i;
|
||||
acc_i = acc_i - elt2_r;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 0, esize] = acc_r<esize-1:0>;
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 1, esize] = acc_i<esize-1:0>;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,38 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CASH, CASAH, CASALH, CASLH -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CASH, CASAH, CASALH, CASLH</h2><p class="aml">Compare and Swap halfword in memory reads a 16-bit halfword from memory, and compares it against the value held in a first register. If the comparison is equal, the value in a second register is written to memory. If the write is performed, the read and write occur atomically such that no other modification of the memory location can take place between the read and write.</p><ul><li><span class="asm-code">CASAH</span> and <span class="asm-code">CASALH</span> load from memory with acquire semantics.</li><li><span class="asm-code">CASLH</span> and <span class="asm-code">CASALH</span> store to memory with release semantics.</li><li><span class="asm-code"><ins>CASH</ins><del>CAS</del></span> has neither acquire nor release semantics.</li></ul><p class="aml">For more information about memory ordering semantics<ins>,</ins> see <a class="armarm-xref" title="Reference to Armv8 ARM section">Load-Acquire, Store-Release</a>.</p><p class="aml">For information about memory accesses<ins>,</ins> see <a class="armarm-xref" title="Reference to Armv8 ARM section">Load/Store addressing modes</a>.</p><p class="aml">The architecture permits that the data read clears any exclusive monitors associated with that location, even if the compare subsequently fails.</p><p class="aml">If the instruction generates a synchronous Data Abort, the register which is compared and loaded, that is <Ws>, is restored to the values held in the register before the instruction was executed.</p><h3 class="classheading"><a id="iclass_base_register"/>No offset<span style="font-size:smaller;"><br/>(FEAT_LSE)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td class="r">1</td><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">L</td><td class="lr">1</td><td class="lr" colspan="5">Rs</td><td class="lr">o0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td class="lr" colspan="5">Rn</td><td class="lr" colspan="5">Rt</td></tr><tr class="secondrow"><td class="droppedname" colspan="2">size</td><td colspan="7"/><td/><td/><td colspan="5"/><td/><td colspan="5"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">CASAH<span class="bitdiff"> (L == 1 && o0 == 0)</span></h4><a id="CASAH_C32_comswap"/><p class="asm-code">CASAH <a href="#sa_ws" title="32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a>, <a href="#sa_wt" title="32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a>{,#0}]</p></div><div class="encoding"><h4 class="encoding">CASALH<span class="bitdiff"> (L == 1 && o0 == 1)</span></h4><a id="CASALH_C32_comswap"/><p class="asm-code">CASALH <a href="#sa_ws" title="32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a>, <a href="#sa_wt" title="32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a>{,#0}]</p></div><div class="encoding"><h4 class="encoding">CASH<span class="bitdiff"> (L == 0 && o0 == 0)</span></h4><a id="CASH_C32_comswap"/><p class="asm-code">CASH <a href="#sa_ws" title="32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a>, <a href="#sa_wt" title="32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a>{,#0}]</p></div><div class="encoding"><h4 class="encoding">CASLH<span class="bitdiff"> (L == 0 && o0 == 1)</span></h4><a id="CASLH_C32_comswap"/><p class="asm-code">CASLH <a href="#sa_ws" title="32-bit general-purpose register to be compared and loaded (field "Rs")"><Ws></a>, <a href="#sa_wt" title="32-bit general-purpose register to be conditionally stored (field "Rt")"><Wt></a>, [<a href="#sa_xn_sp" title="64-bit general-purpose base register or SP (field "Rn")"><Xn|SP></a>{,#0}]</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-shared.HaveAtomicExt.0" title="function: boolean HaveAtomicExt()">HaveAtomicExt</a>() then UNDEFINED;
|
||||
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer t = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rt);
|
||||
integer s = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rs);
|
||||
|
||||
integer datasize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer regsize = if datasize == 64 then 64 else 32;
|
||||
boolean acquire = L == '1';
|
||||
boolean release = o0 == '1';
|
||||
boolean tagchecked = n != 31;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Ws></td><td><a id="sa_ws"/><p class="aml">Is the 32-bit name of the general-purpose register to be compared and loaded, encoded in the "Rs" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Wt></td><td><a id="sa_wt"/><p class="aml">Is the 32-bit name of the general-purpose register to be conditionally stored, encoded in the "Rt" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xn|SP></td><td><a id="sa_xn_sp"/><p class="aml">Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">bits(64) address;
|
||||
bits(datasize) comparevalue;
|
||||
bits(datasize) newvalue;
|
||||
bits(datasize) data;
|
||||
|
||||
<a href="shared_pseudocode.html#AccessDescriptor" title="type AccessDescriptor is ( AccessType acctype, bits(2) el, SecurityState ss, boolean acqsc, boolean acqpc, boolean relsc, boolean limitedordered, boolean exclusive, boolean atomicop, MemAtomicOp modop, boolean nontemporal, boolean read, boolean write, CacheOp cacheop, CacheOpScope opscope, CacheType cachetype, boolean pan, boolean transactional, boolean nonfault, boolean firstfault, boolean first, boolean contiguous, boolean streamingsve, boolean ls64, boolean mops, boolean rcw, boolean rcws, boolean toplevel, VARange varange, boolean a32lsmd, boolean tagchecked, boolean tagaccess, MPAMinfo mpam )">AccessDescriptor</a> accdesc = <a href="shared_pseudocode.html#impl-shared.CreateAccDescAtomicOp.4" title="function: AccessDescriptor CreateAccDescAtomicOp(MemAtomicOp modop, boolean acquire, boolean release, boolean tagchecked)">CreateAccDescAtomicOp</a>(<a href="shared_pseudocode.html#MemAtomicOp_CAS" title="enumeration MemAtomicOp { MemAtomicOp_GCSSS1, MemAtomicOp_ADD, MemAtomicOp_BIC, MemAtomicOp_EOR, MemAtomicOp_ORR, MemAtomicOp_SMAX, MemAtomicOp_SMIN, MemAtomicOp_UMAX, MemAtomicOp_UMIN, MemAtomicOp_SWP, MemAtomicOp_CAS }">MemAtomicOp_CAS</a>, acquire, release, tagchecked);
|
||||
|
||||
comparevalue = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[s, datasize];
|
||||
newvalue = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[t, datasize];
|
||||
|
||||
if n == 31 then
|
||||
<a href="shared_pseudocode.html#impl-aarch64.CheckSPAlignment.0" title="function: CheckSPAlignment()">CheckSPAlignment</a>();
|
||||
address = <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[];
|
||||
else
|
||||
address = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
|
||||
data = <a href="shared_pseudocode.html#impl-aarch64.MemAtomic.4" title="function: bits(size) MemAtomic(bits(64) address, bits(size) cmpoperand, bits(size) operand, AccessDescriptor accdesc_in)">MemAtomic</a>(address, comparevalue, newvalue, accdesc);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[s, regsize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(data, regsize);</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
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|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CBNZ -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CBNZ</h2><p class="aml">Compare and Branch on Nonzero compares the value in a register with zero, and conditionally branches to a label at a PC-relative offset if the comparison is not equal. It provides a hint that this is not a subroutine call or return. This instruction does not affect the condition flags.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">sf</td><td class="l">0</td><td>1</td><td>1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr">1</td><td class="lr" colspan="19">imm19</td><td class="lr" colspan="5">Rt</td></tr><tr class="secondrow"><td/><td colspan="6"/><td class="droppedname">op</td><td colspan="19"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">32-bit<span class="bitdiff"> (sf == 0)</span></h4><a id="CBNZ_32_compbranch"/><p class="asm-code">CBNZ <a href="#sa_wt" title="32-bit general-purpose register to be tested (field "Rt")"><Wt></a>, <a href="#sa_label" title="Label to be conditionally branched to (field imm19)"><label></a></p></div><div class="encoding"><h4 class="encoding">64-bit<span class="bitdiff"> (sf == 1)</span></h4><a id="CBNZ_64_compbranch"/><p class="asm-code">CBNZ <a href="#sa_xt" title="64-bit general-purpose register to be tested (field "Rt")"><Xt></a>, <a href="#sa_label" title="Label to be conditionally branched to (field imm19)"><label></a></p></div><p class="pseudocode">integer t = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rt);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean iszero = (op == '0');
|
||||
bits(64) offset = <a href="shared_pseudocode.html#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm19:'00', 64);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Wt></td><td><a id="sa_wt"/><p class="aml">Is the 32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xt></td><td><a id="sa_xt"/><p class="aml">Is the 64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><label></td><td><a id="sa_label"/><p class="aml">Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">bits(datasize) operand1 = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[t, datasize];
|
||||
boolean branch_conditional = TRUE;
|
||||
if <a href="shared_pseudocode.html#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(operand1) == iszero then
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchTo.3" title="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + offset, <a href="shared_pseudocode.html#BranchType_DIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a><ins>, branch_conditional);
|
||||
else</ins><del>, branch_conditional);</del>
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchNotTaken.2" title="function: BranchNotTaken(BranchType branchtype, boolean branch_conditional)"><ins>BranchNotTaken</ins></a><ins>(</ins><a href="shared_pseudocode.html#BranchType_DIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}"><ins>BranchType_DIR</ins></a><ins>, branch_conditional);</ins></p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,17 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CBZ -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CBZ</h2><p class="aml">Compare and Branch on Zero compares the value in a register with zero, and conditionally branches to a label at a PC-relative offset if the comparison is equal. It provides a hint that this is not a subroutine call or return. This instruction does not affect condition flags.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr">sf</td><td class="l">0</td><td>1</td><td>1</td><td>0</td><td>1</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="19">imm19</td><td class="lr" colspan="5">Rt</td></tr><tr class="secondrow"><td/><td colspan="6"/><td class="droppedname">op</td><td colspan="19"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">32-bit<span class="bitdiff"> (sf == 0)</span></h4><a id="CBZ_32_compbranch"/><p class="asm-code">CBZ <a href="#sa_wt" title="32-bit general-purpose register to be tested (field "Rt")"><Wt></a>, <a href="#sa_label" title="Label to be conditionally branched to (field imm19)"><label></a></p></div><div class="encoding"><h4 class="encoding">64-bit<span class="bitdiff"> (sf == 1)</span></h4><a id="CBZ_64_compbranch"/><p class="asm-code">CBZ <a href="#sa_xt" title="64-bit general-purpose register to be tested (field "Rt")"><Xt></a>, <a href="#sa_label" title="Label to be conditionally branched to (field imm19)"><label></a></p></div><p class="pseudocode">integer t = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rt);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean iszero = (op == '0');
|
||||
bits(64) offset = <a href="shared_pseudocode.html#impl-shared.SignExtend.2" title="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm19:'00', 64);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Wt></td><td><a id="sa_wt"/><p class="aml">Is the 32-bit name of the general-purpose register to be tested, encoded in the "Rt" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xt></td><td><a id="sa_xt"/><p class="aml">Is the 64-bit name of the general-purpose register to be tested, encoded in the "Rt" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><label></td><td><a id="sa_label"/><p class="aml">Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">bits(datasize) operand1 = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[t, datasize];
|
||||
boolean branch_conditional = TRUE;
|
||||
if <a href="shared_pseudocode.html#impl-shared.IsZero.1" title="function: boolean IsZero(bits(N) x)">IsZero</a>(operand1) == iszero then
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchTo.3" title="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a href="shared_pseudocode.html#impl-aarch64.PC.read.0" title="accessor: bits(64) PC[]">PC</a>[] + offset, <a href="shared_pseudocode.html#BranchType_DIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a><ins>, branch_conditional);
|
||||
else</ins><del>, branch_conditional);</del>
|
||||
<a href="shared_pseudocode.html#impl-shared.BranchNotTaken.2" title="function: BranchNotTaken(BranchType branchtype, boolean branch_conditional)"><ins>BranchNotTaken</ins></a><ins>(</ins><a href="shared_pseudocode.html#BranchType_DIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}"><ins>BranchType_DIR</ins></a><ins>, branch_conditional);</ins></p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,58 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CDOT (vectors)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CDOT (vectors)</h2><p>Complex integer dot product</p><p class="aml">The complex integer dot product instructions delimit the source vectors into pairs of 8-bit or 16-bit signed integer complex numbers. Within each pair, the complex numbers in the first source vector are multiplied by the corresponding complex numbers in the second source vector and the resulting wide real or wide imaginary part of the product is accumulated into a 32-bit or 64-bit destination vector element which overlaps all four of the elements that comprise a pair of complex number values in the first source vector.</p><p class="aml">As a result each instruction implicitly deinterleaves the real and imaginary components of their complex number inputs, so that the destination vector accumulates 4×wide real sums or 4×wide imaginary sums.</p><p class="aml">The complex numbers in the second source vector are rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation, by performing the following transformations prior to the dot product operations:</p><ul><li>
|
||||
If the rotation is #0, the imaginary parts of the complex numbers in the second source vector are negated. The destination vector therefore accumulates the real parts of a complex dot product.
|
||||
</li><li>
|
||||
If the rotation is #90, the real and imaginary parts of the complex numbers the second source vector are swapped. The destination vector therefore accumulates the imaginary parts of a complex dot product.
|
||||
</li><li>
|
||||
If the rotation is #180, there is no transformation. The destination vector therefore accumulates the real parts of a complex conjugate dot product.
|
||||
</li><li>
|
||||
If the rotation is #270, the real parts of the complex numbers in the second source vector are negated and then swapped with the imaginary parts. The destination vector therefore accumulates the imaginary parts of a complex conjugate dot product.
|
||||
</li></ul><p class="aml"/><p class="aml">Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="l">0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">rot</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zda</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cdot_z_zzz_"/><p class="asm-code">CDOT <a href="#sa_zda" title="Third source and destination scalable vector register (field "Zda")"><Zda></a>.<a href="#sa_t" title="Size specifier (field "size<0>") [D,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_tb" title="Size specifier (field "size<0>") [B,H]"><Tb></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_tb" title="Size specifier (field "size<0>") [B,H]"><Tb></a>, <a href="#sa_const" title="Const specifier (field "rot") [#0,#90,#180,#270]"><const></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size IN {'0x'} then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zda);
|
||||
integer sel_a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(rot<0>);
|
||||
integer sel_b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(NOT(rot<0>));
|
||||
boolean sub_i = (rot<0> == rot<1>);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zda></td><td><a id="sa_zda"/><p class="aml">Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size<0></q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size<0></th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">0</td><td class="symbol">S</td></tr><tr><td class="bitfield">1</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Tb></td><td><a id="sa_tb"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size<0></q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size<0></th><th class="symbol"><Tb></th></tr></thead><tbody><tr><td class="bitfield">0</td><td class="symbol">B</td></tr><tr><td class="bitfield">1</td><td class="symbol">H</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><const></td><td><a id="sa_const"/><p>Is the const specifier,
|
||||
encoded in
|
||||
<q>rot</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">rot</th><th class="symbol"><const></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">#0</td></tr><tr><td class="bitfield">01</td><td class="symbol">#90</td></tr><tr><td class="bitfield">10</td><td class="symbol">#180</td></tr><tr><td class="bitfield">11</td><td class="symbol">#270</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) res = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize];
|
||||
for i = 0 to 1
|
||||
integer elt1_r = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + 2 * i + 0, esize DIV 4]);
|
||||
integer elt1_i = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + 2 * i + 1, esize DIV 4]);
|
||||
integer elt2_a = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * e + 2 * i + sel_a, esize DIV 4]);
|
||||
integer elt2_b = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * e + 2 * i + sel_b, esize DIV 4]);
|
||||
if sub_i then
|
||||
<ins> res = (res + (elt1_r * elt2_a)) - (elt1_i * elt2_b);
|
||||
</ins><del> res = res + (elt1_r * elt2_a) - (elt1_i * elt2_b);
|
||||
</del> else
|
||||
res = res + (elt1_r * elt2_a) + (elt1_i * elt2_b);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = res;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</p></div><h3>Operational information</h3><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,67 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CDOT (indexed)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CDOT (indexed)</h2><p>Complex integer dot product (indexed)</p><p class="aml">The complex integer dot product instructions delimit the source vectors into pairs of 8-bit or 16-bit signed integer complex numbers. Within each pair, the complex numbers in the first source vector are multiplied by the corresponding complex numbers in the second source vector and the resulting wide real or wide imaginary part of the product is accumulated into a 32-bit or 64-bit destination vector element which overlaps all four of the elements that comprise a pair of complex number values in the first source vector.</p><p class="aml">As a result each instruction implicitly deinterleaves the real and imaginary components of their complex number inputs, so that the destination vector accumulates 4×wide real sums or 4×wide imaginary sums.</p><p class="aml">The complex numbers in the second source vector are rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation, by performing the following transformations prior to the dot product operations:</p><ul><li>
|
||||
If the rotation is #0, the imaginary parts of the complex numbers in the second source vector are negated. The destination vector therefore accumulates the real parts of a complex dot product.
|
||||
</li><li>
|
||||
If the rotation is #90, the real and imaginary parts of the complex numbers the second source vector are swapped. The destination vector therefore accumulates the imaginary parts of a complex dot product.
|
||||
</li><li>
|
||||
If the rotation is #180, there is no transformation. The destination vector therefore accumulates the real parts of a complex conjugate dot product.
|
||||
</li><li>
|
||||
If the rotation is #270, the real parts of the complex numbers in the second source vector are negated and then swapped with the imaginary parts. The destination vector therefore accumulates the imaginary parts of a complex conjugate dot product.
|
||||
</li></ul><p class="aml"/><p class="aml">The indexed form of these instructions select a single pair of complex numbers within each 128-bit segment of the second source vector as the multiplier for all pairs of complex numbers within the corresponding 128-bit segment of the first source vector. The complex number pairs within the second source vector are specified using an immediate index which selects the same complex number pair position within each 128-bit vector segment. The index range is from 0 to one less than the number of complex number pairs per 128-bit segment, encoded in 1 or 2 bits depending on the size of the complex number pair.</p><p class="aml">Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.</p><p class="desc">
|
||||
It has encodings from 2 classes:
|
||||
<a href="#iclass_of_words">32-bit</a>
|
||||
and
|
||||
<a href="#iclass_of_doublewords">64-bit</a></p><h3 class="classheading"><a id="iclass_of_words"/>32-bit</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="2">i2</td><td class="lr" colspan="3">Zm</td><td class="l">0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">rot</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zda</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td/><td colspan="2"/><td colspan="3"/><td colspan="4"/><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cdot_z_zzzi_s"/><p class="asm-code">CDOT <a href="#sa_zda" title="Third source and destination scalable vector register (field "Zda")"><Zda></a>.S, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.B, <a href="#sa_zm_1" title="Second source scalable vector register Z0-Z7 (field "Zm")"><Zm></a>.B[<a href="#sa_imm_1" title="Immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment [0-3] (field "i2")"><imm></a>], <a href="#sa_const" title="Const specifier (field "rot") [#0,#90,#180,#270]"><const></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 32;
|
||||
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(i2);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zda);
|
||||
integer sel_a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(rot<0>);
|
||||
integer sel_b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(NOT(rot<0>));
|
||||
boolean sub_i = (rot<0> == rot<1>);</p><h3 class="classheading"><a id="iclass_of_doublewords"/>64-bit</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr">1</td><td class="lr">i1</td><td class="lr" colspan="4">Zm</td><td class="l">0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">rot</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zda</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td/><td/><td colspan="4"/><td colspan="4"/><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cdot_z_zzzi_d"/><p class="asm-code">CDOT <a href="#sa_zda" title="Third source and destination scalable vector register (field "Zda")"><Zda></a>.D, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.H, <a href="#sa_zm" title="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a>.H[<a href="#sa_imm" title="Immediate index of a 64-bit group of four 16-bit values within each 128-bit vector segment [0-1] (field "i1")"><imm></a>], <a href="#sa_const" title="Const specifier (field "rot") [#0,#90,#180,#270]"><const></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 64;
|
||||
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(i1);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zda);
|
||||
integer sel_a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(rot<0>);
|
||||
integer sel_b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(NOT(rot<0>));
|
||||
boolean sub_i = (rot<0> == rot<1>);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zda></td><td><a id="sa_zda"/><p class="aml">Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm_1"/><p class="aml">For the 32-bit variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.</p></td></tr><tr><td/><td><a id="sa_zm"/><p class="aml">For the 64-bit variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><imm></td><td><a id="sa_imm_1"/><p class="aml">For the 32-bit variant: is the immediate index of a 32-bit group of four 8-bit values within each 128-bit vector segment, in the range 0 to 3, encoded in the "i2" field.</p></td></tr><tr><td/><td><a id="sa_imm"/><p class="aml">For the 64-bit variant: is the immediate index of a 64-bit group of four 16-bit values within each 128-bit vector segment, in the range 0 to 1, encoded in the "i1" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><const></td><td><a id="sa_const"/><p>Is the const specifier,
|
||||
encoded in
|
||||
<q>rot</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">rot</th><th class="symbol"><const></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">#0</td></tr><tr><td class="bitfield">01</td><td class="symbol">#90</td></tr><tr><td class="bitfield">10</td><td class="symbol">#180</td></tr><tr><td class="bitfield">11</td><td class="symbol">#270</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
constant integer eltspersegment = 128 DIV esize;
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
integer segmentbase = e - (e MOD eltspersegment);
|
||||
integer s = segmentbase + index;
|
||||
bits(esize) res = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, esize];
|
||||
for i = 0 to 1
|
||||
integer elt1_r = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + 2 * i + 0, esize DIV 4]);
|
||||
integer elt1_i = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 4 * e + 2 * i + 1, esize DIV 4]);
|
||||
integer elt2_a = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * s + 2 * i + sel_a, esize DIV 4]);
|
||||
integer elt2_b = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 4 * s + 2 * i + sel_b, esize DIV 4]);
|
||||
if sub_i then
|
||||
<ins> res = (res + (elt1_r * elt2_a)) - (elt1_i * elt2_b);
|
||||
</ins><del> res = res + (elt1_r * elt2_a) - (elt1_i * elt2_b);
|
||||
</del> else
|
||||
res = res + (elt1_r * elt2_a) + (elt1_i * elt2_b);
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = res;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</p></div><h3>Operational information</h3><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,103 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CHKFEAT -- A64</title></head><body htmldiffstatus="new"><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">no old file</td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CHKFEAT</h2><p class="aml">Check feature status. This instruction indicates the status of features.</p><p class="aml">If FEAT_CHK is not implemented, this instruction executes as a <span class="asm-code">NOP</span>.</p><h3 class="classheading"><a id="iclass_system"/>System<span style="font-size:smaller;"><br/>(FEAT_CHK)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>1</td><td class="r">0</td><td class="l">0</td><td>1</td><td>0</td><td class="r">1</td><td class="l">0</td><td>0</td><td class="r">0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td></tr><tr class="secondrow"><td colspan="10"/><td/><td colspan="2"/><td colspan="3"/><td colspan="4"/><td class="droppedname" colspan="4">CRm</td><td class="droppedname" colspan="3">op2</td><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="CHKFEAT_HI_hints"/><p class="asm-code">CHKFEAT</p></div><p class="pseudocode"><a href="shared_pseudocode.html#SystemHintOp" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp</a> op;
|
||||
|
||||
case CRm:op2 of
|
||||
when '0000 000' op = <a href="shared_pseudocode.html#SystemHintOp_NOP" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_NOP</a>;
|
||||
when '0000 001' op = <a href="shared_pseudocode.html#SystemHintOp_YIELD" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_YIELD</a>;
|
||||
when '0000 010' op = <a href="shared_pseudocode.html#SystemHintOp_WFE" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFE</a>;
|
||||
when '0000 011' op = <a href="shared_pseudocode.html#SystemHintOp_WFI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFI</a>;
|
||||
when '0000 100' op = <a href="shared_pseudocode.html#SystemHintOp_SEV" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEV</a>;
|
||||
when '0000 101' op = <a href="shared_pseudocode.html#SystemHintOp_SEVL" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEVL</a>;
|
||||
when '0000 110'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveDGHExt.0" title="function: boolean HaveDGHExt()">HaveDGHExt</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_DGH" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_DGH</a>;
|
||||
when '0000 111' SEE "XPACLRI";
|
||||
when '0001 xxx'
|
||||
case op2 of
|
||||
when '000' SEE "PACIA1716";
|
||||
when '010' SEE "PACIB1716";
|
||||
when '100' SEE "AUTIA1716";
|
||||
when '110' SEE "AUTIB1716";
|
||||
otherwise <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
when '0010 000'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveRASExt.0" title="function: boolean HaveRASExt()">HaveRASExt</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_ESB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_ESB</a>;
|
||||
when '0010 001'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveStatisticalProfiling.0" title="function: boolean HaveStatisticalProfiling()">HaveStatisticalProfiling</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_PSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_PSB</a>;
|
||||
when '0010 010'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveSelfHostedTrace.0" title="function: boolean HaveSelfHostedTrace()">HaveSelfHostedTrace</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_TSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_TSB</a>;
|
||||
when '0010 011'
|
||||
if !IsFeatureImplemented(FEAT_GCS) then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_GCSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_GCSB</a>;
|
||||
when '0010 100'
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_CSDB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CSDB</a>;
|
||||
when '0010 110'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveFeatCLRBHB.0" title="function: boolean HaveFeatCLRBHB()">HaveFeatCLRBHB</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_CLRBHB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CLRBHB</a>;
|
||||
when '0011 xxx'
|
||||
case op2 of
|
||||
when '000' SEE "PACIAZ";
|
||||
when '001' SEE "PACIASP";
|
||||
when '010' SEE "PACIBZ";
|
||||
when '011' SEE "PACIBSP";
|
||||
when '100' SEE "AUTIAZ";
|
||||
when '101' SEE "AUTIASP";
|
||||
when '110' SEE "AUTIBZ";
|
||||
when '111' SEE "AUTIBSP";
|
||||
when '0100 xx0'
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_BTI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_BTI</a>;
|
||||
// Check branch target compatibility between BTI instruction and PSTATE.BTYPE
|
||||
<a href="shared_pseudocode.html#impl-aarch64.SetBTypeCompatible.1" title="function: SetBTypeCompatible(boolean x)">SetBTypeCompatible</a>(<a href="shared_pseudocode.html#impl-aarch64.BTypeCompatible_BTI.1" title="function: boolean BTypeCompatible_BTI(bits(2) hintcode)">BTypeCompatible_BTI</a>(op2<2:1>));
|
||||
when '0101 000'
|
||||
if !IsFeatureImplemented(FEAT_CHK) then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_CHKFEAT" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CHKFEAT</a>;
|
||||
otherwise <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP</p><div class="encoding-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">case op of
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_YIELD" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_YIELD</a><a href="shared_pseudocode.html#impl-shared.Hint_Yield.0" title="function: Hint_Yield()">Hint_Yield</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_DGH" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_DGH</a><a href="shared_pseudocode.html#impl-shared.Hint_DGH.0" title="function: Hint_DGH()">Hint_DGH</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_WFE" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFE</a>
|
||||
integer localtimeout = 1 << 64; // No local timeout event is generated
|
||||
<a href="shared_pseudocode.html#impl-shared.Hint_WFE.2" title="function: Hint_WFE(integer localtimeout, WFxType wfxtype)">Hint_WFE</a>(localtimeout, <a href="shared_pseudocode.html#WFxType_WFE" title="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFE</a>);
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_WFI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFI</a>
|
||||
integer localtimeout = 1 << 64; // No local timeout event is generated
|
||||
<a href="shared_pseudocode.html#impl-shared.Hint_WFI.2" title="function: Hint_WFI(integer localtimeout, WFxType wfxtype)">Hint_WFI</a>(localtimeout, <a href="shared_pseudocode.html#WFxType_WFI" title="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFI</a>);
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_SEV" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEV</a><a href="shared_pseudocode.html#impl-shared.SendEvent.0" title="function: SendEvent()">SendEvent</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_SEVL" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEVL</a><a href="shared_pseudocode.html#impl-shared.SendEventLocal.0" title="function: SendEventLocal()">SendEventLocal</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_ESB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_ESB</a>
|
||||
if <a href="shared_pseudocode.html#impl-shared.HaveTME.0" title="function: boolean HaveTME()">HaveTME</a>() && TSTATE.depth > 0 then
|
||||
<a href="shared_pseudocode.html#impl-aarch64.FailTransaction.2" title="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(<a href="shared_pseudocode.html#TMFailure_ERR" title="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_ERR</a>, FALSE);
|
||||
<a href="shared_pseudocode.html#impl-shared.SynchronizeErrors.0" title="function: SynchronizeErrors()">SynchronizeErrors</a>();
|
||||
<a href="shared_pseudocode.html#AArch64.ESBOperation.0" title="function: AArch64.ESBOperation()">AArch64.ESBOperation</a>();
|
||||
if PSTATE.EL IN {<a href="shared_pseudocode.html#EL0" title="constant bits(2) EL0 = '00'">EL0</a>, <a href="shared_pseudocode.html#EL1" title="constant bits(2) EL1 = '01'">EL1</a>} && <a href="shared_pseudocode.html#impl-shared.EL2Enabled.0" title="function: boolean EL2Enabled()">EL2Enabled</a>() then <a href="shared_pseudocode.html#AArch64.vESBOperation.0" title="function: AArch64.vESBOperation()">AArch64.vESBOperation</a>();
|
||||
<a href="shared_pseudocode.html#impl-shared.TakeUnmaskedSErrorInterrupts.0" title="function: TakeUnmaskedSErrorInterrupts()">TakeUnmaskedSErrorInterrupts</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_PSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_PSB</a><a href="shared_pseudocode.html#impl-aarch64.ProfilingSynchronizationBarrier.0" title="function: ProfilingSynchronizationBarrier()">ProfilingSynchronizationBarrier</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_TSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_TSB</a><a href="shared_pseudocode.html#impl-shared.TraceSynchronizationBarrier.0" title="function: TraceSynchronizationBarrier()">TraceSynchronizationBarrier</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_GCSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_GCSB</a><a href="shared_pseudocode.html#impl-aarch64.GCSSynchronizationBarrier.0" title="function: GCSSynchronizationBarrier()">GCSSynchronizationBarrier</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_CHKFEAT" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CHKFEAT</a><a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[16, 64] = AArch64.ChkFeat(X[16, 64]);
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_CSDB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CSDB</a><a href="shared_pseudocode.html#impl-shared.ConsumptionOfSpeculativeDataBarrier.0" title="function: ConsumptionOfSpeculativeDataBarrier()">ConsumptionOfSpeculativeDataBarrier</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_CLRBHB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CLRBHB</a><a href="shared_pseudocode.html#impl-shared.Hint_CLRBHB.0" title="function: Hint_CLRBHB()">Hint_CLRBHB</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_BTI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_BTI</a><a href="shared_pseudocode.html#impl-aarch64.SetBTypeNext.1" title="function: SetBTypeNext(bits(2) x)">SetBTypeNext</a>('00');
|
||||
|
||||
otherwise // do nothing</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa v33.59, AdvSIMD v29.12, pseudocode v2022-12_rel, sve v2022-12_relb
|
||||
; Build timestamp: 2022-12-14T22:29
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">no old file</td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,105 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CLRBHB -- A64</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CLRBHB</h2><p class="aml">Clear Branch History clears the branch history for the current context to the extent that branch history information created before the <span class="asm-code">CLRBHB</span> instruction cannot be used by code before the <span class="asm-code">CLRBHB</span> instruction to exploitatively control the execution of any indirect branches in code in the current context that appear in program order after the instruction.</p><h3 class="classheading"><a id="iclass_system"/>System<span style="font-size:smaller;"><br/>(FEAT_CLRBHB)
|
||||
</span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>1</td><td class="r">0</td><td class="l">0</td><td>0</td><td>1</td><td class="r">0</td><td class="l">1</td><td>1</td><td class="r">0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td></tr><tr class="secondrow"><td colspan="10"/><td/><td colspan="2"/><td colspan="3"/><td colspan="4"/><td class="droppedname" colspan="4">CRm</td><td class="droppedname" colspan="3">op2</td><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="CLRBHB_HI_hints"/><p class="asm-code">CLRBHB</p></div><p class="pseudocode"><a href="shared_pseudocode.html#SystemHintOp" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp</a> op;
|
||||
|
||||
case CRm:op2 of
|
||||
when '0000 000' op = <a href="shared_pseudocode.html#SystemHintOp_NOP" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_NOP</a>;
|
||||
when '0000 001' op = <a href="shared_pseudocode.html#SystemHintOp_YIELD" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_YIELD</a>;
|
||||
when '0000 010' op = <a href="shared_pseudocode.html#SystemHintOp_WFE" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFE</a>;
|
||||
when '0000 011' op = <a href="shared_pseudocode.html#SystemHintOp_WFI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFI</a>;
|
||||
when '0000 100' op = <a href="shared_pseudocode.html#SystemHintOp_SEV" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEV</a>;
|
||||
when '0000 101' op = <a href="shared_pseudocode.html#SystemHintOp_SEVL" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEVL</a>;
|
||||
when '0000 110'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveDGHExt.0" title="function: boolean HaveDGHExt()">HaveDGHExt</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_DGH" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_DGH</a>;
|
||||
when '0000 111' SEE "XPACLRI";
|
||||
when '0001 xxx'
|
||||
case op2 of
|
||||
when '000' SEE "PACIA1716";
|
||||
when '010' SEE "PACIB1716";
|
||||
when '100' SEE "AUTIA1716";
|
||||
when '110' SEE "AUTIB1716";
|
||||
otherwise <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
when '0010 000'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveRASExt.0" title="function: boolean HaveRASExt()">HaveRASExt</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_ESB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_ESB</a>;
|
||||
when '0010 001'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveStatisticalProfiling.0" title="function: boolean HaveStatisticalProfiling()">HaveStatisticalProfiling</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_PSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_PSB</a>;
|
||||
when '0010 010'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveSelfHostedTrace.0" title="function: boolean HaveSelfHostedTrace()">HaveSelfHostedTrace</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_TSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_TSB</a>;
|
||||
<ins> when '0010 011'
|
||||
if !IsFeatureImplemented(FEAT_GCS) then</ins><del> when '0010 100'
|
||||
op =</del> <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()"><ins>EndOfInstruction</ins></a><ins>(); // Instruction executes as NOP
|
||||
op = </ins><a href="shared_pseudocode.html#SystemHintOp_GCSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }"><ins>SystemHintOp_GCSB</ins></a><ins>;
|
||||
when '0010 100'
|
||||
op = </ins><a href="shared_pseudocode.html#SystemHintOp_CSDB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CSDB</a>;
|
||||
when '0010 110'
|
||||
if !<a href="shared_pseudocode.html#impl-shared.HaveFeatCLRBHB.0" title="function: boolean HaveFeatCLRBHB()">HaveFeatCLRBHB</a>() then <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_CLRBHB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CLRBHB</a>;
|
||||
when '0011 xxx'
|
||||
case op2 of
|
||||
when '000' SEE "PACIAZ";
|
||||
when '001' SEE "PACIASP";
|
||||
when '010' SEE "PACIBZ";
|
||||
when '011' SEE "PACIBSP";
|
||||
when '100' SEE "AUTIAZ";
|
||||
when '101' SEE "AUTIASP";
|
||||
when '110' SEE "AUTIBZ";
|
||||
when '111' SEE "AUTIBSP";
|
||||
when '0100 xx0'
|
||||
op = <a href="shared_pseudocode.html#SystemHintOp_BTI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_BTI</a>;
|
||||
// Check branch target compatibility between BTI instruction and PSTATE.BTYPE
|
||||
<a href="shared_pseudocode.html#impl-aarch64.SetBTypeCompatible.1" title="function: SetBTypeCompatible(boolean x)">SetBTypeCompatible</a>(<a href="shared_pseudocode.html#impl-aarch64.BTypeCompatible_BTI.1" title="function: boolean BTypeCompatible_BTI(bits(2) hintcode)">BTypeCompatible_BTI</a><ins>(op2<2:1>));
|
||||
when '0101 000'
|
||||
if !IsFeatureImplemented(FEAT_CHK) then </ins><a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()"><ins>EndOfInstruction</ins></a><ins>(); // Instruction executes as NOP
|
||||
op = </ins><a href="shared_pseudocode.html#SystemHintOp_CHKFEAT" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }"><ins>SystemHintOp_CHKFEAT</ins></a><ins>;
|
||||
</ins><del>(op2<2:1>));
|
||||
</del> otherwise <a href="shared_pseudocode.html#impl-shared.EndOfInstruction.0" title="function: EndOfInstruction()">EndOfInstruction</a>(); // Instruction executes as NOP</p><div class="encoding-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode">case op of
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_YIELD" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_YIELD</a><a href="shared_pseudocode.html#impl-shared.Hint_Yield.0" title="function: Hint_Yield()">Hint_Yield</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_DGH" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_DGH</a><a href="shared_pseudocode.html#impl-shared.Hint_DGH.0" title="function: Hint_DGH()">Hint_DGH</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_WFE" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFE</a>
|
||||
integer localtimeout = 1 << 64; // No local timeout event is generated
|
||||
<a href="shared_pseudocode.html#impl-shared.Hint_WFE.2" title="function: Hint_WFE(integer localtimeout, WFxType wfxtype)">Hint_WFE</a>(localtimeout, <a href="shared_pseudocode.html#WFxType_WFE" title="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFE</a>);
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_WFI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_WFI</a>
|
||||
integer localtimeout = 1 << 64; // No local timeout event is generated
|
||||
<a href="shared_pseudocode.html#impl-shared.Hint_WFI.2" title="function: Hint_WFI(integer localtimeout, WFxType wfxtype)">Hint_WFI</a>(localtimeout, <a href="shared_pseudocode.html#WFxType_WFI" title="enumeration WFxType {WFxType_WFE, WFxType_WFI, WFxType_WFET, WFxType_WFIT}">WFxType_WFI</a>);
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_SEV" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEV</a><a href="shared_pseudocode.html#impl-shared.SendEvent.0" title="function: SendEvent()">SendEvent</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_SEVL" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_SEVL</a><a href="shared_pseudocode.html#impl-shared.SendEventLocal.0" title="function: SendEventLocal()">SendEventLocal</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_ESB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_ESB</a>
|
||||
if <a href="shared_pseudocode.html#impl-shared.HaveTME.0" title="function: boolean HaveTME()">HaveTME</a>() && TSTATE.depth > 0 then
|
||||
<a href="shared_pseudocode.html#impl-aarch64.FailTransaction.2" title="function: FailTransaction(TMFailure cause, boolean retry)">FailTransaction</a>(<a href="shared_pseudocode.html#TMFailure_ERR" title="enumeration TMFailure { TMFailure_CNCL, TMFailure_DBG, TMFailure_ERR, TMFailure_NEST, TMFailure_SIZE, TMFailure_MEM, TMFailure_TRIVIAL, TMFailure_IMP }">TMFailure_ERR</a>, FALSE);
|
||||
<a href="shared_pseudocode.html#impl-shared.SynchronizeErrors.0" title="function: SynchronizeErrors()">SynchronizeErrors</a>();
|
||||
<a href="shared_pseudocode.html#AArch64.ESBOperation.0" title="function: AArch64.ESBOperation()">AArch64.ESBOperation</a>();
|
||||
if PSTATE.EL IN {<a href="shared_pseudocode.html#EL0" title="constant bits(2) EL0 = '00'">EL0</a>, <a href="shared_pseudocode.html#EL1" title="constant bits(2) EL1 = '01'">EL1</a>} && <a href="shared_pseudocode.html#impl-shared.EL2Enabled.0" title="function: boolean EL2Enabled()">EL2Enabled</a>() then <a href="shared_pseudocode.html#AArch64.vESBOperation.0" title="function: AArch64.vESBOperation()">AArch64.vESBOperation</a>();
|
||||
<a href="shared_pseudocode.html#impl-shared.TakeUnmaskedSErrorInterrupts.0" title="function: TakeUnmaskedSErrorInterrupts()">TakeUnmaskedSErrorInterrupts</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_PSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_PSB</a><a href="shared_pseudocode.html#impl-aarch64.ProfilingSynchronizationBarrier.0" title="function: ProfilingSynchronizationBarrier()">ProfilingSynchronizationBarrier</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_TSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_TSB</a><a href="shared_pseudocode.html#impl-shared.TraceSynchronizationBarrier.0" title="function: TraceSynchronizationBarrier()">TraceSynchronizationBarrier</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_GCSB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }"><ins>SystemHintOp_GCSB</ins></a><a href="shared_pseudocode.html#impl-aarch64.GCSSynchronizationBarrier.0" title="function: GCSSynchronizationBarrier()"><ins>GCSSynchronizationBarrier</ins></a><ins>();
|
||||
|
||||
when </ins><a href="shared_pseudocode.html#SystemHintOp_CHKFEAT" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }"><ins>SystemHintOp_CHKFEAT</ins></a><a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value"><ins>X</ins></a><ins>[16, 64] = AArch64.ChkFeat(X[16, 64]);
|
||||
|
||||
when </ins><a href="shared_pseudocode.html#SystemHintOp_CSDB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CSDB</a><a href="shared_pseudocode.html#impl-shared.ConsumptionOfSpeculativeDataBarrier.0" title="function: ConsumptionOfSpeculativeDataBarrier()">ConsumptionOfSpeculativeDataBarrier</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_CLRBHB" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_CLRBHB</a><a href="shared_pseudocode.html#impl-shared.Hint_CLRBHB.0" title="function: Hint_CLRBHB()">Hint_CLRBHB</a>();
|
||||
|
||||
when <a href="shared_pseudocode.html#SystemHintOp_BTI" title="enumeration SystemHintOp { SystemHintOp_NOP, SystemHintOp_YIELD, SystemHintOp_WFE, SystemHintOp_WFI, SystemHintOp_SEV, SystemHintOp_SEVL, SystemHintOp_DGH, SystemHintOp_ESB, SystemHintOp_PSB, SystemHintOp_TSB, SystemHintOp_BTI, SystemHintOp_WFET, SystemHintOp_WFIT, SystemHintOp_CLRBHB, SystemHintOp_GCSB, SystemHintOp_CHKFEAT, SystemHintOp_CSDB }">SystemHintOp_BTI</a><a href="shared_pseudocode.html#impl-aarch64.SetBTypeNext.1" title="function: SetBTypeNext(bits(2) x)">SetBTypeNext</a>('00');
|
||||
|
||||
otherwise // do nothing</p></div><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,33 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CLS</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CLS</h2><p>Count leading sign bits (predicated)</p><p class="aml">Count the number of consecutive sign bits, starting from the most significant bit in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td class="l">1</td><td>0</td><td class="r">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cls_z_p_z_"/><p class="asm-code">CLS <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
bits(esize) element = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.CountLeadingSignBits.1" title="function: integer CountLeadingSignBits(bits(N) x)">CountLeadingSignBits</a>(element)<esize-1:0>;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,33 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CLZ</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CLZ</h2><p>Count leading zero bits (predicated)</p><p class="aml">Count the number of consecutive binary zero bits, starting from the most significant bit in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td class="r">0</td><td class="lr">1</td><td class="l">1</td><td>0</td><td class="r">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="clz_z_p_z_"/><p class="asm-code">CLZ <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
bits(esize) element = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.CountLeadingZeroBits.1" title="function: integer CountLeadingZeroBits(bits(N) x)">CountLeadingZeroBits</a>(element)<esize-1:0>;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,53 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CMLA (vectors)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CMLA (vectors)</h2><p>Complex integer multiply-add with rotate</p><p class="aml">Multiply the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the integral numbers in the first source vector by the corresponding complex number in the second source vector rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation.</p><p class="aml">Then add the products to the corresponding components of the complex numbers in the addend vector. Destructively place the results in the corresponding elements of the addend vector. This instruction is unpredicated.</p><p class="aml">These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart.</p><p class="aml">Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="l">0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="lr" colspan="2">rot</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zda</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmla_z_zzz_"/><p class="asm-code">CMLA <a href="#sa_zda" title="Third source and destination scalable vector register (field "Zda")"><Zda></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_const" title="Const specifier (field "rot") [#0,#90,#180,#270]"><const></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zda);
|
||||
integer sel_a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(rot<0>);
|
||||
integer sel_b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(NOT(rot<0>));
|
||||
boolean sub_r = (rot<0> != rot<1>);
|
||||
boolean sub_i = (rot<1> == '1');</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zda></td><td><a id="sa_zda"/><p class="aml">Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><const></td><td><a id="sa_const"/><p>Is the const specifier,
|
||||
encoded in
|
||||
<q>rot</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">rot</th><th class="symbol"><const></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">#0</td></tr><tr><td class="bitfield">01</td><td class="symbol">#90</td></tr><tr><td class="bitfield">10</td><td class="symbol">#180</td></tr><tr><td class="bitfield">11</td><td class="symbol">#270</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer pairs = VL DIV (2 * esize);
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for p = 0 to pairs-1
|
||||
integer elt1_a = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * p + sel_a, esize]);
|
||||
integer elt2_a = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * p + sel_a, esize]);
|
||||
integer elt2_b = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * p + sel_b, esize]);
|
||||
bits(esize) elt3_r = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, 2 * p + 0, esize];
|
||||
bits(esize) elt3_i = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, 2 * p + 1, esize];
|
||||
integer product_r = elt1_a * elt2_a;
|
||||
integer product_i = elt1_a * elt2_b;
|
||||
if sub_r then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 0, esize] = elt3_r - product_r;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 0, esize] = elt3_r + product_r;
|
||||
if sub_i then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 1, esize] = elt3_i - product_i;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 1, esize] = elt3_i + product_i;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,67 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CMLA (indexed)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CMLA (indexed)</h2><p>Complex integer multiply-add with rotate (indexed)</p><p class="aml">Multiply the duplicated real components for rotations 0 and 180, or imaginary components for rotations 90 and 270, of the integral numbers in each 128-bit segment of the first source vector by the specified complex number in the corresponding the second source vector segment rotated by 0, 90, 180 or 270 degrees in the direction from the positive real axis towards the positive imaginary axis, when considered in polar representation.</p><p class="aml">Then add the products to the corresponding components of the complex numbers in the addend vector. Destructively place the results in the corresponding elements of the addend vector. This instruction is unpredicated.</p><p class="aml">These transformations permit the creation of a variety of multiply-add and multiply-subtract operations on complex numbers by combining two of these instructions with the same vector operands but with rotations that are 90 degrees apart.</p><p class="aml">Each complex number is represented in a vector register as an even/odd pair of elements with the real part in the even-numbered element and the imaginary part in the odd-numbered element.</p><p class="desc">
|
||||
It has encodings from 2 classes:
|
||||
<a href="#iclass_of_halfwords">16-bit</a>
|
||||
and
|
||||
<a href="#iclass_of_words">32-bit</a></p><h3 class="classheading"><a id="iclass_of_halfwords"/>16-bit</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="2">i2</td><td class="lr" colspan="3">Zm</td><td class="l">0</td><td>1</td><td>1</td><td class="r">0</td><td class="lr" colspan="2">rot</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zda</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td/><td colspan="2"/><td colspan="3"/><td colspan="4"/><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmla_z_zzzi_h"/><p class="asm-code">CMLA <a href="#sa_zda" title="Third source and destination scalable vector register (field "Zda")"><Zda></a>.H, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.H, <a href="#sa_zm" title="Second source scalable vector register Z0-Z7 (field "Zm")"><Zm></a>.H[<a href="#sa_imm" title="Element index [0-3] (field "i2")"><imm></a>], <a href="#sa_const" title="Const specifier (field "rot") [#0,#90,#180,#270]"><const></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 16;
|
||||
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(i2);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zda);
|
||||
integer sel_a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(rot<0>);
|
||||
integer sel_b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(NOT(rot<0>));
|
||||
boolean sub_r = (rot<0> != rot<1>);
|
||||
boolean sub_i = (rot<1> == '1');</p><h3 class="classheading"><a id="iclass_of_words"/>32-bit</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>1</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr">1</td><td class="lr">i1</td><td class="lr" colspan="4">Zm</td><td class="l">0</td><td>1</td><td>1</td><td class="r">0</td><td class="lr" colspan="2">rot</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zda</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td/><td/><td colspan="4"/><td colspan="4"/><td colspan="2"/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmla_z_zzzi_s"/><p class="asm-code">CMLA <a href="#sa_zda" title="Third source and destination scalable vector register (field "Zda")"><Zda></a>.S, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.S, <a href="#sa_zm_1" title="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a>.S[<a href="#sa_imm_1" title="Element index [0-1] (field "i1")"><imm></a>], <a href="#sa_const" title="Const specifier (field "rot") [#0,#90,#180,#270]"><const></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE2.0" title="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 32;
|
||||
integer index = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(i1);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zda);
|
||||
integer sel_a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(rot<0>);
|
||||
integer sel_b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(NOT(rot<0>));
|
||||
boolean sub_r = (rot<0> != rot<1>);
|
||||
boolean sub_i = (rot<1> == '1');</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zda></td><td><a id="sa_zda"/><p class="aml">Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">For the 16-bit variant: is the name of the second source scalable vector register Z0-Z7, encoded in the "Zm" field.</p></td></tr><tr><td/><td><a id="sa_zm_1"/><p class="aml">For the 32-bit variant: is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><imm></td><td><a id="sa_imm"/><p class="aml">For the 16-bit variant: is the element index, in the range 0 to 3, encoded in the "i2" field.</p></td></tr><tr><td/><td><a id="sa_imm_1"/><p class="aml">For the 32-bit variant: is the element index, in the range 0 to 1, encoded in the "i1" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><const></td><td><a id="sa_const"/><p>Is the const specifier,
|
||||
encoded in
|
||||
<q>rot</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">rot</th><th class="symbol"><const></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">#0</td></tr><tr><td class="bitfield">01</td><td class="symbol">#90</td></tr><tr><td class="bitfield">10</td><td class="symbol">#180</td></tr><tr><td class="bitfield">11</td><td class="symbol">#270</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer pairs = VL DIV (2 * esize);
|
||||
constant integer pairspersegment = 128 DIV (2 * esize);
|
||||
bits(VL) operand1 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for p = 0 to pairs-1
|
||||
integer segmentbase = p - (p MOD pairspersegment);
|
||||
integer s = segmentbase + index;
|
||||
integer elt1_a = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, 2 * p + sel_a, esize]);
|
||||
integer elt2_a = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * s + sel_a, esize]);
|
||||
integer elt2_b = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, 2 * s + sel_b, esize]);
|
||||
bits(esize) elt3_r = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, 2 * p + 0, esize];
|
||||
bits(esize) elt3_i = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, 2 * p + 1, esize];
|
||||
integer product_r = elt1_a * elt2_a;
|
||||
integer product_i = elt1_a * elt2_b;
|
||||
if sub_r then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 0, esize] = elt3_r - product_r;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 0, esize] = elt3_r + product_r;
|
||||
if sub_i then
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 1, esize] = elt3_i - product_i;
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2 * p + 1, esize] = elt3_i + product_i;
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,130 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CMP<cc> (immediate)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CMP<cc> (immediate)</h2><p>Compare vector to immediate</p><p class="aml">Compare active integer elements in the source vector with an immediate, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the <span class="arm-defined-word">First</span> (N), <span class="arm-defined-word">None</span> (Z), <span class="arm-defined-word">!Last</span> (C) condition flags based on the predicate result, and the V flag to zero.</p><p class="aml"/><table class="valuetable"><thead><tr><th class=""><cc></th><th class="">Comparison</th></tr></thead><tbody><tr><td class="">EQ</td><td class="">equal</td></tr><tr><td class="">GE</td><td class="">signed greater than or equal</td></tr><tr><td class="">GT</td><td class="">signed greater than</td></tr><tr><td class="">HI</td><td class="">unsigned higher than</td></tr><tr><td class="">HS</td><td class="">unsigned higher than or same</td></tr><tr><td class="">LE</td><td class="">signed less than or equal</td></tr><tr><td class="">LO</td><td class="">unsigned lower than</td></tr><tr><td class="">LS</td><td class="">unsigned lower than or same</td></tr><tr><td class="">LT</td><td class="">signed less than</td></tr><tr><td class="">NE</td><td class="">not equal</td></tr></tbody></table><p class="desc">
|
||||
It has encodings from 10 classes:
|
||||
<a href="#iclass_eq">Equal</a>
|
||||
,
|
||||
<a href="#iclass_gt">Greater than</a>
|
||||
,
|
||||
<a href="#iclass_ge">Greater than or equal</a>
|
||||
,
|
||||
<a href="#iclass_hi">Higher</a>
|
||||
,
|
||||
<a href="#iclass_hs">Higher or same</a>
|
||||
,
|
||||
<a href="#iclass_lt">Less than</a>
|
||||
,
|
||||
<a href="#iclass_le">Less than or equal</a>
|
||||
,
|
||||
<a href="#iclass_lo">Lower</a>
|
||||
,
|
||||
<a href="#iclass_ls">Lower or same</a>
|
||||
and
|
||||
<a href="#iclass_ne">Not equal</a></p><h3 class="classheading"><a id="iclass_eq"/>Equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">imm5</td><td class="lr">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpeq_p_p_zi_"/><p class="asm-code">CMPEQ <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, #<a href="#sa_imm" title="Signed immediate operand [-16-15] (field "imm5")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_EQ" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_EQ</a>;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(imm5);
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_gt"/>Greater than</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">imm5</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpgt_p_p_zi_"/><p class="asm-code">CMPGT <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, #<a href="#sa_imm" title="Signed immediate operand [-16-15] (field "imm5")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GT</a>;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(imm5);
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_ge"/>Greater than or equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">imm5</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpge_p_p_zi_"/><p class="asm-code">CMPGE <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, #<a href="#sa_imm" title="Signed immediate operand [-16-15] (field "imm5")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</a>;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(imm5);
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_hi"/>Higher</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">1</td><td class="lr" colspan="7">imm7</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="7"/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmphi_p_p_zi_"/><p class="asm-code">CMPHI <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, #<a href="#sa_imm_1" title="Unsigned immediate operand [0-127] (field "imm7")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GT</a>;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(imm7);
|
||||
boolean unsigned = TRUE;</p><h3 class="classheading"><a id="iclass_hs"/>Higher or same</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">1</td><td class="lr" colspan="7">imm7</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="7"/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmphs_p_p_zi_"/><p class="asm-code">CMPHS <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, #<a href="#sa_imm_1" title="Unsigned immediate operand [0-127] (field "imm7")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</a>;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(imm7);
|
||||
boolean unsigned = TRUE;</p><h3 class="classheading"><a id="iclass_lt"/>Less than</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">imm5</td><td class="lr">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmplt_p_p_zi_"/><p class="asm-code">CMPLT <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, #<a href="#sa_imm" title="Signed immediate operand [-16-15] (field "imm5")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_LT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LT</a>;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(imm5);
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_le"/>Less than or equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">imm5</td><td class="lr">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmple_p_p_zi_"/><p class="asm-code">CMPLE <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, #<a href="#sa_imm" title="Signed immediate operand [-16-15] (field "imm5")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_LE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LE</a>;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(imm5);
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_lo"/>Lower</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">1</td><td class="lr" colspan="7">imm7</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="7"/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmplo_p_p_zi_"/><p class="asm-code">CMPLO <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, #<a href="#sa_imm_1" title="Unsigned immediate operand [0-127] (field "imm7")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_LT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LT</a>;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(imm7);
|
||||
boolean unsigned = TRUE;</p><h3 class="classheading"><a id="iclass_ls"/>Lower or same</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">1</td><td class="lr" colspan="7">imm7</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="7"/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpls_p_p_zi_"/><p class="asm-code">CMPLS <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, #<a href="#sa_imm_1" title="Unsigned immediate operand [0-127] (field "imm7")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_LE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LE</a>;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(imm7);
|
||||
boolean unsigned = TRUE;</p><h3 class="classheading"><a id="iclass_ne"/>Not equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">imm5</td><td class="lr">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpne_p_p_zi_"/><p class="asm-code">CMPNE <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, #<a href="#sa_imm" title="Signed immediate operand [-16-15] (field "imm5")"><imm></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_NE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_NE</a>;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.SInt.1" title="function: integer SInt(bits(N) x)">SInt</a>(imm5);
|
||||
boolean unsigned = FALSE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pd></td><td><a id="sa_pd"/><p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><imm></td><td><a id="sa_imm"/><p class="aml">For the equal, greater than, greater than or equal, less than, less than or equal and not equal variant: is the signed immediate operand, in the range -16 to 15, encoded in the "imm5" field.</p></td></tr><tr><td/><td><a id="sa_imm_1"/><p class="aml">For the higher, higher or same, lower and lower or same variant: is the unsigned immediate operand, in the range 0 to 127, encoded in the "imm7" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(PL) result;
|
||||
constant integer psize = esize DIV 8;
|
||||
|
||||
for e = 0 to elements-1
|
||||
integer element1 = <a href="shared_pseudocode.html#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
boolean cond;
|
||||
case op of
|
||||
when <a href="shared_pseudocode.html#Cmp_EQ" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_EQ</a> cond = element1 == imm;
|
||||
when <a href="shared_pseudocode.html#Cmp_NE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_NE</a> cond = element1 != imm;
|
||||
when <a href="shared_pseudocode.html#Cmp_GE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</a> cond = element1 >= imm;
|
||||
when <a href="shared_pseudocode.html#Cmp_LT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LT</a> cond = element1 < imm;
|
||||
when <a href="shared_pseudocode.html#Cmp_GT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GT</a> cond = element1 > imm;
|
||||
when <a href="shared_pseudocode.html#Cmp_LE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LE</a> cond = element1 <= imm;
|
||||
bit pbit = if cond then '1' else '0';
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(pbit, psize);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', psize);
|
||||
|
||||
PSTATE.<N,Z,C,V> = <a href="shared_pseudocode.html#impl-aarch64.PredTest.3" title="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</a>(mask, result, esize);
|
||||
<a href="shared_pseudocode.html#impl-aarch64.P.write.2" title="accessor: P[integer n, integer width] = bits(width) value">P</a>[d, PL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register or NZCV condition flags written by this instruction might be significantly delayed.</p><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,142 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CMP<cc> (wide elements)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CMP<cc> (wide elements)</h2><p>Compare vector to 64-bit wide elements</p><p class="aml">Compare active integer elements in the first source vector with overlapping 64-bit doubleword elements in the second source vector, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the <span class="arm-defined-word">First</span> (N), <span class="arm-defined-word">None</span> (Z), <span class="arm-defined-word">!Last</span> (C) condition flags based on the predicate result, and the V flag to zero.</p><p class="aml"/><table class="valuetable"><thead><tr><th class=""><cc></th><th class="">Comparison</th></tr></thead><tbody><tr><td class="">EQ</td><td class="">equal</td></tr><tr><td class="">GE</td><td class="">signed greater than or equal</td></tr><tr><td class="">GT</td><td class="">signed greater than</td></tr><tr><td class="">HI</td><td class="">unsigned higher than</td></tr><tr><td class="">HS</td><td class="">unsigned higher than or same</td></tr><tr><td class="">LE</td><td class="">signed less than or equal</td></tr><tr><td class="">LO</td><td class="">unsigned lower than</td></tr><tr><td class="">LS</td><td class="">unsigned lower than or same</td></tr><tr><td class="">LT</td><td class="">signed less than</td></tr><tr><td class="">NE</td><td class="">not equal</td></tr></tbody></table><p class="desc">
|
||||
It has encodings from 10 classes:
|
||||
<a href="#iclass_eq">Equal</a>
|
||||
,
|
||||
<a href="#iclass_gt">Greater than</a>
|
||||
,
|
||||
<a href="#iclass_ge">Greater than or equal</a>
|
||||
,
|
||||
<a href="#iclass_hi">Higher</a>
|
||||
,
|
||||
<a href="#iclass_hs">Higher or same</a>
|
||||
,
|
||||
<a href="#iclass_lt">Less than</a>
|
||||
,
|
||||
<a href="#iclass_le">Less than or equal</a>
|
||||
,
|
||||
<a href="#iclass_lo">Lower</a>
|
||||
,
|
||||
<a href="#iclass_ls">Lower or same</a>
|
||||
and
|
||||
<a href="#iclass_ne">Not equal</a></p><h3 class="classheading"><a id="iclass_eq"/>Equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpeq_p_p_zw_"/><p class="asm-code">CMPEQ <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_EQ" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_EQ</a>;
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_gt"/>Greater than</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">0</td><td class="lr">1</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td class="droppedname">U</td><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpgt_p_p_zw_"/><p class="asm-code">CMPGT <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GT</a>;
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_ge"/>Greater than or equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">0</td><td class="lr">1</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td class="droppedname">U</td><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpge_p_p_zw_"/><p class="asm-code">CMPGE <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</a>;
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_hi"/>Higher</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">1</td><td class="lr">1</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td class="droppedname">U</td><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmphi_p_p_zw_"/><p class="asm-code">CMPHI <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GT</a>;
|
||||
boolean unsigned = TRUE;</p><h3 class="classheading"><a id="iclass_hs"/>Higher or same</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">1</td><td class="lr">1</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td class="droppedname">U</td><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmphs_p_p_zw_"/><p class="asm-code">CMPHS <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</a>;
|
||||
boolean unsigned = TRUE;</p><h3 class="classheading"><a id="iclass_lt"/>Less than</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td class="droppedname">U</td><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmplt_p_p_zw_"/><p class="asm-code">CMPLT <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_LT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LT</a>;
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_le"/>Less than or equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">0</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td class="droppedname">U</td><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmple_p_p_zw_"/><p class="asm-code">CMPLE <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_LE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LE</a>;
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_lo"/>Lower</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">1</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td class="droppedname">U</td><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmplo_p_p_zw_"/><p class="asm-code">CMPLO <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_LT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LT</a>;
|
||||
boolean unsigned = TRUE;</p><h3 class="classheading"><a id="iclass_ls"/>Lower or same</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">1</td><td class="lr">1</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td class="droppedname">U</td><td/><td class="droppedname">lt</td><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpls_p_p_zw_"/><p class="asm-code">CMPLS <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_LE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LE</a>;
|
||||
boolean unsigned = TRUE;</p><h3 class="classheading"><a id="iclass_ne"/>Not equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">0</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpne_p_p_zw_"/><p class="asm-code">CMPNE <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_NE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_NE</a>;
|
||||
boolean unsigned = FALSE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pd></td><td><a id="sa_pd"/><p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">RESERVED</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) operand2 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(PL) result;
|
||||
constant integer psize = esize DIV 8;
|
||||
|
||||
for e = 0 to elements-1
|
||||
integer element1 = <a href="shared_pseudocode.html#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
boolean cond;
|
||||
integer element2 = <a href="shared_pseudocode.html#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, (e * esize) DIV 64, 64], unsigned);
|
||||
case op of
|
||||
when <a href="shared_pseudocode.html#Cmp_EQ" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_EQ</a> cond = element1 == element2;
|
||||
when <a href="shared_pseudocode.html#Cmp_NE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_NE</a> cond = element1 != element2;
|
||||
when <a href="shared_pseudocode.html#Cmp_GE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</a> cond = element1 >= element2;
|
||||
when <a href="shared_pseudocode.html#Cmp_LT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LT</a> cond = element1 < element2;
|
||||
when <a href="shared_pseudocode.html#Cmp_GT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GT</a> cond = element1 > element2;
|
||||
when <a href="shared_pseudocode.html#Cmp_LE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LE</a> cond = element1 <= element2;
|
||||
bit pbit = if cond then '1' else '0';
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(pbit, psize);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', psize);
|
||||
|
||||
PSTATE.<N,Z,C,V> = <a href="shared_pseudocode.html#impl-aarch64.PredTest.3" title="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</a>(mask, result, esize);
|
||||
<a href="shared_pseudocode.html#impl-aarch64.P.write.2" title="accessor: P[integer n, integer width] = bits(width) value">P</a>[d, PL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register or NZCV condition flags written by this instruction might be significantly delayed.</p><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,96 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CMP<cc> (vectors)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CMP<cc> (vectors)</h2><p>Compare vectors</p><p class="aml">Compare active integer elements in the first source vector with corresponding elements in the second source vector, and place the boolean results of the specified comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the <span class="arm-defined-word">First</span> (N), <span class="arm-defined-word">None</span> (Z), <span class="arm-defined-word">!Last</span> (C) condition flags based on the predicate result, and the V flag to zero.</p><p class="aml"/><table class="valuetable"><thead><tr><th class=""><cc></th><th class="">Comparison</th></tr></thead><tbody><tr><td class="">EQ</td><td class="">equal</td></tr><tr><td class="">GE</td><td class="">signed greater than or equal</td></tr><tr><td class="">GT</td><td class="">signed greater than</td></tr><tr><td class="">HI</td><td class="">unsigned higher than</td></tr><tr><td class="">HS</td><td class="">unsigned higher than or same</td></tr><tr><td class="">NE</td><td class="">not equal</td></tr></tbody></table><p class="desc">This instruction is used by the pseudo-instructions <a href="cmple_cmpeq_p_p_zz.html" title="Compare signed less than or equal to vector">CMPLE (vectors)</a>, <a href="cmplo_cmpeq_p_p_zz.html" title="Compare unsigned lower than vector">CMPLO (vectors)</a>, <a href="cmpls_cmpeq_p_p_zz.html" title="Compare unsigned lower or same as vector">CMPLS (vectors)</a>, and <a href="cmplt_cmpeq_p_p_zz.html" title="Compare signed less than vector">CMPLT (vectors)</a>.</p><p class="desc">
|
||||
It has encodings from 6 classes:
|
||||
<a href="#iclass_eq">Equal</a>
|
||||
,
|
||||
<a href="#iclass_gt">Greater than</a>
|
||||
,
|
||||
<a href="#iclass_ge">Greater than or equal</a>
|
||||
,
|
||||
<a href="#iclass_hi">Higher</a>
|
||||
,
|
||||
<a href="#iclass_hs">Higher or same</a>
|
||||
and
|
||||
<a href="#iclass_ne">Not equal</a></p><h3 class="classheading"><a id="iclass_eq"/>Equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">1</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpeq_p_p_zz_"/><p class="asm-code">CMPEQ <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_EQ" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_EQ</a>;
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_gt"/>Greater than</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpgt_p_p_zz_"/><p class="asm-code">CMPGT <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GT</a>;
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_ge"/>Greater than or equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpge_p_p_zz_"/><p class="asm-code">CMPGE <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</a>;
|
||||
boolean unsigned = FALSE;</p><h3 class="classheading"><a id="iclass_hi"/>Higher</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmphi_p_p_zz_"/><p class="asm-code">CMPHI <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GT</a>;
|
||||
boolean unsigned = TRUE;</p><h3 class="classheading"><a id="iclass_hs"/>Higher or same</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmphs_p_p_zz_"/><p class="asm-code">CMPHS <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_GE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</a>;
|
||||
boolean unsigned = TRUE;</p><h3 class="classheading"><a id="iclass_ne"/>Not equal</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">1</td><td class="lr">0</td><td class="lr">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cmpne_p_p_zz_"/><p class="asm-code">CMPNE <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
<a href="shared_pseudocode.html#SVECmp" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">SVECmp</a> op = <a href="shared_pseudocode.html#Cmp_NE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_NE</a>;
|
||||
boolean unsigned = FALSE;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pd></td><td><a id="sa_pd"/><p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) operand2 = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(PL) result;
|
||||
constant integer psize = esize DIV 8;
|
||||
|
||||
for e = 0 to elements-1
|
||||
integer element1 = <a href="shared_pseudocode.html#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize], unsigned);
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
boolean cond;
|
||||
integer element2 = <a href="shared_pseudocode.html#impl-shared.Int.2" title="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize], unsigned);
|
||||
case op of
|
||||
when <a href="shared_pseudocode.html#Cmp_EQ" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_EQ</a> cond = element1 == element2;
|
||||
when <a href="shared_pseudocode.html#Cmp_NE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_NE</a> cond = element1 != element2;
|
||||
when <a href="shared_pseudocode.html#Cmp_GE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GE</a> cond = element1 >= element2;
|
||||
when <a href="shared_pseudocode.html#Cmp_LT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LT</a> cond = element1 < element2;
|
||||
when <a href="shared_pseudocode.html#Cmp_GT" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_GT</a> cond = element1 > element2;
|
||||
when <a href="shared_pseudocode.html#Cmp_LE" title="enumeration SVECmp { Cmp_EQ, Cmp_NE, Cmp_GE, Cmp_GT, Cmp_LT, Cmp_LE, Cmp_UN }">Cmp_LE</a> cond = element1 <= element2;
|
||||
bit pbit = if cond then '1' else '0';
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(pbit, psize);
|
||||
else
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', psize);
|
||||
|
||||
PSTATE.<N,Z,C,V> = <a href="shared_pseudocode.html#impl-aarch64.PredTest.3" title="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</a>(mask, result, esize);
|
||||
<a href="shared_pseudocode.html#impl-aarch64.P.write.2" title="accessor: P[integer n, integer width] = bits(width) value">P</a>[d, PL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register or NZCV condition flags written by this instruction might be significantly delayed.</p><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,25 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CMPLE (vectors)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CMPLE (vectors)</h2><p>Compare signed less than or equal to vector, setting the condition flags</p><p class="aml">Compare active signed integer elements in the first source vector being less than or equal to corresponding signed elements in the second source vector, and place the boolean results of the comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the <span class="arm-defined-word">First</span> (N), <span class="arm-defined-word">None</span> (Z), <span class="arm-defined-word">!Last</span> (C) condition flags based on the predicate result, and the V flag to zero.</p><p>
|
||||
This is a pseudo-instruction of
|
||||
<a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a>.
|
||||
This means:
|
||||
</p><ul><li>
|
||||
The encodings in this description are named to match the encodings of
|
||||
<a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a>.
|
||||
</li><li>
|
||||
The assembler syntax is used only for assembly, and is not used on disassembly.
|
||||
</li><li>The description of <a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="CMPLE_cmpge_p_p_zz_"/><p class="asm-code">CMPLE <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p><p class="equivto">
|
||||
is equivalent to
|
||||
</p><p class="asm-code"><a href="cmpeq_p_p_zz.html#cmpge_p_p_zz_">CMPGE</a> <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pd></td><td><a id="sa_pd"/><p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a> gives the operational pseudocode for this instruction.</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register or NZCV condition flags written by this instruction might be significantly delayed.</p><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,25 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CMPLO (vectors)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CMPLO (vectors)</h2><p>Compare unsigned lower than vector, setting the condition flags</p><p class="aml">Compare active unsigned integer elements in the first source vector being lower than corresponding unsigned elements in the second source vector, and place the boolean results of the comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the <span class="arm-defined-word">First</span> (N), <span class="arm-defined-word">None</span> (Z), <span class="arm-defined-word">!Last</span> (C) condition flags based on the predicate result, and the V flag to zero.</p><p>
|
||||
This is a pseudo-instruction of
|
||||
<a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a>.
|
||||
This means:
|
||||
</p><ul><li>
|
||||
The encodings in this description are named to match the encodings of
|
||||
<a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a>.
|
||||
</li><li>
|
||||
The assembler syntax is used only for assembly, and is not used on disassembly.
|
||||
</li><li>The description of <a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="CMPLO_cmphi_p_p_zz_"/><p class="asm-code">CMPLO <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p><p class="equivto">
|
||||
is equivalent to
|
||||
</p><p class="asm-code"><a href="cmpeq_p_p_zz.html#cmphi_p_p_zz_">CMPHI</a> <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pd></td><td><a id="sa_pd"/><p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a> gives the operational pseudocode for this instruction.</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register or NZCV condition flags written by this instruction might be significantly delayed.</p><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,25 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CMPLS (vectors)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CMPLS (vectors)</h2><p>Compare unsigned lower or same as vector, setting the condition flags</p><p class="aml">Compare active unsigned integer elements in the first source vector being lower than or same as corresponding unsigned elements in the second source vector, and place the boolean results of the comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the <span class="arm-defined-word">First</span> (N), <span class="arm-defined-word">None</span> (Z), <span class="arm-defined-word">!Last</span> (C) condition flags based on the predicate result, and the V flag to zero.</p><p>
|
||||
This is a pseudo-instruction of
|
||||
<a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a>.
|
||||
This means:
|
||||
</p><ul><li>
|
||||
The encodings in this description are named to match the encodings of
|
||||
<a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a>.
|
||||
</li><li>
|
||||
The assembler syntax is used only for assembly, and is not used on disassembly.
|
||||
</li><li>The description of <a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">0</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="CMPLS_cmphs_p_p_zz_"/><p class="asm-code">CMPLS <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p><p class="equivto">
|
||||
is equivalent to
|
||||
</p><p class="asm-code"><a href="cmpeq_p_p_zz.html#cmphs_p_p_zz_">CMPHS</a> <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pd></td><td><a id="sa_pd"/><p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a> gives the operational pseudocode for this instruction.</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register or NZCV condition flags written by this instruction might be significantly delayed.</p><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,25 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CMPLT (vectors)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CMPLT (vectors)</h2><p>Compare signed less than vector, setting the condition flags</p><p class="aml">Compare active signed integer elements in the first source vector being less than corresponding signed elements in the second source vector, and place the boolean results of the comparison in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the <span class="arm-defined-word">First</span> (N), <span class="arm-defined-word">None</span> (Z), <span class="arm-defined-word">!Last</span> (C) condition flags based on the predicate result, and the V flag to zero.</p><p>
|
||||
This is a pseudo-instruction of
|
||||
<a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a>.
|
||||
This means:
|
||||
</p><ul><li>
|
||||
The encodings in this description are named to match the encodings of
|
||||
<a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a>.
|
||||
</li><li>
|
||||
The assembler syntax is used only for assembly, and is not used on disassembly.
|
||||
</li><li>The description of <a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a> gives the operational pseudocode, any <span class="arm-defined-word">constrained unpredictable</span> behavior, and any operational information for this instruction.</li></ul><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="lr">0</td><td class="lr" colspan="5">Zm</td><td class="lr">1</td><td class="lr">0</td><td class="lr">0</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr">1</td><td class="lr" colspan="4">Pd</td></tr><tr class="secondrow"><td colspan="8"/><td colspan="2"/><td/><td colspan="5"/><td/><td/><td/><td colspan="3"/><td colspan="5"/><td class="droppedname">ne</td><td colspan="4"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="CMPLT_cmpgt_p_p_zz_"/><p class="asm-code">CMPLT <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p><p class="equivto">
|
||||
is equivalent to
|
||||
</p><p class="asm-code"><a href="cmpeq_p_p_zz.html#cmpgt_p_p_zz_">CMPGT</a> <a href="#sa_pd" title="Destination scalable predicate register (field "Pd")"><Pd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/Z, <a href="#sa_zn" title="First source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_zm" title="Second source scalable vector register (field "Zm")"><Zm></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pd></td><td><a id="sa_pd"/><p class="aml">Is the name of the destination scalable predicate register, encoded in the "Pd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zm></td><td><a id="sa_zm"/><p class="aml">Is the name of the second source scalable vector register, encoded in the "Zm" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the first source scalable vector register, encoded in the "Zn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="alias_ps_section"><h3 class="pseudocode">Operation</h3><p>The description of <a href="cmpeq_p_p_zz.html">CMP<cc> (vectors)</a> gives the operational pseudocode for this instruction.</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the predicate register or NZCV condition flags written by this instruction might be significantly delayed.</p><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,33 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CNOT</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CNOT</h2><p>Logically invert boolean condition in vector (predicated)</p><p class="aml">Logically invert the boolean value in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.</p><p class="aml">Boolean TRUE is any non-zero value in a source, and one in a result element. Boolean FALSE is always zero.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr" colspan="2">size</td><td class="l">0</td><td>1</td><td class="r">1</td><td class="l">0</td><td class="r">1</td><td class="lr">1</td><td class="l">1</td><td>0</td><td class="r">1</td><td class="lr" colspan="3">Pg</td><td class="lr" colspan="5">Zn</td><td class="lr" colspan="5">Zd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cnot_z_p_z_"/><p class="asm-code">CNOT <a href="#sa_zd" title="Destination scalable vector register (field "Zd")"><Zd></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a>, <a href="#sa_pg" title="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a>/M, <a href="#sa_zn" title="Source scalable vector register (field "Zn")"><Zn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zd></td><td><a id="sa_zd"/><p class="aml">Is the name of the destination scalable vector register, encoded in the "Zd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Zn></td><td><a id="sa_zn"/><p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand = if <a href="shared_pseudocode.html#impl-aarch64.AnyActiveElement.2" title="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
bits(esize) element = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
|
||||
<a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a href="shared_pseudocode.html#impl-shared.ZeroExtend.2" title="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(<a href="shared_pseudocode.html#impl-shared.IsZeroBit.1" title="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(element), esize);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.Z.write.2" title="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">
|
||||
This instruction might be immediately preceded in program order by a <span class="asm-code">MOVPRFX</span> instruction. The <span class="asm-code">MOVPRFX</span> instruction must conform to all of the following requirements, otherwise the behavior of the <span class="asm-code">MOVPRFX</span> and this instruction is <span class="arm-defined-word">unpredictable</span>:
|
||||
</p><ul><li>The <span class="asm-code">MOVPRFX</span> instruction must be unpredicated, or be predicated using the same governing predicate register and source element size as this instruction.</li><li>The <span class="asm-code">MOVPRFX</span> instruction must specify the same destination register as this instruction.</li><li>The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.</li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,49 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CNTB, CNTD, CNTH, CNTW</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CNTB, CNTD, CNTH, CNTW</h2><p>Set scalar to multiple of predicate constraint element count</p><p class="aml">Determines the number of active elements implied by the named predicate constraint, multiplies that by an immediate in the range 1 to 16 inclusive, and then places the result in the scalar destination.</p><p class="aml">The named predicate constraint limits the number of active elements in a single predicate to:</p><ul><li>
|
||||
A fixed number (VL1 to VL256)
|
||||
</li><li>
|
||||
The largest power of two (POW2)
|
||||
</li><li>
|
||||
The largest multiple of three or four (MUL3 or MUL4)
|
||||
</li><li>
|
||||
All available, implicitly a multiple of two (ALL).
|
||||
</li></ul><p class="aml">Unspecified or out of range constraint encodings generate an empty predicate or zero element count rather than Undefined Instruction exception.</p><p class="desc">
|
||||
It has encodings from 4 classes:
|
||||
<a href="#iclass_esize_byte">Byte</a>
|
||||
,
|
||||
<a href="#iclass_esize_doubleword">Doubleword</a>
|
||||
,
|
||||
<a href="#iclass_esize_halfword">Halfword</a>
|
||||
and
|
||||
<a href="#iclass_esize_word">Word</a></p><h3 class="classheading"><a id="iclass_esize_byte"/>Byte</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">0</td><td class="l">1</td><td class="r">0</td><td class="lr" colspan="4">imm4</td><td class="l">1</td><td>1</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="5">pattern</td><td class="lr" colspan="5">Rd</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td colspan="2"/><td colspan="4"/><td colspan="5"/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cntb_r_s_"/><p class="asm-code">CNTB <a href="#sa_xd" title="64-bit destination general-purpose register (field "Rd")"><Xd></a>{, <a href="#sa_pattern" title="Optional pattern specifier, default ALL (field "pattern") [#uimm5,ALL,MUL3,MUL4,POW2,VL1,VL2,VL3,VL4,VL5,VL6,VL7,VL8,VL16,VL32,VL64,VL128,VL256]"><pattern></a>{, MUL #<a href="#sa_imm" title="Immediate multiplier [1-16], default 1 (field "imm4")"><imm></a>}}</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8;
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
bits(5) pat = pattern;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(imm4) + 1;</p><h3 class="classheading"><a id="iclass_esize_doubleword"/>Doubleword</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">1</td><td class="l">1</td><td class="r">0</td><td class="lr" colspan="4">imm4</td><td class="l">1</td><td>1</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="5">pattern</td><td class="lr" colspan="5">Rd</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td colspan="2"/><td colspan="4"/><td colspan="5"/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cntd_r_s_"/><p class="asm-code">CNTD <a href="#sa_xd" title="64-bit destination general-purpose register (field "Rd")"><Xd></a>{, <a href="#sa_pattern" title="Optional pattern specifier, default ALL (field "pattern") [#uimm5,ALL,MUL3,MUL4,POW2,VL1,VL2,VL3,VL4,VL5,VL6,VL7,VL8,VL16,VL32,VL64,VL128,VL256]"><pattern></a>{, MUL #<a href="#sa_imm" title="Immediate multiplier [1-16], default 1 (field "imm4")"><imm></a>}}</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 64;
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
bits(5) pat = pattern;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(imm4) + 1;</p><h3 class="classheading"><a id="iclass_esize_halfword"/>Halfword</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr">1</td><td class="l">1</td><td class="r">0</td><td class="lr" colspan="4">imm4</td><td class="l">1</td><td>1</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="5">pattern</td><td class="lr" colspan="5">Rd</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td colspan="2"/><td colspan="4"/><td colspan="5"/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cnth_r_s_"/><p class="asm-code">CNTH <a href="#sa_xd" title="64-bit destination general-purpose register (field "Rd")"><Xd></a>{, <a href="#sa_pattern" title="Optional pattern specifier, default ALL (field "pattern") [#uimm5,ALL,MUL3,MUL4,POW2,VL1,VL2,VL3,VL4,VL5,VL6,VL7,VL8,VL16,VL32,VL64,VL128,VL256]"><pattern></a>{, MUL #<a href="#sa_imm" title="Immediate multiplier [1-16], default 1 (field "imm4")"><imm></a>}}</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 16;
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
bits(5) pat = pattern;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(imm4) + 1;</p><h3 class="classheading"><a id="iclass_esize_word"/>Word</h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">0</td><td class="l">1</td><td class="r">0</td><td class="lr" colspan="4">imm4</td><td class="l">1</td><td>1</td><td>1</td><td>0</td><td class="r">0</td><td class="lr">0</td><td class="lr" colspan="5">pattern</td><td class="lr" colspan="5">Rd</td></tr><tr class="secondrow"><td colspan="8"/><td class="droppedname">size<1></td><td class="droppedname">size<0></td><td colspan="2"/><td colspan="4"/><td colspan="5"/><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cntw_r_s_"/><p class="asm-code">CNTW <a href="#sa_xd" title="64-bit destination general-purpose register (field "Rd")"><Xd></a>{, <a href="#sa_pattern" title="Optional pattern specifier, default ALL (field "pattern") [#uimm5,ALL,MUL3,MUL4,POW2,VL1,VL2,VL3,VL4,VL5,VL6,VL7,VL8,VL16,VL32,VL64,VL128,VL256]"><pattern></a>{, MUL #<a href="#sa_imm" title="Immediate multiplier [1-16], default 1 (field "imm4")"><imm></a>}}</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 32;
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
bits(5) pat = pattern;
|
||||
integer imm = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(imm4) + 1;</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xd></td><td><a id="sa_xd"/><p class="aml">Is the 64-bit name of the destination general-purpose register, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><pattern></td><td><a id="sa_pattern"/><p>Is the optional pattern specifier, defaulting to ALL,
|
||||
encoded in
|
||||
<q>pattern</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">pattern</th><th class="symbol"><pattern></th></tr></thead><tbody><tr><td class="bitfield">00000</td><td class="symbol">POW2</td></tr><tr><td class="bitfield">00001</td><td class="symbol">VL1</td></tr><tr><td class="bitfield">00010</td><td class="symbol">VL2</td></tr><tr><td class="bitfield">00011</td><td class="symbol">VL3</td></tr><tr><td class="bitfield">00100</td><td class="symbol">VL4</td></tr><tr><td class="bitfield">00101</td><td class="symbol">VL5</td></tr><tr><td class="bitfield">00110</td><td class="symbol">VL6</td></tr><tr><td class="bitfield">00111</td><td class="symbol">VL7</td></tr><tr><td class="bitfield">01000</td><td class="symbol">VL8</td></tr><tr><td class="bitfield">01001</td><td class="symbol">VL16</td></tr><tr><td class="bitfield">01010</td><td class="symbol">VL32</td></tr><tr><td class="bitfield">01011</td><td class="symbol">VL64</td></tr><tr><td class="bitfield">01100</td><td class="symbol">VL128</td></tr><tr><td class="bitfield">01101</td><td class="symbol">VL256</td></tr><tr><td class="bitfield">0111x</td><td class="symbol">#uimm5</td></tr><tr><td class="bitfield">101x1</td><td class="symbol">#uimm5</td></tr><tr><td class="bitfield">10110</td><td class="symbol">#uimm5</td></tr><tr><td class="bitfield">1x0x1</td><td class="symbol">#uimm5</td></tr><tr><td class="bitfield">1x010</td><td class="symbol">#uimm5</td></tr><tr><td class="bitfield">1xx00</td><td class="symbol">#uimm5</td></tr><tr><td class="bitfield">11101</td><td class="symbol">MUL4</td></tr><tr><td class="bitfield">11110</td><td class="symbol">MUL3</td></tr><tr><td class="bitfield">11111</td><td class="symbol">ALL</td></tr></tbody></table></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><imm></td><td><a id="sa_imm"/><p class="aml">Is the immediate multiplier, in the range 1 to 16, defaulting to 1, encoded in the "imm4" field.</p></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
integer count = <a href="shared_pseudocode.html#impl-aarch64.DecodePredCount.2" title="function: integer DecodePredCount(bits(5) pattern, integer esize)">DecodePredCount</a>(pat, esize);
|
||||
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = (count * imm)<63:0>;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its registers.</li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
@@ -1,29 +0,0 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.1//EN" "http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml"><head><link href="insn.css" rel="stylesheet" type="text/css"/><meta content="iform.xsl" name="generator"/><title>CNTP (predicate)</title></head><body><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">CNTP (predicate)</h2><p>Set scalar to count of true predicate elements</p><p class="aml">Counts the number of active and true elements in the source predicate and places the scalar result in the destination general-purpose register. Inactive predicate elements are not counted.</p><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">0</td><td>0</td><td>1</td><td>0</td><td>0</td><td>1</td><td>0</td><td class="r">1</td><td class="lr" colspan="2">size</td><td class="l">1</td><td>0</td><td class="r">0</td><td class="l">0</td><td class="r">0</td><td class="lr">0</td><td class="l">1</td><td class="r">0</td><td class="lr" colspan="4">Pg</td><td class="lr">0</td><td class="lr" colspan="4">Pn</td><td class="lr" colspan="5">Rd</td></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="cntp_r_p_p_"/><p class="asm-code">CNTP <a href="#sa_xd" title="64-bit destination general-purpose register (field "Rd")"><Xd></a>, <a href="#sa_pg" title="Governing scalable predicate register (field "Pg")"><Pg></a>, <a href="#sa_pn" title="Source scalable predicate register (field "Pn")"><Pn></a>.<a href="#sa_t" title="Size specifier (field "size") [B,D,H,S]"><T></a></p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSVE.0" title="function: boolean HaveSVE()">HaveSVE</a>() && !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer d = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rd);</p><div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Xd></td><td><a id="sa_xd"/><p class="aml">Is the 64-bit name of the destination general-purpose register, encoded in the "Rd" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pg></td><td><a id="sa_pg"/><p class="aml">Is the name of the governing scalable predicate register, encoded in the "Pg" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><Pn></td><td><a id="sa_pn"/><p class="aml">Is the name of the source scalable predicate register, encoded in the "Pn" field.</p></td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td><T></td><td><a id="sa_t"/><p>Is the size specifier,
|
||||
encoded in
|
||||
<q>size</q>:
|
||||
</p><table class="valuetable"><thead><tr><th class="bitfield">size</th><th class="symbol"><T></th></tr></thead><tbody><tr><td class="bitfield">00</td><td class="symbol">B</td></tr><tr><td class="bitfield">01</td><td class="symbol">H</td></tr><tr><td class="bitfield">10</td><td class="symbol">S</td></tr><tr><td class="bitfield">11</td><td class="symbol">D</td></tr></tbody></table></td></tr></table></div><div class="syntax-notes"/><div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3><p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckSVEEnabled.0" title="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(PL) operand = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[n, PL];
|
||||
bits(64) sum = <a href="shared_pseudocode.html#impl-shared.Zeros.1" title="function: bits(N) Zeros(integer N)">Zeros</a>(64);
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) && <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(operand, e, esize) then
|
||||
sum = sum + 1;
|
||||
<a href="shared_pseudocode.html#impl-aarch64.X.write.2" title="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = sum;</p></div><h3>Operational information</h3><p class="aml">If FEAT_SVE2 is implemented or FEAT_SME is implemented, then <ins>if</ins><del>when</del> PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
|
||||
<ul><li>The values of the data supplied in any of its operand registers when its governing predicate register contains the same value for each execution.</li><li>The values of the NZCV flags.</li></ul></li></ul><p class="aml">If FEAT_SME is implemented and the PE is in Streaming SVE mode, then any subsequent instruction which is dependent on the general-purpose register written by this instruction might be significantly delayed.</p><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
|
||||
Internal version only: isa <ins>v33.59</ins><del>v33.53</del>, AdvSIMD <ins>v29.12</ins><del>v29.11</del>, pseudocode <ins>v2022-12_rel</ins><del>no_diffs_2022_12_RC1_0</del>, sve <ins>v2022-12_relb</ins><del>shoji_no_diff_2022_12_rc1</del>
|
||||
; Build timestamp: <ins>2022-12-14T22</ins><del>2022-11-21T13</del>:<ins>29</ins><del>57</del>
|
||||
</p><p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p><div align="center" class="htmldiff_header"><table><tbody><tr><td class="old">(old) </td><td class="explain">htmldiff from-</td><td class="new">(new) </td></tr></tbody></table></div></body></html>
|
||||
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Reference in New Issue
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