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docs: Massive redesign of ssa instructions
1. Turns `instruction_t` from a struct into a uint64_t. 2. Remove Global Flags. 3. Add `large_instruction_t` for situations where definition, source1, and source2 are greater than 14 bits. Signed-off-by: Ronald Caesar <github43132@proton.me>
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Ronald Caesar
@@ -98,6 +98,85 @@ typedef struct
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// A massive contiguous array storing all operands for all Phis.
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uint32_t phi_operand_pool[???];
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```
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## Instruction Encoding
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```text
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63 62 57 56 54 53 48 47 42 41 28 27 14 13 00
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| |----------| |-------| |----------| |--------| |----------| |----------| |----------|
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e cs wid TODO opc def src1 src2
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```
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### Encoding Symbols
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<**src2**> 14-bit index for `ssa_versions[]`.
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<**src1**> 14-bit index for `ssa_versions[]`.
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<**def**> 14-bit index for `ssa_versions[]`.
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<**opc**> Instruction opcode.
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<**TODO**> Still figuring out what to out here.
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<**wid**> Instruction width type:
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| Encoding | Mnemonic | Description |
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| :--- | :--- | :--- |
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| `000` | **DEF** | Default / Void / Context-implied width. |
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| `001` | **B** | Byte (8-bit integer). |
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| `010` | **H** | Half-word (16-bit integer). |
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| `011` | **W** | Word (32-bit integer / float). |
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| `100` | **X** | Double-word (64-bit integer / double). |
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| `101` | **Q** | Quad-word (128-bit SIMD vector). |
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| `110` | **PTR** | Object Reference / Pointer (GC tracked). |
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| `111` | - | *Reserved.* |
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<**cs**> Since `instruction_t` only support 2 args, this is for instructions where the 3rd arg is a constant:
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* Vector Element (`EXT`, `INS`, `DUP`)
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- Used for SIMD lane manipulation where the index must be an immediate.
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```text
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62 61 60 57
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|---| |---------|
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r imm
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```
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- <**imm**> Vector lane index (0-15).
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- <**r**> Reserved.
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* Branch and Compare (`B.cond`, `CSET`, `CSEL`)
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```text
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62 61 60 57
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|---| |---------|
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r imm
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```
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| Encoding | Mnemonic | Meaning |
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| :--- | :--- | :--- |
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| `0000` | **EQ** | Equal |
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| `0001` | **NE** | Not Equal |
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| `0010` | **CS / HS** | Carry Set / Unsigned Higher or Same |
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| `0011` | **CC / LO** | Carry Clear / Unsigned Lower |
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| TODO | TODO | TODO |
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| `1110` | **AL** | Always |
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<**e**> Set to 1 if `def`, `src1`, or `src2` is greater than 16383.
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### Operational Information
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If Flags.E is 1:
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* `instruction_t` is an index into `large_instructions[]`. We write the index into the 42-bit space.
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```text
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63 62 57 56 54 53 48 47 42 41 00
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| |----------| |-------| |----------| |--------| |------------------------------------|
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e cs wid TODO opc index
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```
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## Instruction Design
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@@ -117,24 +196,33 @@ uint32_t phi_operand_pool[???];
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// 30: c1 = a1 + b1;
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// instructions[30].source1 = original_variables[5].reaching_definition;
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// ---------------------------------------------------------
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// Instruction Bit Manipulation Macros
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// ---------------------------------------------------------
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// Layout: [Flags 16 | Op 6 | Def 14 | Src1 14 | Src2 14]
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#define IR_MASK_14 0x3FFF
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#define IR_MASK_6 0x3F
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#define IR_MASK_16 0xFFFF
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// Strict 8-byte alignment
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typedef struct
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{
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// 64 Opcodes
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unsigned int opcode: 6;
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// Encoders
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#define IR_ENCODE(flags, op, def, s1, s2) \
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( ((uint64_t)(flags) & IR_MASK_16) << 48 | \
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((uint64_t)(op) & IR_MASK_6) << 42 | \
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((uint64_t)(def) & IR_MASK_14) << 28 | \
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((uint64_t)(s1) & IR_MASK_14) << 14 | \
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((uint64_t)(s2) & IR_MASK_14) )
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// See Section `Instruction Flags Design` for encoding layout.
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uint16_t flags;
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// Decoders
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#define IR_GET_FLAGS(i) (((i) >> 48) & IR_MASK_16)
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#define IR_GET_OP(i) (((i) >> 42) & IR_MASK_6)
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#define IR_GET_DEF(i) (((i) >> 28) & IR_MASK_14)
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#define IR_GET_SRC1(i) (((i) >> 14) & IR_MASK_14)
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#define IR_GET_SRC2(i) ((i) & IR_MASK_14)
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// 0-16383
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unsigned int definition: 14;
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unsigned int source1: 14;
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unsigned int source2: 14;
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} instruction_t;
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typedef uint64_t instruction_t
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instruction_t instructions[???]; // High Density
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// Use when variables or constants > 16383
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typedef struct
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{
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uint32_t definition;
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@@ -143,131 +231,31 @@ typedef struct
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uint32_t _padding;
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} large_instruction_t
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instruction_t instructions[???]; // High Density
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large_instruction_t large_instructions[???]; // Low Density
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size_t large_instructions_count;
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// Extension Handling
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#define IR_GET_LARGE_INDEX(i) ((i) & 0xFFFFFFF) // 42 bits
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```
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## Instruction Flags Design
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### Layout Strategy
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```text
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15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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| |--------------| |------| |---------------|
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E Class Width Global Flags
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Specific
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```
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### 1. Global Flags Bit[5:0]
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These apply to *every* instruction type.
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1. `SIDE_EFFECT` Bit[0]
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Dont delete this instruction. Used for Dead Code Elimination.
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2. `COMMUTATIVE` Bit[1]
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Order doesn't matter. `ADD x, 5` == `ADD 5, x` Used for Global value numbering.
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3. `MAY_TRAP` Bit[2]
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Dont move the instruction aggressively. Set this for `DIV` (div by zero) and `LDR` (segfault). Used for Loop Invariant Code Motion.
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4. `READS_MEMORY` Bit[3]
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Instruction depends on the heap state.
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5. `TERMINATOR` Bit[4]
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Instruction ends the basic block.
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6. `SPILL` Bit[5]
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Instruction was created by the register allocator.
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### 2. Width Bit[8:6]
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Every instruction must set these bits accordingly.
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| Encoding | Mnemonic | Description |
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| :--- | :--- | :--- |
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| `000` | **DEF** | Default / Void / Context-implied width. |
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| `001` | **B** | Byte (8-bit integer). |
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| `010` | **H** | Half-word (16-bit integer). |
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| `011` | **W** | Word (32-bit integer / float). |
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| `100` | **X** | Double-word (64-bit integer / double). |
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| `101` | **Q** | Quad-word (128-bit SIMD vector). |
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| `110` | **PTR** | Object Reference / Pointer (GC tracked). |
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| `111` | - | *Reserved.* |
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### 3. Class-Specific Encodings Bit[14:9]
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We redefine these bits based on the Opcode.
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#### Shift and Rotate (`LSL`, `LSR`, `ASR`, `ROR`)
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Use when the shift amount is a compile-time constant.
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```text
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15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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| |--------------| |------| |---------------|
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E Shift Amount Width Global Flags
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```
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#### Vector Element (`EXT`, `INS`, `DUP`)
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Used for SIMD lane manipulation where the index must be an immediate.
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```text
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15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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| |---------| |------| |---------------|
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E Index Width Global Flags
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```
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<**Index**> Vector lane index (0-15).
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<**Width**> Must be set to `101` for 128-bit operations.
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#### Branch and Compare (`B.cond`, `CSET`, `CSEL`)
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Used for operations dependant on the PSTATE condition flags.
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```text
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15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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| |---------| |------| |---------------|
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E Condition Width Global Flags
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```
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| Encoding | Mnemonic | Meaning |
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| :--- | :--- | :--- |
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| `0000` | **EQ** | Equal |
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| `0001` | **NE** | Not Equal |
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| `0010` | **CS / HS** | Carry Set / Unsigned Higher or Same |
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| `0011` | **CC / LO** | Carry Clear / Unsigned Lower |
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| TODO | TODO | TODO |
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| `1110` | **AL** | Always |
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### 4. Extention Flag Bit[15]
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This is for constants and variables greater than 16383.
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### 5. Access Macros
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Direct bitwise manipulation of flags is discouraged outside of IR Builder. Use these macros instead:
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## How to use `instruction_t` to index into `large_instructions[]`.
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```c
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// Global Flags
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#define IS_SIDE_EFFECT(f) ((f) & 0x1)
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#define IS_COMMUTATIVE(f) ((f) & 0x2)
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#define IS_TRAPPING(f) ((f) & 0x4)
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// Width Extraction
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#define GET_WIDTH(f) (((f) >> 6) & 0x7)
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// Opcode Dependant Bits
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#define GET_SHIFT_VALUET(f) (((f) >> 9) & 0x3F)
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#define GET_LANE(f) (((f) >> 6) & 0xF)
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#define GET_COND(f) (((f) >> 6) & 0xF)
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// etc...
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// # Scenario
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//
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// 1. `large_instructions[]` is empty.
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// 2. Create a new instruction: `z1 = ADD v20000, v20000`.
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// 3. `20000` is larger than `16383`. We must use the large pool.
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//
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// We see our counter `large_instructions_count = 0`. We write the actual values
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// into the pool at index 0;
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//
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// ```
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// large_instructions[0].definition = 1;
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// large_instructions[0].source1 = 20000;
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// large_instructions[0].source2 = 20000;
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// ```
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//
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// Finally we encode `instruction_t`.
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//
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// 1. Bits[0:41] = large_instructions_count;
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// 2. Bits[47:42] = OPCODE_ADD
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// 4. Bits[63] = 1 << 63 // Enable the Extended Flag
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```
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