Bumped version to v0.3.2

[DYNAREC] Fixed a typo which leads to regression (#2121 )
[BOX32][WRAPPER] Cosmetic fix an a function signature
2026-11-08 17:39:19 -10:00 · 2024-12-06 15:59:59 +01:00 · 2024-12-06 15:21:23 +01:00 · 2024-12-06 14:48:41 +01:00 · 2024-12-06 13:29:20 +01:00 · 2024-12-06 10:40:02 +01:00
1812 changed files with 236294 additions and 40364 deletions
@@ -11,4 +11,8 @@ SortIncludes: false
 MaxEmptyLinesToKeep: 2
 IndentCaseLabels: true
 AlignConsecutiveMacros: true
+WhitespaceSensitiveMacros: ['QUOTE']
+IfMacros: ['IFX', 'IFXORNAT', 'IFX2', 'IFXA', 'IFX_PENDOR0', 'IFXX', 'IFX2X', 'IFXN', 'UFLAG_IF', 'PASS2IF']
+UseTab: Never
+IndentPPDirectives: None
 ---
@@ -49,7 +49,7 @@ jobs:
    runs-on: ubuntu-latest
    steps:
      - name: "Checkout Box64 Repository"
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4

      - name: "Environment preparation"
        run: |
@@ -90,7 +90,7 @@ jobs:
          make -j$(nproc) VERBOSE=1

      - name: "Upload Artifact"
-        uses: actions/upload-artifact@v2
+        uses: actions/upload-artifact@v4
        with:
          name: box64-${{ github.event.inputs.platform }}-${{ github.event.inputs.build_type }}
          path: build/box64
@@ -27,37 +27,63 @@ jobs:
    strategy:
      fail-fast: false
      matrix:
-        platform: [X64, OTHER_ARM, RISCV, RPI4ARM64, RPI5ARM64, RK3326, RK3399, RK3588, PHYTIUM, SD845, SD888, ADLINK, ARM64, ANDROID]
-        type: [Release, Trace]
+        platform: [X64, RISCV, RK3588, ARM64, ANDROID, TERMUX, LARCH64, ANDROID_GLIBC]
+        type: [Release, Trace, StaticBuild, Box32]
        os: [ubuntu-latest]
-        include:
-          - platform: TEGRAX1
-            type: Release
-            os: ubuntu-20.04
-          - platform: TEGRAX1
-            type: Trace
-            os: ubuntu-20.04
+        exclude:
+          - platform: ANDROID
+            type: StaticBuild
+          - platform: TERMUX
+            type: StaticBuild
+          - platform: X64
+            type: StaticBuild
+          - platform: ANDROID
+            type: Box32
+          - platform: TERMUX
+            type: Box32

    runs-on: ${{ matrix.os }}
    steps:
      - name: "Checkout Box64 Repository"
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4

      - name: "Environment preparation"
        run: |
          sudo apt-get update
-          if [[ ${{ matrix.platform }} != 'X64' && ${{ matrix.platform }} != 'OTHER_ARM' && ${{ matrix.platform }} != 'RISCV' ]]; then
-            sudo apt-get -y install git cmake make python3
-            if [[ ${{ matrix.platform }} == 'ANDROID' ]]; then
-              wget https://dl.google.com/android/repository/android-ndk-r23b-linux.zip
-              unzip android-ndk-r23b-linux.zip
-              echo "BOX64_COMPILER=$PWD/android-ndk-r23b/toolchains/llvm/prebuilt/linux-x86_64/bin/aarch64-linux-android31-clang" >> $GITHUB_ENV
-              echo "BOX64_PLATFORM_MARCRO=-DANDROID=1 -DARM_DYNAREC=1 -DNOLOADADDR=1" >> $GITHUB_ENV
+          if [[ ${{ matrix.platform }} != 'X64' && ${{ matrix.platform }} != 'RISCV' && ${{ matrix.platform }} != 'LARCH64' ]]; then
+            sudo apt-get -y install git cmake make python3 patchelf
+            if [[ ${{ matrix.platform }} == 'ANDROID' || ${{ matrix.platform }} == 'TERMUX' ]]; then
+              wget https://dl.google.com/android/repository/android-ndk-r26b-linux.zip
+              unzip android-ndk-r26b-linux.zip
+              echo "BOX64_COMPILER=$PWD/android-ndk-r26b/toolchains/llvm/prebuilt/linux-x86_64/bin/aarch64-linux-android31-clang" >> $GITHUB_ENV
+              echo "BOX64_PLATFORM_MARCRO=-DANDROID=1 -DARM_DYNAREC=1 -DBAD_SIGNAL=1" >> $GITHUB_ENV
+              git clone https://github.com/termux/termux-docker.git
+              sudo cp -rf termux-docker/system/arm /system
+              sudo chown -R $(whoami):$(whoami) /system
+              sudo chmod 755 -R /system
+            elif [[ ${{ matrix.platform }} == 'ANDROID_GLIBC' ]]; then
+              sudo apt-get -y install git gcc-aarch64-linux-gnu
+              echo "BOX64_PLATFORM_MARCRO=-DARM64=1 -DARM_DYNAREC=1 -DBAD_SIGNAL=1" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=aarch64-linux-gnu-gcc" >> $GITHUB_ENV
            else
              sudo apt-get -y install git gcc-aarch64-linux-gnu
              echo "BOX64_PLATFORM_MARCRO=-D${{ matrix.platform }}=1" >> $GITHUB_ENV
              echo "BOX64_COMPILER=aarch64-linux-gnu-gcc" >> $GITHUB_ENV
            fi
+            if [[ ${{ matrix.platform }} == 'TERMUX' ]]; then
+              sudo apt-get -y install p7zip
+              wget https://mirrors.utermux.dev/termux/termux-main/pool/main/liba/libandroid-sysv-semaphore/libandroid-sysv-semaphore_0.1_aarch64.deb
+              7z x libandroid-sysv-semaphore_0.1_aarch64.deb
+              tar -xf data.tar.xz
+              sudo cp -rf data /
+              sudo chmod 755 -R /data
+              sudo chown -R $(whoami):$(whoami) /data
+              echo "CFLAGS=-L/data/data/com.termux/files/usr/lib" >> $GITHUB_ENV
+              echo "IS_TERMUX=1" >> $GITHUB_ENV
+              echo "QEMU_SET_ENV=LD_LIBRARY_PATH=/data/data/com.termux/files/usr/lib" >> $GITHUB_ENV
+            else
+              echo "IS_TERMUX=0" >> $GITHUB_ENV
+            fi
          else
            if [[ ${{ matrix.platform }} == 'X64' ]]; then
              echo "BOX64_PLATFORM_MARCRO=-DLD80BITS=1 -DNOALIGN=1" >> $GITHUB_ENV
@@ -66,7 +92,22 @@ jobs:
            elif [[ ${{ matrix.platform }} == 'RISCV' ]]; then
              echo BOX64_PLATFORM_MARCRO="-DRV64=ON" >> $GITHUB_ENV
              echo "BOX64_COMPILER=riscv64-linux-gnu-gcc" >> $GITHUB_ENV
-              sudo apt-get -y install git gcc-riscv64-linux-gnu cmake make python3
+              sudo apt-get -y install git gcc-riscv64-linux-gnu cmake make python3 ninja-build
+            elif [[ ${{ matrix.platform }} == 'LARCH64' ]]; then
+              sudo mkdir /usr/local/larch
+              wget -O- -q https://github.com/loongson/build-tools/releases/download/2023.08.08/CLFS-loongarch64-8.1-x86_64-cross-tools-gcc-glibc.tar.xz | sudo tar -C /usr/local/larch --strip-components=1 --xz -xf -
+              sudo ln -sf /usr/local/larch/target /usr/loongarch64-linux-gnu
+              sudo cp -r /usr/local/larch/loongarch64-unknown-linux-gnu/lib/* /usr/loongarch64-linux-gnu/lib64/
+              for i in objdump objcopy strip; do
+                sudo ln -sf /usr/local/larch/bin/loongarch64-unknown-linux-gnu-$i /usr/bin/loongarch64-linux-gnu-$i
+              done
+              echo '/usr/local/larch/bin/loongarch64-unknown-linux-gnu-gcc -L/usr/local/larch/loongarch64-unknown-linux-gnu "$@"' | sudo tee /usr/bin/loongarch64-linux-gnu-gcc
+              echo '/usr/local/larch/bin/loongarch64-unknown-linux-gnu-g++ -L/usr/local/larch/loongarch64-unknown-linux-gnu "$@"' | sudo tee /usr/bin/loongarch64-linux-gnu-g++
+              sudo chmod 755 /usr/bin/loongarch64-linux-gnu-{gcc,g++}
+
+              echo BOX64_PLATFORM_MARCRO="-DLARCH64=ON" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=loongarch64-linux-gnu-gcc" >> $GITHUB_ENV
+              sudo apt-get -y install git cmake make python3
            else
              echo BOX64_PLATFORM_MARCRO="-DARM_DYNAREC=ON" >> $GITHUB_ENV
              echo "BOX64_COMPILER=aarch64-linux-gnu-gcc" >> $GITHUB_ENV
@@ -76,57 +117,175 @@ jobs:
          if [[ ${{ matrix.type }} == 'Release' ]]; then
            echo BOX64_BUILD_TYPE=Release >> $GITHUB_ENV
            echo BOX64_HAVE_TRACE=0 >> $GITHUB_ENV
+            echo BOX64_STATICBUILD=0 >> $GITHUB_ENV
+            echo BOX64_BOX32=0 >> $GITHUB_ENV
+          elif [[ ${{ matrix.type }} == 'StaticBuild' ]]; then
+            echo BOX64_BUILD_TYPE=Release >> $GITHUB_ENV
+            echo BOX64_HAVE_TRACE=0 >> $GITHUB_ENV
+            echo BOX64_STATICBUILD=1 >> $GITHUB_ENV
+            echo BOX64_BOX32=0 >> $GITHUB_ENV
+          elif [[ ${{ matrix.type }} == 'Box32' ]]; then
+            echo BOX64_BUILD_TYPE=Release >> $GITHUB_ENV
+            echo BOX64_HAVE_TRACE=0 >> $GITHUB_ENV
+            echo BOX64_STATICBUILD=0 >> $GITHUB_ENV
+            echo BOX64_BOX32=1 >> $GITHUB_ENV
          else
            echo BOX64_BUILD_TYPE=RelWithDebInfo >> $GITHUB_ENV
            echo BOX64_HAVE_TRACE=1 >> $GITHUB_ENV
+            echo BOX64_STATICBUILD=0 >> $GITHUB_ENV
+            echo BOX64_BOX32=0 >> $GITHUB_ENV
          fi

+      - name: "Get XuanTie QEMU Cache Key"
+        if: matrix.platform == 'RISCV'
+        id: get-xuantie-qemu-cache-key
+        run: |
+          echo "key=f2dfdd13014d51f957c7172acc2e791cb42dc400" >> $GITHUB_OUTPUT
+
+      - name: "Cache XuanTie QEMU"
+        if: matrix.platform == 'RISCV'
+        id: cache-xuantie-qemu
+        uses: actions/cache@v3
+        with:
+          path: ${{ github.workspace }}/xuantie_qemu_install
+          key: ${{ runner.os }}-${{ steps.get-xuantie-qemu-cache-key.outputs.key }}-xuantie-qemu
+
+      - name: "Checkout XuanTie QEMU"
+        if: matrix.platform == 'RISCV' && steps.cache-xuantie-qemu.outputs.cache-hit != 'true'
+        uses: actions/checkout@v3
+        with:
+          repository: revyos/qemu
+          path: xuantie_qemu
+          ref: f2dfdd13014d51f957c7172acc2e791cb42dc400
+
+      - name: "Build XuanTie QEMU for XTheadVector"
+        if: matrix.platform == 'RISCV' && steps.cache-xuantie-qemu.outputs.cache-hit != 'true'
+        run: |
+          cd xuantie_qemu
+          ./configure --prefix=$GITHUB_WORKSPACE/xuantie_qemu_install --target-list=riscv64-linux-user --disable-system
+          make -j$(nproc)
+          make install
+
      - name: "Display Build info"
        run: |
          echo "CMake Platform Macro: ${{ env.BOX64_PLATFORM_MARCRO }}"
          echo "CMake C Compiler: ${{ env.BOX64_COMPILER }}"
          echo "Build type: ${{ env.BOX64_BUILD_TYPE }}"
          echo "Trace Enabled: ${{ env.BOX64_HAVE_TRACE }}"
+          echo "StaticBuild Enabled: ${{ env.BOX64_STATICBUILD }}"
+          echo "Box32 Enabled: ${{ env.BOX64_BOX32 }}"

      - name: "Build Box64"
        run: |
          mkdir build
          cd build
          cmake .. -DCMAKE_C_COMPILER=${{ env.BOX64_COMPILER }}\
+                   -DTERMUX=${{ env.IS_TERMUX }}\
                   ${{ env.BOX64_PLATFORM_MARCRO }}\
                   -DCMAKE_BUILD_TYPE=${{ env.BOX64_BUILD_TYPE }}\
                   -DHAVE_TRACE=${{ env.BOX64_HAVE_TRACE }}\
+                   -DSTATICBUILD=${{ env.BOX64_STATICBUILD }}\
+                   -DBOX32=${{ env.BOX64_BOX32 }}\
                   -DCMAKE_VERBOSE_MAKEFILE:BOOL=ON\
                   -DCI=${{ matrix.platform != 'ANDROID' }}
          make -j$(nproc) VERBOSE=1

      - name: "Test Box64"
-        if: ${{ matrix.platform != 'TEGRAX1' }}
        run: |
-          if [[ ${{ matrix.platform }} != 'X64' && ${{ matrix.platform }} != 'ANDROID' ]]; then
-            mkdir qemu8.1.0
-            wget -O- -q https://archive.archlinux.org/packages/q/qemu-user-static/qemu-user-static-8.1.0-2-x86_64.pkg.tar.zst | tar -I zstd -C qemu8.1.0 -xf -
-            sudo cp qemu8.1.0/usr/bin/* /usr/bin/
+          if [[ ${{ matrix.platform }} != 'X64' ]]; then
+            mkdir qemu9
+            wget -O- -q https://archive.archlinux.org/packages/q/qemu-user-static/qemu-user-static-9.0.2-1-x86_64.pkg.tar.zst | tar -I zstd -C qemu9 -xf -
+            sudo cp qemu9/usr/bin/* /usr/bin/
          fi

          cd build
+          export CTEST_OPTIONS="-j$(nproc) --timeout 120 --output-on-failure --repeat until-pass:20"
          if [[ ${{ matrix.platform }} == 'RISCV' ]]; then
-            INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ ctest -j$(nproc) --rerun-failed --output-on-failure
-            INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ BOX64_DYNAREC=0 ctest -j$(nproc) --rerun-failed --output-on-failure
-            INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,zba=true,zbb=true,zbc=true,zbs=true ctest -j$(nproc) --rerun-failed --output-on-failure
-            INTERPRETER=qemu-riscv64-static QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ QEMU_CPU=rv64,xtheadba=true,xtheadba=true,xtheadbb=true,xtheadbs=true,xtheadcondmov=true,xtheadmemidx=true,xtheadmempair=true,xtheadfmemidx=true,xtheadmac=true,xtheadfmv=true ctest -j$(nproc) --rerun-failed --output-on-failure
-          elif [[ ${{ matrix.platform }} != 'X64' && ${{ matrix.platform }} != 'ANDROID' ]]; then # AArch64
-            INTERPRETER=qemu-aarch64-static QEMU_LD_PREFIX=/usr/aarch64-linux-gnu/ BOX64_DYNAREC=0 ctest -j$(nproc) --rerun-failed --output-on-failure
-            INTERPRETER=qemu-aarch64-static QEMU_LD_PREFIX=/usr/aarch64-linux-gnu/ ctest -j$(nproc) --rerun-failed --output-on-failure
+            export INTERPRETER=qemu-riscv64-static
+            export QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/
+
+            ctest $CTEST_OPTIONS
+            QEMU_CPU=rv64,v=false BOX64_DYNAREC=0 ctest $CTEST_OPTIONS
+            QEMU_CPU=rv64,v=false,zba=true,zbb=true,zbc=true,zbs=true ctest $CTEST_OPTIONS
+            QEMU_CPU=rv64,v=true,vlen=128,vext_spec=v1.0 ctest $CTEST_OPTIONS
+            QEMU_CPU=rv64,v=true,vlen=256,vext_spec=v1.0 ctest $CTEST_OPTIONS
+            QEMU_CPU=thead-c906 ctest $CTEST_OPTIONS
+
+            BOX64_DYNAREC_TEST=1 ctest $CTEST_OPTIONS -E nocosim
+            BOX64_DYNAREC_TEST=1 QEMU_CPU=rv64,v=false,zba=true,zbb=true,zbc=true,zbs=true ctest $CTEST_OPTIONS -E nocosim
+            BOX64_DYNAREC_TEST=1 QEMU_CPU=rv64,v=true,vlen=128,vext_spec=v1.0 ctest $CTEST_OPTIONS -E nocosim
+            BOX64_DYNAREC_TEST=1 QEMU_CPU=rv64,v=true,vlen=256,vext_spec=v1.0 ctest $CTEST_OPTIONS -E nocosim
+            BOX64_DYNAREC_TEST=1 QEMU_CPU=thead-c906 ctest $CTEST_OPTIONS -E nocosim
+
+            export INTERPRETER=$GITHUB_WORKSPACE/xuantie_qemu_install/bin/qemu-riscv64
+            QEMU_CPU=c910v ctest $CTEST_OPTIONS
+            BOX64_DYNAREC_TEST=1 QEMU_CPU=c910v ctest $CTEST_OPTIONS -E nocosim
+          elif [[ ${{ matrix.platform }} == 'LARCH64' ]]; then
+            export INTERPRETER=qemu-loongarch64-static
+            export QEMU_LD_PREFIX=/usr/loongarch64-linux-gnu/
+
+            BOX64_DYNAREC_LA64NOEXT=1 ctest $CTEST_OPTIONS -E nocosim
+            BOX64_DYNAREC=0 ctest $CTEST_OPTIONS -E nocosim
+
+            BOX64_DYNAREC_TEST=1 BOX64_DYNAREC_LA64NOEXT=1 ctest $CTEST_OPTIONS -E nocosim
          elif [[ ${{ matrix.platform }} == 'ANDROID' ]]; then
-            true
+            export INTERPRETER=qemu-aarch64-static
+            export QEMU_LD_PREFIX=/system/lib64
+            
+            BOX64_DYNAREC=0 ctest $CTEST_OPTIONS
+            ctest $CTEST_OPTIONS
+          elif [[ ${{ matrix.platform }} == 'TERMUX' ]]; then
+            export INTERPRETER=qemu-aarch64-static
+            export QEMU_SET_ENV=LD_LIBRARY_PATH=/data/data/com.termux/files/usr/lib 
+            export QEMU_LD_PREFIX=/system/lib64:/data/data/com.termux/files/usr/lib
+
+            BOX64_DYNAREC=0 ctest $CTEST_OPTIONS
+            ctest $CTEST_OPTIONS
+          elif [[ ${{ matrix.platform }} != 'X64' ]]; then # AArch64
+            export INTERPRETER=qemu-aarch64-static
+            export QEMU_LD_PREFIX=/usr/aarch64-linux-gnu/
+            
+            BOX64_DYNAREC=0 ctest $CTEST_OPTIONS
+            ctest $CTEST_OPTIONS
+            BOX64_DYNAREC_TEST=1 ctest $CTEST_OPTIONS -E nocosim
          else
-            BOX64_DYNAREC=0 ctest -j$(nproc) --rerun-failed --output-on-failure
-            ctest -j$(nproc) --rerun-failed --output-on-failure
+            ctest -j$(nproc)
          fi

+      - name: "Get short Git commit"
+        id: git-info
+        run: echo "SHORT_COMMIT=$(git rev-parse --short HEAD)" >> $GITHUB_ENV
+
+      - name: "Packaging WCP file for Winlator"
+        if: matrix.platform == 'ANDROID_GLIBC' && matrix.type != 'StaticBuild'
+        run: |
+          cd build
+          cat <<EOF > profile.json
+          {
+            "type": "Box64",
+            "versionName": "latest-${SHORT_COMMIT}",
+            "versionCode": 1,
+            "description": "Box64-latest-${SHORT_COMMIT}. Built from [https://github.com/ptitSeb/box64].",
+            "files": [
+              {
+                "source": "box64",
+                "target": "\${localbin}/box64"
+              }
+            ]
+          }
+          EOF
+          patchelf --set-interpreter /data/data/com.winlator/files/imagefs/usr/lib/ld-linux-aarch64.so.1 ./box64
+          tar --zstd -cf box64-latest.wcp box64 profile.json
+
      - name: "Upload Artifact"
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
        with:
          name: box64-${{ matrix.platform }}-${{ matrix.type }}
          path: build/box64
+
+      - name: "Upload WCP file"
+        if: matrix.platform == 'ANDROID_GLIBC' && matrix.type != 'StaticBuild'
+        uses: actions/upload-artifact@v4
+        with:
+          name: box64-latest-${{ matrix.type }}-wcp
+          path: build/box64-latest.wcp
@@ -60,11 +60,16 @@ build*/
 src/git_head.h
 backup/

-# LLVMprivateGenerator
-/LLVMprivateGenerator/*
-!/LLVMprivateGenerator/Makefile
-!/LLVMprivateGenerator/main.cpp
-!/LLVMprivateGenerator/registered_structs.cpp
+# Wrapper helper
+/wrapperhelper/bin
+/wrapperhelper/makedir
+/wrapperhelper/obj
+/wrapperhelper/sanaddress
+/wrapperhelper/sanleak
+/wrapperhelper/sanundefined
+/wrapperhelper/src/machine.gen
+/wrapperhelper/*.h
+!/wrapperhelper/example-libc.h

 # macOS
 .DS_Store
@@ -1,12 +0,0 @@
-all: dumpSigs
-
-dumpSigs: main.o registered_structs.o
-	g++ -g3 -std=gnu++17 -fno-rtti main.o registered_structs.o -o dumpSigs "-L$(LLVM_install_dir)/lib" -lclang-cpp -lclangTooling -Wl,-rpath "-Wl,$(LLVM_install_dir)/lib"
-
-main.o: main.cpp
-	g++ -g3 -std=gnu++17 -fno-rtti -c main.cpp -Wfatal-errors "-I$(LLVM_install_dir)/include" -o main.o
-registered_structs.o: registered_structs.cpp
-	g++ -g3 -std=gnu++17 -fno-rtti -c registered_structs.cpp -Wfatal-errors -o registered_structs.o
-
-clean:
-	$(RM) dumpSigs main.o registered_structs.o
@@ -1,458 +0,0 @@
-#include <algorithm>
-#include <fstream>
-#include <iostream>
-#include <numeric>
-#include <unordered_map>
-#include <utility>
-#include <vector>
-
-#include <llvm/Support/raw_ostream.h>
-#include <clang/AST/ASTConsumer.h>
-#include <clang/AST/Decl.h>
-#include <clang/AST/Mangle.h>
-#include <clang/AST/PrettyPrinter.h>
-#include <clang/AST/RecursiveASTVisitor.h>
-#include <clang/Frontend/CompilerInstance.h>
-#include <clang/Frontend/FrontendActions.h>
-#include <clang/Tooling/CommonOptionsParser.h>
-#include <clang/Tooling/Tooling.h>
-
-clang::MangleContext *mangler = nullptr;
-
-std::unordered_map<std::string, std::pair<std::string, bool>> funMap;
-std::vector<std::string> funList;
-
-bool isTypeTrivial(const clang::QualType &q, const clang::QualType *qorig);
-clang::QualType getPointedType(const clang::QualType q) {
-	if (const clang::PointerType *p = q->getAs<clang::PointerType>())
-		return getPointedType(p->getPointeeType());
-	else if (const clang::ReferenceType *r = q->getAs<clang::ReferenceType>())
-		return getPointedType(r->getPointeeType());
-	else
-		return q;
-}
-
-std::string record2name(const clang::RecordDecl &q, const clang::QualType *qorig) {
-	std::string s = q.getNameAsString();
-	if (s == "") {
-		if (!qorig) return "????.!";
-		if (const clang::TypedefType *tt = (*qorig)->getAs<clang::TypedefType>()) {
-			// Typedef
-			if (clang::TypedefNameDecl *td = tt->getDecl()) {
-				return td->getNameAsString();
-			} else {
-				return "<typedef with no declaration>";
-			}
-		} else {
-			return std::string("<unknown type ") + (*qorig)->getTypeClassName() + ">";
-		}
-	} else {
-		return s;
-	}
-}
-
-char ptr2char(const std::string &str) __attribute__((const));
-const char *ptr2str(const std::string &str) __attribute__((const));
-char type2char(const clang::QualType &qual /* Canonical */, const clang::QualType *qorig) {
-	if (qual->isBuiltinType()) {
-		switch (static_cast<const clang::BuiltinType&>(*qual).getKind()) {
-		case clang::BuiltinType::Kind::Void:
-			return 'v';
-		case clang::BuiltinType::Kind::Bool:
-			return 'i';
-		case clang::BuiltinType::Kind::Char_U:
-			return 'C';
-		case clang::BuiltinType::Kind::Char_S:
-			return 'c';
-		case clang::BuiltinType::Kind::Char8:
-			return 'c';
-		case clang::BuiltinType::Kind::UChar:
-			return 'C';
-		case clang::BuiltinType::Kind::SChar:
-			return 'c';
-		case clang::BuiltinType::Kind::WChar_U:
-			return 'W';
-		case clang::BuiltinType::Kind::UShort:
-			return 'W';
-		case clang::BuiltinType::Kind::WChar_S:
-			return 'w';
-		case clang::BuiltinType::Kind::Char16:
-			return 'w';
-		case clang::BuiltinType::Kind::Short:
-			return 'w';
-		case clang::BuiltinType::Kind::UInt:
-			return 'u';
-		case clang::BuiltinType::Kind::Char32:
-			return 'i';
-		case clang::BuiltinType::Kind::Int:
-			return 'i';
-		case clang::BuiltinType::Kind::ULong:
-			return 'L';
-		case clang::BuiltinType::Kind::Long:
-			return 'l';
-		case clang::BuiltinType::Kind::ULongLong:
-			return 'U';
-		case clang::BuiltinType::Kind::LongLong:
-			return 'I';
-		case clang::BuiltinType::Kind::UInt128:
-			return 'H';
-		case clang::BuiltinType::Kind::Int128:
-			return 'H';
-		case clang::BuiltinType::Kind::Float:
-			return 'f';
-		case clang::BuiltinType::Kind::Double:
-			return 'd';
-		case clang::BuiltinType::Kind::LongDouble:
-			return 'D';
-		case clang::BuiltinType::Kind::NullPtr:
-			return 'p'; // nullptr_t
-		
-		case clang::BuiltinType::Kind::Half:
-		case clang::BuiltinType::Kind::BFloat16:
-		case clang::BuiltinType::Kind::ShortAccum:
-		case clang::BuiltinType::Kind::Accum:
-		case clang::BuiltinType::Kind::LongAccum:
-		case clang::BuiltinType::Kind::UShortAccum:
-		case clang::BuiltinType::Kind::UAccum:
-		case clang::BuiltinType::Kind::ULongAccum:
-		case clang::BuiltinType::Kind::ShortFract:
-		case clang::BuiltinType::Kind::Fract:
-		case clang::BuiltinType::Kind::LongFract:
-		case clang::BuiltinType::Kind::UShortFract:
-		case clang::BuiltinType::Kind::UFract:
-		case clang::BuiltinType::Kind::ULongFract:
-		case clang::BuiltinType::Kind::SatShortAccum:
-		case clang::BuiltinType::Kind::SatAccum:
-		case clang::BuiltinType::Kind::SatLongAccum:
-		case clang::BuiltinType::Kind::SatUShortAccum:
-		case clang::BuiltinType::Kind::SatUAccum:
-		case clang::BuiltinType::Kind::SatULongAccum:
-		case clang::BuiltinType::Kind::SatShortFract:
-		case clang::BuiltinType::Kind::SatFract:
-		case clang::BuiltinType::Kind::SatLongFract:
-		case clang::BuiltinType::Kind::SatUShortFract:
-		case clang::BuiltinType::Kind::SatUFract:
-		case clang::BuiltinType::Kind::SatULongFract:
-		case clang::BuiltinType::Kind::Float16:
-		case clang::BuiltinType::Kind::Float128:
-		case clang::BuiltinType::Kind::Overload:
-		case clang::BuiltinType::Kind::BoundMember:
-		case clang::BuiltinType::Kind::PseudoObject:
-		case clang::BuiltinType::Kind::Dependent:
-		case clang::BuiltinType::Kind::UnknownAny:
-		case clang::BuiltinType::Kind::ARCUnbridgedCast:
-		case clang::BuiltinType::Kind::BuiltinFn:
-		case clang::BuiltinType::Kind::ObjCId:
-		case clang::BuiltinType::Kind::ObjCClass:
-		case clang::BuiltinType::Kind::ObjCSel:
-#define IMAGE_TYPE(it, id, si, a, s) case clang::BuiltinType::Kind::id:
-#include <clang/Basic/OpenCLImageTypes.def>
-#undef IMAGE_TYPE
-		case clang::BuiltinType::Kind::OCLSampler:
-		case clang::BuiltinType::Kind::OCLEvent:
-		case clang::BuiltinType::Kind::OCLClkEvent:
-		case clang::BuiltinType::Kind::OCLQueue:
-		case clang::BuiltinType::Kind::OCLReserveID:
-		case clang::BuiltinType::Kind::IncompleteMatrixIdx:
-		case clang::BuiltinType::Kind::OMPArraySection:
-		case clang::BuiltinType::Kind::OMPArrayShaping:
-		case clang::BuiltinType::Kind::OMPIterator:
-#define EXT_OPAQUE_TYPE(et, id, e) case clang::BuiltinType::Kind::id:
-#include <clang/Basic/OpenCLExtensionTypes.def>
-#define SVE_TYPE(n, id, si) case clang::BuiltinType::Kind::id:
-#include <clang/Basic/AArch64SVEACLETypes.def>
-#define PPC_VECTOR_TYPE(n, id, s) case clang::BuiltinType::Kind::id:
-#include <clang/Basic/PPCTypes.def>
-#undef EXT_OPAQUE_TYPE
-#undef SVE_TYPE
-#undef PPC_VECTOR_TYPE
-			return '!';
-		default:
-			return ':';
-		}
-	} else if (qual->isEnumeralType()) {
-		const clang::EnumDecl *ed = qual->getAs<clang::EnumType>()->getDecl();
-		if (!ed) {
-			return 'i';
-		} else {
-			return type2char(ed->getIntegerType().getCanonicalType(), qorig);
-		}
-	} else if (qual->isFunctionPointerType()) {
-		return '@';
-	} else if (qual->isAnyPointerType() || qual->isReferenceType()) {
-		const clang::QualType &pointed = getPointedType(qual);
-		if (isTypeTrivial(pointed, qorig)) {
-			return 'p';
-		} else if (const clang::RecordType *rct = pointed->getAs<clang::RecordType>()) {
-			clang::RecordDecl *rc = rct->getDecl();
-			if (!rc) {
-				return '!';
-			} else if (!rc->isCompleteDefinition()) {
-				return 'p';
-			} else {
-				std::string str;
-				if (qorig) {
-					const clang::QualType qpted = getPointedType(*qorig);
-					str = record2name(*rc, &qpted);
-				} else {
-					str = record2name(*rc, nullptr);
-				}
-				char ret = ptr2char(str);
-				if (ret) return ret;
-				else {
-					return '!';
-				}
-			}
-		} else {
-			return '!';
-		}
-	} else if (const clang::RecordType *rct = qual->getAs<clang::RecordType>()) {
-		clang::RecordDecl *rc = rct->getDecl();
-		if (!rc) {
-			return '?';
-		} else if (rc->getNameAsString() == "__builtin_va_list") {
-			// va_list
-			return 'A';
-		} else {
-			return '?';
-		}
-	} else {
-		return '?';
-	}
-}
-bool isTypeTrivial(const clang::QualType &q, const clang::QualType *qorig) {
-	const char c = type2char(q, qorig);
-#define GO(chr) || (c == chr)
-	return (c == 'v')
-		GO('i') GO('u')
-		GO('I') GO('U')
-		GO('l') GO('L')
-		GO('f') GO('d')
-		GO('D') GO('K')
-		GO('0') GO('1')
-		GO('C') GO('c')
-		GO('W') GO('w')
-		GO('H')
-		GO('p');
-#undef GO
-}
-bool isTypeValid(const clang::QualType &q, const clang::QualType *qorig) {
-	const char c = type2char(q, qorig);
-	if (c == 'A') return false;
-	if (c == 'V') return false;
-	return ((c >= '0') && (c <= '9')) || ((c >= 'A') && (c <= 'Z')) || ((c >= 'a') && (c <= 'z'));
-}
-
-const std::string type2string(const clang::QualType &qual, const clang::QualType *qorig) {
-	if (qual->isBuiltinType()) {
-		return std::string("(builtin) ") + static_cast<const clang::BuiltinType&>(*qual).getName(clang::PrintingPolicy{{}}).data();
-	} else if (qual->isFunctionPointerType()) {
-		return "Callback (function pointer)";
-	} else if (qual->isAnyPointerType() || qual->isReferenceType()) {
-		std::string prefix = qual->isAnyPointerType() ? "Pointer to " : "Reference to ";
-		const clang::QualType &pointed = getPointedType(qual);
-		if (isTypeTrivial(pointed, qorig)) {
-			return prefix + "trivial object " + type2string(pointed, qorig) + " (" + type2char(pointed, qorig) + ")";
-		} else if (const clang::RecordType *rct = pointed->getAs<clang::RecordType>()) {
-			clang::RecordDecl *rc = rct->getDecl();
-			if (!rc) {
-				return prefix + "unknown record";
-			} else if (!rc->isCompleteDefinition()) {
-				return prefix + "incomplete record " + rc->getNameAsString();
-			} else {
-				std::string str;
-				if (qorig) {
-					const clang::QualType qpted = getPointedType(*qorig);
-					str = record2name(*rc, &qpted);
-				} else {
-					str = record2name(*rc, nullptr);
-				}
-				const char *ret = ptr2str(str);
-				if (ret[0] != '\0') {
-					return prefix + ret;
-				} else {
-					if (mangler && mangler->shouldMangleDeclName(rc)) {
-						std::string mangled;
-						{
-							llvm::raw_string_ostream strstr{mangled};
-							mangler->mangleName(rc, strstr);
-						}
-						return prefix + "unknown record " + str + " (=== " + mangled + ")";
-					} else {
-						return prefix + "unknown record " + str;
-					}
-				}
-			}
-		} else {
-			return prefix + "non-trivial or typedef'ed object " + type2string(pointed, qorig) + " (" + type2char(pointed, qorig) + ")";
-			//return "Pointer (maybe to callback)";
-		}
-	} else if (qual->isEnumeralType()) {
-		const clang::EnumDecl *ed = qual->getAs<clang::EnumType>()->getDecl();
-		if (!ed) {
-			return "Enumeration with unknown underlying integer type (assuming int)";
-		} else {
-			return "Enumeration with underlying type " + type2string(ed->getIntegerType().getCanonicalType(), nullptr);
-		}
-	} else if (const clang::RecordType *rct = qual->getAs<clang::RecordType>()) {
-		clang::RecordDecl *rc = rct->getDecl();
-		if (!rc) {
-			return "Unknown record";
-		} else if (rc->getNameAsString() == "__builtin_va_list") {
-			return "va_list";
-		} else {
-			return "Unknown record " + std::string(rc->getName().data());
-		}
-	} else {
-		return std::string("??? ") + qual->getTypeClassName();
-	}
-}
-
-class Visitor : public clang::RecursiveASTVisitor<Visitor> {
-public:
-	clang::ASTContext &context;
-	
-	bool shouldVisitTemplateInstantiations() const /* override */ { return true; }
-	
-	Visitor(clang::CompilerInstance &ci) : context(ci.getASTContext()) {
-		if (!mangler) {
-			mangler = clang::ItaniumMangleContext::create(context, ci.getDiagnostics());
-		}
-	}
-	
-	~Visitor() {
-		if (mangler) {
-			delete mangler;
-			mangler = nullptr;
-		}
-	}
-	
-	bool VisitDecl(clang::Decl *decl) /* override */ {
-		std::cerr << std::flush;
-		if (!decl) return true;
-		
-		if ((decl->getKind() >= clang::Decl::Kind::firstFunction) && (decl->getKind() <= clang::Decl::Kind::lastFunction)) {
-			clang::DeclaratorDecl *ddecl = static_cast<clang::DeclaratorDecl*>(decl);
-			std::cout << "Function detected!\n";
-			
-			std::string funName{ddecl->getName()};
-			
-			auto niceprint = [](const std::string &infotype, const auto &dat){ std::cout << "    " << infotype << ": " << dat << "\n"; };
-			niceprint("Function name", funName);
-			if (mangler && mangler->shouldMangleDeclName(ddecl)) {
-				std::string mangled;
-				{
-					llvm::raw_string_ostream strstr{mangled};
-					mangler->mangleName(ddecl, strstr);
-				}
-				niceprint("Function mangled name", mangled);
-				funName = std::move(mangled);
-			}
-			
-			bool valid;
-			std::string funTypeStr{""};
-			if (ddecl->getFunctionType()->isFunctionNoProtoType()) {
-				const clang::FunctionNoProtoType *funType = static_cast<const clang::FunctionNoProtoType*>(ddecl->getFunctionType());
-				const auto &retType = funType->getReturnType();
-				
-				niceprint("Function return type", type2string(retType, &retType));
-				niceprint("Canonical function return type",
-					type2string(retType.getCanonicalType(), &retType) +
-					" (" + type2char(retType.getCanonicalType(), &retType) + ")");
-				niceprint("Is sugared", funType->isSugared());
-				if (funType->isSugared()) {
-					clang::QualType qft{funType, 0};
-					niceprint("Desugared", type2string(funType->desugar(), &qft));
-				}
-				
-				funTypeStr = type2char(retType.getCanonicalType(), &retType) + std::string("Fv");
-				valid = isTypeValid(retType.getCanonicalType(), &retType);
-			} else {
-				const clang::FunctionProtoType *funType = static_cast<const clang::FunctionProtoType*>(ddecl->getFunctionType());
-				const auto &retType = funType->getReturnType();
-				
-				niceprint("Function return type", type2string(retType, &retType));
-				niceprint("Canonical function return type",
-					type2string(retType.getCanonicalType(), &retType)
-					+ " (" + type2char(retType.getCanonicalType(), &retType) + ")");
-				niceprint("Parameter count", funType->getNumParams());
-				for (const clang::QualType &type : funType->getParamTypes()) {
-					niceprint("  " + type2string(type, &type),
-						type2string(type.getCanonicalType(), &type) + " (" + type2char(type.getCanonicalType(), &type) + ")");
-				}
-				niceprint("Variadic function", funType->isVariadic() ? "yes" : "no");
-				
-				funTypeStr =
-					type2char(retType.getCanonicalType(), &retType) +
-					((funType->getNumParams() == 0)
-					 ? std::string("Fv") : std::accumulate(funType->getParamTypes().begin(), funType->getParamTypes().end(), std::string("F"),
-											[](const std::string &acc, const clang::QualType &qual){ return acc + type2char(qual.getCanonicalType(), &qual); }));
-				if (funType->isVariadic()) funTypeStr += "V";
-				valid = !funType->isVariadic() &&
-					std::accumulate(funType->getParamTypes().begin(), funType->getParamTypes().end(), isTypeValid(retType.getCanonicalType(), &retType),
-						[](bool acc, const clang::QualType &qual){ return acc && isTypeValid(qual.getCanonicalType(), &qual); });
-			}
-			
-			niceprint("Conclusion", "");
-			niceprint("Function final name", funName);
-			niceprint("Function type", funTypeStr);
-			niceprint("Valid function type", valid ? "yes" : "no");
-			std::cout << "\n";
-			
-			funMap[funName] = std::make_pair(funTypeStr, valid);
-			funList.push_back(funName);
-		}
-		
-		return true;
-	}
-};
-
-class Consumer : public clang::ASTConsumer {
-public:
-	Visitor visitor;
-	
-	Consumer(clang::CompilerInstance &ci) : visitor(ci) {
-	}
-	
-	void HandleTranslationUnit(clang::ASTContext &context) override {
-		visitor.TraverseDecl(context.getTranslationUnitDecl());
-	}
-};
-
-class Action : public clang::ASTFrontendAction {
-public:
-	virtual std::unique_ptr<clang::ASTConsumer> CreateASTConsumer(clang::CompilerInstance &ci, llvm::StringRef inFile) override {
-		return std::make_unique<Consumer>(ci);
-	}
-};
-
-int main(int argc, const char **argv) {
-	if (argc < 2) {
-		std::cerr << "Usage: " << argv[0] << " (filenames) -- [-I...]" << std::endl;
-		return 2;
-	}
-	
-	/*int fakeargc = argc + 1;
-	const char **fakeargv = new const char*[fakeargc];
-	memcpy(fakeargv, argv, argc * sizeof(char*));
-	fakeargv[fakeargc - 1] = "--";*/
-	llvm::cl::OptionCategory opcat{""};
-	clang::tooling::CommonOptionsParser op{argc, argv, opcat};
-	std::vector<std::string> paths; for (int i = 1; i < argc; ++i) paths.push_back(argv[i]);
-	
-	clang::tooling::ClangTool tool{op.getCompilations(), paths};
-	
-	tool.run(clang::tooling::newFrontendActionFactory<Action>().get());
-	
-	std::cout << "Done, outputing output.h" << std::endl;
-	std::sort(funList.begin(), funList.end());
-	std::fstream file{"output.h", std::ios_base::out};
-	for (const std::string &funName : funList) {
-		if (!funMap[funName].second) {
-			file << "//";
-		}
-		file << "GO(" << funName << ", " << funMap[funName].first << ")\n";
-	}
-	
-	return 0;
-}
@@ -1,267 +0,0 @@
-#include <string>
-
-#define ALL START() \
-	/* libc */ \
-	STRUCT("_IO_FILE", "a FILE") \
-	STRUCT("_G_fpos_t", "a file position") \
-	STRUCT("sockaddr", "a socket address") \
-	STRUCT("itimerspec", "an itimerspec") \
-	STRUCT("timespec", "a timespec") \
-	STRUCT("itimerval", "an itimerval") \
-	STRUCT("timeval", "a timeval") \
-	STRUCT("timex", "a timex") \
-	STRUCT("timezone", "a timezone") \
-	STRUCT("dirent", "a dirent") \
-	STRUCT("dirent64", "a dirent64") \
-	STRUCT("__dirstream", "a dir stream") \
-	STRUCT("tm", "a time structure (tm)") \
-	STRUCT("cmsghdr", "a cmsghdr") \
-	STRUCT("msghdr", "a msghdr") \
-	STRUCT("rpcent", "an rpcent") \
-	STRUCT("random_data", "a random_data structure") \
-	STRUCT("drand48_data", "a drand48_data structure") \
-	STRUCT("termios", "a termios") \
-	STRUCT("iovec", "an iovec") \
-	STRUCT("file_handle", "a file handle") \
-	STRUCT("lconv", "an lconv") \
-	STRUCT("__locale_struct", "a locale structure") \
-	STRUCT("aliasent", "an alias") \
-	STRUCT("fstab", "an fstab") \
-	STRUCT("group", "a group") \
-	STRUCT("hostent", "a hostent") \
-	STRUCT("protoent", "a protoent") \
-	STRUCT("passwd", "a password") \
-	STRUCT("spwd", "an spwd") \
-	STRUCT("ttyent", "a ttyent") \
-	STRUCT("utmp", "an utmp structure") \
-	STRUCT("utmpx", "an utmpx structure") \
-	STRUCT("ifaddrs", "an ifaddrs structure") \
-	STRUCT("statfs", "a statfs structure") \
-	STRUCT("statfs64", "a statfs64 structure") \
-	STRUCT("statvfs", "a statvfs structure") \
-	STRUCT("statvfs64", "a statvfs64 structure") \
-	STRUCT("timeb", "a timeb structure") \
-	STRUCT("_ftsent", "an _ftsent structure") \
-	STRUCT("sysinfo", "a sysinfo structure") \
-	STRUCT("rlimit", "an rlimit structure") \
-	STRUCT("rlimit64", "an rlimit64 structure") \
-	STRUCT("rusage", "an rusage structure") \
-	STRUCT("entry", "an entry structure") \
-	STRUCT("pollfd", "a pollfd structure") \
-	STRUCT("re_pattern_buffer", "a re_pattern_buffer structure") \
-	STRUCT("sembuf", "a sembuf structure") \
-	STRUCT("tms", "a tms structure") \
-	STRUCT("utsname", "an utsname structure") \
-	STRUCT("utimbuf", "an utimbuf structure") \
-	STRUCT2("__va_list_tag", "__va_list_tag (aka, a va_list)", 'A') \
-	/* ncurses */ \
-	STRUCT("_win_st", "a _win_st structure") \
-	STRUCT("MEVENT", "an MEVENT structure") \
-	TYPEDEF("cchar_t", "a cchar_t") \
-	/* zlib */ \
-	STRUCT("gz_header_s", "a gz_header_s structure") \
-	STRUCT("gzFile_s", "a gzFile_s structure") \
-	STRUCT("z_stream_s", "a z_stream_s structure") \
-	\
-	END()
-
-#define START()
-#define STRUCT(s, ret) if (str == s) { return 'p'; } else
-#define STRUCT2(s, ret, c) if (str == s) { return c; } else
-#define TYPEDEF(s, ret) if (str == s) { return 'p'; } else
-#define END() { return 0; }
-char ptr2char(const std::string &str) {
-	/*if ((str == "_IO_FILE")
-	 || (str == "_G_fpos_t")
-	 || (str == "sockaddr")
-	 || (str == "itimerspec")
-	 || (str == "timespec")
-	 || (str == "itimerval")
-	 || (str == "timeval")
-	 || (str == "timex")
-	 || (str == "timezone")
-	 || (str == "dirent")
-	 || (str == "dirent64")
-	 || (str == "__dirstream")
-	 || (str == "tm")
-	 || (str == "cmsghdr")
-	 || (str == "msghdr")
-	 || (str == "rpcent")
-	 || (str == "random_data")
-	 || (str == "drand48_data")
-	 || (str == "termios")
-	 || (str == "iovec")
-	 || (str == "file_handle")
-	 || (str == "lconv")
-	 || (str == "__locale_struct")
-	 || (str == "aliasent")
-	 || (str == "fstab")
-	 || (str == "group")
-	 || (str == "hostent")
-	 || (str == "protoent")
-	 || (str == "passwd")
-	 || (str == "spwd")
-	 || (str == "ttyent")
-	 || (str == "utmp")
-	 || (str == "utmpx")
-	 || (str == "ifaddrs")
-	 || (str == "statfs")
-	 || (str == "statfs64")
-	 || (str == "statvfs")
-	 || (str == "timeb")
-	 || (str == "_ftsent")
-	 || (str == "sysinfo")
-	 || (str == "rlimit")
-	 || (str == "rlimit64")
-	 || (str == "rusage")
-	 || (str == "entry")
-	 || (str == "pollfd")
-	 || (str == "re_pattern_buffer")
-	 || (str == "sembuf")
-	 || (str == "tms")
-	 || (str == "utsname")
-	 || (str == "utimbuf")
-	// ncurses
-	 || (str == "_win_st")
-	 
-	 || (str == "cchar_t")
-	) {
-		// FILE*, fpos_t*, ...
-		return 'p';
-	} else if (str == "__va_list_tag") {
-		return 'A';
-	} else {
-		return 0;
-	}*/
-	ALL
-}
-#undef END
-#undef TYPEDEF
-#undef STRUCT2
-#undef STRUCT
-#undef START
-
-#define START()
-#define STRUCT(s, ret) if (str == s) { return ret; } else
-#define STRUCT2(s, ret, c) if (str == s) { return ret; } else
-#define TYPEDEF(s, ret) if (str == s) { return ret; } else
-#define END() return "";
-const char *ptr2str(const std::string &str) {
-	/*if (str == "_IO_FILE") {
-		return "a FILE";
-	} else if (str == "_G_fpos_t") {
-		return "a file position";
-	} else if (str == "sockaddr") {
-		return "a socket address";
-	} else if (str == "itimerspec") {
-		return "an itimerspec";
-	} else if (str == "timespec") {
-		return "a timespec";
-	} else if (str == "itimerval") {
-		return "an itimerval";
-	} else if (str == "timeval") {
-		return "a timeval";
-	} else if (str == "timex") {
-		return "a timex";
-	} else if (str == "timezone") {
-		return "a timezone";
-	} else if (str == "dirent") {
-		return "a dirent";
-	} else if (str == "dirent64") {
-		return "a dirent64";
-	} else if (str == "__dirstream") {
-		return "a dir stream";
-	} else if (str == "tm") {
-		return "a time structure (tm)";
-	} else if (str == "cmsghdr") {
-		return "a cmsghdr";
-	} else if (str == "msghdr") {
-		return "a msghdr";
-	} else if (str == "rpcent") {
-		return "an rpcent";
-	} else if (str == "random_data") {
-		return "a random_data structure";
-	} else if (str == "drand48_data") {
-		return "a drand48_data structure";
-	} else if (str == "termios") {
-		return "a termios";
-	} else if (str == "iovec") {
-		return "an iovec";
-	} else if (str == "file_handle") {
-		return "a file handle";
-	} else if (str == "lconv") {
-		return "an lconv";
-	} else if (str == "__locale_struct") {
-		return "a locale structure";
-	} else if (str == "aliasent") {
-		return "an alias";
-	} else if (str == "fstab") {
-		return "an fstab";
-	} else if (str == "group") {
-		return "a group";
-	} else if (str == "hostent") {
-		return "a hostent";
-	} else if (str == "protoent") {
-		return "a protoent";
-	} else if (str == "passwd") {
-		return "a password";
-	} else if (str == "spwd") {
-		return "an spwd";
-	} else if (str == "ttyent") {
-		return "a ttyent";
-	} else if (str == "utmp") {
-		return "an utmp structure";
-	} else if (str == "utmpx") {
-		return "an utmpx structure";
-	} else if (str == "ifaddrs") {
-		return "an ifaddrs structure";
-	} else if (str == "statfs") {
-		return "a statfs structure";
-	} else if (str == "statfs64") {
-		return "a statfs64 structure";
-	} else if (str == "statvfs") {
-		return "a statvfs structure";
-	} else if (str == "statvfs64") {
-		return "a statvfs64 structure";
-	} else if (str == "timeb") {
-		return "a timeb structure";
-	} else if (str == "_ftsent") {
-		return "an _ftsent structure";
-	} else if (str == "sysinfo") {
-		return "a sysinfo structure";
-	} else if (str == "rlimit") {
-		return "an rlimit structure";
-	} else if (str == "rlimit64") {
-		return "an rlimit64 structure";
-	} else if (str == "rusage") {
-		return "an rusage structure";
-	} else if (str == "entry") {
-		return "an entry structure";
-	} else if (str == "pollfd") {
-		return "a pollfd structure";
-	} else if (str == "re_pattern_buffer") {
-		return "a re_pattern_buffer structure";
-	} else if (str == "sembuf") {
-		return "a sembuf structure";
-	} else if (str == "tms") {
-		return "a tms structure";
-	} else if (str == "utsname") {
-		return "an utsname structure";
-	} else if (str == "utimbuf") {
-		return "an utimbuf structure";
-	} else if (str == "__va_list_tag") {
-		return "__va_list_tag (aka, a va_list)";
-	// ncurses
-	} else if (str == "_win_st") {
-		return "a _win_st structure";
-		
-	} else if (str == "cchar_t") {
-		return "a cchar_t";
-	} else return "";*/
-	ALL
-}
-#undef END
-#undef TYPEDEF
-#undef STRUCT2
-#undef STRUCT
-#undef START
@@ -1,123 +1,108 @@
 ![Official logo](docs/img/Box64Logo.png "Official Logo")

-Linux Userspace x86_64 Emulator with a twist
+# Box64: Linux Userspace x86-64 Emulator with a Twist

-[View changelog](https://github.com/ptitSeb/box64/blob/main/docs/CHANGELOG.md) | [中文](https://github.com/ptitSeb/box64/blob/main/README_CN.md) | [Українська](https://github.com/ptitSeb/box64/blob/main/README_UK.md) | [Report an error](https://github.com/ptitSeb/box64/issues/new)
+[Changelog](https://github.com/ptitSeb/box64/blob/main/docs/CHANGELOG.md) | [中文](https://github.com/ptitSeb/box64/blob/main/README_CN.md) | [Українська](https://github.com/ptitSeb/box64/blob/main/README_UK.md) | [Report an Error](https://github.com/ptitSeb/box64/issues/new)

-![build](https://app.travis-ci.com/ptitSeb/box64.svg?branch=main) ![stars](https://img.shields.io/github/stars/ptitSeb/box64) ![forks](https://img.shields.io/github/forks/ptitSeb/box64) ![contributors](https://img.shields.io/github/contributors/ptitSeb/box64) ![prs](https://img.shields.io/github/issues-pr/ptitSeb/box64) ![issues](https://img.shields.io/github/issues/ptitSeb/box64)
+![Build Status](https://app.travis-ci.com/ptitSeb/box64.svg?branch=main) ![Stars](https://img.shields.io/github/stars/ptitSeb/box64) ![Forks](https://img.shields.io/github/forks/ptitSeb/box64) ![Contributors](https://img.shields.io/github/contributors/ptitSeb/box64) ![Pull Requests](https://img.shields.io/github/issues-pr/ptitSeb/box64) ![Issues](https://img.shields.io/github/issues/ptitSeb/box64)
+
+---
+
+Box64 enables running x86_64 Linux programs, including games, on non-x86_64 Linux systems such as Arm (64-bit little-endian host system required).
+
+Check out Box64 in action on YouTube:
+- [MicroLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)
+- [Pi Labs](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g)
+- [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA)
+
+Box64 leverages native system libraries (libc, libm, SDL, OpenGL), offering ease of integration and surprising performance in many applications. For performance benchmarks, check [this analysis](https://box86.org/index.php/2021/06/game-performances/).
+
+With DynaRec for ARM64, RV64 and LA64 platforms, Box64 achieves a speed boost 5-10x faster than the interpreter alone. For a deeper look at DynaRec, see [Inner workings](https://box86.org/2021/07/inner-workings-a-high%e2%80%91level-view-of-box86-and-a-low%e2%80%91level-view-of-the-dynarec/).
+
+<img src="docs/img/Box64Icon.png" width="96" height="96" alt="Box64 Icon">
+
+_Logo and icon by @grayduck - Thank you!_
+
+---
+
+## 📖 Usage
+
+Box64 offers environment variables to control its behavior. For details, see [Usage Documentation](docs/USAGE.md).
+
+---
+
+## 🚀 Compiling and Installation
+
+- [Compilation Instructions](https://github.com/ptitSeb/box64/blob/main/docs/COMPILE.md)
+- [Wine Installation for Box64](https://github.com/ptitSeb/box64/blob/main/docs/X64WINE.md)
+
+---
+
+## 🔄 Version History
+
+See the [Changelog](docs/CHANGELOG.md) for version updates.
+
+---
+
+## 🖥️ Platform Compatibility Notes
+
+Box64 requires 64-bit libraries on the host system, as it directly translates x86_64 function calls. For 32-bit binaries, use Box86.
+
+**Notes** 
+
+1. Box32 mode is in the making, which aims to support 32-bit binaries on Box64, you can enable it at build time, but do not expect everything to work. There is actually a few things that works, amny that don't. It's a known issue, no need to create tickets about it for now.
+2. Some installers may default to x86 on 64-bit host OSes, causing compatibility issues. Workaround: Use a fake `uname` that returns "x86_64" for `-m`.
+
+---
+
+## ⚙️ Configuration
+
+Box64 has configuration files located in `/etc/box64.box64rc` and `~/.box64rc`, both formatted as `.ini` files. If you don’t want to use the default `/etc/box64.box64rc` file, copy it to `~/.box64rc` to ensure compatibility.
+
+Settings priority: `~/.box64rc` > `/etc/box64.box64rc` > Command line.
+
+---
+
+## 📄 Additional Platform-Specific Notes
+
+### Unity Game Emulation
+
+- Many Unity games require OpenGL 3+, which may be challenging on ARM/RISC-V SBCs.
+- **Tip for Pi4 and Pi5 Users**: Set `MESA_GL_VERSION_OVERRIDE=3.2` with `BOX64_DYNAREC_STRONGMEM=1` to prevent freezes and enable strong memory mode.
+- **Using Panfrost**: For better compatibility on ARM, enable `PAN_MESA_DEBUG=gl3` to force higher OpenGL profiles. This can help if a game starts but quits unexpectedly before showing any content.
+
+### GTK Programs
+
+Box64 wraps GTK libraries, supporting both gtk2 and gtk3.
+
+### Steam
+
+Steam requires Box86 due to its 32-bit client app, but uses 64-bit local server binaries. Systems with less than 6GB RAM may need a swap file for optimal performance.
+
+### Wine
+
+Box64 supports Wine64 and Proton. For 32-bit components, Box86 is required. Systems with both Box64 and Box86 can run 32- and 64-bit Windows programs.
+
+**Note**: You can use Wine WOW64 build to run x86 Windows programs in Box64-only environments, this is still experimental, but it works in most cases.
+
+### Vulkan
+
+Box64 wraps Vulkan libraries.

 ----
-
-Box64 lets you run x86_64 Linux programs (such as games) on non-x86_64 Linux systems, like ARM (host system needs to be 64-bit little-endian).
-
-You can find many Box64 videos on the [MicroLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ), [Pi Labs](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g) or [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA) YouTube channels.
-
-Since Box64 uses the native versions of some "system" libraries, like libc, libm, SDL, and OpenGL, it's easy to integrate and use with most applications, and performance can be surprisingly high in many cases. Take a look at thoses bench analysis for an example [here](https://box86.org/index.php/2021/06/game-performances/).
-
-Box64 integrates with DynaRec (dynamic recompiler) for the ARM64 and RV64 platform, providing a speed boost between 5 to 10 times faster than using only the interpreter. Some high level information on how DynaRec works can be found [here](https://box86.org/2021/07/inner-workings-a-high%e2%80%91level-view-of-box86-and-a-low%e2%80%91level-view-of-the-dynarec/).
-
-Some x64 internal opcodes use parts of "Realmode X86 Emulator Library", see [x64primop.c](src/emu/x64primop.c) for copyright details
-
-<img src="docs/img/Box64Icon.png" width="96" height="96">
-
-Logo and Icon made by @grayduck, thanks!
-
----
-
-Usage
----
-
-There are a few environment variables to control the behaviour of Box64.
-
-See [here](docs/USAGE.md) for all the environment variables and what they do.
-
-Note: Box64's Dynarec uses a mechanism with Memory Protection and a SegFault signal handler to handle JIT code. In simpler terms, if you want to use GDB to debug a running program that use JIT'd code (like mono/Unity3D), you will still have many "normal" segfaults triggering. It is suggested to use something like `handle SIGSEGV nostop` in GDB to not stop at each segfault, and maybe put a breakpoint inside `my_memprotectionhandler` in `signals.c` if you want to trap SegFaults.
-
----
-
-Compiling/Installation
----
-> Compilation instructions can be found [here](https://github.com/ptitSeb/box64/blob/main/docs/COMPILE.md) \
-> Instructions for installing Wine for Box64 can be found [here](https://github.com/ptitSeb/box64/blob/main/docs/X64WINE.md)
-
----
-
-Version history/Change log
----
-
-The change log is available [here](docs/CHANGELOG.md).
-
----
-
-Notes about 32-bit platforms
----
-
-Because Box64 works by directly translating function calls from x86_64 to host system, the host system (the one Box64 is running on) needs to have 64-bit libraries. Box64 doesn't include any 64-bit <-> 32-bit translation. 
-
-So understand that box64 will only run 64-bit linux binaries. For 32-bit binaries, you need box86 (with all the multiarch or proot trickery it implies on a 64-bit OS).
-Note that many installer (mojo setup based) will fall back to "x86" when detecting ARM64 OS, and so will try to use box86 for the setup, even if an x86_64 version exist. You can hack your way around with a fake "uname" that return "x86_64" when the argument is "-m"
-
----
-
-Notes about Box64 configuration
----
-
-Box64 now have configurations files. There are 2 files loaded. `/etc/box4.box64rc` and `~/.box64rc`. Both files have the same syntax, and is basicaly an ini files. Section in square brakets define the process name, and the rest is the env. var. to set. Looke at [Usage](USAGE.md) for detail on what parameters can be put. Box64 comes with a default file that should be installed for better stability. The file in in `system/box64.box64rc` and should be installed to `/etc/box64.box64rc` If, for some reason, you don't want to install that file here, at least copy it to `~/.box64rc` or some game may not function correctly.
-Note that the priority is: `~/.box64rc` > `/etc/box64.box64rc` > command line
-So, your settings in `~/.box64rc` may override the setting from your command line...
-
----
-
-Notes about Unity game emulation
----
-
-Running Unity games should just work, but you should also note that many Unity3D games require OpenGL 3+ which can be tricky to provide on ARM SBC (single-board computers). Also many newer Unity3D (like KSP) games use the BC7 compressed textures, which is not supported on many ARM integrated GPU.
-Hint: on Pi4, use `MESA_GL_VERSION_OVERRIDE=3.2` and with Panfrost use `PAN_MESA_DEBUG=gl3` to use higher profile if the game starts then quits before showing anything.
-
----
-
-Notes about GTK programs
----
-
-GTK libraries are now wrapped on box64, both gtk2 and gtk3.
-
----
-
-Notes about Steam
----
-
-Note that Steam is a hybrid 32-bit / 64-bit. You NEED box86 to run Steam, as the client app is a 32-bit binary. It also uses a 64-bit local server binaries, and that steamwebhelper process is now mandatory, even on the "small mode". And that process will eat lots of memory. So machine with less the 6Gb of RAM will need a swapfile to use Steam.
-
----
-
-Notes about Wine
----
-
-Wine64 is supported on box64. Proton too. Be aware that 64-bit Wine also includes 32-bit components, to be able to run 32-bit Windows programs. The 32-bit apps will need box86 and will not run without it. On a system where both box64 and box86 are present and working, a wine 64-bit setup can run both 32-bit and 64-bit Windows programs (just use `wine` and `wine64` respectively).
-Note that the new 32-bit PE in 64-bit processes that the Wine team is currently implementing in Wine 7.+ is now supported, but the support is quite young so there might be some residual issues.
-
----
-
-Notes about Vulkan
----
-
-Box64 wraps Vulkan libraries, but note that it as mostly been tested with an AMD RX550 card and on the Freedreno driver, so some extensions may be missing depending on your graphics card.
-
----
-
 Final word
 ----

 I want to thank everyone who has contributed to box64 development.
 There are many ways to contribute: code contribution, financial, hardware and advertisement!
 So, in no particular order, I want to thank:
- * For their major code contribution: rajdakin, mogery
- * For their major financial contribution: FlyingFathead, stormchaser3000, dennis1248, sll00, [libre-computer-project](https://libre.computer/), [CubeCoders Limited](http://cubecoders.com/)
+ * For their major code contribution: rajdakin, mogery, ksco, xctan
+ * For their major financial contribution: [Playtron](https://playtron.one), tohodakilla, FlyingFathead, stormchaser3000, dennis1248, sll00, [libre-computer-project](https://libre.computer/), [CubeCoders Limited](http://cubecoders.com/)
 * For hardware contribution and LoongArch migration: [xiaoji](https://www.linuxgame.cn/), Deepin Beijing Develop Team
- * For their major code contribution on the RV64 Dynarec: ksco, xctan
- * For their hardware contribution: [ADLINK](https://www.adlinktech.com/Products/Computer_on_Modules/COM-HPC-Server-Carrier-and-Starter-Kit/Ampere_Altra_Developer_Platform?lang=en) with [Ampere](https://amperecomputing.com/home/edge), [Radxa](https://rockpi.org/), [StarFive](https://rvspace.org/), [Pine64](https://www.pine64.org/), [AYN](https://www.ayntec.com/)
+ * For their hardware contribution: [ADLINK](https://www.adlinktech.com/Products/Computer_on_Modules/COM-HPC-Server-Carrier-and-Starter-Kit/Ampere_Altra_Developer_Platform?lang=en) with [Ampere](https://amperecomputing.com/home/edge), [SOPHGO](https://www.sophon.ai/), [Radxa](https://rockpi.org/), [StarFive](https://rvspace.org/), [Pine64](https://www.pine64.org/), [AYN](https://www.ayntec.com/), [AYANEO](https://ayaneo.com/), [jiangcuo](https://github.com/jiangcuo)
 * For their continuous advertisements for the box64 project: salva ([microLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)), [PILab](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g)/[TwisterOS](https://twisteros.com/) team, [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA), [NicoD](https://www.youtube.com/channel/UCpv7NFr0-9AB5xoklh3Snhg), ekianjo ([Boilingsteam](https://boilingsteam.com/))

 And I also thank the many other people who participated even once in this project.

 (If you use Box64 in your project, please don't forget to mention it!)
+
@@ -1,97 +1,92 @@
-# box64
+![图标](docs/img/Box64Logo.png "图标")

-![Official logo](docs/img/Box64Logo.png "Official Logo")
-Linux 上用户空间的 x86_64 应用模拟器（支持运行原生库）
+# Box64：Linux 用户空间 x86-64 模拟器（支持原生库）

----
-![box64 build status](https://app.travis-ci.com/ptitSeb/box64.svg?branch=main)
+[更新日志](https://github.com/ptitSeb/box64/blob/main/docs/CHANGELOG.md) | [English](https://github.com/ptitSeb/box64/blob/main/README.md) | [Українська](https://github.com/ptitSeb/box64/blob/main/README_UK.md) | [Report an Error](https://github.com/ptitSeb/box64/issues/new)

-[English](docs/README.md) | [Українська](https://github.com/ptitSeb/box64/blob/main/README_UK.md) 
+![Build Status](https://app.travis-ci.com/ptitSeb/box64.svg?branch=main) ![Stars](https://img.shields.io/github/stars/ptitSeb/box64) ![Forks](https://img.shields.io/github/forks/ptitSeb/box64) ![Contributors](https://img.shields.io/github/contributors/ptitSeb/box64) ![Pull Requests](https://img.shields.io/github/issues-pr/ptitSeb/box64) ![Issues](https://img.shields.io/github/issues/ptitSeb/box64)

-Box64 可以在非 x86_64 Linux 系统（比如 ARM64）上运行 x86_64 Linux 程序（比如游戏），注意主机系统需要是 64 位小端。
+---

-您可以在 [MicroLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)、[Pi Labs](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g) 和 [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA) YouTube 频道上找到许多 Box64 视频。
+Box64 可以在非 x86_64 Linux 主机系统（比如 Arm）上运行 x86_64 Linux 程序（比如游戏），目前仅支持 64 位小端主机系统。

-由于 Box64 使用一些“系统”库的原生版本，如 libc、libm、SDL 和 OpenGL 等，因此很容易与大多数应用程序集成和使用，并且在许多情况下性能会相当不错。可以在[这里](https://box86.org/index.php/2021/06/game-performances/)查看一些性能测试的样例。
+在 YouTube 上查看 Box64 的运行效果:
+- [MicroLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)
+- [Pi Labs](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g)
+- [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA)

-Box64 集成了适用于 ARM64 和 RV64 平台的 DynaRec（动态重编译器），速度可以比纯解释模式快 5 到 10 倍。可以在[这里](https://box86.org/2021/07/inner-workings-a-high%E2%80%91level-view-of-box86-and-a-low%E2%80%91level-view-of-the-dynarec/)找到有关 DynaRec 工作原理的一些信息。
+Box64 可以使用本机原生的系统库（libc、libm、SDL、OpenGL），有着易于集成的特性和令人惊讶的性能。如需性能基准测试，请查看[此分析](https://box86.org/index.php/2021/06/game-performances/)。

-一些 x64 内部操作码使用 “Realmode X86 Emulator Library” 的部分内容，有关版权详细信息，请参见 [x64primop.c](../src/emu/x64primop.c)。
+借助适用于 ARM64，RV64 以及 LA64 平台的 DynaRec，Box64 的速度比单独使用解释器快 5-10 倍。如需深入了解 DynaRec，请参考[此文章](https://box86.org/2021/07/inner-workings-a-high%e2%80%91level-view-of-box86-and-a-low%e2%80%91level-view-of-the-dynarec/)。

-<img src="docs/img/Box64Icon.png" width="96" height="96">
+<img src="docs/img/Box64Icon.png" width="96" height="96" alt="Box64 Icon">

-LOGO 由 @grayduck 制作，感谢！
+_Logo 由 @grayduck 制作，感谢！_

----
+---

-使用方法
----
+## 📖 使用方法

-有若干环境变量可以控制 Box64 的行为。
+Box64 提供了环境变量来控制其行为。有关详细信息请参阅[使用文档](docs/USAGE.md)。

-可在[这里](docs/USAGE.md)查看所有环境变量及其作用。
+---

-注意：Box64 的 Dynarec 使用具有内存保护和段错误信号处理的机制来执行 JIT 代码。所以，如果想使用 GDB 调试使用 JIT 代码的程序（如 Mono/Unity3D），这会触发许多“正常”的段错误。建议在 GDB 中使用类似 `handle SIGSEGV nostop` 来防止它每个段错误处停止。如果你想捕获段错误，可以在 `signals.c` 的 `my_memprotectionhandler` 中设置断点。
+## 🚀 编译和安装

----
+- [编译说明](https://github.com/ptitSeb/box64/blob/main/docs/COMPILE.md)
+- [安装 Wine](https://github.com/ptitSeb/box64/blob/main/docs/X64WINE.md)

-编译/安装
----
+---

-编译说明可以在[这里](docs/COMPILE.md)查看。
+## 🔄 版本历史

----
+请参阅[变更日志](docs/CHANGELOG.md)了解版本更新说明。

-版本历史
----
+---

-版本日志在[这里](docs/CHANGELOG.md)。
+## 🖥️ 平台兼容性说明

----
+Box64 直接转换 x86_64 函数调用到本机原生库，因此需要主机系统上的 64 位库。对于 32 位二进制文件，请使用 Box86。

-32位平台的注意事项
----
+**注意事项**

-因为 Box64 的工作原理是直接将函数调用从 x86_64 转换为主机系统，所以主机系统（运行 Box64 的系统）需要有 64 位库。Box64 不包含任何 64 位 <-> 32 位的转换。
+1. Box32 模式正在制作中，旨在支持 Box64 上运行 32 位二进制文件，敬请期待！
+2. 某些安装程序可能会将 64 位的主机操作系统判定为 x86 导致兼容性问题。解决方法：使用假的 `uname` ，并使它在运行参数为 `-m` 时返回 `x86_64`。

-所以 box64 只能运行 64 位的 Linux 二进制。对于 32 位二进制则需要使用 box86 来运行（它在 64 位操作系统上使用了 multiarch 和 proot 等技巧来实现运行）。请注意，许多（基于 mojo 的）安装程序在检测到 ARM64 操作系统时将回退到 “x86”，因此即使存在 x86_64 版本，也会尝试使用 box86。这时你可以使用一个假的 `uname` ，并使它在运行参数为 `-m` 时返回 `x86_64`。
+---

----
+## ⚙️ 配置

-关于 Unity 游戏模拟的注意事项
----
+Box64 的配置文件位于 `/etc/box64.box64rc` 和 `~/.box64rc`，均为 `.ini` 格式的文件。如果您不想使用默认的 `/etc/box64.box64rc` 文件，请将其复制到 `~/.box64rc` 以确保兼容性。

-运行 Unity 游戏应该没什么问题，但还应该注意，许多 Unity3D 游戏需要 OpenGL 3+，这在 ARM SBC 上可能会比较棘手。同时许多较新的 Unity3D游戏（如 KSP）也使用 BC7 压缩纹理，很多 ARM 的集成显卡并不支持。
+配置项的优先级：`~/.box64rc` > `/etc/box64.box64rc` > 命令行。

-> 提示：如果游戏开始后没有显示任何东西就退出了，在 Pi4 上可以使用 `MESA_GL_VERSION_OVERRIDE=3.2`，在 Panfrost 上则可以使用 `PAN_MESA_DEBUG=gl3` 来使用更高的配置。
+---

----
+## 📄 特定平台的其他说明

-关于GTK程序的注意事项
----
+### Unity 游戏
+- 许多 Unity 游戏需要 OpenGL 3+，这对 ARM/RISC-V SBC 来说可能具有挑战性。
+- **对 Pi4 和 Pi5 用户的提示**：设置 `MESA_GL_VERSION_OVERRIDE=3.2` 和 `BOX64_DYNAREC_STRONGMEM=1` 以防止卡死并启用强内存模式。
+- **Panfrost**：为了在 ARM 上实现更好的兼容性，启用 `PAN_MESA_DEBUG=gl3` 以强制更高的 OpenGL Profile。如果游戏可以启动但在显示任何内容之前意外退出，这个设置可能会有所帮助。

-box64 封装了 GTK，包括 gtk2 和 gtk3。
+### GTK 程序

----
+Box64 包装了 GTK 库，支持 gtk2 和 gtk3。

-关于 Steam 的注意事项
----
+### Steam

-请注意，Steam 是 32/64 位混合的应用，所以你需要 box86 才能运行，因为客户端应用程序是 32 位的。它还使用 64 位本地服务器，它的 steamwebhelper 无法被关闭（即使是在最小模式）而且会吃掉大量的内存。对于内存小于 6 GB 的机型，你将会需要创建 swapfile 来运行 Steam。
+由于 Steam 客户端应用是 32 位的，需要使用 Box86，但其本地服务器是 64 位的二进制文件。对于内存少于 6GB 的系统，可能需要使用交换文件以获得最佳性能。

----
+### Wine

-关于 Wine 的注意事项
----
+Box64 支持 Wine64 和 Proton。对于 32 位组件，需要 Box86。配备 Box64 和 Box86 的系统可以运行 32 位和 64 位的 Windows 程序。

-box64 支持 Wine64，Proton 应该也能运行。请注意，64 位 Wine 包含有 32 位组件，以便能够运行 32 位 Windows 程序。32 位应用程序需要 box86，否则无法运行。在 box64 和 box86 都存在并工作的系统上，64 位的 Wine 可以同时运行 32 位和 64 位 Windows 程序（分别使用 `wine` 和 `wine64`）。请注意，目前在 Wine 7.+ 中实现的 Wine 时间在 64 位进程中的新 32bit PE 尚不支持。我测试了 Wine 7.5 64 位可以正常工作，但是更新的版本可能还不行。
+**提示**：您可以使用 Wine WOW64 版本在仅限 Box64 的环境中运行 x86 Windows 程序，这项支持仍处于实验阶段，但在大多数情况下都可以工作。

----
+### Vulkan

-关于 Vulkan 注意事项
----
-
-Box64 封装了 Vulkan 库，但请注意，它仅在 RX550 显卡上进行过测试，因此根据您的显卡，某些扩展可能会丢失。
+Box64 包装了 Vulkan 库。

 ----

@@ -102,10 +97,10 @@ Box64 封装了 Vulkan 库，但请注意，它仅在 RX550 显卡上进行过
 贡献方式有很多种：代码贡献、财务帮助、捐赠捐赠和广告合作！
 以下感谢不分先后： 

- * 代码贡献：rajdakin, mogery
- * 财务帮助：FlyingFathead, stormchaser3000, dennis1248, sll00, [libre-computer-project](https://libre.computer/)
+ * 代码贡献：rajdakin, mogery, ksco, xctan
+ * 财务支持：[Playtron](https://playtron.one), tohodakilla, FlyingFathead, stormchaser3000, dennis1248, sll00, [libre-computer-project](https://libre.computer/), [CubeCoders Limited](http://cubecoders.com/)
 * 硬件捐赠和 LoongArch 迁移：[xiaoji](https://www.linuxgame.cn/), Deepin Beijing Develop Team
- * 硬件捐赠：[ADLink](https://www.adlinktech.com/Products/Computer_on_Modules/COM-HPC-Server-Carrier-and-Starter-Kit/Ampere_Altra_Developer_Platform?lang=en), [Radxa](https://rockpi.org/), [Pine64](https://www.pine64.org/), [StarFive](https://rvspace.org/)
+ * 硬件捐赠：[ADLINK](https://www.adlinktech.com/Products/Computer_on_Modules/COM-HPC-Server-Carrier-and-Starter-Kit/Ampere_Altra_Developer_Platform?lang=en) with [Ampere](https://amperecomputing.com/home/edge), [SOPHGO](https://www.sophon.ai/), [Radxa](https://rockpi.org/), [StarFive](https://rvspace.org/), [Pine64](https://www.pine64.org/), [AYN](https://www.ayntec.com/), [AYANEO](https://ayaneo.com/), [jiangcuo](https://github.com/jiangcuo)
 * 为本项目持续的宣传：salva ([microLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)), [PILab](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g)/[TwisterOS](https://twisteros.com/) team, [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA), [NicoD](https://www.youtube.com/channel/UCpv7NFr0-9AB5xoklh3Snhg), ekianjo ([Boilingsteam](https://boilingsteam.com/))

 我还要感谢很多人，即使他们只参与了一次本项目。
@@ -2,7 +2,7 @@

 Емулятор простіра користувача x86_64 із родзинкою

-[Дивитись журнал змін](https://github.com/ptitSeb/box64/blob/main/docs/CHANGELOG.md) | [中文](https://github.com/ptitSeb/box64/blob/main/README_CN.md) | [Українська](https://github.com/ptitSeb/box64/blob/main/README_UK.md) | [Повідомити про помилку](https://github.com/ptitSeb/box64/issues/new)
+[Дивитись журнал змін](https://github.com/ptitSeb/box64/blob/main/docs/CHANGELOG.md) | [中文](https://github.com/ptitSeb/box64/blob/main/README_CN.md) | [English](https://github.com/ptitSeb/box64/blob/main/README.md) | [Повідомити про помилку](https://github.com/ptitSeb/box64/issues/new)

 ![build](https://app.travis-ci.com/ptitSeb/box64.svg?branch=main) ![stars](https://img.shields.io/github/stars/ptitSeb/box64) ![forks](https://img.shields.io/github/forks/ptitSeb/box64) ![contributors](https://img.shields.io/github/contributors/ptitSeb/box64) ![prs](https://img.shields.io/github/issues-pr/ptitSeb/box64) ![issues](https://img.shields.io/github/issues/ptitSeb/box64)

@@ -40,7 +40,6 @@ Box64 інтегрується з DynaRec (динамічний рекомпіл
 > Інструкцію з встановлення Wine для Box64 можна знайти [тут](docs/X64WINE.md).

 ----
-
 Історія версій/Журнал змін
 ----

@@ -68,7 +67,7 @@ Box64 інтегрується з DynaRec (динамічний рекомпіл
 ----

 Запуск ігор Unity має працювати, але ви також повинні зауважити, що для багатьох ігор Unity3D потрібен OpenGL 3+, який може бути складно забезпечити на ARM SBC (одноплатних комп’ютерах). Крім того, багато нових ігор Unity3D (наприклад, KSP) використовують стиснуті текстури BC7, які не підтримуються багатьма інтегрованими GPU ARM.
-Підказка: в Pi4 використовуйте `MESA_GL_VERSION_OVERRIDE=3.2`, а в Panfrost — `PAN_MESA_DEBUG=gl3`, щоб використовувати вищий профіль, якщо гра запускається, а потім завершується, перш ніж щось показує.
+Підказка: на Pi4 і Pi5 використовуйте `MESA_GL_VERSION_OVERRIDE=3.2` з `BOX64_DYNAREC_STRONGMEM=1`, щоб запобігти зависанням і ввімкнути режим сильної пам’яті, і використовуйте Panfrost `PAN_MESA_DEBUG=gl3`, щоб використовувати вищий профіль, якщо гра починається, а потім завершується, перш ніж щось показати.

 ----

@@ -107,11 +106,10 @@ Box64 використовує бібліотеки Vulkan, але зауваж
 Я хочу подякувати всім, хто зробив внесок у розвиток box64.
 Є багато способів зробити внесок: внесок коду, фінансовий внесок, апаратне забезпечення та реклама!
 Отже, без особливого порядку, я хочу подякувати:
-* За основний внесок у код: rajdakin, mogery
-* За великий фінансовий внесок: FlyingFathead, stormchaser3000, dennis1248, sll00, [libre-computer-project](https://libre.computer/)
+* За основний внесок у код: rajdakin, mogery, ksco, xctan
+* За великий фінансовий внесок: [Playtron](https://playtron.one), tohodakilla, FlyingFathead, stormchaser3000, dennis1248, sll00, [libre-computer-project](https://libre.computer/)
 * За апаратне забезпечення та міграцію LoongArch: [xiaoji](https://www.linuxgame.cn/), команда розробників Deepin Beijing
-* За основний внесок у код RV64 Dynarec: ksco, xctan
-* За внесок у апаратне забезпечення: [ADLink](https://www.adlinktech.com/Products/Computer_on_Modules/COM-HPC-Server-Carrier-and-Starter-Kit/Ampere_Altra_Developer_Platform?lang=en), [Radxa](https://rockpi.org/), [Pine64](https://www.pine64.org/), [StarFive](https://rvspace.org/)
+* За внесок у апаратне забезпечення: [ADLINK](https://www.adlinktech.com/Products/Computer_on_Modules/COM-HPC-Server-Carrier-and-Starter-Kit/Ampere_Altra_Developer_Platform?lang=en) with [Ampere](https://amperecomputing.com/home/edge), [SOPHGO](https://www.sophon.ai/), [Radxa](https://rockpi.org/), [StarFive](https://rvspace.org/), [Pine64](https://www.pine64.org/), [AYN](https://www.ayntec.com/), [AYANEO](https://ayaneo.com/), [jiangcuo](https://github.com/jiangcuo)
 * За безперервну рекламу Box64: salva ([microLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)), [PILab](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g)/Команда [TwisterOS](https://twisteros.com/), [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA), [NicoD](https://www.youtube.com/channel/UCpv7NFr0-9AB5xoklh3Snhg), ekianjo ([Boilingsteam](https://boilingsteam.com/))

 І я також дякую багатьом іншим людям, які хоч раз брали участь у цьому проекті.
@@ -1,3 +1,86 @@
+box64 (0.3.2) unstable; urgency=low
+
+* Introduced Box32 to run 32bits apps on 64bits OS
+*   => Box32 is a build option for Box64, and is disabled by default
+*   => Optionnal binfmt integration available for Box32
+*   => Wrapped some basics libs, including graphics and sounds so a few games already works
+*   => Work In Progress, many issues remain to be fixed, but some Linux games are playable
+* Introduced Native Flags. Can be controled with BOX64_DYNAREC_NATIVEFLAGS, but enabled by default
+*   => Available on the 3 Dynarec backend, with different implementations
+*   => ARM64 Dynarec build have all AVX/AVX2 extensions enabled by default
+*   +> Can lead to large speedup on certain cases
+* Improved Strong Memory Model emulation, with better default options and a more efficiant emulation
+* Dynarec: RV64: using RVV (and XThreadVector) to implement SSEx opcodes, with some massive speedup when used!
+* Some bugfix and improvment in the Signal handler and internal memory tracking
+* Improvment to TRAP signal generation and Handling
+* Improved CPUID opcodes again, and the various virtual file in /proc that represent those data
+* Improved some x87 operations, like long double handling and infinity comparisons...
+* Dynarec: ARM64 fixes to a few opcodes
+* Dynarec: RV64 fixes to many opcodes
+* Dynarec: LA64 fixes to a few opcodes
+* Dynarec: RV64 fixes and improvments on LOCK prefixes opcodes
+* Dynarec: Many optimisation on some individual opcodes, an all 3 backends
+* WRAPPING: More libs and functions wrapped. Some wrapping fixes too
+* WREPPING: New wrapperhelper to help coding new wrapping & fixing/enhancing existing one
+* ElfLoader: Improved object fetching
+* New build profile for SD865 and ORYON
+* Changed the installation folder of x86 libs to avoid conflict with linux distro
+* Added a few syscalls
+* Some more Vulkan extensions wrapped
+* More work on build system, and github CI (generating WCP archive), with some fixes on the Android version (still not 100% operational)
+
+-- Sebastien Chevalier <[email protected]>  Thu, 6 Dec 2024 10:30:33 -0100
+
+box64 (0.3.0) unstable; urgency=low
+
+* AVX and AVX2 implemented, along with BMI1, BMI2, ADX, FMA, F16C and RDANDR extension!
+* Introduced BOX64_AVX env. var. to enable/disable AVX extension:
+*   => BOX64_AVX=1 enable AVX, BMI1, F16C and VAES extension
+*   => BOX64_AVX=2 also enable AVX2, BMI2, FMA, ADX,VPCLMULQDQ and RDRAND
+* Dynarec: Implemented most AVX/AVX2 and friends in ARM64 Dynarec (using only NEON, so available on all ARM64 CPU)
+*   => ARM64 Dynarec build have all AVX/AVX2 extensions enabled by default
+* Improved CPUID opcodes, adding a few leaf, fixing same. Returnning an Haswell type of CPU now (was Pentium IV before)
+* Dynarec: Small optim in the emit_pf helper, on all 3 backends
+* Dynarec: ARM64 some fixes to a few opcodes
+* Dynarec: LA64 many new opcodes added, and fixes.
+* Dynarec: RV64 some new opcodes added, many fixes.
+* Dynarec: RV64 Adding some infrastructure to use RVV (if available) for SIMD emulation.
+* Dynarec: Many small changes and fixes around handling of x87, registers and internal jump.
+* WRAPPING: Added a workaround on SDL_GetThreadID to fix a race condition that was happening mostly on LA64 and broke many SDL games
+* WRAPPING: More libs and functions wrapped. Some wrapping fixes too (including a nasty error on some rare libGL functions)
+* WRAPPING: Wayland is now supported. Wine-wayland at least works now
+* Dynarec: LA64 improved LOCK CMPXCHG handling, and better 16Byte LOCK handling too (fixes many Unity3D games)
+* Dynarec: RV64 improved LOCK CMPXCHG handling
+* COSIM: Many fixes and improvment, to make BOX64_DYNAREC_TEST more usable
+* Detect when a Wine program use UnityPlayer.dll to atumaticaly use BOX64_DYNAREC_STRONGMEM=1 (unless it's already set), so more games just work
+* ElfLoader: Added a new type of relocation
+
+-- Sebastien Chevalier <[email protected]>  Thu, 9 Jul 2024 10:30:33 -0100
+
+box64 (0.2.8) unstable; urgency=low
+
+* Wrapping: More libs and function wrapping (gtk3, vulkan...)
+* Reworked X11 Callback handling, for better stability
+* Reworked exit and the load/unload of libs and symbol resolution
+* Some more profiles in box64rc
+* Better way to rename executable (including wine ones) so driver like mesa can apply the correct profile
+* Reworked memory managment in the Dynarec, limiting amount of dynamic allocation
+* Improved memory tracking and managment. Also introduce BOX64_MMAP32 to force 32bits compatible mmap for external libs (like mesa)
+* => Allow Vulkan drvier on Wine/WOW64 games to allocate 32bits compatible memory, allowing dxvk on 32bits.
+* Reworked memory managment in the Dynarec, limiting amount of dynamic allocation
+* Lots of improvments in x87 handling (virtual stack, rounding, ffree, etc.)
+* => should improve games stability
+* Dynarec: ARM64 some opcodes optimisation, especialy shift and rotation ones
+* Dynarec: RV64 lots of opcoded added.
+* => Some games on linux now have a good speed. Game on Wine are still a bit slow, and dxvk still have issues
+* Dynarec: Added Loogarch backend! Note that Loongarch are 16K pagesize platform by default.
+* => Linux games are running, and with good speed, especialy on 3A6000 platforms. Games on Wine are not working yet due to 16k pagesize limitation
+* Dynarec: Better handling of large block in the dynarec
+* Dynarec: Lots of improvments and fixes to BOX86_DYNAREC_CALLRET optimisation.
+* => It can be used on more software now, and combine with BOX64_DYNAREC_BOGBLOCKS 2 or 3 can gives some good speed boosts.
+
+-- Sebastien Chevalier <[email protected]>  Thu, 31 May 2024 17:30:33 -0100
+
 box64 (0.2.6) unstable; urgency=low

 * X64Libs: Updated libstdc++ & libgcc_s
@@ -10,4 +10,15 @@ override_dh_auto_configure:
 		  -DNOGIT=1

 override_dh_shlibdeps:
-	dh_shlibdeps --exclude=libgcc_s.so.1 --exclude=libpng12.so.0 --exclude=libstdc++.so.5 --exclude=libstdc++.so.6
+	dh_shlibdeps --exclude=libgcc_s.so.1 \
+	--exclude=libpng12.so.0 \
+	--exclude=libstdc++.so.5 \
+	--exclude=libstdc++.so.6 \
+	--exclude=libmbedcrypto.so.7 \
+	--exclude=libssl.so.1.1 \
+	--exclude=libunwind.so.8 \
+	--exclude=libmbedtls.so.14 \
+	--exclude=libcrypto.so.1.1 \
+	--exclude=libmbedx509.so.1 \
+	--exclude=libcrypto.so.1.0.0 \
+	--exclude=libssl.1.0.0
@@ -1,3 +1,80 @@
+v0.3.2
+======
+* Introduced Box32 to run 32bits apps on 64bits OS
+    => Box32 is a build option for Box64, and is disabled by default
+    => Optionnal binfmt integration available for Box32
+    => Wrapped some basics libs, including graphics and sounds so a few games already works
+    => Work In Progress, many issues remain to be fixed, but some Linux games are playable
+* Introduced Native Flags. Can be controled with BOX64_DYNAREC_NATIVEFLAGS, but enabled by default
+    => Available on the 3 Dynarec backend, with different implementations
+    => ARM64 Dynarec build have all AVX/AVX2 extensions enabled by default
+    +> Can lead to large speedup on certain cases
+* Improved Strong Memory Model emulation, with better default options and a more efficiant emulation
+* Dynarec: RV64: using RVV (and XThreadVector) to implement SSEx opcodes, with some massive speedup when used!
+* Some bugfix and improvment in the Signal handler and internal memory tracking
+* Improvment to TRAP signal generation and Handling
+* Improved CPUID opcodes again, and the various virtual file in /proc that represent those data
+* Improved some x87 operations, like long double handling and infinity comparisons...
+* Dynarec: ARM64 fixes to a few opcodes
+* Dynarec: RV64 fixes to many opcodes
+* Dynarec: LA64 fixes to a few opcodes
+* Dynarec: RV64 fixes and improvments on LOCK prefixes opcodes
+* Dynarec: Many optimisation on some individual opcodes, an all 3 backends
+* WRAPPING: More libs and functions wrapped. Some wrapping fixes too
+* WREPPING: New wrapperhelper to help coding new wrapping & fixing/enhancing existing one
+* ElfLoader: Improved object fetching
+* New build profile for SD865 and ORYON
+* Changed the installation folder of x86 libs to avoid conflict with linux distro
+* Added a few syscalls
+* Some more Vulkan extensions wrapped
+* More work on build system, and github CI (generating WCP archive), with some fixes on the Android version (still not 100% operational)
+
+v0.3.0
+======
+* AVX and AVX2 implemented, along with BMI1, BMI2, ADX, FMA, F16C and RDANDR extension!
+* Introduced BOX64_AVX env. var. to enable/disable AVX extension:
+    => BOX64_AVX=1 enable AVX, BMI1, F16C and VAES extension
+    => BOX64_AVX=2 also enable AVX2, BMI2, FMA, ADX,VPCLMULQDQ and RDRAND
+* Dynarec: Implemented most AVX/AVX2 and friends in ARM64 Dynarec (using only NEON, so available on all ARM64 CPU)
+    => ARM64 Dynarec build have all AVX/AVX2 extensions enabled by default
+* Improved CPUID opcodes, adding a few leaf, fixing same. Returnning an Haswell type of CPU now (was Pentium IV before)
+* Dynarec: Small optim in the emit_pf helper, on all 3 backends
+* Dynarec: ARM64 some fixes to a few opcodes
+* Dynarec: LA64 many new opcodes added, and fixes.
+* Dynarec: RV64 some new opcodes added, many fixes.
+* Dynarec: RV64 Adding some infrastructure to use RVV (if available) for SIMD emulation.
+* Dynarec: Many small changes and fixes around handling of x87, registers and internal jump.
+* WRAPPING: Added a workaround on SDL_GetThreadID to fix a race condition that was happening mostly on LA64 and broke many SDL games
+* WRAPPING: More libs and functions wrapped. Some wrapping fixes too (including a nasty error on some rare libGL functions)
+* WRAPPING: Wayland is now supported. Wine-wayland at least works now
+* Dynarec: LA64 improved LOCK CMPXCHG handling, and better 16Byte LOCK handling too (fixes many Unity3D games)
+* Dynarec: RV64 improved LOCK CMPXCHG handling
+* COSIM: Many fixes and improvment, to make BOX64_DYNAREC_TEST more usable
+* Detect when a Wine program use UnityPlayer.dll to atumaticaly use BOX64_DYNAREC_STRONGMEM=1 (unless it's already set), so more games just work
+* ElfLoader: Added a new type of relocation
+
+v0.2.8
+======
+* Wrapping: More libs and function wrapping (gtk3, vulkan...)
+* Reworked X11 Callback handling, for better stability
+* Reworked exit and the load/unload of libs and symbol resolution
+* Some more profiles in box64rc
+* Better way to rename executable (including wine ones) so driver like mesa can apply the correct profile
+* Reworked memory managment in the Dynarec, limiting amount of dynamic allocation
+* Improved memory tracking and managment. Also introduce BOX64_MMAP32 to force 32bits compatible mmap for external libs (like mesa)
+=> Allow Vulkan drvier on Wine/WOW64 games to allocate 32bits compatible memory, allowing dxvk on 32bits.
+* Reworked memory managment in the Dynarec, limiting amount of dynamic allocation
+* Lots of improvments in x87 handling (virtual stack, rounding, ffree, etc.)
+=> should improve games stability
+* Dynarec: ARM64 some opcodes optimisation, especialy shift and rotation ones
+* Dynarec: RV64 lots of opcoded added.
+=> Some games on linux now have a good speed. Game on Wine are still a bit slow, and dxvk still have issues
+* Dynarec: Added Loogarch backend! Note that Loongarch are 16K pagesize platform by default.
+=> Linux games are running, and with good speed, especialy on 3A6000 platforms. Games on Wine are not working yet due to 16k pagesize limitation
+* Dynarec: Better handling of large block in the dynarec
+* Dynarec: Lots of improvments and fixes to BOX86_DYNAREC_CALLRET optimisation.
+=> It can be used on more software now, and combine with BOX64_DYNAREC_BOGBLOCKS 2 or 3 can gives some good speed boosts.
+
 v0.2.6
 ======
 * X64Libs: Updated libstdc++ & libgcc_s
@@ -1,17 +1,11 @@
 Compiling/Installing
 ----

-### Debian-based Linux 
-You can use [@ryanfortner](https://github.com/ryanfortner)'s apt repository to install precompiled box64 debs, updated every 24 hours. 
+If you don't want to compile box64 yourself and prefer to use third-party pre-build version, go to the [end of the document](#pre-build-packages) for alternatives.

-```
-sudo wget https://ryanfortner.github.io/box64-debs/box64.list -O /etc/apt/sources.list.d/box64.list
-wget -qO- https://ryanfortner.github.io/box64-debs/KEY.gpg | sudo gpg --dearmor -o /etc/apt/trusted.gpg.d/box64-debs-archive-keyring.gpg
-sudo apt update && sudo apt install box64-arm64 -y
-```
-
-Alternatively, you can generate your own package using the [instructions below](https://github.com/ptitSeb/box64/blob/main/docs/COMPILE.md#debian-packaging). 
+You can also generate your own package using the [instructions below](https://github.com/ptitSeb/box64/blob/main/docs/COMPILE.md#debian-packaging). 

+## Per-platform compiling instructions
 ----

 ### The general approach is:
@@ -80,7 +74,6 @@ Warning, you need a 64bit OS:

 #### for Raspberry Pi 5

-If your Raspberry Pi OS use 16K pages use `RPI5ARM64PS16K` instead of `RPI5ARM64`:
 ```
 -D RPI5ARM64=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
 ```
@@ -93,6 +86,22 @@ Using a 64bit OS:
 -D TEGRAX1=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
 ```

+#### for Jetson Xavier/T194
+
+Using a 64bit OS:
+
+```
+-D TEGRA_T194=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for Jetson Orin/T234
+
+Using a 64bit OS:
+
+Caution: please use gcc-11 or higher, older gcc doesn't know cortex-a78ae
+```
+-D TEGRA_T234=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```

 #### for ODROID N2/N2+

@@ -134,7 +143,7 @@ Using a 64bit OS:

 #### for M1

-Only test on Asahi for now, using the default "16K page" kernel
+Only test on Asahi with Fedora, using the default "16K page" kernel

 ```
 -D M1=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
@@ -189,7 +198,7 @@ NOTE: BUILDING BOX64 IN TERMUX NATIVE IS EXPERIMENTAL AND DOESN'T GONNA RUN LINU
 You also needed have `libandroid-sysv-semaphore` and `libandroid-spawn` libraries:

 ```
-D TERMUX=1 -D -DCMAKE_C_COMPILER=clang CMAKE_BUILD_TYPE=RelWithDebInfo
+-D TERMUX=1 -DCMAKE_C_COMPILER=clang -D CMAKE_BUILD_TYPE=RelWithDebInfo
 ```

 #### for x86_64 Linux
@@ -202,7 +211,7 @@ If you encounter some linking errors, try using `NOLOADADDR=ON` (`cmake -D NOLOA

 ### Use ccmake

-Alternatively, you can **use the curses-bases ccmake (or any other gui frontend for cmake)** to select wich platform to use interactively.
+Alternatively, you can **use the curses-based ccmake (or any other gui frontend for cmake)** to select which platform to use interactively.

 ### Customize your build

@@ -234,9 +243,14 @@ If you are not building from a git clone (for example, downloading a release sou

 You need to add `-DWITH_MOLD=1` if GNU ld is extremely slow. Then run `mold -run make -j4` to build (make sure [Mold](https://github.com/rui314/mold) is installed).

+#### Build a statically linked box64
+
+You can now build box64 statically linked, with `-DSTATICBUILD`. This is to use inside an x86_64 chroot. Note that this version of box64 will have just the minimum of wrapped libs. So only libc, libm and libpthread basically are wrapped. Other libs (like libGL or libvulkan, SDL2, etc...) will not be wrapped and x86_64 version will be used. It's designed to be used in docker image, or in headless server.
+Also, the Static Build is highly experimental, but feedback are always welcomed.
+
 ----

-Testing
+## Testing
 ----
 A few tests are included with box64.

@@ -246,6 +260,39 @@ The tests are very basic and only tests some functionality for now.

 ----

-Debian Packaging
+## Debian Packaging
 ----
 Box64 can also be packaged into a .deb file ***using the source code zip from the releases page*** with `DEB_BUILD_OPTIONS=nostrip dpkg-buildpackage -us -uc -nc`. Configure any additional cmake options you might want in `debian/rules`.
+
+## Pre-build packages
+----
+### Debian-based Linux 
+You can use the [Pi-Apps-Coders apt repository](https://github.com/Pi-Apps-Coders/box64-debs) to install precompiled box64 debs, updated every 24 hours. 
+
+```
+# check if .list file already exists
+if [ -f /etc/apt/sources.list.d/box64.list ]; then
+  sudo rm -f /etc/apt/sources.list.d/box64.list || exit 1
+fi
+
+# check if .sources file already exists
+if [ -f /etc/apt/sources.list.d/box64.sources ]; then
+  sudo rm -f /etc/apt/sources.list.d/box64.sources || exit 1
+fi
+
+# download gpg key from specified url
+if [ -f /usr/share/keyrings/box64-archive-keyring.gpg ]; then
+  sudo rm -f /usr/share/keyrings/box64-archive-keyring.gpg
+fi
+sudo mkdir -p /usr/share/keyrings
+wget -qO- "https://pi-apps-coders.github.io/box64-debs/KEY.gpg" | sudo gpg --dearmor -o /usr/share/keyrings/box64-archive-keyring.gpg
+
+# create .sources file
+echo "Types: deb
+URIs: https://Pi-Apps-Coders.github.io/box64-debs/debian
+Suites: ./
+Signed-By: /usr/share/keyrings/box64-archive-keyring.gpg" | sudo tee /etc/apt/sources.list.d/box64.sources >/dev/null
+
+sudo apt update
+sudo apt install box64-generic-arm -y
+```
@@ -7,6 +7,8 @@ Env. var with * can also be put inside box64rc files.
 Box64 look for 2 places for rcfile: `/etc/box64.box64rc` and `~/.box64rc`
 The second takes precedence to the first, on an APP level 
 (that means if an [MYAPP] my appears in both file, only the settings in `~/.box64rc` will be applied)
+There is also some égeneric" name, like [*SETUP*] that will be applied to every program containing "setup" in the name
+(Note that this is not a full regex rules, it's just a name between '[*' and '*]', nothing else)

 #### BOX64_LOG *
 Controls the Verbosity level of the logs
@@ -28,7 +30,7 @@ Disables Box64 printing its version and build

 #### BOX64_LD_LIBRARY_PATH *
 Path to look for x86_64 libraries. Default is current folder and `lib` in current folder.
-Also, `/usr/lib/x86_64-linux-gnu` and `/lib/x86_64-linux-gnu` are added if they exist.
+Also, `/usr/lib/x86_64-linux-gnu`, `/lib/x86_64-linux-gnu` and `/usr/lib/box64-x86_64-linux-gnu` are added if they exist.

 #### BOX64_PATH *
 Path to look for x86_64 executable. Default is current folder and `bin` in current folder.
@@ -41,7 +43,7 @@ Enables/Disables the logging of `dlsym` errors.
 #### BOX64_TRACE_FILE *
 Send all log and trace to a file instead of `stdout`
 Also, if name contains `%pid` then this is replaced by the actual PID of box64 instance
-End the filename with `+` to have thetrace appended instead of overwritten
+End the filename with `+` to have the trace appended instead of overwritten
 Use `stderr` to use this instead of default `stdout` 

 #### BOX64_TRACE *
@@ -95,7 +97,7 @@ Show Segfault signal even if a signal handler is present
 * 1 : Show SIGSEGV detail, even if a signal handler is present

 #### BOX64_SHOWBT *
-Show some Backtrace (Nativ e and Emulated) whgen a signal (SEGV, ILL or BUS) is caught
+Show some Backtrace (Native and Emulated) when a signal (SEGV, ILL or BUS) is caught
 * 0 : Don"t show backtraces (Default.)
 * 1 : Show Backtrace detail (for native, box64 is rename as the x86_64 binary run)

@@ -104,6 +106,16 @@ Call XInitThreads when loading X11. (This is mostly for old Loki games with the
 * 0 : Don't force call XInitThreads. (Default.)
 * 1 : Call XInitThreads as soon as libX11 is loaded.

+#### BOX64_MMAP32 *
+Will use 32bits address in priority for external MMAP (when 32bits process are detected)
+ * 0 : Use regular mmap (default, except for Snapdragron build)
+ * 1 : Use 32bits address space mmap in priority for external mmap as soon a 32bits process are detected (default for SnapDragon and TegraX1 build)
+
+#### BOX64_IGNOREINT3 *
+What to do when a CC INT3 opcode is encounter in the code being run
+ * 0 : Trigger a TRAP signal if a handler is present
+ * 1 : Just skip silently the opcode
+
 #### BOX64_X11GLX *
 Force libX11's GLX extension to be present.
 * 0 : Do not force libX11's GLX extension to be present. 
@@ -133,13 +145,14 @@ Enables/Disables trace for generated code.
 * 1 : Enable trace for generated code (like regular Trace, this will slow down the program a lot and generate huge logs).

 #### BOX64_NODYNAREC  *
-Forbid dynablock creation in the interval specified (helpfull for debugging behaviour difference between Dynarec and Interpreter)
+Forbid dynablock creation in the interval specified (helpful for debugging behaviour difference between Dynarec and Interpreter)
 * 0xXXXXXXXX-0xYYYYYYYY : define the interval where dynablock cannot start (inclusive-exclusive)

 #### BOX64_DYNAREC_TEST *
 Dynarec will compare it's execution with the interpreter (super slow, only for testing)
- * 0 : No comparison
- * 1 : Each opcode runs on interepter and on Dynarec, and regs and memory are compared and print if different
+ * 0 : No comparison. (Default.)
+ * 1 : Each opcode runs on interpreter and on Dynarec, and regs and memory are compared and print if different.
+ * 0xXXXXXXXX-0xYYYYYYYY : define the interval where dynarec is tested (inclusive-exclusive)

 #### BOX64_DYNAREC_BIGBLOCK *
 Enables/Disables Box64's Dynarec building BigBlock.
@@ -156,9 +169,22 @@ Define Box64's Dynarec max allowed forward value when building Block.
 #### BOX64_DYNAREC_STRONGMEM *
 Enable/Disable simulation of Strong Memory model
 * 0 : Don't try anything special (Default.)
-* 1 : Enable some Memory Barrier when writting to memory (on some MOV opcode) to simulate Strong Memory Model while trying to limit performance impact (Default when libmonobdwgc-2.0.so is loaded)
-* 2 : All 1. plus a memory barrier on every write to memory using MOV
-* 3 : All 2. plus Memory Barrier when reading from memory and on some SSE/SSE2 opcodes too
+* 1 : Enable some memory barriers when writing to memory to simulate the Strong Memory Model in a limited way (Default when libmonobdwgc-2.0.so is loaded)
+* 2 : All 1. plus memory barriers on SIMD instructions
+* 3 : All 2. plus more memory barriers on a regular basis
+
+#### BOX64_DYNAREC_WEAKBARRIER *
+Tweaking the memory barriers to reduce the performance impact by STRONGMEM
+* 0 : Use regular safe barrier (Default.)
+* 1 : Use weak barriers to have more performance boost
+* 2 : All 1. Plus disabled the last write barriers
+
+#### BOX64_DYNAREC_PAUSE *
+Enable/Disable x86 PAUSE emulation, which may help the performance of spinlocks
+* 0 : Ignore x86 PAUSE instruction (Default.)
+* 1 : Use YIELD to emulate x86 PAUSE instruction
+* 2 : Use WFI to emulate x86 PAUSE instruction
+* 3 : Use SEVL+WFE to emulate x86 PAUSE instruction

 #### BOX64_DYNAREC_X87DOUBLE *
 Force the use of Double for x87 emulation
@@ -174,6 +200,7 @@ Enable/Disable generation of -NAN
 Enable/Disable generation of precise x86 rounding
 * 0 : Generate float/double -> int rounding like on x86
 * 1 : Don't do anything special with edge case Rounding, to go as fast as possible (no INF/NAN/Overflow -> MIN_INT conversion) (default, faster)
+* 2 : Everything from 1 plus also fast round of double->float (not taking into account current rounding mode)

 #### BOX64_DYNAREC_SAFEFLAGS *
 Handling of flags on CALL/RET opcodes
@@ -183,23 +210,18 @@ Handling of flags on CALL/RET opcodes

 #### BOX64_DYNAREC_CALLRET *
 Optimisation of CALL/RET opcodes (not compatible with jit/dynarec/smc)
-* 0 : Don't optimize CALL/RET, use Jump Table for boths
-* 1 : Try to optimized CALL/RET, skipping the use of the JumpTable when possible (Default)
-
-#### BOX64_DYNAREC_HOTPAGE *
-Handling of HotPage (Page being both executed and written)
-* 0 : Don't track hotpage (Default)
-* 1-255 : Track HotPage, and disable execution of a page being written for N attempts
-
-#### BOX64_DYNAREC_FASTPAGE *
-Will use a faster handling of HotPage (Page being both executed and written)
-* 0 : use regular hotpage (Default)
-* 1 : Use faster hotpage, taking the risk of running obsolete JIT code (might be faster, but more prone to crash)
+* 0 : Don't optimize CALL/RET, use Jump Table for boths (Default)
+* 1 : Try to optimized CALL/RET, skipping the use of the JumpTable when possible

 #### BOX64_DYNAREC_ALIGNED_ATOMICS *
 Generated code for aligned atomics only
 * 0 : The code generated can handle unaligned atomics (Default)
-* 1 : Generated code only for aligned atomics (faster and less code generated, but will SEGBUS if LOCK prefix is unsed on unaligned data)
+* 1 : Generated code only for aligned atomics (faster and less code generated, but will SEGBUS if LOCK prefix is unused on unaligned data)
+
+#### BOX64_DYNAREC_NATIVEFLAGS *
+Generate code will use native flags if possible
+* 0 : The code generated whill not use native flags even when possible
+* 1 : Generated code will use native flags when possible (Arm64 only for now) (Default)

 #### BOX64_DYNAREC_BLEEDING_EDGE *
 Detect MonoBleedingEdge and apply conservative settings
@@ -207,12 +229,12 @@ Detect MonoBleedingEdge and apply conservative settings
 * 1 : Detect MonoBleedingEdge, and apply BIGBLOCK=0 STRONGMEM=1 if detected (Default)

 #### BOX64_DYNAREC_JVM *
-Detect libjvm and apply conservative settings
+Detect libjvm and apply conservative settings. Obsolete, use BOX64_JVM instead.
 * 0 : Don't detect libjvm
-* 1 : Detect libjvm, and apply BIGBLOCK=0 STRONGMEM=1 if detected (Default)
+* 1 : Detect libjvm, and apply BIGBLOCK=0 STRONGMEM=1 SSE42=0 if detected (Default)

 #### BOX64_DYNAREC_WAIT *
-Behavior with FillBlock is not availble (FillBlock build Dynarec blocks and is not multithreaded)
+Behavior with FillBlock is not available (FillBlock build Dynarec blocks and is not multithreaded)
 * 0 : Dynarec will not wait for FillBlock to ready and use Interpreter instead (might speedup a bit massive multithread or JIT programs)
 * 1 : Dynarec will wait for FillBlock to be ready (Default)

@@ -220,6 +242,7 @@ Behavior with FillBlock is not availble (FillBlock build Dynarec blocks and is n
 Dynarec print the missing opcodes
 * 0 : not print the missing opcode (Default, unless DYNAREC_LOG>=1 or DYNAREC_DUMP>=1 is used)
 * 1 : Will print the missing opcodes
+* 2 : Will print the fallback to scalar opcodes (only valid on RISC-V)

 #### BOX64_SSE_FLUSHTO0 *
 Handling of SSE Flush to 0 flags
@@ -231,6 +254,11 @@ Handling of x87 80bits long double
 * 0 : Try to handle 80bits long double as precise as possible (Default)
 * 1 : Handle them as double

+#### BOX64_MAXCPU
+Maximum CPU Core exposed
+* 0 : Don't cap the number of cpu core exposed (Default)
+* XXX : Cap the maximum CPU Core exposed to XXX (usefull with wine64 or GridAutosport for example)
+
 #### BOX64_SYNC_ROUNDING *
 Box64 will sync rounding mode with fesetround/fegetround.
 * 0 : Disable rounding mode syncing. (Default.)
@@ -241,6 +269,16 @@ Detect libcef and apply malloc_hack settings
 * 0 : Don't detect libcef
 * 1 : Detect libcef, and apply MALLOC_HACK=2 if detected (Default)

+#### BOX64_JVM *
+Detect libjvm and apply conservative settings
+* 0 : Don't detect libjvm
+* 1 : Detect libjvm, and apply BIGBLOCK=0 STRONGMEM=1 SSE42=0 if detected (Default)
+
+#### BOX64_UNITYPLAYER *
+Detect UnityPlayer.dll and apply strongmem settings
+* 0 : Don't detect UnityPlayer.dll
+* 1 : Detect UnityPlayer.dll, and apply BOX64_DYNAREC_STRONGMEM=1 if detected (Default)
+
 #### BOX64_SDL2_JGUID *
 Need a workaround for SDL_GetJoystickGUIDInfo function for wrapped SDL2
 * 0 : Don't use any workaround
@@ -253,12 +291,12 @@ Need a workaround for SDL_GetJoystickGUIDInfo function for wrapped SDL2

 #### BOX64_LD_PRELOAD
 * XXXX[:YYYYY] force loading XXXX (and YYYY...) libraries with the binary
- PreLoaded libs can be emulated or native, and are treated the same way as if they were comming from the binary
+ PreLoaded libs can be emulated or native, and are treated the same way as if they were coming from the binary
 
 #### BOX64_EMULATED_LIBS *
 * XXXX[:YYYYY] force lib XXXX (and YYYY...) to be emulated (and not wrapped)
 Some games uses an old version of some libraries, with an ABI incompatible with native version.
-Note that LittleInferno for example is auto detected, and libvorbis.so.0 is automatical added to emulated libs, and same for Don't Starve (and Together / Server variant) that use an old SDL2 too
+Note that LittleInferno for example is auto detected, and libvorbis.so.0 is automatically added to emulated libs, and same for Don't Starve (and Together / Server variant) that use an old SDL2 too

 #### BOX64_ALLOWMISSINGLIBS *
 Allow Box64 to continue even if a library is missing.
@@ -271,14 +309,19 @@ Box64 will use wrapped libs even if the lib is specified with absolute path
 * 1 : Use Wrapped native libs even if path is absolute

 #### BOX64_PREFER_EMULATED *
-Box64 will prefer emulated libs first (execpt for glibc, alsa, pulse, GL, vulkan and X11
- * 0 : Native libs are prefered (Default.)
- * 1 : Emulated libs are prefered (Default for program running inside pressure-vessel)
+Box64 will prefer emulated libs first (except for glibc, alsa, pulse, GL, vulkan and X11
+ * 0 : Native libs are preferred (Default.)
+ * 1 : Emulated libs are preferred (Default for program running inside pressure-vessel)
+
+#### BOX64_WRAP_EGL *
+Box64 will prefer wrapped libs for EGL and GLESv2
+ * 0 : Emulated libs are preferred (Default)
+ * 1 : Native libs are preferred

 #### BOX64_CRASHHANDLER *
 Box64 will use a dummy crashhandler.so library
 * 0 : Use Emulated crashhandler.so library if needed
- * 1 : Use an internal dummy (completly empty) crashhandler.so library (defaut)
+ * 1 : Use an internal dummy (completely empty) crashhandler.so library (default)

 #### BOX64_MALLOC_HACK *
 How Box64 will handle hooking of malloc operators
@@ -301,6 +344,16 @@ Disables the load of vulkan libraries.
 * 0 : Load vulkan libraries if found.
 * 1 : Disables the load of vulkan libraries, both the native and the i386 version (can be useful on Pi4, where the vulkan driver is not quite there yet.)

+#### BOX64_SHAEXT *
+Expose or not SHAEXT (a.k.a. SHA_NI) capabilities
+ * 0 : Do not expose SHAEXT capabilities
+ * 1 : Expose SHAEXT capabilities (Default.)
+
+#### BOX64_SSE42 *
+Expose or not SSE 4.2 capabilities
+ * 0 : Do not expose SSE 4.2 capabilities (default when libjvm is detected)
+ * 1 : Expose SSE 4.2 capabilities (Default.)
+
 #### BOX64_FUTEX_WAITV *
 Use of the new fuext_waitc syscall
 * 0 : Do not try to use it, return unsupported (Default for BAD_SIGNAL build)
@@ -315,11 +368,11 @@ Define x86_64 bash to launch script
 * XXX=yyyy
 will add XXX=yyyy env. var.

-#### BOX64_ENV1
+#### BOX64_ENV1 *
 * XXX=yyyy
 will add XXX=yyyy env. var. and continue with BOX86_ENV2 ... until var doesn't exist

-#### BOX64_RESERVE_HIGH
+#### BOX64_RESERVE_HIGH *
 * 0 : Don't try to pe-reserve high memory (beyond 47bits) (Default)
 * 1 : Try to reserve (without allocating it) memory beyond 47bits (seems unstable)

@@ -332,12 +385,15 @@ Define x86_64 bash to launch script
 `set waiting=0` to exit the infinite loop.
 * 2 : Launch `gdbserver` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process, and go in an endless loop, waiting.
 Use `gdb /PATH/TO/box64` and then `target remote 127.0.0.1:1234` to connect to the gdbserver (or use actual IP if not on the machine). After that, the procedure is the same as with ` BOX64_JITGDB=1`.
- This mode can be usefullwhen programs redirect all console output to a file (like Unity3D Games)
+ This mode can be usefull when programs redirect all console output to a file (like Unity3D Games)
 * 3 : Launch `lldb` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process and go in an endless loop, waiting.

 #### BOX64_NORCFILES
 If the env var exist, no rc files (like /etc/box64.box64rc and ~/.box64rc) will be loaded

+#### BOX64_RCFILE
+If the env var is set and file exists, this variable will be used as path to the box64rc file instead of default paths (BOX64_RCFILE is loaded first, default paths are not loaded)
+
 ----

 Those variables are only valid inside a rcfile:
@@ -351,6 +407,20 @@ Those variables are only valid inside a rcfile:
 * 0 : Nothing special
 * 1 : Added "--in-process-gpu" to command line arguments (usefull for chrome based programs)

+#### BOX64_CEFDISABLEGPU
+ * 0 : Nothing special
+ * 1 : Added "-cef-disable-gpu" to command line arguments (usefull for steamwebhelper/cef based programs)
+
+#### BOX64_CEFDISABLEGPUCOMPOSITOR
+ * 0 : Nothing special
+ * 1 : Added "-cef-disable-gpu-compositor" to command line arguments (usefull for steamwebhelper/cef based programs)
+
+#### BOX64_ARGS
+If that var exist, it will be added as argument(s) to the command line if there is no current argument (it's ignored else). Note that "" are supported, but not ''
+
+#### BOX64_INSERT_ARGS
+If that var exist, it will be inserted as firsts argument(s) to the command line. Note that "" are supported, but not ''
+
 #### BOX64_EXIT
 * 0 : Nothing special
 * 1 : Just exit, don't try to run the program
@@ -33,7 +33,7 @@ Print box64 version and quit.
 =head1 CONFIGURATION FILE

 B<Box64> now have configurations files. There are 2 files loaded.
-F</etc/box4.box64rc> and F<~/.box64rc>. Both files have the same syntax, and is
+F</etc/box64.box64rc> and F<~/.box64rc>. Both files have the same syntax, and is
 basically an ini files. Section in square brackets define the process name, and
 the rest is the environment variable. B<Box64> comes with a default file that
 should be installed for better stability. Note that the priority is:
@@ -77,7 +77,7 @@ When set to 1, don't prints the banner including version and build.
 =item B<BOX64_LD_PRELOAD>=I<lib1>[:I<lib2>:...]

 Force loading libraries with the  binary. PreLoaded libs can be emulated or
-native, and are treated the same way as if they were comming from the binary.
+native, and are treated the same way as if they were coming from the binary.

 =item B<BOX64_ENV>=I<env=val>

@@ -118,8 +118,8 @@ B<BOX64_LOG> > 1 (may need B<BOX64_SHOWSEGV=1> also)
 =item B<BOX64_LD_LIBRARY_PATH>=I</path/to/libs>

 Path to look for x86_64 libraries. Default is current folder and C<lib> in
-current folder.  Also, F</usr/lib/x86_64-linux-gnu> and
-F</lib/x86_64-linux-gnu> are added if they exist.
+current folder.  Also, F</usr/lib/x86_64-linux-gnu>,
+F</lib/x86_64-linux-gnu> and F</usr/lib/box64-x86_64-linux-gnu> are added if they exist.

 =item B<BOX64_PATH>=I</path/to/bins>

@@ -205,14 +205,14 @@ Disable handling of SigILL (to ease debugging mainly).

 Show Segfault signal even if a signal handler is present

-    * 0 : Don"t force show the SIGSEGV analysis (Default.)
+    * 0 : Don't force show the SIGSEGV analysis (Default.)
    * 1 : Show SIGSEGV detail, even if a signal handler is present

 =item B<BOX64_SHOWBT>=I<0|1>

-Show some Backtrace (Nativ e and Emulated) whgen a signal (SEGV, ILL or BUS) is caught
+Show some Backtrace (Nativ e and Emulated) when a signal (SEGV, ILL or BUS) is caught

-    * 0 : Don"t show backtraces (Default.)
+    * 0 : Don't show backtraces (Default.)
    * 1 : Show Backtrace detail (for native, box64 is rename as the x86_64 binary run)

 =item B<BOX64_X11THREADS>=I<0|1>
@@ -263,16 +263,17 @@ down the program a lot and generate huge logs.

 =item B<BOX64_NODYNAREC>=I<0xXXXXXXXX-0xYYYYYYYY>

-Forbid dynablock creation in the interval specified (helpfull for debugging
-behaviour difference between Dynarec and Interpretor)
+Forbid dynablock creation in the interval specified (helpful for debugging
+behaviour difference between Dynarec and Interpreter)

 =item B<BOX64_DYNAREC_TEST>=I<0|1>

-Enables/Disables test for generated code. This will run interpreter along the Dynacrec, so this will slow
-down the program a lot.
+Dynarec will compare it's execution with the interpreter (super slow, only for testing)
+
+    * 0 : No comparison. (Default.)
+    * 1 : Each opcode runs on interepter and on Dynarec, and regs and memory are compared and print if different.
+    * 0xXXXXXXXX-0xYYYYYYYY : Define the interval where dynarec is tested (inclusive-exclusive)

-    * 0 : No test for generated code. (Default.)
-    * 1 : Enable Tests for generated code

 =item B<BOX64_DYNAREC_BIGBLOCK>=I<0|1|2|3>

@@ -290,13 +291,31 @@ Define Box64's Dynarec max allowed forward value when building Block.
    * 0 : No forward value. When current block end, don't try to go further even if there are previous forward jumps
    * XXX : Allow up to XXXX bytes of gap when building a Block after the block end to next forward jump (Default: 128)
 
-=item B<BOX64_DYNAREC_STRONGMEM>=I<0|1|2>
+=item B<BOX64_DYNAREC_STRONGMEM>=I<0|1|2|3>

 Enable/Disable simulation of Strong Memory model

    * 0 : Don't try anything special (Default.)
-    * 1 : Enable some Memory Barrier when reading from memory (on some MOV opcode) to simulate Strong Memory Model while trying to limit performance impact (Default when libmonobdwgc-2.0.so is loaded)
-    * 2 : Enable some Memory Barrier when reading from memory (on some MOV opcode) to simulate Strong Memory Model
+    * 1 : Enable some memory barriers when writing to memory to simulate the Strong Memory Model in a limited way (Default when libmonobdwgc-2.0.so is loaded)
+    * 2 : All 1. plus memory barriers on SIMD instructions
+    * 3 : All 2. plus more memory barriers on a regular basis
+
+=item B<BOX64_DYNAREC_WEAKBARRIER>=I<0|1|2>
+
+Tweaking the memory barriers to reduce the performance impact by STRONGMEM
+
+    * 0 : Use regular safe barrier (Default.)
+    * 1 : Use weak barriers to have more performance boost
+    * 2 : All 1. Plus disabled the last write barriers
+
+=item B<BOX64_DYNAREC_PAUSE>=I<0|1|2|3>
+
+Enable/Disable x86 PAUSE emulation, which may help the performance of spinlocks
+
+    * 0 : Ignore x86 PAUSE instruction (Default.)
+    * 1 : Use YIELD to emulate x86 PAUSE instruction
+    * 2 : Use WFI to emulate x86 PAUSE instruction
+    * 3 : Use SEVL+WFE to emulate x86 PAUSE instruction

 =item B<BOX64_DYNAREC_X87DOUBLE>=I<0|1>

@@ -334,20 +353,6 @@ Optimisation of CALL/RET opcodes (not compatible with jit/dynarec/smc)
    * 0 : Don't optimize CALL/RET, use Jump Table for boths (Default)
    * 1 : Try to optimized CALL/RET, skipping the use of the JumpTable when possible (will crash if blacks are invalidate, so probably incompatible with JIT/Dynarec)

-=item B<BOX64_DYNAREC_HOTPAGE>=I<0|1-255>
-
-Handling of HotPage (Page beeing both executed and writen)
-
-    * 0 : Don't track hotpage
-    * 1-255 : Track HotPage, and disable execution of a page beeing writen for N attempts (default is 4)
-
-=item B<BOX64_DYNAREC_FASTPAGE>=I<0|1>
-
-Will use a faster handling of HotPage (Page beeing both executed and writen)
-
-    * 0 : use regular hotpage (Default)
-    * 1 : Use faster hotpage, taking the risk of running obsolete JIT code (might be faster, but more prone to crash)
-
 =item B<BOX64_DYNAREC_BLEEDING_EDGE>=I<0|1>

 Detect MonoBleedingEdge and apply conservative settings
@@ -357,7 +362,7 @@ Detect MonoBleedingEdge and apply conservative settings

 =item B<BOX64_DYNAREC_WAIT>=I<0|1>

-Behavior with FillBlock is not availble (FillBlock build Dynarec blocks and is not multithreaded)
+Behavior with FillBlock is not available (FillBlock build Dynarec blocks and is not multithreaded)

    * 0 : Dynarec will not wait for FillBlock to ready and use Interpreter instead (might speedup a bit massive multithread or JIT programs)
    * 1 : Dynarec will wait for FillBlock to be ready (Default)
@@ -402,7 +407,7 @@ You can also use B<SDL_VIDEO_GL_DRIVER>
 Force lib XXXX (and YYYY...) to be emulated (and not wrapped) Some games uses
 an old version of some libraries, with an ABI incompatible with native version.
 Note that LittleInferno for example is auto detected, and libvorbis.so.0 is
-automatical added to emulated libs, and same for Don't Starve (and Together /
+automatically added to emulated libs, and same for Don't Starve (and Together /
 Server variant) that use an old SDL2 too

 =item B<BOX64_ALLOWMISSINGLIBS>=I<0|1>
@@ -421,18 +426,18 @@ Box64 will use wrapped libs even if the lib is specified with absolute path

 =item B<BOX64_PREFER_EMULATED>=I<0|1>

-Box64 will prefer emulated libs first (execpt for glibc, alsa, pulse, GL,
+Box64 will prefer emulated libs first (except for glibc, alsa, pulse, GL,
 vulkan and X11

-   * 0 : Native libs are prefered (Default.)
-   * 1 : Emulated libs are prefered (Default for program running inside pressure-vessel)
+   * 0 : Native libs are preferred (Default.)
+   * 1 : Emulated libs are preferred (Default for program running inside pressure-vessel)

 =item B<BOX64_CRASHHANDLER>=I<0|1>

 Box64 will use a dummy crashhandler.so library

    * 0 : Use Emulated crashhandler.so library if needed
-    * 1 : Use an internal dummy (completly empty) crashhandler.so library (defaut)
+    * 1 : Use an internal dummy (completely empty) crashhandler.so library (default)

 =item B<BOX64_MALLOC_HACK>=I<0|1|2>

@@ -479,6 +484,21 @@ script. yyyy needs to be a full path to a valid x86_64 version of bash

    * 0 : Just print the Segfault message on segfault (default)
    * 1 : Launch `gdb` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process and go in an endless loop, waiting. When in gdb, you need to find the correct thread yourself (the one with `my_box64signalhandler` in is stack) then probably need to `finish` 1 or 2 functions (inside `usleep(..)`) and then you'll be in `my_box64signalhandler`, just before the printf of the Segfault message. Then simply  `set waiting=0` to exit the infinite loop.
-    * 2 : Launch `gdbserver` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process, and go in an endless loop, waiting. Use `gdb /PATH/TO/box64` and then `target remote 127.0.0.1:1234` to connect to the gdbserver (or use actual IP if not on the machine). After that, the procedure is the same as with ` BOX64_JITGDB=1`. This mode can be usefullwhen programs redirect all console output to a file (like Unity3D Games)
+    * 2 : Launch `gdbserver` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process, and go in an endless loop, waiting. Use `gdb /PATH/TO/box64` and then `target remote 127.0.0.1:1234` to connect to the gdbserver (or use actual IP if not on the machine). After that, the procedure is the same as with ` BOX64_JITGDB=1`. This mode can be usefull when programs redirect all console output to a file (like Unity3D Games)
+
+=back
+
+=head1 VARIABLES FOR ENVIRONMENT ONLY
+
+=over 8
+
+=item B<BOX64_VERSION>
+
+When set, B<box64> will only print its version and then exit. This option is
+analogous to B<QEMU_VERSION> used by C<binfmt_misc> emulation of qemu-user. Its
+purpose is the same: provide a way to soft-disable C<binfmt_misc> emulation as
+well as for identifying B<box64> as the registered C<binfmt_misc> emulator.
+
+=back

 =cut
@@ -1,6 +1,6 @@
 # Maintainer: Jai-JAP <[email protected]>
 # Author: Sebastien Chevalier <[email protected]>
-pkgname=box86-rk3xxx-git
+pkgname=box64-rk3xxx-git
 pkgver=r2431.60c6858
 pkgrel=1
 pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
@@ -150,14 +150,18 @@ class FunctionConvention(object):
 		self.ident = ident
 		self.name = convname
 		self.values = valid_chars
-# Free letters:  B   FG  J      QR T   XYZab  e gh jk mno qrst   xyz
+# Free letters:  B   FG  JK     QR T    YZa   e gh jk mno qrst   yz
 conventions = {
-	'F': FunctionConvention('F', "System V", ['E', 'v', 'c', 'w', 'i', 'I', 'C', 'W', 'u', 'U', 'f', 'd', 'D', 'K', 'l', 'L', 'p', 'V', 'O', 'S', 'N', 'M', 'H', 'P', 'A', 'x', 'X']),
-	'W': FunctionConvention('W', "Windows",  ['E', 'v', 'c', 'w', 'i', 'I', 'C', 'W', 'u', 'U', 'f', 'd',      'K', 'l', 'L', 'p', 'V', 'O', 'S', 'N', 'M',      'P', 'A'])
+	'F': FunctionConvention('F', "System V", ['E', 'v', 'c', 'w', 'i', 'I', 'C', 'W', 'u', 'U', 'f', 'd', 'D', 'l', 'L', 'p', 'V', 'O', 'S', 'N', 'H', 'P', 'A', 'x', 'X', 'Y', 'b']),
+	'W': FunctionConvention('W', "Windows",  ['E', 'v', 'c', 'w', 'i', 'I', 'C', 'W', 'u', 'U', 'f', 'd',      'l', 'L', 'p', 'V', 'O', 'S', 'N',      'P', 'A'])
 }
-sortedvalues = ['E', 'v', 'c', 'w', 'i', 'I', 'C', 'W', 'u', 'U', 'f', 'd', 'D', 'K', 'l', 'L', 'p', 'V', 'O', 'S', 'N', 'M', 'H', 'P', 'A', 'x', 'X', '0', '1']
+sortedvalues = ['E', 'v', 'c', 'w', 'i', 'I', 'C', 'W', 'u', 'U', 'f', 'd', 'D', 'l', 'L', 'p', 'V', 'O', 'S', 'N', 'H', 'P', 'A', 'x', 'X', 'Y', 'b', '0', '1']
 assert(all(all(c not in conv.values[:i] and c in sortedvalues for i, c in enumerate(conv.values)) for conv in conventions.values()))

+# Some type depend on HAVE_LD80BITS; define this here so we can use it in readFiles and main
+depends_on_ld: str = "DY"
+assert(all(c in sortedvalues for c in depends_on_ld))
+
 class FunctionType(str):
 	@staticmethod
 	def validate(s: str, post: str) -> bool:
@@ -197,7 +201,7 @@ class FunctionType(str):
 		except ValueError as e:
 			raise ValueError("Value is " + self) from e
 	
-	def __getitem__(self, i: Union[int, slice]) -> 'FunctionType':
+	def __getitem__(self, i: Union[int, slice]) -> 'FunctionType': # type: ignore [override]
 		return FunctionType(super().__getitem__(i))

 RedirectType = NewType('RedirectType', FunctionType)
@@ -369,7 +373,7 @@ def readFiles(files: Iterable[Filename]) -> Tuple[JumbledGlobals, JumbledRedirec
 		
 		# typedefs is a list of all "*FE*" types for the current file
 		# mystructs  is a map  of all char -> (structure C name, replacement) for structures
-		typedefs  : JumbledTypedefs   = {}
+		typedefs    : JumbledTypedefs   = {}
 		mystructs   : JumbledStructures = {}
 		mystructuses: JumbledStructUses = {}
 		filespec[filename[:-10]] = (typedefs, mystructs, mystructuses)
@@ -399,10 +403,14 @@ def readFiles(files: Iterable[Filename]) -> Tuple[JumbledGlobals, JumbledRedirec
 							 or match("sdl1mixer", "sdl2mixer") \
 							 or match("sdl1net", "sdl2net") \
 							 or match("sdl1ttf", "sdl2ttf") \
-							 or match("libGL", "libEGL") \
+							 or match("libgl", "libegl") \
+							 or match("libgl", "glesv2") \
+							 or match("libegl", "glesv2") \
+							 or match("softokn3", "p11kit") \
 							 or match("libc", "tcmallocminimal") \
 							 or match("libc", "tbbmallocproxy") \
 							 or match("libc", "androidshmem") \
+							 or match("crypto", "libssl3") \
 							 or match("tcmallocminimal", "tbbmallocproxy"):
 								continue
 							
@@ -528,9 +536,22 @@ def readFiles(files: Iterable[Filename]) -> Tuple[JumbledGlobals, JumbledRedirec
 					if ln not in gbl[str(dependants)]:
 						gbl[str(dependants)].append(FunctionType(ln))
 					
+					if any(c in origLine for c in depends_on_ld):
+						if (gotype != "GOM") and (gotype != "GOWM") and (gotype != "GOD") and (gotype != "GOWD"):
+							print("\033[91mError:\033[m type depends on HAVE_LD80BITS but the GO type doesn't support that ({0}:{1})"
+			 					.format(filename, line[:-1]))
+							halt_required = True
+					if (gotype == "GO2") or (gotype == "GOW2") or (gotype == "GOD") or (gotype == "GODW"):
+						altfun = line.split(',')[2].split(')')[0].strip()
+						if altfun == "":
+							print("\033[91mError:\033[m empty alt function ({0}:{1})".format(filename, line[:-1]))
+							halt_required = True
+						elif altfun == funname:
+							print("\033[91mError:\033[m alt function is the original function ({0}:{1})".format(filename, line[:-1]))
+							halt_required = True
 					if origLine[2] == "E":
 						if (gotype != "GOM") and (gotype != "GOWM"):
-							if (gotype != "GO2") or not (line.split(',')[2].split(')')[0].strip().startswith('my_')):
+							if ((gotype != "GO2") and (gotype != "GOW2")) or not (line.split(',')[2].split(')')[0].strip().startswith('my_')):
 								print("\033[91mThis is probably not what you meant!\033[m ({0}:{1})".format(filename, line[:-1]))
 								halt_required = True
 						if len(origLine) > 3:
@@ -816,62 +837,76 @@ def main(root: str, files: Iterable[Filename], ver: str):
 		return 0
 	
 	# Detect simple wrappings
-	simple_wraps: Dict[ClausesStr, List[Tuple[FunctionType, int]]] = {}
 	allowed_conv_ident = "F"
 	allowed_conv = conventions[allowed_conv_ident]
 	
 	# H could be allowed maybe?
-	allowed_simply: str = "v"
-	allowed_regs  : str = "cCwWiuIUlLp"
-	allowed_fpr   : str = "fd"
+	allowed_simply: Dict[str, str] = {"ARM64": "v", "RV64": "v"}
+	allowed_regs  : Dict[str, str] = {"ARM64": "cCwWiuIUlLp", "RV64": "CWuIUlLp"}
+	allowed_fpr   : Dict[str, str] = {"ARM64": "fd", "RV64": "fd"}
 	
 	# Detect functions which return in an x87 register
 	retx87_wraps: Dict[ClausesStr, List[FunctionType]] = {}
-	return_x87: str = "DK"
+	return_x87: str = "D"
 	
 	# Sanity checks
-	forbidden_simple: str = "EDKVOSNMHPAxX"
-	assert(len(allowed_simply) + len(allowed_regs) + len(allowed_fpr) + len(forbidden_simple) == len(allowed_conv.values))
-	assert(all(c not in allowed_regs for c in allowed_simply))
-	assert(all(c not in allowed_simply + allowed_regs for c in allowed_fpr))
-	assert(all(c not in allowed_simply + allowed_regs + allowed_fpr for c in forbidden_simple))
-	assert(all(c in allowed_simply + allowed_regs + allowed_fpr + forbidden_simple for c in allowed_conv.values))
+	forbidden_simple: Dict[str, str] = {"ARM64": "EDVOSNHPAxXYb", "RV64": "EcwiDVOSNHPAxXYb"}
+	assert(all(k in allowed_simply for k in forbidden_simple))
+	assert(all(k in allowed_regs for k in forbidden_simple))
+	assert(all(k in allowed_fpr for k in forbidden_simple))
+	for k1 in forbidden_simple:
+		assert(len(allowed_simply[k1]) + len(allowed_regs[k1]) + len(allowed_fpr[k1]) + len(forbidden_simple[k1]) == len(allowed_conv.values))
+		assert(all(c not in allowed_regs[k1] for c in allowed_simply[k1]))
+		assert(all(c not in allowed_simply[k1] + allowed_regs[k1] for c in allowed_fpr[k1]))
+		assert(all(c not in allowed_simply[k1] + allowed_regs[k1] + allowed_fpr[k1] for c in forbidden_simple[k1]))
+		assert(all(c in allowed_simply[k1] + allowed_regs[k1] + allowed_fpr[k1] + forbidden_simple[k1] for c in allowed_conv.values))
 	assert(all(c in allowed_conv.values for c in return_x87))
+	assert(all(c in forbidden_simple[k] for c in depends_on_ld for k in forbidden_simple))
 	
-	def check_simple(v: FunctionType) -> Optional[int]:
-		regs_count: int = 0
-		fpr_count : int = 0
-		
-		if v.get_convention() is not allowed_conv:
-			return None
-		if v[0] in forbidden_simple:
-			return None
-		for c in v[2:]:
-			if c in allowed_regs:
-				regs_count = regs_count + 1
-			elif c in allowed_fpr:
-				fpr_count = fpr_count + 1
-			elif c in allowed_simply:
+	simple_wraps: Dict[str, Dict[ClausesStr, List[Tuple[FunctionType, int]]]] = {
+		k1: {} for k1 in forbidden_simple
+	}
+	
+	def check_simple(v: FunctionType) -> Dict[str, int]:
+		ret: Dict[str, int] = {}
+		for k in forbidden_simple:
+			regs_count: int = 0
+			fpr_count : int = 0
+    		
+			if v.get_convention() is not allowed_conv:
 				continue
+			if v[0] in forbidden_simple[k]:
+				continue
+			for c in v[2:]:
+				if c in allowed_regs[k]:
+					regs_count = regs_count + 1
+				elif c in allowed_fpr[k]:
+					fpr_count = fpr_count + 1
+				elif c in allowed_simply[k]:
+					continue
+				else:
+					break
 			else:
-				return None
-		# No character in forbidden_simply
-		if (regs_count <= 6) and (fpr_count <= 8):
-			# All checks passed!
-			ret_val = 1 + fpr_count
-			if v[0] in allowed_fpr:
-				ret_val = -ret_val
-			return ret_val
-		else:
-			# Too many arguments...
-			return None
+				# No character in forbidden_simply
+				if (regs_count <= 6) and (fpr_count <= 8):
+					# All checks passed!
+					ret_val = 1 + fpr_count
+					if v[0] in allowed_fpr[k]:
+						ret_val = -ret_val
+					ret[k] = ret_val
+				# Else, too many arguments
+		return ret
 	
 	# Only search in real wrappers (mapped ones are nearly always not simple)
 	for k in gbls:
-		tmp = [ (v, ret_val) for v, ret_val in map(lambda v: (v, check_simple(v)), gbls[k]) if ret_val is not None ]
-		if tmp:
-			simple_wraps[k] = tmp
-	simple_idxs = sorted(simple_wraps.keys(), key=lambda x: Clauses(x).splitdef())
+		for v in gbls[k]:
+			simples = check_simple(v)
+			for k1, i in simples.items():
+				if k in simple_wraps[k1]:
+					simple_wraps[k1][k].append((v, i))
+				else:
+					simple_wraps[k1][k] = [(v, i)]
+	simple_idxs = { k1: sorted(v1.keys(), key=lambda x: Clauses(x).splitdef()) for k1, v1 in simple_wraps.items() }
 	
 	def check_return_x87(v: FunctionType) -> bool:
 		return v[0] in return_x87
@@ -915,9 +950,24 @@ def main(root: str, files: Iterable[Filename], ver: str):
 			return v;
 		{rbr}
 		
+		static void* io_convert_back(void* v)
+		{lbr}
+			if(!v)
+				return v;
+			if(v == stdin)
+				return my__IO_2_1_stdin_;
+			if(v == stdout)
+				return my__IO_2_1_stdout_;
+			if(v == stderr)
+				return my__IO_2_1_stderr_;
+			return v;
+		{rbr}
+		
 		#define ST0val ST0.d
 		
 		int of_convert(int);
+		void* align_xcb_connection(void* src);
+		void unalign_xcb_connection(void* src, void* dst);
 		
 		""",
 		"wrapper.h": """
@@ -949,11 +999,11 @@ def main(root: str, files: Iterable[Filename], ver: str):
 		// o = stdout
 		// S = _IO_2_1_stdXXX_ pointer (or FILE*)
 		// N = ... automatically sending 1 arg
-		// M = ... automatically sending 2 args
 		// A = va_list
 		// 0 = constant 0, 1 = constant 1
 		// x = float complex
 		// X = double complex
+		// b = xcb_connection_t*
 		
 		""",
 		"fntypes.h": """
@@ -1015,20 +1065,59 @@ def main(root: str, files: Iterable[Filename], ver: str):
 	# Rewrite the wrapper.c file:
 	# i and u should only be 32 bits
 	td_types = {
-		#      E            v       c         w          i          I          C          W           u           U           f        d         D              K         l           L            p        V        O          S        N      M      H                    P        A			x				X
-		'F': ["x64emu_t*", "void", "int8_t", "int16_t", "int32_t", "int64_t", "uint8_t", "uint16_t", "uint32_t", "uint64_t", "float", "double", "long double", "double", "intptr_t", "uintptr_t", "void*", "void*", "int32_t", "void*", "...", "...", "unsigned __int128", "void*", "void*", "complexf_t", "complex_t"],
-		#      E            v       c         w          i          I          C          W           u           U           f        d         K         l           L            p        V        O          S        N      M      P        A
-		'W': ["x64emu_t*", "void", "int8_t", "int16_t", "int32_t", "int64_t", "uint8_t", "uint16_t", "uint32_t", "uint64_t", "float", "double", "double", "intptr_t", "uintptr_t", "void*", "void*", "int32_t", "void*", "...", "...", "void*", "void*"]
+		#      E            v       c         w          i          I          C          W           u           U           f        d         D              l           L            p        V        O          S        N      H                    P        A        x             X            Y             b
+		'F': ["x64emu_t*", "void", "int8_t", "int16_t", "int32_t", "int64_t", "uint8_t", "uint16_t", "uint32_t", "uint64_t", "float", "double", "long double", "intptr_t", "uintptr_t", "void*", "void*", "int32_t", "void*", "...", "unsigned __int128", "void*", "void*", "complexf_t", "complex_t", "complexl_t", "void*"],
+		#      E            v       c         w          i          I          C          W           u           U           f        d                        l           L            p        V        O          S        N                           P        A
+		'W': ["x64emu_t*", "void", "int8_t", "int16_t", "int32_t", "int64_t", "uint8_t", "uint16_t", "uint32_t", "uint64_t", "float", "double",                "intptr_t", "uintptr_t", "void*", "void*", "int32_t", "void*", "...",                      "void*", "void*"]
+	}
+	td_types_nold = {
+		'F': {'D': "double", 'Y': "complex_t"},
+		'W': {}
+	}
+	td_types_ld = {
+		k: {t: td_types[k][conventions[k].values.index(t)] for t in td_types_nold[k]} for k in td_types_nold
 	}
 	assert(all(k in conventions for k in td_types))
+	assert(all(k in conventions for k in td_types_nold))
+	assert(all(t in depends_on_ld for k in td_types_nold for t in td_types_nold[k]))
 	for k in conventions:
 		if len(conventions[k].values) != len(td_types[k]):
 			raise NotImplementedError("len(values) = {lenval} != len(td_types) = {lentypes}".format(lenval=len(conventions[k].values), lentypes=len(td_types[k])))
 	
 	def generate_typedefs(arr: Iterable[FunctionType], file) -> None:
+		any_depends_on_ld = False
 		for v in arr:
-			file.write("typedef " + td_types[v.get_convention().ident][v.get_convention().values.index(v[0])] + " (*" + v + "_t)"
+			if any(c in v for c in depends_on_ld):
+				any_depends_on_ld = True
+				continue
+			name = v + "_t"
+			v = v[:-1] if v.endswith('NN') else v # FIXME
+			file.write("typedef " + td_types[v.get_convention().ident][v.get_convention().values.index(v[0])] + " (*" + name + ")"
 				+ "(" + ', '.join(td_types[v.get_convention().ident][v.get_convention().values.index(t)] for t in v[2:]) + ");\n")
+		if any_depends_on_ld:
+			file.write("\n#if defined(HAVE_LD80BITS) || defined(ANDROID)\n")
+			for v in arr:
+				if all(c not in v for c in depends_on_ld):
+					continue
+				name = v + "_t"
+				v = v[:-1] if v.endswith('NN') else v # FIXME
+				file.write("typedef " + td_types[v.get_convention().ident][v.get_convention().values.index(v[0])] + " (*" + name + ")"
+					+ "(" + ', '.join(td_types[v.get_convention().ident][v.get_convention().values.index(t)] for t in v[2:]) + ");\n")
+			file.write("#else // !HAVE_LD80BITS && !ANDROID\n")
+			for k in td_types_nold:
+				for t in td_types_nold[k]:
+					td_types[k][conventions[k].values.index(t)] = td_types_nold[k][t]
+			for v in arr:
+				if all(c not in v for c in depends_on_ld):
+					continue
+				name = v + "_t"
+				v = v[:-1] if v.endswith('NN') else v # FIXME
+				file.write("typedef " + td_types[v.get_convention().ident][v.get_convention().values.index(v[0])] + " (*" + name + ")"
+					+ "(" + ', '.join(td_types[v.get_convention().ident][v.get_convention().values.index(t)] for t in v[2:]) + ");\n")
+			for k in td_types_nold:
+				for t in td_types_ld[k]:
+					td_types[k][conventions[k].values.index(t)] = td_types_ld[k][t]
+			file.write("#endif\n")
 	
 	with open(os.path.join(root, "src", "wrapped", "generated", "wrapper.c"), 'w') as file:
 		file.write(files_header["wrapper.c"].format(lbr="{", rbr="}", version=ver))
@@ -1051,10 +1140,10 @@ def main(root: str, files: Iterable[Filename], ver: str):
 			conventions['F']: [
 				"\n#error Invalid return type: emulator\n",                # E
 				"fn({0});",                                                # v
-				"R_RAX=fn({0});",                                          # c
-				"R_RAX=fn({0});",                                          # w
-				"R_RAX=(int32_t)fn({0});",                                 # i
-				"R_RAX=(int64_t)fn({0});",                                 # I
+				"R_RAX=(uint8_t)fn({0});",                                 # c
+				"R_RAX=(uint16_t)fn({0});",                                # w
+				"R_RAX=(uint32_t)fn({0});",                                # i
+				"S_RAX=(int64_t)fn({0});",                                 # I
 				"R_RAX=(unsigned char)fn({0});",                           # C
 				"R_RAX=(unsigned short)fn({0});",                          # W
 				"R_RAX=(uint32_t)fn({0});",                                # u
@@ -1062,20 +1151,20 @@ def main(root: str, files: Iterable[Filename], ver: str):
 				"emu->xmm[0].f[0]=fn({0});",                               # f
 				"emu->xmm[0].d[0]=fn({0});",                               # d
 				"long double ld=fn({0}); fpu_do_push(emu); ST0val = ld;",  # D
-				"double db=fn({0}); fpu_do_push(emu); ST0val = db;",       # K
 				"R_RAX=(intptr_t)fn({0});",                                # l
 				"R_RAX=(uintptr_t)fn({0});",                               # L
 				"R_RAX=(uintptr_t)fn({0});",                               # p
 				"\n#error Invalid return type: va_list\n",                 # V
 				"\n#error Invalid return type: at_flags\n",                # O
-				"\n#error Invalid return type: _io_file*\n",               # S
+				"R_RAX=(uintptr_t)io_convert_back(fn({0}));",              # S
 				"\n#error Invalid return type: ... with 1 arg\n",          # N
-				"\n#error Invalid return type: ... with 2 args\n",         # M
 				"unsigned __int128 u128 = fn({0}); R_RAX=(u128&0xFFFFFFFFFFFFFFFFL); R_RDX=(u128>>64)&0xFFFFFFFFFFFFFFFFL;", # H
 				"\n#error Invalid return type: pointer in the stack\n",    # P
 				"\n#error Invalid return type: va_list\n",                 # A
-				'from_complexf(emu, fn({0})));', 	                          # x
-				'from_complex(emu, fn({0})));'                             # X
+				"from_complexf(emu, fn({0}));",                            # x
+				"from_complex(emu, fn({0}));",                             # X
+				"from_complexl(emu, fn({0}));",                            # Y
+				"\n#error Invalid return type: xcb_connection_t*\n",       # b
 			],
 			conventions['W']: [
 				"\n#error Invalid return type: emulator\n",                # E
@@ -1090,32 +1179,47 @@ def main(root: str, files: Iterable[Filename], ver: str):
 				"R_RAX=fn({0});",                                          # U
 				"emu->xmm[0].f[0]=fn({0});",                               # f
 				"emu->xmm[0].d[0]=fn({0});",                               # d
-				"double db=fn({0}); fpu_do_push(emu); ST0val = db;",       # K
 				"R_RAX=(intptr_t)fn({0});",                                # l
 				"R_RAX=(uintptr_t)fn({0});",                               # L
 				"R_RAX=(uintptr_t)fn({0});",                               # p
 				"\n#error Invalid return type: va_list\n",                 # V
 				"\n#error Invalid return type: at_flags\n",                # O
-				"\n#error Invalid return type: _io_file*\n",               # S
+				"R_RAX=io_convert_back(fn({0}));",                         # S
 				"\n#error Invalid return type: ... with 1 arg\n",          # N
-				"\n#error Invalid return type: ... with 2 args\n",         # M
 				"\n#error Invalid return type: pointer in the stack\n",    # P
 				"\n#error Invalid return type: va_list\n",                 # A
 			]
 		}
+		vals_nold = {
+			conventions['F']: {
+				'D': "double db=fn({0}); fpu_do_push(emu); ST0val = db;",
+				'Y': "from_complexk(emu, fn({0}));",
+			},
+			conventions['W']: {}
+		}
+		vals_android = {
+			conventions['F']: {
+				"D": "long double ld=fn({0}); emu->xmm[0].u128=*(__uint128_t*)&ld;",
+				"Y": "from_complexl(emu, fn({0}));",
+			},
+			conventions['W']: {}
+		}
+		vals_ld = {
+			k: {t: vals[k][k.values.index(t)] for t in vals_nold[k]} for k in vals_nold
+		}
 		
 		# vreg: value is in a general register
-		#         E  v  c  w  i  I  C  W  u  U  f  d  D  K  l  L  p  V  O  S  N  M  H  P  A  x  X
-		vreg   = [0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 2, 2, 0, 1, 0, 0]
+		#         E  v  c  w  i  I  C  W  u  U  f  d  D  l  L  p  V  O  S  N  H  P  A  x  X  Y  b
+		vreg   = [0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 0, 1, 1, 1, 2, 0, 1, 0, 0, 0, 1]
 		# vxmm: value is in a XMM register
-		#         E  v  c  w  i  I  C  W  u  U  f  d  D  K  l  L  p  V  O  S  N  M  H  P  A  x  X
-		vxmm   = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2]
+		#         E  v  c  w  i  I  C  W  u  U  f  d  D  l  L  p  V  O  S  N  H  P  A  x  X  Y  b
+		vxmm   = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 0, 0]
 		# vother: value is elsewere
-		#         E  v  c  w  i  I  C  W  u  U  f  d  D  K  l  L  p  V  O  S  N  M  H  P  A  x  X
-		vother = [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0]
+		#         E  v  c  w  i  I  C  W  u  U  f  d  D  l  L  p  V  O  S  N  H  P  A  x  X  Y  b
+		vother = [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]
 		# vstack: value is on the stack (or out of register)
-		#         E  v  c  w  i  I  C  W  u  U  f  d  D  K  l  L  p  V  O  S  N  M  H  P  A  x  X
-		vstack = [0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 1, 0, 1, 1, 1, 2, 2, 1, 1, 1, 2]
+		#         E  v  c  w  i  I  C  W  u  U  f  d  D  l  L  p  V  O  S  N  H  P  A  x  X  Y  b
+		vstack = [0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 0, 1, 1, 1, 2, 1, 1, 1, 2, 4, 1]
 		arg_r = [
 			"",                            # E
 			"",                            # v
@@ -1130,7 +1234,6 @@ def main(root: str, files: Iterable[Filename], ver: str):
 			"",                            # f
 			"",                            # d
 			"",                            # D
-			"",                            # K
 			"(intptr_t){p}, ",             # l
 			"(uintptr_t){p}, ",            # L
 			"(void*){p}, ",                # p
@@ -1138,70 +1241,71 @@ def main(root: str, files: Iterable[Filename], ver: str):
 			"of_convert((int32_t){p}), ",  # O
 			"io_convert((void*){p}), ",    # S
 			"(void*){p}, ",                # N
-			"(void*){p}, ",                # M
-			"\n#error Use pp instead\n",   # H
+			"(unsigned __int128){p} + ((unsigned __int128){p2} << 64), ", # H
 			"",                            # P
 			"(void*){p}, ",                # A
-			"",	                           # x
+			"",                            # x
 			"",                            # X
+			"",                            # Y
+			"aligned_xcb, ",               # b
 		]
 		arg_x = [
-			"",                      # E
-			"",                      # v
-			"",                      # c
-			"",                      # w
-			"",                      # i
-			"",                      # I
-			"",                      # C
-			"",                      # W
-			"",                      # u
-			"",                      # U
-			"emu->xmm[{p}].f[0], ",  # f
-			"emu->xmm[{p}].d[0], ",  # d
-			"",                      # D
-			"",                      # K
-			"",                      # l
-			"",                      # L
-			"",                      # p
-			"",                      # V
-			"",                      # O
-			"",                      # S
-			"",                      # N
-			"",                      # M
-			"",                      # H
-			"",                      # P
-			"",                      # A
-			"to_complexf(emu, {p}),",# x
-			"to_complex(emu, {p}),"  # X
+			"",                       # E
+			"",                       # v
+			"",                       # c
+			"",                       # w
+			"",                       # i
+			"",                       # I
+			"",                       # C
+			"",                       # W
+			"",                       # u
+			"",                       # U
+			"emu->xmm[{p}].f[0], ",   # f
+			"emu->xmm[{p}].d[0], ",   # d
+			"",                       # D
+			"",                       # l
+			"",                       # L
+			"",                       # p
+			"",                       # V
+			"",                       # O
+			"",                       # S
+			"",                       # N
+			"",                       # H
+			"",                       # P
+			"",                       # A
+			"to_complexf(emu, {p}), ", # x
+			"to_complex(emu, {p}), ",  # X
+			"",                       # Y
+			"",                       # b
 		]
 		arg_o = [
-			"emu, ",                   # E
-			"",                        # v
-			"",                        # c
-			"",                        # w
-			"",                        # i
-			"",                        # I
-			"",                        # C
-			"",                        # W
-			"",                        # u
-			"",                        # U
-			"",                        # f
-			"",                        # d
-			"",                        # D
-			"",                        # K
-			"",                        # l
-			"",                        # L
-			"",                        # p
-			"(void*)(R_RSP + {p}), ",  # V
-			"",                        # O
-			"",                        # S
-			"",                        # N
-			"",                        # M
-			"",                        # H
-			"",                        # P
-			"",                        # A
-			"",                        # x
-			"",                        # X
+			"emu, ",                  # E
+			"",                       # v
+			"",                       # c
+			"",                       # w
+			"",                       # i
+			"",                       # I
+			"",                       # C
+			"",                       # W
+			"",                       # u
+			"",                       # U
+			"",                       # f
+			"",                       # d
+			"",                       # D
+			"",                       # l
+			"",                       # L
+			"",                       # p
+			"(void*)(R_RSP + {p}), ", # V
+			"",                       # O
+			"",                       # S
+			"",                       # N
+			"",                       # H
+			"",                       # P
+			"",                       # A
+			"",                       # x
+			"",                       # X
+			"",                       # Y
+			"",                       # b
 		]
 		arg_s = [
 			"",                                         # E
@@ -1217,7 +1321,6 @@ def main(root: str, files: Iterable[Filename], ver: str):
 			"*(float*)(R_RSP + {p}), ",                 # f
 			"*(double*)(R_RSP + {p}), ",                # d
 			"LD2localLD((void*)(R_RSP + {p})), ",       # D
-			"FromLD((void*)(R_RSP + {p})), ",           # K
 			"*(intptr_t*)(R_RSP + {p}), ",              # l
 			"*(uintptr_t*)(R_RSP + {p}), ",             # L
 			"*(void**)(R_RSP + {p}), ",                 # p
@@ -1225,13 +1328,36 @@ def main(root: str, files: Iterable[Filename], ver: str):
 			"of_convert(*(int32_t*)(R_RSP + {p})), ",   # O
 			"io_convert(*(void**)(R_RSP + {p})), ",     # S
 			"*(void**)(R_RSP + {p}), ",                 # N
-			"*(void**)(R_RSP + {p}),*(void**)(R_RSP + {p} + 8), ", # M
-			"*(unsigned __int128)(R_RSP + {p}), ",      # H
+			"*(unsigned __int128*)(R_RSP + {p}), ",     # H
 			"*(void**)(R_RSP + {p}), ",                 # P
 			"*(void**)(R_RSP + {p}), ",                 # A
 			"*(complexf_t*)(R_RSP + {p}), ",            # x
 			"*(complex_t*)(R_RSP + {p}), ",             # X
+			"to_complexl(emu, R_RSP + {p}), ",          # Y
+			"aligned_xcb, ",                            # b
 		]
+		arg_s_nold = {
+			'D': "FromLD((void*)(R_RSP + {p})), ",      # K
+			'Y': "to_complexk(emu, R_RSP + {p}), ",     # y
+		}
+		arg_s_android = {
+			'D': "*(long double*)(R_RSP + {p})], ",
+			'Y': "to_complexl(emu, R_RSP + {p}), ",
+		}
+		arg_s_ld = {
+			t: arg_s[conventions['F'].values.index(t)] for t in arg_s_nold
+		}
+		vxmm_noandroid = vxmm[:]
+		vxmm_android = vxmm[:]
+		vxmm_android[conventions['F'].values.index('D')] = 1
+		vxmm_android[conventions['F'].values.index('Y')] = 1
+		arg_x_android = {
+			'D': "*(long double*)&emu->xmm[{p}], ",
+			'Y': "to_complexl(emu, (uintptr_t)&emu->xmm[{p}]), ",
+		}
+		arg_x_ld = {
+			t: arg_x[conventions['F'].values.index(t)] for t in arg_x_android
+		}
 		
 		# Asserts
 		for k in conventions:
@@ -1258,7 +1384,7 @@ def main(root: str, files: Iterable[Filename], ver: str):
 		for k in conventions:
 			c = conventions[k]
 			if c not in vals:
-				raise NotImplementedError("[{k}]values not in vals".format(k=k, lenval=len(c.values), lenvals=len(vals[c])))
+				raise NotImplementedError("convention {k} not in vals".format(k=k))
 			if len(c.values) != len(vals[c]):
 				raise NotImplementedError("len([{k}]values) = {lenval} != len(vals[...]) = {lenvals}".format(k=k, lenval=len(c.values), lenvals=len(vals[c])))
 		# When arg_* is not empty, v* should not be 0
@@ -1282,6 +1408,50 @@ def main(root: str, files: Iterable[Filename], ver: str):
 		
 		# Helper functions to write the function definitions
 		systemVconv = conventions['F']
+		def function_pre_systemV(args: FunctionType, d: int = 8, r: int = 0, x: int = 0) -> Tuple[Optional[str], str]:
+			# args: string of argument types
+			# d: delta (in the stack)
+			# r: general register no
+			# x: XMM register no
+			if len(args) == 0:
+				return None, ""
+			
+			# Redirections
+			if args[0] == "0":
+				return function_pre_systemV(args[1:], d, r, x)
+			elif args[0] == "1":
+				return function_pre_systemV(args[1:], d, r, x)
+			
+			idx = systemVconv.values.index(args[0])
+			# Name of the registers
+			reg_arg = ["R_RDI", "R_RSI", "R_RDX", "R_RCX", "R_R8", "R_R9"]
+			if args[0] == "b":
+				if 'b' in args[1:]:
+					raise NotImplementedError("Multiple XCB connections unsupported")
+				content = ""
+				if r < len(reg_arg):
+					content = reg_arg[r]
+				else:
+					content = "(R_RSP + " + str(d) + ")"
+				return "(void*)" + content, f"void *aligned_xcb = align_xcb_connection((void*){content}); "
+			elif (r < len(reg_arg)) and (vreg[idx] > 0):
+				for _ in range(vreg[idx]):
+					if r < len(reg_arg):
+						r = r + 1
+					else:
+						d = d + 8
+				return function_pre_systemV(args[1:], d, r, x)
+			elif (x < 8) and (vxmm[idx] > 0):
+				return function_pre_systemV(args[1:], d, r, x+1)
+			elif vstack[idx] > 0:
+				return function_pre_systemV(args[1:], d+8*vstack[idx], r, x)
+			else:
+				return function_pre_systemV(args[1:], d, r, x)
+		def function_post_systemV(content: Optional[str]) -> str:
+			if content is not None:
+				return f" unalign_xcb_connection(aligned_xcb, {content});"
+			else:
+				return ""
 		def function_args_systemV(args: FunctionType, d: int = 8, r: int = 0, x: int = 0) -> str:
 			# args: string of argument types
 			# d: delta (in the stack)
@@ -1301,20 +1471,30 @@ def main(root: str, files: Iterable[Filename], ver: str):
 			reg_arg = ["R_RDI", "R_RSI", "R_RDX", "R_RCX", "R_R8", "R_R9"]
 			if (r < len(reg_arg)) and (vreg[idx] > 0):
 				ret = ""
-				for _ in range(vreg[idx]):
-					# There may be values in multiple registers
+				if (vreg[idx] == 2) and ("{p2}" in arg_r[idx]):
 					if r < len(reg_arg):
 						# Value is in a general register
-						ret = ret + arg_r[idx].format(p=reg_arg[r])
-						r = r + 1
+						ret = ret + arg_r[idx].format(p=reg_arg[r], p2=reg_arg[r+1])
+						r = r + 2
 					else:
 						# Remaining is in the stack
 						ret = ret + arg_s[idx].format(p=d)
 						d = d + 8
+				else:
+					for _ in range(vreg[idx]):
+						# There may be values in multiple registers
+						if r < len(reg_arg):
+							# Value is in a general register
+							ret = ret + arg_r[idx].format(p=reg_arg[r])
+							r = r + 1
+						else:
+							# Remaining is in the stack
+							ret = ret + arg_s[idx].format(p=d)
+							d = d + 8
 				return ret + function_args_systemV(args[1:], d, r, x)
 			elif (x < 8) and (vxmm[idx] > 0):
 				# Value is in an XMM register
-				return arg_x[idx].format(p=x) + function_args_systemV(args[1:], d, r, x+1)
+				return arg_x[idx].format(p=x) + function_args_systemV(args[1:], d, r, x+vxmm[idx])
 			elif vstack[idx] > 0:
 				# Value is in the stack
 				return arg_s[idx].format(p=d) + function_args_systemV(args[1:], d+8*vstack[idx], r, x)
@@ -1361,42 +1541,156 @@ def main(root: str, files: Iterable[Filename], ver: str):
 			# Generic function
 			conv = N.get_convention()
 			if conv is systemVconv:
-				f.write(vals[conv][conv.values.index(N[0])].format(function_args_systemV(N[2:])[:-2]) + " }\n")
+				prepost, pre = function_pre_systemV(N[2:])
+				f.write(pre + vals[conv][conv.values.index(N[0])].format(function_args_systemV(N[2:])[:-2]) + function_post_systemV(prepost))
 			else:
-				f.write(vals[conv][conv.values.index(N[0])].format(function_args_windows(N[2:])[:-2]) + " }\n")
+				f.write(vals[conv][conv.values.index(N[0])].format(function_args_windows(N[2:])[:-2]))
+			f.write(" }\n")
 		
 		for k in gbls:
+			any_depends_on_ld = False
 			if k != str(Clauses()):
 				file.write("\n#if " + k + "\n")
 			for v in gbls[k]:
+				if any(c in v for c in depends_on_ld):
+					any_depends_on_ld = True
+					continue
 				if v == FunctionType("vFv"):
 					# Suppress all warnings...
 					file.write("void vFv(x64emu_t *emu, uintptr_t fcn) { vFv_t fn = (vFv_t)fcn; fn(); (void)emu; }\n")
 				else:
 					function_writer(file, v, v + "_t")
+			if any_depends_on_ld:
+				file.write("\n#if defined(ANDROID)\n")
+				for c in vals_android:
+					for t in vals_android[c]:
+						vals[c][c.values.index(t)] = vals_android[c][t]
+				for t in arg_s_android:
+					arg_s[conventions['F'].values.index(t)] = arg_s_android[t]
+				for t in arg_x_android:
+					arg_x[conventions['F'].values.index(t)] = arg_x_android[t]
+				vxmm = vxmm_android
+				for v in gbls[k]:
+					if all(c not in v for c in depends_on_ld):
+						continue
+					if v == FunctionType("vFv"):
+						# Suppress all warnings...
+						file.write("void vFv(x64emu_t *emu, uintptr_t fcn) { vFv_t fn = (vFv_t)fcn; fn(); (void)emu; }\n")
+					else:
+						function_writer(file, v, v + "_t")
+				file.write("#elif !defined(HAVE_LD80BITS)\n")
+				for c in vals_android:
+					for t in vals_ld[c]:
+						vals[c][c.values.index(t)] = vals_ld[c][t]
+				for c in vals_nold:
+					for t in vals_nold[c]:
+						vals[c][c.values.index(t)] = vals_nold[c][t]
+				for t in arg_s_android:
+					arg_s[conventions['F'].values.index(t)] = arg_s_ld[t]
+				for t in arg_s_nold:
+					arg_s[conventions['F'].values.index(t)] = arg_s_nold[t]
+				for t in arg_x_android:
+					arg_x[conventions['F'].values.index(t)] = arg_x_ld[t]
+				vxmm = vxmm_noandroid
+				for v in gbls[k]:
+					if all(c not in v for c in depends_on_ld):
+						continue
+					if v == FunctionType("vFv"):
+						# Suppress all warnings...
+						file.write("void vFv(x64emu_t *emu, uintptr_t fcn) { vFv_t fn = (vFv_t)fcn; fn(); (void)emu; }\n")
+					else:
+						function_writer(file, v, v + "_t")
+				for c in vals_nold:
+					for t in vals_nold[c]:
+						vals[c][c.values.index(t)] = vals_ld[c][t]
+				for t in arg_s_nold:
+					arg_s[conventions['F'].values.index(t)] = arg_s_ld[t]
+				file.write("#else // defined(HAVE_LD80BITS) && !defined(ANDROID)\n")
+				for v in gbls[k]:
+					if all(c not in v for c in depends_on_ld):
+						continue
+					if v == FunctionType("vFv"):
+						# Suppress all warnings...
+						file.write("void vFv(x64emu_t *emu, uintptr_t fcn) { vFv_t fn = (vFv_t)fcn; fn(); (void)emu; }\n")
+					else:
+						function_writer(file, v, v + "_t")
+				file.write("#endif\n")
 			if k != str(Clauses()):
 				file.write("#endif\n")
 		file.write("\n")
 		for k in redirects:
+			any_depends_on_ld = False
 			if k != str(Clauses()):
 				file.write("\n#if " + k + "\n")
 			for vr, vf in redirects[k]:
+				if any(c in vr for c in depends_on_ld):
+					any_depends_on_ld = True
+					continue
 				function_writer(file, vr, vf + "_t")
+			if any_depends_on_ld:
+				file.write("\n#if defined(ANDROID)\n")
+				for c in vals_android:
+					for t in vals_android[c]:
+						vals[c][c.values.index(t)] = vals_android[c][t]
+				for t in arg_s_android:
+					arg_s[conventions['F'].values.index(t)] = arg_s_android[t]
+				for t in arg_x_android:
+					arg_x[conventions['F'].values.index(t)] = arg_x_android[t]
+				vxmm = vxmm_android
+				for vr, vf in redirects[k]:
+					if all(c not in vr for c in depends_on_ld):
+						continue
+					function_writer(file, vr, vf + "_t")
+				file.write("#elif !defined(HAVE_LD80BITS)\n")
+				for c in vals_android:
+					for t in vals_ld[c]:
+						vals[c][c.values.index(t)] = vals_ld[c][t]
+				for c in vals_nold:
+					for t in vals_nold[c]:
+						vals[c][c.values.index(t)] = vals_nold[c][t]
+				for t in arg_s_android:
+					arg_s[conventions['F'].values.index(t)] = arg_s_ld[t]
+				for t in arg_s_nold:
+					arg_s[conventions['F'].values.index(t)] = arg_s_nold[t]
+				for t in arg_x_android:
+					arg_x[conventions['F'].values.index(t)] = arg_x_ld[t]
+				vxmm = vxmm_noandroid
+				for vr, vf in redirects[k]:
+					if all(c not in vr for c in depends_on_ld):
+						continue
+					function_writer(file, vr, vf + "_t")
+				for c in vals_nold:
+					for t in vals_nold[c]:
+						vals[c][c.values.index(t)] = vals_ld[c][t]
+				for t in arg_s_nold:
+					arg_s[conventions['F'].values.index(t)] = arg_s_ld[t]
+				file.write("#else // defined(HAVE_LD80BITS) && !defined(ANDROID)\n")
+				for vr, vf in redirects[k]:
+					if all(c not in vr for c in depends_on_ld):
+						continue
+					function_writer(file, vr, vf + "_t")
+				file.write("#endif\n")
 			if k != str(Clauses()):
 				file.write("#endif\n")
 		
 		# Write the isSimpleWrapper function
-		file.write("\nint isSimpleWrapper(wrapper_t fun) {\n")
-		for k in simple_idxs:
-			if k != str(Clauses()):
-				file.write("#if " + k + "\n")
-			for vf, val in simple_wraps[k]:
-				file.write("\tif (fun == &" + vf + ") return " + str(val) + ";\n")
-			if k != str(Clauses()):
-				file.write("#endif\n")
-		file.write("\treturn 0;\n}\n")
+		inttext = ""
+		file.write("\n")
+		for k1 in simple_idxs:
+			file.write("#{inttext}if defined({k1})\nint isSimpleWrapper(wrapper_t fun) {{\n\tif (box64_is32bits) return 0;\n".format(inttext=inttext, k1=k1))
+			inttext = "el"
+			for k in simple_idxs[k1]:
+				if k != str(Clauses()):
+					file.write("#if " + k + "\n")
+				for vf, val in simple_wraps[k1][k]:
+					file.write("\tif (fun == &" + vf + ") return " + str(val) + ";\n")
+				if k != str(Clauses()):
+					file.write("#endif\n")
+			file.write("\treturn 0;\n}\n")
+		file.write("#else\nint isSimpleWrapper(wrapper_t fun) {\n\treturn 0;\n}\n#endif\n")
 		
 		# Write the isRetX87Wrapper function
+		file.write("\nint isRetX87Wrapper32(wrapper_t fun)\n#ifndef BOX32\n{ return 0; }\n#else\n ;\n#endif\n")
 		file.write("\nint isRetX87Wrapper(wrapper_t fun) {\n")
 		for k in retx87_idxs:
 			if k != str(Clauses()):
@@ -1475,11 +1769,11 @@ def main(root: str, files: Iterable[Filename], ver: str):
 	return 0

 if __name__ == '__main__':
-	limit = []
+	limit: List[int] = []
 	for i, v in enumerate(sys.argv):
 		if v == "--":
 			limit.append(i)
 	Define.defines = list(map(DefineType, sys.argv[2:limit[0]]))
-	if main(sys.argv[1], sys.argv[limit[0]+1:], "2.2.0.18") != 0:
+	if main(sys.argv[1], sys.argv[limit[0]+1:], "2.5.0.24") != 0:
 		exit(2)
 	exit(0)
@@ -19,10 +19,10 @@ set(ENV{BOX64_LOG} 0)
 set(ENV{BOX64_NOBANNER} 1)
 if( EXISTS ${CMAKE_SOURCE_DIR}/x64lib )
  # we are inside box64 folder
-  set(ENV{LD_LIBRARY_PATH} ${CMAKE_SOURCE_DIR}/x64lib)
+  set(ENV{BOX64_LD_LIBRARY_PATH} ${CMAKE_SOURCE_DIR}/x64lib)
 else()
  # we are inside build folder
-  set(ENV{LD_LIBRARY_PATH} ${CMAKE_SOURCE_DIR}/../x64lib)
+  set(ENV{BOX64_LD_LIBRARY_PATH} ${CMAKE_SOURCE_DIR}/../x64lib)
 endif( EXISTS ${CMAKE_SOURCE_DIR}/x64lib )

 # run the test program, capture the stdout/stderr and the result var
@@ -0,0 +1,342 @@
+#include <stdint.h>
+#include <stdlib.h>
+#include <pthread.h>
+#include <stdio.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box32.h"
+#include "custommem.h"
+#include "converter32.h"
+
+#include "khash.h"
+
+KHASH_MAP_INIT_INT64(to, ulong_t);
+KHASH_MAP_INIT_INT(from, uintptr_t);
+KHASH_MAP_INIT_STR(strings, ptr_t);
+
+static kh_from_t*   hash_from = NULL;
+static kh_to_t*     hash_to = NULL;
+#define HASH_MSK    0xf000000f
+#define HASH_VAL    0x00ffffff
+#define HASH_SHIFT  4
+static uint32_t     hash_cnt = 1;
+static pthread_rwlock_t hash_lock = {0};
+static int          hash_running = 0;
+// locale
+static kh_from_t*   locale_from = NULL;
+static kh_to_t*     locale_to = NULL;
+static kh_strings_t* const_strings = NULL;
+
+
+void init_hash_helper() {
+    hash_from = kh_init(from);
+    hash_to = kh_init(to);
+    locale_from = kh_init(from);
+    locale_to = kh_init(to);
+    const_strings = kh_init(strings);
+    pthread_rwlock_init(&hash_lock, NULL);
+    hash_running = 1;
+}
+void fini_hash_helper() {
+    if(!hash_running)
+        return;
+    hash_running = 0;
+    kh_destroy(from, hash_from);
+    hash_from = NULL;
+    kh_destroy(to, hash_to);
+    hash_to = NULL;
+    hash_cnt = 1;
+    kh_destroy(from, locale_from);
+    locale_from = NULL;
+    kh_destroy(to, locale_to);
+    locale_to = NULL;
+    kh_destroy(strings, const_strings); //TODO: does not free memory correctly
+    const_strings = NULL;
+    pthread_rwlock_destroy(&hash_lock);
+}
+
+// Convert from hash key to original 64bits value
+uintptr_t from_hash(ulong_t l) {
+    // easy case first
+    if((l&HASH_MSK)!=HASH_MSK) {
+        return (uintptr_t)l;
+    }
+    if(l==0xffffffff) {
+        return 0xffffffffffffffffll;
+    }
+    // get value from hash table second
+    uintptr_t ret = 0;
+    if(!hash_running) {
+        //printf_log(LOG_INFO, "Warning, from_hash used but hash not running\n");
+        return ret;
+    }
+    pthread_rwlock_rdlock(&hash_lock);
+    khint_t k = kh_get(from, hash_from, l);
+    if (k==kh_end(hash_from)) {
+        ret = (uintptr_t)l;
+    } else {
+        ret = kh_value(hash_from, k);
+    }
+    pthread_rwlock_unlock(&hash_lock);
+    return ret;
+}
+// same as from_hash
+uintptr_t from_hash_d(ulong_t l) {
+    return from_hash(l);
+}
+
+// Convert from 64bits to hash key, creating it if needed
+ulong_t to_hash(uintptr_t p) {
+    if((p<0x100000000LL) && ((p&HASH_MSK)!=HASH_MSK))
+        return (ulong_t)p;
+    if(p==0xffffffffffffffffll) {
+        return 0xffffffff;
+    }
+    ulong_t ret = 0;
+    if(!hash_running) {
+        //printf_log(LOG_INFO, "Warning, to_hash used but hash not running\n");
+        return ret;
+    }
+    khint_t k;
+    pthread_rwlock_rdlock(&hash_lock);
+    k = kh_get(to, hash_to, p);
+    if(k==kh_end(hash_to)) {
+        // create a new key, but need write lock!
+        pthread_rwlock_unlock(&hash_lock);
+        pthread_rwlock_wrlock(&hash_lock);
+        ret = HASH_MSK | (((hash_cnt++)&HASH_VAL)<<HASH_SHIFT);
+        int r;
+        k = kh_put(to, hash_to, p, &r);
+        kh_value(hash_to, k) = ret;
+        k = kh_put(from, hash_from, ret, &r);
+        kh_value(hash_from, k) = p;
+    } else {
+        ret = kh_value(hash_to, k);
+    }
+    pthread_rwlock_unlock(&hash_lock);
+    return ret;
+}
+
+// Convert from 64bits to hash key and delete the entry from both hash table
+ulong_t to_hash_d(uintptr_t p) {
+    if((p<0x100000000LL) && ((p&HASH_MSK)!=HASH_MSK))
+        return (ulong_t)p;
+    if(p==0xffffffffffffffffll)
+        return 0xffffffff;
+    ulong_t ret = 0;
+    if(!hash_running) {
+        //printf_log(LOG_INFO, "Warning, to_hash_d used but hash not running\n");
+        return ret;
+    }
+    khint_t k;
+    pthread_rwlock_wrlock(&hash_lock);
+    k = kh_get(to, hash_to, p);
+    if(k==kh_end(hash_to)) {
+        /// should this be an assert?
+    } else {
+        ret = kh_value(hash_to, k);
+        // delete both entries
+        //k = kh_get(to, hash_to, p);
+        kh_del(to, hash_to, k);
+        k = kh_get(from, hash_from, ret);
+        kh_del(from, hash_from, k);
+    }
+    pthread_rwlock_unlock(&hash_lock);
+    return ret;
+}
+
+typedef struct struct_locale_s {
+	void* p0[13];
+	void* p1;   //const unsigned short int *__ctype_b;
+	void* p2;   //const int *__ctype_tolower;
+	void* p3;   //const int *__ctype_toupper;
+	void* p4[13];
+} struct_locale_t;
+// not a real structure
+#define LOCALE_SIGN 0x54abcd845412LL
+typedef struct struct_locale_32_s {
+    ptr_t p0[13];
+    ptr_t p1;
+    ptr_t p2;
+    ptr_t p3;
+    ptr_t p4[13];
+    uint64_t sign;
+    struct_locale_t* org;   // save the orginal locale
+    // copy of the array, in case some apps use them
+    unsigned short int type_b[384];
+    int tolower[384];
+    int tohigher[384];
+} struct_locale_32_t;
+
+void to_struct_locale(ptr_t d, const struct_locale_t *src) {
+	if (!src) return;
+	struct_locale_32_t* dest = from_ptrv(d);
+    // save the original locale
+    dest->sign = LOCALE_SIGN;
+    dest->org = (void*)src;
+    //copy the 2 arrays
+    for(int i=0; i<13; ++i) {
+	    dest->p0[i] = to_hashv(src->p0[i]);
+    }
+    for(int i=0; i<13; ++i) {
+	    dest->p4[i] = to_hashv(src->p4[i]);
+    }
+    // copy the 3 ctype int (1st is short int, but int will do)
+    memcpy(dest->type_b, src->p1-128*sizeof(short), 384*sizeof(short));
+    memcpy(dest->tolower, src->p2-128*sizeof(int), 384*sizeof(int));
+    memcpy(dest->tohigher, src->p3-128*sizeof(int), 384*sizeof(int));
+    dest->p1 = to_ptrv(dest->type_b)+128*sizeof(short);
+    dest->p2 = to_ptrv(dest->tolower)+128*sizeof(int);
+    dest->p3 = to_ptrv(dest->tohigher)+128*sizeof(int);
+}
+void free_struct_locale(const struct_locale_t *src) {
+    for(int i=0; i<13; ++i) {
+	    to_hash_d((uintptr_t)src->p0[i]);
+    }
+    for(int i=0; i<13; ++i) {
+	    to_hash_d((uintptr_t)src->p4[i]);
+    }
+}
+
+// Convert from locale key to original 64bits value
+void* from_locale(ptr_t l) {
+    // easy case first
+    if(l < 0x100) {
+        return from_ptrv(l);
+    }
+    if(l == 0xffffffff) {
+        return (void*)-1;
+    }
+    // get value from hash table second
+    void* ret = 0;
+    if(!hash_running) {
+        //printf_log(LOG_INFO, "Warning, from_locale used but hash not running\n");
+        return ret;
+    }
+    struct_locale_32_t* loc = from_ptrv(l);
+    if(loc->sign==LOCALE_SIGN)
+        return loc->org;
+    pthread_rwlock_rdlock(&hash_lock);
+    khint_t k = kh_get(from, locale_from, l);
+    if (k==kh_end(locale_from)) {
+        ret = from_ptrv(l);
+    } else {
+        ret = (void*)kh_value(locale_from, k);
+    }
+    pthread_rwlock_unlock(&hash_lock);
+    //from_struct_locale((struct_locale_t*)ret, l);
+    return ret;
+}
+// same as from_locale
+void* from_locale_d(ptr_t l) {
+    return from_locale(l);
+}
+
+// Convert from 64bits to locale key, creating it if needed
+ptr_t to_locale(void* p) {
+    if((uintptr_t)p < 0x100) {
+        return to_ptrv(p);
+    }
+    if(p == (void*)-1) {
+        return 0xffffffff;
+    }
+    ptr_t ret = 0;
+    if(!hash_running) {
+        //printf_log(LOG_INFO, "Warning, to_locale used but hash not running\n");
+        return ret;
+    }
+    khint_t k;
+    pthread_rwlock_rdlock(&hash_lock);
+    k = kh_get(to, locale_to, (uintptr_t)p);
+    int conv = 0;
+    if(k==kh_end(locale_to)) {
+        // create a new key, but need write lock!
+        pthread_rwlock_unlock(&hash_lock);
+        pthread_rwlock_wrlock(&hash_lock);
+        // a locale_t is 5 pointer!
+        void* m = calloc(1, sizeof(struct_locale_32_t)); // the 3 ctype value are also inside the locale struct
+        ret = to_ptrv(m);
+        // add to hash maps
+        int r;
+        k = kh_put(to, locale_to, (uintptr_t)p, &r);
+        kh_value(locale_to, k) = ret;
+        k = kh_put(from, locale_from, ret, &r);
+        kh_value(locale_from, k) = (uintptr_t)p;
+        conv = 1;
+    } else {
+        ret = kh_value(locale_to, k);
+    }
+    pthread_rwlock_unlock(&hash_lock);
+    if(conv)
+        to_struct_locale(ret, (struct_locale_t*)p);
+    return ret;
+}
+
+// Convert from 64bits to hash key and delete the entry from both hash table
+ptr_t to_locale_d(void* p) {
+    if((uintptr_t)p < 0x100)
+        return to_ptrv(p);
+    ptr_t ret = 0;
+    if(!hash_running)
+        return ret;
+    khint_t k;
+    pthread_rwlock_wrlock(&hash_lock);
+    k = kh_get(to, locale_to, (uintptr_t)p);
+    if(k==kh_end(locale_to)) {
+        /// should this be an assert?
+    } else {
+        ret = kh_value(locale_to, k);
+        // free the memory
+        free_struct_locale(p);
+        free(from_ptrv(ret));
+        // delete both entries
+        k = kh_get(to, locale_to, (uintptr_t)p);
+        kh_del(to, locale_to, k);
+        k = kh_get(from, locale_from, ret);
+        kh_del(from, locale_from, k);
+    }
+    pthread_rwlock_unlock(&hash_lock);
+    return ret;
+}
+
+char* from_cstring(ptr_t p) {
+    return (char*)from_ptrv(p);
+}
+
+ptr_t to_cstring(char* p) {
+    if((uintptr_t)p<0x100000000LL)
+        return to_ptrv(p);
+    ptr_t ret = 0;
+    pthread_rwlock_rdlock(&hash_lock);
+    khint_t k = kh_get(strings, const_strings, p);
+    if(k==kh_end(const_strings)) {
+        // create a new key, but need write lock!
+        pthread_rwlock_unlock(&hash_lock);
+        pthread_rwlock_wrlock(&hash_lock);
+        ret = to_ptrv(box_strdup(p));
+        int r;
+        k = kh_put(strings, const_strings, (char*)from_ptrv(ret), &r);
+        kh_value(const_strings, k) = ret;
+    } else
+        ret = kh_value(const_strings, k);
+    pthread_rwlock_unlock(&hash_lock);
+    return ret;
+}
+
+ptr_t to_cstring_d(char* p) {
+    if((uintptr_t)p<0x100000000LL)
+        return to_ptrv(p);
+    ptr_t ret = 0;
+    pthread_rwlock_wrlock(&hash_lock);
+    khint_t k = kh_get(strings, const_strings, p);
+    if(k==kh_end(const_strings)) {
+        // assert?
+    } else {
+        ret = kh_value(const_strings, k);
+        kh_del(strings, const_strings, k);
+        free(from_ptrv(ret));
+    }
+    pthread_rwlock_unlock(&hash_lock);
+    return ret;
+}
@@ -21,6 +21,11 @@
 #include "signals.h"
 #include "rcfile.h"
 #include "gltools.h"
+#include "rbtree.h"
+#include "dynarec.h"
+#ifdef BOX32
+#include "box32.h"
+#endif

 EXPORTDYN
 void initAllHelpers(box64context_t* context)
@@ -29,6 +34,9 @@ void initAllHelpers(box64context_t* context)
    if(inited)
        return;
    my_context = context;
+    #ifdef BOX32
+    init_hash_helper();
+    #endif
    init_pthread_helper();
    init_bridge_helper();
    init_signal_helper(context);
@@ -45,6 +53,9 @@ void finiAllHelpers(box64context_t* context)
    fini_pthread_helper(context);
    fini_signal_helper();
    fini_bridge_helper();
+    #ifdef BOX32
+    fini_hash_helper();
+    #endif
    fini_custommem_helper(context);
    finied = 1;
 }
@@ -73,6 +84,7 @@ void free_tlsdatasize(void* p)
 }

 void x64Syscall(x64emu_t *emu);
+void x86Syscall(x64emu_t *emu);

 int unlockMutex()
 {
@@ -126,7 +138,7 @@ void relockMutex(int locks)
    #undef GO
 }

-static void init_mutexes(box64context_t* context)
+void init_mutexes(box64context_t* context)
 {
 #ifndef DYNAREC
    pthread_mutexattr_t attr;
@@ -211,25 +223,33 @@ box64context_t *NewBox64Context(int argc)

    init_custommem_helper(context);

-    context->maplib = NewLibrarian(context, 1);
-    context->local_maplib = NewLibrarian(context, 1);
+    context->maplib = NewLibrarian(context);
+    context->local_maplib = NewLibrarian(context);
    context->versym = NewDictionnary();
    context->system = NewBridge();
    // Cannot use Bridge name as the map is not initialized yet
    // create vsyscall
-    context->vsyscall = AddBridge(context->system, vFEv, x64Syscall, 0, NULL);
+    context->vsyscall = AddBridge(context->system, vFEv, box64_is32bits?x86Syscall:x64Syscall, 0, NULL);
    // create the vsyscalls
-    context->vsyscalls[0] = AddVSyscall(context->system, 96);
-    context->vsyscalls[1] = AddVSyscall(context->system, 201);
-    context->vsyscalls[2] = AddVSyscall(context->system, 309);
-    // create the alternate to map at address
-    addAlternate((void*)0xffffffffff600000, (void*)context->vsyscalls[0]);
-    addAlternate((void*)0xffffffffff600400, (void*)context->vsyscalls[1]);
-    addAlternate((void*)0xffffffffff600800, (void*)context->vsyscalls[2]);
+    if(box64_is32bits) {
+        #ifdef BOX32
+        addAlternate((void*)0xffffe400, from_ptrv(context->vsyscall));
+        #endif
+    } else {
+        context->vsyscalls[0] = AddVSyscall(context->system, 96);
+        context->vsyscalls[1] = AddVSyscall(context->system, 201);
+        context->vsyscalls[2] = AddVSyscall(context->system, 309);
+        // create the alternate to map at address
+        addAlternate((void*)0xffffffffff600000, (void*)context->vsyscalls[0]);
+        addAlternate((void*)0xffffffffff600400, (void*)context->vsyscalls[1]);
+        addAlternate((void*)0xffffffffff600800, (void*)context->vsyscalls[2]);
+    }
    // create exit bridge
    context->exit_bridge = AddBridge(context->system, NULL, NULL, 0, NULL);
    // get handle to box64 itself
+    #ifndef STATICBUILD
    context->box64lib = dlopen(NULL, RTLD_NOW|RTLD_GLOBAL);
+    #endif
    context->dlprivate = NewDLPrivate();

    context->argc = argc;
@@ -262,8 +282,13 @@ box64context_t *NewBox64Context(int argc)
    context->segtls[4].is32bits = 1;

    context->globdata = NewMapSymbols();
+    context->uniques = NewMapSymbols();

    initAllHelpers(context);
+    
+    #ifdef DYNAREC
+    context->db_sizes = rbtree_init("db_sizes");
+    #endif

    return context;
 }
@@ -335,8 +360,12 @@ void FreeBox64Context(box64context_t** context)

    FreeBridge(&ctx->system);

+    #ifndef STATICBUILD
    freeGLProcWrapper(ctx);
    freeALProcWrapper(ctx);
+    #ifdef BOX32
+    #endif
+    #endif

    if(ctx->stack_clone)
        box_free(ctx->stack_clone);
@@ -358,6 +387,12 @@ void FreeBox64Context(box64context_t** context)
        FreeX64Emu(&ctx->emu_sig);

    FreeMapSymbols(&ctx->globdata);
+    FreeMapSymbols(&ctx->uniques);
+
+#ifdef DYNAREC
+    //dynarec_log(LOG_INFO, "BOX64 Dynarec at exit: Max DB=%d, righter=%d\n", ctx->max_db_size, rb_get_righter(ctx->db_sizes));
+    rbtree_delete(ctx->db_sizes);
+#endif

    finiAllHelpers(ctx);

@@ -2,7 +2,7 @@
 #define __BOX64_VERSION_H_

 #define BOX64_MAJOR 0
-#define BOX64_MINOR 2
-#define BOX64_REVISION 6
+#define BOX64_MINOR 3
+#define BOX64_REVISION 2

 #endif //__BOX64_VERSION_H_
@@ -9,7 +9,7 @@

 void PrintBox64Version()
 {
-    printf("Box64%s%s v%d.%d.%d %s built on %s %s\n", 
+    printf_log(LOG_NONE, "Box64%s%s v%d.%d.%d %s built on %s %s\n", 
    #ifdef HAVE_TRACE
        " with trace",
    #else
@@ -0,0 +1,53 @@
+#define _GNU_SOURCE         /* See feature_test_macros(7) */
+#include <unistd.h>
+#include <stdint.h>
+
+#ifndef MAP_FAILED
+#define MAP_FAILED ((void *) -1)
+#endif
+
+#define EXPORT __attribute__((visibility("default")))
+#ifdef BUILD_DYNAMIC
+#define EXPORTDYN __attribute__((visibility("default")))
+#else
+#define EXPORTDYN
+#endif
+
+#ifndef MAP_32BIT
+#define MAP_32BIT   0x40
+#endif
+
+typedef void x64emu_t;
+extern void* mapallmem;
+extern int box64_is32bits;
+void setProtection(uintptr_t addr, size_t size, uint32_t prot);
+void freeProtection(uintptr_t addr, size_t size);
+void* internal_mmap(void *addr, unsigned long length, int prot, int flags, int fd, ssize_t offset);
+int internal_munmap(void* addr, unsigned long length);
+
+void* my_mmap64(x64emu_t* emu, void *addr, unsigned long length, int prot, int flags, int fd, ssize_t offset);
+
+extern int running32bits;
+extern int box64_mmap32;
+
+EXPORT void* mmap64(void *addr, unsigned long length, int prot, int flags, int fd, ssize_t offset)
+{
+    void* ret;
+    if(!addr && ((running32bits && box64_mmap32) || (flags&MAP_32BIT) || box64_is32bits))
+        ret = my_mmap64(NULL, addr, length, prot, flags | MAP_32BIT, fd, offset);
+    else
+        ret = internal_mmap(addr, length, prot, flags, fd, offset);
+    if(ret!=MAP_FAILED && mapallmem)
+        setProtection((uintptr_t)ret, length, prot);
+    return ret;
+}
+EXPORT void* mmap(void *addr, unsigned long length, int prot, int flags, int fd, ssize_t offset) __attribute__((alias("mmap64")));
+
+EXPORT int munmap(void* addr, unsigned long length)
+{
+    int ret = internal_munmap(addr, length);
+    if(!ret && mapallmem) {
+        freeProtection((uintptr_t)addr, length);
+    }
+    return ret;
+}
@@ -5,6 +5,41 @@

 */

+/* 
+    ARM64 Linux Call Convention
+
+SP          The Stack Pointer.
+r30 LR      The Link Register.
+r29 FP      The Frame Pointer
+r19…r28     Callee-saved registers
+r18         The Platform Register, if needed; otherwise a temporary register. See notes.
+r17 IP1     The second intra-procedure-call temporary register (can be used by call veneers and PLT code); at other times may be used as a temporary register.
+r16 IP0     The first intra-procedure-call scratch register (can be used by call veneers and PLT code); at other times may be used as a temporary register.
+r9…r15      Temporary registers
+r8          Indirect result location register
+r0…r7       Parameter/result registers
+
+For SIMD:
+The first eight registers, v0-v7, are used to pass argument values into a subroutine and to return result values from a function. 
+    They may also be used to hold intermediate values within a routine (but, in general, only between subroutine calls).
+
+Registers v8-v15 must be preserved by a callee across subroutine calls; 
+    the remaining registers (v0-v7, v16-v31) do not need to be preserved (or should be preserved by the caller).
+    Additionally, only the bottom 64 bits of each value stored in v8-v15 need to be preserved [8];
+    it is the responsibility of the caller to preserve larger values.
+
+For SVE:
+z0-z7 are used to pass scalable vector arguments to a subroutine, and to return scalable vector results from a function.
+    If a subroutine takes at least one argument in scalable vector registers or scalable predicate registers,
+    or returns results in such regisers, the subroutine must ensure that the entire contents of z8-z23 are preserved across the call.
+    In other cases it need only preserve the low 64 bits of z8-z15, as described in SIMD and Floating-Point registers.
+p0-p3 are used to pass scalable predicate arguments to a subroutine and to return scalable predicate results from a function.
+    If a subroutine takes at least one argument in scalable vector registers or scalable predicate registers,
+    or returns results in such registers, the subroutine must ensure that p4-p15 are preserved across the call.
+    In other cases it need not preserve any scalable predicate register contents.
+
+*/
+
 // x86 Register mapping
 #define xRAX    10
 #define xRCX    11
@@ -25,6 +60,10 @@
 #define xFlags  26
 #define xRIP    27
 #define xSavedSP 28
+
+// convert a x86 register to native according to the register mapping
+#define TO_NAT(A) (xRAX + (A))
+
 // 32bits version
 #define wEAX    xRAX
 #define wECX    xRCX
@@ -70,24 +109,46 @@
 #define wZR     xZR

 // conditions
+// Z == 1
 #define cEQ 0b0000
+// Z != 1
 #define cNE 0b0001
+// C == 1
 #define cCS 0b0010
+// C == 1
 #define cHS cCS
+// C != 1
 #define cCC 0b0011
+// C != 1
 #define cLO cCC
+// N == 1
 #define cMI 0b0100
+// N != 1
 #define cPL 0b0101
+// V == 1
 #define cVS 0b0110
+// V != 1
 #define cVC 0b0111
+// C == 1 && Z == 0
 #define cHI 0b1000
+// C !=1 || Z == 1
 #define cLS 0b1001
+// N == V
 #define cGE 0b1010
+// N != V
 #define cLT 0b1011
+// N == V && Z == 0
 #define cGT 0b1100
+// N != V || Z == 1
 #define cLE 0b1101
+// always
 #define c__ 0b1110

+int convert_bitmask(uint64_t bitmask);
+#define convert_bitmask_w(A)    convert_bitmask(((uint64_t)(A) << 32) + (uint32_t)(A))
+#define convert_bitmask_x(A)    convert_bitmask((uint64_t)A)
+#define convert_bitmask_xw(A)   convert_bitmask(rex.w?((uint64_t)(A)):(((uint64_t)(A) << 32) + (uint32_t)(A)))
+
 #define invCond(cond)   ((cond)^0b0001)

 // MOVZ
@@ -111,23 +172,8 @@
 #define MOVKw(Rd, imm16)                    EMIT(MOVK_gen(0, 0, ((uint16_t)(imm16))&0xffff, Rd))
 #define MOVKw_LSL(Rd, imm16, shift)         EMIT(MOVK_gen(0, (shift)/16, ((uint16_t)(imm16))&0xffff, Rd))

-// This macro will give a -Wsign-compare warning, probably bug #38341
-#define MOV32w(Rd, imm32) \
-    if(~((uint32_t)(imm32))<0xffffu) {                                      \
-        MOVNw(Rd, (~(uint32_t)(imm32))&0xffff);                             \
-    } else {                                                                \
-        MOVZw(Rd, (imm32)&0xffff);                                          \
-        if((imm32)&0xffff0000) {MOVKw_LSL(Rd, ((imm32)>>16)&0xffff, 16);}   \
-    }
-#define MOV64x(Rd, imm64) \
-    if(~((uint64_t)(imm64))<0xffff) {                                                                       \
-        MOVNx(Rd, (~(uint64_t)(imm64))&0xffff);                                                             \
-    } else {                                                                                                \
-        MOVZx(Rd, ((uint64_t)(imm64))&0xffff);                                                              \
-        if(((uint64_t)(imm64))&0xffff0000) {MOVKx_LSL(Rd, (((uint64_t)(imm64))>>16)&0xffff, 16);}           \
-        if(((uint64_t)(imm64))&0xffff00000000LL) {MOVKx_LSL(Rd, (((uint64_t)(imm64))>>32)&0xffff, 32);}      \
-        if(((uint64_t)(imm64))&0xffff000000000000LL) {MOVKx_LSL(Rd, (((uint64_t)(imm64))>>48)&0xffff, 48);}  \
-    }
+#define MOV32w(Rd, imm32) arm64_move32(dyn, ninst, Rd, imm32)
+#define MOV64x(Rd, imm64) arm64_move64(dyn, ninst, Rd, imm64)

 #define MOV64xw(Rd, imm64)   if(rex.w) {MOV64x(Rd, imm64);} else {MOV32w(Rd, imm64);}
 #define MOV64z(Rd, imm64)    if(rex.is32bits) {MOV32w(Rd, imm64);} else {MOV64x(Rd, imm64);}
@@ -136,35 +182,37 @@
 // ADD / SUB
 #define ADDSUB_REG_gen(sf, op, S, shift, Rm, imm6, Rn, Rd) ((sf)<<31 | (op)<<30 | (S)<<29 | 0b01011<<24 | (shift)<<22 | (Rm)<<16 | (imm6)<<10 | (Rn)<<5 | (Rd))
 #define ADDx_REG(Rd, Rn, Rm)                EMIT(ADDSUB_REG_gen(1, 0, 0, 0b00, Rm, 0, Rn, Rd))
-#define ADDSx_REG(Rd, Rn, Rm)               EMIT(ADDSUB_REG_gen(1, 0, 1, 0b00, Rm, 0, Rn, Rd))
+#define ADDSx_REG(Rd, Rn, Rm)              FEMIT(ADDSUB_REG_gen(1, 0, 1, 0b00, Rm, 0, Rn, Rd))
 #define ADDx_REG_LSL(Rd, Rn, Rm, lsl)       EMIT(ADDSUB_REG_gen(1, 0, 0, 0b00, Rm, lsl, Rn, Rd))
+#define ADDz_REG_LSL(Rd, Rn, Rm, lsl)       EMIT(ADDSUB_REG_gen(rex.is32bits?0:1, 0, 0, 0b00, Rm, lsl, Rn, Rd))
 #define ADDw_REG(Rd, Rn, Rm)                EMIT(ADDSUB_REG_gen(0, 0, 0, 0b00, Rm, 0, Rn, Rd))
-#define ADDSw_REG(Rd, Rn, Rm)               EMIT(ADDSUB_REG_gen(0, 0, 1, 0b00, Rm, 0, Rn, Rd))
+#define ADDSw_REG(Rd, Rn, Rm)              FEMIT(ADDSUB_REG_gen(0, 0, 1, 0b00, Rm, 0, Rn, Rd))
 #define ADDw_REG_LSL(Rd, Rn, Rm, lsl)       EMIT(ADDSUB_REG_gen(0, 0, 0, 0b00, Rm, lsl, Rn, Rd))
+#define ADDSw_REG_LSL(Rd, Rn, Rm, lsl)     FEMIT(ADDSUB_REG_gen(0, 0, 1, 0b00, Rm, lsl, Rn, Rd))
 #define ADDxw_REG(Rd, Rn, Rm)               EMIT(ADDSUB_REG_gen(rex.w, 0, 0, 0b00, Rm, 0, Rn, Rd))
 #define ADDz_REG(Rd, Rn, Rm)                EMIT(ADDSUB_REG_gen(rex.is32bits?0:1, 0, 0, 0b00, Rm, 0, Rn, Rd))
-#define ADDSxw_REG(Rd, Rn, Rm)              EMIT(ADDSUB_REG_gen(rex.w, 0, 1, 0b00, Rm, 0, Rn, Rd))
+#define ADDSxw_REG(Rd, Rn, Rm)             FEMIT(ADDSUB_REG_gen(rex.w, 0, 1, 0b00, Rm, 0, Rn, Rd))
 #define ADDxw_REG_LSR(Rd, Rn, Rm, lsr)      EMIT(ADDSUB_REG_gen(rex.w, 0, 0, 0b01, Rm, lsr, Rn, Rd))

 #define ADDSUB_IMM_gen(sf, op, S, shift, imm12, Rn, Rd)    ((sf)<<31 | (op)<<30 | (S)<<29 | 0b10001<<24 | (shift)<<22 | (imm12)<<10 | (Rn)<<5 | (Rd))
 #define ADDx_U12(Rd, Rn, imm12)     EMIT(ADDSUB_IMM_gen(1, 0, 0, 0b00, (imm12)&0xfff, Rn, Rd))
-#define ADDSx_U12(Rd, Rn, imm12)    EMIT(ADDSUB_IMM_gen(1, 0, 1, 0b00, (imm12)&0xfff, Rn, Rd))
+#define ADDSx_U12(Rd, Rn, imm12)   FEMIT(ADDSUB_IMM_gen(1, 0, 1, 0b00, (imm12)&0xfff, Rn, Rd))
 #define ADDw_U12(Rd, Rn, imm12)     EMIT(ADDSUB_IMM_gen(0, 0, 0, 0b00, (imm12)&0xfff, Rn, Rd))
-#define ADDSw_U12(Rd, Rn, imm12)    EMIT(ADDSUB_IMM_gen(0, 0, 1, 0b00, (imm12)&0xfff, Rn, Rd))
+#define ADDSw_U12(Rd, Rn, imm12)   FEMIT(ADDSUB_IMM_gen(0, 0, 1, 0b00, (imm12)&0xfff, Rn, Rd))
 #define ADDxw_U12(Rd, Rn, imm12)    EMIT(ADDSUB_IMM_gen(rex.w, 0, 0, 0b00, (imm12)&0xfff, Rn, Rd))
-#define ADDSxw_U12(Rd, Rn, imm12)   EMIT(ADDSUB_IMM_gen(rex.w, 0, 1, 0b00, (imm12)&0xfff, Rn, Rd))
+#define ADDSxw_U12(Rd, Rn, imm12)  FEMIT(ADDSUB_IMM_gen(rex.w, 0, 1, 0b00, (imm12)&0xfff, Rn, Rd))
 #define ADDz_U12(Rd, Rn, imm12)     EMIT(ADDSUB_IMM_gen(rex.is32bits?0:1, 0, 0, 0b00, (imm12)&0xfff, Rn, Rd))

 #define SUBx_REG(Rd, Rn, Rm)                EMIT(ADDSUB_REG_gen(1, 1, 0, 0b00, Rm, 0, Rn, Rd))
-#define SUBSx_REG(Rd, Rn, Rm)               EMIT(ADDSUB_REG_gen(1, 1, 1, 0b00, Rm, 0, Rn, Rd))
+#define SUBSx_REG(Rd, Rn, Rm)              FEMIT(ADDSUB_REG_gen(1, 1, 1, 0b00, Rm, 0, Rn, Rd))
 #define SUBx_REG_LSL(Rd, Rn, Rm, lsl)       EMIT(ADDSUB_REG_gen(1, 1, 0, 0b00, Rm, lsl, Rn, Rd))
 #define SUBw_REG(Rd, Rn, Rm)                EMIT(ADDSUB_REG_gen(0, 1, 0, 0b00, Rm, 0, Rn, Rd))
 #define SUBw_REG_LSL(Rd, Rn, Rm, lsl)       EMIT(ADDSUB_REG_gen(0, 1, 0, 0b00, Rm, lsl, Rn, Rd))
-#define SUBSw_REG(Rd, Rn, Rm)               EMIT(ADDSUB_REG_gen(0, 1, 1, 0b00, Rm, 0, Rn, Rd))
-#define SUBSw_REG_LSL(Rd, Rn, Rm, lsl)      EMIT(ADDSUB_REG_gen(0, 1, 1, 0b00, Rm, lsl, Rn, Rd))
+#define SUBSw_REG(Rd, Rn, Rm)              FEMIT(ADDSUB_REG_gen(0, 1, 1, 0b00, Rm, 0, Rn, Rd))
+#define SUBSw_REG_LSL(Rd, Rn, Rm, lsl)     FEMIT(ADDSUB_REG_gen(0, 1, 1, 0b00, Rm, lsl, Rn, Rd))
 #define SUBxw_REG(Rd, Rn, Rm)               EMIT(ADDSUB_REG_gen(rex.w, 1, 0, 0b00, Rm, 0, Rn, Rd))
 #define SUBz_REG(Rd, Rn, Rm)                EMIT(ADDSUB_REG_gen(rex.is32bits?0:1, 1, 0, 0b00, Rm, 0, Rn, Rd))
-#define SUBSxw_REG(Rd, Rn, Rm)              EMIT(ADDSUB_REG_gen(rex.w, 1, 1, 0b00, Rm, 0, Rn, Rd))
+#define SUBSxw_REG(Rd, Rn, Rm)             FEMIT(ADDSUB_REG_gen(rex.w, 1, 1, 0b00, Rm, 0, Rn, Rd))
 #define CMPSx_REG(Rn, Rm)                   SUBSx_REG(xZR, Rn, Rm)
 #define CMPSw_REG(Rn, Rm)                   SUBSw_REG(wZR, Rn, Rm)
 #define CMPSxw_REG(Rn, Rm)                  SUBSxw_REG(xZR, Rn, Rm)
@@ -176,12 +224,12 @@
 #define NEGSxw_REG(Rd, Rm)                  SUBSxw_REG(Rd, xZR, Rm);

 #define SUBx_U12(Rd, Rn, imm12)     EMIT(ADDSUB_IMM_gen(1, 1, 0, 0b00, (imm12)&0xfff, Rn, Rd))
-#define SUBSx_U12(Rd, Rn, imm12)    EMIT(ADDSUB_IMM_gen(1, 1, 1, 0b00, (imm12)&0xfff, Rn, Rd))
+#define SUBSx_U12(Rd, Rn, imm12)   FEMIT(ADDSUB_IMM_gen(1, 1, 1, 0b00, (imm12)&0xfff, Rn, Rd))
 #define SUBw_U12(Rd, Rn, imm12)     EMIT(ADDSUB_IMM_gen(0, 1, 0, 0b00, (imm12)&0xfff, Rn, Rd))
-#define SUBSw_U12(Rd, Rn, imm12)    EMIT(ADDSUB_IMM_gen(0, 1, 1, 0b00, (imm12)&0xfff, Rn, Rd))
+#define SUBSw_U12(Rd, Rn, imm12)   FEMIT(ADDSUB_IMM_gen(0, 1, 1, 0b00, (imm12)&0xfff, Rn, Rd))
 #define SUBxw_U12(Rd, Rn, imm12)    EMIT(ADDSUB_IMM_gen(rex.w, 1, 0, 0b00, (imm12)&0xfff, Rn, Rd))
 #define SUBz_U12(Rd, Rn, imm12)     EMIT(ADDSUB_IMM_gen(rex.is32bits?0:1, 1, 0, 0b00, (imm12)&0xfff, Rn, Rd))
-#define SUBSxw_U12(Rd, Rn, imm12)   EMIT(ADDSUB_IMM_gen(rex.w, 1, 1, 0b00, (imm12)&0xfff, Rn, Rd))
+#define SUBSxw_U12(Rd, Rn, imm12)  FEMIT(ADDSUB_IMM_gen(rex.w, 1, 1, 0b00, (imm12)&0xfff, Rn, Rd))
 #define CMPSx_U12(Rn, imm12)        SUBSx_U12(xZR, Rn, imm12)
 #define CMPSw_U12(Rn, imm12)        SUBSw_U12(wZR, Rn, imm12)
 #define CMPSxw_U12(Rn, imm12)       SUBSxw_U12(xZR, Rn, imm12)
@@ -193,18 +241,18 @@
 #define SBCx_REG(Rd, Rn, Rm)        EMIT(ADDSUBC_gen(1, 1, 0, Rm, Rn, Rd))
 #define SBCw_REG(Rd, Rn, Rm)        EMIT(ADDSUBC_gen(0, 1, 0, Rm, Rn, Rd))
 #define SBCxw_REG(Rd, Rn, Rm)       EMIT(ADDSUBC_gen(rex.w, 1, 0, Rm, Rn, Rd))
-#define ADCSx_REG(Rd, Rn, Rm)       EMIT(ADDSUBC_gen(1, 0, 1, Rm, Rn, Rd))
-#define ADCSw_REG(Rd, Rn, Rm)       EMIT(ADDSUBC_gen(0, 0, 1, Rm, Rn, Rd))
-#define ADCSxw_REG(Rd, Rn, Rm)      EMIT(ADDSUBC_gen(rex.w, 0, 1, Rm, Rn, Rd))
-#define SBCSx_REG(Rd, Rn, Rm)       EMIT(ADDSUBC_gen(1, 1, 1, Rm, Rn, Rd))
-#define SBCSw_REG(Rd, Rn, Rm)       EMIT(ADDSUBC_gen(0, 1, 1, Rm, Rn, Rd))
-#define SBCSxw_REG(Rd, Rn, Rm)      EMIT(ADDSUBC_gen(rex.w, 1, 1, Rm, Rn, Rd))
+#define ADCSx_REG(Rd, Rn, Rm)      FEMIT(ADDSUBC_gen(1, 0, 1, Rm, Rn, Rd))
+#define ADCSw_REG(Rd, Rn, Rm)      FEMIT(ADDSUBC_gen(0, 0, 1, Rm, Rn, Rd))
+#define ADCSxw_REG(Rd, Rn, Rm)     FEMIT(ADDSUBC_gen(rex.w, 0, 1, Rm, Rn, Rd))
+#define SBCSx_REG(Rd, Rn, Rm)      FEMIT(ADDSUBC_gen(1, 1, 1, Rm, Rn, Rd))
+#define SBCSw_REG(Rd, Rn, Rm)      FEMIT(ADDSUBC_gen(0, 1, 1, Rm, Rn, Rd))
+#define SBCSxw_REG(Rd, Rn, Rm)     FEMIT(ADDSUBC_gen(rex.w, 1, 1, Rm, Rn, Rd))

 // CCMP compare if cond is true, set nzcv if false
 #define CCMP_reg(sf, Rm, cond, Rn, nzcv)    ((sf)<<31 | 1<<30 | 1<<29 | 0b11010010<<21 | (Rm)<<16 | (cond)<<12 | (Rn)<<5 | (nzcv))
-#define CCMPw(Wn, Wm, nzcv, cond)   EMIT(CCMP_reg(0, Wm, cond, Wn, nzcv))
-#define CCMPx(Xn, Xm, nzcv, cond)   EMIT(CCMP_reg(1, Xm, cond, Xn, nzcv))
-#define CCMPxw(Xn, Xm, nzcv, cond)  EMIT(CCMP_reg(rex.w, Xm, cond, Xn, nzcv))
+#define CCMPw(Wn, Wm, nzcv, cond)  FEMIT(CCMP_reg(0, Wm, cond, Wn, nzcv))
+#define CCMPx(Xn, Xm, nzcv, cond)  FEMIT(CCMP_reg(1, Xm, cond, Xn, nzcv))
+#define CCMPxw(Xn, Xm, nzcv, cond) FEMIT(CCMP_reg(rex.w, Xm, cond, Xn, nzcv))

 // ADR
 #define ADR_gen(immlo, immhi, Rd)   ((immlo)<<29 | 0b10000<<24 | (immhi)<<5 | (Rd))
@@ -241,13 +289,19 @@
 #define LDRx_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(0b11, Rm, 0b011, 0, Rn, Rt))
 #define LDRx_REG_LSL3(Rt, Rn, Rm)       EMIT(LDR_REG_gen(0b11, Rm, 0b011, 1, Rn, Rt))
 #define LDRx_REG_UXTW3(Rt, Rn, Rm)      EMIT(LDR_REG_gen(0b11, Rm, 0b010, 1, Rn, Rt))
+#define LDRx_REG_SXTW(Rt, Rn, Rm)       EMIT(LDR_REG_gen(0b11, Rm, 0b110, 0, Rn, Rt))
 #define LDRw_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(0b10, Rm, 0b011, 0, Rn, Rt))
 #define LDRw_REG_LSL2(Rt, Rn, Rm)       EMIT(LDR_REG_gen(0b10, Rm, 0b011, 1, Rn, Rt))
+#define LDRw_REG_SXTW(Rt, Rn, Rm)       EMIT(LDR_REG_gen(0b10, Rm, 0b110, 0, Rn, Rt))
 #define LDRxw_REG(Rt, Rn, Rm)           EMIT(LDR_REG_gen(0b10+rex.w, Rm, 0b011, 0, Rn, Rt))
 #define LDRz_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(rex.is32bits?0b10:0b11, Rm, 0b011, 0, Rn, Rt))
+#define LDRxw_REG_SXTW(Rt, Rn, Rm)      EMIT(LDR_REG_gen(0b10+rex.w, Rm, 0b110, 0, Rn, Rt))
+#define LDRz_REG_SXTW(Rt, Rn, Rm)       EMIT(LDR_REG_gen(rex.is32bits?0b10:0b11, Rm, 0b110, 0, Rn, Rt))
 #define LDRB_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(0b00, Rm, 0b011, 0, Rn, Rt))
 #define LDRB_REG_UXTW(Rt, Rn, Rm)       EMIT(LDR_REG_gen(0b00, Rm, 0b010, 0, Rn, Rt))
+#define LDRB_REG_SXTW(Rt, Rn, Rm)       EMIT(LDR_REG_gen(0b00, Rm, 0b110, 0, Rn, Rt))
 #define LDRH_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(0b01, Rm, 0b011, 0, Rn, Rt))
+#define LDRH_REG_SXTW(Rt, Rn, Rm)       EMIT(LDR_REG_gen(0b01, Rm, 0b110, 0, Rn, Rt))

 #define LDRS_U12_gen(size, op1, opc, imm12, Rn, Rt)    ((size)<<30 | 0b111<<27 | (op1)<<24 | (opc)<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
 #define LDRSHx_U12(Rt, Rn, imm12)           EMIT(LDRS_U12_gen(0b01, 0b01, 0b10, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
@@ -259,6 +313,7 @@

 #define LDRS_REG_gen(size, Rm, option, S, Rn, Rt)    ((size)<<30 | 0b111<<27 | 0b10<<22 | 1<<21 | (Rm)<<16 | (option)<<13 | (S)<<12 | (0b10)<<10 | (Rn)<<5 | (Rt))
 #define LDRSW_REG(Rt, Rn, Rm)           EMIT(LDRS_REG_gen(0b10, Rm, 0b011, 0, Rn, Rt))
+#define LDRSW_REG_SXTW(Rt, Rn, Rm)      EMIT(LDRS_REG_gen(0b10, Rm, 0b110, 0, Rn, Rt))

 #define LDR_PC_gen(opc, imm19, Rt)      ((opc)<<30 | 0b011<<27 | (imm19)<<5 | (Rt))
 #define LDRx_literal(Rt, imm19)         EMIT(LDR_PC_gen(0b01, ((imm19)>>2)&0x7FFFF, Rt))
@@ -329,12 +384,18 @@
 #define STRx_REG(Rt, Rn, Rm)            EMIT(STR_REG_gen(0b11, Rm, 0b011, 0, Rn, Rt))
 #define STRx_REG_LSL3(Rt, Rn, Rm)       EMIT(STR_REG_gen(0b11, Rm, 0b011, 1, Rn, Rt))
 #define STRx_REG_UXTW(Rt, Rn, Rm)       EMIT(STR_REG_gen(0b11, Rm, 0b010, 0, Rn, Rt))
+#define STRx_REG_SXTW(Rt, Rn, Rm)       EMIT(STR_REG_gen(0b11, Rm, 0b110, 0, Rn, Rt))
 #define STRw_REG(Rt, Rn, Rm)            EMIT(STR_REG_gen(0b10, Rm, 0b011, 0, Rn, Rt))
 #define STRw_REG_LSL2(Rt, Rn, Rm)       EMIT(STR_REG_gen(0b10, Rm, 0b011, 1, Rn, Rt))
+#define STRw_REG_SXTW(Rt, Rn, Rm)       EMIT(STR_REG_gen(0b10, Rm, 0b110, 0, Rn, Rt))
 #define STRB_REG(Rt, Rn, Rm)            EMIT(STR_REG_gen(0b00, Rm, 0b011, 0, Rn, Rt))
+#define STRB_REG_SXTW(Rt, Rn, Rm)       EMIT(STR_REG_gen(0b00, Rm, 0b110, 0, Rn, Rt))
 #define STRH_REG(Rt, Rn, Rm)            EMIT(STR_REG_gen(0b01, Rm, 0b011, 0, Rn, Rt))
+#define STRH_REG_SXTW(Rt, Rn, Rm)       EMIT(STR_REG_gen(0b01, Rm, 0b110, 0, Rn, Rt))
 #define STRxw_REG(Rt, Rn, Rm)           EMIT(STR_REG_gen(rex.w?0b11:0b10, Rm, 0b011, 0, Rn, Rt))
+#define STRxw_REG_SXTW(Rt, Rn, Rm)      EMIT(STR_REG_gen(rex.w?0b11:0b10, Rm, 0b110, 0, Rn, Rt))
 #define STRz_REG(Rt, Rn, Rm)            EMIT(STR_REG_gen(rex.is32bits?0b10:0b11, Rm, 0b011, 0, Rn, Rt))
+#define STRz_REG_SXTW(Rt, Rn, Rm)       EMIT(STR_REG_gen(rex.is32bits?0b10:0b11, Rm, 0b110, 0, Rn, Rt))

 // LOAD/STORE PAIR
 #define MEMPAIR_gen(size, L, op2, imm7, Rt2, Rn, Rt)    ((size)<<31 | 0b101<<27 | (op2)<<23 | (L)<<22 | (imm7)<<15 | (Rt2)<<10 | (Rn)<<5 | (Rt))
@@ -434,12 +495,19 @@
 // Data Memory Barrier
 #define DMB_gen(CRm)                    (0b1101010100<<22 | 0b011<<16 | 0b0011<<12 | (CRm)<<8 | 1<<7 | 0b01<<5 | 0b11111)
 #define DMB_ISH()                       EMIT(DMB_gen(0b1011))
+#define DMB_ISHLD()                     EMIT(DMB_gen(0b1001))
+#define DMB_ISHST()                     EMIT(DMB_gen(0b1010))
+#define DMB_LD()                        EMIT(DMB_gen(0b1101))
+#define DMB_ST()                        EMIT(DMB_gen(0b1110))
 #define DMB_SY()                        EMIT(DMB_gen(0b1111))

 // Data Synchronization Barrier
 #define DSB_gen(CRm)                    (0b1101010100<<22 | 0b011<<16 | 0b0011<<12 | (CRm)<<8 | 1<<7 | 0b00<<5 | 0b11111)
 #define DSB_ISH()                       EMIT(DSB_gen(0b1011))
+#define DSB_ISHLD()                     EMIT(DSB_gen(0b1001))
 #define DSB_ISHST()                     EMIT(DSB_gen(0b1010))
+#define DSB_LD()                        EMIT(DSB_gen(0b1101))
+#define DSB_ST()                        EMIT(DSB_gen(0b1110))
 #define DSB_SY()                        EMIT(DSB_gen(0b1111))

 // Break
@@ -450,6 +518,7 @@
 #define BR_gen(Z, op, A, M, Rn, Rm)       (0b1101011<<25 | (Z)<<24 | (op)<<21 | 0b11111<<16 | (A)<<11 | (M)<<10 | (Rn)<<5 | (Rm))
 #define BR(Rn)                            EMIT(BR_gen(0, 0b00, 0, 0, Rn, 0))
 #define BLR(Rn)                           EMIT(BR_gen(0, 0b01, 0, 0, Rn, 0))
+#define RET(Rn)                           EMIT(BR_gen(0, 0b10, 0, 0, Rn, 0))

 #define CB_gen(sf, op, imm19, Rt)       ((sf)<<31 | 0b011010<<25 | (op)<<24 | (imm19)<<5 | (Rt))
 #define CBNZx(Rt, imm19)                EMIT(CB_gen(1, 1, ((imm19)>>2)&0x7FFFF, Rt))
@@ -475,6 +544,10 @@
 #define BL(imm26)                       EMIT(BL_gen(((imm26)>>2)&0x3ffffff))

 #define NOP                             EMIT(0b11010101000000110010000000011111)
+#define WFE                             EMIT(0b11010101000000110010000001011111)
+#define WFI                             EMIT(0b11010101000000110010000001111111)
+#define YIELD                           EMIT(0b11010101000000110010000000111111)
+#define SEVL                            EMIT(0b11010101000000110010000010111111)

 #define CSINC_gen(sf, Rm, cond, Rn, Rd)     ((sf)<<31 | 0b11010100<<21 | (Rm)<<16 | (cond)<<12 | 1<<10 | (Rn)<<5 | (Rd))
 #define CSINCx(Rd, Rn, Rm, cond)            EMIT(CSINC_gen(1, Rm, cond, Rn, Rd))
@@ -513,22 +586,29 @@
 // logic to get the mask is ... convoluted... list of possible value there: https://gist.github.com/dinfuehr/51a01ac58c0b23e4de9aac313ed6a06a
 #define ANDx_mask(Rd, Rn, N, immr, imms)    EMIT(LOGIC_gen(1, 0b00, N, immr, imms, Rn, Rd))
 #define ANDw_mask(Rd, Rn, immr, imms)       EMIT(LOGIC_gen(0, 0b00, 0, immr, imms, Rn, Rd))
-#define ANDSx_mask(Rd, Rn, N, immr, imms)   EMIT(LOGIC_gen(1, 0b11, N, immr, imms, Rn, Rd))
-#define ANDSw_mask(Rd, Rn, immr, imms)      EMIT(LOGIC_gen(0, 0b11, 0, immr, imms, Rn, Rd))
+#define ANDxw_mask(Rd, Rn, N, immr, imms)   EMIT(LOGIC_gen(rex.w, 0b00, rex.w?(N):0, immr, imms, Rn, Rd))
+#define ANDSx_mask(Rd, Rn, N, immr, imms)  FEMIT(LOGIC_gen(1, 0b11, N, immr, imms, Rn, Rd))
+#define ANDSw_mask(Rd, Rn, immr, imms)     FEMIT(LOGIC_gen(0, 0b11, 0, immr, imms, Rn, Rd))
+#define ANDSxw_mask(Rd, Rn, N, immr, imms) FEMIT(LOGIC_gen(rex.w, 0b11, rex.w?(N):0, immr, imms, Rn, Rd))
 #define ORRx_mask(Rd, Rn, N, immr, imms)    EMIT(LOGIC_gen(1, 0b01, N, immr, imms, Rn, Rd))
 #define ORRw_mask(Rd, Rn, immr, imms)       EMIT(LOGIC_gen(0, 0b01, 0, immr, imms, Rn, Rd))
+#define ORRxw_mask(Rd, Rn, N, immr, imms)   EMIT(LOGIC_gen(rex.w, 0b01, rex.w?(N):0, immr, imms, Rn, Rd))
 #define EORx_mask(Rd, Rn, N, immr, imms)    EMIT(LOGIC_gen(1, 0b10, N, immr, imms, Rn, Rd))
 #define EORw_mask(Rd, Rn, immr, imms)       EMIT(LOGIC_gen(0, 0b10, 0, immr, imms, Rn, Rd))
+#define EORxw_mask(Rd, Rn, N, immr, imms)   EMIT(LOGIC_gen(rex.w, 0b10, rex.w?(N):0, immr, imms, Rn, Rd))
 #define TSTx_mask(Rn, N, immr, imms)        ANDSx_mask(xZR, Rn, N, immr, imms)
 #define TSTw_mask(Rn, immr, imms)           ANDSw_mask(wZR, Rn, immr, imms)
+#define TSTxw_mask(Rn, N, immr, imms)       ANDSxw_mask(xZR, Rn, N, immr, imms)

 #define LOGIC_REG_gen(sf, opc, shift, N, Rm, imm6, Rn, Rd)    ((sf)<<31 | (opc)<<29 | 0b01010<<24 | (shift)<<22 | (N)<<21 | (Rm)<<16 | (imm6)<<10 | (Rn)<<5 | (Rd))
 #define ANDx_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(1, 0b00, 0b00, 0, Rm, 0, Rn, Rd))
 #define ANDw_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(0, 0b00, 0b00, 0, Rm, 0, Rn, Rd))
+#define ANDw_REG_LSR(Rd, Rn, Rm, lsr)   EMIT(LOGIC_REG_gen(0, 0b00, 0b01, 0, Rm, lsr, Rn, Rd))
 #define ANDxw_REG(Rd, Rn, Rm)           EMIT(LOGIC_REG_gen(rex.w, 0b00, 0b00, 0, Rm, 0, Rn, Rd))
-#define ANDSx_REG(Rd, Rn, Rm)           EMIT(LOGIC_REG_gen(1, 0b11, 0b00, 0, Rm, 0, Rn, Rd))
-#define ANDSw_REG(Rd, Rn, Rm)           EMIT(LOGIC_REG_gen(0, 0b11, 0b00, 0, Rm, 0, Rn, Rd))
-#define ANDSxw_REG(Rd, Rn, Rm)          EMIT(LOGIC_REG_gen(rex.w, 0b11, 0b00, 0, Rm, 0, Rn, Rd))
+#define ANDSx_REG(Rd, Rn, Rm)          FEMIT(LOGIC_REG_gen(1, 0b11, 0b00, 0, Rm, 0, Rn, Rd))
+#define ANDSw_REG(Rd, Rn, Rm)          FEMIT(LOGIC_REG_gen(0, 0b11, 0b00, 0, Rm, 0, Rn, Rd))
+#define ANDSxw_REG(Rd, Rn, Rm)         FEMIT(LOGIC_REG_gen(rex.w, 0b11, 0b00, 0, Rm, 0, Rn, Rd))
+#define ANDSw_REG_LSL(Rd, Rn, Rm, lsl) FEMIT(LOGIC_REG_gen(0, 0b11, 0b00, 0, Rm, lsl, Rn, Rd))
 #define ORRx_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(1, 0b01, 0b00, 0, Rm, 0, Rn, Rd))
 #define ORRx_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(1, 0b01, 0b00, 0, Rm, lsl, Rn, Rd))
 #define ORRw_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(0, 0b01, 0b00, 0, Rm, lsl, Rn, Rd))
@@ -579,10 +659,10 @@
 #define BICx(Rd, Rn, Rm)                EMIT(LOGIC_REG_gen(1, 0b00, 0b00, 1, Rm, 0, Rn, Rd))
 #define BICw(Rd, Rn, Rm)                EMIT(LOGIC_REG_gen(0, 0b00, 0b00, 1, Rm, 0, Rn, Rd))
 #define BICw_LSL(Rd, Rn, Rm, lsl)       EMIT(LOGIC_REG_gen(0, 0b00, 0b00, 1, Rm, lsl, Rn, Rd))
-#define BICSx(Rd, Rn, Rm)               EMIT(LOGIC_REG_gen(1, 0b00, 0b00, 1, Rm, 0, Rn, Rd))
-#define BICSw(Rd, Rn, Rm)               EMIT(LOGIC_REG_gen(0, 0b00, 0b00, 1, Rm, 0, Rn, Rd))
-#define BICxw(Rd, Rn, Rm)               EMIT(LOGIC_REG_gen(rex.w, 0b00, 0b00, 1, Rm, 0, Rn, Rd))
-#define BICSxw(Rd, Rn, Rm)              EMIT(LOGIC_REG_gen(rex.w, 0b00, 0b00, 1, Rm, 0, Rn, Rd))
+#define BICSx(Rd, Rn, Rm)              FEMIT(LOGIC_REG_gen(1, 0b11, 0b00, 1, Rm, 0, Rn, Rd))
+#define BICSw(Rd, Rn, Rm)              FEMIT(LOGIC_REG_gen(0, 0b11, 0b00, 1, Rm, 0, Rn, Rd))
+#define BICxw(Rd, Rn, Rm)              FEMIT(LOGIC_REG_gen(rex.w, 0b00, 0b00, 1, Rm, 0, Rn, Rd))
+#define BICSxw(Rd, Rn, Rm)             FEMIT(LOGIC_REG_gen(rex.w, 0b11, 0b00, 1, Rm, 0, Rn, Rd))
 #define BICx_REG    BICx
 #define BICw_REG    BICw
 #define BICxw_REG   BICxw
@@ -610,6 +690,7 @@
 #define BFIx(Rd, Rn, lsb, width)        BFMx(Rd, Rn, ((-(lsb))%64)&0x3f, (width)-1)
 #define BFIw(Rd, Rn, lsb, width)        BFMw(Rd, Rn, ((-(lsb))%32)&0x1f, (width)-1)
 #define BFIxw(Rd, Rn, lsb, width)       if(rex.w) {BFIx(Rd, Rn, lsb, width);} else {BFIw(Rd, Rn, lsb, width);}
+#define BFIz(Rd, Rn, lsb, width)        if(rex.is32bits) {BFIw(Rd, Rn, lsb, width);} else {BFIx(Rd, Rn, lsb, width);}
 #define BFCx(Rd, lsb, width)            BFMx(Rd, xZR, ((-(lsb))%64)&0x3f, (width)-1)
 #define BFCw(Rd, lsb, width)            BFMw(Rd, xZR, ((-(lsb))%32)&0x1f, (width)-1)
 #define BFCxw(Rd, lsb, width)           BFMxw(Rd, xZR, rex.w?(((-(lsb))%64)&0x3f):(((-(lsb))%32)&0x1f), (width)-1)
@@ -757,15 +838,21 @@
 #define MRS_gen(L, o0, op1, CRn, CRm, op2, Rt)  (0b1101010100<<22 | (L)<<21 | 1<<20 | (o0)<<19 | (op1)<<16 | (CRn)<<12 | (CRm)<<8 | (op2)<<5 | (Rt))
 // mrs    x0, nzcv : 1101010100 1 1 1 011 0100 0010 000 00000    o0=1(op0=3), op1=0b011(3) CRn=0b0100(4) CRm=0b0010(2) op2=0
 // MRS : from System register
-#define MRS_nzvc(Rt)                    EMIT(MRS_gen(1, 1, 3, 4, 2, 0, Rt))
+#define MRS_nzcv(Rt)                    EMIT(MRS_gen(1, 1, 3, 4, 2, 0, Rt))
 // MSR : to System register
-#define MSR_nzvc(Rt)                    EMIT(MRS_gen(0, 1, 3, 4, 2, 0, Rt))
+#define MSR_nzcv(Rt)                   FEMIT(MRS_gen(0, 1, 3, 4, 2, 0, Rt))
 // mrs    x0, fpcr : 1101010100 1 1 1 011 0100 0100 000 00000    o0=1(op0=3), op1=0b011(3) CRn=0b0100(4) CRm=0b0100(4) op2=0
 #define MRS_fpcr(Rt)                    EMIT(MRS_gen(1, 1, 3, 4, 4, 0, Rt))
 #define MSR_fpcr(Rt)                    EMIT(MRS_gen(0, 1, 3, 4, 4, 0, Rt))
 // mrs    x0, fpsr : 1101010100 1 1 1 011 0100 0100 001 00000    o0=1(op0=3), op1=0b011(3) CRn=0b0100(4) CRm=0b0100(4) op2=1
 #define MRS_fpsr(Rt)                    EMIT(MRS_gen(1, 1, 3, 4, 4, 1, Rt))
 #define MSR_fpsr(Rt)                    EMIT(MRS_gen(0, 1, 3, 4, 4, 1, Rt))
+// mrs   x0, cntvct_el0     op0=0b11 op1=0b011 CRn=0b1110 CRm=0b0000 op2=0b010
+#define MRS_cntvct_el0(Rt)              EMIT(MRS_gen(1, 1, 0b011, 0b1110, 0b0000, 0b010, Rt))
+// mrs   x0, cntpctss_el0   op0=0b11 op1=0b011 CRn=0b1110 CRm=0b0000 op2=0b101
+#define MRS_cntpctss_el0(Rt)            EMIT(MRS_gen(1, 1, 0b011, 0b1110, 0b0000, 0b101, Rt))
+// mrs   rt, rndr           op0=0b11 op1=0b011 CRn=0b0010 CRm=0b0100 op2=0b000
+#define MRS_rndr(Rt)                    EMIT(MRS_gen(1, 1, 0b011, 0b0010, 0b0100, 0b000, Rt))
 // NEON Saturation Bit
 #define FPSR_QC 27
 // NEON Input Denormal Cumulative
@@ -780,6 +867,14 @@
 #define FPSR_DZC    1
 // NEON Invalid Operation Cumulative
 #define FPSR_IOC    0
+// NZCV N
+#define NZCV_N      31
+// NZCV Z
+#define NZCV_Z      30
+// NZCV C
+#define NZCV_C      29
+// NZCV V
+#define NZCV_V      28
                     
 // FCSEL
 #define FCSEL_scalar(type, Rm, cond, Rn, Rd)    (0b11110<<24 | (type)<<22 | 1<<21 | (Rm)<<16 | (cond)<<12 | 0b11<<10 | (Rn)<<5 | (Rd))
@@ -841,18 +936,24 @@
 #define VMEM_REG_gen(size, opc, Rm, option, S, Rn, Rt)  ((size)<<30 | 0b111<<27 | 1<<26 | (opc)<<22 | 1<<21 | (Rm)<<16 | (option)<<13 | (S)<<12 | 0b10<<10 | (Rn)<<5 | (Rt))

 #define VLDR32_REG(Dt, Rn, Rm)              EMIT(VMEM_REG_gen(0b10, 0b01, Rm, 0b011, 0, Rn, Dt))
+#define VLDR32_REG_SXTW(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b10, 0b01, Rm, 0b110, 0, Rn, Dt))
 #define VLDR32_REG_LSL2(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b10, 0b01, Rm, 0b011, 1, Rn, Dt))
 #define VLDR64_REG(Dt, Rn, Rm)              EMIT(VMEM_REG_gen(0b11, 0b01, Rm, 0b011, 0, Rn, Dt))
+#define VLDR64_REG_SXTW(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b11, 0b01, Rm, 0b110, 0, Rn, Dt))
 #define VLDR64_REG_LSL3(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b11, 0b01, Rm, 0b011, 1, Rn, Dt))
 #define VLDR128_REG(Qt, Rn, Rm)             EMIT(VMEM_REG_gen(0b00, 0b11, Rm, 0b011, 0, Rn, Qt))
 #define VLDR128_REG_LSL4(Qt, Rn, Rm)        EMIT(VMEM_REG_gen(0b00, 0b11, Rm, 0b011, 1, Rn, Qt))
+#define VLDR128_REG_SXTW(Qt, Rn, Rm)        EMIT(VMEM_REG_gen(0b00, 0b11, Rm, 0b110, 0, Rn, Qt))

 #define VSTR32_REG(Dt, Rn, Rm)              EMIT(VMEM_REG_gen(0b10, 0b00, Rm, 0b011, 0, Rn, Dt))
 #define VSTR32_REG_LSL2(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b10, 0b00, Rm, 0b011, 1, Rn, Dt))
+#define VSTR32_REG_SXTW(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b10, 0b00, Rm, 0b110, 0, Rn, Dt))
 #define VSTR64_REG(Dt, Rn, Rm)              EMIT(VMEM_REG_gen(0b11, 0b00, Rm, 0b011, 0, Rn, Dt))
 #define VSTR64_REG_LSL3(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b11, 0b00, Rm, 0b011, 1, Rn, Dt))
+#define VSTR64_REG_SXTW(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b11, 0b00, Rm, 0b110, 0, Rn, Dt))
 #define VSTR128_REG(Qt, Rn, Rm)             EMIT(VMEM_REG_gen(0b00, 0b10, Rm, 0b011, 0, Rn, Qt))
 #define VSTR128_REG_LSL4(Qt, Rn, Rm)        EMIT(VMEM_REG_gen(0b00, 0b10, Rm, 0b011, 1, Rn, Qt))
+#define VSTR128_REG_SXTW(Qt, Rn, Rm)        EMIT(VMEM_REG_gen(0b00, 0b10, Rm, 0b110, 0, Rn, Qt))

 #define VLDR_PC_gen(opc, imm19, Rt)         ((opc)<<30 | 0b011<<27 | 1<<26 | (imm19)<<5 | (Rt))
 #define VLDR32_literal(Vt, imm19)           EMIT(VLDR_PC_gen(0b00, ((imm19)>>2)&0x7FFFF, Vt))
@@ -1062,6 +1163,12 @@
 #define VMOVHto(Wd, Vn, index)      EMIT(UMOV_gen(0, ((index)<<2) | 2, Vn, Wd))
 #define VMOVSto(Wd, Vn, index)      EMIT(UMOV_gen(0, ((index)<<3) | 4, Vn, Wd))

+#define SMOV_gen(Q, imm5, Rn, Rd)   ((Q)<<30 | 0b01110000<<21 | (imm5)<<16 | 0b01<<13 | 0<<12 | 1<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define SMOVQDto(Xd, Vn, index)     EMIT(SMOV_gen(1, ((index)<<4) | 8, Vn, Xd))
+#define SMOVQBto(Xd, Vn, index)     EMIT(SMOV_gen(1, ((index)<<1) | 1, Vn, Xd))
+#define SMOVQHto(Xd, Vn, index)     EMIT(SMOV_gen(1, ((index)<<2) | 2, Vn, Xd))
+#define SMOVQSto(Xd, Vn, index)     EMIT(SMOV_gen(1, ((index)<<3) | 4, Vn, Xd))
+
 #define MVN_vector(Q, Rn, Rd)       ((Q)<<30 | 1<<29 | 0b01110<<24 | 0b10000<<17 | 0b00101<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 #define VMVNQ(Rd, Rn)               EMIT(MVN_vector(1, Rn, Rd))

@@ -1132,6 +1239,13 @@
 #define FABSS(Sd, Sn)               EMIT(FNEGABS_scalar(0b00, 0b01, Sn, Sd))
 #define FABSD(Dd, Dn)               EMIT(FNEGABS_scalar(0b01, 0b01, Dn, Dd))

+#define FNEGABS_vector(Q, U, sz, Rn, Rd)    ((Q)<<30 | (U)<<29 | 0b01110<<24 | 1<<23 | (sz)<<22 | 0b10000<<17 | 0b01111<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define VFNEGS(Vd, Vn)              EMIT(FNEGABS_vector(0, 1, 0, Vn, Vd))
+#define VFNEGQS(Vd, Vn)             EMIT(FNEGABS_vector(1, 1, 0, Vn, Vd))
+#define VFNEGQD(Vd, Vn)             EMIT(FNEGABS_vector(1, 1, 1, Vn, Vd))
+#define VFABSS(Vd, Vn)              EMIT(FNEGABS_vector(0, 0, 0, Vn, Vd))
+#define VFABSQS(Vd, Vn)             EMIT(FNEGABS_vector(1, 0, 0, Vn, Vd))
+#define VFABSQD(Vd, Vn)             EMIT(FNEGABS_vector(1, 0, 1, Vn, Vd))

 // MUL
 #define FMUL_vector(Q, sz, Rm, Rn, Rd)  ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11011<<11 | 1<<10 | (Rn)<<5 | (Rd))
@@ -1143,11 +1257,6 @@
 #define FMULS(Sd, Sn, Sm)           EMIT(FMUL_scalar(0b00, Sm, Sn, Sd))
 #define FMULD(Dd, Dn, Dm)           EMIT(FMUL_scalar(0b01, Dm, Dn, Dd))

-#define FMLA_vector(Q, op, sz, Rm, Rn, Rd)	((Q)<<30 | 0b01110<<24 | (op)<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11001<<11 | 1<<10 | (Rn)<<5 | (Rd))
-#define VFMLAS(Sd, Sn, Sm)	        EMIT(FMLA_vector(0, 0, 0, Sm, Sn, Sd))
-#define VFMLAQS(Sd, Sn, Sm)	        EMIT(FMLA_vector(1, 0, 0, Sm, Sn, Sd))
-#define VFMLAQD(Dd, Dn, Dm)	        EMIT(FMLA_vector(1, 0, 1, Dm, Dn, Dd))
-
 // DIV
 #define FDIV_vector(Q, sz, Rm, Rn, Rd)  ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11111<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define VFDIVS(Sd, Sn, Sm)          EMIT(FDIV_vector(0, 0, Sm, Sn, Sd))
@@ -1190,10 +1299,10 @@

 // CMP
 #define FCMP_scalar(type, Rn, Rm, opc)  (0b11110<<24 | (type)<<22 | 1<<21 | (Rm)<<16 | 0b1000<<10 | (Rn)<<5 | (opc)<<3)
-#define FCMPS(Sn, Sm)               EMIT(FCMP_scalar(0b00, Sn, Sm, 0b00))
-#define FCMPD(Dn, Dm)               EMIT(FCMP_scalar(0b01, Dn, Dm, 0b00))
-#define FCMPS_0(Sn)                 EMIT(FCMP_scalar(0b00, 0, Sn, 0b01))
-#define FCMPD_0(Dn)                 EMIT(FCMP_scalar(0b01, 0, Dn, 0b01))
+#define FCMPS(Sn, Sm)              FEMIT(FCMP_scalar(0b00, Sn, Sm, 0b00))
+#define FCMPD(Dn, Dm)              FEMIT(FCMP_scalar(0b01, Dn, Dm, 0b00))
+#define FCMPS_0(Sn)                FEMIT(FCMP_scalar(0b00, Sn, 0, 0b01))
+#define FCMPD_0(Dn)                FEMIT(FCMP_scalar(0b01, Dn, 0, 0b01))

 // CVT
 #define FCVT_scalar(sf, type, rmode, opcode, Rn, Rd)    ((sf)<<31 | 0b11110<<24 | (type)<<22 | 1<<21 | (rmode)<<19 | (opcode)<<16 | (Rn)<<5 | (Rd))
@@ -1349,18 +1458,30 @@
 #define FCVTN(Vd, Vn)               EMIT(FCVTN_vector(0, 1, Vn, Vd))
 // Convert Vn from 2*Double to higher Vd as 2*float, use FPCR rounding
 #define FCVTN2(Vd, Vn)              EMIT(FCVTN_vector(1, 1, Vn, Vd))
+// Convert Vn from 2*Float to lower Vd as 2*float16 and clears the upper half, use FPCR rounding
+#define FCVTN16(Vd, Vn)             EMIT(FCVTN_vector(0, 0, Vn, Vd))
+// Convert Vn from 2*Float to higher Vd as 2*float16, use FPCR rounding
+#define FCVTN162(Vd, Vn)            EMIT(FCVTN_vector(1, 0, Vn, Vd))

 #define FCVTXN_vector(Q, sz, Rn, Rd)   ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b10110<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 // Convert Vn from 2*Double to lower Vd as 2*float and clears the upper half
 #define FCVTXN(Vd, Vn)              EMIT(FCVTXN_vector(0, 1, Vn, Vd))
 // Convert Vn from 2*Double to higher Vd as 2*float
 #define FCVTXN2(Vd, Vn)             EMIT(FCVTXN_vector(1, 1, Vn, Vd))
+// Convert Vn from 2*Float to lower Vd as 2*float16 and clears the upper half
+#define FCVTXN16(Vd, Vn)            EMIT(FCVTXN_vector(0, 0, Vn, Vd))
+// Convert Vn from 2*Float to higher Vd as 2*float16
+#define FCVTXN162(Vd, Vn)           EMIT(FCVTXN_vector(1, 0, Vn, Vd))

 #define FCVTL_vector(Q, sz, Rn, Rd)     ((Q)<<30 | 0<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b10111<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 // Convert lower Vn from 2*float to Vd as 2*double
 #define FCVTL(Vd, Vn)               EMIT(FCVTL_vector(0, 1, Vn, Vd))
 // Convert higher Vn from 2*float to Vd as 2*double
 #define FCVTL2(Vd, Vn)              EMIT(FCVTL_vector(1, 1, Vn, Vd))
+// Convert lower Vn from 2*float16 to Vd as 2*float
+#define FCVTL16(Vd, Vn)             EMIT(FCVTL_vector(0, 0, Vn, Vd))
+// Convert higher Vn from 2*float16 to Vd as 2*float
+#define FCVTL162(Vd, Vn)            EMIT(FCVTL_vector(1, 0, Vn, Vd))

 #define SCVTF_scalar(sf, type, rmode, opcode, Rn, Rd)   ((sf)<<31 | 0b11110<<24 | (type)<<22 | 1<<21 | (rmode)<<19 | (opcode)<<16 | (Rn)<<5 | (Rd))
 #define SCVTFSw(Sd, Wn)             EMIT(SCVTF_scalar(0, 0b00, 0b00, 0b010, Wn, Sd))
@@ -1432,6 +1553,37 @@
 // FMAXNM NaN vs Number: number is picked
 #define FMAXNMD(Dd, Dn, Dm)         EMIT(FMINMAX_scalar(0b01, Dm, 0b10, Dn, Dd))

+// Fused Add Multiply
+#define FMADD_gen(type, o1, Rm, o0, Ra, Rn, Rd) (0b11111<<24 | (type)<<22 | (o1)<<21 | (Rm)<<16 | (o0)<<15 | (Ra)<<10 | (Rn)<<5 | (Rd))
+// scalar Rd = Ra + Rn*Rm
+#define FMADD_32(Sd, Sa, Sn, Sm)    EMIT(FMADD_gen(0b00, 0, Sm, 0, Sa, Sn, Sd))
+// scalar Rd = Ra + Rn*Rm
+#define FMADD_64(Dd, Da, Dn, Dm)    EMIT(FMADD_gen(0b01, 0, Dm, 0, Da, Dn, Dd))
+// scalar Rd = -Ra - Rn*Rm
+#define FNMADD_32(Sd, Sa, Sn, Sm)   EMIT(FMADD_gen(0b00, 1, Sm, 0, Sa, Sn, Sd))
+// scalar Rd = -Ra - Rn*Rm
+#define FNMADD_64(Dd, Da, Dn, Dm)   EMIT(FMADD_gen(0b01, 1, Dm, 0, Da, Dn, Dd))
+// scalar Rd = Ra - Rn*Rm
+#define FMSUB_32(Sd, Sa, Sn, Sm)    EMIT(FMADD_gen(0b00, 0, Sm, 1, Sa, Sn, Sd))
+// scalar Rd = Ra - Rn*Rm
+#define FMSUB_64(Dd, Da, Dn, Dm)    EMIT(FMADD_gen(0b01, 0, Dm, 1, Da, Dn, Dd))
+// scalar Rd = -Ra + Rn*Rm
+#define FNMSUB_32(Sd, Sa, Sn, Sm)   EMIT(FMADD_gen(0b00, 1, Sm, 1, Sa, Sn, Sd))
+// scalar Rd = -Ra + Rn*Rm
+#define FNMSUB_64(Dd, Da, Dn, Dm)   EMIT(FMADD_gen(0b01, 1, Dm, 1, Da, Dn, Dd))
+
+#define FMLA_vector(Q, op, sz, Rm, Rn, Rd)  ((Q)<<30 | 0b01110<<24 | (op)<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11001<<11 | 1<<10 | (Rn)<<5 | (Rd))
+// Vd += Vn*Vm
+#define VFMLAS(Vd, Vn, Vm)          EMIT(FMLA_vector(0, 0, 0, Vm, Vn, Vd))
+// Vd += Vn*Vm
+#define VFMLAQS(Vd, Vn, Vm)         EMIT(FMLA_vector(1, 0, 0, Vm, Vn, Vd))
+// Vd += Vn*Vm
+#define VFMLAQD(Vd, Vn, Vm)         EMIT(FMLA_vector(1, 0, 1, Vm, Vn, Vd))
+// Vd -= Vn*Vm
+#define VFMLSQS(Vd, Vn, Vm)         EMIT(FMLA_vector(1, 1, 0, Vm, Vn, Vd))
+// Vd -= Vn*Vm
+#define VFMLSQD(Vd, Vn, Vm)         EMIT(FMLA_vector(1, 1, 1, Vm, Vn, Vd))
+
 // ZIP / UZP
 #define ZIP_gen(Q, size, Rm, op, Rn, Rd)    ((Q)<<30 | 0b001110<<24 | (size)<<22 | (Rm)<<16 | (op)<<14 | 0b11<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 #define VZIP1Q_8(Rt, Rn, Rm)        EMIT(ZIP_gen(1, 0b00, Rm, 0, Rn, Rt))
@@ -1465,6 +1617,16 @@
 #define VUZP1Q_64(Rt, Rn, Rm)       EMIT(UZP_gen(1, 0b11, Rm, 0, Rn, Rt))
 #define VUZP2Q_64(Rt, Rn, Rm)       EMIT(UZP_gen(1, 0b11, Rm, 1, Rn, Rt))

+#define BITBIF_gen(Q, opc2, Rm, Rn, Rd) ((Q)<<30 | 0b101110<<24 | (opc2)<<22 | 1<<21 | (Rm)<<16 | 0b000111<<10 | (Rn)<<5 | (Rd))
+// Bitwise insert Vn in Vd if Vm is "0"
+#define VBIF(Vd, Vn,Vm)             EMIT(BITBIF_gen(0, 0b11, Vm, Vn, Vd))
+// Bitwise insert Vn in Vd if Vm is "0"
+#define VBIFQ(Vd, Vn,Vm)            EMIT(BITBIF_gen(1, 0b11, Vm, Vn, Vd))
+// Bitwise insert Vn in Vd if Vm is "1"
+#define VBIT(Vd, Vn,Vm)             EMIT(BITBIF_gen(0, 0b10, Vm, Vn, Vd))
+// Bitwise insert Vn in Vd if Vm is "1"
+#define VBITQ(Vd, Vn,Vm)            EMIT(BITBIF_gen(1, 0b10, Vm, Vn, Vd))
+
 #define DUP_element(Q, imm5, Rn, Rd)    ((Q)<<30 | 0b01110000<<21 | (imm5)<<16 | 1<<10 | (Rn)<<5 | (Rd))
 #define VDUP_8(Vd, Vn, idx)         EMIT(DUP_element(0, ((idx)<<1|1), Vn, Vd))
 #define VDUPQ_8(Vd, Vn, idx)        EMIT(DUP_element(1, ((idx)<<1|1), Vn, Vd))
@@ -1563,6 +1725,15 @@
 // Signed saturating extract Unsigned Narrow, takes Rn element and reduce 16->8 with Unsigned saturation and fit higher part of Rd
 #define SQXTUN2_8(Rd, Rn)           EMIT(QXTUN_vector(1, 1, 0b00, Rn, Rd))

+#define XTN_vector(Q, size, Rn, Rd) ((Q)<<30 | 0b01110<<24 | (size)<<22 | 0b10000<<17 | 0b10010<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+// Xtract narrow to X bits
+#define XTN_8(Vd, Vn)               EMIT(XTN_vector(0, 0b00, Vn, Vd))
+#define XTN_16(Vd, Vn)              EMIT(XTN_vector(0, 0b01, Vn, Vd))
+#define XTN_32(Vd, Vn)              EMIT(XTN_vector(0, 0b10, Vn, Vd))
+#define XTN2_8(Vd, Vn)              EMIT(XTN_vector(1, 0b00, Vn, Vd))
+#define XTN2_16(Vd, Vn)             EMIT(XTN_vector(1, 0b01, Vn, Vd))
+#define XTN2_32(Vd, Vn)             EMIT(XTN_vector(1, 0b10, Vn, Vd))
+
 // Integer CMP
 // EQual
 #define CMEQ_vector(Q, U, size, Rm, Rn, Rd)     ((Q)<<30 | (U)<<29 | 0b01110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 0b10001<<11 | 1<<10 | (Rn)<<5 | (Rd))
@@ -1600,8 +1771,8 @@
 #define VCHIQQ_64(Rd, Rn, Rm)       EMIT(CMG_vector(1, 1, 0b11, 0, Rm, Rn, Rd))

 // Less Than 0
-#define CMLT_0_vector(Q, size, Rn, Rd)		((Q)<<30 | 0b01110<<24 | (size)<<22 | 0b10000<<17 | 0b01010<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
-#define CMLT_0_8(Rd, Rn)		    EMIT(CMLT_0_vector(0, 0b00, Rn, Rd))
+#define CMLT_0_vector(Q, size, Rn, Rd)      ((Q)<<30 | 0b01110<<24 | (size)<<22 | 0b10000<<17 | 0b01010<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define CMLT_0_8(Rd, Rn)            EMIT(CMLT_0_vector(0, 0b00, Rn, Rd))
 #define CMLT_0_16(Rd, Rn)           EMIT(CMLT_0_vector(0, 0b01, Rn, Rd))
 #define CMLT_0_32(Rd, Rn)           EMIT(CMLT_0_vector(0, 0b10, Rn, Rd))
 #define CMLTQ_0_8(Rd, Rn)           EMIT(CMLT_0_vector(1, 0b00, Rn, Rd))
@@ -1785,8 +1956,12 @@
 #define MOVI_vector(Q, op, abc, cmode, defgh, Rd)   ((Q)<<30 | (op)<<29 | 0b0111100000<<19 | (abc)<<16 | (cmode)<<12 | 1<<10 | (defgh)<<5 | (Rd))
 #define MOVIQ_8(Rd, imm8)           EMIT(MOVI_vector(1, 0, (((imm8)>>5)&0b111), 0b1110, ((imm8)&0b11111), Rd))
 #define MOVIQ_16(Rd, imm8, lsl8)    EMIT(MOVI_vector(1, 0, (((imm8)>>5)&0b111), 0b1000|((lsl8)?0b10:0), ((imm8)&0b11111), Rd))
+#define MOVIQ_32(Rd, imm8)          EMIT(MOVI_vector(1, 0, (((imm8)>>5)&0b111), 0b0000, ((imm8)&0b11111), Rd))
+#define MOVIQ_32_lsl(Rd, imm8, lsl8) EMIT(MOVI_vector(1, 0, (((imm8)>>5)&0b111), (lsl8<<1), ((imm8)&0b11111), Rd))
+#define MOVIQ_64(Rd, imm8)          EMIT(MOVI_vector(1, 1, (((imm8)>>5)&0b111), 0b1110, ((imm8)&0b11111), Rd))
 #define MOVI_8(Rd, imm8)            EMIT(MOVI_vector(0, 0, (((imm8)>>5)&0b111), 0b1110, ((imm8)&0b11111), Rd))
 #define MOVI_16(Rd, imm8, lsl8)     EMIT(MOVI_vector(0, 0, (((imm8)>>5)&0b111), 0b1000|((lsl8)?0b10:0), ((imm8)&0b11111), Rd))
+#define MOVI_32_lsl(Rd, imm8, lsl8) EMIT(MOVI_vector(0, 0, (((imm8)>>5)&0b111), (lsl8<<1), ((imm8)&0b11111), Rd))
 #define MOVI_32(Rd, imm8)           EMIT(MOVI_vector(0, 0, (((imm8)>>5)&0b111), 0b0000, ((imm8)&0b11111), Rd))
 #define MOVI_64(Rd, imm8)           EMIT(MOVI_vector(0, 1, (((imm8)>>5)&0b111), 0b1110, ((imm8)&0b11111), Rd))

@@ -1888,6 +2063,33 @@
 #define UMINQ_32(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 1, 0b10, Vm, 1, Vn, Vd))
 //#define UMINQ_64(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 1, 0b11, Vm, 1, Vn, Vd))

+// MIN or MAX accros vector
+#define MAXMINV_vector(Q, U, size, op, Rn, Rd)  ((Q)<<30 | (U)<<29 | 0b01110<<24 | (size)<<22 | 0b11000<<17 | (op)<<16 | 0b1010<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define SMAXV_8(Vd, Vn)             EMIT(MAXMINV_vector(0, 0, 0b00, 0, Vn, Vd))
+#define SMINV_8(Vd, Vn)             EMIT(MAXMINV_vector(0, 0, 0b00, 1, Vn, Vd))
+#define UMAXV_8(Vd, Vn)             EMIT(MAXMINV_vector(0, 1, 0b00, 0, Vn, Vd))
+#define UMINV_8(Vd, Vn)             EMIT(MAXMINV_vector(0, 1, 0b00, 1, Vn, Vd))
+#define SMAXV_16(Vd, Vn)            EMIT(MAXMINV_vector(0, 0, 0b01, 0, Vn, Vd))
+#define SMINV_16(Vd, Vn)            EMIT(MAXMINV_vector(0, 0, 0b01, 1, Vn, Vd))
+#define UMAXV_16(Vd, Vn)            EMIT(MAXMINV_vector(0, 1, 0b01, 0, Vn, Vd))
+#define UMINV_16(Vd, Vn)            EMIT(MAXMINV_vector(0, 1, 0b01, 1, Vn, Vd))
+#define SMAXV_32(Vd, Vn)            EMIT(MAXMINV_vector(0, 0, 0b10, 0, Vn, Vd))
+#define SMINV_32(Vd, Vn)            EMIT(MAXMINV_vector(0, 0, 0b10, 1, Vn, Vd))
+#define UMAXV_32(Vd, Vn)            EMIT(MAXMINV_vector(0, 1, 0b10, 0, Vn, Vd))
+#define UMINV_32(Vd, Vn)            EMIT(MAXMINV_vector(0, 1, 0b10, 1, Vn, Vd))
+#define SMAXVQ_8(Vd, Vn)            EMIT(MAXMINV_vector(1, 0, 0b00, 0, Vn, Vd))
+#define SMINVQ_8(Vd, Vn)            EMIT(MAXMINV_vector(1, 0, 0b00, 1, Vn, Vd))
+#define UMAXVQ_8(Vd, Vn)            EMIT(MAXMINV_vector(1, 1, 0b00, 0, Vn, Vd))
+#define UMINVQ_8(Vd, Vn)            EMIT(MAXMINV_vector(1, 1, 0b00, 1, Vn, Vd))
+#define SMAXVQ_16(Vd, Vn)           EMIT(MAXMINV_vector(1, 0, 0b01, 0, Vn, Vd))
+#define SMINVQ_16(Vd, Vn)           EMIT(MAXMINV_vector(1, 0, 0b01, 1, Vn, Vd))
+#define UMAXVQ_16(Vd, Vn)           EMIT(MAXMINV_vector(1, 1, 0b01, 0, Vn, Vd))
+#define UMINVQ_16(Vd, Vn)           EMIT(MAXMINV_vector(1, 1, 0b01, 1, Vn, Vd))
+#define SMAXVQ_32(Vd, Vn)           EMIT(MAXMINV_vector(1, 0, 0b10, 0, Vn, Vd))
+#define SMINVQ_32(Vd, Vn)           EMIT(MAXMINV_vector(1, 0, 0b10, 1, Vn, Vd))
+#define UMAXVQ_32(Vd, Vn)           EMIT(MAXMINV_vector(1, 1, 0b10, 0, Vn, Vd))
+#define UMINVQ_32(Vd, Vn)           EMIT(MAXMINV_vector(1, 1, 0b10, 1, Vn, Vd))
+
 // HADD vector
 #define HADD_vector(Q, U, size, Rm, Rn, Rd)     ((Q)<<30 | (U)<<29 | 0b01110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 1<<10 | (Rn)<<5 | (Rd))
 #define SHADD_8(Vd, Vn, Vm)         EMIT(HADD_vector(0, 0, 0b00, Vm, Vn, Vd))
@@ -2026,7 +2228,7 @@
 #define LDSETLH(Rs, Rt, Rn)             EMIT(ATOMIC_gen(0b01, 0, 1, Rs, 0b011, Rn, Rt))
 #define STSETH(Rs, Rn)                  EMIT(ATOMIC_gen(0b01, 0, 0, Rs, 0b011, Rn, 0b11111))
 #define STSETLH(Rs, Rn)                 EMIT(ATOMIC_gen(0b01, 0, 1, Rs, 0b011, Rn, 0b11111))
-// Atomic Signel Max
+// Atomic Signed Max
 #define LDSMAXxw(Rs, Rt, Rn)             EMIT(ATOMIC_gen(0b10+rex.w, 0, 0, Rs, 0b100, Rn, Rt))
 #define LDSMAXAxw(Rs, Rt, Rn)            EMIT(ATOMIC_gen(0b10+rex.w, 1, 0, Rs, 0b100, Rn, Rt))
 #define LDSMAXALxw(Rs, Rt, Rn)           EMIT(ATOMIC_gen(0b10+rex.w, 1, 1, Rs, 0b100, Rn, Rt))
@@ -2142,23 +2344,23 @@

 // FLAGM extension
 // Invert Carry Flag
-#define CFINV()             EMIT(0b1101010100<<22 | 0b0100<<12 | 0b000<<5 | 0b11111)
+#define CFINV()                        FEMIT(0b1101010100<<22 | 0b0100<<12 | 0b000<<5 | 0b11111)

 #define RMIF_gen(imm6, Rn, mask)        (0b10111010000<<21 | (imm6)<<15 | 0b00001<<10 | (Rn)<<5 | (mask))
 // Rotate right reg and use as NZCV
-#define RMIF(Xn, shift, mask)           EMIT(RMIF_gen(shift, Xn, mask))
+#define RMIF(Xn, shift, mask)          FEMIT(RMIF_gen(shift, Xn, mask))

 #define SETF_gen(sz, Rn)                (0b00111010000<<21 | (sz)<<14 | 0b0010<<10 | (Rn)<<5 | 0b1101)
 // Set NZVc with 8bit value of reg: N=bit7, Z=[0..7]==0, V=bit8 eor bit7, C unchanged
-#define SETF8(Wn)                       EMIT(SETF_gen(0, Wn))
+#define SETF8(Wn)                      FEMIT(SETF_gen(0, Wn))
 // Set NZVc with 16bit value of reg: N=bit15, Z=[0..15]==0, V=bit16 eor bit15, C unchanged
-#define SETF16(Wn)                      EMIT(SETF_gen(1, Wn))
+#define SETF16(Wn)                     FEMIT(SETF_gen(1, Wn))

 // FLAGM2 extension
 // NZCV -> N=0 Z=C|V C=C&!V V=0
-#define AXFLAG()            EMIT(0b1101010100<<22 | 0b0100<<12 | 0b010<<5 | 0b11111)
+#define AXFLAG()           FEMIT(0b1101010100<<22 | 0b0100<<12 | 0b010<<5 | 0b11111)
 // NZCV -> N=!C&!Z Z=Z&C C=C|Z V=!C&Z
-#define XAFLAG()            EMIT(0b1101010100<<22 | 0b0100<<12 | 0b001<<5 | 0b11111)
+#define XAFLAG()           FEMIT(0b1101010100<<22 | 0b0100<<12 | 0b001<<5 | 0b11111)

 // FRINTTS extension
 #define FRINTxx_scalar(type, op, Rn, Rd)  (0b11110<<24 | (type)<<22 | 1<<21 | 0b0100<<17 | (op)<<15 | 0b10000<<10 | (Rn)<<5 | (Rd))
@@ -2171,6 +2373,24 @@
 #define FRINT64XS(Sd, Sn)           EMIT(FRINTxx_scalar(0b00, 0b11, Sn, Sd))
 #define FRINT64XD(Dd, Dn)           EMIT(FRINTxx_scalar(0b01, 0b11, Dn, Dd))

+#define FRINTxx_vector(Q, U, sz, op, Rn, Rd)    ((Q)<<30 | (U)<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b1111<<13 | (op)<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define VFRINT32ZS(Vd, Vn)          EMIT(FRINTxx_vector(0, 0, 0, 0, Vn, Vd))
+#define VFRINT32ZSQ(Vd, Vn)         EMIT(FRINTxx_vector(1, 0, 0, 0, Vn, Vd))
+#define VFRINT32XS(Vd, Vn)          EMIT(FRINTxx_vector(0, 1, 0, 0, Vn, Vd))
+#define VFRINT32XSQ(Vd, Vn)         EMIT(FRINTxx_vector(1, 1, 0, 0, Vn, Vd))
+#define VFRINT32ZD(Vd, Vn)          EMIT(FRINTxx_vector(0, 0, 1, 0, Vn, Vd))
+#define VFRINT32ZDQ(Vd, Vn)         EMIT(FRINTxx_vector(1, 0, 1, 0, Vn, Vd))
+#define VFRINT32XD(Vd, Vn)          EMIT(FRINTxx_vector(0, 1, 1, 0, Vn, Vd))
+#define VFRINT32XDQ(Vd, Vn)         EMIT(FRINTxx_vector(1, 1, 1, 0, Vn, Vd))
+#define VFRINT64ZS(Vd, Vn)          EMIT(FRINTxx_vector(0, 0, 0, 1, Vn, Vd))
+#define VFRINT64ZSQ(Vd, Vn)         EMIT(FRINTxx_vector(1, 0, 0, 1, Vn, Vd))
+#define VFRINT64XS(Vd, Vn)          EMIT(FRINTxx_vector(0, 1, 0, 1, Vn, Vd))
+#define VFRINT64XSQ(Vd, Vn)         EMIT(FRINTxx_vector(1, 1, 0, 1, Vn, Vd))
+#define VFRINT64ZD(Vd, Vn)          EMIT(FRINTxx_vector(0, 0, 1, 1, Vn, Vd))
+#define VFRINT64ZDQ(Vd, Vn)         EMIT(FRINTxx_vector(1, 0, 1, 1, Vn, Vd))
+#define VFRINT64XD(Vd, Vn)          EMIT(FRINTxx_vector(0, 1, 1, 1, Vn, Vd))
+#define VFRINT64XDQ(Vd, Vn)         EMIT(FRINTxx_vector(1, 1, 1, 1, Vn, Vd))
+
 // CRC32 extension
 #define CRC32C_gen(sf, Rm, sz, Rn, Rd)  ((sf)<<31 | 0b11010110<<21 | (Rm)<<16 | 0b010<<13 | 1<<12 | (sz)<<10 | (Rn)<<5 | (Rd))
 #define CRC32CB(Wd, Wn, Wm)         EMIT(CRC32C_gen(0, Wm, 0b00, Wn, Wd))
@@ -34,23 +34,3 @@ arm64_epilog:
    ldp     x30, x29, [sp], 16  // saved lr
    //end, return...
    ret
-
-
-.global arm64_epilog_fast
-arm64_epilog_fast:
-    //restore all used register
-    add     sp, x28, 0
-    //vpop     {d8-d15}
-    ldp     x19, x20, [sp, (8 * 0)]
-    ldp     x21, x22, [sp, (8 * 2)]
-    ldp     x23, x24, [sp, (8 * 4)]
-    ldp     x25, x26, [sp, (8 * 6)]
-    ldp     x27, x28, [sp, (8 * 8)]
-    ldp     d8, d9,   [sp, (8 *10)]
-    ldp     d10, d11, [sp, (8 *12)]
-    ldp     d12, d13, [sp, (8 *14)]
-    ldp     d14, d15, [sp, (8 *16)]
-    add     sp,  sp, (8 * 18)
-    ldp     x30, x29, [sp], 16  // saved lr
-    //end, return...
-    ret
@@ -0,0 +1,88 @@
+#include <stdint.h>
+#include "arm64_immenc.h"
+
+#define one (uint64_t)1
+
+// Returns the packed valid-N-imms-immr (1-1-6-6 bits); returns 0 if bitmask is not encodable
+int convert_bitmask(uint64_t bitmask) {
+    if (bitmask == 0 || bitmask == ~0ULL) return 0;
+
+    uint64_t size, mask, pat;
+
+    for (size = 6; size > 1; --size) {
+        mask = (one << (1 << (size - 1))) - 1;
+        pat = bitmask & mask;
+
+        if (pat != ((bitmask >> (1 << (size - 1))) & mask)) {
+            break;
+        }
+    }
+
+    mask = (size >= 6) ? ~0ULL : ((one << (1 << size)) - 1);
+    pat = bitmask & mask;
+
+    for (uint64_t i = 1; i < 7 - size; ++i) {
+        uint64_t boff = i * (1 << size);
+        if (((bitmask >> boff) & mask) != pat) {
+            return 0;
+        }
+    }
+
+    int immr = 0;
+    uint64_t last_bit = one << ((1 << size) - 1);
+
+    if (pat & 1) {
+        while (pat & last_bit) {
+            pat = ((pat - last_bit) << 1) | 1;
+            ++immr;
+        }
+    } else {
+        immr = 1 << size;
+        while (!(pat & 1)) {
+            pat >>= 1;
+            --immr;
+        }
+    }
+
+    if (pat & (pat + 1)) return 0;
+
+    int to = 1;
+    while (pat & (one << to)) ++to;
+
+    return 0x2000 + ((size == 6) << 12) + ((((0x1E << size) & 0x3F) + (to - 1)) << 6) + immr;
+}
+
+#if 0
+#include <unordered_set>
+int main() {
+    std::unordered_set<uint64_t> okvals;
+    uint64_t val;
+
+    for (int n = 1; n < 7; ++n) {
+        int imms0 = ((n == 6) ? 0xC0 : 0x80) + ((0x1E << n) & 0x3F);
+        for (int nones = 0; nones < (1 << n) - 1; ++nones) {
+            val = (one << (nones + 1)) - 1;
+            for (int j = 0; j < 6 - n; ++j) {
+                val += val << (1 << (n + j));
+            }
+            for (int immr = 0; immr < (1 << n); ++immr) {
+                int exp = ((imms0 + nones) << 6) + immr;
+                int got = convert_bitmask(val);
+                if (exp != got) {
+                    printf("0x%016lX: expected %04X, got %04X\n", val, exp, got);
+                }
+                okvals.emplace(val);
+                val = (val >> 1) | ((val & 1) << 63);
+            }
+        }
+    }
+
+#pragma omp parallel for
+    for (uint64_t i = 1; i < 0xFFFFFFFFFFFFFFFFu; ++i) {
+        int got = convert_bitmask(i);
+        if (!!got != (okvals.find(i) != okvals.cend())) {
+            printf("0x%016lX: expected %s, got %04X\n", i, (!!got ? "non0" : "0000"), got);
+        }
+    }
+}
+#endif
@@ -0,0 +1,8 @@
+#ifndef __ARM64_IMMENC_H__
+#define __ARM64_IMMENC_H__
+
+#include <stdint.h>
+
+int convert_bitmask(uint64_t bitmask);
+
+#endif // __ARM64_IMMENC_H__
@@ -34,10 +34,12 @@ uint64_t DecodeBitMasks(int N, int imms, int immr)
    if(s==levels) return 0;
    uint64_t mask = (1LL<<(s+1))-1;
    if(r) { // rotate
-         mask=(mask>>r)|(mask<<(e-r));
-         mask&=((1LL<<e)-1);
+        mask=(mask>>r)|(mask<<(e-r));
+        if(e<64) {
+            mask&=((1LL<<e)-1);
+        }
    }
-    while (e<64) {  // replicate
+    while(e<64) {  // replicate
        mask|=(mask<<e);
        e<<=1;
    }
@@ -122,6 +124,22 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
        snprintf(buff, sizeof(buff), "NOP");
        return buff;
    }
+    if(isMask(opcode, "11010101000000110010000001011111", &a)) {
+        snprintf(buff, sizeof(buff), "WFE");
+        return buff;
+    }
+    if(isMask(opcode, "11010101000000110010000001111111", &a)) {
+        snprintf(buff, sizeof(buff), "WFI");
+        return buff;
+    }
+    if(isMask(opcode, "11010101000000110010000000111111", &a)) {
+        snprintf(buff, sizeof(buff), "YIELD");
+        return buff;
+    }
+    if(isMask(opcode, "11010101000000110010000010111111", &a)) {
+        snprintf(buff, sizeof(buff), "SEVL");
+        return buff;
+    }
    // --- LDR / STR
    if(isMask(opcode, "f010100011iiiiiii22222nnnnnttttt", &a)) {
        int offset = signExtend(imm, 7)<<(2+sf);
@@ -387,13 +405,13 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
    }
    if(isMask(opcode, "f00100101wwiiiiiiiiiiiiiiiiddddd", &a)) {
        if(sf) {
-            uint64_t noti=~(uint64_t)imm;
+            uint64_t noti=~(((uint64_t)imm)<<(hw*16));
            if(!hw)
                snprintf(buff, sizeof(buff), "MOVN %s, 0x%x\t; 0x%lx", Xt[Rd], imm, noti);
            else
                snprintf(buff, sizeof(buff), "MOVN %s, 0x%x LSL %d\t; 0x%lx", Xt[Rd], imm, 16*hw, noti);
        } else {
-            uint32_t noti=~(uint32_t)imm;
+            uint32_t noti=~(((uint32_t)imm)<<(hw*16));
            if(!hw)
                snprintf(buff, sizeof(buff), "MOVN %s, 0x%x\t; 0x%x", Wt[Rd], imm, noti);
            else
@@ -571,6 +589,14 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
            snprintf(buff, sizeof(buff), "BIC %s, %s, %s, %s %d", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], sf?Xt[Rm]:Wt[Rm], shifts[shift], imm);
        return buff;
    }
+    if(isMask(opcode, "f1101010hh1mmmmmiiiiiinnnnnddddd", &a)) {
+        const char* shifts[] = { "LSL", "LSR", "ASR", "ROR" };
+        if(shift==0 && imm==0)
+            snprintf(buff, sizeof(buff), "BICS %s, %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], sf?Xt[Rm]:Wt[Rm]);
+        else
+            snprintf(buff, sizeof(buff), "BICS %s, %s, %s, %s %d", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], sf?Xt[Rm]:Wt[Rm], shifts[shift], imm);
+        return buff;
+    }
    if(isMask(opcode, "f01100100Nrrrrrrssssssnnnnnddddd", &a)) {
        uint64_t i = DecodeBitMasks(a.N, imms, immr);
        if(!sf) i&=0xffffffff;
@@ -914,7 +940,6 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
    }
    // UMOV
    if(isMask(opcode, "0Q001110000rrrrr001111nnnnnddddd", &a)) {
-        char q = a.Q?'Q':'D';
        char s = '?';
        int sz=0;
        if(a.Q==0 && immr&1) {s='B'; sz=0; }
@@ -923,9 +948,24 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
        else if(a.Q==1 && (immr&15)==8) {s='D'; sz=3; }
        int index = (immr)>>(sz+1);
        if(sz>2)
-            snprintf(buff, sizeof(buff), "MOV %s, %c%d.%c[%d]", a.Q?Xt[Rd]:Wt[Rd], q, Rn, s, index);
+            snprintf(buff, sizeof(buff), "MOV %s, V%d.%c[%d]", a.Q?Xt[Rd]:Wt[Rd], Rn, s, index);
        else
-            snprintf(buff, sizeof(buff), "UMOV %s, %c%d.%c[%d]", a.Q?Xt[Rd]:Wt[Rd], q, Rn, s, index);
+            snprintf(buff, sizeof(buff), "UMOV %s, V%d.%c[%d]", a.Q?Xt[Rd]:Wt[Rd], Rn, s, index);
+        return buff;
+    }
+    // SMOV
+    if(isMask(opcode, "0Q001110000rrrrr001011nnnnnddddd", &a)) {
+        char s = '?';
+        int sz=0;
+        if(a.Q==0 && immr&1) {s='B'; sz=0; }
+        else if(/*a.Q==0 &&*/ (immr&3)==2) {s='H'; sz=1; }
+        else if(/*a.Q==0 &&*/ (immr&7)==4) {s='S'; sz=2; }
+        else if(a.Q==1 && (immr&15)==8) {s='D'; sz=3; }
+        int index = (immr)>>(sz+1);
+        if(sz>2)
+            snprintf(buff, sizeof(buff), "MOV %s, V%d.%c[%d]", a.Q?Xt[Rd]:Wt[Rd], Rn, s, index);
+        else
+            snprintf(buff, sizeof(buff), "SMOV %s, V%d.%c[%d]", a.Q?Xt[Rd]:Wt[Rd], Rn, s, index);
        return buff;
    }
    // VEOR
@@ -950,6 +990,12 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
        snprintf(buff, sizeof(buff), "VMUL V%d.%s, V%d.%s, V%d.%s", Rd, Vd, Rn, Vd, Rm, Vd);
        return buff;
    }
+    // VBIT / VBIF
+    if(isMask(opcode, "0Q1011101o1mmmmm000111nnnnnddddd", &a)) {
+        char q = a.Q?'Q':'D';
+        snprintf(buff, sizeof(buff), "VBI%c %c%d, %c%d, %c%d", a.o?'F':'T', q, Rd, q, Rn, q, Rm);
+        return buff;
+    }
    // CMP
    if(isMask(opcode, "0Q101110ff1mmmmm100011nnnnnddddd", &a)) {
        const char* Y[] = {"8B", "16B", "4H", "8H", "2S", "4S", "??", "2D"};
@@ -1005,6 +1051,19 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
        snprintf(buff, sizeof(buff), "MOVI V%d.%s, #0x%x", Rd, Vd, imm<<8);
        return buff;
    }
+    // MOV immediate 64bits
+    if(isMask(opcode, "0Q10111100000iii111001iiiiiddddd", &a)) {
+        uint64_t tmp64u = 0;
+        for(int i=0; i<8; ++i)
+            if((imm)&(1<<i))
+                tmp64u |= 0xffLL<<(i*8);
+
+        if(a.Q)
+            snprintf(buff, sizeof(buff), "MOVI V%d.2D, #0x%016lx", Rd, tmp64u);
+        else
+            snprintf(buff, sizeof(buff), "MOVI D%d, #0x%016lx", Rd, tmp64u);
+        return buff;
+    }

    // Shift
    if(isMask(opcode, "0QU011110hhhhrrr000001nnnnnddddd", &a)) {
@@ -1295,6 +1354,28 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
        snprintf(buff, sizeof(buff), "F%s%s V%d.%d%c, V%d.%d%c, V%d.%d%c", option?"MIN":"MAX", a.Q?"Q":"", Rd, n, s, Rn, n, s, Rm, n, s);
        return buff;
    }
+    // FMADD
+    if(isMask(opcode, "00011111tt0mmmmmoaaaaannnnnddddd", &a)) {
+        char s = (a.t==0b00)?'S':((a.t==0b01)?'D':'?');
+        int n = (a.t==0)?1:2;
+        snprintf(buff, sizeof(buff), "FM%s V%d.%d%c, V%d.%d%c, V%d.%d%c, V%d.%d%c", option?"SUB":"ADD", Rd, n, s, Ra, n, s, Rn, n, s, Rm, n, s);
+        return buff;
+    }
+    // FNMADD
+    if(isMask(opcode, "00011111tt1mmmmmoaaaaannnnnddddd", &a)) {
+        char s = (a.t==0b00)?'S':((a.t==0b01)?'D':'?');
+        int n = (a.t==0)?1:2;
+        snprintf(buff, sizeof(buff), "FNM%s V%d.%d%c, V%d.%d%c, V%d.%d%c, V%d.%d%c", option?"SUB":"ADD", Rd, n, s, Ra, n, s, Rn, n, s, Rm, n, s);
+        return buff;
+    }
+    // FMLA
+    if(isMask(opcode, "0Q001110of1mmmmm110011nnnnnddddd", &a)) {
+        char s = (sf==0)?'S':((sf==1)?'D':'?');
+        int n = (sf==0)?2:1;
+        n *= a.Q?2:1;
+        snprintf(buff, sizeof(buff), "FML%s%s V%d.%d%c, V%d.%d%c, V%d.%d%c", option?"S":"A", a.Q?"Q":"", Rd, n, s, Rn, n, s, Rm, n, s);
+        return buff;
+    }
    // NEG
    if(isMask(opcode, "0Q101110ff100000101110nnnnnddddd", &a)) {
        const char* Y[] = {"8B", "16B", "4H", "8H", "2S", "4S", "??", "2D"};
@@ -1574,6 +1655,17 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
            snprintf(buff, sizeof(buff), "%cSHLL%s V%d.%s, V%d.%s, #%d", a.U?'U':'S', a.Q?"2":"", Rd, Va, Rn, Vd, sh);
        return buff;
    }
+    if(isMask(opcode, "0Q0011110hhhhiii010101nnnnnddddd", &a) && (a.h != 0b1000)) {
+        const char* Y[] = {"8B", "16B", "4H", "8H", "2S", "4S", "??", "2D"};
+        int sz = 3;
+        if((a.h&0b1111)==0b0001) sz=0;
+        else if((a.h&0b1110)==0b0010) sz=1;
+        else if((a.h&0b1100)==0b0100) sz=2;
+        int sh=(((a.h)<<3)|(imm)) - (8<<sz);
+        const char* Vd = Y[(sz<<1)|a.Q];
+        snprintf(buff, sizeof(buff), "SHL%s V%d.%s, V%d.%s, #%d", a.Q?"Q":"", Rd, Vd, Rn, Vd, sh);
+        return buff;
+    }

    // DUP
    if(isMask(opcode, "0Q001110000iiiii000001nnnnnddddd", &a)) {
@@ -1583,7 +1675,7 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
        if((imm&0b0001)==0b0001) sz=0;
        else if((imm&0b0011)==0b0010) sz=1;
        else if((imm&0b0111)==0b0100) sz=2;
-        int sh=imm - (1<<sz);
+        int sh=(imm>>sz) - 1;
        const char* Vd = Y[(sz<<1)|a.Q];
        const char* Vn = Z[sz];
        snprintf(buff, sizeof(buff), "DUP V%d.%s, V%d.%s[%d]", Rd, Vd, Rn, Vn, sh);
@@ -1759,6 +1851,11 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
        snprintf(buff, sizeof(buff), "SHA256H2 Q%d, Q%d, V%d.4S", Rd, Rn, Rm);
        return buff;
    }
+    // UDF
+    if(isMask(opcode, "0000000000000000iiiiiiiiiiiiiiii", &a)) {
+        snprintf(buff, sizeof(buff), "UDF 0x%x", a.i);
+        return buff;
+    }

    snprintf(buff, sizeof(buff), "%08X ???", __builtin_bswap32(opcode));
    return buff;
@@ -6,8 +6,6 @@
 .text
 .align 4

-.extern arm64_next
-
 .global arm64_prolog
 arm64_prolog:
    //save all 18 used register
@@ -34,8 +32,7 @@ arm64_prolog:
    ldp     x24, x25, [x0, (8 * 14)]
    ldp     x26, x27, [x0, (8 * 16)]
    // Push a jump next on the stack
-    adr     x28, arm64_next
-    stp     x28, xzr, [sp, -16]!
+    stp     xzr, xzr, [sp, -16]!
    // Save old xSP in x28
    add     x28, sp, 16
    //jump to function
@@ -18,7 +18,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"

 uintptr_t dynarec64_6664(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int seg, int* ok, int* need_epilog)
@@ -27,8 +27,9 @@ uintptr_t dynarec64_6664(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n

    uint8_t opcode = F8;
    uint8_t nextop;
-    uint8_t gd, ed;
+    uint8_t gd, ed, wb1, wback;
    int64_t j64;
+    int16_t i16;
    int v0, v1;
    int64_t fixedaddress;
    int unscaled;
@@ -60,39 +61,170 @@ uintptr_t dynarec64_6664(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                        grab_segdata(dyn, addr, ninst, x4, seg);
                        SMREAD();
                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
-                        v1 = fpu_get_scratch(dyn);
-                        VLDR64_REG(v1, ed, x4);
+                        v1 = fpu_get_scratch(dyn, ninst);
+                        if(rex.is32bits)
+                            VLDR64_REG_SXTW(v1, x4, ed);
+                        else
+                            VLDR64_REG(v1, ed, x4);
                    }
                    FCMPD(v0, v1);
-                    FCOMI(x1, x2);
+                    FCOMI(x1, x2, 0, v0, v1, 0);    //disable precise cmp
+                    break;
+
+                case 0x6F:
+                    INST_NAME("MOVDQA Gx,Ex");
+                    nextop = F8;
+                    if(MODREG) {
+                        v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                        GETGX_empty(v0);
+                        VMOVQ(v0, v1);
+                    } else {
+                        GETGX_empty(v0);
+                        grab_segdata(dyn, addr, ninst, x4, seg);
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                        SMREAD();
+                        if(rex.is32bits)
+                            VLDR128_REG_SXTW(v0, x4, ed);
+                        else
+                            VLDR128_REG(v0, ed, x4);
+                    }
+                    break;
+
+                case 0x7F:
+                    INST_NAME("MOVDQA Ex,Gx");
+                    nextop = F8;
+                    GETGX(v0, 0);
+                    if(MODREG) {
+                        v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 1);
+                        VMOVQ(v1, v0);
+                    } else {
+                        grab_segdata(dyn, addr, ninst, x4, seg);
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                        if(rex.is32bits)
+                            VSTR128_REG_SXTW(v0, x4, ed);
+                        else
+                            VSTR128_REG(v0, ed, x4);
+                        SMWRITE2();
+                    }
+                    break;
+
+                case 0xD6:
+                    INST_NAME("MOVQ Ex, Gx");
+                    nextop = F8;
+                    GETG;
+                    v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+                    if(MODREG) {
+                        v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
+                        FMOVD(v1, v0);
+                    } else {
+                        grab_segdata(dyn, addr, ninst, x4, seg);
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                        if(rex.is32bits)
+                            VSTR64_REG_SXTW(v0, x4, ed);
+                        else
+                            VSTR64_REG(v0, ed, x4);
+                        SMWRITE();
+                    }
                    break;
-            case 0xD6:
-                INST_NAME("MOVQ Ex, Gx");
-                nextop = F8;
-                GETG;
-                v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
-                if(MODREG) {
-                    v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
-                    FMOVD(v1, v0);
-                } else {
-                    grab_segdata(dyn, addr, ninst, x4, seg);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
-                    VSTR64_REG(v0, ed, x4);
-                    SMWRITE();
-                }
-                break;

                default:
                    DEFAULT;
            }
            break;

+        case 0x83:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 0: //ADD
+                    if(opcode==0x81) {INST_NAME("ADD Ew, Iw");} else {INST_NAME("ADD Ew, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    GETEWO(x1, (opcode==0x81)?2:1);
+                    if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                    MOVZw(x5, i16);
+                    emit_add16(dyn, ninst, ed, x5, x2, x4);
+                    EWBACK;
+                    break;
+                case 1: //OR
+                    if(opcode==0x81) {INST_NAME("OR Ew, Iw");} else {INST_NAME("OR Ew, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    GETEWO(x1, (opcode==0x81)?2:1);
+                    if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                    emit_or16c(dyn, ninst, x1, i16, x2, x4);
+                    EWBACK;
+                    break;
+                case 2: //ADC
+                    if(opcode==0x81) {INST_NAME("ADC Ew, Iw");} else {INST_NAME("ADC Ew, Ib");}
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    GETEWO(x1, (opcode==0x81)?2:1);
+                    if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                    MOVZw(x5, i16);
+                    emit_adc16(dyn, ninst, x1, x5, x2, x4);
+                    EWBACK;
+                    break;
+                case 3: //SBB
+                    if(opcode==0x81) {INST_NAME("SBB Ew, Iw");} else {INST_NAME("SBB Ew, Ib");}
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    GETEWO(x1, (opcode==0x81)?2:1);
+                    if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                    MOVZw(x5, i16);
+                    emit_sbb16(dyn, ninst, x1, x5, x2, x4);
+                    EWBACK;
+                    break;
+                case 4: //AND
+                    if(opcode==0x81) {INST_NAME("AND Ew, Iw");} else {INST_NAME("AND Ew, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    GETEWO(x1, (opcode==0x81)?2:1);
+                    if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                    emit_and16c(dyn, ninst, x1, i16, x2, x4);
+                    EWBACK;
+                    break;
+                case 5: //SUB
+                    if(opcode==0x81) {INST_NAME("SUB Ew, Iw");} else {INST_NAME("SUB Ew, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    GETEWO(x1, (opcode==0x81)?2:1);
+                    if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                    MOVZw(x5, i16);
+                    emit_sub16(dyn, ninst, x1, x5, x2, x4);
+                    EWBACK;
+                    break;
+                case 6: //XOR
+                    if(opcode==0x81) {INST_NAME("XOR Ew, Iw");} else {INST_NAME("XOR Ew, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    GETEWO(x1, (opcode==0x81)?2:1);
+                    if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                    emit_xor16c(dyn, ninst, x1, i16, x2, x4);
+                    EWBACK;
+                    break;
+                case 7: //CMP
+                    if(opcode==0x81) {INST_NAME("CMP Ew, Iw");} else {INST_NAME("CMP Ew, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    GETEWO(x1, (opcode==0x81)?2:1);
+                    if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                    if(i16) {
+                        MOVZw(x2, i16);
+                        emit_cmp16(dyn, ninst, x1, x2, x3, x4, x5);
+                    } else
+                        emit_cmp16_0(dyn, ninst, x1, x3, x4);
+                    break;
+            }
+            break;
+            
        case 0x89:
            INST_NAME("MOV FS:Ew, Gw");
            nextop = F8;
            GETGD;  // don't need GETGW here
            if(MODREG) {
-                ed = xRAX+(nextop&7)+(rex.b<<3);
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                if(rex.w) {
                    MOVx_REG(ed, gd);
                } else {
@@ -106,18 +238,21 @@ uintptr_t dynarec64_6664(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                if(rex.w) {
                    STRx_REG(gd, ed, x4);
                } else {
-                    STRH_REG(gd, ed, x4);
+                    if(rex.is32bits)
+                        STRH_REG_SXTW(gd, x4, ed);
+                    else
+                        STRH_REG(gd, ed, x4);
                }
                SMWRITE();
            }
            break;

        case 0x8B:
-            INST_NAME("MOV Gd, FS:Ed");
+            INST_NAME("MOV Gw, FS:Ew");
            nextop=F8;
            GETGD;
            if(MODREG) {   // reg <= reg
-                ed = xRAX+(nextop&7)+(rex.b<<3);
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                if(rex.w) {
                    MOVx_REG(gd, ed);
                } else {
@@ -132,7 +267,10 @@ uintptr_t dynarec64_6664(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                if(rex.w) {
                    LDRx_REG(gd, ed, x4);
                } else {
-                    LDRH_REG(x1, ed, x4);
+                    if(rex.is32bits)
+                        LDRH_REG_SXTW(x1, x4, ed);
+                    else
+                        LDRH_REG(x1, ed, x4);
                    BFIx(gd, x1, 0, 16);
                }
            }
@@ -18,7 +18,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"


@@ -30,7 +30,7 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
    uint8_t nextop;
    uint8_t gd, ed, u8;
    uint8_t wback, wb1, wb2, gb1, gb2;
-    int32_t i32;
+    int16_t i16;
    int64_t i64, j64;
    int64_t fixedaddress;
    int unscaled;
@@ -48,13 +48,44 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
    GETREX();

    switch(opcode) {
+
+        case 0x01:
+            INST_NAME("LOCK ADD Ew, Gw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x5);
+            if(MODREG) {
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                UXTHw(x6, ed);
+                emit_add16(dyn, ninst, x6, x5, x3, x4);
+                BFIx(ed, x6, 0, 16);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                if(arm64_atomics) {
+                    UFLAG_IF {
+                        LDADDALH(x5, x1, wback);
+                        emit_add16(dyn, ninst, x1, x5, x3, x4);
+                    } else {
+                        STADDLH(x5, wback);
+                    }
+                } else {
+                    MARKLOCK;
+                    LDAXRH(x1, wback);
+                    emit_add16(dyn, ninst, x1, x5, x3, x4);
+                    STLXRH(x3, x1, wback);
+                    CBNZx_MARKLOCK(x3);
+                }
+                SMDMB();
+            }
+            break;
+
        case 0x09:
            INST_NAME("LOCK OR Ew, Gw");
            SETFLAGS(X_ALL, SF_SET_PENDING);
            nextop = F8;
            GETGW(x5);
            if(MODREG) {
-                ed = xRAX+(nextop&7)+(rex.b<<3);
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                UXTHw(x6, ed);
                emit_or16(dyn, ninst, x6, x5, x3, x4);
                BFIx(ed, x6, 0, 16);
@@ -89,7 +120,7 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    GETGD;
                    UXTHw(x6, xRAX);
                    if(MODREG) {
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        wback = 0;
                        UXTHw(x1, ed);
                        CMPSxw_REG(x6, x1);
@@ -98,8 +129,14 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
                        if(!ALIGNED_ATOMICH) {
-                            TSTx_mask(wback, 1, 0, 0);    // mask=1
-                            B_MARK3(cNE);
+                            if(arm64_uscat) {
+                                ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                                CMPSw_U12(x1, 0xF);
+                                B_MARK3(cGE);
+                            } else {
+                                TSTx_mask(wback, 1, 0, 0);    // mask=1
+                                B_MARK3(cNE);
+                            }
                        }
                        // Aligned version
                        if(arm64_atomics) {
@@ -140,10 +177,10 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    INST_NAME("LOCK XADD Gw, Ew");
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    nextop = F8;
-                    gd = xRAX+((nextop&0x38)>>3)+(rex.r<<3);
+                    gd = TO_NAT(((nextop & 0x38) >> 3) + (rex.r << 3));
                    UXTHx(x5, gd);
                    if(MODREG) {
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        BFIx(gd, ed, 0, 16);
                        emit_add16(dyn, ninst, x5, gd, x3, x4);
                        BFIx(ed, x5, 0, 16);
@@ -171,6 +208,7 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    DEFAULT;
            }
            break;
+
        case 0x11:
            INST_NAME("LOCK ADC Ew, Gw");
            READFLAGS(X_CF);
@@ -178,7 +216,7 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            nextop = F8;
            GETGW(x5);
            if(MODREG) {
-                ed = xRAX+(nextop&7)+(rex.b<<3);
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                UXTHw(x6, ed);
                emit_adc16(dyn, ninst, x6, x5, x3, x4);
                BFIx(ed, x6, 0, 16);
@@ -192,6 +230,38 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                SMDMB();
            }
            break;
+
+        case 0x21:
+            INST_NAME("LOCK AND Ew, Gw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x5);
+            if(MODREG) {
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                UXTHw(x6, ed);
+                emit_and16(dyn, ninst, x6, gd, x3, x4);
+                BFIx(ed, x6, 0, 16);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                if(arm64_atomics) {
+                    MVNw_REG(x3, gd);
+                    UFLAG_IF {
+                        LDCLRALH(x3, x1, wback);
+                        emit_and16(dyn, ninst, x1, gd, x3, x4);
+                    } else {
+                        STCLRLH(x3, wback);
+                    }
+                } else {
+                    MARKLOCK;
+                    LDAXRH(x1, wback);
+                    emit_and16(dyn, ninst, x1, gd, x3, x4);
+                    STLXRH(x3, x1, wback);
+                    CBNZx_MARKLOCK(x3);
+                }
+                SMDMB();
+            }
+            break;
+
        case 0x81:
        case 0x83:
            nextop = F8;
@@ -204,19 +274,25 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    }
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                        MOV32w(x5, i16);
                        UXTHw(x6, ed);
                        emit_add16(dyn, ninst, x6, x5, x3, x4);
                        BFIx(ed, x6, 0, 16);
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        MOV32w(x5, i16);
                        if(!ALIGNED_ATOMICH) {
-                            TSTx_mask(wback, 1, 0, 0);    // mask=1
-                            B_MARK(cNE);
+                            if(arm64_uscat) {
+                                ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                                CMPSw_U12(x1, 0xF);
+                                B_MARK(cGE);
+                            } else {
+                                TSTx_mask(wback, 1, 0, 0);    // mask=1
+                                B_MARK(cNE);
+                            }
                        }
                        if(arm64_atomics) {
                            LDADDALH(x5, x1, wback);
@@ -249,27 +325,32 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    if(opcode==0x81) {INST_NAME("LOCK OR Ew, Iw");} else {INST_NAME("LOCK OR Ew, Ib");}
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        UXTHw(x6, ed);
-                        emit_or16(dyn, ninst, x6, x5, x3, x4);
+                        emit_or16c(dyn, ninst, x6, i16, x3, x4);
                        BFIx(ed, x6, 0, 16);
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        if(!i64) {MOV32w(x5, i16);}
                        if(arm64_atomics) {
                            UFLAG_IF {
                                LDSETALH(x5, x1, wback);
-                                emit_or16(dyn, ninst, x1, x5, x3, x4);
+                                emit_or16c(dyn, ninst, x1, i16, x3, x4);
                            } else {
                                STSETLH(x5, wback);
                            }
                        } else {
+                            i64 = convert_bitmask_w(i16);
+                            if(!i64) {MOV32w(x5, i16);}
                            MARKLOCK;
                            LDAXRH(x1, wback);
-                            emit_or16(dyn, ninst, x1, x5, x3, x4);
+                            if(i64) {
+                                emit_or16c(dyn, ninst, x1, i16, x3, x4);
+                            } else {
+                                emit_or16(dyn, ninst, x1, x5, x3, x4);
+                            }
                            STLXRH(x3, x1, wback);
                            CBNZx_MARKLOCK(x3);
                        }
@@ -281,16 +362,16 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    READFLAGS(X_CF);
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                        MOV32w(x5, i16);
                        UXTHw(x6, ed);
                        emit_adc16(dyn, ninst, x6, x5, x3, x4);
                        BFIx(ed, x6, 0, 16);
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        MOV32w(x5, i16);
                        MARKLOCK;
                        LDAXRH(x1, wback);
                        emit_adc16(dyn, ninst, x1, x5, x3, x4);
@@ -304,16 +385,16 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    READFLAGS(X_CF);
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                        MOV32w(x5, i16);
                        UXTHw(x6, ed);
                        emit_sbb16(dyn, ninst, x6, x5, x3, x4);
                        BFIx(ed, x6, 0, 16);
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        MOV32w(x5, i16);
                        MARKLOCK;
                        LDAXRH(x1, wback);
                        emit_sbb16(dyn, ninst, x1, x5, x3, x4);
@@ -326,29 +407,37 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    if(opcode==0x81) {INST_NAME("LOCK AND Ew, Iw");} else {INST_NAME("LOCK AND Ew, Ib");}
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        UXTHw(x6, ed);
-                        emit_and16(dyn, ninst, x6, x5, x3, x4);
+                        emit_and16c(dyn, ninst, x6, i16, x3, x4);
                        BFIx(ed, x6, 0, 16);
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        i64 = convert_bitmask_w(i16);
                        if(arm64_atomics) {
-                            MOV32w(x5, ~i32);
+                            MOV32w(x5, ~i16);
                            UFLAG_IF {
                                LDCLRALH(x5, x1, wback);
-                                MVNw_REG(x5, x5);
-                                emit_and16(dyn, ninst, x1, x5, x3, x4);
+                                if(i64) {
+                                    emit_and16c(dyn, ninst, x1, i16, x3, x4);
+                                } else {
+                                    MVNw_REG(x5, x5);
+                                    emit_and16(dyn, ninst, x1, x5, x3, x4);
+                                }
                            } else {
                                STCLRLH(x5, wback);
                            }
                        } else {
-                            MOV32w(x5, i32);
+                            if(!i64) {MOV32w(x5, i16);}
                            MARKLOCK;
                            LDAXRH(x1, wback);
-                            emit_and16(dyn, ninst, x1, x5, x3, x4);
+                            if(i64) {
+                                emit_and16c(dyn, ninst, x1, i16, x3, x4);
+                            } else {
+                                emit_and16(dyn, ninst, x1, x5, x3, x4);
+                            }
                            STLXRH(x3, x1, wback);
                            CBNZx_MARKLOCK(x3);
                            SMDMB();
@@ -359,19 +448,25 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    if(opcode==0x81) {INST_NAME("LOCK SUB Ew, Iw");} else {INST_NAME("LOCK SUB Ew, Ib");}
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                        MOV32w(x5, i16);
                        UXTHw(x6, ed);
                        emit_sub16(dyn, ninst, x6, x5, x3, x4);
                        BFIx(ed, x6, 0, 16);
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        MOV32w(x5, i16);
                        if(!ALIGNED_ATOMICH) {
-                            TSTx_mask(wback, 1, 0, 0);    // mask=1
-                            B_MARK(cNE);
+                            if(arm64_uscat) {
+                                ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                                CMPSw_U12(x1, 0xF);
+                                B_MARK(cGE);
+                            } else {
+                                TSTx_mask(wback, 1, 0, 0);    // mask=1
+                                B_MARK(cNE);
+                            }
                        }
                        if(arm64_atomics) {
                            NEGw_REG(x4, x5);
@@ -407,27 +502,30 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    if(opcode==0x81) {INST_NAME("LOCK XOR Ew, Iw");} else {INST_NAME("LOCK XOR Ew, Ib");}
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        UXTHw(x6, ed);
-                        emit_xor16(dyn, ninst, x6, x5, x3, x4);
+                        emit_xor16c(dyn, ninst, x6, i16, x3, x4);
                        BFIx(ed, x6, 0, 16);
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
-                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                        MOV32w(x5, i32);
+                        if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                        i64 = convert_bitmask_w(i16);
                        if(arm64_atomics) {
                            UFLAG_IF {
                                LDEORALH(x5, x1, wback);
-                                emit_xor16(dyn, ninst, x1, x5, x3, x4);
+                                emit_xor16c(dyn, ninst, x1, i16, x3, x4);
                            } else {
                                STEORLH(x5, wback);
                            }
                        } else {
+                            if(!i64) {MOV32w(x5, i16);}
                            MARKLOCK;
                            LDAXRH(x1, wback);
-                            emit_xor16(dyn, ninst, x1, x5, x3, x4);
+                            if(i64)
+                                emit_xor16c(dyn, ninst, x1, i16, x3, x4);
+                            else
+                                emit_xor16(dyn, ninst, x1, x5, x3, x4);
                            STLXRH(x3, x1, wback);
                            CBNZx_MARKLOCK(x3);
                            SMDMB();
@@ -440,9 +538,9 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                    GETEW(x6, (opcode==0x81)?2:1);
                    (void)wb1;
                    // No need to LOCK, this is readonly
-                    if(opcode==0x81) i32 = F16S; else i32 = F8S;
-                    if(i32) {
-                        MOV32w(x5, i32);
+                    if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                    if(i16) {
+                        MOV32w(x5, i16);
                        emit_cmp16(dyn, ninst, x6, x5, x3, x4, x6);
                    } else {
                        emit_cmp16_0(dyn, ninst, ed, x3, x4);
@@ -457,9 +555,9 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                {
                    case 0: // INC Ew
                        INST_NAME("LOCK INC Ew");
-                        SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                        SETFLAGS(X_ALL&~X_CF, SF_SUBSET);
                        if(MODREG) {
-                            ed = xRAX+(nextop&7)+(rex.b<<3);
+                            ed = TO_NAT((nextop & 7) + (rex.b << 3));
                            UXTHw(x6, ed);
                            emit_inc16(dyn, ninst, x6, x5, x3);
                            BFIx(ed, x6, 0, 16);
@@ -485,9 +583,9 @@ uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                        break;
                    case 1: //DEC Ew
                        INST_NAME("LOCK DEC Ew");
-                        SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                        SETFLAGS(X_ALL&~X_CF, SF_SUBSET);
                        if(MODREG) {
-                            ed = xRAX+(nextop&7)+(rex.b<<3);
+                            ed = TO_NAT((nextop & 7) + (rex.b << 3));
                            UXTHw(x6, ed);
                            emit_dec16(dyn, ninst, x6, x5, x3);
                            BFIx(ed, x6, 0, 16);
@@ -19,7 +19,7 @@
 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "emu/x64compstrings.h"

 uintptr_t dynarec64_66F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog)
@@ -19,7 +19,7 @@
 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "emu/x64compstrings.h"

 uintptr_t dynarec64_66F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog)
@@ -56,6 +56,27 @@ uintptr_t dynarec64_66F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int

    switch(opcode) {

+        case 0xBD:
+            INST_NAME("LZCNT Gw, Ew");
+            SETFLAGS(X_CF|X_ZF, SF_SUBSET);
+            SET_DFNONE(x1);
+            nextop = F8;
+            GETEW(x1, 0);
+            GETGW(x2);
+            IFX(X_CF) {
+                TSTxw_REG(ed, ed);
+                CSETw(x3, cEQ);
+                BFIw(xFlags, x3, F_CF, 1);  // CF = is source 0?
+            }
+            LSLw_IMM(ed, ed, 16);
+            CLZw(gd, ed);
+            IFX(X_ZF) {
+                TSTxw_REG(gd, gd);
+                CSETw(x3, cEQ);
+                BFIw(xFlags, x3, F_ZF, 1);  // ZF = is dest 0?
+            }
+            EWBACK;
+            break;

        default:
            DEFAULT;
@@ -15,10 +15,11 @@
 #include "emu/x64run_private.h"
 #include "x64trace.h"
 #include "dynarec_native.h"
+#include "custommem.h"

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"

 #define GETGm   gd = ((nextop&0x38)>>3)
@@ -36,6 +37,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
    uint8_t u8;
    int32_t i32;
    int64_t j64, i64;
+    int16_t i16;
    int cacheupd = 0;
    int lock;
    int v0, v1, s0;
@@ -53,11 +55,18 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
        return addr;
    }

+
+    while(opcode==0x67) opcode = F8;
+    
+    // reset rex after 67
    GETREX();

    rep = 0;
-    while((opcode==0xF2) || (opcode==0xF3)) {
-        rep = opcode-0xF1;
+    while((opcode==0xF2) || (opcode==0xF3) || (opcode>=0x40 && opcode<=0x4F)) {
+        if((opcode==0xF2) || (opcode==0xF3))
+            rep = opcode-0xF1;
+        if(opcode>=0x40 && opcode<=0x4F)
+            rex.rex = opcode;
        opcode = F8;
    }

@@ -200,13 +209,46 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                            if(MODREG) {
                                s0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 0);
                            } else {
-                                s0 = fpu_get_scratch(dyn);
+                                s0 = fpu_get_scratch(dyn, ninst);
                                SMREAD();
                                addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
                                VLD32(s0, ed, fixedaddress);
                            }
                            FCMPS(v0, s0);
-                            FCOMI(x1, x2);
+                            FCOMI(x1, x2, 0, v0, s0, 1);    //disabled precise cmp
+                            break;
+                        default:
+                            DEFAULT;
+                    }
+                    break;
+
+                case 0x38:  /* MAP 0F38 */
+                    opcode = F8;
+                    switch(opcode) {
+                        case 0xF6:
+                            switch(rep) {
+                                case 2:
+                                    INST_NAME("ADOX Gd, Ed");
+                                    nextop = F8;
+                                    READFLAGS(X_OF);
+                                    SETFLAGS(X_OF, SF_SUBSET);
+                                    GETED32(0);
+                                    GETGD;
+                                    MRS_nzcv(x3);
+                                    LSRw(x4, xFlags, F_OF);
+                                    BFIx(x3, x4, 29, 1); // set C
+                                    MSR_nzcv(x3);      // load CC into ARM CF
+                                    IFX(X_OF) {
+                                        ADCSxw_REG(gd, gd, ed);
+                                        CSETw(x3, cCS);
+                                        BFIw(xFlags, x3, F_OF, 1);
+                                    } else {
+                                        ADCxw_REG(gd, gd, ed);
+                                    }
+                                    break;
+                                default:
+                                    DEFAULT;
+                            }
                            break;
                        default:
                            DEFAULT;
@@ -264,6 +306,19 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                                SMWRITE();
                            }
                            break;
+                        case 2:
+                            INST_NAME("MOVDQU Ex, Gx");
+                            nextop = F8;
+                            GETGX(v0, 0);
+                            if(MODREG) {
+                                v1 = sse_get_reg_empty(dyn, ninst, x1, nextop&7);
+                                VMOVQ(v1, v0);
+                            } else {
+                                addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0);
+                                VST128(v0, ed, fixedaddress);
+                                SMWRITE();
+                            }
+                            break;
                        default:
                            DEFAULT;
                    }
@@ -275,11 +330,11 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    GETGD;
                    if(MODREG) {
                        if(rex.rex) {
-                            eb1 = xRAX+(nextop&7)+(rex.b<<3);
+                            eb1 = TO_NAT((nextop & 7) + (rex.b << 3));
                            eb2 = 0;
                        } else {
                            ed = (nextop&7);
-                            eb1 = xRAX+(ed&3);  // Ax, Cx, Dx or Bx
+                            eb1 = TO_NAT(ed & 3); // Ax, Cx, Dx or Bx
                            eb2 = (ed&4)>>2;    // L or H
                        }
                        UBFXxw(gd, eb1, eb2*8, 8);
@@ -294,7 +349,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    nextop = F8;
                    GETGD;
                    if(MODREG) {
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        UBFXxw(gd, ed, 0, 16);
                    } else {
                        SMREAD();
@@ -627,13 +682,32 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                emit_cmp32_0(dyn, ninst, rex, xRAX, x3, x4);
            break;

+        case 0x50:
+        case 0x51:
+        case 0x52:
+        case 0x53:
+        case 0x54:
+        case 0x55:
+        case 0x56:
+        case 0x57:
+        case 0x58:
+        case 0x59:
+        case 0x5A:
+        case 0x5B:
+        case 0x5C:
+        case 0x5D:
+        case 0x5E:
+        case 0x5F:
+            // just use regular conditional jump
+            return dynarec64_00(dyn, addr-1, ip, ninst, rex, rep, ok, need_epilog);
+
        case 0x63:
            INST_NAME("MOVSXD Gd, Ed");
            nextop = F8;
            GETGD;
            if(rex.w) {
                if(MODREG) {   // reg <= reg
-                    SXTWx(gd, xRAX+(nextop&7)+(rex.b<<3));
+                    SXTWx(gd, TO_NAT((nextop & 7) + (rex.b << 3)));
                } else {                    // mem <= reg
                    SMREAD();
                    addr = geted32(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
@@ -641,7 +715,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                }
            } else {
                if(MODREG) {   // reg <= reg
-                    MOVw_REG(gd, xRAX+(nextop&7)+(rex.b<<3));
+                    MOVw_REG(gd, TO_NAT((nextop & 7) + (rex.b << 3)));
                } else {                    // mem <= reg
                    SMREAD();
                    addr = geted32(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
@@ -652,29 +726,273 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin

        case 0x66:
            opcode=F8;
+            GETREX();
            switch(opcode) {

+                case 0x0F:
+                    nextop = F8;
+                    switch(nextop) {
+                        case 0x6F:
+                            INST_NAME("MOVDQA Gx,Ex");
+                            nextop = F8;
+                            if(MODREG) {
+                                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                                GETGX_empty(v0);
+                                VMOVQ(v0, v1);
+                            } else {
+                                GETGX_empty(v0);
+                                SMREAD();
+                                addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0);
+                                VLD128(v0, ed, fixedaddress);
+                            }
+                            break;
+
+                        case 0x7E:
+                            INST_NAME("MOVD Ed,Gx");
+                            nextop = F8;
+                            GETGX(v0, 0);
+                            if(rex.w) {
+                                if(MODREG) {
+                                    ed = TO_NAT((nextop & 0x07) + (rex.b << 3));
+                                    VMOVQDto(ed, v0, 0);
+                                } else {
+                                    addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                                    VST64(v0, ed, fixedaddress);
+                                    SMWRITE2();
+                                }
+                            } else {
+                                if(MODREG) {
+                                    ed = TO_NAT((nextop & 0x07) + (rex.b << 3));
+                                    VMOVSto(ed, v0, 0);
+                                } else {
+                                    addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                                    VST32(v0, ed, fixedaddress);
+                                    SMWRITE2();
+                                }
+                            }
+                            break;
+
+                        case 0xD6:
+                            INST_NAME("MOVQ Ex, Gx");
+                            nextop = F8;
+                            GETGX(v0, 0);
+                            if(MODREG) {
+                                v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
+                                FMOVD(v1, v0);
+                            } else {
+                                addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                                VST64(v0, ed, fixedaddress);
+                                SMWRITE2();
+                            }
+                            break;
+
+                        case 0xFE:
+                            INST_NAME("PADDD Gx,Ex");
+                            nextop = F8;
+                            GETGX(v0, 1);
+                            GETEX32(v1, 0, 0);
+                            VADDQ_32(v0, v0, v1);
+                            break;
+
+                            default:
+                                DEFAULT;
+                    }
+                    break;
+
+                    case 0x81:
+                    case 0x83:
+                        nextop = F8;
+                        switch((nextop>>3)&7) {
+                            case 0: //ADD
+                                if(opcode==0x81) {INST_NAME("ADD Ew, Iw");} else {INST_NAME("ADD Ew, Ib");}
+                                SETFLAGS(X_ALL, SF_SET_PENDING);
+                                GETEW32(x1, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                                MOVZw(x5, i16);
+                                emit_add16(dyn, ninst, ed, x5, x2, x4);
+                                EWBACK;
+                                break;
+                            case 1: //OR
+                                if(opcode==0x81) {INST_NAME("OR Ew, Iw");} else {INST_NAME("OR Ew, Ib");}
+                                SETFLAGS(X_ALL, SF_SET_PENDING);
+                                GETEW32(x1, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                                emit_or16c(dyn, ninst, x1, i16, x2, x4);
+                                EWBACK;
+                                break;
+                            case 2: //ADC
+                                if(opcode==0x81) {INST_NAME("ADC Ew, Iw");} else {INST_NAME("ADC Ew, Ib");}
+                                READFLAGS(X_CF);
+                                SETFLAGS(X_ALL, SF_SET_PENDING);
+                                GETEW32(x1, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                                MOVZw(x5, i16);
+                                emit_adc16(dyn, ninst, x1, x5, x2, x4);
+                                EWBACK;
+                                break;
+                            case 3: //SBB
+                                if(opcode==0x81) {INST_NAME("SBB Ew, Iw");} else {INST_NAME("SBB Ew, Ib");}
+                                READFLAGS(X_CF);
+                                SETFLAGS(X_ALL, SF_SET_PENDING);
+                                GETEW32(x1, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                                MOVZw(x5, i16);
+                                emit_sbb16(dyn, ninst, x1, x5, x2, x4);
+                                EWBACK;
+                                break;
+                            case 4: //AND
+                                if(opcode==0x81) {INST_NAME("AND Ew, Iw");} else {INST_NAME("AND Ew, Ib");}
+                                SETFLAGS(X_ALL, SF_SET_PENDING);
+                                GETEW32(x1, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                                emit_and16c(dyn, ninst, x1, i16, x2, x4);
+                                EWBACK;
+                                break;
+                            case 5: //SUB
+                                if(opcode==0x81) {INST_NAME("SUB Ew, Iw");} else {INST_NAME("SUB Ew, Ib");}
+                                SETFLAGS(X_ALL, SF_SET_PENDING);
+                                GETEW32(x1, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                                MOVZw(x5, i16);
+                                emit_sub16(dyn, ninst, x1, x5, x2, x4);
+                                EWBACK;
+                                break;
+                            case 6: //XOR
+                                if(opcode==0x81) {INST_NAME("XOR Ew, Iw");} else {INST_NAME("XOR Ew, Ib");}
+                                SETFLAGS(X_ALL, SF_SET_PENDING);
+                                GETEW32(x1, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                                emit_xor16c(dyn, ninst, x1, i16, x2, x4);
+                                EWBACK;
+                                break;
+                            case 7: //CMP
+                                if(opcode==0x81) {INST_NAME("CMP Ew, Iw");} else {INST_NAME("CMP Ew, Ib");}
+                                SETFLAGS(X_ALL, SF_SET_PENDING);
+                                GETEW32(x1, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i16 = F16S; else i16 = F8S;
+                                if(i16) {
+                                    MOVZw(x2, i16);
+                                    emit_cmp16(dyn, ninst, x1, x2, x3, x4, x5);
+                                } else
+                                    emit_cmp16_0(dyn, ninst, x1, x3, x4);
+                                break;
+                        }
+                        break;
                case 0x89:
                    INST_NAME("MOV Ew, Gw");
                    nextop = F8;
                    GETGD;  // don't need GETGW here
                    if(MODREG) {
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        if(ed!=gd) {
                            BFIx(ed, gd, 0, 16);
                        }
                    } else {
-                        addr = geted32(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, &lock, 0, 0);
+                        addr = geted32(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff << 1, 1, rex, &lock, 0, 0);
                        STH(gd, ed, fixedaddress);
                        SMWRITELOCK(lock);
                    }
                    break;

+                case 0x8D:
+                    INST_NAME("LEA Gw, Ed");
+                    nextop=F8;
+                    //GETGW(x1);
+                    gd = x1;    // no need to read
+                    if(MODREG) {   // reg <= reg? that's an invalid operation
+                        DEFAULT;
+                    } else {                    // mem <= reg
+                        addr = geted32(dyn, addr, ninst, nextop, &ed, gd, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                        if(ed!=gd)
+                            gd = ed;
+                    }
+                    GWBACK;
+                    break;
+
                default:
                    DEFAULT;
            }
            break;

+        case 0x6B:
+            INST_NAME("IMUL Gd, Ed, Ib");
+            SETFLAGS(X_ALL, SF_PENDING);
+            nextop = F8;
+            GETGD;
+            GETED32(1);
+            i64 = F8S;
+            MOV64xw(x4, i64);
+            if(rex.w) {
+                // 64bits imul
+                UFLAG_IF {
+                    SMULH(x3, ed, x4);
+                    MULx(gd, ed, x4);
+                    SET_DFNONE(x1);
+                    IFX(X_ZF | X_PF | X_AF | X_SF) {
+                        MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
+                        BICw(xFlags, xFlags, x1);
+                    }
+                    IFX(X_CF | X_OF) {
+                        ASRx(x4, gd, 63);
+                        CMPSx_REG(x3, x4);
+                        CSETw(x1, cNE);
+                        IFX(X_CF) {
+                            BFIw(xFlags, x1, F_CF, 1);
+                        }
+                        IFX(X_OF) {
+                            BFIw(xFlags, x1, F_OF, 1);
+                        }
+                    }
+                } else {
+                    MULxw(gd, ed, x4);
+                }
+            } else {
+                // 32bits imul
+                UFLAG_IF {
+                    SMULL(gd, ed, x4);
+                    LSRx(x3, gd, 32);
+                    MOVw_REG(gd, gd);
+                    SET_DFNONE(x1);
+                    IFX(X_ZF | X_PF | X_AF | X_SF) {
+                        MOV32w(x1, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
+                        BICw(xFlags, xFlags, x1);
+                    }
+                    IFX(X_CF | X_OF) {
+                        ASRw(x4, gd, 31);
+                        CMPSw_REG(x3, x4);
+                        CSETw(x1, cNE);
+                        IFX(X_CF) {
+                            BFIw(xFlags, x1, F_CF, 1);
+                        }
+                        IFX(X_OF) {
+                            BFIw(xFlags, x1, F_OF, 1);
+                        }
+                    }
+                } else {
+                    MULxw(gd, ed, x4);
+                }
+            }
+            break;
+
+        case 0x70:
+        case 0x71:
+        case 0x72:
+        case 0x73:
+        case 0x74:
+        case 0x75:
+        case 0x76:
+        case 0x77:
+        case 0x78:
+        case 0x79:
+        case 0x7A:
+        case 0x7B:
+        case 0x7C:
+        case 0x7D:
+        case 0x7E:
+        case 0x7F:
+            // just use regular conditional jump
+            return dynarec64_00(dyn, addr-1, ip, ninst, rex, rep, ok, need_epilog);
+
        case 0x81:
        case 0x83:
            nextop = F8;
@@ -759,10 +1077,10 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            gd = ((nextop&0x38)>>3)+(rex.r<<3);
            if(rex.rex) {
                gb2 = 0;
-                gb1 = xRAX + gd;
+                gb1 = TO_NAT(gd);
            } else {
                gb2 = ((gd&4)<<1);
-                gb1 = xRAX+(gd&3);
+                gb1 = TO_NAT(gd & 3);
            }
            if(gb2) {
                gd = x4;
@@ -773,10 +1091,10 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            if(MODREG) {
                ed = (nextop&7) + (rex.b<<3);
                if(rex.rex) {
-                    eb1 = xRAX+ed;
+                    eb1 = TO_NAT(ed);
                    eb2 = 0;
                } else {
-                    eb1 = xRAX+(ed&3);  // Ax, Cx, Dx or Bx
+                    eb1 = TO_NAT(ed & 3); // Ax, Cx, Dx or Bx
                    eb2 = ((ed&4)>>2);    // L or H
                }
                BFIx(eb1, gd, eb2*8, 8);
@@ -791,9 +1109,9 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            nextop=F8;
            GETGD;
            if(MODREG) {   // reg <= reg
-                MOVxw_REG(xRAX+(nextop&7)+(rex.b<<3), gd);
+                MOVxw_REG(TO_NAT((nextop & 7) + (rex.b << 3)), gd);
            } else {                    // mem <= reg
-                addr = geted32(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, &lock, 0, 0);
+                addr = geted32(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff << (2 + rex.w), (1 << (2 + rex.w)) - 1, rex, &lock, 0, 0);
                STxw(gd, ed, fixedaddress);
                SMWRITELOCK(lock);
            }
@@ -802,21 +1120,21 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            INST_NAME("MOV Gb, Eb");
            nextop = F8;
            if(rex.rex) {
-                gb1 = gd = xRAX+((nextop&0x38)>>3)+(rex.r<<3);
+                gb1 = gd = TO_NAT(((nextop & 0x38) >> 3) + (rex.r << 3));
                gb2=0;
            } else {
                gd = (nextop&0x38)>>3;
-                gb1 = xRAX+(gd&3);
+                gb1 = TO_NAT(gd & 3);
                gb2 = ((gd&4)<<1);
            }
            if(MODREG) {
                if(rex.rex) {
-                    wback = xRAX+(nextop&7)+(rex.b<<3);
+                    wback = TO_NAT((nextop & 7) + (rex.b << 3));
                    wb2 = 0;
                } else {
                    wback = (nextop&7);
                    wb2 = (wback>>2);
-                    wback = xRAX+(wback&3);
+                    wback = TO_NAT(wback & 3);
                }
                if(wb2) {
                    UBFXw(x4, wback, wb2*8, 8);
@@ -837,7 +1155,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            nextop=F8;
            GETGD;
            if(MODREG) {
-                MOVxw_REG(gd, xRAX+(nextop&7)+(rex.b<<3));
+                MOVxw_REG(gd, TO_NAT((nextop & 7) + (rex.b << 3)));
            } else {
                addr = geted32(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, &lock, 0, 0);
                SMREADLOCK(lock);
@@ -859,12 +1177,38 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            }
            break;

+        case 0x90:
+        case 0x91:
+        case 0x92:
+        case 0x93:
+        case 0x94:
+        case 0x95:
+        case 0x96:
+        case 0x97:
+            gd = TO_NAT((opcode & 0x07) + (rex.b << 3));
+            if(gd==xRAX) {
+                INST_NAME("NOP");
+            } else {
+                INST_NAME("XCHG EAX, Reg");
+                MOVxw_REG(x2, xRAX);
+                MOVxw_REG(xRAX, gd);
+                MOVxw_REG(gd, x2);
+            }
+            break;
+
+        case 0xA9:
+            INST_NAME("TEST EAX, Id");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            i64 = F32S;
+            emit_test32c(dyn, ninst, rex, xRAX, i64, x3, x4, x5);
+            break;
+
        case 0xC1:
            nextop = F8;
            switch((nextop>>3)&7) {
                case 0:
                    INST_NAME("ROL Ed, Ib");
-                    SETFLAGS(X_OF|X_CF, SF_SUBSET_PENDING);
+                    SETFLAGS(X_OF|X_CF, SF_SUBSET); // removed PENDING on purpose
                    GETED32(1);
                    u8 = (F8)&(rex.w?0x3f:0x1f);
                    emit_rol32c(dyn, ninst, rex, ed, u8, x3, x4);
@@ -872,7 +1216,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    break;
                case 1:
                    INST_NAME("ROR Ed, Ib");
-                    SETFLAGS(X_OF|X_CF, SF_SUBSET_PENDING);
+                    SETFLAGS(X_OF|X_CF, SF_SUBSET); // removed PENDING on purpose
                    GETED32(1);
                    u8 = (F8)&(rex.w?0x3f:0x1f);
                    emit_ror32c(dyn, ninst, rex, ed, u8, x3, x4);
@@ -880,34 +1224,32 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    break;
                case 2:
                    INST_NAME("RCL Ed, Ib");
-                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                    READFLAGS(X_CF);
-                    SETFLAGS(X_OF|X_CF, SF_SET);
-                    GETED32W(x4, x1, 1);
-                    u8 = F8;
-                    MOV32w(x2, u8);
-                    CALL_(rex.w?((void*)rcl64):((void*)rcl32), ed, x4);
-                    WBACK;
+                    SETFLAGS(X_OF|X_CF, SF_SUBSET); // removed PENDING on purpose
+                    GETED32(1);
+                    u8 = (F8)&(rex.w?0x3f:0x1f);
+                    emit_rcl32c(dyn, ninst, rex, ed, u8, x3, x4);
+                    if(u8) { WBACK; }
                    break;
                case 3:
                    INST_NAME("RCR Ed, Ib");
-                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                    READFLAGS(X_CF);
-                    SETFLAGS(X_OF|X_CF, SF_SET);
-                    GETED32W(x4, x1, 1);
-                    u8 = F8;
-                    MOV32w(x2, u8);
-                    CALL_(rex.w?((void*)rcr64):((void*)rcr32), ed, x4);
-                    WBACK;
+                    SETFLAGS(X_OF|X_CF, SF_SUBSET); // removed PENDING on purpose
+                    GETED32(1);
+                    u8 = (F8)&(rex.w?0x3f:0x1f);
+                    emit_rcr32c(dyn, ninst, rex, ed, u8, x3, x4);
+                    if(u8) { WBACK; }
                    break;
                case 4:
                case 6:
                    INST_NAME("SHL Ed, Ib");
-                    SETFLAGS(X_ALL, SF_SET_PENDING);    // some flags are left undefined
                    GETED32(1);
                    u8 = (F8)&(rex.w?0x3f:0x1f);
-                    emit_shl32c(dyn, ninst, rex, ed, u8, x3, x4);
-                    WBACK;
+                    if(u8) {    //should create the geted32_ib utility function for that
+                        SETFLAGS(X_ALL, SF_SET_PENDING);    // some flags are left undefined
+                        emit_shl32c(dyn, ninst, rex, ed, u8, x3, x4);
+                        WBACK;
+                    }
                    break;
                case 5:
                    INST_NAME("SHR Ed, Ib");
@@ -932,12 +1274,86 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            }
            break;

+        case 0xC4:
+            nextop = F8;
+            if(rex.is32bits && !(MODREG)) {
+                DEFAULT;
+            } else {
+                if(rex.is32bits) {
+                    DEFAULT;
+                    return addr;
+                }
+                vex_t vex = {0};
+                vex.rex = rex;
+                u8 = nextop;
+                vex.m = u8&0b00011111;
+                vex.rex.b = (u8&0b00100000)?0:1;
+                vex.rex.x = (u8&0b01000000)?0:1;
+                vex.rex.r = (u8&0b10000000)?0:1;
+                u8 = F8;
+                vex.p = u8&0b00000011;
+                vex.l = (u8>>2)&1;
+                vex.v = ((~u8)>>3)&0b1111;
+                vex.rex.w = (u8>>7)&1;
+                addr = dynarec64_67_AVX(dyn, addr, ip, ninst, vex, ok, need_epilog);
+            }
+            break;
+        case 0xC5:
+            nextop = F8;
+            if(rex.is32bits && !(MODREG)) {
+                DEFAULT;
+            } else {
+                if(rex.is32bits) {
+                    DEFAULT;
+                    return addr;
+                }
+                vex_t vex = {0};
+                vex.rex = rex;
+                u8 = nextop;
+                vex.p = u8&0b00000011;
+                vex.l = (u8>>2)&1;
+                vex.v = ((~u8)>>3)&0b1111;
+                vex.rex.r = (u8&0b10000000)?0:1;
+                vex.rex.b = 0;
+                vex.rex.x = 0;
+                vex.rex.w = 0;
+                vex.m = VEX_M_0F;
+                addr = dynarec64_67_AVX(dyn, addr, ip, ninst, vex, ok, need_epilog);
+            }
+            break;
+        case 0xC6:
+            INST_NAME("MOV Eb, Ib");
+            nextop=F8;
+            if(MODREG) {   // reg <= u8
+                u8 = F8;
+                if(!rex.rex) {
+                    ed = (nextop&7);
+                    eb1 = TO_NAT(ed & 3); // Ax, Cx, Dx or Bx
+                    eb2 = (ed&4)>>2;    // L or H
+                } else {
+                    eb1 = TO_NAT((nextop & 7) + (rex.b << 3));
+                    eb2 = 0;
+                }
+                MOV32w(x3, u8);
+                BFIx(eb1, x3, eb2*8, 8);
+            } else {                    // mem <= u8
+                addr = geted32(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, &unscaled, 0xfff, 0, rex, &lock, 0, 1);
+                u8 = F8;
+                if(u8) {
+                    MOV32w(x3, u8);
+                    ed = x3;
+                } else
+                    ed = xZR;
+                STB(ed, wback, fixedaddress);
+                SMWRITELOCK(lock);
+            }
+            break;
        case 0xC7:
            INST_NAME("MOV Ed, Id");
            nextop=F8;
            if(MODREG) {   // reg <= i32
                i64 = F32S;
-                ed = xRAX+(nextop&7)+(rex.b<<3);
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                MOV64xw(ed, i64);
            } else {                    // mem <= i32
                addr = geted32(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, &lock, 0, 4);
@@ -960,25 +1376,27 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                if(dyn->insts[ninst].x64.jmp_insts==-1) {               \
                    if(!(dyn->insts[ninst].x64.barrier&BARRIER_FLOAT))  \
                        fpu_purgecache(dyn, ninst, 1, x1, x2, x3);      \
-                    jump_to_next(dyn, addr+i8, 0, ninst);               \
+                    jump_to_next(dyn, addr+i8, 0, ninst, rex.is32bits); \
                } else {                                                \
                    CacheTransform(dyn, ninst, cacheupd, x1, x2, x3);   \
                    i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size);\
+                    SKIP_SEVL(i32);                                     \
                    B(i32);                                             \
                }                                                       \
-            } else {    \
-                /* inside the block */  \
+            } else {                                                    \
+                /* inside the block */                                  \
                i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size);    \
-                Bcond(YES, i32);    \
+                SKIP_SEVL(i32);                                         \
+                Bcond(YES, i32);                                        \
            }
        case 0xE0:
            INST_NAME("LOOPNZ (32bits)");
            READFLAGS(X_ZF);
            i8 = F8S;
            MOVw_REG(x1, xRCX);
-            SUBSw_U12(x1, x1, 1);
+            SUBw_U12(x1, x1, 1);
            BFIx(xRCX, x1, 0, 32);
-            B_NEXT(cEQ);    // ECX is 0, no LOOP
+            CBZw_NEXT(x1);    // ECX is 0, no LOOP
            TSTw_mask(xFlags, 0b011010, 0); //mask=0x40
            GO(cNE, cEQ);
            break;
@@ -987,9 +1405,9 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            READFLAGS(X_ZF);
            i8 = F8S;
            MOVw_REG(x1, xRCX);
-            SUBSw_U12(x1, x1, 1);
+            SUBw_U12(x1, x1, 1);
            BFIx(xRCX, x1, 0, 32);
-            B_NEXT(cEQ);    // ECX is 0, no LOOP
+            CBZw_NEXT(x1);    // ECX is 0, no LOOP
            TSTw_mask(xFlags, 0b011010, 0); //mask=0x40
            GO(cEQ, cNE);
            break;
@@ -1022,8 +1440,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    GETED32H(x1, 4);
                    i64 = F32S;
-                    MOV64xw(x2, i64);
-                    emit_test32(dyn, ninst, rex, ed, x2, x3, x4, x5);
+                    emit_test32c(dyn, ninst, rex, ed, i64, x3, x4, x5);
                    break;
                case 2:
                    INST_NAME("NOT Ed");
@@ -1040,7 +1457,7 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    break;
                case 4:
                    INST_NAME("MUL EAX, Ed");
-                    SETFLAGS(X_ALL, SF_PENDING);
+                    SETFLAGS(X_ALL, SF_SET);
                    GETED32(0);
                    if(rex.w) {
                        if(ed==xRDX) gd=x3; else gd=xRDX;
@@ -1052,9 +1469,25 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                        MOVw_REG(xRAX, xRDX);
                        LSRx(xRDX, xRDX, 32);
                    }
-                    UFLAG_RES(xRAX);
-                    UFLAG_OP1(xRDX);
-                    UFLAG_DF(x2, rex.w?d_mul64:d_mul32);
+                    UFLAG_IF {
+                        SET_DFNONE(x4);
+                        IFX(X_CF|X_OF) {
+                            CMPSxw_U12(xRDX, 0);
+                            CSETw(x3, cNE);
+                            IFX(X_CF) {
+                                BFIw(xFlags, x3, F_CF, 1);
+                            }
+                            IFX(X_OF) {
+                                BFIw(xFlags, x3, F_OF, 1);
+                            }
+                        }
+                        IFX(X_AF | X_PF | X_ZF | X_SF)
+                            if(box64_dynarec_test) {
+                                // to avoid noise during test
+                                MOV32w(x3, (1<<F_ZF)|(1<<F_AF)|(1<<F_PF)|(1<<F_SF));
+                                BICw(xFlags, xFlags, x3);
+                            }
+                    }
                    break;
                case 5:
                    INST_NAME("IMUL EAX, Ed");
@@ -1078,7 +1511,6 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    INST_NAME("DIV Ed");
                    SETFLAGS(X_ALL, SF_SET);
                    if(!rex.w) {
-                        SET_DFNONE(x2);
                        GETED32(0);
                        MOVw_REG(x3, xRAX);
                        ORRx_REG_LSL(x3, x3, xRDX, 32);
@@ -1095,7 +1527,6 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                           && dyn->insts[ninst-1].x64.addr
                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr)==0x31
                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr+1)==0xD2) {
-                            SET_DFNONE(x2);
                            GETED32(0);
                            UDIVx(x2, xRAX, ed);
                            MSUBx(xRDX, x2, ed, xRAX);
@@ -1110,16 +1541,20 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                            UDIVx(x2, xRAX, ed);
                            MSUBx(xRDX, x2, ed, xRAX);
                            MOVx_REG(xRAX, x2);
-                            SET_DFNONE(x2);
                        }
                    }
+                    SET_DFNONE(x2);
+                    IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
+                        if(box64_dynarec_test) {
+                            MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
+                            BICw(xFlags, xFlags, x1);
+                        }
                    break;
                case 7:
                    INST_NAME("IDIV Ed");
                    NOTEST(x1);
                    SETFLAGS(X_ALL, SF_SET);
                    if(!rex.w) {
-                        SET_DFNONE(x2)
                        GETSED32w(0);
                        MOVw_REG(x3, xRAX);
                        ORRx_REG_LSL(x3, x3, xRDX, 32);
@@ -1132,7 +1567,6 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                           &&  dyn->insts[ninst-1].x64.addr
                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr)==0x48
                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr+1)==0x99) {
-                            SET_DFNONE(x2)
                            GETED32(0);
                            SDIVx(x2, xRAX, ed);
                            MSUBx(xRDX, x2, ed, xRAX);
@@ -1149,12 +1583,84 @@ uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                            SDIVx(x2, xRAX, ed);
                            MSUBx(xRDX, x2, ed, xRAX);
                            MOVx_REG(xRAX, x2);
-                            SET_DFNONE(x2)
                        }
                    }
+                    SET_DFNONE(x2);
+                    IFX(X_AF | X_SF | X_CF | X_PF | X_ZF | X_OF)
+                        if(box64_dynarec_test) {
+                            MOV32w(x1, (1<<F_AF) | (1<<F_SF) | (1<<F_CF) | (1<<F_PF) | (1<<F_ZF) | (1<<F_OF));
+                            BICw(xFlags, xFlags, x1);
+                        }
                    break;
            }
            break;
+        case 0xFF:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 0: // INC Ed
+                    INST_NAME("INC Ed");
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET);
+                    GETED32(0);
+                    emit_inc32(dyn, ninst, rex, ed, x3, x4);
+                    WBACK;
+                    break;
+                case 1: //DEC Ed
+                    INST_NAME("DEC Ed");
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET);
+                    GETED32(0);
+                    emit_dec32(dyn, ninst, rex, ed, x3, x4);
+                    WBACK;
+                    break;
+                case 2: // CALL Ed
+                    INST_NAME("CALL Ed");
+                    PASS2IF((box64_dynarec_safeflags>1) ||
+                        ((ninst && dyn->insts[ninst-1].x64.set_flags)
+                        || ((ninst>1) && dyn->insts[ninst-2].x64.set_flags)), 1)
+                    {
+                        READFLAGS(X_PEND);          // that's suspicious
+                    } else {
+                        SETFLAGS(X_ALL, SF_SET_NODF);    //Hack to put flag in "don't care" state
+                    }
+                    GETED32(0);
+                    if(box64_dynarec_callret && box64_dynarec_bigblock>1) {
+                        BARRIER(BARRIER_FULL);
+                    } else {
+                        BARRIER(BARRIER_FLOAT);
+                        *need_epilog = 0;
+                        *ok = 0;
+                    }
+                    GETIP_(addr);
+                    if(box64_dynarec_callret) {
+                        SET_HASCALLRET();
+                        // Push actual return address
+                        if(addr < (dyn->start+dyn->isize)) {
+                            // there is a next...
+                            j64 = (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->native_size)):0;
+                            ADR_S20(x4, j64);
+                            MESSAGE(LOG_NONE, "\tCALLRET set return to +%di\n", j64>>2);
+                        } else {
+                            j64 = (dyn->insts)?(GETMARK-(dyn->native_size)):0;
+                            ADR_S20(x4, j64);
+                            MESSAGE(LOG_NONE, "\tCALLRET set return to +%di\n", j64>>2);
+                        }
+                        STPx_S7_preindex(x4, xRIP, xSP, -16);
+                    }
+                    PUSH1z(xRIP);
+                    jump_to_next(dyn, 0, ed, ninst, rex.is32bits);
+                    if(box64_dynarec_callret && addr >= (dyn->start + dyn->isize)) {
+                        // jumps out of current dynablock...
+                        MARK;
+                        j64 = getJumpTableAddress64(addr);
+                        TABLE64(x4, j64);
+                        LDRx_U12(x4, x4, 0);
+                        BR(x4);
+                    }
+                    break;
+                default:
+                    DEFAULT;
+                    return addr;
+            }
+            break;

        default:
            DEFAULT;
@@ -18,7 +18,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"

 #define GETGm   gd = ((nextop&0x38)>>3)
@@ -61,6 +61,60 @@ uintptr_t dynarec64_6764_32(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, in

    switch(opcode) {

+        case 0x89:
+            INST_NAME("MOV Seg:Ed, Gd");
+            nextop=F8;
+            GETGD;
+            if(MODREG) {   // reg <= reg
+                MOVxw_REG(TO_NAT((nextop & 7) + (rex.b << 3)), gd);
+            } else {                    // mem <= reg
+                grab_segdata(dyn, addr, ninst, x4, seg);
+                addr = geted16(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, NULL, 0, 0, 0);
+                STRw_REG(gd, ed, x4);
+            }
+            break;
+
+        case 0x8B:
+            INST_NAME("MOV Gd, Seg:Ed");
+            nextop=F8;
+            GETGD;
+            if(MODREG) {   // reg => reg
+                MOVxw_REG(gd, TO_NAT((nextop & 7) + (rex.b << 3)));
+            } else {                    // mem => reg
+                grab_segdata(dyn, addr, ninst, x4, seg);
+                addr = geted16(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, NULL, 0, 0, 0);
+                LDRw_REG(gd, ed, x4);
+            }
+            break;
+
+        case 0x8F:
+            INST_NAME("POP Seg:Ed");
+            nextop=F8;
+            if(MODREG) {   // reg <= reg
+                POP1_32(x1);
+                MOVxw_REG(TO_NAT((nextop & 7) + (rex.b << 3)), x1);
+            } else {                    // mem <= reg
+                grab_segdata(dyn, addr, ninst, x4, seg);
+                POP1_32(x1);
+                addr = geted16(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, NULL, 0, 0, 0);
+                STRw_REG(x1, ed, x4);
+            }
+            break;
+
+        case 0xA1:
+            INST_NAME("MOV EAX, Seg:[Od]");
+            i32 = F16;
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            if(i32<4096 && !(i32&3)) {
+                LDRw_U12(xRAX, x4, i32);
+            } else if(i32<256) {
+                LDURw_I9(xRAX, x4, i32);
+            } else {
+                MOV32w(x1, i32);
+                LDRw_REG(xRAX, x4, x1);
+            }
+            break;
+
        case 0xA3:
            INST_NAME("MOV Seg:[Od], EAX");
            i32 = F16;
@@ -18,7 +18,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"

 #define GETGm   gd = ((nextop&0x38)>>3)
@@ -65,6 +65,68 @@ uintptr_t dynarec64_67_32(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int
            addr = dynarec64_6764_32(dyn, addr, ip, ninst, rex, rep, _FS, ok, need_epilog);
            break;

+        #define GO(NO, YES)                                             \
+            BARRIER(BARRIER_MAYBE);                                     \
+            JUMP(addr+i8, 1);                                           \
+            if(dyn->insts[ninst].x64.jmp_insts==-1 ||                   \
+                CHECK_CACHE()) {                                        \
+                /* out of the block */                                  \
+                i32 = dyn->insts[ninst].epilog-(dyn->native_size);      \
+                Bcond(NO, i32);                                         \
+                if(dyn->insts[ninst].x64.jmp_insts==-1) {               \
+                    if(!(dyn->insts[ninst].x64.barrier&BARRIER_FLOAT))  \
+                        fpu_purgecache(dyn, ninst, 1, x1, x2, x3);      \
+                    jump_to_next(dyn, addr+i8, 0, ninst, rex.is32bits); \
+                } else {                                                \
+                    CacheTransform(dyn, ninst, cacheupd, x1, x2, x3);   \
+                    i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size);\
+                    SKIP_SEVL(i32);                                     \
+                    B(i32);                                             \
+                }                                                       \
+            } else {                                                    \
+                /* inside the block */                                  \
+                i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size);    \
+                SKIP_SEVL(i32);                                         \
+                Bcond(YES, i32);                                        \
+            }
+        case 0xE0:
+            INST_NAME("LOOPNZ (16bits)");
+            READFLAGS(X_ZF);
+            i8 = F8S;
+            UXTHw(x1, xRCX);
+            SUBw_U12(x1, x1, 1);
+            BFIx(xRCX, x1, 0, 16);
+            CBZw_NEXT(x1);    // ECX is 0, no LOOP
+            TSTw_mask(xFlags, 0b011010, 0); //mask=0x40
+            GO(cNE, cEQ);
+            break;
+        case 0xE1:
+            INST_NAME("LOOPZ (16bits)");
+            READFLAGS(X_ZF);
+            i8 = F8S;
+            UXTHw(x1, xRCX);
+            SUBw_U12(x1, x1, 1);
+            BFIx(xRCX, x1, 0, 16);
+            CBZw_NEXT(x1);    // ECX is 0, no LOOP
+            TSTw_mask(xFlags, 0b011010, 0); //mask=0x40
+            GO(cEQ, cNE);
+            break;
+        case 0xE2:
+            INST_NAME("LOOP (16bits)");
+            i8 = F8S;
+            UXTHw(x1, xRCX);
+            SUBSw_U12(x1, x1, 1);
+            BFIx(xRCX, x1, 0, 16);
+            GO(cEQ, cNE);
+            break;
+        case 0xE3:
+            INST_NAME("JCXZ");
+            i8 = F8S;
+            TSTw_mask(xRCX, 0, 15); //mask=0xffff
+            GO(cNE, cEQ);
+            break;
+        #undef GO
+        
        default:
            DEFAULT;
    }
@@ -0,0 +1,133 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "../dynarec_helper.h"
+
+static const char* avx_prefix_string(uint16_t p)
+{
+    switch(p) {
+        case VEX_P_NONE: return "0";
+        case VEX_P_66: return "66";
+        case VEX_P_F2: return "F2";
+        case VEX_P_F3: return "F3";
+        default: return "??";
+    }
+}
+static const char* avx_map_string(uint16_t m)
+{
+    switch(m) {
+        case VEX_M_NONE: return "0";
+        case VEX_M_0F: return "0F";
+        case VEX_M_0F38: return "0F38";
+        case VEX_M_0F3A: return "0F3A";
+        default: return "??";
+    }
+}
+
+uintptr_t dynarec64_67_AVX(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed, vd;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_F2)) {
+        switch(opcode) {
+
+            case 0xF6:
+                INST_NAME("MULX Gd, Vd, Ed (,RDX)");
+                nextop = F8;
+                GETGD;
+                GETED32(0);
+                GETVD;
+                if(rex.w) {
+                    // 64bits mul
+                    UMULH(x3, xRDX, ed);
+                    MULx(vd, xRDX, ed);
+                    MOVx_REG(gd, x3);
+                } else {
+                    // 32bits mul
+                    UMULL(x3, xRDX, ed);
+                    MOVw_REG(vd, x3);
+                    LSRx(gd, x3, 32);
+                }
+                break;
+
+            default:
+                DEFAULT;
+        }
+        
+    }
+    else if((vex.m==VEX_M_0F) && (vex.p==VEX_P_66)) {
+        switch(opcode) {
+            case 0xD6:
+                INST_NAME("VMOVQ Ex, Gx");
+                nextop = F8;
+                GETG;
+                v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+                if(MODREG) {
+                    v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                    VMOV(v1, v0);
+                    YMM0((nextop&7)+(rex.b<<3));
+                } else {
+                    addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VSTR64_U12(v0, ed, fixedaddress);
+                }
+                break;
+
+            default:
+                DEFAULT;
+        }
+    }
+    else {DEFAULT;}
+
+    if((*ok==-1) && (box64_dynarec_log>=LOG_INFO || box64_dynarec_dump || box64_dynarec_missing==1)) {
+        dynarec_log(LOG_NONE, "Dynarec unimplemented AVX opcode size %d prefix %s map %s opcode %02X ", 128<<vex.l, avx_prefix_string(vex.p), avx_map_string(vex.m), opcode);
+    }
+    return addr;
+}
@@ -0,0 +1,78 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "../dynarec_helper.h"
+
+static const char* avx_prefix_string(uint16_t p)
+{
+    switch(p) {
+        case VEX_P_NONE: return "0";
+        case VEX_P_66: return "66";
+        case VEX_P_F2: return "F2";
+        case VEX_P_F3: return "F3";
+        default: return "??";
+    }
+}
+static const char* avx_map_string(uint16_t m)
+{
+    switch(m) {
+        case VEX_M_NONE: return "0";
+        case VEX_M_0F: return "0F";
+        case VEX_M_0F38: return "0F38";
+        case VEX_M_0F3A: return "0F3A";
+        default: return "??";
+    }
+}
+
+uintptr_t dynarec64_AVX(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = PK(0);
+    rex_t rex = vex.rex;
+
+    if( (vex.m==VEX_M_0F) && (vex.p==VEX_P_NONE))
+        addr = dynarec64_AVX_0F(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_NONE))
+        addr = dynarec64_AVX_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if( (vex.m==VEX_M_0F) && (vex.p==VEX_P_66))
+        addr = dynarec64_AVX_66_0F(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if( (vex.m==VEX_M_0F) && (vex.p==VEX_P_F2))
+        addr = dynarec64_AVX_F2_0F(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if( (vex.m==VEX_M_0F) && (vex.p==VEX_P_F3))
+        addr = dynarec64_AVX_F3_0F(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_66))
+        addr = dynarec64_AVX_66_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if( (vex.m==VEX_M_0F3A) && (vex.p==VEX_P_66))
+        addr = dynarec64_AVX_66_0F3A(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_F2))
+        addr = dynarec64_AVX_F2_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if( (vex.m==VEX_M_0F3A) && (vex.p==VEX_P_F2))
+        addr = dynarec64_AVX_F2_0F3A(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else if( (vex.m==VEX_M_0F38) && (vex.p==VEX_P_F3))
+        addr = dynarec64_AVX_F3_0F38(dyn, addr, ip, ninst, vex, ok, need_epilog);
+    else {DEFAULT;}
+
+    if((*ok==-1) && (box64_dynarec_log>=LOG_INFO || box64_dynarec_dump || box64_dynarec_missing==1)) {
+        dynarec_log(LOG_NONE, "Dynarec unimplemented AVX opcode size %d prefix %s map %s opcode %02X ", 128<<vex.l, avx_prefix_string(vex.p), avx_map_string(vex.m), opcode);
+    }
+    return addr;
+}
@@ -0,0 +1,712 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+#include "my_cpuid.h"
+#include "emu/x87emu_private.h"
+#include "emu/x64shaext.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+    #if STEP > 1
+    static const int8_t mask_shift8[] = { -7, -6, -5, -4, -3, -2, -1, 0 };
+    #endif
+
+    rex_t rex = vex.rex;
+
+    switch(opcode) {
+
+        case 0x10:
+            INST_NAME("VMOVUPS Gx,Ex");
+            nextop = F8;
+            GETG;
+            if(MODREG) {
+                ed = (nextop&7)+(rex.b<<3);
+                v1 = sse_get_reg(dyn, ninst, x1, ed, 0);
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                if(v0!=v1) VMOVQ(v0, v1);
+                if(vex.l) {
+                    v1 = ymm_get_reg(dyn, ninst, x1, ed, 0, gd, -1, -1);
+                    v0 = ymm_get_reg_empty(dyn, ninst, x1, gd, ed, -1, -1);
+                    if(v0!=v1) VMOVQ(v0, v1);
+                }
+            } else {
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0xffe<<4, 15, rex, NULL, 0, 0);
+                VLDR128_U12(v0, ed, fixedaddress);   // no alignment issue with ARMv8 NEON :)
+                if(vex.l) {
+                    v0 = ymm_get_reg_empty(dyn, ninst, x1, gd, -1, -1, -1);
+                    VLDR128_U12(v0, ed, fixedaddress+16);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x11:
+            INST_NAME("VMOVUPS Ex,Gx");
+            nextop = F8;
+            GETG;
+            v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+            if(MODREG) {
+                ed = (nextop&7)+(rex.b<<3);
+                v1 = sse_get_reg_empty(dyn, ninst, x1, ed);
+                VMOVQ(v1, v0);
+                if(vex.l) {
+                    v0 = ymm_get_reg(dyn, ninst, x1, gd, 0, ed, -1, -1);
+                    v1 = ymm_get_reg_empty(dyn, ninst, x1, ed, gd, -1, -1);
+                    VMOVQ(v1, v0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0xffe<<4, 15, rex, NULL, 0, 0);
+                VSTR128_U12(v0, ed, fixedaddress);
+                if(vex.l) {
+                    v0 = ymm_get_reg(dyn, ninst, x1, gd, 0, ed, -1, -1);
+                    VSTR128_U12(v0, ed, fixedaddress+16);
+                }
+                SMWRITE2();
+            }
+            break;
+        case 0x12:
+            nextop = F8;
+            GETVX(v2, 0);
+            if(MODREG) {
+                INST_NAME("VMOVHLPS Gx, Vx, Ex");
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                GETGX_empty(v0);
+                if((v0!=v2) && (v0!=v1))
+                    VMOVQ(v0, v2);
+                VMOVeD(v0, 0, v1, 1);
+                if((v0!=v2) && (v0==v1))
+                    VMOVeD(v0, 1, v2, 1);
+            } else {
+                INST_NAME("VMOVLPS Gx, Vx, Ex");
+                GETGX_empty(v0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                if(v0!=v2)
+                    VMOVQ(v0, v2);
+                VLD1_64(v0, 0, ed);
+            }
+            YMM0(gd);
+            break;
+        case 0x13:
+            nextop = F8;
+            INST_NAME("VMOVLPS Ex, Vx, Gx");
+            GETGX(v0, 0);
+            GETVX(v2, 0);
+            if(v1!=v2)
+                VMOVQ(v0, v2);
+            if(MODREG) {
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 1);
+                if(v0!=v1) VMOVeD(v1, 0, v0, 0);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                VST1_64(v0, 0, ed);  // better to use VST1 than VSTR_64, to avoid NEON->VFPU transfert I assume
+                SMWRITE2();
+            }
+            break;
+        case 0x14:
+            INST_NAME("VUNPCKLPS Gx, Vx, Ex");
+            nextop = F8;
+            SMREAD();
+            GETGX_empty_VXEX(v0, v2, v1, 0);
+            VZIP1Q_32(v0, v2, v1);
+            if(vex.l) {
+                GETGY_empty_VYEY(v0, v2, v1);
+                VZIP1Q_32(v0, v2, v1);
+            } else YMM0(gd);
+            break;
+        case 0x15:
+            INST_NAME("VUNPCKHPS Gx, Vx, Ex");
+            nextop = F8;
+            SMREAD();
+            GETGX_empty_VXEX(v0, v2, v1, 0);
+            VZIP2Q_32(v0, v2, v1);
+            if(vex.l) {
+                GETGY_empty_VYEY(v0, v2, v1);
+                VZIP2Q_32(v0, v2, v1);
+            } else YMM0(gd);
+            break;
+        case 0x16:
+            nextop = F8;
+            if(MODREG) {
+                INST_NAME("VMOVLHPS Gx, Vx, Ex");
+                GETGX(v0, 1);
+                GETVX(v2, 0);
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                if(v0!=v2 && v0!=v1) VMOVQ(v0, v2);
+                VMOVeD(v0, 1, v1, 0);
+                if(v0!=v2 && v0==v1) VMOVeD(v0, 0, v2, 0);
+            } else {
+                INST_NAME("VMOVHPS Gx, Vx, Ex");
+                SMREAD();
+                GETGX(v0, 1);
+                GETVX(v2, 0);
+                if(v0!=v2) VMOVQ(v0, v2);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                VLD1_64(v0, 1, ed);
+            }
+            YMM0(gd);
+            break;
+        case 0x17:
+            INST_NAME("VMOVHPS Ex,Gx");
+            nextop = F8;
+            GETGX(v0, 0);
+            if(MODREG) {
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 1);
+                VMOVeD(v1, 0, v0, 1);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                VST1_64(v0, 1, ed);
+            }
+            break;
+
+        case 0x28:
+            INST_NAME("VMOVAPS Gx, Ex");
+            nextop = F8;
+            GETG;
+            if(MODREG) {
+                ed = (nextop&7)+(rex.b<<3);
+                v1 = sse_get_reg(dyn, ninst, x1, ed, 0);
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                VMOVQ(v0, v1);
+                if(vex.l) {
+                    GETGY_empty_EY(v0, v1);
+                    VMOVQ(v0, v1);
+                }
+            } else {
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x3, &fixedaddress, NULL, 0xffe<<4, 15, rex, NULL, 0, 0);
+                VLDR128_U12(v0, ed, fixedaddress);
+                if(vex.l) {
+                    GETGY_empty(v0, -1, -1, -1);
+                    VLDR128_U12(v0, ed, fixedaddress+16);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x29:
+            INST_NAME("VMOVAPS Ex, Gx");
+            nextop = F8;
+            GETG;
+            v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+            if(MODREG) {
+                ed = (nextop&7)+(rex.b<<3);
+                v1 = sse_get_reg_empty(dyn, ninst, x1, ed);
+                VMOVQ(v1, v0);
+                if(vex.l) {
+                    GETGYEY_empty(v0, v1);
+                    VMOVQ(v1, v0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0xffe<<4, 15, rex, NULL, 0, 0);
+                VSTR128_U12(v0, ed, fixedaddress);
+                if(vex.l) {
+                    GETGY(v0, 0, -1, -1, -1);
+                    VSTR128_U12(v0, ed, fixedaddress+16);
+                }
+                SMWRITE2();
+            }
+            break;
+
+        case 0x2B:
+            INST_NAME("VMOVNTPS Ex, Gx");
+            nextop = F8;
+            GETG;
+            v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+            if(MODREG) {
+                ed = (nextop&7)+(rex.b<<3);
+                v1 = sse_get_reg_empty(dyn, ninst, x1, ed);
+                VMOVQ(v1, v0);
+                if(vex.l) {
+                    GETGYEY_empty(v0, v1);
+                    VMOVQ(v1, v0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0xffe<<4, 15, rex, NULL, 0, 0);
+                VSTR128_U12(v0, ed, fixedaddress);
+                if(vex.l) {
+                    GETGY(v0, 0, -1, -1, -1);
+                    VSTR128_U12(v0, ed, fixedaddress+16);
+                }
+            }
+            break;
+
+        case 0x2E:
+            // no special check...
+        case 0x2F:
+            if(opcode==0x2F) {INST_NAME("VCOMISS Gx, Ex");} else {INST_NAME("VUCOMISS Gx, Ex");}
+            SETFLAGS(X_ALL, SF_SET_NODF);
+            nextop = F8;
+            GETGX(v0, 0);
+            GETEXSS(s0, 0, 0);
+            FCMPS(v0, s0);
+            FCOMI(x1, x2, 0, v0, s0, 1);    //disable precise cmp
+            break;
+
+        case 0x50:
+            INST_NAME("VMOVMSPKPS Gd, Ex");
+            nextop = F8;
+            GETGD;
+            MOV32w(gd, 0);
+            if(MODREG) {
+                // EX is an xmm reg
+                q0 = fpu_get_scratch(dyn, ninst);
+                for(int l=0; l<1+vex.l; ++l) {
+                    if(!l) { GETEX(v0, 0, 0); } else { GETEY(v0); }
+                    SQXTN_16(q0, v0);   // reduces the 4 32bits to 4 16bits
+                    VMOVQDto(x1, q0, 0);
+                    LSRx(x1, x1, 15);
+                    BFIx(gd, x1, 0+(l*4), 1);
+                    LSRx(x1, x1, 16);
+                    BFIx(gd, x1, 1+(l*4), 1);
+                    LSRx(x1, x1, 16);
+                    BFIx(gd, x1, 2+(l*4), 1);
+                    LSRx(x1, x1, 16);
+                    BFIx(gd, x1, 3+(l*4), 1);
+                }
+            } else {
+                // EX is memory
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, NULL, (0xfff<<3)-24, 7, rex, NULL, 0, 0);
+                for(int l=0; l<1+vex.l; ++l) {
+                    LDRx_U12(x1, ed, fixedaddress+16*l);
+                    LSRx(x1, x1, 31);
+                    BFIx(gd, x1, 0+(l*4), 1);
+                    LSRx(x1, x1, 32);
+                    BFIx(gd, x1, 1+(l*4), 1);
+                    LDRx_U12(x1, ed, fixedaddress+8+16*l);
+                    LSRx(x1, x1, 31);
+                    BFIx(gd, x1, 2+(l*4), 1);
+                    LSRx(x1, x1, 32);
+                    BFIx(gd, x1, 3+(l*4), 1);
+                }
+            }
+            break;
+        case 0x51:
+            INST_NAME("VSQRTPS Gx, Ex");
+            nextop = F8;
+            SKIPTEST(x1);
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_EX(q0, q1, 0); } else { GETGY_empty_EY(q0, q1); }
+                VFSQRTQS(q0, q1);
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x52:
+            INST_NAME("VRSQRTPS Gx, Ex");
+            nextop = F8;
+            SKIPTEST(x1);
+            v0 = fpu_get_scratch(dyn, ninst);
+            VFMOVSQ_8(v0, 0b01110000);    //1.0f
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_EX(q0, q1, 0); } else { GETGY_empty_EY(q0, q1); }
+                #if 0
+                // the aproximation doesn't not work on Death Stranding. code around 0x1419c9100 fail...
+                if(!l) {
+                    if(q1==q0)
+                        v1 = fpu_get_scratch(dyn, ninst);
+                    else
+                        v1 = q1;
+                }
+                // more precise
+                VFRSQRTEQS(v0, q1);
+                VFMULQS(v1, v0, q1);
+                VFRSQRTSQS(v1, v1, v0);
+                VFMULQS(q0, v1, v0);
+                #else
+                VFSQRTQS(q0, q1);
+                VFDIVQS(q0, v0, q0);
+                #endif
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x53:
+            INST_NAME("VRCPPS Gx, Ex");
+            nextop = F8;
+            SKIPTEST(x1);
+            q0 = fpu_get_scratch(dyn, ninst);
+            VFMOVSQ_8(q0, 0b01110000);    //1.0f
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) {
+                    GETGX_empty_EX(v0, v1, 0);
+                    #if 0
+                    if(v0==v1)
+                        q1 = fpu_get_scratch(dyn, ninst);
+                    #endif
+                } else {
+                    GETGY_empty_EY(v0, v1);
+                }
+                #if 0
+                if(v0!=v1) q1 = v0;
+                VFRECPEQS(q0, v1);
+                VFRECPSQS(q1, q0, v1);
+                VFMULQS(v0, q0, q1);
+                #else
+                VFDIVQS(v0, q0, v1);
+                #endif
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x54:
+            INST_NAME("VANDPS Gx, Vx, Ex");
+            nextop = F8;
+            GETGX_empty_VXEX(v0, v2, v1, 0);
+            VANDQ(v0, v2, v1);
+            if(vex.l) {
+                GETGY_empty_VYEY(v0, v2, v1);
+                VANDQ(v0, v2, v1);
+            } else YMM0(gd)
+            break;
+        case 0x55:
+            INST_NAME("VANDNPS Gx, Vx, Ex");
+            nextop = F8;
+            GETGX_empty_VXEX(v0, v2, v1, 0);
+            VBICQ(v0, v1, v2);
+            if(vex.l) {
+                GETGY_empty_VYEY(v0, v2, v1);
+                VBICQ(v0, v1, v2);
+            } else YMM0(gd)
+            break;
+        case 0x56:
+            INST_NAME("VORPS Gx, Vx, Ex");
+            nextop = F8;
+            GETGX_empty_VXEX(v0, v2, v1, 0);
+            VORRQ(v0, v2, v1);
+            if(vex.l) {
+                GETGY_empty_VYEY(v0, v2, v1);
+                VORRQ(v0, v2, v1);
+            } else YMM0(gd)
+            break;
+        case 0x57:
+            INST_NAME("VXORPS Gx, Vx, Ex");
+            nextop = F8;
+            GETGX_empty_VXEX(v0, v2, v1, 0);
+            VEORQ(v0, v2, v1);
+            if(vex.l) {
+                GETGY_empty_VYEY(v0, v2, v1);
+                VEORQ(v0, v2, v1);
+            } else YMM0(gd)
+            break;
+        case 0x58:
+            INST_NAME("VADDPS Gx, Vx, Ex");
+            nextop = F8;
+            GETGX_empty_VXEX(v0, v2, v1, 0);
+            VFADDQS(v0, v2, v1);
+            if(vex.l) {
+                GETGY_empty_VYEY(v0, v2, v1);
+                VFADDQS(v0, v2, v1);
+            } else YMM0(gd)
+            break;
+        case 0x59:
+            INST_NAME("VMULPS Gx, Vx, Ex");
+            nextop = F8;
+            GETGX_empty_VXEX(v0, v2, v1, 0);
+            VFMULQS(v0, v2, v1);
+            if(vex.l) {
+                GETGY_empty_VYEY(v0, v2, v1);
+                VFMULQS(v0, v2, v1);
+            } else YMM0(gd)
+            break;
+        case 0x5A:
+            INST_NAME("VCVTPS2PD Gx, Ex");
+            nextop = F8;
+            GETGX_empty_EX(v0, v1, 0);
+            if(vex.l) {
+                GETGY_empty(q0, -1, -1, -1);
+                FCVTL2(q0, v1);
+            } else YMM0(gd)
+            FCVTL(v0, v1);
+            break;
+        case 0x5B:
+            INST_NAME("VCVTDQ2PS Gx, Ex");
+            nextop = F8;
+            GETGX_empty_EX(v0, v1, 0);
+            SCVTQFS(v0, v1);
+            if(vex.l) {
+                GETGY_empty_EY(v0, v1);
+                SCVTQFS(v0, v1);
+            } else YMM0(gd)
+            break;
+        case 0x5C:
+            INST_NAME("VSUBPS Gx, Vx, Ex");
+            nextop = F8;
+            GETGX_empty_VXEX(v0, v2, v1, 0);
+            VFSUBQS(v0, v2, v1);
+            if(vex.l) {
+                GETGY_empty_VYEY(v0, v2, v1);
+                VFSUBQS(v0, v2, v1);
+            } else YMM0(gd)
+            break;
+        case 0x5D:
+            INST_NAME("VMINPS Gx, Vx, Ex");
+            nextop = F8;
+            if(!box64_dynarec_fastnan) {
+                q0 = fpu_get_scratch(dyn, ninst);
+            }
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_VXEX(v0, v2, v1, 0); } else { GETGY_empty_VYEY(v0, v2, v1); }
+                // FMIN/FMAX wll not copy a NaN if either is NaN
+                // but x86 will copy src2 if either value is NaN, so lets force a copy of Src2 (Ex) if result is NaN
+                VFMINQS(v0, v2, v1);
+                if(!box64_dynarec_fastnan && (v2!=v1)) {
+                    VFCMEQQS(q0, v0, v0);   // 0 is NaN, 1 is not NaN, so MASK for NaN
+                    VBIFQ(v0, v1, q0);   // copy dest where source is NaN
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x5E:
+            INST_NAME("VDIVPS Gx, Vx, Ex");
+            nextop = F8;
+            GETGX_empty_VXEX(v0, v2, v1, 0);
+            VFDIVQS(v0, v2, v1);
+            if(vex.l) {
+                GETGY_empty_VYEY(v0, v2, v1);
+                VFDIVQS(v0, v2, v1);
+            } else YMM0(gd)
+            break;
+        case 0x5F:
+            INST_NAME("VMAXPS Gx, Vx, Ex");
+            nextop = F8;
+            if(!box64_dynarec_fastnan) {
+                q0 = fpu_get_scratch(dyn, ninst);
+            }
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_VXEX(v0, v2, v1, 0); } else { GETGY_empty_VYEY(v0, v2, v1); }
+                // FMIN/FMAX wll not copy a NaN if either is NaN
+                // but x86 will copy src2 if either value is NaN, so lets force a copy of Src2 (Ex) if result is NaN
+                VFMAXQS(v0, v2, v1);
+                if(!box64_dynarec_fastnan && (v2!=v1)) {
+                    VFCMEQQS(q0, v0, v0);   // 0 is NaN, 1 is not NaN, so MASK for NaN
+                    VBIFQ(v0, v1, q0);   // copy dest where source is NaN
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        case 0x77:
+            if(!vex.l) {
+                INST_NAME("VZEROUPPER");
+                if(vex.v!=0) {
+                    UDF(0);
+                } else {
+                    for(int i=0; i<(rex.is32bits?8:16); ++i) {
+                        YMM0(i);
+                    }
+                }
+            } else {
+                INST_NAME("VZEROALL");
+                if(vex.v!=0) {
+                    UDF(0);
+                } else {
+                    for(int i=0; i<(rex.is32bits?8:16); ++i) {
+                        v0 = sse_get_reg_empty(dyn, ninst, x1, i);
+                        VEORQ(v0, v0, v0);
+                        YMM0(i);
+                    }
+                }
+            }
+            break;
+
+        case 0xAE:
+            nextop = F8;
+            if(MODREG) {
+                DEFAULT;
+            } else
+                switch((nextop>>3)&7) {
+                    case 2:
+                        INST_NAME("VLDMXCSR Md");
+                        GETED(0);
+                        STRw_U12(ed, xEmu, offsetof(x64emu_t, mxcsr));
+                        if(box64_sse_flushto0) {
+                            MRS_fpcr(x1);                   // get fpscr
+                            LSRw_IMM(x3, ed, 15);           // get FZ bit
+                            BFIw(x1, x3, 24, 1);            // inject FZ bit
+                            EORw_REG_LSR(x3, x3, ed, 1);    // FZ xor DAZ
+                            BFIw(x1, x3, 1, 1);             // inject AH bit
+                            MSR_fpcr(x1);                   // put new fpscr
+                        }
+                        break;
+                    case 3:
+                        INST_NAME("VSTMXCSR Md");
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                        LDRw_U12(x4, xEmu, offsetof(x64emu_t, mxcsr));
+                        STW(x4, ed, fixedaddress);
+                        break;
+                    default:
+                        DEFAULT;
+                }
+            break;
+
+        case 0xC2:
+            INST_NAME("VCMPPS Gx, Vx, Ex, Ib");
+            nextop = F8;
+            q0 = fpu_get_scratch(dyn, ninst);
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_VXEX(v0, v2, v1, 1); u8 = F8; } else { GETGY_empty_VYEY(v0, v2, v1); }
+                if(((u8&15)==3) || ((u8&15)==7) || ((u8&15)==8) || ((u8&15)==9) || ((u8&15)==10) || ((u8&15)==12) || ((u8&15)==13) || ((u8&15)==14)) {
+                    VFMAXQS(q0, v2, v1);    // propagate NAN
+                    VFCMEQQS(((u8&15)==7)?v0:q0, q0, q0);   // 0 if NAN, 1 if not NAN
+                }
+                switch(u8&0xf) {
+                    // the inversion of the params in the comparison is there to handle NaN the same way SSE does
+                    case 0x00: VFCMEQQS(v0, v2, v1); break;   // Equal, not unordered
+                    case 0x01: VFCMGTQS(v0, v1, v2); break;   // Less than
+                    case 0x02: VFCMGEQS(v0, v1, v2); break;   // Less or equal
+                    case 0x03: VMVNQ(v0, q0); break;   // unordered
+                    case 0x04: VFCMEQQS(v0, v2, v1); VMVNQ(v0, v0); break;   // Not Equal (or unordered on ARM, not on X86...)
+                    case 0x05: VFCMGTQS(v0, v1, v2); VMVNQ(v0, v0); break;   // Greater or equal or unordered
+                    case 0x06: VFCMGEQS(v0, v1, v2); VMVNQ(v0, v0); break;   // Greater or unordered
+                    case 0x07: break;  // ordered
+                    case 0x08: VFCMEQQS(v0, v2, v1); VORNQ(v0, v0, q0); break;   // Equal, or unordered
+                    case 0x09: VFCMGTQS(v0, v1, v2); VORNQ(v0, v0, q0); break;   // Less than or unordered
+                    case 0x0a: VFCMGEQS(v0, v1, v2); VORNQ(v0, v0, q0); break;   // Less or equal or unordered
+                    case 0x0b: VEORQ(v0, v0, v0); break; // false
+                    case 0x0c: VFCMEQQS(v0, v2, v1); VBICQ(v0, q0, v0); break;
+                    case 0x0d: VFCMGEQS(v0, v2, v1); break;
+                    case 0x0e: VFCMGTQS(v0, v2, v1); break;
+                    case 0x0f: MOVIQ_64(v0, 0xff); break; //true
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        case 0xC6:
+            INST_NAME("VSHUFPS Gx, Vx, Ex, Ib");
+            nextop = F8;
+            GETVX(v2, 0);
+            if(!MODREG) {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x3, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 1);
+                v1 = -1; // to avoid a warning
+            } else
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+            GETGX_empty(v0);
+            u8 = F8;
+            if(v2==v1 && (u8&0x3)==((u8>>2)&3) && (u8&0xf)==((u8>>4)&0xf)) {
+                VDUPQ_32(v0, v2, u8&3);
+            } else if(v2==v1 && (u8==0xe0)) {   // easy special case
+                VMOVQ(v0, v2);
+                VMOVeS(v0, 1, v0, 0);
+            } else if(v2==v1 && (u8==0xe5)) {   // easy special case
+                VMOVQ(v0, v2);
+                VMOVeS(v0, 0, v0, 1);
+            } else if(MODREG && u8==0x88) {
+                VUZP1Q_32(v0, v2, v1);
+            } else if(MODREG && u8==0xdd) {
+                VUZP2Q_32(v0, v2, v1);
+            } else {
+                if((v0==v1) || (v0==v2)) {
+                    d0 = fpu_get_scratch(dyn, ninst); s0 = 0;
+                } else {
+                    d0 = v0; s0 = 1;
+                }
+                // first two elements from Vx
+                for(int i=0; i<2; ++i) {
+                    VMOVeS(d0, i, v2, (u8>>(i*2))&3);
+                }
+                // second two from Ex
+                if(MODREG) {
+                    for(int i=2; i<4; ++i) {
+                        VMOVeS(d0, i, v1, (u8>>(i*2))&3);
+                    }
+                } else {
+                    SMREAD();
+                    for(int i=2; i<4; ++i) {
+                        ADDx_U12(x2, ed, ((u8>>(i*2))&3)*4);
+                        VLD1_32(d0, i, x2);
+                    }
+                }
+                if(v0!=d0) VMOVQ(v0, d0);
+            }
+            if(vex.l) {
+                if(MODREG)
+                    v1 = ymm_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0, gd, vex.v, -1);
+                GETGY_empty_VY(v0, v2, 0, (MODREG)?((nextop&7)+(rex.b<<3)):-1, -1);
+                if(v2==v1 && (u8&0x3)==((u8>>2)&3) && (u8&0xf)==((u8>>4)&0xf)) {
+                    VDUPQ_32(v0, v2, u8&3);
+                } else if(v2==v1 && (u8==0xe0)) {
+                    VMOVQ(v0, v2);
+                    VMOVeS(v0, 1, v0, 0);
+                } else if(v2==v1 && (u8==0xe5)) {
+                    VMOVQ(v0, v2);
+                    VMOVeS(v0, 0, v0, 1);
+                } else if(MODREG && u8==0x88) {
+                    VUZP1Q_32(v0, v2, v1);
+                } else if(MODREG && u8==0xdd) {
+                    VUZP2Q_32(v0, v2, v1);
+                } else {
+                    if(s0) d0 = v0;
+                    for(int i=0; i<2; ++i) {
+                        VMOVeS(d0, i, v2, (u8>>(i*2))&3);
+                    }
+                    if(MODREG) {
+                        for(int i=2; i<4; ++i) {
+                            VMOVeS(d0, i, v1, (u8>>(i*2))&3);
+                        }
+                    } else {
+                        SMREAD();
+                        for(int i=2; i<4; ++i) {
+                            ADDx_U12(x2, ed, 16+((u8>>(i*2))&3)*4);
+                            VLD1_32(d0, i, x2);
+                        }
+                    }
+                    VMOVQ(v0, d0);
+                }
+            } else YMM0(gd);
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
@@ -0,0 +1,161 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+#include "my_cpuid.h"
+#include "emu/x87emu_private.h"
+#include "emu/x64shaext.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_0F38(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed, vd;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    switch(opcode) {
+
+        case 0xF2:
+            INST_NAME("ANDN Gd, Vd, Ed");
+            nextop = F8;
+            SETFLAGS(X_ALL, SF_SET);
+            GETGD;
+            GETED(0);
+            GETVD;
+            IFX(X_ZF)
+                BICSxw(gd, ed, vd);
+            else
+                BICxw(gd, ed, vd);
+            IFX(X_ZF) {
+                CSETw(x1, cEQ);
+                BFIw(xFlags, x1, F_ZF, 1);
+            }
+            IFX(X_OF)
+                BFCw(xFlags, F_OF, 1);
+            IFX(X_CF)
+                BFCw(xFlags, F_CF, 1);
+            IFX(X_SF) {
+                LSRxw_IMM(x1, gd, rex.w?63:31);
+                BFIw(xFlags, x1, F_SF, 1);
+            }
+            break;
+        case 0xF3:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 1:
+                    INST_NAME("BLSR Vd, Ed");
+                    SETFLAGS(X_ALL, SF_SET);
+                    GETED(0);
+                    GETVD;
+                    IFX(X_CF) {
+                        TSTxw_REG(ed, ed);
+                        CSETMw(x3, cEQ);
+                        BFIw(xFlags, x3, F_CF, 1);
+                    }
+                    SUBxw_U12(x3, ed, 1);
+                    IFX(X_ZF)
+                        ANDSxw_REG(vd, ed, x3);
+                    else
+                        ANDxw_REG(vd, ed, x3);
+                    IFX(X_ZF) {
+                        CSETMw(x3, cEQ);
+                        BFIw(xFlags, x3, F_ZF, 1);
+                    }
+                    IFX(X_SF) {
+                        LSRxw(x3, vd, rex.w?63:31);
+                        BFIw(xFlags, x3, F_SF, 1);
+                    }
+                    IFX(X_OF) BFCw(xFlags, F_OF, 1);
+                    if(box64_dynarec_test) {
+                        IFX(X_AF) BFCw(xFlags, F_AF, 1);
+                        IFX(X_PF) BFCw(xFlags, F_PF, 1);
+                    }
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+
+        case 0xF5:
+            INST_NAME("BZHI Gd, Ed, Vd");
+            nextop = F8;
+            SETFLAGS(X_ALL, SF_SET);
+            GETGD;
+            GETED(0);
+            GETVD;
+            UXTBw(x1, vd);
+            CMPSw_U12(x1, rex.w?64:32);
+            CSETxw(x2, cPL);
+            IFX(F_CF) {
+                BFIw(xFlags, x2, F_CF, 1);
+            }
+            MVNxw_REG(x2, x2); //prepare mask
+            B_MARK(cPL);
+            LSLxw_REG(x2, x2, x1);
+            MARK;
+            IFX(X_ZF) {
+                BICSxw(gd, ed, x2);
+                CSETw(x3, cEQ);
+                BFIw(xFlags, x3, F_ZF, 1);
+            } else
+                BICxw(gd, ed, x2);
+            IFX(X_SF) {
+                LSRxw(x3, gd, rex.w?63:31);
+                BFIw(xFlags, x3, F_SF, 1);
+            }
+            IFX(X_AF) BFCw(xFlags, F_AF, 1);
+            IFX(X_PF) BFCw(xFlags, F_PF, 1);
+            IFX(X_OF) BFCw(xFlags, F_OF, 1);
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
@@ -0,0 +1,777 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+#include "my_cpuid.h"
+#include "emu/x87emu_private.h"
+#include "emu/x64shaext.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_66_0F3A(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+    #if STEP > 1
+    static const int8_t round_round[] = { 0, 2, 1, 3};
+    #endif
+
+    rex_t rex = vex.rex;
+
+    switch(opcode) {
+        case 0x00:
+        case 0x01:
+            if(opcode) {INST_NAME("VPERMPD Gx, Ex, Imm8");} else {INST_NAME("VPERMQ Gx, Ex, Imm8");}
+            nextop = F8;
+            GETGX_empty_EX(v0, q0, 1);
+            u8 = F8;
+            if(v0==q0) d0 = fpu_get_scratch(dyn, ninst);
+            if(v0==q0 || !MODREG) d1 = fpu_get_scratch(dyn, ninst);
+            q1 = d1;
+            GETGY_empty_EY(v1, q1);
+            if(v0==q0) { VMOVQ(d0, q0); VMOVQ(d1, q1); } else {d1 = q1; d0 = q0;}
+            VMOVeD(v0, 0, ((u8>>1)&1)?d1:d0, (u8>>0)&1);
+            VMOVeD(v0, 1, ((u8>>3)&1)?d1:d0, (u8>>2)&1);
+            VMOVeD(v1, 0, ((u8>>5)&1)?d1:d0, (u8>>4)&1);
+            VMOVeD(v1, 1, ((u8>>7)&1)?d1:d0, (u8>>6)&1);
+            break;
+        case 0x02:
+            INST_NAME("VPBLENDD Gx, Vx, Ex, u8");
+            nextop = F8;
+            q0 = fpu_get_scratch(dyn, ninst);
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_VXEX(v0, v2, v1, 1); u8 = F8;} else { GETGY_empty_VYEY(v0, v2, v1); u8 >>=4;}
+                wb1 = 0; // mask
+                for(int i=0; i<4; ++i)
+                    if(u8&(1<<i))
+                        wb1 |= (3<<(i*2));
+                MOVI_64(q0, wb1);   // load 8bits value as a 8bytes mask
+                SXTL_16(q0, q0);    // expand 16bits to 32bits...
+                if(v0==v1) {
+                    VBIFQ(v0, v2, q0);
+                } else {
+                    if(v0!=v2) VMOVQ(v0, v2);
+                    VBITQ(v0, v1, q0);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        case 0x04:
+            INST_NAME("VPERMILPS Gx, Ex, Imm8");
+            nextop = F8;
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) {
+                    GETGX_empty_EX(v0, v1, 1);
+                    u8 = F8;
+                    if(v0==v1) {q1 = fpu_get_scratch(dyn, ninst); VMOVQ(q1, v1);}
+                } else {
+                    GETGY_empty_EY(v0, v1);
+                    if(v0==v1) {VMOVQ(q1, v1);}
+                }
+                if(u8==0x00 || u8==0x55 || u8==0xAA || u8==0xFF)
+                    VDUPQ_32(v0, (v0==v1)?q1:v1, u8&3);
+                else if(u8==0x50)
+                    VZIP1Q_32(v0, v1, v1);
+                else if(u8==0xFA)
+                    VZIP2Q_32(v0, v1, v1);
+                else if(u8==0xA0)
+                    VTRNQ1_32(v0, v1, v1);
+                else if(u8==0xF5)
+                    VTRNQ2_32(v0, v1, v1);
+                else for(int i=0; i<4; ++i)
+                    VMOVeS(v0, i, (v0==v1)?q1:v1, (u8>>(i*2))&3);
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x05:
+            INST_NAME("VPERMILD Gx, Ex, Imm8");
+            nextop = F8;
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) {
+                    GETGX_empty_EX(v0, v1, 1);
+                    u8 = F8;
+                    if(v0==v1) {q1 = fpu_get_scratch(dyn, ninst); VMOVQ(q1, v1);}
+                } else {
+                    GETGY_empty_EY(v0, v1);
+                    if(v0==v1) {VMOVQ(q1, v1);}
+                }
+                if(((u8>>(l*2))&1)==((u8>>(1+l*2))&1))
+                    VDUPQ_64(v0, (v0==v1)?q1:v1, ((u8>>(l*2))&1));
+                else for(int i=0; i<2; ++i)
+                    VMOVeD(v0, i, (v0==v1)?q1:v1, (u8>>(i+l*2))&1);
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x06:
+        case 0x46:
+            if(opcode==0x06) { INST_NAME("VPERM2F128 Gx, Vx, Ex, Imm8"); } else { INST_NAME("VPERM2I128 Gx, Vx, Ex, Imm8"); }
+            nextop = F8;
+            if(!vex.l) UDF(0);
+            if(MODREG) {
+                s0 = (nextop&7)+(rex.b<<3);
+                v1 = sse_get_reg(dyn, ninst, x1, s0, 0);
+            } else {
+                s0 = -1;
+                v1 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x3, &fixedaddress, NULL, 0xffe<<4, 15, rex, NULL, 0, 0);
+            }
+            u8 = F8;
+            GETVX(v2, 0);
+            GETGX_empty(v0);
+            if((v0==v2) && ((u8&0xf0)==0)) {
+                q0 = fpu_get_scratch(dyn, ninst);
+                VMOVQ(q0, v2);
+                v2 = q0;
+            }
+            if((v0==v1) && ((u8&0xf0)==0x20)) {
+                q1 = fpu_get_scratch(dyn, ninst);
+                VMOVQ(q1, v1);
+                v1 = q1;
+            }
+            switch(u8&0x0f) {
+                case 0: if(v0!=v2) VMOVQ(v0, v2); break;
+                case 1: d2 = ymm_get_reg(dyn, ninst, x1, vex.v, 0, gd, s0, -1); VMOVQ(v0, d2); break;
+                case 2: if(MODREG) { if(v0!=v1) VMOVQ(v0, v1); } else { VLDR128_U12(v0, ed, fixedaddress); } break;
+                case 3: if(MODREG) { d1 = ymm_get_reg(dyn, ninst, x1, s0, 0, gd, vex.v, -1); VMOVQ(v0, d1); } else { VLDR128_U12(v0, ed, fixedaddress+16); } break;
+                default: VEORQ(v0, v0, v0);
+            }
+            if((u8&0xf0)==0x10) { if((u8&0x0f)!=1) d2 = ymm_get_reg(dyn, ninst, x1, vex.v, 0, gd, s0, -1); }
+            if(MODREG && ((u8&0xf0)==0x30)) { if((u8&0x0f)!=3) d1 = ymm_get_reg(dyn, ninst, x1, s0, 0, gd, vex.v, -1); }
+            v0 = ymm_get_reg_empty(dyn, ninst, x1, gd, vex.v, s0, -1);
+            switch((u8>>4)&0x0f) {
+                case 0: VMOVQ(v0, v2); break;
+                case 1: if(v0!=d2) VMOVQ(v0, d2); break;
+                case 2: if(MODREG) { if(v0!=v1) VMOVQ(v0, v1); } else { VLDR128_U12(v0, ed, fixedaddress); } break;
+                case 3: if(MODREG) { if(v0!=d1) VMOVQ(v0, d1); } else { VLDR128_U12(v0, ed, fixedaddress+16); } break;
+                default: VEORQ(v0, v0, v0);
+            }
+            break;
+
+        case 0x08:
+            INST_NAME("VROUNDPS Gx, Ex, Ib");
+            nextop = F8;
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_EX(v0, v1, 1); u8 = F8; } else { GETGY_empty_EY(v0, v1); }
+                if(u8&4) {
+                    if(!l) wb1 = sse_setround(dyn, ninst, x1, x2, x4);
+                    VFRINTISQ(v0, v1);
+                    if(l || !vex.l) x87_restoreround(dyn, ninst, wb1);
+                } else {
+                    VFRINTRSQ(v0, v1, round_round[u8&3]);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x09:
+            INST_NAME("VROUNDPD Gx, Ex, Ib");
+            nextop = F8;
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_EX(v0, v1, 1); u8 = F8; } else { GETGY_empty_EY(v0, v1); }
+                if(u8&4) {
+                    if(!l) wb1 = sse_setround(dyn, ninst, x1, x2, x4);
+                    VFRINTIDQ(v0, v1);
+                    if(l || !vex.l) x87_restoreround(dyn, ninst, wb1);
+                } else {
+                    VFRINTRDQ(v0, v1, round_round[u8&3]);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x0A:
+            INST_NAME("VROUNDSS Gx, Vx, Ex, Ib");
+            nextop = F8;
+            GETEXSS(v1, 0, 1);
+            GETGX_empty_VX(v0, v2);
+            u8 = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            if(u8&4) {
+                u8 = sse_setround(dyn, ninst, x1, x2, x3);
+                FRINTXS(d1, v1);
+                x87_restoreround(dyn, ninst, u8);
+            } else {
+                FRINTRRS(d1, v1, round_round[u8&3]);
+            }
+            if(v0!=v2) VMOVQ(v0, v2);
+            VMOVeS(v0, 0, d1, 0);
+            YMM0(gd);
+            break;
+        case 0x0B:
+            INST_NAME("VROUNDSD Gx, Vx, Ex, Ib");
+            nextop = F8;
+            GETEXSD(v1, 0, 1);
+            GETGX_empty_VX(v0, v2);
+            u8 = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            if(u8&4) {
+                u8 = sse_setround(dyn, ninst, x1, x2, x3);
+                FRINTXD(d1, v1);
+                x87_restoreround(dyn, ninst, u8);
+            } else {
+                FRINTRRD(d1, v1, round_round[u8&3]);
+            }
+            if(v0!=v2) VMOVQ(v0, v2);
+            VMOVeD(v0, 0, d1, 0);
+            YMM0(gd);
+            break;
+        case 0x0C:
+            INST_NAME("VBLENDPS Gx, Vx, Ex, Ib");
+            nextop = F8;
+            GETGX_empty_VXEX(q0, q2, q1, 1);
+            u8 = F8;
+            if((u8&0xf)==0xf) {
+                if(q0!=q1) VMOVQ(q0, q1);
+            } else if(q0==q1) {
+                for(int i=0; i<4; ++i)
+                    if(u8&(1<<i)) {
+                        VMOVeS(q0, i, q1, i);
+                    } else if(q0!=q2)
+                        VMOVeS(q0, i, q2, i);
+            } else {
+                if(q0!=q2)
+                    VMOVQ(q0, q2);
+                if((u8&15)==0b0011) {
+                    VMOVeD(q0, 0, q1, 0);
+                } else if((u8&15)==0b1100) {
+                    VMOVeD(q0, 1, q1, 1);
+                } else for(int i=0; i<4; ++i)
+                    if(u8&(1<<i)) {
+                        VMOVeS(q0, i, q1, i);
+                    }
+            }
+            if(vex.l) {
+                GETGY_empty_VYEY(q0, q2, q1);
+                if((u8&0xf0)==0xf0) {
+                    if(q0!=q1) VMOVQ(q0, q1);
+                } else if(q0==q1) {
+                    for(int i=0; i<4; ++i)
+                        if(u8&(1<<(i+4))) {
+                            VMOVeS(q0, i, q1, i);
+                        } else if(q0!=q2)
+                            VMOVeS(q0, i, q2, i);
+                } else {
+                    if(q0!=q2)
+                        VMOVQ(q0, q2);
+                    if((u8>>4)==0b0011) {
+                        VMOVeD(q0, 0, q1, 0);
+                    } else if((u8>>4)==0b1100) {
+                        VMOVeD(q0, 1, q1, 1);
+                    } else for(int i=0; i<4; ++i)
+                        if(u8&(1<<(i+4))) {
+                            VMOVeS(q0, i, q1, i);
+                        }
+                }
+            } else YMM0(gd);
+            break;
+        case 0x0D:
+            INST_NAME("VPBLENDPD Gx, Vx, Ex, Ib");
+            nextop = F8;
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_VXEX(q0, q2, q1, 1); u8 = F8; } else { GETGY_empty_VYEY(q0, q2, q1); }
+                switch(u8>>(l*2)&3) {
+                    case 0b00: if(q0!=q2) VMOVQ(q0, q2); break;    //  VxVx
+                    case 0b01: if(q0!=q1) VMOVeD(q0, 0, q1, 0); if(q0!=q2) VMOVeD(q0, 1, q2, 1); break; // Ex[0]Vx[1]
+                    case 0b10: if(q0!=q2) VMOVeD(q0, 0, q2, 0); if(q0!=q1) VMOVeD(q0, 1, q1, 1); break; // Vx[0]Ex[1]
+                    case 0b11: if(q0!=q1) VMOVQ(q0, q1); break;    //  ExEx
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x0E:
+            INST_NAME("VPBLENDW Gx, Vx, Ex, u8");
+            nextop = F8;
+            q0 = fpu_get_scratch(dyn, ninst);
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_VXEX(v0, v2, v1, 1); u8 = F8;} else { GETGY_empty_VYEY(v0, v2, v1); }
+                if(!l) {
+                    MOVI_64(q0, u8);
+                    SXTL_8(q0, q0);    // expand 8bits to 16bits...
+                }
+                if(v0==v1) {
+                    VBIFQ(v0, v2, q0);
+                } else {
+                    if(v0!=v2) VMOVQ(v0, v2);
+                    VBITQ(v0, v1, q0);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x0F:
+            INST_NAME("VPALIGNR Gx, Vx, Ex, Ib");
+            nextop = F8;
+            d0 = fpu_get_scratch(dyn, ninst);
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) {
+                    GETGX_empty_VXEX(v0, v2, v1, 1);
+                    u8 = F8;
+                } else {
+                    GETGY_empty_VYEY(v0, v2, v1);
+                }
+                if(u8>31) {
+                    VEORQ(v0, v0, v0);
+                } else if(u8>15) {
+                    if(!l) VEORQ(d0, d0, d0);
+                    VEXTQ_8(v0, v2, d0, u8-16);
+                } else {
+                    VEXTQ_8(v0, v1, v2, u8);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        case 0x14:
+            INST_NAME("VPEXTRB Ed, Gx, imm8");
+            nextop = F8;
+            GETGX(v0, 0);
+            if(MODREG) {
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+            } else {
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff, 0, rex, NULL, 0, 1);
+                ed = x1;
+            }
+            u8 = F8;
+            VMOVBto(ed, v0, u8&0x0f);
+            if(!MODREG) {
+                STB(ed, wback, fixedaddress);
+            }
+            break;
+        case 0x15:
+            INST_NAME("VPEXTRW Ed, Gx, imm8");
+            nextop = F8;
+            GETGX(v0, 0);
+            if(MODREG) {
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+            } else {
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 1);
+                ed = x1;
+            }
+            u8 = F8;
+            VMOVHto(ed, v0, u8&7);
+            if(!MODREG) {
+                STH(ed, wback, fixedaddress);
+            }
+            break;
+        case 0x16:
+            INST_NAME("VPEXTRD/Q Ed, Gx, imm8");
+            nextop = F8;
+            GETGX(v0, 0);
+            if(MODREG) {
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+            } else {
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, NULL, 0, 1);
+                ed = x1;
+            }
+            u8 = F8;
+            if(rex.w) {
+                VMOVQDto(ed, v0, u8&1);
+            } else {
+                VMOVSto(ed, v0, u8&3);
+            }
+            if(!MODREG) {
+                STxw(ed, wback, fixedaddress);
+            }
+            break;
+        case 0x17:
+            INST_NAME("VEXTRACTPS Ed, Gx, imm8");
+            nextop = F8;
+            GETGX(v0, 0);
+            if(MODREG) {
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+            } else {
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 1);
+                ed = x1;
+            }
+            u8 = F8;
+            VMOVSto(ed, v0, u8&3);
+            if(!MODREG) {
+                STW(ed, wback, fixedaddress);
+            }
+            break;
+        case 0x18:
+        case 0x38:
+            if(opcode==0x18) {INST_NAME("VINSERTF128 Gx, Vx, Ex, imm8");} else {INST_NAME("VINSERTI128 Gx, Vx, Ex, imm8");}
+            nextop = F8;
+            if(MODREG) {
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x3, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 1);
+                v1 = -1; // to avoid a warning
+            }
+            u8 = F8;
+            GETVX(v2, 0);
+            GETGX_empty(v0);
+            if(v0==v2 && u8==1) {
+                GETGY_empty(q0, 0, (MODREG)?((nextop&7)+(rex.b<<3)):-1, -1);
+                q2 = q0;
+            } else {
+                GETGY_empty_VY(q0, q2, 0, (MODREG)?((nextop&7)+(rex.b<<3)):-1, -1);
+            }
+            if(MODREG)
+                VMOVQ((u8&1)?q0:v0, v1);
+            else
+                VLD128((u8&1)?q0:v0, ed, fixedaddress);
+            if(v0!=v2)
+                VMOVQ((u8&1)?v0:q0, (u8&1)?v2:q2);
+            break;
+        case 0x19:
+        case 0x39:
+            if(opcode==0x19) {INST_NAME("VEXTRACTF128 Ex, Gx, imm8");} else {INST_NAME("VEXTRACTI128 Ex, Gx, imm8");}
+            nextop = F8;
+            u8 = geted_ib(dyn, addr, ninst, nextop);
+            GETGX(v0, 0);
+            if(u8&1) {GETGY(v0, ((nextop&7)+(rex.b<<3)==gd && MODREG)?1:0, -1, -1, -1);}
+            if(MODREG) {
+                v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                VMOVQ(v1, v0);
+                if((nextop&7)+(rex.b<<3)==gd && (u8&1))
+                    VEORQ(v0, v0, v0);  // special case like vextractf128 xmm3, ymm3, 0x01
+                else
+                    YMM0((nextop&7)+(rex.b<<3));
+                
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x3, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 1);
+                VST128(v0, ed, fixedaddress);
+            }
+            F8; // read u8, but it's been already handled
+            break;
+
+        case 0x1D:
+            INST_NAME("VCVTPS2PH Ex, Gx");
+            nextop = F8;
+            GETGX(v0, 0);
+            if(MODREG) {
+                v1 = sse_get_reg_empty(dyn, ninst, x3, (nextop&7)+(rex.b<<3));
+            } else {
+                v1 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x3, &fixedaddress, &unscaled, 0xfff<<(3+vex.l), vex.l?15:7, rex, NULL, 0, 1);
+            }
+            if(vex.l && v0==v1) {
+                q0 = fpu_get_scratch(dyn, ninst);
+                VMOVQ(q0, v0);
+                v0 = q0;
+            }
+            u8 = F8;
+            if(u8&4) {
+                s0 = sse_setround(dyn, ninst, x1, x2, x6);
+            } else {
+                u8&=3;
+                if(u8==1) u8=2;
+                else if(u8==2) u8=1;
+                MRS_fpcr(x1);               // get fpscr
+                MOV32w(x2, u8);
+                MOVx_REG(x6, x1);
+                BFIx(x1, x2, 22, 2);     // inject new round
+                MSR_fpcr(x1);               // put new fpscr
+                s0 = x6;
+            }
+            FCVTN16(v1, v0);
+            if(vex.l) {
+                GETGY(v0, 0, MODREG?((nextop&7)+(rex.b<<3)):-1, -1,-1);
+                FCVTN162(v1, v0);
+            }
+            x87_restoreround(dyn, ninst, s0);
+            if(MODREG) {
+                YMM0((nextop&7)+(rex.b<<3));
+            } else {
+                if(vex.l) {
+                    VST128(v1, ed, fixedaddress);
+                } else {
+                    VST64(v1, ed, fixedaddress);
+                }
+                SMWRITE2();
+            }
+            break;
+
+        case 0x20:
+            INST_NAME("VINSERTD Gx, Vx, Ex, Ib");
+            nextop = F8;
+            GETGX_empty_VX(v0, v2);
+            GETED(1);
+            u8 = F8;
+            if(v0!=v2) VMOVQ(v0, v2);
+            VMOVQBfrom(v0, u8&0xf, ed);
+            YMM0(gd);
+            break;
+        case 0x21:
+            INST_NAME("VINSERTPS Gx, Vx, Ex, Ib");
+            nextop = F8;
+            if (MODREG) {
+                GETGX_empty_VXEX(v0, v2, v1, 1);
+                u8 = F8;
+                if(v0==v1) {
+                    d0 = fpu_get_scratch(dyn, ninst);
+                    VMOVQ(d0, v1);
+                    if(v0!=v2) VMOVQ(v0, v2);
+                    VMOVeS(v0, (u8>>4)&3, d0, (u8>>6)&3);
+                } else {
+                    if(v0!=v2) VMOVQ(v0, v2);
+                    VMOVeS(v0, (u8>>4)&3, v1, (u8>>6)&3);
+                }
+            } else {
+                GETGX_empty_VX(v0, v2);
+                if(v0!=v2) VMOVQ(v0, v2);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 1);
+                u8 = F8;
+                LDW(x2, wback, fixedaddress);
+                VMOVQSfrom(v0, (u8>>4)&3, x2);
+            }
+            uint8_t zmask = u8 & 0xf;
+            for (uint8_t i=0; i<4; i++) {
+                if (zmask & (1<<i)) {
+                    VMOVQSfrom(v0, i, wZR);
+                }
+            }
+            YMM0(gd);
+            break;
+        case 0x22:
+            INST_NAME("VINSERTD Gx, Vx, Ex, Ib");
+            nextop = F8;
+            GETGX_empty_VX(v0, v2);
+            GETED(1);
+            u8 = F8;
+            if(v0!=v2) VMOVQ(v0, v2);
+            if(rex.w)
+                VMOVQDfrom(v0, u8&1, ed);
+            else
+                VMOVQSfrom(v0, u8&3, ed);
+            YMM0(gd);
+            break;
+
+        case 0x40:
+            INST_NAME("VDPPS Gx, Vx, Ex, Ib");
+            nextop = F8;
+            u8 = geted_ib(dyn, addr, ninst, nextop);
+            q0 = fpu_get_scratch(dyn, ninst);
+            // first mask
+            wb1 = 0; // mask
+            for(int i=0; i<4; ++i)
+                if(u8&(1<<i))
+                    wb1 |= (3<<(i*2));
+            MOVI_64(q0, wb1);   // load 8bits value as a 8bytes mask
+            SXTL_16(q0, q0);    // expand 16bits to 32bits...
+            q1 = fpu_get_scratch(dyn, ninst);
+            // second mask
+            wb1 = 0; // mask
+            for(int i=0; i<4; ++i)
+                if((u8>>4)&(1<<i))
+                    wb1 |= (3<<(i*2));
+            MOVI_64(q1, wb1);   // load 8bits value as a 8bytes mask
+            SXTL_16(q1, q1);    // expand 16bits to 32bits...
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_VXEX(v0, v2, v1, 1); u8 = F8; } else { GETGY_empty_VYEY(v0, v2, v1); }
+                VFMULQS(v0, v2, v1);
+                VANDQ(v0, v0, q1);  // second mask
+                VFADDPQS(v0, v0, v0);
+                FADDPS(v0, v0);
+                VDUPQ_32(v0, v0, 0);
+                VANDQ(v0, v0, q0);  // first mask
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        case 0x44:
+            INST_NAME("PCLMULQDQ Gx, Vx, Ex, Ib");
+            nextop = F8;
+            if(arm64_pmull) {
+                d0 = fpu_get_scratch(dyn, ninst);
+                for(int l=0; l<1+vex.l; ++l) {
+                    if(!l) {
+                        GETGX_empty_VXEX(v0, v2, v1, 1);
+                        u8 = F8;
+                    } else {
+                        GETGY_empty_VYEY(v0, v2, v1);
+                    }
+                    switch (u8&0b00010001) {
+                        case 0b00000000:
+                            PMULL_128(v0, v2, v1);
+                            break;
+                        case 0b00010001:
+                            PMULL2_128(v0, v2, v1);
+                            break;
+                        case 0b00000001:
+                            VEXTQ_8(d0, v2, v2, 8); // Swap Up/Lower 64bits parts
+                            PMULL_128(v0, d0, v1);
+                            break;
+                        case 0b00010000:
+                            VEXTQ_8(d0, v2, v2, 8); // Swap Up/Lower 64bits parts
+                            PMULL2_128(v0, d0, v1);
+                            break;
+                    }
+                }
+            } else {
+                for(int l=0; l<1+vex.l; ++l) {
+                    if(!l) {
+                        GETG;
+                        sse_forget_reg(dyn, ninst, gd);
+                        sse_reflect_reg(dyn, ninst, vex.v);
+                    }
+                    MOV32w(x1, gd); // gx
+                    MOV32w(x2, vex.v); // vx
+                    if(MODREG) {
+                        if(!l) {
+                            ed = (nextop&7)+(rex.b<<3);
+                            sse_forget_reg(dyn, ninst, ed);
+                        }
+                        MOV32w(x3, ed);
+                    } else {
+                        if(!l) {
+                            addr = geted(dyn, addr, ninst, nextop, &ed, x3, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 1);
+                            if(ed!=x3) {
+                                MOVx_REG(x3, ed);
+                            }
+                        } else {
+                            ADDx_U12(x3, ed, 16);
+                        }
+                    }
+                    if(!l) u8 = F8;
+                    MOV32w(x4, u8);
+                    CALL_(l?native_pclmul_y:native_pclmul_x, -1, x3);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        //case 0x46:    // see 0x06
+
+        case 0x4A:
+            INST_NAME("VBLENDVPS Gx, Vx, Ex, XMMImm8");
+            nextop = F8;
+            q0 = fpu_get_scratch(dyn, ninst);
+            u8 = geted_ib(dyn, addr, ninst, nextop)>>4;
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { 
+                    q1 = sse_get_reg(dyn, ninst, x1, u8, 0);
+                    GETGX_empty_VXEX(v0, v2, v1, 1); 
+                    F8;
+                } else { 
+                    v2 = ymm_get_reg(dyn, ninst, x1, vex.v, 0, gd, u8, (MODREG)?((nextop&7)+(rex.b<<3)):-1);
+                    if(MODREG)
+                        v1 = ymm_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0, gd, vex.v, u8);
+                    else
+                        VLDR128_U12(v1, ed, fixedaddress+16);
+                    q1 = ymm_get_reg(dyn, ninst, x1, u8, 0, vex.v, gd, (MODREG)?((nextop&7)+(rex.b<<3)):-1);
+                    v0 = ymm_get_reg_empty(dyn, ninst, x1, gd, vex.v, u8, (MODREG)?((nextop&7)+(rex.b<<3)):-1);
+                }
+                VSSHRQ_32(q0, q1, 31);   // create mask
+                if(v0==v1)
+                    VBIFQ(v0, v2, q0);
+                else {
+                    if(v0!=v2) VMOVQ(v0, v2);
+                    VBITQ(v0, v1, q0);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x4B:
+            INST_NAME("VBLENDVPD Gx, Vx, Ex, XMMImm8");
+            nextop = F8;
+            q0 = fpu_get_scratch(dyn, ninst);
+            u8 = geted_ib(dyn, addr, ninst, nextop)>>4;
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { 
+                    q1 = sse_get_reg(dyn, ninst, x1, u8, 0);
+                    GETGX_empty_VXEX(v0, v2, v1, 1); 
+                    F8;
+                } else { 
+                    v2 = ymm_get_reg(dyn, ninst, x1, vex.v, 0, gd, u8, (MODREG)?((nextop&7)+(rex.b<<3)):-1);
+                    if(MODREG)
+                        v1 = ymm_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0, gd, vex.v, u8);
+                    else
+                        VLDR128_U12(v1, ed, fixedaddress+16);
+                    q1 = ymm_get_reg(dyn, ninst, x1, u8, 0, vex.v, gd, (MODREG)?((nextop&7)+(rex.b<<3)):-1);
+                    v0 = ymm_get_reg_empty(dyn, ninst, x1, gd, vex.v, u8, (MODREG)?((nextop&7)+(rex.b<<3)):-1);
+                }
+                VSSHRQ_64(q0, q1, 63);   // create mask
+                if(v0==v1)
+                    VBIFQ(v0, v2, q0);
+                else {
+                    if(v0!=v2) VMOVQ(v0, v2);
+                    VBITQ(v0, v1, q0);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x4C:
+            INST_NAME("VBLENDPVB Gx, Vx, Ex, XMMImm8");
+            nextop = F8;
+            q0 = fpu_get_scratch(dyn, ninst);
+            u8 = geted_ib(dyn, addr, ninst, nextop)>>4;
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { 
+                    q1 = sse_get_reg(dyn, ninst, x1, u8, 0);
+                    GETGX_empty_VXEX(v0, v2, v1, 1); 
+                    F8;
+                } else { 
+                    v2 = ymm_get_reg(dyn, ninst, x1, vex.v, 0, gd, u8, (MODREG)?((nextop&7)+(rex.b<<3)):-1);
+                    if(MODREG)
+                        v1 = ymm_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0, gd, vex.v, u8);
+                    else
+                        VLDR128_U12(v1, ed, fixedaddress+16);
+                    q1 = ymm_get_reg(dyn, ninst, x1, u8, 0, vex.v, gd, (MODREG)?((nextop&7)+(rex.b<<3)):-1);
+                    v0 = ymm_get_reg_empty(dyn, ninst, x1, gd, vex.v, u8, (MODREG)?((nextop&7)+(rex.b<<3)):-1);
+                }
+                VSSHRQ_8(q0, q1, 7);   // create mask
+                if(v0==v1)
+                    VBIFQ(v0, v2, q0);
+                else {
+                    if(v0!=v2) VMOVQ(v0, v2);
+                    VBITQ(v0, v1, q0);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
@@ -0,0 +1,483 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+#include "my_cpuid.h"
+#include "emu/x87emu_private.h"
+#include "emu/x64shaext.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_F2_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed, vd;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u, u64;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    switch(opcode) {
+
+        case 0x10:
+            INST_NAME("VMOVSD Gx, [Vx,] Ex");
+            nextop = F8;
+            GETG;
+            if(MODREG) {
+                GETGX_empty_VXEX(v0, v2, v1, 0);
+                if(v0!=v1) VMOVeD(v0, 0, v1, 0);
+                if(v0!=v2) VMOVeD(v0, 1, v2, 1);
+            } else {
+                SMREAD();
+                GETGX_empty(v0);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v0, ed, fixedaddress); // upper part reseted
+            }
+            YMM0(gd);
+            break;
+        case 0x11:
+            INST_NAME("VMOVSD Ex, Vx, Gx");
+            nextop = F8;
+            GETG;
+            v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+            if(MODREG) {
+                GETVXEX(v2, 0, v1, 1, 0);
+                if(v0!=v1) VMOVeD(v1, 0, v0, 0);
+                if(v1!=v2) VMOVeD(v1, 1, v2, 1);
+                YMM0((nextop&7)+(rex.b<<3));
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VST64(v0, ed, fixedaddress);
+                SMWRITE2();
+            }
+            break;
+        case 0x12:
+            INST_NAME("VMOVDDUP Gx, Ex");
+            nextop = F8;
+            GETG;
+            if(MODREG) {
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                GETGX_empty(v0);
+                VDUPQ_64(v0, v1, 0);
+                if(vex.l) {
+                    GETGY_empty_EY(v0, v1);
+                    VDUPQ_64(v0, v1, 0);
+                }
+            } else {
+                SMREAD();
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x3, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                VLDQ1R_64(v0, ed);
+                if(vex.l) {
+                    GETGY_empty(v0, -1, -1, -1);
+                    ADDx_U12(x3, ed, 16);
+                    VLDQ1R_64(v0, ed);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        case 0x2A:
+            INST_NAME("VCVTSI2SD Gx, Vx, Ed");
+            nextop = F8;
+            GETGX_empty_VX(v0, v1);
+            GETED(0);
+            d1 = fpu_get_scratch(dyn, ninst);
+            if(rex.w) {
+                SCVTFDx(d1, ed);
+            } else {
+                SCVTFDw(d1, ed);
+            }
+            if(v0!=v1) VMOVQ(v0, v1);
+            VMOVeD(v0, 0, d1, 0);
+            YMM0(gd);
+            break;
+
+        case 0x2C:
+            INST_NAME("VCVTTSD2SI Gd, Ex");
+            nextop = F8;
+            GETGD;
+            GETEXSD(q0, 0, 0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                MSR_fpsr(x5);
+            }
+            FCVTZSxwD(gd, q0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                TBZ_NEXT(x5, FPSR_IOC);
+                if(rex.w) {
+                    ORRx_mask(gd, xZR, 1, 1, 0);    //0x8000000000000000
+                } else {
+                    MOV32w(gd, 0x80000000);
+                }
+            }
+            break;
+        case 0x2D:
+            INST_NAME("VCVTSD2SI Gd, Ex");
+            nextop = F8;
+            GETGD;
+            GETEXSD(q0, 0, 0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                MSR_fpsr(x5);
+            }
+            u8 = sse_setround(dyn, ninst, x1, x2, x3);
+            d1 = fpu_get_scratch(dyn, ninst);
+            FRINTID(d1, q0);
+            x87_restoreround(dyn, ninst, u8);
+            FCVTZSxwD(gd, d1);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                TBZ_NEXT(x5, FPSR_IOC);
+                if(rex.w) {
+                    ORRx_mask(gd, xZR, 1, 1, 0);    //0x8000000000000000
+                } else {
+                    MOV32w(gd, 0x80000000);
+                }
+            }
+            break;
+
+        case 0x51:
+            INST_NAME("VSQRTSD Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSD(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            if(!box64_dynarec_fastnan) {
+                q0 = fpu_get_scratch(dyn, ninst);
+                q1 = fpu_get_scratch(dyn, ninst);
+                // check if any input value was NAN
+                FCMEQD(q0, v1, v1);    // 0 if NAN, 1 if not NAN
+            }
+            FSQRTD(d1, v1);
+            if(!box64_dynarec_fastnan) {
+                FCMEQD(q1, d1, d1);    // 0 => out is NAN
+                VBIC(q1, q0, q1);      // forget it in any input was a NAN already
+                VSHLQ_64(q1, q1, 63);   // only keep the sign bit
+                VORR(d1, d1, q1);      // NAN -> -NAN
+            }
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeD(v0, 0, d1, 0);
+            YMM0(gd)
+            break;
+
+        case 0x58:
+            INST_NAME("VADDSD Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSD(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            FADDD(d1, v2, v1);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeD(v0, 0, d1, 0);
+            YMM0(gd)
+            break;
+        case 0x59:
+            INST_NAME("VMULSD Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSD(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            FMULD(d1, v2, v1);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeD(v0, 0, d1, 0);
+            YMM0(gd)
+            break;
+        case 0x5A:
+            INST_NAME("VCVTSD2SS Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSD(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            FCVT_S_D(d1, v1);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeS(v0, 0, d1, 0);
+            YMM0(gd)
+            break;
+
+        case 0x5C:
+            INST_NAME("VSUBSD Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSD(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            FSUBD(d1, v2, v1);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeD(v0, 0, d1, 0);
+            YMM0(gd)
+            break;
+        case 0x5D:
+            INST_NAME("VMINSD Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSD(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            // VMINSD: if any input is NaN, or Ex[0]<Gx[0], copy Ex[0] -> Gx[0]
+            FCMPD(v2, v1);
+            FCSELD(d1, v1, v2, cCS);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeD(v0, 0, d1, 0);   // to not erase uper part
+            YMM0(gd)
+            break;
+        case 0x5E:
+            INST_NAME("VDIVSD Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSD(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            if(!box64_dynarec_fastnan) {
+                q0 = fpu_get_scratch(dyn, ninst);
+                q1 = fpu_get_scratch(dyn, ninst);
+                // check if any input value was NAN
+                FMAXD(q0, v2, v1);    // propagate NAN
+                FCMEQD(q0, q0, q0);    // 0 if NAN, 1 if not NAN
+            }
+            FDIVD(d1, v2, v1);
+            if(!box64_dynarec_fastnan) {
+                FCMEQD(q1, d1, d1);    // 0 => out is NAN
+                VBIC(q1, q0, q1);      // forget it in any input was a NAN already
+                VSHLQ_64(q1, q1, 63);   // only keep the sign bit
+                VORR(d1, d1, q1);      // NAN -> -NAN
+            }
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeD(v0, 0, d1, 0);
+            YMM0(gd)
+            break;
+        case 0x5F:
+            INST_NAME("VMAXSD Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSD(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            FCMPD(v1, v2);
+            FCSELD(d1, v1, v2, cCS);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeD(v0, 0, d1, 0);   // to not erase uper part
+            YMM0(gd)
+            break;
+
+        case 0x70:
+            INST_NAME("VPSHUFLW Gx, Ex, Ib");
+            nextop = F8;
+            d0 = fpu_get_scratch(dyn, ninst);
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETEX(v1, 0, 1); GETGX(v0, 1); u8 = F8; } else { GETGY(v0, 1, MODREG?((nextop&7)+(rex.b<<3)):-1, -1, -1); GETEY(v1); }
+                if(u8==0b00000000 || u8==0b01010101 || u8==0b10101010 || u8==0b11111111) {
+                    if(v0==v1) {
+                        VMOVQ(d0, v1);
+                    }
+                    VDUP_16(v0, v1, u8&3);
+                    if(v0==v1)
+                        v1 = d0;
+                } else {
+                    // only low part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits
+                    if(!l) {
+                        u64 = 0;
+                        for (int i=0; i<4; ++i) {
+                            u64 |= ((uint64_t)((u8>>(i*2))&3)*2+0)<<(i*16+0);
+                            u64 |= ((uint64_t)((u8>>(i*2))&3)*2+1)<<(i*16+8);
+                        }
+                        MOV64x(x2, u64);
+                    }
+                    VMOVQDfrom(d0, 0, x2);
+                    VTBL1_8(d0, v1, d0);
+                    VMOVeD(v0, 0, d0, 0);
+                }
+                if(v0!=v1) {
+                    VMOVeD(v0, 1, v1, 1);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        case 0x7C:
+            INST_NAME("VHADDPS Gx, Vx, Ex");
+            nextop = F8;
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_VXEX(v0, v2, v1, 0); } else { GETGY_empty_VYEY(v0, v2, v1); }
+                VFADDPQS(v0, v2, v1);
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        case 0xC2:
+            INST_NAME("CMPSD Gx, Ex, Ib");
+            nextop = F8;
+            GETEXSD(v1, 0, 1);
+            GETGX_empty_VX(v0, v2);
+            u8 = F8;
+            FCMPD(v2, v1);
+            if(v0!=v2) VMOVQ(v0, v2);
+            switch(u8&7) {
+                case 0: CSETMx(x2, cEQ); break;   // Equal
+                case 1: CSETMx(x2, cCC); break;   // Less than
+                case 2: CSETMx(x2, cLS); break;   // Less or equal
+                case 3: CSETMx(x2, cVS); break;   // NaN
+                case 4: CSETMx(x2, cNE); break;   // Not Equal or unordered
+                case 5: CSETMx(x2, cCS); break;   // Greater or equal or unordered
+                case 6: CSETMx(x2, cHI); break;   // Greater or unordered, test inverted, N!=V so unordered or less than (inverted)
+                case 7: CSETMx(x2, cVC); break;   // not NaN
+            }
+            VMOVQDfrom(v0, 0, x2);
+            YMM0(gd);
+            break;
+
+        case 0xD0:
+            INST_NAME("VADDSUBPS Gx, Vx, Ex");
+            nextop = F8;
+            q0 = fpu_get_scratch(dyn, ninst);
+            static float addsubps[4] = {-1.f, 1.f, -1.f, 1.f};
+            MAYUSE(addsubps);
+            TABLE64(x2, (uintptr_t)&addsubps);
+            VLDR128_U12(q0, x2, 0);
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_VXEX(v0, v2, v1, 0); if(v0==v1) q1 = fpu_get_scratch(dyn, ninst); } else { GETGY_empty_VYEY(v0, v2, v1); }
+                if(v0==v1) {
+                    VFMULQS(q1, v1, q0);
+                    VFADDQS(v0, v2, q1);
+                } else {
+                    if(v0!=v2) VMOVQ(v0, v2);
+                    VFMLAQS(v0, v1, q0);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        case 0xE6:
+            INST_NAME("VCVTPD2DQ Gx, Ex");
+            nextop = F8;
+            u8 = sse_setround(dyn, ninst, x1, x2, x6);
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) {
+                    GETEX_Y(v1, 0, 0);
+                    GETGX_empty(v0);
+                    if(!box64_dynarec_fastround || vex.l)
+                        d0 = fpu_get_scratch(dyn, ninst);
+                } else {
+                    GETEY(v1);
+                }
+                if(box64_dynarec_fastround) {
+                    VFRINTIDQ(l?d0:v0, v1);
+                    VFCVTNSQD(l?d0:v0, l?d0:v0);  // convert double -> int64
+                    if(!l)
+                        SQXTN_32(v0, v0);   // convert int64 -> int32 with saturation in lower part, RaZ high part
+                    else
+                        SQXTN2_32(v0, d0);   // convert int64 -> int32 with saturation in higher part
+                } else {
+                    if(!l) {
+                        MRS_fpsr(x5);
+                        BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                        MSR_fpsr(x5);
+                        ORRw_mask(x4, xZR, 1, 0);    //0x80000000
+                    }
+                    for(int i=0; i<2; ++i) {
+                        BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                        MSR_fpsr(x5);
+                        if(i) {
+                            VMOVeD(d0, 0, v1, i);
+                            FRINTID(d0, d0);
+                        } else {
+                            FRINTID(d0, v1);
+                        }
+                        FCVTZSwD(x1, d0);
+                        MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                        TSTw_mask(x5, 0, 0);    // mask = 1 = FPSR_IOC
+                        CSELx(x1, x1, x4, cEQ);
+                        VMOVQSfrom(v0, i+l*2, x1);
+                    }
+                    if(!vex.l && !l) VMOVQDfrom(v0, 1, xZR);
+                }
+            }
+            x87_restoreround(dyn, ninst, u8);
+            YMM0(gd);
+            break;
+
+        case 0xF0:
+            INST_NAME("LDDQU Gx,Ex");
+            nextop = F8;
+            GETG;
+            if(MODREG) {
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                VMOVQ(v0, v1);
+                if(vex.l) {
+                    GETGY_empty_EY(v0, v1);
+                    VMOVQ(v0, v1);
+                }
+            } else {
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0xffe<<4, 7, rex, NULL, 0, 0);
+                VLDR128_U12(v0, ed, fixedaddress);
+                v0 = ymm_get_reg_empty(dyn, ninst, x1, gd, -1, -1, -1);
+                VLDR128_U12(v0, ed, fixedaddress+16);
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
@@ -0,0 +1,96 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+#include "my_cpuid.h"
+#include "emu/x87emu_private.h"
+#include "emu/x64shaext.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_F2_0F38(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed, vd;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    switch(opcode) {
+
+        case 0xF6:
+            INST_NAME("MULX Gd, Vd, Ed (,RDX)");
+            nextop = F8;
+            GETGD;
+            GETED(0);
+            GETVD;
+            if(rex.w) {
+                // 64bits mul
+                UMULH(x3, xRDX, ed);
+                MULx(vd, xRDX, ed);
+                MOVx_REG(gd, x3);
+            } else {
+                // 32bits mul
+                UMULL(x3, xRDX, ed);
+                MOVw_REG(vd, x3);
+                LSRx(gd, x3, 32);
+            }
+            break;
+        case 0xF7:
+            INST_NAME("SHRX Gd, Ed, Vd");
+            nextop = F8;
+            GETGD;
+            GETED(0);
+            GETVD;
+            ANDx_mask(x3, vd, 1, 0, rex.w?5:4); // mask 0x3f/0x1f
+            LSRxw_REG(gd, ed, x3);
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
@@ -0,0 +1,78 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+#include "my_cpuid.h"
+#include "emu/x87emu_private.h"
+#include "emu/x64shaext.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_F2_0F3A(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed, vd;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    switch(opcode) {
+
+        case 0xF0:
+            INST_NAME("RORX Gd, Ed, Ib");
+            nextop = F8;
+            GETGD;
+            GETED(1);
+            u8 = F8;
+            u8&=rex.w?0x3f:0x1f;
+            RORxw(gd, ed, u8);
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
@@ -0,0 +1,519 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+#include "my_cpuid.h"
+#include "emu/x87emu_private.h"
+#include "emu/x64shaext.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_F3_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed, vd;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u, u64;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    switch(opcode) {
+
+        case 0x10:
+            INST_NAME("VMOVSS Gx, Ex [,Vx]");
+            nextop = F8;
+            GETG;
+            if(MODREG) {
+                GETGX_empty_VXEX(v0, v2, v1, 0);
+                if((v0!=v2) && (v0!=v1)) VMOVQ(v0, v2);
+                if(v0!=v1) VMOVeS(v0, 0, v1, 0);
+                if((v0!=v2) && (v0==v1)) { VMOVeS(v0, 1, v2, 1); VMOVeD(v0, 1, v2, 1);}
+            } else {
+                GETGX_empty(v0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v0, ed, fixedaddress);
+            }
+            YMM0(gd);
+            break;
+        case 0x11:
+            INST_NAME("VMOVSS Ex, Gx [,Vx]");
+            nextop = F8;
+            GETG;
+            if(MODREG) {
+                GETGXVXEX_empty(v0, v2, v1, 0);
+                if((v2!=v1) && (v2!=v0)) VMOVQ(v2, v1);
+                if(v2!=v0) VMOVeS(v2, 0, v0, 0);
+                if((v2!=v1) && (v2==v0)) { VMOVeS(v2, 1, v0, 1); VMOVeD(v2, 1, v0, 1);}
+                YMM0((nextop&7)+(rex.b<<3));
+            } else {
+                v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VST32(v0, ed, fixedaddress);
+                SMWRITE2();
+            }
+            break;
+        case 0x12:
+            INST_NAME("VMOVSLDUP Gx, Ex");
+            nextop = F8;
+            GETEX_Y(q1, 0, 0);
+            GETGX_empty(q0);
+            VTRNQ1_32(q0, q1, q1);
+            if(vex.l) {
+                GETGY_empty_EY(q0, q1);
+                VTRNQ1_32(q0, q1, q1);
+            } else YMM0(gd);
+            break;
+
+        case 0x16:
+            INST_NAME("MOVSHDUP Gx, Ex");
+            nextop = F8;
+            GETEX_Y(q1, 0, 0);
+            GETGX_empty(q0);
+            VTRNQ2_32(q0, q1, q1);
+            if(vex.l) {
+                GETGY_empty_EY(q0, q1);
+                VTRNQ2_32(q0, q1, q1);
+            } else YMM0(gd);
+            break;
+
+        case 0x2A:
+            INST_NAME("VCVTSI2SS Gx, Vx, Ed");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETGX_empty_VX(v0, v1);
+            GETED(0);
+            if(rex.w) {
+                SCVTFSx(d1, ed);
+            } else {
+                SCVTFSw(d1, ed);
+            }
+            if(v0!=v1) VMOVQ(v0, v1);
+            VMOVeS(v0, 0, d1, 0);
+            YMM0(gd);
+            break;
+
+        case 0x2C:
+            INST_NAME("VCVTTSS2SI Gd, Ex");
+            nextop = F8;
+            GETGD;
+            GETEXSS(d0, 0, 0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                MSR_fpsr(x5);
+            }
+            FCVTZSxwS(gd, d0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                TBZ_NEXT(x5, FPSR_IOC);
+                if(rex.w) {
+                    ORRx_mask(gd, xZR, 1, 1, 0);    //0x8000000000000000
+                } else {
+                    ORRw_mask(gd, xZR, 1, 0);    //0x80000000
+                }
+            }
+            break;
+        case 0x2D:
+            INST_NAME("VCVTSS2SI Gd, Ex");
+            nextop = F8;
+            GETGD;
+            GETEXSS(q0, 0, 0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                MSR_fpsr(x5);
+            }
+            u8 = sse_setround(dyn, ninst, x1, x2, x3);
+            d1 = fpu_get_scratch(dyn, ninst);
+            FRINTIS(d1, q0);
+            x87_restoreround(dyn, ninst, u8);
+            FCVTZSxwS(gd, d1);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                TBZ_NEXT(x5, FPSR_IOC);
+                if(rex.w) {
+                    ORRx_mask(gd, xZR, 1, 1, 0);    //0x8000000000000000
+                } else {
+                    ORRw_mask(gd, xZR, 1, 0);    //0x80000000
+                }
+            }
+            break;
+
+        case 0x51:
+            INST_NAME("SQRTSS Gx, Ex");
+            nextop = F8;
+            GETEXSS(d0, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            d1 = fpu_get_scratch(dyn, ninst);
+            FSQRTS(d1, d0);
+            if(v0!=v2) VMOVQ(v0, v2);
+            VMOVeS(v0, 0, d1, 0);
+            YMM0(gd);
+            break;
+        case 0x52:
+            INST_NAME("VRSQRTSS Gx, Vx Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            GETVX(v2, 0);
+            GETEXSS(v1, 0, 0);
+            d0 = fpu_get_scratch(dyn, ninst);
+            d1 = fpu_get_scratch(dyn, ninst);
+            // so here: F32: Imm8 = abcd efgh that gives => aBbbbbbc defgh000 00000000 00000000
+            // and want 1.0f = 0x3f800000
+            // so 00111111 10000000 00000000 00000000
+            // a = 0, b = 1, c = 1, d = 1, efgh=0
+            // 0b01110000
+            FMOVS_8(d0, 0b01110000);
+            FSQRTS(d1, v1);
+            FDIVS(d0, d0, d1);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeS(v0, 0, d0, 0);
+            YMM0(gd);
+            break;
+        case 0x53:
+            INST_NAME("VRCPSS Gx, Vx, Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            GETVX(v2, 0);
+            GETEXSS(v1, 0, 0);
+            d0 = fpu_get_scratch(dyn, ninst);
+            FMOVS_8(d0, 0b01110000);    //1.0f
+            FDIVS(d0, d0, v1);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeS(v0, 0, d0, 0);
+            YMM0(gd);
+            break;
+
+        case 0x58:
+            INST_NAME("VADDSS Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSS(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            if(v0!=v2) {
+                if(v0==v1)  {
+                    VMOV(d1, v1);
+                    v1 = d1;
+                }
+                VMOVQ(v0, v2);
+            }
+            FADDS(d1, v0, v1);
+            VMOVeS(v0, 0, d1, 0);
+            YMM0(gd)
+            break;
+        case 0x59:
+            INST_NAME("VMULSS Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSS(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            if(v0!=v2) {
+                if(v0==v1)  {
+                    VMOV(d1, v1);
+                    v1 = d1;
+                }
+                VMOVQ(v0, v2);
+            }
+            FMULS(d1, v0, v1);
+            VMOVeS(v0, 0, d1, 0);
+            YMM0(gd)
+            break;
+        case 0x5A:
+            INST_NAME("VCVTSS2SD Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSS(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            if(v0!=v2) {
+                if(v0==v1)  {
+                    VMOV(d1, v1);
+                    v1 = d1;
+                }
+                VMOVQ(v0, v2);
+            }
+            FCVT_D_S(d1, v1);
+            VMOVeD(v0, 0, d1, 0);
+            YMM0(gd);
+            break;
+        case 0x5B:
+            INST_NAME("VCVTTPS2DQ Gx, Ex");
+            nextop = F8;
+            d0 = fpu_get_scratch(dyn, ninst);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);
+                ORRw_mask(x4, xZR, 1, 0);    //0x80000000
+            }
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETGX_empty_EX(v0, v1, 0); } else { GETGY_empty_EY(v0, v1); }
+                if(box64_dynarec_fastround) {
+                    VFCVTZSQS(v0, v1);
+                } else {
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    for(int i=0; i<4; ++i) {
+                        BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                        MSR_fpsr(x5);
+                        VMOVeS(d0, 0, v1, i);
+                        VFCVTZSs(d0, d0);
+                        MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                        TBZ(x5, FPSR_IOC, 4+4);
+                        VMOVQSfrom(d0, 0, x4);
+                        VMOVeS(v0, i, d0, 0);
+                    }
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x5C:
+            INST_NAME("VSUBSS Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSS(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            FSUBS(d1, v2, v1);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeS(v0, 0, d1, 0);
+            YMM0(gd)
+            break;
+        case 0x5D:
+            INST_NAME("VMINSS Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSS(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            FCMPS(v2, v1);
+            FCSELS(d1, v1, v2, cCS);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeS(v0, 0, d1, 0);   // to not erase uper part
+            YMM0(gd)
+            break;
+        case 0x5E:
+            INST_NAME("VDIVSS Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSS(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            FDIVS(d1, v2, v1);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeS(v0, 0, d1, 0);
+            YMM0(gd)
+            break;
+        case 0x5F:
+            INST_NAME("VMAXSS Gx, Vx, Ex");
+            nextop = F8;
+            d1 = fpu_get_scratch(dyn, ninst);
+            GETEXSS(v1, 0, 0);
+            GETGX_empty_VX(v0, v2);
+            FCMPS(v1, v2);
+            FCSELS(d1, v1, v2, cCS);
+            if(v0!=v2) {
+                VMOVQ(v0, v2);
+            }
+            VMOVeS(v0, 0, d1, 0);   // to not erase uper part
+            YMM0(gd)
+            break;
+
+        case 0x6F:
+            INST_NAME("VMOVDQU Gx, Ex");// no alignment constraint on NEON here, so same as MOVDQA
+            nextop = F8;
+            if(MODREG) {
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                GETGX_empty(v0);
+                VMOVQ(v0, v1);
+                if(vex.l) {
+                    v1 = ymm_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0, gd, -12, -1);
+                    GETGY_empty(v0, (nextop&7)+(rex.b<<3), -1, -1);
+                    VMOVQ(v0, v1);
+                }
+            } else {
+                GETGX_empty(v0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0xffe<<4, 15, rex, NULL, 0, 0);
+                VLDR128_U12(v0, ed, fixedaddress);
+                if(vex.l) {
+                    GETGY_empty(v0, -1, -1, -1);
+                    VLDR128_U12(v0, ed, fixedaddress+16);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+        case 0x70:
+            INST_NAME("VPSHUFHW Gx, Ex, Ib");
+            nextop = F8;
+            d0 = fpu_get_scratch(dyn, ninst);
+            for(int l=0; l<1+vex.l; ++l) {
+                if(!l) { GETEX(v1, 0, 1); GETGX(v0, 1); u8 = F8; } else { GETGY(v0, 1, MODREG?((nextop&7)+(rex.b<<3)):-1, -1, -1); GETEY(v1); }
+                if(u8==0b00000000 || u8==0b01010101 || u8==0b10101010 || u8==0b11111111) {
+                    VDUP_16(d0, v1, 4+(u8&3));
+                } else {
+                    // only high part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits
+                    if(!l) {
+                        u64 = 0;
+                        for (int i=0; i<4; ++i) {
+                            u64 |= ((uint64_t)((u8>>(i*2))&3)*2+8)<<(i*16+0);
+                            u64 |= ((uint64_t)((u8>>(i*2))&3)*2+9)<<(i*16+8);
+                        }
+                        MOV64x(x2, u64);
+                    }
+                    VMOVQDfrom(d0, 0, x2);
+                    VTBL1_8(d0, v1, d0);
+                }
+                VMOVeD(v0, 1, d0, 0);
+                if(v0!=v1) {
+                    VMOVeD(v0, 0, v1, 0);
+                }
+            }
+            if(!vex.l) YMM0(gd);
+            break;
+
+        case 0x7E:
+            INST_NAME("MOVQ Gx, Ex");
+            nextop = F8;
+            if(MODREG) {
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 0);
+                GETGX_empty(v0);
+                FMOVD(v0, v1);
+            } else {
+                GETGX_empty(v0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v0, ed, fixedaddress);
+            }
+            YMM0(gd);
+            break;
+        case 0x7F:
+            INST_NAME("VMOVDQU Ex, Gx");
+            nextop = F8;
+            GETGX(v0, 0);
+            if(MODREG) {
+                v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
+                VMOVQ(v1, v0);
+                if(vex.l) {
+                    GETGY(v0, 0, (nextop&7) + (rex.b<<3), -1, -1);
+                    v1 = ymm_get_reg_empty(dyn, ninst, x1, (nextop&7) + (rex.b<<3), gd, -1, -1);
+                    VMOVQ(v1, v0);
+                } // no ymm raz here it seems
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0xffe<<4, 15, rex, NULL, 0, 0);
+                VSTR128_U12(v0, ed, fixedaddress);
+                if(vex.l) {
+                    GETGY(v0, 0, -1, -1, -1);
+                    VSTR128_U12(v0, ed, fixedaddress+16);
+                }
+                SMWRITE2();
+            }
+            break;
+
+        case 0xC2:
+            INST_NAME("VCMPSS Gx, Vx, Ex, Ib");
+            nextop = F8;
+            GETEXSS(v1, 0, 1);
+            GETGX_empty_VX(v0, v2);
+            u8 = F8;
+            if(((u8&15)!=11) && ((u8&15)!=15)) {
+                if((u8&15)>7)
+                    FCMPS(v1, v2);
+                else
+                    FCMPS(v2, v1);
+            }
+            // TODO: create a test for this one, there might be an issue with cases 9, 10 and 13
+            if(v0!=v2) VMOVQ(v0, v2);
+            switch(u8&15) {
+                case 0x00: CSETMw(x2, cEQ); break;  // Equal
+                case 0x01: CSETMw(x2, cCC); break;  // Less than
+                case 0x02: CSETMw(x2, cLS); break;  // Less or equal
+                case 0x03: CSETMw(x2, cVS); break;  // NaN
+                case 0x04: CSETMw(x2, cNE); break;  // Not Equal or unordered
+                case 0x05: CSETMw(x2, cCS); break;  // Greater or equal or unordered
+                case 0x06: CSETMw(x2, cHI); break;  // Greater or unordered
+                case 0x07: CSETMw(x2, cVC); break;  // not NaN
+                case 0x08: CSETMw(x2, cEQ); CSETMw(x3, cVS); ORRw_REG(x2, x2, x3); break;  // Equal or unordered
+                case 0x09: CSETMw(x2, cHI); break;  // Less than or unordered
+                case 0x0a: CSETMw(x2, cCS); break;  // Less or equal or unordered
+                case 0x0b: MOV32w(x2, 0); break;    // false
+                case 0x0c: CSETMw(x2, cNE); CSETMw(x3, cVS); BICw(x2, x2, x3); break;  // Not Equal not unordered
+                case 0x0d: CSETMw(x2, cLS); break;  // Greater or equal not unordered
+                case 0x0e: CSETMw(x2, cCC); break;  // Greater not unordered
+                case 0x0f: MOV32w(x2, 0xffffffff); break; // true
+            }
+            VMOVQSfrom(v0, 0, x2);
+            YMM0(gd);
+            break;
+
+        case 0xE6:
+            INST_NAME("VCVTDQ2PD Gx, Ex");
+            nextop = F8;
+            if(vex.l) {
+                GETEX_Y(v1, 0, 0);
+            } else {
+                GETEXSD(v1, 0, 0);
+            }
+            GETGX_empty(v0);
+            d0 = fpu_get_scratch(dyn, ninst);
+            if(vex.l) {
+                q0 = ymm_get_reg_empty(dyn, ninst, x1, gd, -1, -1, -1);
+                SXTL2_32(q0, v1);
+                SCVTQFD(q0, q0);
+            } else YMM0(gd);
+            SXTL_32(v0, v1);
+            SCVTQFD(v0, v0);
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
@@ -0,0 +1,78 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+#include "my_cpuid.h"
+#include "emu/x87emu_private.h"
+#include "emu/x64shaext.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "../dynarec_helper.h"
+
+uintptr_t dynarec64_AVX_F3_0F38(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, vex_t vex, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    uint8_t gd, ed, vd;
+    uint8_t wback, wb1, wb2;
+    uint8_t eb1, eb2, gb1, gb2;
+    int32_t i32, i32_;
+    int cacheupd = 0;
+    int v0, v1, v2;
+    int q0, q1, q2;
+    int d0, d1, d2;
+    int s0;
+    uint64_t tmp64u;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(q0);
+    MAYUSE(q1);
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(j64);
+    MAYUSE(cacheupd);
+
+    rex_t rex = vex.rex;
+
+    switch(opcode) {
+
+        case 0xF7:
+            INST_NAME("SARX Gd, Ed, Vd");
+            nextop = F8;
+            GETGD;
+            GETED(0);
+            GETVD;
+            ANDx_mask(x3, vd, 1, 0, rex.w?5:4); // mask 0x3f/0x1f
+            ASRxw_REG(gd, ed, x3);
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
@@ -19,7 +19,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"


@@ -38,6 +38,7 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
    MAYUSE(v2);
    MAYUSE(v1);

+    if(MODREG)
    switch(nextop) {
        case 0xC0:
        case 0xC1:
@@ -89,7 +90,7 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOM(x1, x2, x3);
+            FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
            break;
        case 0xD8:
        case 0xD9:
@@ -107,7 +108,7 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOM(x1, x2, x3);
+            FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
            X87_POP_OR_FAIL(dyn, ninst, x3);
            break;
        case 0xE0:
@@ -178,119 +179,120 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                FDIVD(v1, v2, v1);
            }
            break;
-
        default:
-            switch((nextop>>3)&7) {
-                case 0:
-                    INST_NAME("FADD ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
-                    s0 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(s0, ed, fixedaddress);
-                    if(ST_IS_F(0)) {
-                        FADDS(v1, v1, s0);
-                    } else {
-                        FCVT_D_S(s0, s0);
-                        FADDD(v1, v1, s0);
-                    }
-                    break;
-                case 1:
-                    INST_NAME("FMUL ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
-                    s0 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(s0, ed, fixedaddress);
-                    if(ST_IS_F(0)) {
-                        FMULS(v1, v1, s0);
-                    } else {
-                        FCVT_D_S(s0, s0);
-                        FMULD(v1, v1, s0);
-                    }
-                    break;
-                case 2:
-                    INST_NAME("FCOM ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
-                    s0 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(s0, ed, fixedaddress);
-                    if(ST_IS_F(0)) {
-                        FCMPS(v1, s0);
-                    } else {
-                        FCVT_D_S(s0, s0);
-                        FCMPD(v1, s0);
-                    }
-                    FCOM(x1, x2, x3);
-                    break;
-                case 3:
-                    INST_NAME("FCOMP ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
-                    s0 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(s0, ed, fixedaddress);
-                    if(ST_IS_F(0)) {
-                        FCMPS(v1, s0);
-                    } else {
-                        FCVT_D_S(s0, s0);
-                        FCMPD(v1, s0);
-                    }
-                    FCOM(x1, x2, x3);
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                case 4:
-                    INST_NAME("FSUB ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
-                    s0 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(s0, ed, fixedaddress);
-                    if(ST_IS_F(0)) {
-                        FSUBS(v1, v1, s0);
-                    } else {
-                        FCVT_D_S(s0, s0);
-                        FSUBD(v1, v1, s0);
-                    }
-                    break;
-                case 5:
-                    INST_NAME("FSUBR ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
-                    s0 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(s0, ed, fixedaddress);
-                    if(ST_IS_F(0)) {
-                        FSUBS(v1, s0, v1);
-                    } else {
-                        FCVT_D_S(s0, s0);
-                        FSUBD(v1, s0, v1);
-                    }
-                    break;
-                case 6:
-                    INST_NAME("FDIV ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
-                    s0 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(s0, ed, fixedaddress);
-                    if(ST_IS_F(0)) {
-                        FDIVS(v1, v1, s0);
-                    } else {
-                        FCVT_D_S(s0, s0);
-                        FDIVD(v1, v1, s0);
-                    }
-                    break;
-                case 7:
-                    INST_NAME("FDIVR ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
-                    s0 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(s0, ed, fixedaddress);
-                    if(ST_IS_F(0)) {
-                        FDIVS(v1, s0, v1);
-                    } else {
-                        FCVT_D_S(s0, s0);
-                        FDIVD(v1, s0, v1);
-                    }
-                    break;
-                default:
-                    DEFAULT;
-            }
-    }
+            DEFAULT;
+            break;
+    } else
+        switch((nextop>>3)&7) {
+            case 0:
+                INST_NAME("FADD ST0, float[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                s0 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(s0, ed, fixedaddress);
+                if(ST_IS_F(0)) {
+                    FADDS(v1, v1, s0);
+                } else {
+                    FCVT_D_S(s0, s0);
+                    FADDD(v1, v1, s0);
+                }
+                break;
+            case 1:
+                INST_NAME("FMUL ST0, float[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                s0 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(s0, ed, fixedaddress);
+                if(ST_IS_F(0)) {
+                    FMULS(v1, v1, s0);
+                } else {
+                    FCVT_D_S(s0, s0);
+                    FMULD(v1, v1, s0);
+                }
+                break;
+            case 2:
+                INST_NAME("FCOM ST0, float[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                s0 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(s0, ed, fixedaddress);
+                if(ST_IS_F(0)) {
+                    FCMPS(v1, s0);
+                } else {
+                    FCVT_D_S(s0, s0);
+                    FCMPD(v1, s0);
+                }
+                FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
+                break;
+            case 3:
+                INST_NAME("FCOMP ST0, float[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                s0 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(s0, ed, fixedaddress);
+                if(ST_IS_F(0)) {
+                    FCMPS(v1, s0);
+                } else {
+                    FCVT_D_S(s0, s0);
+                    FCMPD(v1, s0);
+                }
+                FCOM(x1, x2, x3, x4, v1, s0, ST_IS_F(0));
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            case 4:
+                INST_NAME("FSUB ST0, float[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                s0 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(s0, ed, fixedaddress);
+                if(ST_IS_F(0)) {
+                    FSUBS(v1, v1, s0);
+                } else {
+                    FCVT_D_S(s0, s0);
+                    FSUBD(v1, v1, s0);
+                }
+                break;
+            case 5:
+                INST_NAME("FSUBR ST0, float[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                s0 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(s0, ed, fixedaddress);
+                if(ST_IS_F(0)) {
+                    FSUBS(v1, s0, v1);
+                } else {
+                    FCVT_D_S(s0, s0);
+                    FSUBD(v1, s0, v1);
+                }
+                break;
+            case 6:
+                INST_NAME("FDIV ST0, float[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                s0 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(s0, ed, fixedaddress);
+                if(ST_IS_F(0)) {
+                    FDIVS(v1, v1, s0);
+                } else {
+                    FCVT_D_S(s0, s0);
+                    FDIVD(v1, v1, s0);
+                }
+                break;
+            case 7:
+                INST_NAME("FDIVR ST0, float[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                s0 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(s0, ed, fixedaddress);
+                if(ST_IS_F(0)) {
+                    FDIVS(v1, s0, v1);
+                } else {
+                    FCVT_D_S(s0, s0);
+                    FDIVD(v1, s0, v1);
+                }
+                break;
+            default:
+                DEFAULT;
+        }
    return addr;
 }
@@ -19,7 +19,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"


@@ -31,7 +31,7 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
    uint8_t ed;
    uint8_t wback, wb1;
    uint8_t u8;
-    int64_t fixedaddress;
+    int64_t fixedaddress, j64;
    int unscaled;
    int v1, v2;
    int s0;
@@ -41,6 +41,7 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
    MAYUSE(v2);
    MAYUSE(v1);

+    if(MODREG)
    switch(nextop) {
        case 0xC0:
        case 0xC1:
@@ -127,22 +128,113 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD_0(v1);
            }
-            FCOM(x1, x2, x3);   // same flags...
+            FCOM(x1, x2, x3, x4, 0, 0, ST_IS_F(0));   // same flags...
            break;
        case 0xE5:
            INST_NAME("FXAM");
+            #if 1
+            i1 = x87_get_current_cache(dyn, ninst, 0, NEON_CACHE_ST_D);
+            // value put in x14
+            if(i1==-1) {
+                if(fpu_is_st_freed(dyn, ninst, 0)) {
+                    MOV32w(x4, 0b100000100000000);
+                    B_MARK3_nocond;
+                } else {
+                    // not in cache, so check Empty status and load it
+                    i2 = -dyn->n.x87stack;
+                    LDRw_U12(x3, xEmu, offsetof(x64emu_t, fpu_stack));
+                    if(i2) {
+                        if(i2<0) {
+                            ADDw_U12(x3, x3, -i2);
+                        } else {
+                            SUBw_U12(x3, x3, i2);
+                        }
+                    }
+                    CMPSw_U12(x3, 0);
+                    MOV32w(x4, 0b100000100000000);  // empty: C3,C2,C0 = 101
+                    B_MARK3(cLE);
+                    // x5 will be the actual top
+                    LDRw_U12(x5, xEmu, offsetof(x64emu_t, top));
+                    if(i2) {
+                        if(i2<0) {
+                            SUBw_U12(x5, x5, -i2);
+                        } else {
+                            ADDw_U12(x5, x5, i2);
+                        }
+                        ANDw_mask(x5, x5, 0, 2);    // (emu->top + i)&7
+                    }
+                    // load x2 with ST0 anyway, for sign extraction
+                    ADDx_REG_LSL(x1, xEmu, x5, 3);
+                    LDRx_U12(x2, x1, offsetof(x64emu_t, x87));
+                    // load tag
+                    if(i2>=0) {
+                        LDRH_U12(x3, xEmu, offsetof(x64emu_t, fpu_tags));
+                        if(i2>0) {
+                            ORRw_mask(x3, x3, 0b010000, 0b001111);  // 0xffff0000
+                            LSRw_IMM(x3, x3, i2*2);
+                        }
+                        TSTw_mask(x3, 0, 1);    // 0b11
+                        B_MARK3(cNE);   // empty: C3,C2,C0 = 101
+                    }
+                }
+            } else {
+                // simply move from cache reg to x2
+                v1 = dyn->n.x87reg[i1];
+                VMOVQDto(x2, v1, 0);
+            }
+            // get exponant in x1
+            LSRx_IMM(x1, x2, 20+32);
+            ANDSx_mask(x1, x1, 1, 0b00000, 0b001010); // 0x7ff
+            B_MARK(cNE); // not zero or denormal
+            ANDSx_mask(x1, x2, 1, 0, 0b111110); // 0x7fffffffffffffff
+            MOV32w(x4, 0b100000000000000); // Zero: C3,C2,C0 = 100
+            MOV32w(x5, 0b100010000000000); // Denormal: C3,C2,C0 = 110
+            CSELx(x4, x4, x5, cEQ);
+            B_MARK3(c__);
+            MARK;
+            CMPSx_U12(x1, 0x7ff);   // infinite/NaN?
+            MOV32w(x5, 0b000010000000000); // normal: C3,C2,C0 = 010
+            CSELx(x4, x5, x4, cNE);
+            B_MARK3(cNE);
+            TSTx_mask(x2, 1, 0b000000, 0b110011); // 0x000fffffffffffff
+            MOV32w(x4, 0b000010100000000); // infinity: C3,C2,C0 = 011
+            MOV32w(x3, 0b000000100000000); // NaN: C3,C2,C0 = 001
+            CSELx(x4, x4, x3, cEQ);
+            MARK3;
+            // Extract signa & Update SW
+            LSRx_IMM(x1, x2, 63);
+            BFIx(x4, x1, 9, 1); //C1
+            LDRH_U12(x1, xEmu, offsetof(x64emu_t, sw));
+            MOV32w(x2, 0b01000111);
+            BICw_REG_LSL(x1, x1, x2, 8);
+            ORRw_REG(x4, x4, x1);
+            STRH_U12(x4, xEmu, offsetof(x64emu_t, sw));
+            #else
            MESSAGE(LOG_DUMP, "Need Optimization\n");
-            x87_refresh(dyn, ninst, x1, x2, 0);
+            i1 = x87_stackcount(dyn, ninst, x1);
+            x87_forget(dyn, ninst, x1, x2, 0);
            CALL(fpu_fxam, -1);  // should be possible inline, but is it worth it?
+            x87_unstackcount(dyn, ninst, x1, i1);
+            #endif
            break;

        case 0xE8:
            INST_NAME("FLD1");
-            X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, NEON_CACHE_ST_F);
-            if(ST_IS_F(0)) {
-                FMOVS_8(v1, 0b01110000);
+            if(ninst<dyn->size+2 && (dyn->insts[ninst+1].pred_sz==1) && (dyn->insts[ninst+2].pred_sz==1)
+                && PK(0)==0xD9 && PK(1)==0xE8
+                && PK(2)==0xD9 && PK(3)==0xF3
+            ) {
+                MESSAGE(LOG_DUMP, "Hack for FLD1 FLD1 FPATAN");
+                X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, NEON_CACHE_ST_F);
+                FTABLE64(v1, PI/4.0);
+                addr+=4;
            } else {
-                FMOVD_8(v1, 0b01110000);
+                X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, NEON_CACHE_ST_F);
+                if(ST_IS_F(0)) {
+                    FMOVS_8(v1, 0b01110000);
+                } else {
+                    FMOVD_8(v1, 0b01110000);
+                }
            }
            break;
        case 0xE9:
@@ -202,7 +294,7 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            CALL(native_ftan, -1);
            x87_unstackcount(dyn, ninst, x1, i1);
            if(PK(0)==0xdd && PK(1)==0xd8) {
-                MESSAGE(LOG_DUMP, "Optimized next DD D8 fstp st0, st0, not emiting 1\n");
+                MESSAGE(LOG_DUMP, "Optimized next DD D8 fstp st0, st0, not emitting 1\n");
                u8 = F8;
                u8 = F8;
            } else {
@@ -245,7 +337,7 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            #else
            v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
            v2 = x87_get_st(dyn, ninst, x1, x2, 1, NEON_CACHE_ST_D);
-            s0 = fpu_get_scratch(dyn);
+            s0 = fpu_get_scratch(dyn, ninst);
            FDIVD(s0, v1, v2);
            FRINTRRD(s0, s0, 0b00); // Nearest == TieToEven?
            FCVTZSxD(x4, s0);
@@ -293,7 +385,7 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            #else
            v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
            v2 = x87_get_st(dyn, ninst, x1, x2, 1, NEON_CACHE_ST_D);
-            s0 = fpu_get_scratch(dyn);
+            s0 = fpu_get_scratch(dyn, ninst);
            FDIVD(s0, v1, v2);
            FRINTZD(s0, s0);
            FCVTZSxD(x4, s0);
@@ -384,92 +476,79 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            CALL(native_fcos, -1);
            x87_unstackcount(dyn, ninst, x1, i1);
            break;
-
-
-        case 0xD1:
-        case 0xD4:
-        case 0xD5:
-        case 0xD6:
-        case 0xD7:
-        case 0xE2:
-        case 0xE3:
-        case 0xE6:
-        case 0xE7:
-        case 0xEF:
+        default:
            DEFAULT;
            break;
-
-        default:
-            switch((nextop>>3)&7) {
-                case 0:
-                    INST_NAME("FLD ST0, float[ED]");
-                    X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, box64_dynarec_x87double?NEON_CACHE_ST_D:NEON_CACHE_ST_F);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(v1, ed, fixedaddress);
-                    if(!ST_IS_F(0)) {
-                        FCVT_D_S(v1, v1);
-                    }
-                    break;
-                case 2:
-                    INST_NAME("FST float[ED], ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
-                    if(ST_IS_F(0))
-                        s0 = v1;
-                    else {
-                        s0 = fpu_get_scratch(dyn);
-                        FCVT_S_D(s0, v1);
-                    }
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VST32(s0, ed, fixedaddress);
-                    break;
-                case 3:
-                    INST_NAME("FSTP float[ED], ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    if(!ST_IS_F(0)) {
-                        FCVT_S_D(v1, v1);
-                    }
-                    VST32(v1, ed, fixedaddress);
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                case 4:
-                    INST_NAME("FLDENV Ed");
-                    MESSAGE(LOG_DUMP, "Need Optimization\n");
-                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3); // maybe only x87, not SSE?
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
-                    if(ed!=x1) {
-                        MOVx_REG(x1, ed);
-                    }
-                    MOV32w(x2, 0);
-                    CALL(fpu_loadenv, -1);
-                    break;
-                case 5:
-                    INST_NAME("FLDCW Ew");
-                    GETEW(x1, 0);
-                    STRH_U12(x1, xEmu, offsetof(x64emu_t, cw));    // hopefully cw is not too far for an imm8
-                    break;
-                case 6:
-                    INST_NAME("FNSTENV Ed");
-                    MESSAGE(LOG_DUMP, "Need Optimization\n");
-                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3); // maybe only x87, not SSE?
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
-                    if(ed!=x1) {
-                        MOVx_REG(x1, ed);
-                    }
-                    MOV32w(x2, 0);
-                    CALL(fpu_savenv, -1);
-                    break;
-                case 7:
-                    INST_NAME("FNSTCW Ew");
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    ed = x1;
-                    wb1 = 1;
-                    LDRH_U12(x1, xEmu, offsetof(x64emu_t, cw));
-                    EWBACK;
-                    break;
-                default:
-                    DEFAULT;
-            }
-    }
+    } else
+        switch((nextop>>3)&7) {
+            case 0:
+                INST_NAME("FLD ST0, float[ED]");
+                X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, box64_dynarec_x87double?NEON_CACHE_ST_D:NEON_CACHE_ST_F);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v1, ed, fixedaddress);
+                if(!ST_IS_F(0)) {
+                    FCVT_D_S(v1, v1);
+                }
+                break;
+            case 2:
+                INST_NAME("FST float[ED], ST0");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                if(ST_IS_F(0))
+                    s0 = v1;
+                else {
+                    s0 = fpu_get_scratch(dyn, ninst);
+                    FCVT_S_D(s0, v1);
+                }
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VST32(s0, ed, fixedaddress);
+                break;
+            case 3:
+                INST_NAME("FSTP float[ED], ST0");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                if(!ST_IS_F(0)) {
+                    FCVT_S_D(v1, v1);
+                }
+                VST32(v1, ed, fixedaddress);
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            case 4:
+                INST_NAME("FLDENV Ed");
+                MESSAGE(LOG_DUMP, "Need Optimization\n");
+                fpu_purgecache(dyn, ninst, 0, x1, x2, x3); // maybe only x87, not SSE?
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                if(ed!=x1) {
+                    MOVx_REG(x1, ed);
+                }
+                MOV32w(x2, 0);
+                CALL(fpu_loadenv, -1);
+                break;
+            case 5:
+                INST_NAME("FLDCW Ew");
+                GETEW(x1, 0);
+                STRH_U12(x1, xEmu, offsetof(x64emu_t, cw));    // hopefully cw is not too far for an imm8
+                break;
+            case 6:
+                INST_NAME("FNSTENV Ed");
+                MESSAGE(LOG_DUMP, "Need Optimization\n");
+                fpu_purgecache(dyn, ninst, 0, x1, x2, x3); // maybe only x87, not SSE?
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                if(ed!=x1) {
+                    MOVx_REG(x1, ed);
+                }
+                MOV32w(x2, 0);
+                CALL(fpu_savenv, -1);
+                break;
+            case 7:
+                INST_NAME("FNSTCW Ew");
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                ed = x1;
+                wb1 = 1;
+                LDRH_U12(x1, xEmu, offsetof(x64emu_t, cw));
+                EWBACK;
+                break;
+            default:
+                DEFAULT;
+        }
    return addr;
 }
@@ -19,7 +19,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"


@@ -42,6 +42,7 @@ uintptr_t dynarec64_DA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
    MAYUSE(ed);
    MAYUSE(j64);

+    if(MODREG)
    switch(nextop) {
        case 0xC0:
        case 0xC1:
@@ -129,111 +130,100 @@ uintptr_t dynarec64_DA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOM(x1, x2, x3);
+            FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
            X87_POP_OR_FAIL(dyn, ninst, x3);
            X87_POP_OR_FAIL(dyn, ninst, x3);
            break;

-        case 0xE4:
-        case 0xF0:
-        case 0xF1:
-        case 0xF4:
-        case 0xF5:
-        case 0xF6:
-        case 0xF7:
-        case 0xF8:
-        case 0xF9:
-        case 0xFD:
-            DEFAULT;
-            break;
-
        default:
-            switch((nextop>>3)&7) {
-                case 0:
-                    INST_NAME("FIADD ST0, Ed");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(v2, ed, fixedaddress);
-                    SXTL_32(v2, v2);    // i32 -> i64
-                    SCVTFDD(v2, v2);    // i64 -> double
-                    FADDD(v1, v1, v2);
-                    break;
-                case 1:
-                    INST_NAME("FIMUL ST0, Ed");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(v2, ed, fixedaddress);
-                    SXTL_32(v2, v2);    // i32 -> i64
-                    SCVTFDD(v2, v2);    // i64 -> double
-                    FMULD(v1, v1, v2);
-                    break;
-                case 2:
-                    INST_NAME("FICOM ST0, Ed");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(v2, ed, fixedaddress);
-                    SXTL_32(v2, v2);    // i32 -> i64
-                    SCVTFDD(v2, v2);    // i64 -> double
-                    FCMPD(v1, v2);
-                    FCOM(x1, x2, x3);
-                    break;
-                case 3:
-                    INST_NAME("FICOMP ST0, Ed");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(v2, ed, fixedaddress);
-                    SXTL_32(v2, v2);    // i32 -> i64
-                    SCVTFDD(v2, v2);    // i64 -> double
-                    FCMPD(v1, v2);
-                    FCOM(x1, x2, x3);
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                case 4:
-                    INST_NAME("FISUB ST0, Ed");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(v2, ed, fixedaddress);
-                    SXTL_32(v2, v2);    // i32 -> i64
-                    SCVTFDD(v2, v2);    // i64 -> double
-                    FSUBD(v1, v1, v2);
-                    break;
-                case 5:
-                    INST_NAME("FISUBR ST0, Ed");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(v2, ed, fixedaddress);
-                    SXTL_32(v2, v2);    // i32 -> i64
-                    SCVTFDD(v2, v2);    // i64 -> double
-                    FSUBD(v1, v2, v1);
-                    break;
-                case 6:
-                    INST_NAME("FIDIV ST0, Ed");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(v2, ed, fixedaddress);
-                    SXTL_32(v2, v2);    // i32 -> i64
-                    SCVTFDD(v2, v2);    // i64 -> double
-                    FDIVD(v1, v1, v2);
-                    break;
-                case 7:
-                    INST_NAME("FIDIVR ST0, Ed");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(v2, ed, fixedaddress);
-                    SXTL_32(v2, v2);    // i32 -> i64
-                    SCVTFDD(v2, v2);    // i64 -> double
-                    FDIVD(v1, v2, v1);
-                    break;
-            }
-    }
+            DEFAULT;
+            break;
+    } else
+        switch((nextop>>3)&7) {
+            case 0:
+                INST_NAME("FIADD ST0, Ed");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v2, ed, fixedaddress);
+                SXTL_32(v2, v2);    // i32 -> i64
+                SCVTFDD(v2, v2);    // i64 -> double
+                FADDD(v1, v1, v2);
+                break;
+            case 1:
+                INST_NAME("FIMUL ST0, Ed");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v2, ed, fixedaddress);
+                SXTL_32(v2, v2);    // i32 -> i64
+                SCVTFDD(v2, v2);    // i64 -> double
+                FMULD(v1, v1, v2);
+                break;
+            case 2:
+                INST_NAME("FICOM ST0, Ed");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v2, ed, fixedaddress);
+                SXTL_32(v2, v2);    // i32 -> i64
+                SCVTFDD(v2, v2);    // i64 -> double
+                FCMPD(v1, v2);
+                FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
+                break;
+            case 3:
+                INST_NAME("FICOMP ST0, Ed");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v2, ed, fixedaddress);
+                SXTL_32(v2, v2);    // i32 -> i64
+                SCVTFDD(v2, v2);    // i64 -> double
+                FCMPD(v1, v2);
+                FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            case 4:
+                INST_NAME("FISUB ST0, Ed");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v2, ed, fixedaddress);
+                SXTL_32(v2, v2);    // i32 -> i64
+                SCVTFDD(v2, v2);    // i64 -> double
+                FSUBD(v1, v1, v2);
+                break;
+            case 5:
+                INST_NAME("FISUBR ST0, Ed");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v2, ed, fixedaddress);
+                SXTL_32(v2, v2);    // i32 -> i64
+                SCVTFDD(v2, v2);    // i64 -> double
+                FSUBD(v1, v2, v1);
+                break;
+            case 6:
+                INST_NAME("FIDIV ST0, Ed");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v2, ed, fixedaddress);
+                SXTL_32(v2, v2);    // i32 -> i64
+                SCVTFDD(v2, v2);    // i64 -> double
+                FDIVD(v1, v1, v2);
+                break;
+            case 7:
+                INST_NAME("FIDIVR ST0, Ed");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v2, ed, fixedaddress);
+                SXTL_32(v2, v2);    // i32 -> i64
+                SCVTFDD(v2, v2);    // i64 -> double
+                FDIVD(v1, v2, v1);
+                break;
+        }
    return addr;
 }

@@ -19,7 +19,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"


@@ -42,6 +42,7 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
    MAYUSE(v1);
    MAYUSE(j64);

+    if(MODREG)
    switch(nextop) {
        case 0xC0:
        case 0xC1:
@@ -154,7 +155,7 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOMI(x1, x2);
+            FCOMI(x1, x2, x4, v1, v2, ST_IS_F(0));
            break;
        case 0xF0:
        case 0xF1:
@@ -173,38 +174,32 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOMI(x1, x2);
-            break;
-
-        case 0xE0:
-        case 0xE4:
-        case 0xE5:
-        case 0xE6:
-        case 0xE7:
-            DEFAULT;
+            FCOMI(x1, x2, x4, v1, v2, ST_IS_F(0));
            break;

        default:
-            switch((nextop>>3)&7) {
-                case 0:
-                    INST_NAME("FILD ST0, Ed");
-                    X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, NEON_CACHE_ST_D);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    VLD32(v1, ed, fixedaddress);
-                    SXTL_32(v1, v1);    // i32 -> i64
-                    SCVTFDD(v1, v1);    // i64 -> double
-                    break;
-                case 1:
-                    INST_NAME("FISTTP Ed, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    s0 = fpu_get_scratch(dyn);
-                    #if 0
-                    ed = x1;
+            DEFAULT;
+            break;
+    } else
+        switch((nextop>>3)&7) {
+            case 0:
+                INST_NAME("FILD ST0, Ed");
+                X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, NEON_CACHE_ST_D);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v1, ed, fixedaddress);
+                SXTL_32(v1, v1);    // i32 -> i64
+                SCVTFDD(v1, v1);    // i64 -> double
+                break;
+            case 1:
+                INST_NAME("FISTTP Ed, ST0");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                s0 = fpu_get_scratch(dyn, ninst);
+                if(arm64_frintts) {
                    FRINT32ZD(s0, v1);
-                    FCVTZSwD(ed, s0);
-                    WBACK;
-                    #else
+                    FCVTZSwD(x5, s0);
+                    STW(x5, wback, fixedaddress);
+                } else {
                    MRS_fpsr(x5);
                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                    MSR_fpsr(x5);
@@ -217,21 +212,20 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    MOV32w(x5, 0x80000000);
                    STW(x5, wback, fixedaddress);
                    MARK3;
-                    #endif
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                case 2:
-                    INST_NAME("FIST Ed, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    u8 = x87_setround(dyn, ninst, x1, x2, x4); // x1 have the modified RPSCR reg
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    s0 = fpu_get_scratch(dyn);
-                    #if 0
-                    ed = x1;
+                }
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            case 2:
+                INST_NAME("FIST Ed, ST0");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                u8 = x87_setround(dyn, ninst, x1, x2, x4); // x1 have the modified RPSCR reg
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                s0 = fpu_get_scratch(dyn, ninst);
+                if(arm64_frintts) {
                    FRINT32XD(s0, v1);
-                    FCVTZSwD(ed, s0);
-                    WBACK;
-                    #else
+                    FCVTZSwD(x5, s0);
+                    STW(x5, wback, fixedaddress);
+                } else {
                    MRS_fpsr(x5);
                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                    MSR_fpsr(x5);
@@ -244,21 +238,20 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    MOV32w(x5, 0x80000000);
                    STW(x5, wback, fixedaddress);
                    MARK3;
-                    #endif
-                    x87_restoreround(dyn, ninst, u8);
-                    break;
-                case 3:
-                    INST_NAME("FISTP Ed, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    u8 = x87_setround(dyn, ninst, x1, x2, x4); // x1 have the modified RPSCR reg
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
-                    s0 = fpu_get_scratch(dyn);
-                    #if 0
-                    ed = x1;
+                }
+                x87_restoreround(dyn, ninst, u8);
+                break;
+            case 3:
+                INST_NAME("FISTP Ed, ST0");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                u8 = x87_setround(dyn, ninst, x1, x2, x4); // x1 have the modified RPSCR reg
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                s0 = fpu_get_scratch(dyn, ninst);
+                if(arm64_frintts) {
                    FRINT32XD(s0, v1);
-                    FCVTZSwD(ed, s0);
-                    WBACK;
-                    #else
+                    FCVTZSwD(x5, s0);
+                    STW(x5, wback, fixedaddress);
+                } else {
                    MRS_fpsr(x5);
                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                    MSR_fpsr(x5);
@@ -271,112 +264,116 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    MOV32w(x5, 0x80000000);
                    STW(x5, wback, fixedaddress);
                    MARK3;
-                    #endif
-                    x87_restoreround(dyn, ninst, u8);
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                case 5:
-                    INST_NAME("FLD tbyte");
+                }
+                x87_restoreround(dyn, ninst, u8);
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            case 5:
+                INST_NAME("FLD tbyte");
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                if((PK(0)==0xDB && ((PK(1)>>3)&7)==7) || (!rex.is32bits && PK(0)>=0x40 && PK(0)<=0x4f && PK(1)==0xDB && ((PK(2)>>3)&7)==7)) {
+                    NOTEST(x5);
+                    // the FLD is immediatly followed by an FSTP
+                    LDRx_U12(x5, ed, 0);
+                    LDRH_U12(x6, ed, 8);
+                    // no persistant scratch register, so unrool both instruction here...
+                    MESSAGE(LOG_DUMP, "\tHack: FSTP tbyte\n");
+                    nextop = F8;    // 0xDB or rex
+                    if(!rex.is32bits && nextop>=0x40 && nextop<=0x4f) {
+                        rex.rex = nextop;
+                        nextop = F8;    //0xDB
+                    } else
+                        rex.rex = 0;
+                    nextop = F8;    //modrm
                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
-                    if((PK(0)==0xDB && ((PK(1)>>3)&7)==7) || (PK(0)>=0x40 && PK(0)<=0x4f && PK(1)==0xDB && ((PK(2)>>3)&7)==7)) {
-                        // the FLD is immediatly followed by an FSTP
-                        LDRx_U12(x5, ed, 0);
-                        LDRH_U12(x6, ed, 8);
-                        // no persistant scratch register, so unrool both instruction here...
-                        MESSAGE(LOG_DUMP, "\tHack: FSTP tbyte\n");
-                        nextop = F8;    // 0xDB or rex
-                        if(nextop>=0x40 && nextop<=0x4f) {
-                            rex.rex = nextop;
-                            nextop = F8;    //0xDB
-                        } else
-                            rex.rex = 0;
-                        nextop = F8;    //modrm
-                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
-                        STRx_U12(x5, ed, 0);
-                        STRH_U12(x6, ed, 8);
-                    } else {
-                        if(box64_x87_no80bits) {
-                            X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, NEON_CACHE_ST_D);
-                            VLDR64_U12(v1, ed, fixedaddress);
-                        } else {
-                            if(ed!=x1) {
-                                MOVx_REG(x1, ed);
-                            }
-                            X87_PUSH_EMPTY_OR_FAIL(dyn, ninst, x3);
-                            CALL(native_fld, -1);
-                        }
-                    }
-                    break;
-                case 7:
-                    INST_NAME("FSTP tbyte");
+                    STRx_U12(x5, ed, 0);
+                    STRH_U12(x6, ed, 8);
+                } else {
                    if(box64_x87_no80bits) {
-                        v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                        VST64(v1, wback, fixedaddress);
+                        X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, NEON_CACHE_ST_D);
+                        VLDR64_U12(v1, ed, fixedaddress);
                    } else {
-                        #if 0
-                        x87_forget(dyn, ninst, x1, x3, 0);
-                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
                        if(ed!=x1) {
                            MOVx_REG(x1, ed);
                        }
-                        CALL(native_fstp, -1);
-                        #else
-                        // Painfully long, straight conversion from the C code, shoud be optimized
-                        v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
-                        FMOVxD(x1, v1);
-                        // do special value first
-                        TSTx_mask(x1, 1, 0b00000, 0b111110);    //0x7fffffffffffffffL
-                        B_MARK(cNE);
-                        // Zero
-                        LSRx(x3, x1, 63-15);    //x3 = sign+exp
-                        MOVZw(x5, 0);           // x5 = mantisse
-                        B_MARK3_nocond;
-                        MARK;
-                        // get sign, in main ouput x5 for sign+exp
-                        ANDx_mask(x5, x1, 1, 1, 0); //0x8000000000000000
-                        LSRx(x5, x5, 63-15);    // x5 = sign
-                        // get exp
-                        LSRx(x3, x1, 52);       // x3 = exp11
-                        ANDw_mask(x3, x3, 0, 0b1010);    //0x7ff
-                        MOV32w(x4, 0x7ff);
-                        CMPSw_REG(x3, x4);
-                        B_MARK2(cNE);
-                        // NaN and Infinite
-                        ORRw_mask(x3, x5, 0, 0b1110);    //x3 = sign | 0x7fff
-                        TSTx_mask(x1, 1, 0, 0b110011); //0x000fffffffffffffL
-                        ORRx_mask(x5, xZR, 1, 1, 0);    //0x8000000000000000
-                        ORRx_mask(x4, xZR, 1, 0b10, 0b01); //0xc000000000000000
-                        CSELx(x5, x5, x4, cEQ);     // x5 = mantisse
-                        B_MARK3_nocond;
-                        MARK2;
-                        // regular / denormals
-                        ANDx_mask(x1, x1, 1, 0, 0b110011); //0x000fffffffffffffL
-                        LSLx_IMM(x1, x1, 11);   //x1 = mantisse missing "1"
-                        MOVZw(x4, 16383-1023);  //BIAS80 - BIAS64
-                        CBZw(x3, 4+3*4);        // exp11 == 0?
-                        // normals
-                        ADDw_REG(x3, x3, x4);   // x3 = exp16
-                        ORRw_REG(x3, x3, x5);   // x3 = sign | exp
-                        ORRx_mask(x5, x1, 1, 1, 0);    //0x8000000000000000 x5 = mantisse
-                        B_MARK3_nocond;
-                        // denormals
-                        CLZx(x6, x1);
-                        ADDw_U12(x6, x6, 1);    // "one"
-                        SUBw_REG(x3, x4, x6);   // x3 = exp16
-                        ORRw_REG(x3, x3, x5);   // x3 = sign | exp16
-                        LSLx_REG(x5, x1, x6);   // x5 = mantisse
-                        MARK3;
-                        STRx_U12(x5, wback, 0);
-                        STRH_U12(x3, wback, 8);
-                        #endif
+                        X87_PUSH_EMPTY_OR_FAIL(dyn, ninst, 0);
+                        // sync top
+                        s0 = x87_stackcount(dyn, ninst, x3);
+                        CALL(native_fld, -1);
+                        // go back with the top & stack counter
+                        x87_unstackcount(dyn, ninst, x3, s0);
                    }
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                default:
-                    DEFAULT;
-            }
-    }
+                }
+                break;
+            case 7:
+                INST_NAME("FSTP tbyte");
+                if(box64_x87_no80bits) {
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VST64(v1, wback, fixedaddress);
+                } else {
+                    #if 0
+                    x87_forget(dyn, ninst, x1, x3, 0);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                    if(ed!=x1) {
+                        MOVx_REG(x1, ed);
+                    }
+                    CALL(native_fstp, -1);
+                    #else
+                    // Painfully long, straight conversion from the C code, shoud be optimized
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                    FMOVxD(x1, v1);
+                    // do special value first
+                    TSTx_mask(x1, 1, 0b00000, 0b111110);    //0x7fffffffffffffffL
+                    B_MARK(cNE);
+                    // Zero
+                    LSRx(x3, x1, 63-15);    //x3 = sign+exp
+                    MOVZw(x5, 0);           // x5 = mantisse
+                    B_MARK3_nocond;
+                    MARK;
+                    // get sign, in main ouput x5 for sign+exp
+                    ANDx_mask(x5, x1, 1, 1, 0); //0x8000000000000000
+                    LSRx(x5, x5, 63-15);    // x5 = sign
+                    // get exp
+                    LSRx(x3, x1, 52);       // x3 = exp11
+                    ANDw_mask(x3, x3, 0, 0b1010);    //0x7ff
+                    MOV32w(x4, 0x7ff);
+                    CMPSw_REG(x3, x4);
+                    B_MARK2(cNE);
+                    // NaN and Infinite
+                    ORRw_mask(x3, x5, 0, 0b1110);    //x3 = sign | 0x7fff
+                    TSTx_mask(x1, 1, 0, 0b110011); //0x000fffffffffffffL
+                    ORRx_mask(x5, xZR, 1, 1, 0);    //0x8000000000000000
+                    ORRx_mask(x4, xZR, 1, 0b10, 0b01); //0xc000000000000000
+                    CSELx(x5, x5, x4, cEQ);     // x5 = mantisse
+                    B_MARK3_nocond;
+                    MARK2;
+                    // regular / denormals
+                    ANDx_mask(x1, x1, 1, 0, 0b110011); //0x000fffffffffffffL
+                    LSLx_IMM(x1, x1, 11);   //x1 = mantisse missing "1"
+                    MOVZw(x4, 16383-1023);  //BIAS80 - BIAS64
+                    CBZw(x3, 4+3*4);        // exp11 == 0?
+                    // normals
+                    ADDw_REG(x3, x3, x4);   // x3 = exp16
+                    ORRw_REG(x3, x3, x5);   // x3 = sign | exp
+                    ORRx_mask(x5, x1, 1, 1, 0);    //0x8000000000000000 x5 = mantisse
+                    B_MARK3_nocond;
+                    // denormals
+                    CLZx(x6, x1);
+                    ADDw_U12(x6, x6, 1);    // "one"
+                    SUBw_REG(x3, x4, x6);   // x3 = exp16
+                    ORRw_REG(x3, x3, x5);   // x3 = sign | exp16
+                    LSLx_REG(x5, x1, x6);   // x5 = mantisse
+                    MARK3;
+                    STRx_U12(x5, wback, 0);
+                    STRH_U12(x3, wback, 8);
+                    #endif
+                }
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            default:
+                DEFAULT;
+        }
    return addr;
 }
@@ -19,7 +19,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"


@@ -36,6 +36,7 @@ uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
    MAYUSE(v2);
    MAYUSE(v1);

+    if(MODREG)
    switch(nextop) {
        case 0xC0:
        case 0xC1:
@@ -87,7 +88,7 @@ uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOM(x1, x2, x3);
+            FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
            break;
        case 0xD8:
        case 0xD9:
@@ -105,7 +106,7 @@ uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOM(x1, x2, x3);
+            FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
            X87_POP_OR_FAIL(dyn, ninst, x3);
            break;
        case 0xE0:
@@ -177,75 +178,77 @@ uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            }
            break;
        default:
-            switch((nextop>>3)&7) {
-                case 0:
-                    INST_NAME("FADD ST0, double[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VLD64(v2, wback, fixedaddress);
-                    FADDD(v1, v1, v2);
-                    break;
-                case 1:
-                    INST_NAME("FMUL ST0, double[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VLD64(v2, wback, fixedaddress);
-                    FMULD(v1, v1, v2);
-                    break;
-                case 2:
-                    INST_NAME("FCOM ST0, double[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VLD64(v2, wback, fixedaddress);
-                    FCMPD(v1, v2);
-                    FCOM(x1, x2, x3);
-                    break;
-                case 3:
-                    INST_NAME("FCOMP ST0, double[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VLD64(v2, wback, fixedaddress);
-                    FCMPD(v1, v2);
-                    FCOM(x1, x2, x3);
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                case 4:
-                    INST_NAME("FSUB ST0, double[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VLD64(v2, wback, fixedaddress);
-                    FSUBD(v1, v1, v2);
-                    break;
-                case 5:
-                    INST_NAME("FSUBR ST0, double[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VLD64(v2, wback, fixedaddress);
-                    FSUBD(v1, v2, v1);
-                    break;
-                case 6:
-                    INST_NAME("FDIV ST0, double[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VLD64(v2, wback, fixedaddress);
-                    FDIVD(v1, v1, v2);
-                    break;
-                case 7:
-                    INST_NAME("FDIVR ST0, double[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VLD64(v2, wback, fixedaddress);
-                    FDIVD(v1, v2, v1);
-                    break;
-            }
-    }
+            DEFAULT;
+            break;
+    } else
+        switch((nextop>>3)&7) {
+            case 0:
+                INST_NAME("FADD ST0, double[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v2, wback, fixedaddress);
+                FADDD(v1, v1, v2);
+                break;
+            case 1:
+                INST_NAME("FMUL ST0, double[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v2, wback, fixedaddress);
+                FMULD(v1, v1, v2);
+                break;
+            case 2:
+                INST_NAME("FCOM ST0, double[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v2, wback, fixedaddress);
+                FCMPD(v1, v2);
+                FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
+                break;
+            case 3:
+                INST_NAME("FCOMP ST0, double[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v2, wback, fixedaddress);
+                FCMPD(v1, v2);
+                FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            case 4:
+                INST_NAME("FSUB ST0, double[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v2, wback, fixedaddress);
+                FSUBD(v1, v1, v2);
+                break;
+            case 5:
+                INST_NAME("FSUBR ST0, double[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v2, wback, fixedaddress);
+                FSUBD(v1, v2, v1);
+                break;
+            case 6:
+                INST_NAME("FDIV ST0, double[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v2, wback, fixedaddress);
+                FDIVD(v1, v1, v2);
+                break;
+            case 7:
+                INST_NAME("FDIVR ST0, double[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v2, wback, fixedaddress);
+                FDIVD(v1, v2, v1);
+                break;
+        }
    return addr;
 }
@@ -19,7 +19,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"


@@ -40,6 +40,7 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
    MAYUSE(v1);
    MAYUSE(j64);

+    if(MODREG)
    switch(nextop) {
        case 0xC0:
        case 0xC1:
@@ -50,10 +51,20 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
        case 0xC6:
        case 0xC7:
            INST_NAME("FFREE STx");
+            #if 1
+            if((nextop&7)==0 && PK(0)==0xD9 && PK(1)==0xF7) {
+                MESSAGE(LOG_DUMP, "Hack for FFREE ST0 / FINCSTP\n");
+                x87_do_pop(dyn, ninst, x1);
+                addr+=2;
+                SKIPTEST(x1);
+            } else
+                x87_free(dyn, ninst, x1, x2, x3, nextop&7);
+            #else
            MESSAGE(LOG_DUMP, "Need Optimization\n");
            x87_purgecache(dyn, ninst, 0, x1, x2, x3);
            MOV32w(x1, nextop&7);
            CALL(fpu_do_free, -1);
+            #endif
            break;
        case 0xD0:
        case 0xD1:
@@ -107,7 +118,7 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOM(x1, x2, x3);
+            FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
            break;
        case 0xE8:
        case 0xE9:
@@ -125,125 +136,99 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOM(x1, x2, x3);
+            FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
            X87_POP_OR_FAIL(dyn, ninst, x3);
            break;

-        case 0xC8:
-        case 0xC9:
-        case 0xCA:
-        case 0xCB:
-        case 0xCC:
-        case 0xCD:
-        case 0xCE:
-        case 0xCF:
-        case 0xF0:
-        case 0xF1:
-        case 0xF2:
-        case 0xF3:
-        case 0xF4:
-        case 0xF5:
-        case 0xF6:
-        case 0xF7:
-        case 0xF8:
-        case 0xF9:
-        case 0xFA:
-        case 0xFB:
-        case 0xFC:
-        case 0xFD:
-        case 0xFE:
-        case 0xFF:
+        default:
            DEFAULT;
            break;
-
-        default:
-            switch((nextop>>3)&7) {
-                case 0:
-                    INST_NAME("FLD double");
-                    X87_PUSH_OR_FAIL(v1, dyn, ninst, x3, NEON_CACHE_ST_D);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VLD64(v1, ed, fixedaddress);
-                    break;
-                case 1:
-                    INST_NAME("FISTTP i64, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_I64);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    if(ST_IS_I64(0)) {
-                        VST64(v1, ed, fixedaddress);
-                    } else {
-                        s0 = fpu_get_scratch(dyn);
-                        #if 0
-                        // those are ARM 8.5 opcode!
+    } else
+        switch((nextop>>3)&7) {
+            case 0:
+                INST_NAME("FLD double");
+                X87_PUSH_OR_FAIL(v1, dyn, ninst, x3, NEON_CACHE_ST_D);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v1, ed, fixedaddress);
+                break;
+            case 1:
+                INST_NAME("FISTTP i64, ST0");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_I64);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                if(ST_IS_I64(0)) {
+                    VST64(v1, ed, fixedaddress);
+                } else {
+                    s0 = fpu_get_scratch(dyn, ninst);
+                    if(arm64_frintts) {
                        FRINT64ZD(s0, v1);
                        FCVTZSxD(x2, s0);
-                        STRx_U12(x2, ed, fixedaddress);
-                        #else
+                        STx(x2, ed, fixedaddress);
+                    } else {
                        MRS_fpsr(x5);
                        BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                        MSR_fpsr(x5);
                        FRINTRRD(s0, v1, 3);
                        FCVTZSxD(x2, s0);
-                        STx(x2, ed, fixedaddress);
                        MRS_fpsr(x5);   // get back FPSR to check the IOC bit
                        TBZ_MARK3(x5, FPSR_IOC);
-                        ORRx_mask(x5, xZR, 1, 1, 0);    //0x8000000000000000
-                        STx(x5, ed, fixedaddress);
+                        ORRx_mask(x2, xZR, 1, 1, 0);    //0x8000000000000000
                        MARK3;
-                        #endif
+                        STx(x2, ed, fixedaddress);
                    }
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                case 2:
-                    INST_NAME("FST double");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VST64(v1, ed, fixedaddress);
-                    break;
-                case 3:
-                    INST_NAME("FSTP double");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VST64(v1, ed, fixedaddress);
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                case 4:
-                    INST_NAME("FRSTOR m108byte");
-                    MESSAGE(LOG_DUMP, "Need Optimization\n");
-                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
-                    if(ed!=x1) {MOVx_REG(x1, ed);}
-                    CALL(native_frstor, -1);
-                    break;
-                case 6:
-                    INST_NAME("FSAVE m108byte");
-                    MESSAGE(LOG_DUMP, "Need Optimization\n");
-                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
-                    if(ed!=x1) {MOVx_REG(x1, ed);}
-                    CALL(native_fsave, -1);
-                    break;
-                case 7:
-                    INST_NAME("FNSTSW m2byte");
-                    //fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x4, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
-                    LDRH_U12(x3, xEmu, offsetof(x64emu_t, sw));
-                    if(dyn->n.x87stack) {
-                        // update top
-                        if(dyn->n.x87stack>0) {
-                            SUBw_U12(x2, x2, dyn->n.x87stack);
-                        } else {
-                            ADDw_U12(x2, x2, -dyn->n.x87stack);
-                        }
-                        ANDw_mask(x2, x2, 0, 2);
+                }
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            case 2:
+                INST_NAME("FST double");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VST64(v1, ed, fixedaddress);
+                break;
+            case 3:
+                INST_NAME("FSTP double");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VST64(v1, ed, fixedaddress);
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            case 4:
+                INST_NAME("FRSTOR m108byte");
+                MESSAGE(LOG_DUMP, "Need Optimization\n");
+                fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                if(ed!=x1) {MOVx_REG(x1, ed);}
+                CALL(native_frstor, -1);
+                break;
+            case 6:
+                INST_NAME("FNSAVE m108byte");
+                MESSAGE(LOG_DUMP, "Need Optimization\n");
+                fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                if(ed!=x1) {MOVx_REG(x1, ed);}
+                CALL(native_fsave, -1);
+                CALL(reset_fpu, -1);
+                break;
+            case 7:
+                INST_NAME("FNSTSW m2byte");
+                //fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x4, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
+                LDRH_U12(x3, xEmu, offsetof(x64emu_t, sw));
+                if(dyn->n.x87stack) {
+                    // update top
+                    if(dyn->n.x87stack>0) {
+                        SUBw_U12(x2, x2, dyn->n.x87stack);
+                    } else {
+                        ADDw_U12(x2, x2, -dyn->n.x87stack);
                    }
-                    BFIw(x3, x2, 11, 3); // inject TOP at bit 11 (3 bits)
-                    STRH_U12(x3, xEmu, offsetof(x64emu_t, sw));
-                    STH(x3, ed, fixedaddress);   // store whole sw flags
-                    break;
-                default:
-                    DEFAULT;
-            }
-    }
+                    ANDw_mask(x2, x2, 0, 2);
+                }
+                BFIw(x3, x2, 11, 3); // inject TOP at bit 11 (3 bits)
+                STRH_U12(x3, xEmu, offsetof(x64emu_t, sw));
+                STH(x3, ed, fixedaddress);   // store whole sw flags
+                break;
+            default:
+                DEFAULT;
+        }
    return addr;
 }
@@ -19,7 +19,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"


@@ -36,6 +36,7 @@ uintptr_t dynarec64_DE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
    MAYUSE(v2);
    MAYUSE(v1);

+    if(MODREG)
    switch(nextop) {
        case 0xC0:
        case 0xC1:
@@ -89,7 +90,7 @@ uintptr_t dynarec64_DE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOM(x1, x2, x3);
+            FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
            X87_POP_OR_FAIL(dyn, ninst, x3);
            break;
        case 0xD9:
@@ -101,7 +102,7 @@ uintptr_t dynarec64_DE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOM(x1, x2, x3);
+            FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
            X87_POP_OR_FAIL(dyn, ninst, x3);
            X87_POP_OR_FAIL(dyn, ninst, x3);
            break;
@@ -177,109 +178,102 @@ uintptr_t dynarec64_DE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            }
            X87_POP_OR_FAIL(dyn, ninst, x3);
            break;
-        case 0xD8:
-        case 0xDA:
-        case 0xDB:
-        case 0xDC:
-        case 0xDD:
-        case 0xDE:
-        case 0xDF:
+        default:
            DEFAULT;
            break;
-        default:
-            switch((nextop>>3)&7) {
-                case 0:
-                    INST_NAME("FIADD ST0, word[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    VLD16(v2, wback, fixedaddress);
-                    SXTL_16(v2, v2);
-                    SXTL_32(v2, v2);
-                    SCVTFDD(v2, v2);
-                    FADDD(v1, v1, v2);
-                    break;
-                case 1:
-                    INST_NAME("FIMUL ST0, word[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    VLD16(v2, wback, fixedaddress);
-                    SXTL_16(v2, v2);
-                    SXTL_32(v2, v2);
-                    SCVTFDD(v2, v2);
-                    FMULD(v1, v1, v2);
-                    break;
-                case 2:
-                    INST_NAME("FICOM ST0, word[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    VLD16(v2, wback, fixedaddress);
-                    SXTL_16(v2, v2);
-                    SXTL_32(v2, v2);
-                    SCVTFDD(v2, v2);
-                    FCMPD(v1, v2);
-                    FCOM(x1, x2, x3);
-                    break;
-                case 3:
-                    INST_NAME("FICOMP ST0, word[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    VLD16(v2, wback, fixedaddress);
-                    SXTL_16(v2, v2);
-                    SXTL_32(v2, v2);
-                    SCVTFDD(v2, v2);
-                    FCMPD(v1, v2);
-                    FCOM(x1, x2, x3);
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                case 4:
-                    INST_NAME("FISUB ST0, word[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    VLD16(v2, wback, fixedaddress);
-                    SXTL_16(v2, v2);
-                    SXTL_32(v2, v2);
-                    SCVTFDD(v2, v2);
-                    FSUBD(v1, v1, v2);
-                    break;
-                case 5:
-                    INST_NAME("FISUBR ST0, word[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    VLD16(v2, wback, fixedaddress);
-                    SXTL_16(v2, v2);
-                    SXTL_32(v2, v2);
-                    SCVTFDD(v2, v2);
-                    FSUBD(v1, v2, v1);
-                    break;
-                case 6:
-                    INST_NAME("FIDIV ST0, word[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    VLD16(v2, wback, fixedaddress);
-                    SXTL_16(v2, v2);
-                    SXTL_32(v2, v2);
-                    SCVTFDD(v2, v2);
-                    FDIVD(v1, v1, v2);
-                    break;
-                case 7:
-                    INST_NAME("FIDIVR ST0, word[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
-                    v2 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    VLD16(v2, wback, fixedaddress);
-                    SXTL_16(v2, v2);
-                    SXTL_32(v2, v2);
-                    SCVTFDD(v2, v2);
-                    FDIVD(v1, v2, v1);
-                    break;
-            }
-    }
+    } else
+        switch((nextop>>3)&7) {
+            case 0:
+                INST_NAME("FIADD ST0, word[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                VLD16(v2, wback, fixedaddress);
+                SXTL_16(v2, v2);
+                SXTL_32(v2, v2);
+                SCVTFDD(v2, v2);
+                FADDD(v1, v1, v2);
+                break;
+            case 1:
+                INST_NAME("FIMUL ST0, word[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                VLD16(v2, wback, fixedaddress);
+                SXTL_16(v2, v2);
+                SXTL_32(v2, v2);
+                SCVTFDD(v2, v2);
+                FMULD(v1, v1, v2);
+                break;
+            case 2:
+                INST_NAME("FICOM ST0, word[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                VLD16(v2, wback, fixedaddress);
+                SXTL_16(v2, v2);
+                SXTL_32(v2, v2);
+                SCVTFDD(v2, v2);
+                FCMPD(v1, v2);
+                FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
+                break;
+            case 3:
+                INST_NAME("FICOMP ST0, word[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                VLD16(v2, wback, fixedaddress);
+                SXTL_16(v2, v2);
+                SXTL_32(v2, v2);
+                SCVTFDD(v2, v2);
+                FCMPD(v1, v2);
+                FCOM(x1, x2, x3, x4, v1, v2, ST_IS_F(0));
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            case 4:
+                INST_NAME("FISUB ST0, word[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                VLD16(v2, wback, fixedaddress);
+                SXTL_16(v2, v2);
+                SXTL_32(v2, v2);
+                SCVTFDD(v2, v2);
+                FSUBD(v1, v1, v2);
+                break;
+            case 5:
+                INST_NAME("FISUBR ST0, word[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                VLD16(v2, wback, fixedaddress);
+                SXTL_16(v2, v2);
+                SXTL_32(v2, v2);
+                SCVTFDD(v2, v2);
+                FSUBD(v1, v2, v1);
+                break;
+            case 6:
+                INST_NAME("FIDIV ST0, word[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                VLD16(v2, wback, fixedaddress);
+                SXTL_16(v2, v2);
+                SXTL_32(v2, v2);
+                SCVTFDD(v2, v2);
+                FDIVD(v1, v1, v2);
+                break;
+            case 7:
+                INST_NAME("FIDIVR ST0, word[ED]");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                v2 = fpu_get_scratch(dyn, ninst);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                VLD16(v2, wback, fixedaddress);
+                SXTL_16(v2, v2);
+                SXTL_32(v2, v2);
+                SCVTFDD(v2, v2);
+                FDIVD(v1, v2, v1);
+                break;
+        }
    return addr;
 }
@@ -19,7 +19,7 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"


@@ -41,6 +41,7 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
    MAYUSE(v1);
    MAYUSE(j64);

+    if(MODREG)
    switch(nextop) {
        case 0xC0:
        case 0xC1:
@@ -55,6 +56,25 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            X87_POP_OR_FAIL(dyn, ninst, x3);
            break;

+        case 0xD0:
+        case 0xD1:
+        case 0xD2:
+        case 0xD3:
+        case 0xD4:
+        case 0xD5:
+        case 0xD6:
+        case 0xD7:
+            INST_NAME("FSTP STx, ST0");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FMOVS(v2, v1);
+            } else {
+                FMOVD(v2, v1);
+            }
+            X87_POP_OR_FAIL(dyn, ninst, x3);
+            break;
+
        case 0xE0:
            INST_NAME("FNSTSW AX");
            LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
@@ -89,7 +109,7 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOMI(x1, x2);
+            FCOMI(x1, x2, x4, v1, v2, ST_IS_F(0));
            X87_POP_OR_FAIL(dyn, ninst, x3);
            break;
        case 0xF0:
@@ -110,287 +130,249 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            } else {
                FCMPD(v1, v2);
            }
-            FCOMI(x1, x2);
+            FCOMI(x1, x2, x4, v1, v2, ST_IS_F(0));
            X87_POP_OR_FAIL(dyn, ninst, x3);
            break;

-        case 0xC8:
-        case 0xC9:
-        case 0xCA:
-        case 0xCB:
-        case 0xCC:
-        case 0xCD:
-        case 0xCE:
-        case 0xCF:
-        case 0xD0:
-        case 0xD1:
-        case 0xD2:
-        case 0xD3:
-        case 0xD4:
-        case 0xD5:
-        case 0xD6:
-        case 0xD7:
-        case 0xD8:
-        case 0xD9:
-        case 0xDA:
-        case 0xDB:
-        case 0xDC:
-        case 0xDD:
-        case 0xDE:
-        case 0xDF:
-        case 0xE1:
-        case 0xE2:
-        case 0xE3:
-        case 0xE4:
-        case 0xE5:
-        case 0xE6:
-        case 0xE7:
-        case 0xF8:
-        case 0xF9:
-        case 0xFA:
-        case 0xFB:
-        case 0xFC:
-        case 0xFD:
-        case 0xFE:
-        case 0xFF:
+        default:
            DEFAULT;
            break;
-
-        default:
-            switch((nextop>>3)&7) {
-                case 0:
-                    INST_NAME("FILD ST0, Ew");
-                    X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, NEON_CACHE_ST_F);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    LDSHw(x1, wback, fixedaddress);
-                    if(ST_IS_F(0)) {
-                        SCVTFSw(v1, x1);
-                    } else {
-                        SCVTFDw(v1, x1);
-                    }
-                    break;
-                case 1:
-                    INST_NAME("FISTTP Ew, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    ed = x1;
-                    s0 = fpu_get_scratch(dyn);
-                    #if 0
-                    // this version needs ARM v8.5, //TODO: add detection of this extension to use it
-                    FRINT32ZD(s0, v1);
-                    // no saturation instruction on Arm, so using NEON
+    } else
+        switch((nextop>>3)&7) {
+            case 0:
+                INST_NAME("FILD ST0, Ew");
+                X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, NEON_CACHE_ST_F);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                LDSHw(x1, wback, fixedaddress);
+                if(ST_IS_F(0)) {
+                    SCVTFSw(v1, x1);
+                } else {
+                    SCVTFDw(v1, x1);
+                }
+                break;
+            case 1:
+                INST_NAME("FISTTP Ew, ST0");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                ed = x1;
+                s0 = fpu_get_scratch(dyn, ninst);
+                #if 0
+                // this version needs ARM v8.5, and doesn't handle saturation for 32bits integer not fitting 16bits
+                FRINT32ZD(s0, v1);
+                // no saturation instruction on Arm, so using NEON
+                VFCVTZSd(s0, s0);
+                SQXTN_S_D(s0, s0);
+                SQXTN_H_S(s0, s0);
+                VST16(s0, wback, fixedaddress);
+                #else
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                BFCw(x5, FPSR_QC, 1);   // reset QC bit
+                MSR_fpsr(x5);
+                if(ST_IS_F(0)) {
+                    VFCVTZSs(s0, v1);
+                } else {
+                    VFCVTZSd(s0, v1);
+                    SQXTN_S_D(s0, s0);
+                }
+                VMOVSto(x3, s0, 0);
+                MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                TBNZ_MARK2(x5, FPSR_IOC);
+                SXTHw(x5, x3);  // check if 16bits value is fine
+                SUBw_REG(x5, x5, x3);
+                CBZw_MARK3(x5);
+                MARK2;
+                MOV32w(x3, 0x8000);
+                MARK3;
+                STH(x3, wback, fixedaddress);
+                #endif
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            case 2:
+                INST_NAME("FIST Ew, ST0");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                u8 = x87_setround(dyn, ninst, x1, x2, x4);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                ed = x1;
+                s0 = fpu_get_scratch(dyn, ninst);
+                #if 0
+                FRINT32XD(s0, v1);
+                // no saturation instruction on Arm, so using NEON
+                VFCVTZSd(s0, s0);
+                SQXTN_S_D(s0, s0);
+                SQXTN_H_S(s0, s0);
+                VST16(s0, wback, fixedaddress);
+                #else
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                BFCw(x5, FPSR_QC, 1);   // reset QC bit
+                MSR_fpsr(x5);
+                if(ST_IS_F(0)) {
+                    FRINTXS(s0, v1);
+                    VFCVTZSs(s0, s0);
+                } else {
+                    FRINTXD(s0, v1);
                    VFCVTZSd(s0, s0);
                    SQXTN_S_D(s0, s0);
-                    SQXTN_H_S(s0, s0);
-                    VST16(s0, wback, fixedaddress);
-                    #else
-                    MRS_fpsr(x5);
-                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
-                    BFCw(x5, FPSR_QC, 1);   // reset QC bit
-                    MSR_fpsr(x5);
-                    if(ST_IS_F(0)) {
-                        VFCVTZSs(s0, v1);
-                    } else {
-                        VFCVTZSd(s0, v1);
-                        SQXTN_S_D(s0, s0);
-                    }
-                    VMOVSto(x3, s0, 0);
-                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
-                    TBNZ_MARK2(x5, FPSR_IOC);
-                    SXTHw(x5, x3);  // check if 16bits value is fine
-                    SUBw_REG(x5, x5, x3);
-                    CBZw_MARK3(x5);
-                    MARK2;
-                    MOV32w(x3, 0x8000);
-                    MARK3;
-                    STH(x3, wback, fixedaddress);
-                    #endif
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                case 2:
-                    INST_NAME("FIST Ew, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
-                    u8 = x87_setround(dyn, ninst, x1, x2, x4);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    ed = x1;
-                    s0 = fpu_get_scratch(dyn);
-                    #if 0
-                    FRINT32XD(s0, v1);
-                    // no saturation instruction on Arm, so using NEON
+                }
+                VMOVSto(x3, s0, 0);
+                MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                TBNZ_MARK2(x5, FPSR_IOC);
+                SXTHw(x5, x3);  // check if 16bits value is fine
+                SUBw_REG(x5, x5, x3);
+                CBZw_MARK3(x5);
+                MARK2;
+                MOV32w(x3, 0x8000);
+                MARK3;
+                STH(x3, wback, fixedaddress);
+                #endif
+                x87_restoreround(dyn, ninst, u8);
+                break;
+            case 3:
+                INST_NAME("FISTP Ew, ST0");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                u8 = x87_setround(dyn, ninst, x1, x2, x4);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                ed = x1;
+                s0 = fpu_get_scratch(dyn, ninst);
+                #if 0
+                FRINT32XD(s0, v1);
+                // no saturation instruction on Arm, so using NEON
+                VFCVTZSd(s0, s0);
+                SQXTN_S_D(s0, s0);
+                SQXTN_H_S(s0, s0);
+                VST16(s0, wback, fixedaddress);
+                #else
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                MSR_fpsr(x5);
+                if(ST_IS_F(0)) {
+                    FRINTXS(s0, v1);
+                    VFCVTZSs(s0, s0);
+                } else {
+                    FRINTXD(s0, v1);
                    VFCVTZSd(s0, s0);
                    SQXTN_S_D(s0, s0);
-                    SQXTN_H_S(s0, s0);
-                    VST16(s0, wback, fixedaddress);
-                    #else
-                    MRS_fpsr(x5);
-                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
-                    BFCw(x5, FPSR_QC, 1);   // reset QC bit
-                    MSR_fpsr(x5);
-                    if(ST_IS_F(0)) {
-                        FRINTXS(s0, v1);
-                        VFCVTZSs(s0, s0);
-                    } else {
-                        FRINTXD(s0, v1);
-                        VFCVTZSd(s0, s0);
-                        SQXTN_S_D(s0, s0);
-                    }
-                    VMOVSto(x3, s0, 0);
-                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
-                    TBNZ_MARK2(x5, FPSR_IOC);
-                    SXTHw(x5, x3);  // check if 16bits value is fine
-                    SUBw_REG(x5, x5, x3);
-                    CBZw_MARK3(x5);
-                    MARK2;
-                    MOV32w(x3, 0x8000);
-                    MARK3;
-                    STH(x3, wback, fixedaddress);
-                    #endif
-                    x87_restoreround(dyn, ninst, u8);
-                    break;
-                case 3:
-                    INST_NAME("FISTP Ew, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
-                    u8 = x87_setround(dyn, ninst, x1, x2, x4);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
-                    ed = x1;
-                    s0 = fpu_get_scratch(dyn);
-                    #if 0
-                    FRINT32XD(s0, v1);
-                    // no saturation instruction on Arm, so using NEON
-                    VFCVTZSd(s0, s0);
-                    SQXTN_S_D(s0, s0);
-                    SQXTN_H_S(s0, s0);
-                    VST16(s0, wback, fixedaddress);
-                    #else
-                    MRS_fpsr(x5);
-                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
-                    MSR_fpsr(x5);
-                    if(ST_IS_F(0)) {
-                        FRINTXS(s0, v1);
-                        VFCVTZSs(s0, s0);
-                    } else {
-                        FRINTXD(s0, v1);
-                        VFCVTZSd(s0, s0);
-                        SQXTN_S_D(s0, s0);
-                    }
-                    VMOVSto(x3, s0, 0);
-                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
-                    TBNZ_MARK2(x5, FPSR_IOC);
-                    SXTHw(x5, x3);  // check if 16bits value is fine
-                    SUBw_REG(x5, x5, x3);
-                    CBZw_MARK3(x5);
-                    MARK2;
-                    MOV32w(x3, 0x8000);
-                    MARK3;
-                    STH(x3, wback, fixedaddress);
-                    #endif
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    x87_restoreround(dyn, ninst, u8);
-                    break;
-                case 4:
-                    INST_NAME("FBLD ST0, tbytes");
-                    X87_PUSH_EMPTY_OR_FAIL(dyn, ninst, x1);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
-                    if(ed!=x1) {MOVx_REG(x1, ed);}
-                    CALL(fpu_fbld, -1);
-                    break;
-                case 5:
-                    INST_NAME("FILD ST0, i64");
-                    X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, NEON_CACHE_ST_I64);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    VLD64(v1, wback, fixedaddress);
-                    if(!ST_IS_I64(0)) {
-                        if(rex.is32bits) {
-                            // need to also feed the STll stuff...
-                            ADDx_U12(x4, xEmu, offsetof(x64emu_t, fpu_ll));
-                            LDRw_U12(x1, xEmu, offsetof(x64emu_t, top));
-                            int a = 0 - dyn->n.x87stack;
-                            if(a) {
-                                if(a<0) {
-                                    SUBw_U12(x1, x1, -a);
-                                } else {
-                                    ADDw_U12(x1, x1, a);
-                                }
-                                ANDw_mask(x1, x1, 0, 2); //mask=7
+                }
+                VMOVSto(x3, s0, 0);
+                MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                TBNZ_MARK2(x5, FPSR_IOC);
+                SXTHw(x5, x3);  // check if 16bits value is fine
+                SUBw_REG(x5, x5, x3);
+                CBZw_MARK3(x5);
+                MARK2;
+                MOV32w(x3, 0x8000);
+                MARK3;
+                STH(x3, wback, fixedaddress);
+                #endif
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                x87_restoreround(dyn, ninst, u8);
+                break;
+            case 4:
+                INST_NAME("FBLD ST0, tbytes");
+                X87_PUSH_EMPTY_OR_FAIL(dyn, ninst, x1);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                if(ed!=x1) {MOVx_REG(x1, ed);}
+                s0 = x87_stackcount(dyn, ninst, x3);
+                CALL(fpu_fbld, -1);
+                x87_unstackcount(dyn, ninst, x3, s0);
+                break;
+            case 5:
+                INST_NAME("FILD ST0, i64");
+                X87_PUSH_OR_FAIL(v1, dyn, ninst, x1, NEON_CACHE_ST_I64);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v1, wback, fixedaddress);
+                if(!ST_IS_I64(0)) {
+                    if(rex.is32bits) {
+                        // need to also feed the STll stuff...
+                        ADDx_U12(x4, xEmu, offsetof(x64emu_t, fpu_ll));
+                        LDRw_U12(x1, xEmu, offsetof(x64emu_t, top));
+                        int a = 0 - dyn->n.x87stack;
+                        if(a) {
+                            if(a<0) {
+                                SUBw_U12(x1, x1, -a);
+                            } else {
+                                ADDw_U12(x1, x1, a);
                            }
-                            ADDx_REG_LSL(x1, x4, x1, 4);    // fpu_ll is 2 i64
-                            VSTR64_U12(v1, x1, 8);  // ll
-                        }
-                        SCVTFDD(v1, v1);
-                        if(rex.is32bits) {
-                            VSTR64_U12(v1, x1, 0);  // ref
+                            ANDw_mask(x1, x1, 0, 2); //mask=7
                        }
+                        ADDx_REG_LSL(x1, x4, x1, 4);    // fpu_ll is 2 i64
+                        VSTR64_U12(v1, x1, 8);  // ll
                    }
-                    break;
-                case 6:
-                    INST_NAME("FBSTP tbytes, ST0");
-                    i1 = x87_stackcount(dyn, ninst, x1);
-                    x87_forget(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
-                    if(ed!=x1) {MOVx_REG(x1, ed);}
-                    CALL(fpu_fbst, -1);
-                    x87_unstackcount(dyn, ninst, x1, i1);
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                case 7:
-                    INST_NAME("FISTP i64, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_I64);
-                    if(!ST_IS_I64(0)) {
-                        u8 = x87_setround(dyn, ninst, x1, x2, x4);
+                    SCVTFDD(v1, v1);
+                    if(rex.is32bits) {
+                        VSTR64_U12(v1, x1, 0);  // ref
                    }
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                    ed = x1;
-                    s0 = fpu_get_scratch(dyn);
-                    if(ST_IS_I64(0)) {
-                        VST64(v1, wback, fixedaddress);
-                    } else {
-                        #if 0
-                        FRINT64XD(s0, v1);
-                        VFCVTZSd(s0, s0);
-                        VSTR64_U12(s0, wback, fixedaddress);
-                        #else
-                        if(rex.is32bits) {
-                            // need to check STll first...
-                            ADDx_U12(x5, xEmu, offsetof(x64emu_t, fpu_ll));
-                            LDRw_U12(x1, xEmu, offsetof(x64emu_t, top));
-                            VMOVQDto(x3, v1, 0);
-                            int a = 0 - dyn->n.x87stack;
-                            if(a) {
-                                if(a<0) {
-                                    SUBw_U12(x1, x1, -a);
-                                } else {
-                                    ADDw_U12(x1, x1, a);
-                                }
-                                ANDw_mask(x1, x1, 0, 2); //mask=7
+                }
+                break;
+            case 6:
+                INST_NAME("FBSTP tbytes, ST0");
+                i1 = x87_stackcount(dyn, ninst, x1);
+                x87_forget(dyn, ninst, x1, x2, 0);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                if(ed!=x1) {MOVx_REG(x1, ed);}
+                CALL(fpu_fbst, -1);
+                x87_unstackcount(dyn, ninst, x1, i1);
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            case 7:
+                INST_NAME("FISTP i64, ST0");
+                v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_I64);
+                if(!ST_IS_I64(0)) {
+                    u8 = x87_setround(dyn, ninst, x1, x2, x4);
+                }
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                ed = x1;
+                s0 = fpu_get_scratch(dyn, ninst);
+                if(ST_IS_I64(0)) {
+                    VST64(v1, wback, fixedaddress);
+                } else {
+                    #if 0
+                    FRINT64XD(s0, v1);
+                    VFCVTZSd(s0, s0);
+                    VSTR64_U12(s0, wback, fixedaddress);
+                    #else
+                    if(rex.is32bits) {
+                        // need to check STll first...
+                        ADDx_U12(x5, xEmu, offsetof(x64emu_t, fpu_ll));
+                        LDRw_U12(x1, xEmu, offsetof(x64emu_t, top));
+                        VMOVQDto(x3, v1, 0);
+                        int a = 0 - dyn->n.x87stack;
+                        if(a) {
+                            if(a<0) {
+                                SUBw_U12(x1, x1, -a);
+                            } else {
+                                ADDw_U12(x1, x1, a);
                            }
-                            ADDx_REG_LSL(x1, x5, x1, 4);    // fpu_ll is 2 i64
-                            LDRx_U12(x5, x1, 0);  // ref
-                            SUBx_REG(x5, x5, x3);
-                            CBNZx_MARK2(x5);
-                            LDRx_U12(x5, x1, 8);  // ll
-                            STx(x5, wback, fixedaddress);
-                            B_MARK3(c__);
-                            MARK2;
+                            ANDw_mask(x1, x1, 0, 2); //mask=7
                        }
-                        MRS_fpsr(x5);
-                        BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
-                        MSR_fpsr(x5);
-                        FRINTXD(s0, v1);
-                        VFCVTZSd(s0, s0);
-                        VST64(s0, wback, fixedaddress);
-                        MRS_fpsr(x5);   // get back FPSR to check the IOC bit
-                        TBZ_MARK3(x5, FPSR_IOC);
-                        ORRx_mask(x5, xZR, 1, 1, 0);    //0x8000000000000000
+                        ADDx_REG_LSL(x1, x5, x1, 4);    // fpu_ll is 2 i64
+                        LDRx_U12(x5, x1, 0);  // ref
+                        SUBx_REG(x5, x5, x3);
+                        CBNZx_MARK2(x5);
+                        LDRx_U12(x5, x1, 8);  // ll
                        STx(x5, wback, fixedaddress);
-                        MARK3;
-                        #endif
-                        x87_restoreround(dyn, ninst, u8);
+                        B_MARK3(c__);
+                        MARK2;
                    }
-                    X87_POP_OR_FAIL(dyn, ninst, x3);
-                    break;
-                default:
-                    DEFAULT;
-            }
-    }
+                    MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    FRINTXD(s0, v1);
+                    VFCVTZSd(s0, s0);
+                    VST64(s0, wback, fixedaddress);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
+                    ORRx_mask(x5, xZR, 1, 1, 0);    //0x8000000000000000
+                    STx(x5, wback, fixedaddress);
+                    MARK3;
+                    #endif
+                    x87_restoreround(dyn, ninst, u8);
+                }
+                X87_POP_OR_FAIL(dyn, ninst, x3);
+                break;
+            default:
+                DEFAULT;
+        }
    return addr;
 }
@@ -19,7 +19,7 @@
 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"

 // emit OR32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_or32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
@@ -34,52 +34,93 @@ void emit_or32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3,
    IFX(X_PEND) {
        STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
    }
-    IFX(X_CF | X_AF | X_OF) {
-        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
-        BICw(xFlags, xFlags, s3);
+    int need_tst = 0;
+    IFX(X_ZF) need_tst = 1;
+    IFXNATIVE(X_SF, NF_SF) need_tst = 1;
+    IFXNATIVE(X_OF, NF_VF) need_tst = 1;
+    IFXNATIVE(X_CF, NF_CF) need_tst = 1;
+    if(need_tst) TSTxw_REG(s1, s1);
+    IFX(X_CF) {
+        IFNATIVE(NF_CF) {} else {
+            BFCw(xFlags, F_CF, 1);
+        }
+    }
+    IFX(X_OF) {
+        IFNATIVE(NF_VF) {} else {
+            BFCw(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
    }
    IFX(X_ZF) {
-        TSTxw_REG(s1, s1);
-        CSETw(s3, cEQ);
-        BFIw(xFlags, s3, F_ZF, 1);
+        IFNATIVE(NF_EQ) {} else {
+            CSETw(s3, cEQ);
+            BFIw(xFlags, s3, F_ZF, 1);
+        }
    }
    IFX(X_SF) {
-        LSRxw(s3, s1, (rex.w)?63:31);
-        BFIw(xFlags, s3, F_SF, 1);
+        IFNATIVE(NF_SF) {} else {
+            LSRxw(s3, s1, (rex.w)?63:31);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

 // emit OR32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
 void emit_or32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int s3, int s4)
 {
+    int mask = convert_bitmask_xw(c);
+    if(!mask) {
+        MOV64xw(s3, c);
+        emit_or32(dyn, ninst, rex, s1, s3, s3, s4);
+        return;
+    }
    IFX(X_PEND) {
        SET_DF(s4, rex.w?d_or64:d_or32);
    } else IFX(X_ALL) {
        SET_DFNONE(s4);
    }
-    MOV64xw(s3, c);
-    ORRxw_REG(s1, s1, s3);
+    ORRxw_mask(s1, s1, (mask>>12)&1, mask&0x3F, (mask>>6)&0x3F);
    IFX(X_PEND) {
        STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
    }
-    IFX(X_CF | X_AF | X_OF) {
-        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
-        BICw(xFlags, xFlags, s3);
+    int need_tst = 0;
+    IFX(X_ZF) need_tst = 1;
+    IFXNATIVE(X_SF, NF_SF) need_tst = 1;
+    IFXNATIVE(X_OF, NF_VF) need_tst = 1;
+    IFXNATIVE(X_CF, NF_CF) need_tst = 1;
+    if(need_tst) TSTxw_REG(s1, s1);
+    IFX(X_CF) {
+        IFNATIVE(NF_CF) {} else {
+            BFCw(xFlags, F_CF, 1);
+        }
+    }
+    IFX(X_OF) {
+        IFNATIVE(NF_VF) {} else {
+            BFCw(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
    }
    IFX(X_ZF) {
-        TSTxw_REG(s1, s1);
-        CSETw(s3, cEQ);
-        BFIw(xFlags, s3, F_ZF, 1);
+        IFNATIVE(NF_EQ) {} else {
+            CSETw(s3, cEQ);
+            BFIw(xFlags, s3, F_ZF, 1);
+        }
    }
    IFX(X_SF) {
-        LSRxw(s3, s1, (rex.w)?63:31);
-        BFIw(xFlags, s3, F_SF, 1);
+        IFNATIVE(NF_SF) {} else {
+            LSRxw(s3, s1, (rex.w)?63:31);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

@@ -96,52 +137,93 @@ void emit_xor32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
    IFX(X_PEND) {
        STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
    }
-    IFX(X_CF | X_AF | X_OF) {
-        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
-        BICw(xFlags, xFlags, s3);
+    int need_tst = 0;
+    IFX(X_ZF) need_tst = 1;
+    IFXNATIVE(X_SF, NF_SF) need_tst = 1;
+    IFXNATIVE(X_OF, NF_VF) need_tst = 1;
+    IFXNATIVE(X_CF, NF_CF) need_tst = 1;
+    if(need_tst) TSTxw_REG(s1, s1);
+    IFX(X_CF) {
+        IFNATIVE(NF_CF) {} else {
+            BFCw(xFlags, F_CF, 1);
+        }
+    }
+    IFX(X_OF) {
+        IFNATIVE(NF_VF) {} else {
+            BFCw(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
    }
    IFX(X_ZF) {
-        TSTxw_REG(s1, s1);
-        CSETw(s3, cEQ);
-        BFIw(xFlags, s3, F_ZF, 1);
+        IFNATIVE(NF_EQ) {} else {
+            CSETw(s3, cEQ);
+            BFIw(xFlags, s3, F_ZF, 1);
+        }
    }
    IFX(X_SF) {
-        LSRxw(s3, s1, (rex.w)?63:31);
-        BFIw(xFlags, s3, F_SF, 1);
+        IFNATIVE(NF_SF) {} else {
+            LSRxw(s3, s1, (rex.w)?63:31);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

 // emit XOR32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
 void emit_xor32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int s3, int s4)
 {
+    int mask = convert_bitmask_xw(c);
+    if(!mask) {
+        MOV64xw(s3, c);
+        emit_xor32(dyn, ninst, rex, s1, s3, s3, s4);
+        return;
+    }
    IFX(X_PEND) {
        SET_DF(s4, rex.w?d_xor64:d_xor32);
    } else IFX(X_ALL) {
        SET_DFNONE(s4);
    }
-    MOV64xw(s3, c);
-    EORxw_REG(s1, s1, s3);
+    EORxw_mask(s1, s1, (mask>>12)&1, mask&0x3F, (mask>>6)&0x3F);
    IFX(X_PEND) {
        STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
    }
-    IFX(X_CF | X_AF | X_OF) {
-        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
-        BICw(xFlags, xFlags, s3);
+    int need_tst = 0;
+    IFX(X_ZF) need_tst = 1;
+    IFXNATIVE(X_SF, NF_SF) need_tst = 1;
+    IFXNATIVE(X_OF, NF_VF) need_tst = 1;
+    IFXNATIVE(X_CF, NF_CF) need_tst = 1;
+    if(need_tst) TSTxw_REG(s1, s1);
+    IFX(X_CF) {
+        IFNATIVE(NF_CF) {} else {
+            BFCw(xFlags, F_CF, 1);
+        }
+    }
+    IFX(X_OF) {
+        IFNATIVE(NF_VF) {} else {
+            BFCw(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
    }
    IFX(X_ZF) {
-        TSTxw_REG(s1, s1);
-        CSETw(s3, cEQ);
-        BFIw(xFlags, s3, F_ZF, 1);
+        IFNATIVE(NF_EQ) {} else {
+            CSETw(s3, cEQ);
+            BFIw(xFlags, s3, F_ZF, 1);
+        }
    }
    IFX(X_SF) {
-        LSRxw(s3, s1, (rex.w)?63:31);
-        BFIw(xFlags, s3, F_SF, 1);
+        IFNATIVE(NF_SF) {} else {
+            LSRxw(s3, s1, (rex.w)?63:31);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

@@ -154,7 +236,7 @@ void emit_and32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
    } else IFX(X_ALL) {
        SET_DFNONE(s4);
    }
-    IFX(X_ZF) {
+    IFX(X_ZF|X_SF|X_CF|X_OF) {
        ANDSxw_REG(s1, s1, s2);
    } else {
        ANDxw_REG(s1, s1, s2);
@@ -162,54 +244,85 @@ void emit_and32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
    IFX(X_PEND) {
        STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
    }
-    IFX(X_CF | X_AF | X_OF) {
-        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
-        BICw(xFlags, xFlags, s3);
+    IFX(X_CF) {
+        IFNATIVE(NF_CF) {} else {
+            BFCw(xFlags, F_CF, 1);
+        }
+    }
+    IFX(X_OF) {
+        IFNATIVE(NF_VF) {} else {
+            BFCw(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
    }
    IFX(X_ZF) {
-        CSETw(s3, cEQ);
-        BFIw(xFlags, s3, F_ZF, 1);
+        IFNATIVE(NF_EQ) {} else {
+            CSETw(s3, cEQ);
+            BFIw(xFlags, s3, F_ZF, 1);
+        }
    }
    IFX(X_SF) {
-        LSRxw(s3, s1, (rex.w)?63:31);
-        BFIw(xFlags, s3, F_SF, 1);
+        IFNATIVE(NF_SF) {} else {
+            LSRxw(s3, s1, (rex.w)?63:31);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

 // emit AND32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
 void emit_and32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int s3, int s4)
 {
+    int mask = convert_bitmask_xw(c);
+    if(!mask) {
+        MOV64xw(s3, c);
+        emit_and32(dyn, ninst, rex, s1, s3, s3, s4);
+        return;
+    }
    IFX(X_PEND) {
        SET_DF(s4, rex.w?d_and64:d_and32);
    } else IFX(X_ALL) {
        SET_DFNONE(s4);
    }
-    MOV64xw(s3, c);
-    IFX(X_ALL) {
-        ANDSxw_REG(s1, s1, s3);
+    IFX(X_ZF|X_SF|X_CF|X_OF) {
+        ANDSxw_mask(s1, s1, (mask>>12)&1, mask&0x3F, (mask>>6)&0x3F);
    } else {
-        ANDxw_REG(s1, s1, s3);
+        ANDxw_mask(s1, s1, (mask>>12)&1, mask&0x3F, (mask>>6)&0x3F);
    }
    IFX(X_PEND) {
        STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
    }
-    IFX(X_CF | X_AF | X_OF) {
-        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
-        BICw(xFlags, xFlags, s3);
+    IFX(X_CF) {
+        IFNATIVE(NF_CF) {} else {
+            BFCw(xFlags, F_CF, 1);
+        }
+    }
+    IFX(X_OF) {
+        IFNATIVE(NF_VF) {} else {
+            BFCw(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
    }
    IFX(X_ZF) {
-        CSETw(s3, cEQ);
-        BFIw(xFlags, s3, F_ZF, 1);
+        IFNATIVE(NF_EQ) {} else {
+            CSETw(s3, cEQ);
+            BFIw(xFlags, s3, F_ZF, 1);
+        }
    }
    IFX(X_SF) {
-        LSRxw(s3, s1, (rex.w)?63:31);
-        BFIw(xFlags, s3, F_SF, 1);
+        IFNATIVE(NF_SF) {} else {
+            LSRxw(s3, s1, (rex.w)?63:31);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

@@ -218,9 +331,9 @@ void emit_or8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
    MAYUSE(s2);
    IFX(X_PEND) {
-        SET_DF(s3, d_or8);
+        SET_DF(s4, d_or8);
    } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE(s4);
    }
    ORRw_REG(s1, s1, s2);
    IFX(X_PEND) {
@@ -232,20 +345,25 @@ void emit_or8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
    }
    COMP_ZFSF(s1, 8)
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

 // emit OR8 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
-void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4)
 {
-    MOV32w(s3, c&0xff);
+    int mask = convert_bitmask_w(c);
+    if(!mask) {
+        MOV32w(s3, c);
+        emit_or8(dyn, ninst, s1, s3, s3, s4);
+        return;
+    }
    IFX(X_PEND) {
        SET_DF(s4, d_or8);
    } else IFX(X_ALL) {
        SET_DFNONE(s4);
    }
-    ORRw_REG(s1, s1, s3);
+    ORRw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
    IFX(X_PEND) {
        STRB_U12(s1, xEmu, offsetof(x64emu_t, res));
    }
@@ -255,7 +373,7 @@ void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
    }
    COMP_ZFSF(s1, 8)
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

@@ -264,9 +382,9 @@ void emit_xor8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
    MAYUSE(s2);
    IFX(X_PEND) {
-        SET_DF(s3, d_xor8);
+        SET_DF(s4, d_xor8);
    } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE(s4);
    }
    EORx_REG(s1, s1, s2);
    IFX(X_PEND) {
@@ -278,20 +396,25 @@ void emit_xor8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
    }
    COMP_ZFSF(s1, 8)
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

 // emit XOR8 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
-void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4)
 {
-    MOV32w(s3, c&0xff);
+    int mask = convert_bitmask_w(c);
+    if(!mask) {
+        MOV32w(s3, c&0xff);
+        emit_xor8(dyn, ninst, s1, s3, s3, s4);
+        return;
+    }
    IFX(X_PEND) {
        SET_DF(s4, d_xor8);
    } else IFX(X_ALL) {
        SET_DFNONE(s4);
    }
-    EORw_REG(s1, s1, s3);
+    EORw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
    IFX(X_PEND) {
        STRB_U12(s1, xEmu, offsetof(x64emu_t, res));
    }
@@ -301,7 +424,7 @@ void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4
    }
    COMP_ZFSF(s1, 8)
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

@@ -310,9 +433,9 @@ void emit_and8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
    MAYUSE(s2);
    IFX(X_PEND) {
-        SET_DF(s3, d_and8);
+        SET_DF(s4, d_and8);
    } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE(s4);
    }
    IFX(X_ZF) {
        ANDSw_REG(s1, s1, s2);
@@ -326,32 +449,43 @@ void emit_and8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
        BICw_REG(xFlags, xFlags, s3);
    }
-    IFX(X_ZF) {
-        CSETw(s3, cEQ);
-        BFIw(xFlags, s3, F_ZF, 1);
-    }
-    IFX(X_SF) {
-        LSRw(s3, s1, 7);
-        BFIw(xFlags, s3, F_SF, 1);
+    if(arm64_flagm) {
+        COMP_ZFSF(s1, 8)
+    } else {
+        IFX(X_ZF) {
+            IFNATIVE(NF_EQ) {} else {
+                CSETw(s3, cEQ);
+                BFIw(xFlags, s3, F_ZF, 1);
+            }
+        }
+        IFX(X_SF) {
+            LSRw(s3, s1, 7);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

 // emit AND8 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
-void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, uint8_t c, int s3, int s4)
 {
-    MOV32w(s3, c&0xff);
+    int mask = convert_bitmask_w(c);
+    if(!mask) {
+        MOV32w(s3, c);
+        emit_and8(dyn, ninst, s1, s3, s3, s4);
+        return;
+    }
    IFX(X_PEND) {
        SET_DF(s4, d_and8);
    } else IFX(X_ALL) {
        SET_DFNONE(s4);
    }
    IFX(X_ZF) {
-        ANDSw_REG(s1, s1, s3);
+        ANDSw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
    } else {
-        ANDw_REG(s1, s1, s3);
+        ANDw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
    }
    IFX(X_PEND) {
        STRB_U12(s1, xEmu, offsetof(x64emu_t, res));
@@ -360,28 +494,33 @@ void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4
        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
        BICw(xFlags, xFlags, s3);
    }
-    IFX(X_ZF) {
-        CSETw(s3, cEQ);
-        BFIw(xFlags, s3, F_ZF, 1);
-    }
-    IFX(X_SF) {
-        LSRw(s3, s1, 7);
-        BFIw(xFlags, s3, F_SF, 1);
+    if(arm64_flagm) {
+        COMP_ZFSF(s1, 8)
+    } else {
+        IFX(X_ZF) {
+            IFNATIVE(NF_EQ) {} else {
+                CSETw(s3, cEQ);
+                BFIw(xFlags, s3, F_ZF, 1);
+            }
+        }
+        IFX(X_SF) {
+            LSRw(s3, s1, 7);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

-
 // emit OR16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_or16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
    MAYUSE(s2);
    IFX(X_PEND) {
-        SET_DF(s3, d_or16);
+        SET_DF(s4, d_or16);
    } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE(s4);
    }
    ORRw_REG(s1, s1, s2);
    IFX(X_PEND) {
@@ -393,64 +532,46 @@ void emit_or16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
    }
    COMP_ZFSF(s1, 16)
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

 // emit OR16 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
-//void emit_or16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
-//{
-//    IFX(X_PEND) {
-//        MOVW(s3, c);
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, op1));
-//        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
-//        SET_DF(s4, d_or16);
-//    } else IFX(X_ALL) {
-//        SET_DFNONE(s4);
-//    }
-//    if(c>=0 && c<256) {
-//        IFX(X_ALL) {
-//            ORRS_IMM8(s1, s1, c, 0);
-//        } else {
-//            ORR_IMM8(s1, s1, c, 0);
-//        }
-//    } else {
-//        IFX(X_PEND) {} else {MOVW(s3, c);}
-//        IFX(X_ALL) {
-//            ORRS_REG_LSL_IMM5(s1, s1, s3, 0);
-//        } else {
-//            ORR_REG_LSL_IMM5(s1, s1, s3, 0);
-//        }
-//    }
-//    IFX(X_PEND) {
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//    }
-//    IFX(X_CF | X_AF | X_ZF) {
-//        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF)|(1<<F_ZF), 0);
-//    }
-//    IFX(X_OF) {
-//        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
-//    }
-//    IFX(X_ZF) {
-//        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
-//    }
-//    IFX(X_SF) {
-//        MOV_REG_LSR_IMM5(s3, s1, 15);
-//        BFI(xFlags, s3, F_SF, 1);
-//    }
-//    IFX(X_PF) {
-//        emit_pf(dyn, ninst, s1, s3, s4);
-//    }
-//}
+void emit_or16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s4)
+{
+    int mask = convert_bitmask_w((uint16_t)c);
+    if(!mask) {
+        MOV32w(s3, (uint16_t)c);
+        emit_or16(dyn, ninst, s1, s3, s3, s4);
+        return;
+    }
+    IFX(X_PEND) {
+        SET_DF(s4, d_or16);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    ORRw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
+    IFX(X_PEND) {
+        STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_CF | X_AF | X_OF) {
+        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
+        BICw(xFlags, xFlags, s3);
+    }
+    COMP_ZFSF(s1, 16)
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s1, s4);
+    }
+}

 // emit XOR16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_xor16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
    MAYUSE(s2);
    IFX(X_PEND) {
-        SET_DF(s3, d_xor16);
+        SET_DF(s4, d_xor16);
    } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE(s4);
    }
    EORw_REG(s1, s1, s2);
    IFX(X_PEND) {
@@ -462,66 +583,49 @@ void emit_xor16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
    }
    COMP_ZFSF(s1, 16)
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

 // emit XOR16 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
-//void emit_xor16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
-//{
-//    IFX(X_PEND) {
-//        MOVW(s3, c);
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, op1));
-//        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
-//        SET_DF(s4, d_xor16);
-//    } else IFX(X_ALL) {
-//        SET_DFNONE(s4);
-//    }
-//    if(c>=0 && c<256) {
-//        IFX(X_ALL) {
-//            XORS_IMM8(s1, s1, c);
-//        } else {
-//            XOR_IMM8(s1, s1, c);
-//        }
-//    } else {
-//        IFX(X_PEND) {} else {MOVW(s3, c);}
-//        IFX(X_ALL) {
-//            XORS_REG_LSL_IMM5(s1, s1, s3, 0);
-//        } else {
-//            XOR_REG_LSL_IMM5(s1, s1, s3, 0);
-//        }
-//    }
-//    IFX(X_PEND) {
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//    }
-//    IFX(X_CF | X_AF | X_ZF) {
-//        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF)|(1<<F_ZF), 0);
-//    }
-//    IFX(X_OF) {
-//        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
-//    }
-//    IFX(X_ZF) {
-//        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
-//    }
-//    IFX(X_SF) {
-//        MOV_REG_LSR_IMM5(s3, s1, 15);
-//        BFI(xFlags, s3, F_SF, 1);
-//    }
-//    IFX(X_PF) {
-//        emit_pf(dyn, ninst, s1, s3, s4);
-//    }
-//}
+void emit_xor16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s4)
+{
+    int mask = convert_bitmask_w((uint16_t)c);
+    if(!mask) {
+        MOV32w(s3, (uint16_t)c);
+        emit_xor16(dyn, ninst, s1, s3, s3, s4);
+        return;
+    }
+    IFX(X_PEND) {
+        SET_DF(s4, d_xor16);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    EORw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
+    IFX(X_PEND) {
+        STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_CF | X_AF | X_OF) {
+        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
+        BICw(xFlags, xFlags, s3);
+    }
+    COMP_ZFSF(s1, 16)
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s1, s4);
+    }
+}
+

 // emit AND16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
    MAYUSE(s2);
    IFX(X_PEND) {
-        SET_DF(s3, d_and16);
+        SET_DF(s4, d_and16);
    } else IFX(X_ALL) {
-        SET_DFNONE(s3);
+        SET_DFNONE(s4);
    }
-    IFX(X_ALL) {
+    IFX(X_ZF) {
        ANDSw_REG(s1, s1, s2);
    } else {
        ANDw_REG(s1, s1, s2);
@@ -533,61 +637,66 @@ void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
        BICw_REG(xFlags, xFlags, s3);
    }
-    IFX(X_ZF) {
-        CSETw(s3, cEQ);
-        BFIw(xFlags, s3, F_ZF, 1);
-    }
-    IFX(X_SF) {
-        LSRw(s3, s1, 15);
-        BFIw(xFlags, s3, F_SF, 1);
+    if(arm64_flagm) {
+        COMP_ZFSF(s1, 16)
+    } else {
+        IFX(X_ZF) {
+            IFNATIVE(NF_EQ) {} else {
+                CSETw(s3, cEQ);
+                BFIw(xFlags, s3, F_ZF, 1);
+            }
+        }
+        IFX(X_SF) {
+            LSRw(s3, s1, 15);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

 // emit AND16 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
-//void emit_and16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
-//{
-//    IFX(X_PEND) {
-//        MOVW(s3, c);
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, op1));
-//        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
-//        SET_DF(s4, d_and16);
-//    } else IFX(X_ALL) {
-//        SET_DFNONE(s4);
-//    }
-//    if(c>=0 && c<256) {
-//        IFX(X_ALL) {
-//            ANDS_IMM8(s1, s1, c);
-//        } else {
-//            AND_IMM8(s1, s1, c);
-//        }
-//    } else {
-//        IFX(X_PEND) {} else {MOVW(s3, c);}
-//        IFX(X_ALL) {
-//            ANDS_REG_LSL_IMM5(s1, s1, s3, 0);
-//        } else {
-//            AND_REG_LSL_IMM5(s1, s1, s3, 0);
-//        }
-//    }
-//    IFX(X_PEND) {
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//    }
-//    IFX(X_CF | X_AF | X_ZF) {
-//        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF)|(1<<F_ZF), 0);
-//    }
-//    IFX(X_OF) {
-//        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
-//    }
-//    IFX(X_ZF) {
-//        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
-//    }
-//    IFX(X_SF) {
-//        MOV_REG_LSR_IMM5(s3, s1, 15);
-//        BFI(xFlags, s3, F_SF, 1);
-//    }
-//    IFX(X_PF) {
-//        emit_pf(dyn, ninst, s1, s3, s4);
-//    }
-//}
+void emit_and16c(dynarec_arm_t* dyn, int ninst, int s1, int16_t c, int s3, int s4)
+{
+    int mask = convert_bitmask_w((uint16_t)c);
+    if(!mask) {
+        MOV32w(s3, (uint16_t)c);
+        emit_and16(dyn, ninst, s1, s3, s3, s4);
+        return;
+    }
+    IFX(X_PEND) {
+        SET_DF(s4, d_and16);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    IFX(X_ZF) {
+        ANDSw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
+    } else {
+        ANDw_mask(s1, s1, mask&0x3F, (mask>>6)&0x3F);
+    }
+    IFX(X_PEND) {
+        STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_CF | X_AF | X_OF) {
+        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
+        BICw(xFlags, xFlags, s3);
+    }
+    if(arm64_flagm) {
+        COMP_ZFSF(s1, 16)
+    } else {
+        IFX(X_ZF) {
+            IFNATIVE(NF_EQ) {} else {
+                CSETw(s3, cEQ);
+                BFIw(xFlags, s3, F_ZF, 1);
+            }
+        }
+        IFX(X_SF) {
+            LSRw(s3, s1, 15);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
+    }
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s1, s4);
+    }
+}
@@ -19,7 +19,7 @@
 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"

 // emit CMP32 instruction, from cmp s1, s2, using s3 and s4 as scratch
 void emit_cmp32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4, int s5)
@@ -47,24 +47,34 @@ void emit_cmp32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
        BFIx(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
    }
    IFX(X_ZF) {
-        CSETw(s4, cEQ);
-        BFIw(xFlags, s4, F_ZF, 1);
+        IFNATIVE(NF_EQ) {} else {
+            CSETw(s4, cEQ);
+            BFIw(xFlags, s4, F_ZF, 1);
+        }
    }
    IFX(X_CF) {
        // inverted carry
-        CSETw(s4, cCC);
-        BFIw(xFlags, s4, F_CF, 1);
+        IFNATIVE(NF_CF) {
+            GEN_INVERTED_CARRY();
+        } else {
+            CSETw(s4, cCC);
+            BFIw(xFlags, s4, F_CF, 1);
+        }
    }
    IFX(X_OF) {
-        CSETw(s4, cVS);
-        BFIw(xFlags, s4, F_OF, 1);
+        IFNATIVE(NF_VF) {} else {
+            CSETw(s4, cVS);
+            BFIw(xFlags, s4, F_OF, 1);
+        }
    }
    IFX(X_SF) {
-        LSRxw(s3, s5, (rex.w)?63:31);
-        BFIw(xFlags, s3, F_SF, 1);
+        IFNATIVE(NF_SF) {} else {
+            LSRxw(s3, s5, (rex.w)?63:31);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s5, s3, s4);
+        emit_pf(dyn, ninst, s5, s4);
    }
 }

@@ -83,20 +93,35 @@ void emit_cmp32_0(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int
    SUBSxw_U12(s3, s1, 0);   // res = s1 - 0
    // and now the tricky ones (and mostly unused), PF and AF
    // bc = (res & (~d | s)) | (~d & s) => is 0 here...
-    IFX(X_OF|X_AF|X_CF) {
-        MOV32w(s4, (1<<F_OF)|(1<<F_AF)|(1<<F_CF));
-        BICw(xFlags, xFlags, s4);
+    IFX(X_CF) {
+        IFNATIVE(NF_CF) {
+            GEN_INVERTED_CARRY();
+        } else {
+            BFCw(xFlags, F_CF, 1);
+        }
+    }
+    IFX(X_OF) {
+        IFNATIVE(NF_VF) {} else {
+            BFCw(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
    }
    IFX(X_ZF) {
-        CSETw(s4, cEQ);
-        BFIw(xFlags, s4, F_ZF, 1);
+        IFNATIVE(NF_EQ) {} else {
+            CSETw(s4, cEQ);
+            BFIw(xFlags, s4, F_ZF, 1);
+        }
    }
    IFX(X_SF) {
-        LSRxw(s3, s1, (rex.w)?63:31);
-        BFIw(xFlags, s3, F_SF, 1);
+        IFNATIVE(NF_SF) {} else {
+            LSRxw(s3, s1, (rex.w)?63:31);
+            BFIw(xFlags, s3, F_SF, 1);
+        }
    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

@@ -111,34 +136,63 @@ void emit_cmp16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, i
    } else {
        SET_DFNONE(s3);
    }
-    SUBw_REG(s5, s1, s2);   // res = s1 - s2
+    IFX(X_AF) {
+        ORNw_REG(s3, s2, s1);  // s3 = ~op1 | op2
+        BICw(s4, s2, s1);      // s4 = ~op1 & op2
+    }
+    IFX(X_CF|X_ZF|X_SF|X_OF) {
+        LSLw(s5, s1, 16);
+        SUBSw_REG_LSL(s5, s5, s2, 16);
+        IFX(X_AF) {
+            ANDw_REG_LSR(s3, s3, s5, 16);   // s3 = (~op1 | op2) & res
+            ORRw_REG(s3, s3, s4);   // s3 = (~op1 & op2) | ((~op1 | op2) & res)
+            LSRw(s4, s3, 3);
+            BFIx(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
+        }
+        IFX(X_ZF) {
+            IFNATIVE(NF_EQ) {} else {
+                CSETw(s4, cEQ);
+                BFIw(xFlags, s4, F_ZF, 1);
+            }
+        }
+        IFX(X_CF) {
+            // inverted carry
+            IFNATIVE(NF_CF) {
+                GEN_INVERTED_CARRY();
+            } else {
+                CSETw(s4, cCC);
+                BFIw(xFlags, s4, F_CF, 1);
+            }
+        }
+        IFX(X_OF) {
+            IFNATIVE(NF_VF) {} else {
+                CSETw(s4, cVS);
+                BFIw(xFlags, s4, F_OF, 1);
+            }
+        }
+        IFX(X_SF) {
+            IFNATIVE(NF_SF) {} else {
+                CSETw(s4, cMI);
+                BFIw(xFlags, s4, F_SF, 1);
+            }
+        }
+        IFX(X_PF|X_PEND) {
+            LSRw(s5, s5, 16);
+        }
+    } else {
+        SUBw_REG(s5, s1, s2);   // res = s1 - s2
+        IFX(X_AF) {
+            ANDw_REG(s3, s3, s5);   // s3 = (~op1 | op2) & res
+            ORRw_REG(s3, s3, s4);   // s3 = (~op1 & op2) | ((~op1 | op2) & res)
+            LSRw(s4, s3, 3);
+            BFIx(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
+        }
+    }
    IFX_PENDOR0 {
        STRH_U12(s5, xEmu, offsetof(x64emu_t, res));
    }
-    COMP_ZFSF(s5, 16)
-    // bc = (res & (~d | s)) | (~d & s)
-    IFX(X_CF|X_AF|X_OF) {
-        MVNw_REG(s4, s1);        // s4 = ~d
-        ORRw_REG(s4, s4, s2);    // s4 = ~d | s
-        ANDw_REG(s4, s4, s5);    // s4 = res & (~d | s)
-        BICw_REG(s3, s2, s1);    // s3 = s & ~d
-        ORRw_REG(s3, s4, s3);    // s3 = (res & (~d | s)) | (s & ~d)
-        IFX(X_CF) {
-            LSRw(s4, s3, 15);
-            BFIw(xFlags, s4, F_CF, 1);    // CF : bc & 0x8000
-        }
-        IFX(X_AF) {
-            LSRw(s4, s3, 3);
-            BFIw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
-        }
-        IFX(X_OF) {
-            LSRw(s4, s3, 14);
-            EORw_REG_LSR(s4, s4, s4, 1);
-            BFIw(xFlags, s4, F_OF, 1);    // OF: ((bc >> 14) ^ ((bc>>14)>>1)) & 1
-        }
-    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s5, s3, s4);
+        emit_pf(dyn, ninst, s5, s4);
    }
 }

@@ -161,7 +215,7 @@ void emit_cmp16_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
    }
    COMP_ZFSF(s1, 16)
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }
 // emit CMP8 instruction, from cmp s1, s2, using s3 and s4 as scratch
@@ -171,37 +225,67 @@ void emit_cmp8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, in
    IFX_PENDOR0 {
        STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
        STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
-        SET_DF(s4, d_cmp8);
+        SET_DF(s3, d_cmp8);
    } else {
-        SET_DFNONE(s4);
+        SET_DFNONE(s3);
+    }
+    IFX(X_AF) {
+        ORNw_REG(s3, s2, s1);  // s3 = ~op1 | op2
+        BICw(s4, s2, s1);      // s4 = ~op1 & op2
+    }
+    IFX(X_CF|X_ZF|X_SF|X_OF) {
+        LSLw(s5, s1, 24);
+        SUBSw_REG_LSL(s5, s5, s2, 24);
+        IFX(X_AF) {
+            ANDw_REG_LSR(s3, s3, s5, 24);   // s3 = (~op1 | op2) & res
+            ORRw_REG(s3, s3, s4);   // s3 = (~op1 & op2) | ((~op1 | op2) & res)
+            LSRw(s4, s3, 3);
+            BFIx(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
+        }
+        IFX(X_ZF) {
+            IFNATIVE(NF_EQ) {} else {
+                CSETw(s4, cEQ);
+                BFIw(xFlags, s4, F_ZF, 1);
+            }
+        }
+        IFX(X_CF) {
+            // inverted carry
+            IFNATIVE(NF_CF) {
+                GEN_INVERTED_CARRY();
+            } else {
+                CSETw(s4, cCC);
+                BFIw(xFlags, s4, F_CF, 1);
+            }
+        }
+        IFX(X_OF) {
+            IFNATIVE(NF_VF) {} else {
+                CSETw(s4, cVS);
+                BFIw(xFlags, s4, F_OF, 1);
+            }
+        }
+        IFX(X_SF) {
+            IFNATIVE(NF_SF) {} else {
+                CSETw(s4, cMI);
+                BFIw(xFlags, s4, F_SF, 1);
+            }
+        }
+        IFX(X_PF|X_PEND) {
+            LSRw(s5, s5, 24);
+        }
+    } else {
+        SUBw_REG(s5, s1, s2);   // res = s1 - s2
+        IFX(X_AF) {
+            ANDw_REG(s3, s3, s5);   // s3 = (~op1 | op2) & res
+            ORRw_REG(s3, s3, s4);   // s3 = (~op1 & op2) | ((~op1 | op2) & res)
+            LSRw(s4, s3, 3);
+            BFIx(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
+        }
    }
-    SUBw_REG(s5, s1, s2);   // res = s1 - s2
    IFX_PENDOR0 {
        STRB_U12(s5, xEmu, offsetof(x64emu_t, res));
    }
-    COMP_ZFSF(s5, 8)
-    // bc = (res & (~d | s)) | (~d & s)
-    IFX(X_CF|X_AF|X_OF) {
-        ORNw_REG(s4, s2, s1);   // s4 = ~d | s
-        ANDw_REG(s4, s4, s5);   // s4 = res & (~d | s)
-        BICw_REG(s3, s2, s1);   // s3 = s & ~d
-        ORRw_REG(s3, s4, s3);   // s3 = (res & (~d | s)) | (s & ~d)
-        IFX(X_CF) {
-            LSRw(s4, s3, 7);
-            BFIw(xFlags, s4, F_CF, 1);    // CF : bc & 0x80
-        }
-        IFX(X_AF) {
-            LSRw(s4, s3, 3);
-            BFIw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
-        }
-        IFX(X_OF) {
-            LSRw(s4, s3, 6);
-            EORw_REG_LSR(s4, s4, s4, 1);
-            BFIw(xFlags, s4, F_OF, 1);    // OF: ((bc >> 6) ^ ((bc>>6)>>1)) & 1
-        }
-    }
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s5, s3, s4);
+        emit_pf(dyn, ninst, s5, s4);
    }
 }
 // emit CMP8 instruction, from cmp s1 , 0, using s3 and s4 as scratch
@@ -223,7 +307,7 @@ void emit_cmp8_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
    }
    COMP_ZFSF(s1, 8)
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
+        emit_pf(dyn, ninst, s1, s4);
    }
 }

@@ -236,25 +320,86 @@ void emit_test32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s
    } else {
        SET_DFNONE(s4);
    }
-    IFX(X_CF | X_AF | X_OF) {
-        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
-        BICw(xFlags, xFlags, s3);
+    IFX(X_CF) {
+        IFNATIVE(NF_CF) {} else {
+            BFCw(xFlags, F_CF, 1);
+        }
+    }
+    IFX(X_OF) {
+        IFNATIVE(NF_VF) {} else {
+            BFCw(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
    }
    ANDSxw_REG(s3, s1, s2);   // res = s1 & s2
    IFX_PENDOR0 {
        STRxw_U12(s3, xEmu, offsetof(x64emu_t, res));
    }
    IFX(X_ZF) {
-        CSETw(s4, cEQ);
-        BFIw(xFlags, s4, F_ZF, 1);
+        IFNATIVE(NF_EQ) {} else {
+            CSETw(s4, cEQ);
+            BFIw(xFlags, s4, F_ZF, 1);
+        }
    }
    IFX(X_SF) {
-        LSRxw(s4, s3, rex.w?63:31);
-        BFIw(xFlags, s4, F_SF, 1);
+        IFNATIVE(NF_SF) {} else {
+            LSRxw(s4, s3, rex.w?63:31);
+            BFIw(xFlags, s4, F_SF, 1);
+        }
    }
-    // PF: (((emu->x64emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s3, s4, s5);
+        emit_pf(dyn, ninst, s3, s5);
+    }
+}
+
+// emit TEST32 instruction, from test s1, s2, using s3, s4 and s5 as scratch
+void emit_test32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int s3, int s4, int s5)
+{
+    MAYUSE(s1); MAYUSE(s3); MAYUSE(s4);
+    int mask = convert_bitmask_xw(c);
+    IFX_PENDOR0 {
+        SET_DF(s3, rex.w?d_tst64:d_tst32);
+    } else {
+        SET_DFNONE(s4);
+    }
+    IFX(X_CF) {
+        IFNATIVE(NF_CF) {} else {
+            BFCw(xFlags, F_CF, 1);
+        }
+    }
+    IFX(X_OF) {
+        IFNATIVE(NF_VF) {} else {
+            BFCw(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
+    }
+    if(mask) {
+        ANDSxw_mask(s3, s1, (mask>>12)&1, mask&0x3F, (mask>>6)&0x3F);
+    } else {
+        MOV64xw(s3, c);
+        ANDSxw_REG(s3, s1, s3);   // res = s1 & s2
+    }
+    IFX_PENDOR0 {
+        STRxw_U12(s3, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_ZF) {
+        IFNATIVE(NF_EQ) {} else {
+            CSETw(s4, cEQ);
+            BFIw(xFlags, s4, F_ZF, 1);
+        }
+    }
+    IFX(X_SF) {
+        IFNATIVE(NF_SF) {} else {
+            LSRxw(s4, s3, rex.w?63:31);
+            BFIw(xFlags, s4, F_SF, 1);
+        }
+    }
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s3, s5);
    }
 }

@@ -267,25 +412,101 @@ void emit_test16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4,
    } else {
        SET_DFNONE(s4);
    }
-    IFX(X_CF | X_AF | X_OF) {
-        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
-        BICw(xFlags, xFlags, s3);
+    IFX(X_CF|X_ZF|X_SF|X_OF) {
+        LSLw(s5, s1, 16);
+        ANDSw_REG_LSL(s5, s5, s2, 16);
+        IFX(X_ZF) {
+            IFNATIVE(NF_EQ) {} else {
+                CSETw(s4, cEQ);
+                BFIw(xFlags, s4, F_ZF, 1);
+            }
+        }
+        IFX(X_CF) {
+            IFNATIVE(NF_CF) {} else {BFCw(xFlags, F_CF, 1);}
+        }
+        IFX(X_OF) {
+            IFNATIVE(NF_VF) {} else {BFCw(xFlags, F_OF, 1);}
+        }
+        IFX(X_SF) {
+            IFNATIVE(NF_SF) {} else {
+                CSETw(s4, cMI);
+                BFIw(xFlags, s4, F_SF, 1);
+            }
+        }
+        IFX(X_PF|X_PEND) {
+            LSRw(s5, s5, 16);
+        }
+    } else {
+        ANDw_REG(s5, s1, s2);   // res = s1 & s2
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
    }
-    ANDSw_REG(s5, s1, s2);   // res = s1 & s2
    IFX_PENDOR0 {
        STRH_U12(s5, xEmu, offsetof(x64emu_t, res));
    }
-    IFX(X_ZF) {
-        CSETw(s4, cEQ);
-        BFIw(xFlags, s4, F_ZF, 1);
-    }
-    IFX(X_SF) {
-        LSRw(s4, s5, 15);
-        BFIw(xFlags, s4, F_SF, 1);
-    }
-    // PF: (((emu->x64emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s5, s3, s4);
+        emit_pf(dyn, ninst, s5, s4);
+    }
+}
+
+// emit TEST16 instruction, from test s1, s2, using s3, s4 and s5 as scratch
+void emit_test16c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s4, int s5)
+{
+    MAYUSE(s1);
+    int mask = 0;
+    IFX_PENDOR0 {
+        SET_DF(s3, d_tst16);
+    } else {
+        SET_DFNONE(s4);
+    }
+    IFX(X_CF|X_ZF|X_SF|X_OF) {
+        LSLw(s5, s1, 16);
+        mask = convert_bitmask_w(c<<16);
+        if(mask) {
+            ANDSw_mask(s5, s5, mask&0x3F, (mask>>6)&0x3F);
+        } else {
+            MOV32w(s3, c);
+            ANDSw_REG_LSL(s5, s5, s3, 16);
+        }
+        IFX(X_ZF) {
+            IFNATIVE(NF_EQ) {} else {
+                CSETw(s4, cEQ);
+                BFIw(xFlags, s4, F_ZF, 1);
+            }
+        }
+        IFX(X_CF) {
+            IFNATIVE(NF_CF) {} else {BFCw(xFlags, F_CF, 1);}
+        }
+        IFX(X_OF) {
+            IFNATIVE(NF_VF) {} else {BFCw(xFlags, F_OF, 1);}
+        }
+        IFX(X_SF) {
+            IFNATIVE(NF_SF) {} else {
+                CSETw(s4, cMI);
+                BFIw(xFlags, s4, F_SF, 1);
+            }
+        }
+        IFX(X_PF|X_PEND) {
+            LSRw(s5, s5, 16);
+        }
+    } else {
+        mask = convert_bitmask_w(c);
+        if(mask) {
+            ANDw_mask(s5, s1, mask&0x3F, (mask>>6)&0x3F);
+        } else {
+            MOV32w(s5, c);
+            ANDw_REG(s5, s1, s5);   // res = s1 & s2
+        }
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
+    }
+    IFX_PENDOR0 {
+        STRH_U12(s5, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s5, s4);
    }
 }

@@ -298,24 +519,100 @@ void emit_test8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, i
    } else {
        SET_DFNONE(s4);
    }
-    IFX(X_CF | X_AF | X_OF) {
-        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
-        BICw(xFlags, xFlags, s3);
+    IFX(X_CF|X_ZF|X_SF|X_OF) {
+        LSLw(s5, s1, 24);
+        ANDSw_REG_LSL(s5, s5, s2, 24);
+        IFX(X_ZF) {
+            IFNATIVE(NF_EQ) {} else {
+                CSETw(s4, cEQ);
+                BFIw(xFlags, s4, F_ZF, 1);
+            }
+        }
+        IFX(X_CF) {
+            IFNATIVE(NF_CF) {} else {BFCw(xFlags, F_CF, 1);}
+        }
+        IFX(X_OF) {
+            IFNATIVE(NF_VF) {} else {BFCw(xFlags, F_OF, 1);}
+        }
+        IFX(X_SF) {
+            IFNATIVE(NF_SF) {} else {
+                CSETw(s4, cMI);
+                BFIw(xFlags, s4, F_SF, 1);
+            }
+        }
+        IFX(X_PF|X_PEND) {
+            LSRw(s5, s5, 24);
+        }
+    } else {
+        ANDw_REG(s5, s1, s2);   // res = s1 & s2
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
    }
-    ANDSw_REG(s5, s1, s2);   // res = s1 & s2
    IFX_PENDOR0 {
        STRB_U12(s5, xEmu, offsetof(x64emu_t, res));
    }
-    IFX(X_ZF) {
-        CSETw(s4, cEQ);
-        BFIw(xFlags, s4, F_ZF, 1);
-    }
-    IFX(X_SF) {
-        LSRw(s4, s5, 7);
-        BFIw(xFlags, s4, F_SF, 1);
-    }
-    // PF: (((emu->x64emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
    IFX(X_PF) {
-        emit_pf(dyn, ninst, s5, s3, s4);
+        emit_pf(dyn, ninst, s5, s4);
+    }
+}
+
+// emit TEST8 instruction, from test s1, s2, using s3, s4 and s5 as scratch
+void emit_test8c(dynarec_arm_t* dyn, int ninst, int s1, uint32_t c, int s3, int s4, int s5)
+{
+    MAYUSE(s1);
+    int mask = 0;
+    IFX_PENDOR0 {
+        SET_DF(s3, d_tst8);
+    } else {
+        SET_DFNONE(s4);
+    }
+    IFX(X_CF|X_ZF|X_SF|X_OF) {
+        LSLw(s5, s1, 24);
+        mask = convert_bitmask_w(c<<24);
+        if(mask) {
+            ANDSw_mask(s5, s5, mask&0x3F, (mask>>6)&0x3F);
+        } else {
+            MOV32w(s3, c);
+            ANDSw_REG_LSL(s5, s5, s3, 24);
+        }
+        IFX(X_ZF) {
+            IFNATIVE(NF_EQ) {} else {
+                CSETw(s4, cEQ);
+                BFIw(xFlags, s4, F_ZF, 1);
+            }
+        }
+        IFX(X_CF) {
+            IFNATIVE(NF_CF) {} else {BFCw(xFlags, F_CF, 1);}
+        }
+        IFX(X_OF) {
+            IFNATIVE(NF_VF) {} else {BFCw(xFlags, F_OF, 1);}
+        }
+        IFX(X_SF) {
+            IFNATIVE(NF_SF) {} else {
+                CSETw(s4, cMI);
+                BFIw(xFlags, s4, F_SF, 1);
+            }
+        }
+        IFX(X_PF|X_PEND) {
+            LSRw(s5, s5, 24);
+        }
+    } else {
+        mask = convert_bitmask_w(c);
+        if(mask) {
+            ANDw_mask(s5, s1, mask&0x3F, (mask>>6)&0x3F);
+        } else {
+            MOV32w(s5, c);
+            ANDw_REG(s5, s1, s5);   // res = s1 & s2
+        }
+    }
+    IFX(X_AF) {
+        BFCw(xFlags, F_AF, 1);
+    }
+    IFX_PENDOR0 {
+        STRB_U12(s5, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s5, s4);
    }
 }
@@ -18,13 +18,13 @@

 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"
 #include "dynarec_arm64_functions.h"


 uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
 {
-    (void)ip; (void)rep; (void)need_epilog;
+    (void)ip; (void)need_epilog;

    uint8_t opcode = F8;
    uint8_t nextop;
@@ -46,8 +46,13 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
        rep = opcode-0xF1;
        opcode = F8;
    }
+    while((opcode==0x36) || (opcode==0x2e) || (opcode==0x3E) || (opcode==0x26)) {
+        opcode = F8;
+    }
+

    GETREX();
+    SKIPTEST(x1);   // DYNAREC_TEST doesn't work, by nature, on atomic opration

    switch(opcode) {
        case 0x00:
@@ -57,12 +62,12 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            GETGB(x2);
            if((nextop&0xC0)==0xC0) {
                if(rex.rex) {
-                    wback = xRAX + (nextop&7) + (rex.b<<3);
+                    wback = TO_NAT((nextop & 0x07) + (rex.b << 3));
                    wb2 = 0;
                } else {
                    wback = (nextop&7);
                    wb2 = (wback>>2);
-                    wback = xRAX+(wback&3);
+                    wback = TO_NAT(wback & 3);
                }
                UBFXw(x1, wback, wb2*8, 8);
                emit_add8(dyn, ninst, x1, x2, x4, x3);
@@ -91,11 +96,21 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            SETFLAGS(X_ALL, SF_SET_PENDING);
            nextop = F8;
            GETGD;
-            if((nextop&0xC0)==0xC0) {
-                ed = xRAX+(nextop&7)+(rex.b<<3);
+            if(MODREG) {
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                emit_add32(dyn, ninst, rex, ed, gd, x3, x4);
            } else {
                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                if(!ALIGNED_ATOMICxw) {
+                    if(arm64_uscat) {
+                        ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                        CMPSw_U12(x1, 16-(1<<(2+rex.w)));
+                        B_MARK(cGT);
+                    } else {
+                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                        B_MARK(cNE);
+                    }
+                }
                if(arm64_atomics) {
                    UFLAG_IF {
                        LDADDALxw(gd, x1, wback);
@@ -103,14 +118,27 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    } else {
                        STADDLxw(gd, wback);
                    }
+                    SMDMB();
                } else {
                    MARKLOCK;
                    LDAXRxw(x1, wback);
                    emit_add32(dyn, ninst, rex, x1, gd, x3, x4);
                    STLXRxw(x3, x1, wback);
                    CBNZx_MARKLOCK(x3);
+                    SMDMB();
+                }
+                if(!ALIGNED_ATOMICxw) {
+                    B_NEXT_nocond;
+                    MARK;   // unaligned! also, not enough
+                    LDRxw_U12(x1, wback, 0);
+                    LDAXRB(x4, wback);
+                    BFIxw(x1, x4, 0, 8); // re-inject
+                    emit_add32(dyn, ninst, rex, x1, gd, x3, x4);
+                    STLXRB(x3, x1, wback);
+                    CBNZx_MARK(x3);
+                    STRxw_U12(x1, wback, 0);    // put the whole value
+                    SMDMB();
                }
-                SMDMB();
            }
            break;

@@ -121,12 +149,12 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            GETGB(x2);
            if((nextop&0xC0)==0xC0) {
                if(rex.rex) {
-                    wback = xRAX + (nextop&7) + (rex.b<<3);
+                    wback = TO_NAT((nextop & 0x07) + (rex.b << 3));
                    wb2 = 0;
                } else {
                    wback = (nextop&7);
                    wb2 = (wback>>2);
-                    wback = xRAX+(wback&3);
+                    wback = TO_NAT(wback & 3);
                }
                UBFXw(x1, wback, wb2*8, 8);
                emit_or8(dyn, ninst, x1, x2, x4, x3);
@@ -154,7 +182,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            nextop = F8;
            GETGD;
            if(MODREG) {
-                ed = xRAX+(nextop&7)+(rex.b<<3);
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                emit_or32(dyn, ninst, rex, ed, gd, x3, x4);
            } else {
                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
@@ -185,7 +213,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    nextop = F8;
                    GETGD;
                    if(MODREG) {
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        wback = 0;
                        if(rex.w) {
                            ANDx_mask(x2, gd, 1, 0, 0b00101);  //mask=0x000000000000003f
@@ -214,7 +242,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                        MARKLOCK;
                        LDAXRB(ed, wback);
                        LSRw_REG(x4, ed, x2);
-                        BFIw(xFlags, x5, F_CF, 1);
+                        BFIw(xFlags, x4, F_CF, 1);
                        LSLw_REG(x4, x5, x2);
                        ORRw_REG(ed, ed, x4);
                        STLXRB(x4, ed, wback);
@@ -232,19 +260,19 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                            UBFXx(x6, xRAX, 0, 8);
                            if(MODREG) {
                                if(rex.rex) {
-                                    wback = xRAX+(nextop&7)+(rex.b<<3);
+                                    wback = TO_NAT((nextop & 7) + (rex.b << 3));
                                    wb2 = 0;
                                } else {
                                    wback = (nextop&7);
                                    wb2 = (wback>>2)*8;
-                                    wback = xRAX+(wback&3);
+                                    wback = TO_NAT(wback & 3);
                                }
                                UBFXx(x2, wback, wb2, 8);
                                wb1 = 0;
                                ed = x2;
                                UFLAG_IF {emit_cmp8(dyn, ninst, x6, ed, x3, x4, x5);}
-                                CMPSxw_REG(x6, x2);
-                                B_MARK2(cNE);
+                                SUBxw_REG(x6, x6, x2);
+                                CBNZxw_MARK2(x6);
                                BFIx(wback, x2, wb2, 8);
                                MOVxw_REG(ed, gd);
                                MARK2;
@@ -289,12 +317,12 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                            nextop = F8;
                            GETGD;
                            if(MODREG) {
-                                ed = xRAX+(nextop&7)+(rex.b<<3);
+                                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                                wback = 0;
                                UFLAG_IF {emit_cmp32(dyn, ninst, rex, xRAX, ed, x3, x4, x5);}
                                MOVxw_REG(x1, ed);  // save value
-                                CMPSxw_REG(xRAX, x1);
-                                B_MARK2(cNE);
+                                SUBxw_REG(x3, xRAX, x1);
+                                CBNZxw_MARK2(x3);
                                MOVxw_REG(ed, gd);
                                MARK2;
                                MOVxw_REG(xRAX, x1);
@@ -302,8 +330,14 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                            } else {
                                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
                                if(!ALIGNED_ATOMICxw) {
-                                    TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
-                                    B_MARK3(cNE);
+                                    if(arm64_uscat) {
+                                        ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                                        CMPSw_U12(x1, 16-(1<<(2+rex.w)));
+                                        B_MARK3(cGT);
+                                    } else {
+                                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                                        B_MARK3(cNE);
+                                    }
                                }
                                // Aligned version
                                if(arm64_atomics) {
@@ -366,7 +400,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    nextop = F8;
                    GETGD;
                    if(MODREG) {
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        wback = 0;
                        if(rex.w) {
                            ANDx_mask(x2, gd, 1, 0, 0b00101);  //mask=0x000000000000003f
@@ -413,7 +447,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                        SET_DFNONE(x1);
                        gd = x2;
                        if(MODREG) {
-                            ed = xRAX+(nextop&7)+(rex.b<<3);
+                            ed = TO_NAT((nextop & 7) + (rex.b << 3));
                            u8 = F8;
                            u8&=rex.w?0x3f:0x1f;
                            BFXILxw(xFlags, ed, u8, 1);  // inject 1 bit from u8 to F_CF (i.e. pos 0)
@@ -437,7 +471,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                        SETFLAGS(X_CF, SF_SUBSET);
                        SET_DFNONE(x1);
                        if(MODREG) {
-                            ed = xRAX+(nextop&7)+(rex.b<<3);
+                            ed = TO_NAT((nextop & 7) + (rex.b << 3));
                            wback = 0;
                            u8 = F8;
                            u8&=(rex.w?0x3f:0x1f);
@@ -469,7 +503,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                        SETFLAGS(X_CF, SF_SUBSET);
                        SET_DFNONE(x1);
                        if(MODREG) {
-                            ed = xRAX+(nextop&7)+(rex.b<<3);
+                            ed = TO_NAT((nextop & 7) + (rex.b << 3));
                            wback = 0;
                            u8 = F8;
                            u8&=(rex.w?0x3f:0x1f);
@@ -498,7 +532,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                        SETFLAGS(X_CF, SF_SUBSET);
                        SET_DFNONE(x1);
                        if(MODREG) {
-                            ed = xRAX+(nextop&7)+(rex.b<<3);
+                            ed = TO_NAT((nextop & 7) + (rex.b << 3));
                            wback = 0;
                            u8 = F8;
                            u8&=(rex.w?0x3f:0x1f);
@@ -528,6 +562,52 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                }
                break;

+                case 0xC0:
+                    switch(rep) {
+                        case 0:
+                            INST_NAME("LOCK XADD Eb, Gb");
+                            SETFLAGS(X_ALL, SF_SET_PENDING);
+                            nextop = F8;
+                            GETGB(x1);
+                            if(MODREG) {
+                                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                                GETEB(x2, 0);
+                                gd = x2; ed = x1;    // swap gd/ed
+                                emit_add8(dyn, ninst, x1, x2, x4, x5);
+                                GBBACK; // gb gets x2 (old ed)
+                                EBBACK; // eb gets x1 (sum)
+                            } else {
+                                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                                if(arm64_atomics) {
+                                    UFLAG_IF {
+                                        MOVxw_REG(x3, gd);
+                                        LDADDALB(x3, gd, wback);
+                                        SMDMB();
+                                        emit_add8(dyn, ninst, x3, gd, x4, x5);
+                                    } else {
+                                        LDADDALB(gd, gd, wback);
+                                        SMDMB();
+                                    }
+                                    GBBACK;
+                                } else {
+                                    MARKLOCK;
+                                    LDAXRB(x1, wback);
+                                    ADDw_REG(x4, x1, gd);
+                                    STLXRB(x3, x4, wback);
+                                    CBNZx_MARKLOCK(x3);
+                                    SMDMB();
+                                    IFX(X_ALL|X_PEND) {
+                                        MOVxw_REG(x2, x1);
+                                        emit_add8(dyn, ninst, x2, gd, x3, x4);
+                                    }
+                                    BFIz(gb1, x1, gb2, 8);
+                                }
+                            }
+                            break;
+                        default:
+                            DEFAULT;
+                    }
+                    break;
                case 0xC1:
                    switch(rep) {
                        case 0:
@@ -536,7 +616,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                            nextop = F8;
                            GETGD;
                            if(MODREG) {
-                                ed = xRAX+(nextop&7)+(rex.b<<3);
+                                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                                MOVxw_REG(x1, ed);
                                MOVxw_REG(ed, gd);
                                MOVxw_REG(gd, x1);
@@ -544,8 +624,14 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                            } else {
                                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
                                if(!ALIGNED_ATOMICxw) {
-                                    TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
-                                    B_MARK(cNE);    // unaligned
+                                    if(arm64_uscat) {
+                                        ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                                        CMPSw_U12(x1, 16-(1<<(2+rex.w)));
+                                        B_MARK(cGT);
+                                    } else {
+                                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                                        B_MARK(cNE);    // unaligned
+                                    }
                                }
                                if(arm64_atomics) {
                                    UFLAG_IF {
@@ -598,52 +684,103 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    break;

                case 0xC7:
-                    switch(rep) {
-                        case 0:
+                    // rep has no impact here
+                    nextop = F8;
+                    switch((nextop>>3)&7) {
+                        case 1:
+                        if (rex.w) {
+                            INST_NAME("LOCK CMPXCHG16B Gq, Eq");
+                        } else {
                            INST_NAME("LOCK CMPXCHG8B Gq, Eq");
-                            SETFLAGS(X_ZF, SF_SUBSET);
-                            nextop = F8;
-                            addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
-                            if(arm64_atomics) {
-                                MOVx_REG(x2, xRAX);
-                                MOVx_REG(x3, xRDX);
-                                MOVx_REG(x4, xRBX);
-                                MOVx_REG(x5, xRCX);
-                                CASPALxw(x2, x4, wback);
-                                UFLAG_IF {
-                                    CMPSxw_REG(x2, xRAX);
-                                    CCMPxw(x3, xRDX, 0, cEQ);
-                                    CSETw(x1, cEQ);
+                        }
+                        SETFLAGS(X_ZF, SF_SUBSET);
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                        if(!ALIGNED_ATOMICxw) {
+                            if(arm64_uscat) {
+                                if(rex.w) {
+                                    TSTx_mask(wback, 1, 0, 3);
+                                    B_MARK2(cNE);    
+                                } else {
+                                    ANDx_mask(x2, wback, 1, 0, 3);  // mask = F
+                                    CMPSw_U12(x2, 8);
+                                    B_MARK2(cGT);
                                }
-                                MOVx_REG(xRAX, x2);
-                                MOVx_REG(xRDX, x3);
                            } else {
-                                MARKLOCK;
-                                LDAXPxw(x2, x3, wback);
-                                CMPSxw_REG(xRAX, x2);
-                                CCMPxw(xRDX, x3, 0, cEQ);
-                                B_MARK(cNE);    // EAX!=ED[0] || EDX!=Ed[1]
-                                STLXPxw(x4, xRBX, xRCX, wback);
-                                CBNZx_MARKLOCK(x4);
-                                UFLAG_IF {
-                                    MOV32w(x1, 1);
-                                }
-                                B_MARK3_nocond;
-                                MARK;
-                                MOVxw_REG(xRAX, x2);
-                                MOVxw_REG(xRDX, x3);
-                                UFLAG_IF {
-                                    MOV32w(x1, 0);
-                                }
+                                TSTx_mask(wback, 1, 0, 2+rex.w);    // mask=7 or F
+                                B_MARK2(cNE);    // unaligned
                            }
-                            MARK3;
-                            SMDMB();
+                        }
+                        if(arm64_atomics) {
+                            MOVx_REG(x2, xRAX);
+                            MOVx_REG(x3, xRDX);
+                            MOVx_REG(x4, xRBX);
+                            MOVx_REG(x5, xRCX);
+                            CASPALxw(x2, x4, wback);
                            UFLAG_IF {
-                                BFIw(xFlags, x1, F_ZF, 1);
+                                CMPSxw_REG(x2, xRAX);
+                                CCMPxw(x3, xRDX, 0, cEQ);
+                                IFNATIVE(NF_EQ) {} else {CSETw(x1, cEQ);}
                            }
-                            break;
-                        default:
-                            DEFAULT;
+                            MOVx_REG(xRAX, x2);
+                            MOVx_REG(xRDX, x3);
+                            if(!ALIGNED_ATOMICxw) {
+                                B_MARK3_nocond;
+                            }
+                        } else {
+                            MARKLOCK;
+                            LDAXPxw(x2, x3, wback);
+                            CMPSxw_REG(xRAX, x2);
+                            CCMPxw(xRDX, x3, 0, cEQ);
+                            B_MARK(cNE);    // EAX!=ED[0] || EDX!=Ed[1]
+                            STLXPxw(x4, xRBX, xRCX, wback);
+                            CBNZx_MARKLOCK(x4);
+                            UFLAG_IF {
+                                IFNATIVE(NF_EQ) {} else {MOV32w(x1, 1);}
+                            }
+                            B_MARK3_nocond;
+                            MARK;
+                            STLXPxw(x4, x2, x3, wback); // write back, to be sure it was "atomic"
+                            CBNZx_MARKLOCK(x4);
+                            MOVxw_REG(xRAX, x2);
+                            MOVxw_REG(xRDX, x3);
+                            UFLAG_IF {
+                                IFNATIVE(NF_EQ) {} else {MOV32w(x1, 0);}
+                            }
+                            if(!ALIGNED_ATOMICxw) {
+                                B_MARK3_nocond;
+                            }
+                        }
+                        if(!ALIGNED_ATOMICxw) {
+                            MARK2;
+                            LDPxw_S7_offset(x2, x3, wback, 0);
+                            LDAXRB(x5, wback);
+                            CMPSxw_REG(xRAX, x2);
+                            CCMPxw(xRDX, x3, 0, cEQ);
+                            B_MARKSEG(cNE);    // EAX!=ED[0] || EDX!=Ed[1]
+                            STLXRB(x4, xRBX, wback);
+                            CBNZx_MARK2(x4);
+                            STPxw_S7_offset(xRBX, xRCX, wback, 0);
+                            UFLAG_IF {
+                                IFNATIVE(NF_EQ) {} else {MOV32w(x1, 1);}
+                            }
+                            B_MARK3_nocond;
+                            MARKSEG;
+                            STLXRB(x4, x5, wback); //write back
+                            CBNZx_MARK2(x4);
+                            MOVxw_REG(xRAX, x2);
+                            MOVxw_REG(xRDX, x3);
+                            UFLAG_IF {
+                                IFNATIVE(NF_EQ) {} else {MOV32w(x1, 0);}
+                            }
+                        }
+                        MARK3;
+                        SMDMB();
+                        UFLAG_IF {
+                            IFNATIVE(NF_EQ) {} else {BFIw(xFlags, x1, F_ZF, 1);}
+                        }
+                        break;
+                    default:
+                        DEFAULT;
                    }
                    break;

@@ -659,12 +796,12 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            GETGB(x2);
            if((nextop&0xC0)==0xC0) {
                if(rex.rex) {
-                    wback = xRAX + (nextop&7) + (rex.b<<3);
+                    wback = TO_NAT((nextop & 0x07) + (rex.b << 3));
                    wb2 = 0;
                } else {
                    wback = (nextop&7);
                    wb2 = (wback>>2);
-                    wback = xRAX+(wback&3);
+                    wback = TO_NAT(wback & 3);
                }
                UBFXw(x1, wback, wb2*8, 8);
                emit_adc8(dyn, ninst, x1, x2, x4, x5);
@@ -686,7 +823,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            nextop = F8;
            GETGD;
            if(MODREG) {
-                ed = xRAX+(nextop&7)+(rex.b<<3);
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                emit_adc32(dyn, ninst, rex, ed, gd, x3, x4);
            } else {
                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
@@ -698,13 +835,44 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                SMDMB();
            }
            break;
+        case 0x20:
+            INST_NAME("LOCK AND Eb, Gb");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGD;
+            if(MODREG) {
+                GETEB(x1, 0);
+                GETGB(x2);
+                emit_and8(dyn, ninst, x1, x2, x4, x5);
+                EBBACK;
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                GETGB(x5);
+                if(arm64_atomics) {
+                    MVNxw_REG(x1, gd);
+                    UFLAG_IF {
+                        LDCLRALB(x1, x1, wback);
+                        emit_and8(dyn, ninst, x1, gd, x3, x4);
+                    } else {
+                        STCLRLB(x1, wback);
+                    }
+                } else {
+                    MARKLOCK;
+                    LDAXRB(x1, wback);
+                    emit_and8(dyn, ninst, x1, gd, x3, x4);
+                    STLXRB(x3, x1, wback);
+                    CBNZx_MARKLOCK(x3);
+                    SMDMB();
+                }
+            }
+            break;
        case 0x21:
            INST_NAME("LOCK AND Ed, Gd");
            SETFLAGS(X_ALL, SF_SET_PENDING);
            nextop = F8;
            GETGD;
            if(MODREG) {
-                ed = xRAX+(nextop&7)+(rex.b<<3);
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                emit_and32(dyn, ninst, rex, ed, gd, x3, x4);
            } else {
                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
@@ -733,10 +901,20 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            nextop = F8;
            GETGD;
            if(MODREG) {
-                ed = xRAX+(nextop&7)+(rex.b<<3);
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
                emit_sub32(dyn, ninst, rex, ed, gd, x3, x4);
            } else {
                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                if(!ALIGNED_ATOMICxw) {
+                    if(arm64_uscat) {
+                        ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                        CMPSw_U12(x1, 16-(1<<(2+rex.w)));
+                        B_MARK(cGT);
+                    } else {
+                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                        B_MARK(cNE);
+                    }
+                }
                if(arm64_atomics) {
                    NEGxw_REG(x1, gd);
                    UFLAG_IF {
@@ -753,6 +931,69 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    CBNZx_MARKLOCK(x3);
                    SMDMB();
                }
+                if(!ALIGNED_ATOMICxw) {
+                    B_NEXT_nocond;
+                    MARK;   // unaligned! also, not enough
+                    LDRxw_U12(x1, wback, 0);
+                    LDAXRB(x4, wback);
+                    BFIxw(x1, x4, 0, 8); // re-inject
+                    emit_sub32(dyn, ninst, rex, x1, gd, x3, x4);
+                    STLXRB(x3, x1, wback);
+                    CBNZx_MARK(x3);
+                    STRxw_U12(x1, wback, 0);    // put the whole value
+                    SMDMB();
+                }
+            }
+            break;
+
+        case 0x31:
+            INST_NAME("LOCK XOR Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGD;
+            if((nextop&0xC0)==0xC0) {
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                emit_xor32(dyn, ninst, rex, ed, gd, x3, x4);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                if(!ALIGNED_ATOMICxw) {
+                    if(arm64_uscat) {
+                        ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                        CMPSw_U12(x1, 16-(1<<(2+rex.w)));
+                        B_MARK(cGT);
+                    } else {
+                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                        B_MARK(cNE);
+                    }
+                }
+                if(arm64_atomics) {
+                    UFLAG_IF {
+                        LDEORALxw(gd, x1, wback);
+                        emit_xor32(dyn, ninst, rex, x1, gd, x3, x4);    
+                    } else {
+                        STEORLxw(gd, wback);
+                    }
+                    SMDMB();
+                } else {
+                    MARKLOCK;
+                    LDAXRxw(x1, wback);
+                    emit_xor32(dyn, ninst, rex, x1, gd, x3, x4);
+                    STLXRxw(x3, x1, wback);
+                    CBNZx_MARKLOCK(x3);
+                    SMDMB();
+                }
+                if(!ALIGNED_ATOMICxw) {
+                    B_NEXT_nocond;
+                    MARK;   // unaligned! also, not enough
+                    LDRxw_U12(x1, wback, 0);
+                    LDAXRB(x4, wback);
+                    BFIxw(x1, x4, 0, 8); // re-inject
+                    emit_xor32(dyn, ninst, rex, x1, gd, x3, x4);
+                    STLXRB(x3, x1, wback);
+                    CBNZx_MARK(x3);
+                    STRxw_U12(x1, wback, 0);    // put the whole value
+                    SMDMB();
+                }
            }
            break;

@@ -991,15 +1232,21 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        MOV64xw(x5, i64);
                        emit_add32(dyn, ninst, rex, ed, x5, x3, x4);
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?4:1);
                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
                        if(!ALIGNED_ATOMICxw) {
-                            TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
-                            B_MARK(cNE);
+                            if(arm64_uscat) {
+                                ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                                CMPSw_U12(x1, 16-(1<<(2+rex.w)));
+                                B_MARK(cGT);
+                            } else {
+                                TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                                B_MARK(cNE);
+                            }
                        }
                        if(arm64_atomics) {
                            MOV64xw(x3, i64);
@@ -1038,7 +1285,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        MOV64xw(x5, i64);
                        emit_or32(dyn, ninst, rex, ed, x5, x3, x4);
                    } else {
@@ -1068,7 +1315,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        MOV64xw(x5, i64);
                        emit_adc32(dyn, ninst, rex, ed, x5, x3, x4);
                    } else {
@@ -1089,7 +1336,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        MOV64xw(x5, i64);
                        emit_sbb32(dyn, ninst, rex, ed, x5, x3, x4);
                    } else {
@@ -1109,7 +1356,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        MOV64xw(x5, i64);
                        emit_and32(dyn, ninst, rex, ed, x5, x3, x4);
                    } else {
@@ -1140,15 +1387,21 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        MOV64xw(x5, i64);
                        emit_sub32(dyn, ninst, rex, ed, x5, x3, x4);
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?4:1);
                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
                        if(!ALIGNED_ATOMICxw) {
-                            TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
-                            B_MARK(cNE);
+                            if(arm64_uscat) {
+                                ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                                CMPSw_U12(x1, 16-(1<<(2+rex.w)));
+                                B_MARK(cGT);
+                            } else {
+                                TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                                B_MARK(cNE);
+                            }
                        }
                        if(arm64_atomics) {
                            MOV64xw(x5, -i64);
@@ -1188,7 +1441,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    SETFLAGS(X_ALL, SF_SET_PENDING);
                    if(MODREG) {
                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        MOV64xw(x5, i64);
                        emit_xor32(dyn, ninst, rex, ed, x5, x3, x4);
                    } else {
@@ -1235,12 +1488,12 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            if(MODREG) {
                GETGB(x4);
                if(rex.rex) {
-                    ed = xRAX+(nextop&7)+(rex.b<<3);
+                    ed = TO_NAT((nextop & 7) + (rex.b << 3));
                    eb1 = ed;
                    eb2 = 0;
                } else {
                    ed = (nextop&7);
-                    eb1 = xRAX+(ed&3);
+                    eb1 = TO_NAT(ed & 3);
                    eb2 = ((ed&4)<<1);
                }
                UBFXw(x1, eb1, eb2, 8);
@@ -1277,8 +1530,14 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                GETGD;
                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
                if(!ALIGNED_ATOMICxw) {
-                    TSTx_mask(ed, 1, 0, 1+rex.w);    // mask=3 or 7
-                    B_MARK(cNE);
+                    if(arm64_uscat) {
+                        ANDx_mask(x1, ed, 1, 0, 3);  // mask = F
+                        CMPSw_U12(x1, 16-(1<<(2+rex.w)));
+                        B_MARK(cGT);
+                    } else {
+                        TSTx_mask(ed, 1, 0, 1+rex.w);    // mask=3 or 7
+                        B_MARK(cNE);
+                    }
                }
                if(arm64_atomics) {
                    SWPALxw(gd, gd, ed);
@@ -1320,8 +1579,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    SMDMB();
                    GETEB(x1, 1);
                    u8 = F8;
-                    MOV32w(x2, u8);
-                    emit_test8(dyn, ninst, x1, x2, x3, x4, x5);
+                    emit_test8c(dyn, ninst, x1, u8, x3, x4, x5);
                    break;
                case 2:
                    INST_NAME("LOCK NOT Eb");
@@ -1350,7 +1608,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            {
                case 0: // INC Eb
                    INST_NAME("LOCK INC Eb");
-                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET);
                    if(MODREG) {
                        GETEB(x1, 0);
                        emit_inc8(dyn, ninst, x1, x2, x4);
@@ -1377,7 +1635,7 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    break;
                case 1: //DEC Eb
                    INST_NAME("LOCK DEC Eb");
-                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET);
                    if(MODREG) {
                        GETEB(x1, 0);
                        emit_dec8(dyn, ninst, x1, x2, x4);
@@ -1412,15 +1670,21 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
            {
                case 0: // INC Ed
                    INST_NAME("LOCK INC Ed");
-                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET);
                    if(MODREG) {
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        emit_inc32(dyn, ninst, rex, ed, x3, x4);
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
                        if(!ALIGNED_ATOMICxw) {
-                            TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
-                            B_MARK(cNE);    // unaligned
+                            if(arm64_uscat) {
+                                ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                                CMPSw_U12(x1, 16-(1<<(2+rex.w)));
+                                B_MARK(cGT);
+                            } else {
+                                TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                                B_MARK(cNE);    // unaligned
+                            }
                        }
                        if(arm64_atomics) {
                            MOV32w(x3, 1);
@@ -1454,15 +1718,21 @@ uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                    break;
                case 1: //DEC Ed
                    INST_NAME("LOCK DEC Ed");
-                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET);
                    if(MODREG) {
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        ed = TO_NAT((nextop & 7) + (rex.b << 3));
                        emit_dec32(dyn, ninst, rex, ed, x3, x4);
                    } else {
                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
                        if(!ALIGNED_ATOMICxw) {
-                            TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
-                            B_MARK(cNE);    // unaligned
+                            if(arm64_uscat) {
+                                ANDx_mask(x1, wback, 1, 0, 3);  // mask = F
+                                CMPSw_U12(x1, 16-(1<<(2+rex.w)));
+                                B_MARK(cGT);
+                            } else {
+                                TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                                B_MARK(cNE);    // unaligned
+                            }
                        }
                        if(arm64_atomics) {
                            MOV64xw(x3, -1);
@@ -19,7 +19,7 @@
 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"

 uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog)
 {
@@ -31,6 +31,8 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
    uint8_t wback, wb1, wb2;
    uint8_t u8;
    uint64_t u64, j64;
+    int32_t i32, i32_;
+    int cacheupd = 0;
    int v0, v1;
    int q0;
    int d0, d1;
@@ -83,14 +85,13 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            if(MODREG) {
                d0 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
-                VMOVeD(v0, 0, d0, 0);
+                VDUPQ_64(v0, d0, 0);
            } else {
                SMREAD();
                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
-                VLD64(v0, ed, fixedaddress);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                VLDQ1R_64(v0, ed);
            }
-            VMOVeD(v0, 1, v0, 0);
            break;

        case 0x2A:
@@ -98,7 +99,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            nextop = F8;
            GETGX(v0, 1);
            GETED(0);
-            d1 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn, ninst);
            if(rex.w) {
                SCVTFDx(d1, ed);
            } else {
@@ -139,7 +140,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                MSR_fpsr(x5);
            }
            u8 = sse_setround(dyn, ninst, x1, x2, x3);
-            d1 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn, ninst);
            FRINTID(d1, q0);
            x87_restoreround(dyn, ninst, u8);
            FCVTZSxwD(gd, d1);
@@ -206,10 +207,10 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            INST_NAME("SQRTSD Gx, Ex");
            nextop = F8;
            GETGX(v0, 1);
-            d1 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn, ninst);
            GETEXSD(d0, 0, 0);
            if(!box64_dynarec_fastnan) {
-                v1 = fpu_get_scratch(dyn);
+                v1 = fpu_get_scratch(dyn, ninst);
                FCMLTD_0(v1, d0);
                SHL_64(v1, v1, 63);
                FSQRTD(d1, d0);
@@ -224,11 +225,11 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            INST_NAME("ADDSD Gx, Ex");
            nextop = F8;
            GETGX(d1, 1);
-            v1 = fpu_get_scratch(dyn);
+            v1 = fpu_get_scratch(dyn, ninst);
            GETEXSD(d0, 0, 0);
            if(!box64_dynarec_fastnan) {
-                v0 = fpu_get_scratch(dyn);
-                q0 = fpu_get_scratch(dyn);
+                v0 = fpu_get_scratch(dyn, ninst);
+                q0 = fpu_get_scratch(dyn, ninst);
                // check if any input value was NAN
                FMAXD(v0, d0, d1);    // propagate NAN
                FCMEQD(v0, v0, v0);    // 0 if NAN, 1 if not NAN
@@ -246,11 +247,11 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            INST_NAME("MULSD Gx, Ex");
            nextop = F8;
            GETGX(d1, 1);
-            v1 = fpu_get_scratch(dyn);
+            v1 = fpu_get_scratch(dyn, ninst);
            GETEXSD(d0, 0, 0);
            if(!box64_dynarec_fastnan) {
-                v0 = fpu_get_scratch(dyn);
-                q0 = fpu_get_scratch(dyn);
+                v0 = fpu_get_scratch(dyn, ninst);
+                q0 = fpu_get_scratch(dyn, ninst);
                // check if any input value was NAN
                FMAXD(v0, d0, d1);    // propagate NAN
                FCMEQD(v0, v0, v0);    // 0 if NAN, 1 if not NAN
@@ -269,7 +270,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            nextop = F8;
            GETGX(v0, 1);
            GETEXSD(d0, 0, 0);
-            d1 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn, ninst);
            FCVT_S_D(d1, d0);
            VMOVeS(v0, 0, d1, 0);
            break;
@@ -278,11 +279,11 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            INST_NAME("SUBSD Gx, Ex");
            nextop = F8;
            GETGX(d1, 1);
-            v1 = fpu_get_scratch(dyn);
+            v1 = fpu_get_scratch(dyn, ninst);
            GETEXSD(d0, 0, 0);
            if(!box64_dynarec_fastnan) {
-                v0 = fpu_get_scratch(dyn);
-                q0 = fpu_get_scratch(dyn);
+                v0 = fpu_get_scratch(dyn, ninst);
+                q0 = fpu_get_scratch(dyn, ninst);
                // check if any input value was NAN
                FMAXD(v0, d0, d1);    // propagate NAN
                FCMEQD(v0, v0, v0);    // 0 if NAN, 1 if not NAN
@@ -303,7 +304,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            GETEXSD(v1, 0, 0);
            // MINSD: if any input is NaN, or Ex[0]<Gx[0], copy Ex[0] -> Gx[0]
            #if 0
-            d0 = fpu_get_scratch(dyn);
+            d0 = fpu_get_scratch(dyn, ninst);
            FMINNMD(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
            VMOVeD(v0, 0, d0, 0);   // to not erase uper part
            #else
@@ -316,11 +317,11 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            INST_NAME("DIVSD Gx, Ex");
            nextop = F8;
            GETGX(v0, 1);
-            d1 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn, ninst);
            GETEXSD(v1, 0, 0);
            if(!box64_dynarec_fastnan) {
-                d0 = fpu_get_scratch(dyn);
-                q0 = fpu_get_scratch(dyn);
+                d0 = fpu_get_scratch(dyn, ninst);
+                q0 = fpu_get_scratch(dyn, ninst);
                // check if any input value was NAN
                FMAXD(d0, v0, v1);      // propagate NAN
                FCMEQD(d0, d0, d0);     // 0 if NAN, 1 if not NAN
@@ -341,7 +342,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            GETEXSD(v1, 0, 0);
            // MAXSD: if any input is NaN, or Ex[0]>Gx[0], copy Ex[0] -> Gx[0]
            #if 0
-            d0 = fpu_get_scratch(dyn);
+            d0 = fpu_get_scratch(dyn, ninst);
            FMAXNMD(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
            VMOVeD(v0, 0, d0, 0);   // to not erase uper part
            #else
@@ -358,17 +359,27 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            GETGX(v0, 1);

            u8 = F8;
-            // only low part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits
-            u64 = 0;
-            for (int i=0; i<4; ++i) {
-                u64 |= ((uint64_t)((u8>>(i*2))&3)*2+0)<<(i*16+0);
-                u64 |= ((uint64_t)((u8>>(i*2))&3)*2+1)<<(i*16+8);
-            }
-            MOV64x(x2, u64);
-            d0 = fpu_get_scratch(dyn);
-            VMOVQDfrom(d0, 0, x2);
-            VTBL1_8(d0, v1, d0);
-            VMOVeD(v0, 0, d0, 0);
+            if(u8==0b00000000 || u8==0b01010101 || u8==0b10101010 || u8==0b11111111) {
+                if(v0==v1) {
+                    d0 = fpu_get_scratch(dyn, ninst);
+                    VMOVQ(d0, v1);
+                }
+                VDUP_16(v0, v1, u8&3);
+                if(v0==v1)
+                    v1 = d0;
+            } else {
+                // only low part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits
+                u64 = 0;
+                for (int i=0; i<4; ++i) {
+                    u64 |= ((uint64_t)((u8>>(i*2))&3)*2+0)<<(i*16+0);
+                    u64 |= ((uint64_t)((u8>>(i*2))&3)*2+1)<<(i*16+8);
+                }
+                MOV64x(x2, u64);
+                d0 = fpu_get_scratch(dyn, ninst);
+                VMOVQDfrom(d0, 0, x2);
+                VTBL1_8(d0, v1, d0);
+                VMOVeD(v0, 0, d0, 0);
+                }
            if(v0!=v1) {
                VMOVeD(v0, 1, v1, 1);
            }
@@ -382,7 +393,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
            } else {
                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0);
-                v1 = fpu_get_scratch(dyn);
+                v1 = fpu_get_scratch(dyn, ninst);
                VLD128(v1, ed, fixedaddress);
            }
            VFADDPQS(v0, v0, v1);
@@ -395,14 +406,63 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
            } else {
                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0);
-                v1 = fpu_get_scratch(dyn);
+                v1 = fpu_get_scratch(dyn, ninst);
                VLD128(v1, ed, fixedaddress);
            }
-            d0 = fpu_get_scratch(dyn);
+            d0 = fpu_get_scratch(dyn, ninst);
            VUZP1Q_32(d0, v0, v1);
            VUZP2Q_32(v0, v0, v1);
            VFSUBQS(v0, d0, v0);
            break;
+
+        #define GO(GETFLAGS, NO, YES, F)   \
+            READFLAGS(F);                                               \
+            i32_ = F32S;                                                \
+            if(rex.is32bits)                                            \
+                j64 = (uint32_t)(addr+i32_);                            \
+            else                                                        \
+                j64 = addr+i32_;                                        \
+            BARRIER(BARRIER_MAYBE);                                     \
+            JUMP(j64, 1);                                               \
+            GETFLAGS;                                                   \
+            if(dyn->insts[ninst].x64.jmp_insts==-1 ||                   \
+                CHECK_CACHE()) {                                        \
+                /* out of the block */                                  \
+                i32 = dyn->insts[ninst].epilog-(dyn->native_size);      \
+                Bcond(NO, i32);                                         \
+                if(dyn->insts[ninst].x64.jmp_insts==-1) {               \
+                    if(!(dyn->insts[ninst].x64.barrier&BARRIER_FLOAT))  \
+                        fpu_purgecache(dyn, ninst, 1, x1, x2, x3);      \
+                    jump_to_next(dyn, j64, 0, ninst, rex.is32bits);     \
+                } else {                                                \
+                    CacheTransform(dyn, ninst, cacheupd, x1, x2, x3);   \
+                    i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size);    \
+                    SKIP_SEVL(i32);                                     \
+                    B(i32);                                             \
+                }                                                       \
+            } else {                                                    \
+                /* inside the block */                                  \
+                i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size);    \
+                SKIP_SEVL(i32);                                         \
+                Bcond(YES, i32);                                        \
+            }
+
+        GOCOND(0x80, "J", "Id");
+        #undef GO
+
+        case 0xAE:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 6:
+                    INST_NAME("(unsupported) UWAIT Ed");
+                    FAKEED;
+                    UDF(0);
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+
        case 0xC2:
            INST_NAME("CMPSD Gx, Ex, Ib");
            nextop = F8;
@@ -428,7 +488,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            nextop = F8;
            GETGX(v0, 1);
            GETEX(v1, 0, 0);
-            q0 = fpu_get_scratch(dyn);
+            q0 = fpu_get_scratch(dyn, ninst);
            static float addsubps[4] = {-1.f, 1.f, -1.f, 1.f};
            MAYUSE(addsubps);
            TABLE64(x2, (uintptr_t)&addsubps);
@@ -461,7 +521,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                MSR_fpsr(x5);
                ORRw_mask(x4, xZR, 1, 0);    //0x80000000
-                d0 = fpu_get_scratch(dyn);
+                d0 = fpu_get_scratch(dyn, ninst);
                for(int i=0; i<2; ++i) {
                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                    MSR_fpsr(x5);
@@ -19,7 +19,7 @@
 #include "arm64_printer.h"
 #include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
-#include "dynarec_arm64_helper.h"
+#include "../dynarec_helper.h"

 uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog)
 {
@@ -84,7 +84,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            } else {
                SMREAD();
                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0);
-                q1 = fpu_get_scratch(dyn);
+                q1 = fpu_get_scratch(dyn, ninst);
                VLD128(q1, ed, fixedaddress);
            }
            GETGX_empty(q0);
@@ -99,7 +99,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            } else {
                SMREAD();
                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0);
-                q1 = fpu_get_scratch(dyn);
+                q1 = fpu_get_scratch(dyn, ninst);
                VLD128(q1, ed, fixedaddress);
            }
            GETGX_empty(q0);
@@ -117,7 +117,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            nextop = F8;
            GETGX(v0, 1);
            GETED(0);
-            d1 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn, ninst);
            if(rex.w) {
                SCVTFSx(d1, ed);
            } else {
@@ -158,7 +158,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                MSR_fpsr(x5);
            }
            u8 = sse_setround(dyn, ninst, x1, x2, x3);
-            d1 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn, ninst);
            FRINTIS(d1, q0);
            x87_restoreround(dyn, ninst, u8);
            FCVTZSxwS(gd, d1);
@@ -172,11 +172,41 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                }
            }
            break;
+
+        case 0x38:  /* MAP */
+            opcode = F8;
+            switch(opcode) {
+
+                case 0xF6:
+                    INST_NAME("ADOX Gd, Ed");
+                    nextop = F8;
+                    READFLAGS(X_OF);
+                    SETFLAGS(X_OF, SF_SUBSET);
+                    GETED(0);
+                    GETGD;
+                    MRS_nzcv(x3);
+                    LSRw(x4, xFlags, F_OF);
+                    BFIx(x3, x4, 29, 1); // set C
+                    MSR_nzcv(x3);      // load CC into ARM CF
+                    IFX(X_OF) {
+                        ADCSxw_REG(gd, gd, ed);
+                        CSETw(x3, cCS);
+                        BFIw(xFlags, x3, F_OF, 1);
+                    } else {
+                        ADCxw_REG(gd, gd, ed);
+                    }
+                    break;
+
+                default:
+                    DEFAULT;
+            }
+            break;
+
        case 0x51:
            INST_NAME("SQRTSS Gx, Ex");
            nextop = F8;
            GETGX(v0, 1);
-            d1 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn, ninst);
            GETEXSS(d0, 0, 0);
            FSQRTS(d1, d0);
            VMOVeS(v0, 0, d1, 0);
@@ -186,8 +216,8 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            nextop = F8;
            GETGX(v0, 1);
            GETEXSS(v1, 0, 0);
-            d0 = fpu_get_scratch(dyn);
-            d1 = fpu_get_scratch(dyn);
+            d0 = fpu_get_scratch(dyn, ninst);
+            d1 = fpu_get_scratch(dyn, ninst);
            // so here: F32: Imm8 = abcd efgh that gives => aBbbbbbc defgh000 00000000 00000000
            // and want 1.0f = 0x3f800000
            // so 00111111 10000000 00000000 00000000
@@ -203,7 +233,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            nextop = F8;
            GETGX(v0, 1);
            GETEXSS(v1, 0, 0);
-            d0 = fpu_get_scratch(dyn);
+            d0 = fpu_get_scratch(dyn, ninst);
            FMOVS_8(d0, 0b01110000);    //1.0f
            FDIVS(d0, d0, v1);
            VMOVeS(v0, 0, d0, 0);
@@ -213,7 +243,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            INST_NAME("ADDSS Gx, Ex");
            nextop = F8;
            GETGX(v0, 1);
-            d1 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn, ninst);
            GETEXSS(d0, 0, 0);
            FADDS(d1, v0, d0);  // the high part of the vector is erased...
            VMOVeS(v0, 0, d1, 0);
@@ -221,18 +251,31 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
        case 0x59:
            INST_NAME("MULSS Gx, Ex");
            nextop = F8;
-            GETGX(v0, 1);
-            d1 = fpu_get_scratch(dyn);
+            GETGX(d1, 1);
+            v1 = fpu_get_scratch(dyn, ninst);
            GETEXSS(d0, 0, 0);
-            FMULS(d1, v0, d0);
-            VMOVeS(v0, 0, d1, 0);
+            if(!box64_dynarec_fastnan) {
+                v0 = fpu_get_scratch(dyn, ninst);
+                q0 = fpu_get_scratch(dyn, ninst);
+                // check if any input value was NAN
+                FMAXS(v0, d0, d1);    // propagate NAN
+                FCMEQS(v0, v0, v0);    // 0 if NAN, 1 if not NAN
+                FMULS(v1, d1, d0);
+                FCMEQS(q0, v1, v1);    // 0 => out is NAN
+                VBIC(q0, v0, q0);      // forget it in any input was a NAN already
+                VSHL_32(q0, q0, 31);   // only keep the sign bit
+                VORR(v1, v1, q0);      // NAN -> -NAN
+            } else {
+                FMULS(v1, d1, d0);
+            }
+            VMOVeS(d1, 0, v1, 0);
            break;
        case 0x5A:
            INST_NAME("CVTSS2SD Gx, Ex");
            nextop = F8;
            GETGX(v0, 1);
            GETEXSS(v1, 0, 0);
-            d0 = fpu_get_scratch(dyn);
+            d0 = fpu_get_scratch(dyn, ninst);
            FCVT_D_S(d0, v1);
            VMOVeD(v0, 0, d0, 0);
            break;
@@ -248,7 +291,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                MSR_fpsr(x5);
                ORRw_mask(x4, xZR, 1, 0);    //0x80000000
-                d0 = fpu_get_scratch(dyn);
+                d0 = fpu_get_scratch(dyn, ninst);
                for(int i=0; i<4; ++i) {
                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                    MSR_fpsr(x5);
@@ -261,12 +304,11 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                }
            }
            break;
-
        case 0x5C:
            INST_NAME("SUBSS Gx, Ex");
            nextop = F8;
            GETGX(v0, 1);
-            d1 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn, ninst);
            GETEXSS(d0, 0, 0);
            FSUBS(d1, v0, d0);
            VMOVeS(v0, 0, d1, 0);
@@ -278,12 +320,12 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            GETEXSS(v1, 0, 0);
            // MINSS: if any input is NaN, or Ex[0]<Gx[0], copy Ex[0] -> Gx[0]
            #if 0
-            d0 = fpu_get_scratch(dyn);
+            d0 = fpu_get_scratch(dyn, ninst);
            FMINNMS(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
            VMOVeS(v0, 0, d0, 0);   // to not erase uper part
            #else
            FCMPS(v0, v1);
-            B_NEXT(cLS);    //Less than or equal
+            B_NEXT(cCC);    //Less than
            VMOVeS(v0, 0, v1, 0);   // to not erase uper part
            #endif
            break;
@@ -291,7 +333,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            INST_NAME("DIVSS Gx, Ex");
            nextop = F8;
            GETGX(v0, 1);
-            d1 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn, ninst);
            GETEXSS(d0, 0, 0);
            FDIVS(d1, v0, d0);
            VMOVeS(v0, 0, d1, 0);
@@ -303,16 +345,16 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            GETEXSS(v1, 0, 0);
            // MAXSS: if any input is NaN, or Ex[0]>Gx[0], copy Ex[0] -> Gx[0]
            #if 0
-            d0 = fpu_get_scratch(dyn);
+            d0 = fpu_get_scratch(dyn, ninst);
            FMAXNMS(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
            VMOVeS(v0, 0, d0, 0);   // to not erase uper part
            #else
            FCMPS(v0, v1);
-            B_NEXT(cGE);    //Greater than or equal
+            B_NEXT(cGT);    //Greater than
            VMOVeS(v0, 0, v1, 0);   // to not erase uper part
            #endif
            break;
-            
+
        case 0x6F:
            INST_NAME("MOVDQU Gx,Ex");// no alignment constraint on NEON here, so same as MOVDQA
            nextop = F8;
@@ -333,16 +375,20 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            GETEX(v1, 0, 1) ;
            GETGX(v0, 1);
            u8 = F8;
-            // only high part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits
-            u64 = 0;
-            for (int i=0; i<4; ++i) {
-                u64 |= ((uint64_t)((u8>>(i*2))&3)*2+8)<<(i*16+0);
-                u64 |= ((uint64_t)((u8>>(i*2))&3)*2+9)<<(i*16+8);
+            d0 = fpu_get_scratch(dyn, ninst);
+            if (u8 == 0b00000000 || u8 == 0b01010101 || u8 == 0b10101010 || u8 == 0b11111111) {
+                VDUPQ_16(d0, v1, (u8 & 3) + 4);
+            } else {
+                // only high part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits
+                u64 = 0;
+                for (int i = 0; i < 4; ++i) {
+                    u64 |= ((uint64_t)((u8 >> (i * 2)) & 3) * 2 + 8) << (i * 16 + 0);
+                    u64 |= ((uint64_t)((u8 >> (i * 2)) & 3) * 2 + 9) << (i * 16 + 8);
+                }
+                MOV64x(x2, u64);
+                VMOVQDfrom(d0, 0, x2);
+                VTBL1_8(d0, v1, d0);
            }
-            MOV64x(x2, u64);
-            d0 = fpu_get_scratch(dyn);
-            VMOVQDfrom(d0, 0, x2);
-            VTBL1_8(d0, v1, d0);
            VMOVeD(v0, 1, d0, 0);
            if(v0!=v1) {
                VMOVeD(v0, 0, v1, 0);
@@ -377,12 +423,40 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            }
            break;

+        case 0xAE:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 2:
+                    INST_NAME("(unsupported) WRFSBASE Ed");
+                    FAKEED;
+                    UDF(0);
+                    break;
+                case 3:
+                    INST_NAME("(unsupported) WRGSBASE Ed");
+                    FAKEED;
+                    UDF(0);
+                    break;
+                case 5:
+                    INST_NAME("(unsupported) INCSSPD/INCSSPQ Ed");
+                    FAKEED;
+                    UDF(0);
+                    break;
+                case 6:
+                    INST_NAME("(unsupported) UMONITOR Ed");
+                    FAKEED;
+                    UDF(0);
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+
        case 0xB8:
            INST_NAME("POPCNT Gd, Ed");
            SETFLAGS(X_ALL, SF_SET);
            SET_DFNONE(x1);
            nextop = F8;
-            v1 = fpu_get_scratch(dyn);
+            v1 = fpu_get_scratch(dyn, ninst);
            GETGD;
            if(MODREG) {
                GETED(0);
@@ -420,14 +494,18 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            nextop = F8;
            GETED(0);
            GETGD;
-            TSTxw_REG(ed, ed);
-            CSETw(x3, cEQ);
-            BFIw(xFlags, x3, F_CF, 1);  // CF = is source 0?
+            IFX(X_CF) {
+                TSTxw_REG(ed, ed);
+                CSETw(x3, cEQ);
+                BFIw(xFlags, x3, F_CF, 1);  // CF = is source 0?
+            }
            RBITxw(x3, ed);   // reverse
            CLZxw(gd, x3);    // x2 gets leading 0 == TZCNT
-            TSTxw_REG(gd, gd);
-            CSETw(x3, cEQ);
-            BFIw(xFlags, x3, F_ZF, 1);  // ZF = is dest 0?
+            IFX(X_ZF) {
+                TSTxw_REG(gd, gd);
+                CSETw(x3, cEQ);
+                BFIw(xFlags, x3, F_ZF, 1);  // ZF = is dest 0?
+            }
            break;
        case 0xBD:
            INST_NAME("LZCNT Gd, Ed");
@@ -436,13 +514,17 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            nextop = F8;
            GETED(0);
            GETGD;
-            TSTxw_REG(ed, ed);
-            CSETw(x3, cEQ);
-            BFIw(xFlags, x3, F_CF, 1);  // CF = is source 0?
+            IFX(X_CF) {
+                TSTxw_REG(ed, ed);
+                CSETw(x3, cEQ);
+                BFIw(xFlags, x3, F_CF, 1);  // CF = is source 0?
+            }
            CLZxw(gd, ed);    // x2 gets leading 0 == LZCNT
-            TSTxw_REG(gd, gd);
-            CSETw(x3, cEQ);
-            BFIw(xFlags, x3, F_ZF, 1);  // ZF = is dest 0?
+            IFX(X_ZF) {
+                TSTxw_REG(gd, gd);
+                CSETw(x3, cEQ);
+                BFIw(xFlags, x3, F_ZF, 1);  // ZF = is dest 0?
+            }
            break;

        case 0xC2:
@@ -485,7 +567,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
            nextop = F8;
            GETEXSD(v1, 0, 0);
            GETGX_empty(v0);
-            d0 = fpu_get_scratch(dyn);
+            d0 = fpu_get_scratch(dyn, ninst);
            SXTL_32(v0, v1);
            SCVTQFD(v0, v0);    // there is only I64 -> Double vector conversion, not from i32
            break;
@@ -26,26 +26,55 @@
 #include "custommem.h"
 #include "bridge.h"

-#define XMM0    0
-#define XMM8    16
-#define X870    8
-#define EMM0    8
-
 // Get a FPU scratch reg
-int fpu_get_scratch(dynarec_arm_t* dyn)
+int fpu_get_scratch(dynarec_arm_t* dyn, int ninst)
 {
-    return SCRATCH0 + dyn->n.fpu_scratch++;  // return an Sx
+    int ret = SCRATCH0 + dyn->n.fpu_scratch++;
+    if(dyn->n.ymm_used) printf_log(LOG_INFO, "Warning, getting a scratch register after getting some YMM at inst=%d\n", ninst);
+    if(dyn->n.neoncache[ret].t==NEON_CACHE_YMMR || dyn->n.neoncache[ret].t==NEON_CACHE_YMMW) {
+        // should only happens in step 0...
+        dyn->insts[ninst].purge_ymm |= (1<<dyn->n.neoncache[ret].n); // mark as purged
+        dyn->n.neoncache[ret].v = 0; // reset it
+    }
+    return ret;
+}
+// Get 2 consicutive FPU scratch reg
+int fpu_get_double_scratch(dynarec_arm_t* dyn, int ninst)
+{
+    int ret = SCRATCH0 + dyn->n.fpu_scratch;
+    if(dyn->n.ymm_used) printf_log(LOG_INFO, "Warning, getting a double scratch register after getting some YMM at inst=%d\n", ninst);
+    if(dyn->n.neoncache[ret].t==NEON_CACHE_YMMR || dyn->n.neoncache[ret].t==NEON_CACHE_YMMW) {
+        // should only happens in step 0...
+        dyn->insts[ninst].purge_ymm |= (1<<dyn->n.neoncache[ret].n); // mark as purged
+        dyn->n.neoncache[ret].v = 0; // reset it
+    }
+    if(dyn->n.neoncache[ret+1].t==NEON_CACHE_YMMR || dyn->n.neoncache[ret+1].t==NEON_CACHE_YMMW) {
+        // should only happens in step 0...
+        dyn->insts[ninst].purge_ymm |= (1<<dyn->n.neoncache[ret+1].n); // mark as purged
+        dyn->n.neoncache[ret+1].v = 0; // reset it
+    }
+    dyn->n.fpu_scratch+=2;
+    return ret;
 }
 // Reset scratch regs counter
 void fpu_reset_scratch(dynarec_arm_t* dyn)
 {
    dyn->n.fpu_scratch = 0;
+    dyn->n.ymm_used = 0;
+    dyn->n.ymm_regs = 0;
+    dyn->n.ymm_write = 0;
+    dyn->n.ymm_removed = 0;
 }
 // Get a x87 double reg
-int fpu_get_reg_x87(dynarec_arm_t* dyn, int t, int n)
+int fpu_get_reg_x87(dynarec_arm_t* dyn, int ninst, int t, int n)
 {
    int i=X870;
    while (dyn->n.fpuused[i]) ++i;
+    if(dyn->n.neoncache[i].t==NEON_CACHE_YMMR || dyn->n.neoncache[i].t==NEON_CACHE_YMMW) {
+        // should only happens in step 0...
+        dyn->insts[ninst].purge_ymm |= (1<<dyn->n.neoncache[i].n); // mark as purged
+        dyn->n.neoncache[i].v = 0; // reset it
+    }
    dyn->n.fpuused[i] = 1;
    dyn->n.neoncache[i].n = n;
    dyn->n.neoncache[i].t = t;
@@ -57,17 +86,34 @@ void fpu_free_reg(dynarec_arm_t* dyn, int reg)
 {
    // TODO: check upper limit?
    dyn->n.fpuused[reg] = 0;
+    if(dyn->n.neoncache[reg].t==NEON_CACHE_YMMR || dyn->n.neoncache[reg].t==NEON_CACHE_YMMW) {
+        dyn->n.ymm_removed |= 1<<dyn->n.neoncache[reg].n;
+        if(dyn->n.neoncache[reg].t==NEON_CACHE_YMMW)
+            dyn->n.ymm_write |= 1<<dyn->n.neoncache[reg].n;
+        if(reg>SCRATCH0)
+            dyn->n.ymm_regs |= (8LL+reg-SCRATCH0)<<(dyn->n.neoncache[reg].n*4);
+        else
+            dyn->n.ymm_regs |= ((uint64_t)(reg-EMM0))<<(dyn->n.neoncache[reg].n*4);
+    }
    if(dyn->n.neoncache[reg].t!=NEON_CACHE_ST_F && dyn->n.neoncache[reg].t!=NEON_CACHE_ST_D && dyn->n.neoncache[reg].t!=NEON_CACHE_ST_I64)
        dyn->n.neoncache[reg].v = 0;
+    if(dyn->n.fpu_scratch && reg==SCRATCH0+dyn->n.fpu_scratch-1)
+        --dyn->n.fpu_scratch;
 }
 // Get an MMX double reg
-int fpu_get_reg_emm(dynarec_arm_t* dyn, int emm)
+int fpu_get_reg_emm(dynarec_arm_t* dyn, int ninst, int emm)
 {
-    dyn->n.fpuused[EMM0 + emm] = 1;
-    dyn->n.neoncache[EMM0 + emm].t = NEON_CACHE_MM;
-    dyn->n.neoncache[EMM0 + emm].n = emm;
-    dyn->n.news |= (1<<(EMM0 + emm));
-    return EMM0 + emm;
+    int ret = EMM0 + emm;
+    if(dyn->n.neoncache[ret].t==NEON_CACHE_YMMR || dyn->n.neoncache[ret].t==NEON_CACHE_YMMW) {
+        // should only happens in step 0...
+        dyn->insts[ninst].purge_ymm |= (1<<dyn->n.neoncache[ret].n); // mark as purged
+        dyn->n.neoncache[ret].v = 0; // reset it
+    }
+    dyn->n.fpuused[ret] = 1;
+    dyn->n.neoncache[ret].t = NEON_CACHE_MM;
+    dyn->n.neoncache[ret].n = emm;
+    dyn->n.news |= (1<<(ret));
+    return ret;
 }
 // Get an XMM quad reg
 int fpu_get_reg_xmm(dynarec_arm_t* dyn, int t, int xmm)
@@ -84,15 +130,54 @@ int fpu_get_reg_xmm(dynarec_arm_t* dyn, int t, int xmm)
    dyn->n.news |= (1<<i);
    return i;
 }
+int internal_mark_ymm(dynarec_arm_t* dyn, int t, int ymm, int reg)
+{
+    if((dyn->n.neoncache[reg].t==NEON_CACHE_YMMR) || (dyn->n.neoncache[reg].t==NEON_CACHE_YMMW)) {
+        if(dyn->n.neoncache[reg].n == ymm) {
+            // already there!
+            if(t==NEON_CACHE_YMMW)
+                dyn->n.neoncache[reg].t=t;
+            return reg;
+        }
+    } else if(!dyn->n.neoncache[reg].v) {
+        // found a slot!
+        dyn->n.neoncache[reg].t=t;
+        dyn->n.neoncache[reg].n=ymm;
+        dyn->n.news |= (1<<reg);
+        return reg;
+    }
+    return -1;
+}
+int is_ymm_to_keep(dynarec_arm_t* dyn, int reg, int k1, int k2, int k3)
+{
+    if((k1!=-1) && (dyn->n.neoncache[reg].n==k1))
+        return 1;
+    if((k2!=-1) && (dyn->n.neoncache[reg].n==k2))
+        return 1;
+    if((k3!=-1) && (dyn->n.neoncache[reg].n==k3))
+        return 1;
+    if((dyn->n.neoncache[reg].t==NEON_CACHE_YMMR || dyn->n.neoncache[reg].t==NEON_CACHE_YMMW) && (dyn->n.ymm_used&(1<<dyn->n.neoncache[reg].n)))
+        return 1;
+    return 0;
+}
+
 // Reset fpu regs counter
+static void fpu_reset_reg_neoncache(neoncache_t* n)
+{
+    n->fpu_reg = 0;
+    for (int i=0; i<32; ++i) {
+        n->fpuused[i]=0;
+        n->neoncache[i].v = 0;
+    }
+    n->ymm_regs = 0;
+    n->ymm_removed = 0;
+    n->ymm_used = 0;
+    n->ymm_write = 0;
+
+}
 void fpu_reset_reg(dynarec_arm_t* dyn)
 {
-    dyn->n.fpu_reg = 0;
-    for (int i=0; i<24; ++i) {
-        dyn->n.fpuused[i]=0;
-        dyn->n.neoncache[i].v = 0;
-    }
-
+    fpu_reset_reg_neoncache(&dyn->n);
 }

 int neoncache_no_i64(dynarec_arm_t* dyn, int ninst, int st, int a)
@@ -208,15 +293,13 @@ static void neoncache_promote_double_combined(dynarec_arm_t* dyn, int ninst, int
                neoncache_promote_double_internal(dyn, ninst-1, maxinst, a-dyn->insts[ninst].n.stack_push);
            // go forward is combined is not pop'd
            if(a-dyn->insts[ninst].n.stack_pop>=0)
-                if(!dyn->insts[ninst+1].n.barrier)
+                if(!((ninst+1<dyn->size) && dyn->insts[ninst+1].n.barrier))
                    neoncache_promote_double_forward(dyn, ninst+1, maxinst, a-dyn->insts[ninst].n.stack_pop);
        }
    }
 }
 static void neoncache_promote_double_internal(dynarec_arm_t* dyn, int ninst, int maxinst, int a)
 {
-    if(dyn->insts[ninst+1].n.barrier)
-        return;
    while(ninst>=0) {
        a+=dyn->insts[ninst].n.stack_pop;    // adjust Stack depth: add pop'd ST (going backward)
        int i = neoncache_get_st_f_i64(dyn, ninst, a);
@@ -341,10 +424,11 @@ int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst) {
        return ((dyn->insts[ninst].x64.barrier&BARRIER_FLOAT))?0:(isCacheEmpty(dyn, ninst)?0:1);
    int ret = 0;
    if(!i2) { // just purge
-        if(dyn->insts[ninst].n.stack_next) {
+        if(dyn->insts[ninst].n.stack_next)
            return 1;
-        }
-        for(int i=0; i<24 && !ret; ++i)
+        if(dyn->insts[ninst].ymm0_out)
+            return 1;
+        for(int i=0; i<32 && !ret; ++i)
            if(dyn->insts[ninst].n.neoncache[i].v) {       // there is something at ninst for i
                if(!(
                (dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
@@ -359,10 +443,12 @@ int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst) {
    if(dyn->insts[ninst].n.stack_next != dyn->insts[i2].n.stack-dyn->insts[i2].n.stack_push) {
        return 1;
    }
+    if(dyn->insts[ninst].ymm0_out && (dyn->insts[ninst].ymm0_out&~dyn->insts[i2].ymm0_in))
+        return 1;
    neoncache_t cache_i2 = dyn->insts[i2].n;
    neoncacheUnwind(&cache_i2);

-    for(int i=0; i<24; ++i) {
+    for(int i=0; i<32; ++i) {
        if(dyn->insts[ninst].n.neoncache[i].v) {       // there is something at ninst for i
            if(!cache_i2.neoncache[i].v) {    // but there is nothing at i2 for i
                ret = 1;
@@ -372,6 +458,8 @@ int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst) {
                }
                else if(dyn->insts[ninst].n.neoncache[i].t == NEON_CACHE_XMMR && cache_i2.neoncache[i].t == NEON_CACHE_XMMW)
                    {/* nothing */ }
+                else if(dyn->insts[ninst].n.neoncache[i].t == NEON_CACHE_YMMR && cache_i2.neoncache[i].t == NEON_CACHE_YMMW)
+                    {/* nothing */ }
                else
                    ret = 1;
            }
@@ -387,6 +475,7 @@ void neoncacheUnwind(neoncache_t* cache)
        // unswap
        int a = -1;
        int b = -1;
+        // in neoncache
        for(int j=0; j<24 && ((a==-1) || (b==-1)); ++j)
            if((cache->neoncache[j].t == NEON_CACHE_ST_D || cache->neoncache[j].t == NEON_CACHE_ST_F || cache->neoncache[j].t == NEON_CACHE_ST_I64)) {
                if(cache->neoncache[j].n == cache->combined1)
@@ -399,12 +488,13 @@ void neoncacheUnwind(neoncache_t* cache)
            cache->neoncache[a].n = cache->neoncache[b].n;
            cache->neoncache[b].n = tmp;
        }
+        // done
        cache->swapped = 0;
        cache->combined1 = cache->combined2 = 0;
    }
    if(cache->news) {
-        // reove the newly created neoncache
-        for(int i=0; i<24; ++i)
+        // remove the newly created neoncache
+        for(int i=0; i<32; ++i)
            if(cache->news&(1<<i))
                cache->neoncache[i].v = 0;
        cache->news = 0;
@@ -420,17 +510,28 @@ void neoncacheUnwind(neoncache_t* cache)
            }
        }
        cache->x87stack-=cache->stack_push;
+        cache->tags>>=(cache->stack_push*2);
        cache->stack-=cache->stack_push;
+        if(cache->pushed>=cache->stack_push)
+            cache->pushed-=cache->stack_push;
+        else
+            cache->pushed = 0;
        cache->stack_push = 0;
    }
    cache->x87stack+=cache->stack_pop;
    cache->stack_next = cache->stack;
+    if(cache->stack_pop) {
+        if(cache->poped>=cache->stack_pop)
+            cache->poped-=cache->stack_pop;
+        else
+            cache->poped = 0;
+        cache->tags<<=(cache->stack_pop*2);
+    }
    cache->stack_pop = 0;
    cache->barrier = 0;
    // And now, rebuild the x87cache info with neoncache
    cache->mmxcount = 0;
    cache->fpu_scratch = 0;
-    cache->fpu_extra_qscratch = 0;
    cache->fpu_reg = 0;
    for(int i=0; i<8; ++i) {
        cache->x87cache[i] = -1;
@@ -440,7 +541,7 @@ void neoncacheUnwind(neoncache_t* cache)
        cache->ssecache[i*2+1].v = -1;
    }
    int x87reg = 0;
-    for(int i=0; i<24; ++i) {
+    for(int i=0; i<32; ++i) {
        if(cache->neoncache[i].v) {
            cache->fpuused[i] = 1;
            switch (cache->neoncache[i].t) {
@@ -455,6 +556,10 @@ void neoncacheUnwind(neoncache_t* cache)
                    cache->ssecache[cache->neoncache[i].n].write = (cache->neoncache[i].t==NEON_CACHE_XMMW)?1:0;
                    ++cache->fpu_reg;
                    break;
+                case NEON_CACHE_YMMR:
+                case NEON_CACHE_YMMW:
+                    cache->fpuused[i] = 0;  // YMM does not mark the fpu reg as used
+                    break;
                case NEON_CACHE_ST_F:
                case NEON_CACHE_ST_D:
                case NEON_CACHE_ST_I64:
@@ -472,11 +577,29 @@ void neoncacheUnwind(neoncache_t* cache)
            cache->fpuused[i] = 0;
        }
    }
+    // add back removed YMM
+    if(cache->ymm_removed) {
+        for(int i=0; i<16; ++i)
+            if(cache->ymm_removed&(1<<i)) {
+                int reg = cache->ymm_regs>>(i*4)&15;
+                if(reg>7)
+                    reg = reg - 8 + SCRATCH0;
+                else
+                    reg = reg + EMM0;
+                if(cache->neoncache[reg].v)
+                    printf_log(LOG_INFO, "Warning, recreating YMM%d on non empty slot %s", i, getCacheName(cache->neoncache[reg].t, cache->neoncache[reg].n));
+                cache->neoncache[reg].t = (cache->ymm_write&(1<<i))?NEON_CACHE_YMMW:NEON_CACHE_YMMR;
+                cache->neoncache[reg].n = i;
+            }
+        cache->ymm_regs = 0;
+        cache->ymm_write = cache->ymm_removed = 0;
+    }
+    cache->ymm_used = 0;
 }

 #define F8      *(uint8_t*)(addr++)
 #define F32S64  (uint64_t)(int64_t)*(int32_t*)(addr+=4, addr-4)
-// Get if ED will have the correct parity. Not emiting anything. Parity is 2 for DWORD or 3 for QWORD
+// Get if ED will have the correct parity. Not emitting anything. Parity is 2 for DWORD or 3 for QWORD
 int getedparity(dynarec_arm_t* dyn, int ninst, uintptr_t addr, uint8_t nextop, int parity, int delta)
 {
    (void)dyn; (void)ninst;
@@ -527,6 +650,8 @@ const char* getCacheName(int t, int n)
        case NEON_CACHE_MM: sprintf(buff, "MM%d", n); break;
        case NEON_CACHE_XMMW: sprintf(buff, "XMM%d", n); break;
        case NEON_CACHE_XMMR: sprintf(buff, "xmm%d", n); break;
+        case NEON_CACHE_YMMW: sprintf(buff, "YMM%d", n); break;
+        case NEON_CACHE_YMMR: sprintf(buff, "ymm%d", n); break;
        case NEON_CACHE_SCR: sprintf(buff, "Scratch"); break;
        case NEON_CACHE_NONE: buff[0]='\0'; break;
    }
@@ -537,7 +662,7 @@ void inst_name_pass3(dynarec_native_t* dyn, int ninst, const char* name, rex_t r
 {
    if(box64_dynarec_dump) {
        printf_x64_instruction(rex.is32bits?my_context->dec32:my_context->dec, &dyn->insts[ninst].x64, name);
-        dynarec_log(LOG_NONE, "%s%p: %d emitted opcodes, inst=%d, barrier=%d state=%d/%d(%d), %s=%X/%X, use=%X, need=%X/%X, sm=%d/%d",
+        dynarec_log(LOG_NONE, "%s%p: %d emitted opcodes, inst=%d, barrier=%d state=%d/%d/%d(%d:%d->%d:%d), %s=%X/%X, use=%X, need=%X/%X, sm=%d(%d/%d)",
            (box64_dynarec_dump>1)?"\e[32m":"",
            (void*)(dyn->native_start+dyn->insts[ninst].address),
            dyn->insts[ninst].size/4,
@@ -546,25 +671,49 @@ void inst_name_pass3(dynarec_native_t* dyn, int ninst, const char* name, rex_t r
            dyn->insts[ninst].x64.state_flags,
            dyn->f.pending,
            dyn->f.dfnone,
+            dyn->insts[ninst].f_entry.pending,
+            dyn->insts[ninst].f_entry.dfnone,
+            dyn->insts[ninst].f_exit.pending,
+            dyn->insts[ninst].f_exit.dfnone,
            dyn->insts[ninst].x64.may_set?"may":"set",
            dyn->insts[ninst].x64.set_flags,
            dyn->insts[ninst].x64.gen_flags,
            dyn->insts[ninst].x64.use_flags,
            dyn->insts[ninst].x64.need_before,
            dyn->insts[ninst].x64.need_after,
-            dyn->smread, dyn->smwrite);
+            dyn->smwrite, dyn->insts[ninst].will_write, dyn->insts[ninst].last_write);
+        if(dyn->insts[ninst].nat_flags_op) {
+            if(dyn->insts[ninst].nat_flags_op==NAT_FLAG_OP_TOUCH && dyn->insts[ninst].before_nat_flags)
+                printf_log(LOG_NONE, " NF:%d/read:%x", dyn->insts[ninst].nat_flags_op, dyn->insts[ninst].before_nat_flags);
+            else
+                printf_log(LOG_NONE, " NF:%d", dyn->insts[ninst].nat_flags_op);
+        }
+        if(dyn->insts[ninst].use_nat_flags || dyn->insts[ninst].set_nat_flags || dyn->insts[ninst].need_nat_flags)
+            printf_log(LOG_NONE, " nf:%hhx/%hhx/%hhx", dyn->insts[ninst].set_nat_flags, dyn->insts[ninst].use_nat_flags, dyn->insts[ninst].need_nat_flags);
+        if(dyn->insts[ninst].invert_carry)
+            printf_log(LOG_NONE, " CI");
+        if(dyn->insts[ninst].gen_inverted_carry)
+            printf_log(LOG_NONE, " gic");
+        if(dyn->insts[ninst].before_nat_flags&NF_CF)
+            printf_log(LOG_NONE, " %ccb", dyn->insts[ninst].normal_carry_before?'n':'i');
+        if(dyn->insts[ninst].need_nat_flags&NF_CF)
+            printf_log(LOG_NONE, " %cc", dyn->insts[ninst].normal_carry?'n':'i');
        if(dyn->insts[ninst].pred_sz) {
            dynarec_log(LOG_NONE, ", pred=");
            for(int ii=0; ii<dyn->insts[ninst].pred_sz; ++ii)
                dynarec_log(LOG_NONE, "%s%d", ii?"/":"", dyn->insts[ninst].pred[ii]);
        }
+        if(!dyn->insts[ninst].x64.alive)
+            dynarec_log(LOG_NONE, " not executed");
        if(dyn->insts[ninst].x64.jmp && dyn->insts[ninst].x64.jmp_insts>=0)
            dynarec_log(LOG_NONE, ", jmp=%d", dyn->insts[ninst].x64.jmp_insts);
        if(dyn->insts[ninst].x64.jmp && dyn->insts[ninst].x64.jmp_insts==-1)
            dynarec_log(LOG_NONE, ", jmp=out");
+        if(dyn->insts[ninst].x64.has_callret)
+            dynarec_log(LOG_NONE, ", callret");
        if(dyn->last_ip)
            dynarec_log(LOG_NONE, ", last_ip=%p", (void*)dyn->last_ip);
-        for(int ii=0; ii<24; ++ii) {
+        for(int ii=0; ii<32; ++ii) {
            switch(dyn->insts[ninst].n.neoncache[ii].t) {
                case NEON_CACHE_ST_D: dynarec_log(LOG_NONE, " D%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
                case NEON_CACHE_ST_F: dynarec_log(LOG_NONE, " S%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
@@ -572,11 +721,27 @@ void inst_name_pass3(dynarec_native_t* dyn, int ninst, const char* name, rex_t r
                case NEON_CACHE_MM: dynarec_log(LOG_NONE, " D%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
                case NEON_CACHE_XMMW: dynarec_log(LOG_NONE, " Q%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
                case NEON_CACHE_XMMR: dynarec_log(LOG_NONE, " Q%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
-                case NEON_CACHE_SCR: dynarec_log(LOG_NONE, " D%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
+                case NEON_CACHE_YMMW: dynarec_log(LOG_NONE, " Q%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
+                case NEON_CACHE_YMMR: dynarec_log(LOG_NONE, " Q%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
+                //case NEON_CACHE_SCR: dynarec_log(LOG_NONE, " D%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
                case NEON_CACHE_NONE:
                default:    break;
            }
        }
+        if(memcmp(dyn->insts[ninst].n.neoncache, dyn->n.neoncache, sizeof(dyn->n.neoncache))) {
+            dynarec_log(LOG_NONE, " %s(Change:", (box64_dynarec_dump>1)?"\e[1;91m":"");
+            for(int ii=0; ii<32; ++ii) if(dyn->insts[ninst].n.neoncache[ii].v!=dyn->n.neoncache[ii].v) {
+                dynarec_log(LOG_NONE, " V%d:%s", ii, getCacheName(dyn->n.neoncache[ii].t, dyn->n.neoncache[ii].n));
+                dynarec_log(LOG_NONE, "->%s", getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n));
+            }
+            dynarec_log(LOG_NONE, ")%s", (box64_dynarec_dump>1)?"\e[0;32m":"");
+        }
+        if(dyn->insts[ninst].n.ymm_used)
+            dynarec_log(LOG_NONE, " ymmUsed=%04x", dyn->insts[ninst].n.ymm_used);
+        if(dyn->ymm_zero || dyn->insts[ninst].ymm0_add || dyn->insts[ninst].ymm0_sub || dyn->insts[ninst].ymm0_out)
+            dynarec_log(LOG_NONE, " ymm0=(%04x/%04x+%04x-%04x=%04x)", dyn->ymm_zero, dyn->insts[ninst].ymm0_in, dyn->insts[ninst].ymm0_add ,dyn->insts[ninst].ymm0_sub, dyn->insts[ninst].ymm0_out);
+        if(dyn->insts[ninst].purge_ymm)
+            dynarec_log(LOG_NONE, " purgeYmm=%04x", dyn->insts[ninst].purge_ymm);
        if(dyn->n.stack || dyn->insts[ninst].n.stack_next || dyn->insts[ninst].n.x87stack)
            dynarec_log(LOG_NONE, " X87:%d/%d(+%d/-%d)%d", dyn->n.stack, dyn->insts[ninst].n.stack_next, dyn->insts[ninst].n.stack_push, dyn->insts[ninst].n.stack_pop, dyn->insts[ninst].n.x87stack);
        if(dyn->insts[ninst].n.combined1 || dyn->insts[ninst].n.combined2)
@@ -589,3 +754,269 @@ void print_opcode(dynarec_native_t* dyn, int ninst, uint32_t opcode)
 {
    dynarec_log(LOG_NONE, "\t%08x\t%s\n", opcode, arm64_print(opcode, (uintptr_t)dyn->block));
 }
+
+static void x87_reset(neoncache_t* n)
+{
+    for (int i=0; i<8; ++i)
+        n->x87cache[i] = -1;
+    n->tags = 0;
+    n->x87stack = 0;
+    n->stack = 0;
+    n->stack_next = 0;
+    n->stack_pop = 0;
+    n->stack_push = 0;
+    n->combined1 = n->combined2 = 0;
+    n->swapped = 0;
+    n->barrier = 0;
+    n->pushed = 0;
+    n->poped = 0;
+
+    for(int i=0; i<24; ++i)
+        if(n->neoncache[i].t == NEON_CACHE_ST_F
+         || n->neoncache[i].t == NEON_CACHE_ST_D
+         || n->neoncache[i].t == NEON_CACHE_ST_I64)
+            n->neoncache[i].v = 0;
+}
+
+static void mmx_reset(neoncache_t* n)
+{
+    n->mmxcount = 0;
+    for (int i=0; i<8; ++i)
+        n->mmxcache[i] = -1;
+}
+
+static void sse_reset(neoncache_t* n)
+{
+    for (int i=0; i<16; ++i)
+        n->ssecache[i].v = -1;
+    for (int i=0; i<32; ++i)
+        if(n->neoncache[i].t==NEON_CACHE_YMMR || n->neoncache[i].t==NEON_CACHE_YMMW)
+            n->neoncache[i].v = 0;
+}
+
+void fpu_reset(dynarec_native_t* dyn)
+{
+    x87_reset(&dyn->n);
+    mmx_reset(&dyn->n);
+    sse_reset(&dyn->n);
+    fpu_reset_reg(dyn);
+    dyn->ymm_zero = 0;
+}
+
+void fpu_reset_ninst(dynarec_native_t* dyn, int ninst)
+{
+    x87_reset(&dyn->insts[ninst].n);
+    mmx_reset(&dyn->insts[ninst].n);
+    sse_reset(&dyn->insts[ninst].n);
+    fpu_reset_reg_neoncache(&dyn->insts[ninst].n);
+
+}
+
+int fpu_is_st_freed(dynarec_native_t* dyn, int ninst, int st)
+{
+    return (dyn->n.tags&(0b11<<(st*2)))?1:0;
+}
+
+
+uint8_t mark_natflag(dynarec_arm_t* dyn, int ninst, uint8_t flag, int before)
+{
+    if(dyn->insts[ninst].x64.set_flags && !before) {
+        dyn->insts[ninst].set_nat_flags |= flag;
+        if(dyn->insts[ninst].x64.use_flags) {
+            dyn->insts[ninst].use_nat_flags |= flag;
+        }
+    } else {
+        if(before)
+            dyn->insts[ninst].use_nat_flags_before |= flag;
+        else
+            dyn->insts[ninst].use_nat_flags |= flag;
+    }
+    return flag;
+}
+
+uint8_t flag2native(uint8_t flags)
+{
+    uint8_t ret = 0;
+    #ifdef ARM64
+    if(flags&X_ZF) ret|=NF_EQ;
+    if(flags&X_SF) ret|=NF_SF;
+    if(flags&X_OF) ret|=NF_VF;
+    if(flags&X_CF) ret|=NF_CF;
+    #else
+    // no native flags on rv64 or la64
+    #endif
+    return ret;
+}
+
+int flagIsNative(uint8_t flags)
+{
+    if(flags&(X_AF|X_PF)) return 0;
+    return 1;
+}
+
+static uint8_t getNativeFlagsUsed(dynarec_arm_t* dyn, int start, uint8_t flags)
+{
+    // propagate and check wich flags are actually used
+    uint8_t used_flags = 0;
+    int nat_flags_used = 0;
+    int ninst = start;
+    while(ninst<dyn->size) {
+//printf_log(LOG_INFO, "getNativeFlagsUsed ninst:%d/%d, flags=%x, used_flags=%x(%d), nat_flags_op_before:%x, nat_flags_op:%x, need_after:%x\n", ninst, start, flags, used_flags, nat_flags_used, dyn->insts[ninst].nat_flags_op_before, dyn->insts[ninst].nat_flags_op, flag2native(dyn->insts[ninst].x64.need_after));
+        // check if this is an opcode that generate flags but consume flags before
+        if(dyn->insts[ninst].nat_flags_op_before)
+            return 0;
+        // check if nat flags are used "before"
+        if(dyn->insts[ninst].use_nat_flags_before)
+            nat_flags_used = 1;
+        if(dyn->insts[ninst].nat_flags_op==NAT_FLAG_OP_TOUCH && dyn->insts[ninst].use_nat_flags_before)
+            used_flags|=dyn->insts[ninst].use_nat_flags_before&flags;
+        // if the opcode generate flags, return
+        if(dyn->insts[ninst].nat_flags_op==NAT_FLAG_OP_TOUCH && (start!=ninst)) {
+            if(used_flags&~dyn->insts[ninst].set_nat_flags) {
+                // check partial changes that would destroy flag state
+                if(dyn->insts[ninst].use_nat_flags_before&flags)
+                    return nat_flags_used?used_flags:0;
+                // but also check if there is before needed
+                return 0;
+            }
+            return nat_flags_used?used_flags:0;
+        }
+        // check if there is a callret barrier
+        if(dyn->insts[ninst].x64.has_callret)
+            return 0;
+        // check if nat flags are used
+        if(dyn->insts[ninst].use_nat_flags)
+            nat_flags_used = 1;
+        // check if flags are used, but not the natives ones
+        if(ninst!=start && dyn->insts[ninst].x64.use_flags) {
+            if((flag2native(dyn->insts[ninst].x64.use_flags)&~(dyn->insts[ninst].use_nat_flags))&used_flags)
+                return 0;
+            // also check if the gen flags are compatible
+            if((dyn->insts[ninst].use_nat_flags)&~flags)
+                return 0;
+        }
+        // check if flags are generated without native option
+        if((start!=ninst) && dyn->insts[ninst].x64.gen_flags && (flag2native(dyn->insts[ninst].x64.gen_flags&dyn->insts[ninst].x64.need_after)&used_flags)) {
+            if(used_flags&~flag2native(dyn->insts[ninst].x64.gen_flags&dyn->insts[ninst].x64.need_after))
+                return 0;   // partial covert, not supported for now (TODO: this might be fixable)
+            else
+                return nat_flags_used?used_flags:0;  // full covert... End of propagation
+        }
+        // check if flags are still needed
+        if(!(flag2native(dyn->insts[ninst].x64.need_after)&flags))
+            return nat_flags_used?used_flags:0;
+        // check if flags are destroyed, cancel the use then
+        if(dyn->insts[ninst].nat_flags_op && (start!=ninst))
+            return 0;
+        // update used flags
+        used_flags |= (flag2native(dyn->insts[ninst].x64.need_after)&flags);
+        // go next
+        if(!dyn->insts[ninst].x64.has_next) {
+            // check if it's a jump to an opcode with only 1 preds, then just follow the jump
+            int jmp = dyn->insts[ninst].x64.jmp_insts;
+            if(dyn->insts[ninst].x64.jmp && (jmp!=-1) && (getNominalPred(dyn, jmp)==ninst))
+                ninst = jmp;
+            else
+                return nat_flags_used?used_flags:0;
+        } else
+            ++ninst;
+    }
+    return nat_flags_used?used_flags:0;
+}
+
+static void propagateNativeFlags(dynarec_arm_t* dyn, int start)
+{
+    int ninst = start;
+    // those are the flags generated by the opcode and used later on
+    uint8_t flags = dyn->insts[ninst].set_nat_flags&flag2native(dyn->insts[ninst].x64.need_after);
+    //check if they are actualy used before starting
+//printf_log(LOG_INFO, "propagateNativeFlags called for start=%d, flags=%x, will need:%x\n", start, flags, flag2native(dyn->insts[ninst].x64.need_after));
+    if(!flags) return;
+    // also check if some native flags are used but not genereated here
+    if(flag2native(dyn->insts[ninst].x64.need_after)&~flags) return;
+    uint8_t used_flags = getNativeFlagsUsed(dyn, start, flags);
+//printf_log(LOG_INFO, " will use:%x, carry:%d, generate inverted carry:%d\n", used_flags, used_flags&NF_CF, dyn->insts[ninst].gen_inverted_carry);
+    if(!used_flags) return; // the flags wont be used, so just cancel
+    int nc = dyn->insts[ninst].gen_inverted_carry?0:1;
+    int carry = used_flags&NF_CF;
+    // propagate
+    while(ninst<dyn->size) {
+        // check if this is an opcode that generate flags but consume flags before
+        if((start!=ninst) && dyn->insts[ninst].nat_flags_op==NAT_FLAG_OP_TOUCH) {
+            if(dyn->insts[ninst].use_nat_flags_before) {
+                dyn->insts[ninst].before_nat_flags |= used_flags;
+                if(carry) dyn->insts[ninst].normal_carry_before = nc;
+            }
+            // if the opcode generate flags, return
+            return;
+        }
+        // check if flags are generated without native option
+        if((start!=ninst) && dyn->insts[ninst].x64.gen_flags && (flag2native(dyn->insts[ninst].x64.gen_flags&dyn->insts[ninst].x64.need_after)&used_flags))
+            return;
+        // mark the opcode
+        uint8_t use_flags = flag2native(dyn->insts[ninst].x64.need_before|dyn->insts[ninst].x64.need_after);
+        if(dyn->insts[ninst].x64.use_flags) use_flags |= flag2native(dyn->insts[ninst].x64.use_flags);  // should not change anything
+//printf_log(LOG_INFO, " marking ninst=%d with %x | %x&%x => %x\n", ninst, dyn->insts[ninst].need_nat_flags, used_flags, use_flags, dyn->insts[ninst].need_nat_flags | (used_flags&use_flags));
+        dyn->insts[ninst].need_nat_flags |= used_flags&use_flags;
+        if(carry) dyn->insts[ninst].normal_carry = nc;
+        if(carry && dyn->insts[ninst].invert_carry) nc = 0;
+        // check if flags are still needed
+        if(!(flag2native(dyn->insts[ninst].x64.need_after)&used_flags))
+            return;
+        // go next
+        if(!dyn->insts[ninst].x64.has_next) {
+            // check if it's a jump to an opcode with only 1 preds, then just follow the jump
+            int jmp = dyn->insts[ninst].x64.jmp_insts;
+            if(dyn->insts[ninst].x64.jmp && (jmp!=-1) && (getNominalPred(dyn, jmp)==ninst))
+                ninst = jmp;
+            else
+                return;
+        } else
+            ++ninst;
+    }
+}
+
+void updateNativeFlags(dynarec_native_t* dyn)
+{
+    if(!box64_dynarec_nativeflags)
+        return;
+    // backward check if native flags are used
+    for(int ninst=0; ninst<dyn->size; ++ninst)
+        if(flag2native(dyn->insts[ninst].x64.gen_flags) && (dyn->insts[ninst].nat_flags_op==NAT_FLAG_OP_TOUCH)) {
+            propagateNativeFlags(dyn, ninst);
+        }
+}
+
+void rasNativeState(dynarec_arm_t* dyn, int ninst)
+{
+    dyn->insts[ninst].nat_flags_op = dyn->insts[ninst].set_nat_flags = dyn->insts[ninst].use_nat_flags = dyn->insts[ninst].need_nat_flags = 0;
+}
+
+int nativeFlagsNeedsTransform(dynarec_arm_t* dyn, int ninst)
+{
+    int jmp = dyn->insts[ninst].x64.jmp_insts;
+    if(jmp<0)
+        return 0;
+    if(!dyn->insts[ninst].x64.need_after || !dyn->insts[jmp].x64.need_before)
+        return 0;
+    if(dyn->insts[ninst].set_nat_flags)
+        return 0;
+    uint8_t flags_before = dyn->insts[ninst].need_nat_flags;
+    uint8_t nc_before = dyn->insts[ninst].normal_carry;
+    if(dyn->insts[ninst].invert_carry)
+        nc_before = 0;
+    uint8_t flags_after = dyn->insts[jmp].need_nat_flags;
+    uint8_t nc_after = dyn->insts[jmp].normal_carry;
+    if(dyn->insts[jmp].nat_flags_op==NAT_FLAG_OP_TOUCH) {
+        flags_after = dyn->insts[jmp].before_nat_flags;
+        nc_after = dyn->insts[jmp].normal_carry_before;
+    }
+    uint8_t flags_x86 = flag2native(dyn->insts[jmp].x64.need_before);
+    flags_x86 &= ~flags_after;
+    if((flags_before&NF_CF) && (flags_after&NF_CF) && (nc_before!=nc_after))
+        return 1;
+    // all flags_after should be present and none remaining flags_x86 
+    if(((flags_before&flags_after)!=flags_after) || (flags_before&flags_x86))
+        return 1;
+    return 0;
+}
@@ -4,21 +4,32 @@
 #include "../dynarec_native_functions.h"

 #define SCRATCH0    24
+#define XMM0    0
+#define XMM8    16
+#define X870    8
+#define EMM0    8
+

 // Get an FPU scratch reg
-int fpu_get_scratch(dynarec_arm_t* dyn);
+int fpu_get_scratch(dynarec_arm_t* dyn, int ninst);
+// Get 2 consecutive FPU scratch reg
+int fpu_get_double_scratch(dynarec_arm_t* dyn, int ninst);
 // Reset scratch regs counter
 void fpu_reset_scratch(dynarec_arm_t* dyn);
 // Get an x87 double reg
-int fpu_get_reg_x87(dynarec_arm_t* dyn, int t, int n);
+int fpu_get_reg_x87(dynarec_arm_t* dyn, int ninst, int t, int n);
 // Get an MMX double reg
-int fpu_get_reg_emm(dynarec_arm_t* dyn, int emm);
+int fpu_get_reg_emm(dynarec_arm_t* dyn, int ninst, int emm);
 // Get an XMM quad reg
 int fpu_get_reg_xmm(dynarec_arm_t* dyn, int t, int xmm);
 // Free a FPU/MMX/XMM reg
 void fpu_free_reg(dynarec_arm_t* dyn, int reg);
 // Reset fpu regs counter
 void fpu_reset_reg(dynarec_arm_t* dyn);
+// internal YMM handling
+int internal_mark_ymm(dynarec_arm_t* dyn, int t, int ymm, int reg);
+// is ymm neoncache[reg] one of k1, k2, k3?
+int is_ymm_to_keep(dynarec_arm_t* dyn, int reg, int k1, int k2, int k3);

 // ---- Neon cache functions
 // Get type for STx
@@ -40,6 +51,16 @@ int neoncache_combine_st(dynarec_arm_t* dyn, int ninst, int a, int b);  // with
 // Do not allow i64 type
 int neoncache_no_i64(dynarec_arm_t* dyn, int ninst, int st, int a);

+// transform x86 flags to native flags
+uint8_t flag2native(uint8_t flags);
+// mark a instruction as using/generating flags. return flag
+uint8_t mark_natflag(dynarec_arm_t* dyn, int ninst, uint8_t flag, int before);
+// propage the use of nativeflags or not (done between step 0 and step 1)
+void updateNativeFlags(dynarec_arm_t* dyn);
+// raz arm speicifc state when an opcode is unused
+void rasNativeState(dynarec_arm_t* dyn, int ninst);
+// check if natives flags needs some tranform to/from x86 flags
+int nativeFlagsNeedsTransform(dynarec_arm_t* dyn, int ninst);

 // FPU Cache transformation (for loops) // Specific, need to be written by backend
 int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst);
@@ -47,11 +68,18 @@ int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst);
 // Undo the changes of a neoncache to get the status before the instruction
 void neoncacheUnwind(neoncache_t* cache);

-// Get if ED will have the correct parity. Not emiting anything. Parity is 2 for DWORD or 3 for QWORD
+// Get if ED will have the correct parity. Not emitting anything. Parity is 2 for DWORD or 3 for QWORD
 int getedparity(dynarec_native_t* dyn, int ninst, uintptr_t addr, uint8_t nextop, int parity, int delta);

 const char* getCacheName(int t, int n);

 void inst_name_pass3(dynarec_native_t* dyn, int ninst, const char* name, rex_t rex);
 void print_opcode(dynarec_native_t* dyn, int ninst, uint32_t opcode);
+
+// reset the cache
+void fpu_reset(dynarec_native_t* dyn);
+void fpu_reset_ninst(dynarec_native_t* dyn, int ninst);
+
+// is st freed
+int fpu_is_st_freed(dynarec_native_t* dyn, int ninst, int st);
 #endif //__DYNAREC_ARM_FUNCTIONS_H__
@@ -2,10 +2,14 @@

 #include "arm64_emitter.h"

-#define EMIT(A) *block = (A); ++block
+#define EMIT(A)       \
+    do {              \
+        *block = (A); \
+        ++block;      \
+    } while (0)
 void CreateJmpNext(void* addr, void* next)
 {
    uint32_t* block = (uint32_t*)addr;
    LDRx_literal(x2, (intptr_t)next - (intptr_t)addr);
    BR(x2);
-}
+}
@@ -5,28 +5,22 @@
    dyn->insts[ninst].x64.addr = addr;  \
    if(ninst) dyn->insts[ninst-1].x64.size = dyn->insts[ninst].x64.addr - dyn->insts[ninst-1].x64.addr

-#define MESSAGE(A, ...)  
+#define MESSAGE(A, ...) do {} while (0)
 #define MAYSETFLAGS()   dyn->insts[ninst].x64.may_set = 1
 #define READFLAGS(A)    \
        dyn->insts[ninst].x64.use_flags = A; dyn->f.dfnone = 1;\
        dyn->f.pending=SF_SET
 #define SETFLAGS(A,B)   \
        dyn->insts[ninst].x64.set_flags = A;    \
-        dyn->insts[ninst].x64.state_flags = B;  \
+        dyn->insts[ninst].x64.state_flags = (B)&~SF_DF;  \
        dyn->f.pending=(B)&SF_SET_PENDING;      \
-        dyn->f.dfnone=((B)&SF_SET)?1:0;
-#define EMIT(A)     
-#define JUMP(A, C)         add_jump(dyn, ninst); add_next(dyn, (uintptr_t)A); SMEND(); dyn->insts[ninst].x64.jmp = A; dyn->insts[ninst].x64.jmp_cond = C
+        dyn->f.dfnone=((B)&SF_SET)?(((B)==SF_SET_NODF)?0:1):0;
+#define EMIT(A)         dyn->native_size+=4
+#define JUMP(A, C)         add_jump(dyn, ninst); add_next(dyn, (uintptr_t)A); SMEND(); dyn->insts[ninst].x64.jmp = A; dyn->insts[ninst].x64.jmp_cond = C; dyn->insts[ninst].x64.jmp_insts = 0
 #define BARRIER(A)      if(A!=BARRIER_MAYBE) {fpu_purgecache(dyn, ninst, 0, x1, x2, x3); dyn->insts[ninst].x64.barrier = A;} else dyn->insts[ninst].barrier_maybe = 1
-#define BARRIER_NEXT(A) dyn->insts[ninst].x64.barrier_next = A
 #define SET_HASCALLRET()    dyn->insts[ninst].x64.has_callret = 1
 #define NEW_INST \
        ++dyn->size;                            \
-        if(dyn->size+3>=dyn->cap) {             \
-                dyn->insts = (instruction_native_t*)dynaRealloc(dyn->insts, sizeof(instruction_native_t)*dyn->cap*2);\
-                memset(&dyn->insts[dyn->cap], 0, sizeof(instruction_native_t)*dyn->cap);   \
-                dyn->cap *= 2;                  \
-        }                                       \
        dyn->insts[ninst].x64.addr = ip;        \
        dyn->n.combined1 = dyn->n.combined2 = 0;\
        dyn->n.swapped = 0; dyn->n.barrier = 0; \
@@ -36,14 +30,16 @@
 #define INST_EPILOG                             \
        dyn->insts[ninst].f_exit = dyn->f;      \
        dyn->insts[ninst].n = dyn->n;           \
+        if(dyn->insts[ninst].nat_flags_op==NAT_FLAG_OP_TOUCH && !dyn->insts[ninst].set_nat_flags)       \
+                dyn->insts[ninst].nat_flags_op=NAT_FLAG_OP_UNUSABLE;                                    \
        dyn->insts[ninst].x64.has_next = (ok>0)?1:0;
 #define INST_NAME(name) 
 #define DEFAULT                         \
        --dyn->size;                    \
        *ok = -1;                       \
-        if(box64_dynarec_log>=LOG_INFO || box64_dynarec_dump || box64_dynarec_missing) {\
+        if(box64_dynarec_log>=LOG_INFO || box64_dynarec_dump || box64_dynarec_missing==1) {\
        dynarec_log(LOG_NONE, "%p: Dynarec stopped because of %sOpcode %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X", \
-        (void*)ip, rex.is32bits?"32bits ":"",\
+        (void*)ip, rex.is32bits?"x86 ":"x64 ",\
        PKip(0),                        \
        PKip(1), PKip(2), PKip(3),      \
        PKip(4), PKip(5), PKip(6),      \
@@ -53,3 +49,18 @@
        printFunctionAddr(ip, " => ");  \
        dynarec_log(LOG_NONE, "\n");    \
        }
+
+#define FEMIT(A)        dyn->insts[ninst].nat_flags_op = dyn->insts[ninst].x64.set_flags?NAT_FLAG_OP_TOUCH:NAT_FLAG_OP_UNUSABLE
+#define IFNATIVE(A)     if(mark_natflag(dyn, ninst, A, 0))
+#define IFNATIVEN(A)    if(mark_natflag(dyn, ninst, A, 0))
+#define IFX(A)  if((dyn->insts[ninst].x64.set_flags&(A)))
+#define IFX2(A, B)  if((dyn->insts[ninst].x64.set_flags&(A)) B)
+#define IFX_PENDOR0  if((dyn->insts[ninst].x64.set_flags&(X_PEND) || !dyn->insts[ninst].x64.set_flags))
+#define IFXX(A) if((dyn->insts[ninst].x64.set_flags==(A)))
+#define IFX2X(A, B) if((dyn->insts[ninst].x64.set_flags==(A) || dyn->insts[ninst].x64.set_flags==(B) || dyn->insts[ninst].x64.set_flags==((A)|(B))))
+#define IFXN(A, B)  if((dyn->insts[ninst].x64.set_flags&(A) && !(dyn->insts[ninst].x64.set_flags&(B))))
+#define IFXNATIVE(X, N)  if((dyn->insts[ninst].x64.set_flags&(X)) && mark_natflag(dyn, ninst, N, 0))
+#define GEN_INVERTED_CARRY()        dyn->insts[ninst].gen_inverted_carry = 1
+#define IFNATIVE_BEFORE(A)     if(mark_natflag(dyn, ninst, A, 1))
+#define INVERT_CARRY(A) dyn->insts[ninst].invert_carry = 1
+#define INVERT_CARRY_BEFORE(A) dyn->insts[ninst].invert_carry_before = 1
@@ -1,7 +1,17 @@
 #define INIT    
 #define FINI
-#define MESSAGE(A, ...)  
-#define EMIT(A)     
+#define MESSAGE(A, ...) do {} while (0)
+#define EMIT(A) do {} while (0)
+#define MAYSETFLAGS()   dyn->insts[ninst].x64.may_set = 1
+#define SET_NODF()      \
+        if(!dyn->insts[ninst].x64.gen_flags && !dyn->insts[ninst].x64.use_flags)   \
+                propagate_nodf(dyn, ninst);     \
+        dyn->f.dfnone = 0
+#define SETFLAGS(A,B)   \
+        dyn->insts[ninst].x64.set_flags = A;    \
+        dyn->insts[ninst].x64.state_flags = (B)&~SF_DF;  \
+        dyn->f.pending=(B)&SF_SET_PENDING;      \
+        dyn->f.dfnone=((B)&SF_SET)?(((B)==SF_SET_NODF)?0:1):0;
 #define NEW_INST                                \
        dyn->insts[ninst].f_entry = dyn->f;     \
        dyn->n.combined1 = dyn->n.combined2 = 0;\
@@ -5,14 +5,15 @@
                dyn->insts_size += 1+((dyn->insts[ninst].x64.size>(dyn->insts[ninst].size/4))?dyn->insts[ninst].x64.size:(dyn->insts[ninst].size/4))/15; \
        }

-#define MESSAGE(A, ...)  
+#define MESSAGE(A, ...) do {} while (0)
 #define EMIT(A)     do{dyn->insts[ninst].size+=4; dyn->native_size+=4;}while(0)
 #define NEW_INST                                                                                        \
        if(ninst) {                                                                                     \
                dyn->insts[ninst].address = (dyn->insts[ninst-1].address+dyn->insts[ninst-1].size);     \
                dyn->insts_size += 1+((dyn->insts[ninst-1].x64.size>(dyn->insts[ninst-1].size/4))?dyn->insts[ninst-1].x64.size:(dyn->insts[ninst-1].size/4))/15; \
+                dyn->insts[ninst].ymm0_pass2 = dyn->ymm_zero;   \
        }
 #define INST_EPILOG dyn->insts[ninst].epilog = dyn->native_size; 
 #define INST_NAME(name) 
 #define TABLE64(A, V)   {Table64(dyn, (V), 2); EMIT(0);}
-#define FTABLE64(A, V)  {mmx87_regs_t v = {.d = V}; Table64(dyn, v.q, 2); EMIT(0);}
+#define FTABLE64(A, V)  {mmx87_regs_t v = {.d = V}; Table64(dyn, v.q, 2); EMIT(0);}
@@ -14,8 +14,11 @@

 #define MESSAGE(A, ...)  if(box64_dynarec_dump) dynarec_log(LOG_NONE, __VA_ARGS__)
 #define NEW_INST        \
-    if(ninst)                                                   \
-        addInst(dyn->instsize, &dyn->insts_size, dyn->insts[ninst-1].x64.size, dyn->insts[ninst-1].size/4);
+    if(ninst) {                                                  \
+        if(dyn->insts[ninst].address!=(uintptr_t)dyn->block-(uintptr_t)dyn->native_start) dyn->abort = 1;   \
+        addInst(dyn->instsize, &dyn->insts_size, dyn->insts[ninst-1].x64.size, dyn->insts[ninst-1].size/4); \
+        dyn->insts[ninst].ymm0_pass3 = dyn->ymm_zero;   \
+    }
 #define INST_EPILOG     
 #define INST_NAME(name) inst_name_pass3(dyn, ninst, name, rex)
 #define TABLE64(A, V)   {int val64offset = Table64(dyn, (V), 3); MESSAGE(LOG_DUMP, "  Table64: 0x%lx\n", (V)); LDRx_literal(A, val64offset);}
@@ -9,6 +9,20 @@ typedef struct instsize_s instsize_t;

 #define BARRIER_MAYBE   8

+#define NF_EQ   (1<<0)
+#define NF_SF   (1<<1)
+#define NF_VF   (1<<2)
+#define NF_CF   (1<<3)
+
+// Nothing happens to the native flags
+#define NAT_FLAG_OP_NONE        0
+// Native flags are touched on this opcode
+#define NAT_FLAG_OP_TOUCH       1
+// Native flags are destroyed and unusable
+#define NAT_FLAG_OP_UNUSABLE    2
+// Native flags usaged are canceled here
+#define NAT_FLAG_OP_CANCELED    3
+
 #define NEON_CACHE_NONE     0
 #define NEON_CACHE_ST_D     1
 #define NEON_CACHE_ST_F     2
@@ -16,7 +30,9 @@ typedef struct instsize_s instsize_t;
 #define NEON_CACHE_MM       4
 #define NEON_CACHE_XMMW     5
 #define NEON_CACHE_XMMR     6
-#define NEON_CACHE_SCR      7
+#define NEON_CACHE_YMMW     7
+#define NEON_CACHE_YMMR     8
+#define NEON_CACHE_SCR      9
 typedef union neon_cache_s {
    int8_t           v;
    struct {
@@ -33,7 +49,7 @@ typedef union sse_cache_s {
 } sse_cache_t;
 typedef struct neoncache_s {
    // Neon cache
-    neon_cache_t        neoncache[24];
+    neon_cache_t        neoncache[32];
    int8_t              stack;
    int8_t              stack_next;
    int8_t              stack_pop;
@@ -42,23 +58,30 @@ typedef struct neoncache_s {
    uint8_t             combined2;
    uint8_t             swapped;        // the combined reg were swapped
    uint8_t             barrier;        // is there a barrier at instruction epilog?
+    uint8_t             pushed;         // positive pushed value (to check for overflow)
+    uint8_t             poped;          // positive poped value (to check for underflow)
    uint32_t            news;           // bitmask, wich neoncache are new for this opcode
    // fpu cache
    int8_t              x87cache[8];    // cache status for the 8 x87 register behind the fpu stack
    int8_t              x87reg[8];      // reg used for x87cache entry
+    int16_t             tags;           // similar to fpu_tags
    int8_t              mmxcache[8];    // cache status for the 8 MMX registers
    sse_cache_t         ssecache[16];   // cache status for the 16 SSE(2) registers
-    int8_t              fpuused[24];    // all 0..24 double reg from fpu, used by x87, sse and mmx
+    int8_t              fpuused[32];    // all neon regs, used by x87, mmx, sse and avx
    int8_t              x87stack;       // cache stack counter
    int8_t              mmxcount;       // number of mmx register used (not both mmx and x87 at the same time)
    int8_t              fpu_scratch;    // scratch counter
-    int8_t              fpu_extra_qscratch; // some opcode need an extra quad scratch register
    int8_t              fpu_reg;        // x87/sse/mmx reg counter
+    uint16_t            ymm_used;       // mask of the ymm regs used in this opcode
+    uint64_t            ymm_regs;       // 4bits (0-15) position of 16 ymmXX regs removed
+    uint16_t            ymm_write;      // 1bits of ymmXX removed write
+    uint16_t            ymm_removed;    // 1bits if ymmXX was removed
 } neoncache_t;

 typedef struct flagcache_s {
    int                 pending;    // is there a pending flags here, or to check?
-    int                 dfnone;     // if deferred flags is already set to df_none
+    uint8_t             dfnone;     // if deferred flags is already set to df_none
+    uint8_t             dfnone_here;// defered flags is cleared in this opcode
 } flagcache_t;

 typedef struct instruction_arm64_s {
@@ -75,8 +98,30 @@ typedef struct instruction_arm64_s {
    uintptr_t           marklock;
    int                 pass2choice;// value for choices that are fixed on pass2 for pass3
    uintptr_t           natcall;
-    int                 retn;
-    int                 barrier_maybe;
+    uint16_t            retn;
+    uint16_t            purge_ymm;  // need to purge some ymm
+    uint16_t            ymm0_in;    // bitmap of ymm to zero at purge
+    uint16_t            ymm0_add;   // the ymm0 added by the opcode
+    uint16_t            ymm0_sub;   // the ymm0 removed by the opcode
+    uint16_t            ymm0_out;   // the ymm0 at th end of the opcode
+    uint16_t            ymm0_pass2, ymm0_pass3;
+    uint8_t             barrier_maybe;
+    uint8_t             will_write:2; // [strongmem] will write to memory
+    uint8_t             last_write:1; // [strongmem] the last write in a SEQ
+    uint8_t             lock:1;       // [strongmem] lock semantic
+    uint8_t             wfe:1;        // opcode uses sevl + wfe
+    uint8_t             set_nat_flags;  // 0 or combinaison of native flags define
+    uint8_t             use_nat_flags;  // 0 or combinaison of native flags define
+    uint8_t             use_nat_flags_before;  // 0 or combinaison of native flags define
+    uint8_t             nat_flags_op:4;// what happens to native flags here
+    uint8_t             nat_flags_op_before:4;// what happens to native flags here
+    uint8_t             before_nat_flags;  // 0 or combinaison of native flags define
+    uint8_t             need_nat_flags;
+    unsigned            gen_inverted_carry:1;
+    unsigned            normal_carry:1;
+    unsigned            normal_carry_before:1;
+    unsigned            invert_carry:1; // this opcode force an inverted carry
+    unsigned            df_notneeded:1;
    flagcache_t         f_exit;     // flags status at end of instruction
    neoncache_t         n;          // neoncache at end of instruction (but before poping)
    flagcache_t         f_entry;    // flags status before the instruction begin
@@ -109,21 +154,23 @@ typedef struct dynarec_arm_s {
    dynablock_t*        dynablock;
    instsize_t*         instsize;
    size_t              insts_size; // size of the instruction size array (calculated)
-    uint8_t             smread;     // for strongmem model emulation
-    uint8_t             smwrite;    // for strongmem model emulation
    uintptr_t           forward;    // address of the last end of code while testing forward
    uintptr_t           forward_to; // address of the next jump to (to check if everything is ok)
    int32_t             forward_size;   // size at the forward point
    int                 forward_ninst;  // ninst at the forward point
+    uint16_t            ymm_zero;   // bitmap of ymm to zero at purge
+    uint8_t             smwrite;    // for strongmem model emulation
    uint8_t             doublepush;
    uint8_t             doublepop;
    uint8_t             always_test;
+    uint8_t             abort;      // abort the creation of the block
 } dynarec_arm_t;

 void add_next(dynarec_arm_t *dyn, uintptr_t addr);
 uintptr_t get_closest_next(dynarec_arm_t *dyn, uintptr_t addr);
 void add_jump(dynarec_arm_t *dyn, int ninst);
 int get_first_jump(dynarec_arm_t *dyn, int next);
+int get_first_jump_addr(dynarec_arm_t *dyn, uintptr_t next);
 int is_nops(dynarec_arm_t *dyn, uintptr_t addr, int n);
 int is_instructions(dynarec_arm_t *dyn, uintptr_t addr, int n);

@@ -134,9 +181,11 @@ void CreateJmpNext(void* addr, void* next);
 #define GO_TRACE(A, B, s0)  \
    GETIP(addr);            \
    MOVx_REG(x1, xRIP);     \
+    MRS_nzcv(s0);           \
    STORE_XEMU_CALL(xRIP);  \
    MOV32w(x2, B);          \
-    CALL(A, -1);            \
+    CALL_(A, -1, s0);       \
+    MSR_nzcv(s0);           \
    LOAD_XEMU_CALL(xRIP)

 #endif //__DYNAREC_ARM_PRIVATE_H_
@@ -19,20 +19,22 @@
 #include "dynarec_private.h"
 #include "elfloader.h"
 #include "bridge.h"
+#include "signals.h"

 #include "dynarec_native.h"
 #include "native_lock.h"

 #include "custommem.h"
 #include "khash.h"
+#include "rbtree.h"

 uint32_t X31_hash_code(void* addr, int len)
 {
    if(!len) return 0;
    uint8_t* p = (uint8_t*)addr;
-	int32_t h = *p;
-	for (--len, ++p; len; --len, ++p) h = (h << 5) - h + (int32_t)*p;
-	return (uint32_t)h;
+    int32_t h = *p;
+    for (--len, ++p; len; --len, ++p) h = (h << 5) - h + (int32_t)*p;
+    return (uint32_t)h;
 }

 dynablock_t* InvalidDynablock(dynablock_t* db, int need_lock)
@@ -47,6 +49,18 @@ dynablock_t* InvalidDynablock(dynablock_t* db, int need_lock)
            mutex_lock(&my_context->mutex_dyndump);
        db->done = 0;
        db->gone = 1;
+        uintptr_t db_size = db->x64_size;
+        if(db_size && my_context) {
+            uint32_t n = rb_get(my_context->db_sizes, db_size);
+            if(n>1)
+                rb_set(my_context->db_sizes, db_size, db_size+1, n-1);
+            else
+                rb_unset(my_context->db_sizes, db_size, db_size+1);
+            if(db_size == my_context->max_db_size) {
+                my_context->max_db_size = rb_get_righter(my_context->db_sizes);
+                dynarec_log(LOG_INFO, "BOX64 Dynarec: lower max_db=%d\n", my_context->max_db_size);
+            }
+        }
        if(need_lock)
            mutex_unlock(&my_context->mutex_dyndump);
    }
@@ -81,6 +95,18 @@ void FreeDynablock(dynablock_t* db, int need_lock)
        dynarec_log(LOG_DEBUG, " -- FreeDyrecMap(%p, %d)\n", db->actual_block, db->size);
        db->done = 0;
        db->gone = 1;
+        uintptr_t db_size = db->x64_size;
+        if(db_size && my_context) {
+            uint32_t n = rb_get(my_context->db_sizes, db_size);
+            if(n>1)
+                rb_set(my_context->db_sizes, db_size, db_size+1, n-1);
+            else
+                rb_unset(my_context->db_sizes, db_size, db_size+1);
+            if(db_size == my_context->max_db_size) {
+                my_context->max_db_size = rb_get_righter(my_context->db_sizes);
+                dynarec_log(LOG_INFO, "BOX64 Dynarec: lower max_db=%d\n", my_context->max_db_size);
+            }
+        }
        if(db->previous)
            FreeInvalidDynablock(db->previous, 0);
        FreeDynarecMap((uintptr_t)db->actual_block);
@@ -120,15 +146,6 @@ static int IntervalIntersects(uintptr_t start1, uintptr_t end1, uintptr_t start2
    return 1;
 }

-static int MarkedDynablock(dynablock_t* db)
-{
-    if(db) {
-        if(getNeedTest((uintptr_t)db->x64_addr))
-            return 1; // already done
-    }
-    return 0;
-}
-
 void MarkRangeDynablock(dynablock_t* db, uintptr_t addr, uintptr_t size)
 {
    // Mark will try to find *any* blocks that intersect the range to mark
@@ -155,15 +172,6 @@ int FreeRangeDynablock(dynablock_t* db, uintptr_t addr, uintptr_t size)
 dynablock_t *AddNewDynablock(uintptr_t addr)
 {
    dynablock_t* block;
-    #if 0
-    // check if memory as the correct flags
-    int prot = getProtection(addr);
-    if(!(prot&(PROT_EXEC|PROT_DYNAREC|PROT_DYNAREC_R))) {
-        dynarec_log(LOG_VERBOSE, "Block asked on a memory with no execution flags 0x%02X\n", prot);
-        return NULL;
-    }
-    
-    #endif
    // create and add new block
    dynarec_log(LOG_VERBOSE, "Ask for DynaRec Block creation @%p\n", (void*)addr);
    block = (dynablock_t*)customCalloc(1, sizeof(dynablock_t));
@@ -191,9 +199,13 @@ static dynablock_t* internalDBGetBlock(x64emu_t* emu, uintptr_t addr, uintptr_t
 {
    if(hasAlternate((void*)addr))
        return NULL;
+    const uint32_t req_prot = (box64_pagesize==4096)?(PROT_EXEC|PROT_READ):PROT_READ;
    dynablock_t* block = getDB(addr);
-    if(block || !create)
+    if(block || !create) {
+        if(block && getNeedTest(addr) && (getProtection(addr)&req_prot)!=req_prot)
+            block = NULL;
        return block;
+    }

    if(need_lock) {
        if(box64_dynarec_wait) {
@@ -204,11 +216,17 @@ static dynablock_t* internalDBGetBlock(x64emu_t* emu, uintptr_t addr, uintptr_t
        }
        block = getDB(addr);    // just in case
        if(block) {
+            if(block && getNeedTest(addr) && (getProtection_fast(addr)&req_prot)!=req_prot)
+                block = NULL;
            mutex_unlock(&my_context->mutex_dyndump);
            return block;
        }
    }
-    
+    if((getProtection_fast(addr)&req_prot)!=req_prot) {// cannot be run, get out of the Dynarec
+        if(need_lock)
+            mutex_unlock(&my_context->mutex_dyndump);
+        return NULL;
+    }
    block = AddNewDynablock(addr);

    // fill the block
@@ -228,17 +246,20 @@ static dynablock_t* internalDBGetBlock(x64emu_t* emu, uintptr_t addr, uintptr_t
    }
    // check size
    if(block) {
-        int blocksz = block->x64_size;
-        if(blocksz>my_context->max_db_size)
-            my_context->max_db_size = blocksz;
        // fill-in jumptable
        if(!addJumpTableIfDefault64(block->x64_addr, block->dirty?block->jmpnext:block->block)) {
            FreeDynablock(block, 0);
            block = getDB(addr);
            MarkDynablock(block);   // just in case...
        } else {
-            if(block->x64_size)
+            if(block->x64_size) {
+                if(block->x64_size>my_context->max_db_size) {
+                    my_context->max_db_size = block->x64_size;
+                    dynarec_log(LOG_INFO, "BOX64 Dynarec: higher max_db=%d\n", my_context->max_db_size);
+                }
                block->done = 1;    // don't validate the block if the size is null, but keep the block
+                rb_set(my_context->db_sizes, block->x64_size, block->x64_size+1, rb_get(my_context->db_sizes, block->x64_size)+1);
+            }
        }
    }
    if(need_lock)
@@ -251,33 +272,17 @@ static dynablock_t* internalDBGetBlock(x64emu_t* emu, uintptr_t addr, uintptr_t

 dynablock_t* DBGetBlock(x64emu_t* emu, uintptr_t addr, int create, int is32bits)
 {
+    if(isInHotPage(addr))
+        return NULL;
    dynablock_t *db = internalDBGetBlock(emu, addr, addr, create, 1, is32bits);
    if(db && db->done && db->block && getNeedTest(addr)) {
        if(db->always_test)
            sched_yield();  // just calm down...
-        if(AreaInHotPage((uintptr_t)db->x64_addr, (uintptr_t)db->x64_addr + db->x64_size - 1)) {
-            emu->test.test = 0;
-            if(box64_dynarec_fastpage) {
-                uint32_t hash = X31_hash_code(db->x64_addr, db->x64_size);
-                if(hash==db->hash) { // seems ok, run it without reprotecting it
-                    setJumpTableIfRef64(db->x64_addr, db->block, db->jmpnext);
-                    return db;
-                }
-                db->done = 0;   // invalidating the block, it's already not good
-                dynarec_log(LOG_DEBUG, "Invalidating block %p from %p:%p (hash:%X/%X) for %p\n", db, db->x64_addr, db->x64_addr+db->x64_size-1, hash, db->hash, (void*)addr);
-                // Free db, it's now invalid!
-                FreeDynablock(db, 1);
-                return NULL;    // not building a new one, it's still a hotpage
-            } else {
-                dynarec_log(LOG_INFO, "Not running block %p from %p:%p with for %p because it's in a hotpage\n", db, db->x64_addr, db->x64_addr+db->x64_size-1, (void*)addr);
-                return NULL;
-            }
-        }
        uint32_t hash = X31_hash_code(db->x64_addr, db->x64_size);
        int need_lock = mutex_trylock(&my_context->mutex_dyndump);
        if(hash!=db->hash) {
            db->done = 0;   // invalidating the block
-            dynarec_log(LOG_DEBUG, "Invalidating block %p from %p:%p (hash:%X/%X) for %p\n", db, db->x64_addr, db->x64_addr+db->x64_size-1, hash, db->hash, (void*)addr);
+            dynarec_log(LOG_DEBUG, "Invalidating block %p from %p:%p (hash:%X/%X, always_test:%d) for %p\n", db, db->x64_addr, db->x64_addr+db->x64_size-1, hash, db->hash, db->always_test,(void*)addr);
            // Free db, it's now invalid!
            dynablock_t* old = InvalidDynablock(db, need_lock);
            // start again... (will create a new block)
@@ -289,12 +294,11 @@ dynablock_t* DBGetBlock(x64emu_t* emu, uintptr_t addr, int create, int is32bits)
            } else
                FreeInvalidDynablock(old, need_lock);
        } else {
-            dynarec_log(LOG_DEBUG, "Validating block %p from %p:%p (hash:%X) for %p\n", db, db->x64_addr, db->x64_addr+db->x64_size-1, db->hash, (void*)addr);
-            protectDB((uintptr_t)db->x64_addr, db->x64_size);
-            // fill back jumptable
-            if(isprotectedDB((uintptr_t)db->x64_addr, db->x64_size) && !db->always_test) {
-                setJumpTableIfRef64(db->x64_addr, db->block, db->jmpnext);
-            }
+            dynarec_log(LOG_DEBUG, "Validating block %p from %p:%p (hash:%X, always_test:%d) for %p\n", db, db->x64_addr, db->x64_addr+db->x64_size-1, db->hash, db->always_test, (void*)addr);
+            if(db->always_test)
+                protectDB((uintptr_t)db->x64_addr, db->x64_size);
+            else
+                protectDBJumpTable((uintptr_t)db->x64_addr, db->x64_size, db->block, db->jmpnext);
        }
        if(!need_lock)
            mutex_unlock(&my_context->mutex_dyndump);
@@ -328,11 +332,10 @@ dynablock_t* DBAlternateBlock(x64emu_t* emu, uintptr_t addr, uintptr_t filladdr,
            } else
                FreeInvalidDynablock(old, need_lock);
        } else {
-            protectDB((uintptr_t)db->x64_addr, db->x64_size);
-            // fill back jumptable
-            if(isprotectedDB((uintptr_t)db->x64_addr, db->x64_size) && !db->always_test) {
-                setJumpTableIfRef64(db->x64_addr, db->block, db->jmpnext);
-            }
+            if(db->always_test)
+                protectDB((uintptr_t)db->x64_addr, db->x64_size);
+            else
+                protectDBJumpTable((uintptr_t)db->x64_addr, db->x64_size, db->block, db->jmpnext);
        }
        if(!need_lock)
            mutex_unlock(&my_context->mutex_dyndump);
@@ -10,14 +10,15 @@ typedef struct dynablock_s {
    void*           block;  // block-sizeof(void*) == self
    void*           actual_block;   // the actual start of the block (so block-sizeof(void*))
    struct dynablock_s*    previous;   // a previous block that might need to be freed
-    int             size;
    void*           x64_addr;
    uintptr_t       x64_size;
+    int             size;
    uint32_t        hash;
    uint8_t         done;
    uint8_t         gone;
-    uint8_t         always_test;
    uint8_t         dirty;      // if need to be tested as soon as it's created
+    uint8_t         always_test:1;
+    uint8_t         is32bits:1;
    int             isize;
    instsize_t*     instsize;
    void*           jmpnext;    // a branch jmpnext code when block is marked
@@ -19,6 +19,7 @@
 #include "dynablock_private.h"
 #include "bridge.h"
 #include "dynarec_next.h"
+#include "custommem.h"
 #endif
 #ifdef HAVE_TRACE
 #include "elfloader.h"
@@ -33,7 +34,18 @@ void* LinkNext(x64emu_t* emu, uintptr_t addr, void* x2, uintptr_t* x3)
    #ifdef HAVE_TRACE
    if(!addr) {
        dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
-        printf_log(LOG_NONE, "Warning, jumping to NULL address from %p (db=%p, x64addr=%p/%s)\n", x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL, db?getAddrFunctionName(getX64Address(db, (uintptr_t)x2-4)):"(nil)");
+        printf_log(LOG_INFO, "Warning, jumping to NULL address from %p (db=%p, x64addr=%p/%s)\n", x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL, db?getAddrFunctionName(getX64Address(db, (uintptr_t)x2-4)):"(nil)");
+    } else if(addr<0x10000) {
+        dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
+        printf_log(LOG_INFO, "Warning, jumping to low address %p from %p (db=%p, x64addr=%p/%s)\n", (void*)addr, x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL, db?getAddrFunctionName(getX64Address(db, (uintptr_t)x2-4)):"(nil)");
+    #ifdef BOX32
+    } else if(emu->segs[_CS]==0x23 && addr>0x100000000LL) {
+        dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
+        printf_log(LOG_INFO, "Warning, jumping to high address %p from %p (db=%p, x64addr=%p/%s)\n", (void*)addr, x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL, db?getAddrFunctionName(getX64Address(db, (uintptr_t)x2-4)):"(nil)");
+    } else if(!memExist(addr)) {
+        dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
+        printf_log(LOG_INFO, "Warning, jumping to an unmapped address %p from %p (db=%p, x64addr=%p/%s)\n", (void*)addr, x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL, db?getAddrFunctionName(getX64Address(db, (uintptr_t)x2-4)):"(nil)");
+    #endif
    }
    #endif
    void * jblock;
@@ -52,9 +64,13 @@ void* LinkNext(x64emu_t* emu, uintptr_t addr, void* x2, uintptr_t* x3)
    if(!block) {
        #ifdef HAVE_TRACE
        if(LOG_INFO<=box64_dynarec_log) {
-            dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
-            elfheader_t* h = FindElfAddress(my_context, (uintptr_t)x2-4);
-            dynarec_log(LOG_INFO, "Warning, jumping to a no-block address %p from %p (db=%p, x64addr=%p(elf=%s))\n", (void*)addr, x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL, h?ElfName(h):"(none)");
+            if(checkInHotPage(addr)) {
+                dynarec_log(LOG_INFO, "Not trying to run a block from a Hotpage at %p\n", (void*)addr);
+            } else {
+                dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
+                elfheader_t* h = FindElfAddress(my_context, (uintptr_t)x2-4);
+                dynarec_log(LOG_INFO, "Warning, jumping to a no-block address %p from %p (db=%p, x64addr=%p(elf=%s), RIP=%p)\n", (void*)addr, x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL, h?ElfName(h):"(none)", (void*)*x3);
+            }
        }
        #endif
        //tableupdate(native_epilog, addr, table);
@@ -62,6 +78,12 @@ void* LinkNext(x64emu_t* emu, uintptr_t addr, void* x2, uintptr_t* x3)
    }
    if(!block->done) {
        // not finished yet... leave linker
+        #ifdef HAVE_TRACE
+        if(box64_dynarec_log && !block->isize) {
+            dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
+            printf_log(LOG_NONE, "Warning, NULL block at %p from %p (db=%p, x64addr=%p/%s)\n", (void*)addr, x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL, db?getAddrFunctionName(getX64Address(db, (uintptr_t)x2-4)):"(nil)");
+        }
+        #endif
        return native_epilog;
    }
    if(!(jblock=block->block)) {
@@ -81,19 +103,22 @@ void DynaCall(x64emu_t* emu, uintptr_t addr)
    uint64_t old_rsi = R_RSI;
    uint64_t old_rbp = R_RBP;
    uint64_t old_rip = R_RIP;
+    x64flags_t old_eflags = emu->eflags;
    // save defered flags
    deferred_flags_t old_df = emu->df;
    multiuint_t old_op1 = emu->op1;
    multiuint_t old_op2 = emu->op2;
    multiuint_t old_res = emu->res;
-    multiuint_t old_op1_sav= emu->op1_sav;
-    multiuint_t old_res_sav= emu->res_sav;
-    deferred_flags_t old_df_sav= emu->df_sav;
    // uc_link
-    x64_ucontext_t* old_uc_link = emu->uc_link;
+    void* old_uc_link = emu->uc_link;
    emu->uc_link = NULL;

-    PushExit(emu);
+    #ifdef BOX32
+    if(box64_is32bits)
+        PushExit_32(emu);
+    else
+    #endif
+        PushExit(emu);
    R_RIP = addr;
    emu->df = d_none;
    DynaRun(emu);
@@ -109,10 +134,8 @@ void DynaCall(x64emu_t* emu, uintptr_t addr)
        emu->op1 = old_op1;
        emu->op2 = old_op2;
        emu->res = old_res;
-        emu->op1_sav = old_op1_sav;
-        emu->res_sav = old_res_sav;
-        emu->df_sav = old_df_sav;
        // and the old registers
+        emu->eflags = old_eflags;
        R_RBX = old_rbx;
        R_RDI = old_rdi;
        R_RSI = old_rsi;
@@ -123,22 +146,32 @@ void DynaCall(x64emu_t* emu, uintptr_t addr)
 }

 int my_setcontext(x64emu_t* emu, void* ucp);
+#ifdef BOX32
+int my32_setcontext(x64emu_t* emu, void* ucp);
+#endif
+extern int running32bits;
 void DynaRun(x64emu_t* emu)
 {
    // prepare setjump for signal handling
    JUMPBUFF jmpbuf[1] = {0};
    int skip = 0;
    JUMPBUFF *old_jmpbuf = emu->jmpbuf;
+    #ifdef RV64
+    uintptr_t old_savesp = emu->xSPSave;
+    #endif
    emu->flags.jmpbuf_ready = 0;
-
+    int is32bits = (emu->segs[_CS]==0x23);
    while(!(emu->quit)) {
        if(!emu->jmpbuf || (emu->flags.need_jmpbuf && emu->jmpbuf!=jmpbuf)) {
            emu->jmpbuf = jmpbuf;
+            #ifdef RV64
+            emu->old_savedsp = emu->xSPSave;
+            #endif
            emu->flags.jmpbuf_ready = 1;
            #ifdef ANDROID
-            if((skip=sigsetjmp(*(JUMPBUFF*)emu->jmpbuf, 1))) 
+            if((skip=sigsetjmp(*(JUMPBUFF*)emu->jmpbuf, 1)))
            #else
-            if((skip=sigsetjmp(emu->jmpbuf, 1))) 
+            if((skip=sigsetjmp(emu->jmpbuf, 1)))
            #endif
            {
                printf_log(LOG_DEBUG, "Setjmp DynaRun, fs=0x%x\n", emu->segs[_FS]);
@@ -160,7 +193,22 @@ void DynaRun(x64emu_t* emu)
            Run(emu, 0);
 #ifdef DYNAREC
        else {
-            int is32bits = (emu->segs[_CS]==0x23);
+            int newis32bits = (emu->segs[_CS]==0x23);
+            if(newis32bits!=is32bits) {
+                is32bits = newis32bits;
+                if(is32bits) {
+                    // Zero upper part of the 32bits regs
+                    R_RAX = R_EAX;
+                    R_RBX = R_EBX;
+                    R_RCX = R_ECX;
+                    R_RDX = R_EDX;
+                    R_RSP = R_ESP;
+                    R_RBP = R_EBP;
+                    R_RSI = R_ESI;
+                    R_RDI = R_EDI;
+                    running32bits = 1;
+                }
+            }
            dynablock_t* block = (skip)?NULL:DBGetBlock(emu, R_RIP, 1, is32bits);
            if(!block || !block->block || !block->done || ACCESS_FLAG(F_TF)) {
                skip = 0;
@@ -183,7 +231,12 @@ void DynaRun(x64emu_t* emu)
            }
            if(emu->quit && emu->uc_link) {
                emu->quit = 0;
-                my_setcontext(emu, emu->uc_link);
+                #ifdef BOX32
+                if(box64_is32bits)
+                    my32_setcontext(emu, emu->uc_link);
+                else
+                #endif
+                    my_setcontext(emu, emu->uc_link);
            }
        }
 #endif
@@ -192,4 +245,7 @@ void DynaRun(x64emu_t* emu)
    }
    // clear the setjmp
    emu->jmpbuf = old_jmpbuf;
+    #ifdef RV64
+    emu->xSPSave = old_savesp;
+    #endif
 }
@@ -9,38 +9,62 @@
 #define ADDITIONNAL_DEFINITION()  \
    int fpuCacheNeedsTransform(dynarec_native_t* dyn, int ninst);

-#define OTHER_CACHE()   \
-    if (fpuCacheNeedsTransform(dyn, ninst)) ret|=2;
+#define OTHER_CACHE()                                   \
+    if (fpuCacheNeedsTransform(dyn, ninst)) ret|=2;     \
+    if (nativeFlagsNeedsTransform(dyn, ninst)) ret|=4;

 #include "arm64/arm64_printer.h"
 #include "arm64/dynarec_arm64_private.h"
 #include "arm64/dynarec_arm64_functions.h"
-#elif defined(LA464)
+// Limit here is defined by LD litteral, that is 19bits
+#define MAXBLOCK_SIZE ((1<<19)-200)

-#define instruction_native_t        instruction_la464_t
-#define dynarec_native_t            dynarec_la464_t
+#define RAZ_SPECIFIC(A, N)      rasNativeState(A, N)
+#define UPDATE_SPECIFICS(A)     updateNativeFlags(A)
+#define PREUPDATE_SPECIFICS(A)

-#define ADDITIONNAL_DEFINITION()
+#elif defined(LA64)

-#define OTHER_CACHE()
+#define instruction_native_t        instruction_la64_t
+#define dynarec_native_t            dynarec_la64_t

-#include "la464/la464_printer.h"
-#include "la464/dynarec_la464_private.h"
-#include "la464/dynarec_la464_functions.h"
+#define ADDITIONNAL_DEFINITION() \
+    int fpuCacheNeedsTransform(dynarec_native_t* dyn, int ninst);
+
+#define OTHER_CACHE() \
+    if (fpuCacheNeedsTransform(dyn, ninst)) ret |= 2;
+
+#include "la64/la64_printer.h"
+#include "la64/dynarec_la64_private.h"
+#include "la64/dynarec_la64_functions.h"
+// Limit here is unconditionnal jump, that is signed 28bits
+#define MAXBLOCK_SIZE ((1 << 27) - 200)
+
+#define RAZ_SPECIFIC(A, N)
+#define UPDATE_SPECIFICS(A)
+#define PREUPDATE_SPECIFICS(A)
 #elif defined(RV64)

 #define instruction_native_t        instruction_rv64_t
 #define dynarec_native_t            dynarec_rv64_t

-#define ADDITIONNAL_DEFINITION()  \
-    int fpuCacheNeedsTransform(dynarec_native_t* dyn, int ninst);
+#define ADDITIONNAL_DEFINITION()                                  \
+    int fpuCacheNeedsTransform(dynarec_native_t* dyn, int ninst); \
+    int sewNeedsTransform(dynarec_rv64_t* dyn, int ninst);

-#define OTHER_CACHE()   \
-    if (fpuCacheNeedsTransform(dyn, ninst)) ret|=2;
+#define OTHER_CACHE()                                 \
+    if (fpuCacheNeedsTransform(dyn, ninst)) ret |= 2; \
+    if (sewNeedsTransform(dyn, ninst)) ret |= 4;

 #include "rv64/rv64_printer.h"
 #include "rv64/dynarec_rv64_private.h"
 #include "rv64/dynarec_rv64_functions.h"
+// Limit here is unconditionnal jump, that is signed 21bits
+#define MAXBLOCK_SIZE ((1<<20)-200)
+
+#define RAZ_SPECIFIC(A, N)
+#define UPDATE_SPECIFICS(A)
+#define PREUPDATE_SPECIFICS(A) updateNativeFlags(A)
 #else
 #error Unsupported platform
 #endif
@@ -1,14 +1,197 @@
 #ifndef __DYNAREC_HELPER__H_
 #define __DYNAREC_HELPER__H_

+/* Box64 Strong Memory Model Emulation
+ *
+ * Definition of a SEQ:
+ * A SEQ is a sequence of opcodes that writes to guest memory, terminated by JMP, RET, CALL, etc.
+ *
+ * Memory barriers are added in the following cases to emulate the strong memory model:
+ * 1. End of a SEQ:
+ *    - Scalar operations (a1)
+ *    - SIMD operations (a2)
+ * 2. Start of a SEQ:
+ *    - Scalar operations (b1)
+ *    - SIMD operations (b2)
+ * 3. Right before the last guest memory store in a SEQ:
+ *    - Scalar operations (c1)
+ *    - SIMD operations (c2)
+ * 4. After every third guest memory store in a SEQ (d)
+ *
+ * STRONGMEM levels (coarse-grained):
+ * 1: Includes a1, b1, c1
+ * 2: Includes LEVEL1, plus a2, b2, c2
+ * 3: Includes LEVEL2, plus d
+ *
+ * WEAKBARRIER levels (fine-grained):
+ * 1: Use dmb.ishld and dmb.ishst over dmb.ish for more performance
+ * 2. All 1. Plus disabled the last write barriers (c1, c2)
+ */
+
+#define STRONGMEM_SIMD_WRITE 2 // The level of SIMD memory writes will be tracked
+#define STRONGMEM_LAST_WRITE 1 // The level of a barrier before the last guest memory store will be put
+#define STRONGMEM_SEQ_WRITE  3 // The level of a barrier at every third memory store will be  put
+
+#if STEP == 1
+
+#define SMWRITE()                                                \
+    do {                                                         \
+        /* Mark that current sequence writes to guest memory. */ \
+        /* This will be used in SMEND for last_write. */         \
+        dyn->smwrite = 1;                                        \
+        /* Mark that current opcode writes to guest memory. */   \
+        dyn->insts[ninst].will_write = 1;                        \
+    } while (0)
+
+#define SMWRITELOCK(lock)              \
+    do {                               \
+        dyn->insts[ninst].lock = lock; \
+        SMWRITE();                     \
+    } while (0)
+
+#define SMWRITE2()                                             \
+    do {                                                       \
+        if (box64_dynarec_strongmem >= STRONGMEM_SIMD_WRITE) { \
+            dyn->smwrite = 1;                                  \
+            dyn->insts[ninst].will_write = 2;                  \
+        }                                                      \
+    } while (0)
+
+#define SMREAD()
+#define SMREADLOCK(lock)
+#define WILLWRITE()
+#define WILLWRITELOCK(lock)
+
+#define SMSTART()                                                  \
+    do {                                                           \
+        /* Clear current state at the start of a potential SEQ. */ \
+        dyn->smwrite = 0;                                          \
+    } while (0)
+
+#define SMEND()                                                                                \
+    do {                                                                                       \
+        /* If there is any guest memory write, which is a SEQ, then compute the last_write. */ \
+        if (dyn->smwrite && (box64_dynarec_strongmem >= STRONGMEM_LAST_WRITE)) {               \
+            int i = ninst;                                                                     \
+            while (i >= 0 && !dyn->insts[i].will_write)                                        \
+                --i;                                                                           \
+            if (i >= 0) { dyn->insts[i].last_write = 1; }                                      \
+        }                                                                                      \
+        dyn->smwrite = 0;                                                                      \
+    } while (0)
+
+#define SMDMB()
+
+#else
+
+// An opcode writes guest memory, this need to be put after the STORE instruction manually.
+#define SMWRITE()                                                     \
+    do {                                                              \
+        /* Put a barrier at every third memory write. */              \
+        if (box64_dynarec_strongmem >= STRONGMEM_SEQ_WRITE) {         \
+            if (++dyn->smwrite >= 3 /* Every third memory write */) { \
+                DMB_ISH();                                            \
+                dyn->smwrite = 1;                                     \
+            }                                                         \
+        } else {                                                      \
+            /* Mark that current sequence writes to guest memory. */  \
+            dyn->smwrite = 1;                                         \
+        }                                                             \
+    } while (0)
+
+// Similar to SMWRITE, but checks lock.
+#define SMWRITELOCK(lock) \
+    do {                  \
+        if (lock) {       \
+            DMB_ISH();    \
+        } else {          \
+            SMWRITE();    \
+        }                 \
+    } while (0)
+
+// Similar to SMWRITE, but for SIMD instructions.
+#define SMWRITE2()                                           \
+    do {                                                     \
+        if (box64_dynarec_strongmem >= STRONGMEM_SIMD_WRITE) \
+            SMWRITE();                                       \
+    } while (0)
+
+// An opcode reads guest memory, this need to be put before the LOAD instruction manually.
+#define SMREAD()
+
+// Similar to SMREAD, but checks lock.
+#define SMREADLOCK(lock) \
+    do {                 \
+        if (lock) {      \
+            DMB_ISH();   \
+        } else {         \
+            SMREAD();    \
+        }                \
+    } while (0)
+
+// An opcode will write memory, this will be put before the STORE instruction automatically.
+#define WILLWRITE()                                                                                  \
+    do {                                                                                             \
+        if (box64_dynarec_strongmem >= dyn->insts[ninst].will_write && dyn->smwrite == 0) {          \
+            /* Will write but never written, this is the start of a SEQ, put a barrier. */           \
+            if (box64_dynarec_weakbarrier)                                                           \
+                DMB_ISHLD();                                                                         \
+            else                                                                                     \
+                DMB_ISH();                                                                           \
+        } else if (box64_dynarec_strongmem >= STRONGMEM_LAST_WRITE && box64_dynarec_weakbarrier != 2 \
+            && dyn->insts[ninst].last_write) {                                                       \
+            /* Last write, put a barrier */                                                          \
+            if (box64_dynarec_weakbarrier)                                                           \
+                DMB_ISHST();                                                                         \
+            else                                                                                     \
+                DMB_ISH();                                                                           \
+        }                                                                                            \
+    } while (0)
+
+// Similar to WILLWRITE, but checks lock.
+#define WILLWRITELOCK(lock) \
+    do {                    \
+        if (lock) {         \
+            DMB_ISH();      \
+        } else {            \
+            WILLWRITE();    \
+        }                   \
+    } while (0)
+
+// Used to clear the state at the start of a SEQ
+#define SMSTART()         \
+    do {                  \
+        dyn->smwrite = 0; \
+    } while (0)
+
+// Will be put at the end of the SEQ
+#define SMEND()                                                         \
+    do {                                                                \
+        if (box64_dynarec_strongmem) {                                  \
+            /* It's a SEQ, put a barrier here. */                       \
+            if (dyn->smwrite) {                                         \
+                /* Check if the next instruction has a end loop mark */ \
+                if (box64_dynarec_weakbarrier)                          \
+                    DMB_ISHST();                                        \
+                else                                                    \
+                    DMB_ISH();                                          \
+            }                                                           \
+        }                                                               \
+        dyn->smwrite = 0;                                               \
+    } while (0)
+
+// The barrier.
+#define SMDMB() DMB_ISH()
+#endif
+
 #ifdef ARM64
 #include "arm64/dynarec_arm64_helper.h"
-#elif defined(LA464)
-#include "la464/dynarec_la464_helper.h"
+#elif defined(LA64)
+#include "la64/dynarec_la64_helper.h"
 #elif defined(RV64)
 #include "rv64/dynarec_rv64_helper.h"
 #else
 #error Unsupported architecture
 #endif

-#endif //__DYNAREC_HELPER__H_
+#endif //__DYNAREC_HELPER__H_
@@ -72,8 +72,7 @@ void add_next(dynarec_native_t *dyn, uintptr_t addr) {
        }
    // add slots
    if(dyn->next_sz == dyn->next_cap) {
-        dyn->next_cap += 64;
-        dyn->next = (uintptr_t*)dynaRealloc(dyn->next, dyn->next_cap*sizeof(uintptr_t));
+        printf_log(LOG_NONE, "Warning, overallocating next\n");
    }
    dyn->next[dyn->next_sz++] = addr;
 }
@@ -97,15 +96,19 @@ uintptr_t get_closest_next(dynarec_native_t *dyn, uintptr_t addr) {
 void add_jump(dynarec_native_t *dyn, int ninst) {
    // add slots
    if(dyn->jmp_sz == dyn->jmp_cap) {
-        dyn->jmp_cap += 64;
-        dyn->jmps = (int*)dynaRealloc(dyn->jmps, dyn->jmp_cap*sizeof(int));
+        printf_log(LOG_NONE, "Warning, overallocating jmps\n");
    }
    dyn->jmps[dyn->jmp_sz++] = ninst;
 }
 int get_first_jump(dynarec_native_t *dyn, int next) {
+    if(next<0 || next>dyn->size)
+        return -2;
+    return get_first_jump_addr(dyn, dyn->insts[next].x64.addr);
+}
+int get_first_jump_addr(dynarec_native_t *dyn, uintptr_t next) {
    for(int i=0; i<dyn->jmp_sz; ++i)
        if(dyn->insts[dyn->jmps[i]].x64.jmp == next)
-            return i;
+            return dyn->jmps[i];
    return -2;
 }

@@ -118,6 +121,8 @@ int is_nops(dynarec_native_t *dyn, uintptr_t addr, int n)
        return is_nops(dyn, addr+1, n-1);
    if(n>1 && PK(0)==0x66)  // if opcode start with 0x66, and there is more after, than is *can* be a NOP
        return is_nops(dyn, addr+1, n-1);
+    if(n>1 && PK(0)==0xF3 && PK(1)==0x90)
+        return is_nops(dyn, addr+2, n-2);
    if(n>2 && PK(0)==0x0f && PK(1)==0x1f && PK(2)==0x00)
        return is_nops(dyn, addr+3, n-3);
    if(n>2 && PK(0)==0x8d && PK(1)==0x76 && PK(2)==0x00)    // lea esi, [esi]
@@ -226,6 +231,14 @@ int next_instruction(dynarec_native_t *dyn, uintptr_t addr)
        case 0xBE:
        case 0xBF:
            return 5;
+        case 0xF3:
+            nextop = PK(1);
+            switch(nextop) {
+                case 0x90: 
+                    return 2;
+                default: break;
+            }
+            break;
        case 0xFF:
            nextop = PK(1);
            switch((nextop>>3)&7) {
@@ -289,15 +302,10 @@ int Table64(dynarec_native_t *dyn, uint64_t val, int pass)
            idx = i;
    // not found, add it
    if(idx==-1) {
-        if(dyn->table64size == dyn->table64cap) {
-            dyn->table64cap+=16;
-            if(pass<3)  // do not resize on pass3, it's not the same type of memory anymore
-                dyn->table64 = (uint64_t*)dynaRealloc(dyn->table64, dyn->table64cap * sizeof(uint64_t));
-        }
        idx = dyn->table64size++;
        if(idx < dyn->table64cap)
            dyn->table64[idx] = val;
-        else
+        else if(pass==3)
            printf_log(LOG_NONE, "Warning, table64 bigger than expected %d vs %d\n", idx, dyn->table64cap);
    }
    // calculate offset
@@ -305,23 +313,35 @@ int Table64(dynarec_native_t *dyn, uint64_t val, int pass)
    return delta;
 }

-static void fillPredecessors(dynarec_native_t* dyn)
+static void recurse_mark_alive(dynarec_native_t* dyn, int i)
+{
+    if(dyn->insts[i].x64.alive)
+        return;
+    dyn->insts[i].x64.alive = 1;
+    if(dyn->insts[i].x64.jmp && dyn->insts[i].x64.jmp_insts!=-1)
+        recurse_mark_alive(dyn, dyn->insts[i].x64.jmp_insts);
+    if(i<dyn->size-1 && dyn->insts[i].x64.has_next)
+        recurse_mark_alive(dyn, i+1);
+}
+
+static int sizePredecessors(dynarec_native_t* dyn)
 {
    int pred_sz = 1;    // to be safe
    // compute total size of predecessor to allocate the array
+    // mark alive...
+    recurse_mark_alive(dyn, 0);
    // first compute the jumps
+    int jmpto;
    for(int i=0; i<dyn->size; ++i) {
-        if(dyn->insts[i].x64.jmp && (dyn->insts[i].x64.jmp_insts!=-1)) {
+        if(dyn->insts[i].x64.alive && dyn->insts[i].x64.jmp && ((jmpto=dyn->insts[i].x64.jmp_insts)!=-1)) {
            pred_sz++;
-            dyn->insts[dyn->insts[i].x64.jmp_insts].pred_sz++;
+            dyn->insts[jmpto].pred_sz++;
        }
    }
    // remove "has_next" from orphan branch
    for(int i=0; i<dyn->size-1; ++i) {
-        if(!dyn->insts[i].x64.has_next) {
-            if(dyn->insts[i+1].x64.has_next && !dyn->insts[i+1].pred_sz)
-                dyn->insts[i+1].x64.has_next = 0;
-        }
+        if(dyn->insts[i].x64.has_next && !dyn->insts[i+1].x64.alive)
+            dyn->insts[i].x64.has_next = 0;
    }
    // second the "has_next"
    for(int i=0; i<dyn->size-1; ++i) {
@@ -330,8 +350,10 @@ static void fillPredecessors(dynarec_native_t* dyn)
            dyn->insts[i+1].pred_sz++;
        }
    }
-    int alloc_size = pred_sz;
-    dyn->predecessor = (int*)dynaMalloc(pred_sz*sizeof(int));
+    return pred_sz;
+}
+static void fillPredecessors(dynarec_native_t* dyn)
+{
    // fill pred pointer
    int* p = dyn->predecessor;
    for(int i=0; i<dyn->size; ++i) {
@@ -340,7 +362,7 @@ static void fillPredecessors(dynarec_native_t* dyn)
        dyn->insts[i].pred_sz=0;  // reset size, it's reused to actually fill pred[]
    }
    // fill pred
-    for(int i=0; i<dyn->size; ++i) {
+    for(int i=0; i<dyn->size; ++i) if(dyn->insts[i].x64.alive) {
        if((i!=dyn->size-1) && dyn->insts[i].x64.has_next)
            dyn->insts[i+1].pred[dyn->insts[i+1].pred_sz++] = i;
        if(dyn->insts[i].x64.jmp && (dyn->insts[i].x64.jmp_insts!=-1)) {
@@ -350,19 +372,15 @@ static void fillPredecessors(dynarec_native_t* dyn)
    }
 }

-// updateNeed goes backward, from last instruction to top
+// updateNeed for the current block. recursive function that goes backward
 static int updateNeed(dynarec_native_t* dyn, int ninst, uint8_t need) {
    while (ninst>=0) {
        // need pending but instruction is only a subset: remove pend and use an X_ALL instead
        need |= dyn->insts[ninst].x64.need_after;
-        if((need&X_PEND) && (dyn->insts[ninst].x64.state_flags==SF_SUBSET)) {
+        if((need&X_PEND) && (dyn->insts[ninst].x64.state_flags==SF_SUBSET || dyn->insts[ninst].x64.state_flags==SF_SET || dyn->insts[ninst].x64.state_flags==SF_SET_NODF)) {
            need &=~X_PEND;
            need |= X_ALL;
        }
-        if((need&X_PEND) && (dyn->insts[ninst].x64.state_flags==SF_SET)) {
-            need &=~X_PEND;
-            need |= dyn->insts[ninst].x64.set_flags;    // SF_SET will compute all flags, it's not SUBSET!
-        }
        if((need&X_PEND) && dyn->insts[ninst].x64.state_flags==SF_SUBSET_PENDING) {
            need |= X_ALL&~(dyn->insts[ninst].x64.set_flags);
        }
@@ -397,26 +415,106 @@ static int updateNeed(dynarec_native_t* dyn, int ninst, uint8_t need) {
    return ninst;
 }

+static void updateYmm0s(dynarec_native_t* dyn, int ninst, int max_ninst_reached) {
+    int can_incr = ninst == max_ninst_reached; // Are we the top-level call?
+    int ok = 1;
+    while ((can_incr || ok) && ninst<dyn->size) {
+        //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "update ninst=%d (%d): can_incr=%d\n", ninst, max_ninst_reached, can_incr);
+        uint16_t new_purge_ymm, new_ymm0_in, new_ymm0_out;
+
+        if (dyn->insts[ninst].pred_sz && dyn->insts[ninst].x64.alive) {
+            // The union of the empty set is empty (0), the intersection is the universe (-1)
+            // The first instruction is the entry point, which has a virtual pred with ymm0_out = 0
+            // Similarly, float barriers reset ymm0s
+            uint16_t ymm0_union = 0;
+            uint16_t ymm0_inter = (ninst && !(dyn->insts[ninst].x64.barrier & BARRIER_FLOAT)) ? ((uint16_t)-1) : (uint16_t)0;
+            for (int i = 0; i < dyn->insts[ninst].pred_sz; ++i) {
+                int pred = dyn->insts[ninst].pred[i];
+                //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "\twith pred[%d] = %d", i, pred);
+                if (pred >= max_ninst_reached) {
+                    //if(box64_dynarec_dump) dynarec_log(LOG_NONE, " (skipped)\n");
+                    continue;
+                }
+
+                int pred_out = dyn->insts[pred].x64.has_callret ? 0 : dyn->insts[pred].ymm0_out;
+                //if(box64_dynarec_dump) dynarec_log(LOG_NONE, " ~> %04X\n", pred_out);
+                ymm0_union |= pred_out;
+                ymm0_inter &= pred_out;
+            }
+            //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "\t=> %04X,%04X\n", ymm0_union, ymm0_inter);
+            // Notice the default values yield something coherent here (if all pred are after ninst)
+            new_purge_ymm = ymm0_union & ~ymm0_inter;
+            new_ymm0_in = ymm0_inter;
+            new_ymm0_out = (ymm0_inter | dyn->insts[ninst].ymm0_add) & ~dyn->insts[ninst].ymm0_sub;
+
+            if ((dyn->insts[ninst].purge_ymm != new_purge_ymm) || (dyn->insts[ninst].ymm0_in != new_ymm0_in) || (dyn->insts[ninst].ymm0_out != new_ymm0_out)) {
+                // Need to update self and next(s)
+                dyn->insts[ninst].purge_ymm = new_purge_ymm;
+                dyn->insts[ninst].ymm0_in = new_ymm0_in;
+                dyn->insts[ninst].ymm0_out = new_ymm0_out;
+
+                if (can_incr) {
+                    // We always have ninst == max_ninst_reached when can_incr == 1
+                    ++max_ninst_reached;
+                } else {
+                    // We need to stop here if the opcode has no "real" next or if we reached the ninst of the toplevel
+                    ok = (max_ninst_reached - 1 != ninst) && dyn->insts[ninst].x64.has_next && !dyn->insts[ninst].x64.has_callret;
+                }
+
+                int jmp = (dyn->insts[ninst].x64.jmp)?dyn->insts[ninst].x64.jmp_insts:-1;
+                if((jmp!=-1) && (jmp < max_ninst_reached)) {
+                    //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "\t! jump to %d\n", jmp);
+                    // The jump goes before the last instruction reached, update the destination
+                    // If this is the top level call, this means the jump goes backward (jmp != ninst)
+                    // Otherwise, since we don't update all instructions, we may miss the update (don't use jmp < ninst)
+                    updateYmm0s(dyn, jmp, max_ninst_reached);
+                }
+            } else {
+                if (can_incr) {
+                    // We always have ninst == max_ninst_reached when can_incr == 1
+                    ++max_ninst_reached;
+
+                    // Also update jumps to before (they are skipped otherwise)
+                    int jmp = (dyn->insts[ninst].x64.jmp)?dyn->insts[ninst].x64.jmp_insts:-1;
+                    if((jmp!=-1) && (jmp < max_ninst_reached)) {
+                        //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "\t! jump to %d\n", jmp);
+                        updateYmm0s(dyn, jmp, max_ninst_reached);
+                    }
+                } else {
+                    // We didn't update anything, we can leave
+                    ok = 0;
+                }
+            }
+        } else if (can_incr) {
+            // We always have ninst == max_ninst_reached when can_incr == 1
+            ++max_ninst_reached;
+        } else {
+            // We didn't update anything, we can leave
+            ok = 0;
+        }
+        ++ninst;
+    }
+}
+
 void* current_helper = NULL;
+static int static_jmps[MAX_INSTS+2];
+static uintptr_t static_next[MAX_INSTS+2];
+static uint64_t static_table64[(MAX_INSTS+3)/4];
+static instruction_native_t static_insts[MAX_INSTS+2] = {0};
+// TODO: ninst could be a uint16_t instead of an int, that could same some temp. memory

 void CancelBlock64(int need_lock)
 {
    if(need_lock)
        mutex_lock(&my_context->mutex_dyndump);
    dynarec_native_t* helper = (dynarec_native_t*)current_helper;
-    current_helper = NULL;
    if(helper) {
-        dynaFree(helper->next);
-        dynaFree(helper->jmps);
-        dynaFree(helper->insts);
-        dynaFree(helper->predecessor);
-        if(helper->table64 && (helper->table64!=(uint64_t*)helper->tablestart))
-            dynaFree(helper->table64);
        if(helper->dynablock && helper->dynablock->actual_block) {
            FreeDynarecMap((uintptr_t)helper->dynablock->actual_block);
            helper->dynablock->actual_block = NULL;
        }
    }
+    current_helper = NULL;
    if(need_lock)
        mutex_unlock(&my_context->mutex_dyndump);
 }
@@ -426,7 +524,7 @@ uintptr_t native_pass1(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
 uintptr_t native_pass2(dynarec_native_t* dyn, uintptr_t addr, int alternate, int is32bits);
 uintptr_t native_pass3(dynarec_native_t* dyn, uintptr_t addr, int alternate, int is32bits);

-void* CreateEmptyBlock(dynablock_t* block, uintptr_t addr) {
+void* CreateEmptyBlock(dynablock_t* block, uintptr_t addr, int is32bits) {
    block->isize = 0;
    block->done = 0;
    size_t sz = 4*sizeof(void*);
@@ -441,6 +539,7 @@ void* CreateEmptyBlock(dynablock_t* block, uintptr_t addr) {
    block->actual_block = actual_p;
    block->block = p;
    block->jmpnext = p;
+    block->is32bits = is32bits;
    *(dynablock_t**)actual_p = block;
    *(void**)(p+2*sizeof(void*)) = native_epilog;
    CreateJmpNext(block->jmpnext, p+2*sizeof(void*));
@@ -458,18 +557,14 @@ void* FillBlock64(dynablock_t* block, uintptr_t addr, int alternate, int is32bit
        A ..    A+8*n   : Table64: n 64bits values
        B ..    B+7     : dynablock_t* : self (as part of JmpNext, that simulate another block)
        B+8 ..  B+15    : 2 Native code for jmpnext (or jmp epilog in case of empty block)
-        B+16 .. B+23    : jmpnext (or jmp_epilog) address
+        B+16 .. B+23    : jmpnext (or jmp_epilog) address. jumpnext is used when the block needs testing
        B+24 .. B+31    : empty (in case an architecture needs more than 2 opcodes)
        B+32 .. B+32+sz : instsize (compressed array with each instruction length on x64 and native side)

    */
-    if(IsInHotPage(addr)) {
-        dynarec_log(LOG_DEBUG, "Canceling dynarec FillBlock on hotpage for %p\n", (void*)addr);
-        return NULL;
-    }
    if(addr>=box64_nodynarec_start && addr<box64_nodynarec_end) {
        dynarec_log(LOG_INFO, "Create empty block in no-dynarec zone\n");
-        return CreateEmptyBlock(block, addr);
+        return CreateEmptyBlock(block, addr, is32bits);
    }
    if(current_helper) {
        dynarec_log(LOG_DEBUG, "Canceling dynarec FillBlock at %p as another one is going on\n", (void*)addr);
@@ -483,24 +578,34 @@ void* FillBlock64(dynablock_t* block, uintptr_t addr, int alternate, int is32bit
    helper.dynablock = block;
    helper.start = addr;
    uintptr_t start = addr;
-    helper.cap = 128;
-    helper.insts = (instruction_native_t*)dynaCalloc(helper.cap, sizeof(instruction_native_t));
+    helper.cap = MAX_INSTS;
+    helper.insts = static_insts;
+    helper.jmps = static_jmps;
+    helper.jmp_cap = MAX_INSTS;
+    helper.next = static_next;
+    helper.next_cap = MAX_INSTS;
+    helper.table64 = static_table64;
+    helper.table64cap = sizeof(static_table64)/sizeof(uint64_t);
    // pass 0, addresses, x64 jump addresses, overall size of the block
    uintptr_t end = native_pass0(&helper, addr, alternate, is32bits);
+    if(helper.abort) {
+        if(box64_dynarec_dump || box64_dynarec_log)dynarec_log(LOG_NONE, "Abort dynablock on pass0\n");
+        CancelBlock64(0);
+        return NULL;
+    }
    // basic checks
    if(!helper.size) {
        dynarec_log(LOG_INFO, "Warning, null-sized dynarec block (%p)\n", (void*)addr);
        CancelBlock64(0);
-        return CreateEmptyBlock(block, addr);
+        return CreateEmptyBlock(block, addr, is32bits);
    }
    if(!isprotectedDB(addr, 1)) {
        dynarec_log(LOG_INFO, "Warning, write on current page on pass0, aborting dynablock creation (%p)\n", (void*)addr);
-        AddHotPage(addr);
        CancelBlock64(0);
        return NULL;
    }
    // protect the block of it goes over the 1st page
-    if((addr&~box64_pagesize)!=(end&~box64_pagesize)) // need to protect some other pages too
+    if((addr&~(box64_pagesize-1))!=(end&~(box64_pagesize-1))) // need to protect some other pages too
        protectDB(addr, end-addr);  //end is 1byte after actual end
    // compute hash signature
    uint32_t hash = X31_hash_code((void*)addr, end-addr);
@@ -508,10 +613,10 @@ void* FillBlock64(dynablock_t* block, uintptr_t addr, int alternate, int is32bit
    for(int ii=0; ii<helper.jmp_sz; ++ii) {
        int i = helper.jmps[ii];
        uintptr_t j = helper.insts[i].x64.jmp;
+        helper.insts[i].x64.jmp_insts = -1;
        if(j<start || j>=end || j==helper.insts[i].x64.addr) {
            if(j==helper.insts[i].x64.addr) // if there is a loop on some opcode, make the block "always to tested"
                helper.always_test = 1;
-            helper.insts[i].x64.jmp_insts = -1;
            helper.insts[i].x64.need_after |= X_PEND;
        } else {
            // find jump address instruction
@@ -544,30 +649,73 @@ void* FillBlock64(dynablock_t* block, uintptr_t addr, int alternate, int is32bit
                if(helper.insts[i2].x64.addr==j)
                    k=i2;
            }*/
-            if(k!=-1 && !helper.insts[i].barrier_maybe)
-                helper.insts[k].x64.barrier |= BARRIER_FULL;
-            helper.insts[i].x64.jmp_insts = k;
+            if(k!=-1) {
+                if(!helper.insts[i].barrier_maybe)
+                    helper.insts[k].x64.barrier |= BARRIER_FULL;
+                // special case, loop on itself with some nop in between
+                if(k<i && !helper.insts[i].x64.has_next && is_nops(&helper, helper.insts[k].x64.addr, helper.insts[i].x64.addr-helper.insts[k].x64.addr)) {
+                    helper.always_test = 1;
+                    k = -1;
+                }
+                helper.insts[i].x64.jmp_insts = k;
+            }
        }
    }
-    // no need for next and jmps anymore
-    dynaFree(helper.next);
+    // no need for next anymore
    helper.next_sz = helper.next_cap = 0;
    helper.next = NULL;
-    dynaFree(helper.jmps);
-    helper.jmp_sz = helper.jmp_cap = 0;
-    helper.jmps = NULL;
    // fill predecessors with the jump address
+    int alloc_size = sizePredecessors(&helper);
+    helper.predecessor = (int*)alloca(alloc_size*sizeof(int));
    fillPredecessors(&helper);

+    PREUPDATE_SPECIFICS(&helper);
+
    int pos = helper.size;
    while (pos>=0)
        pos = updateNeed(&helper, pos, 0);
+    // remove fpu stuff on non-executed code
+    for(int i=1; i<helper.size-1; ++i)
+        if(!helper.insts[i].pred_sz) {
+            int ii = i;
+            while(ii<helper.size && !helper.insts[ii].pred_sz) {
+                fpu_reset_ninst(&helper, ii);
+                helper.insts[ii].ymm0_in = helper.insts[ii].ymm0_sub = helper.insts[ii].ymm0_add = helper.insts[ii].ymm0_out = helper.insts[ii].purge_ymm = 0;
+                RAZ_SPECIFIC(&helper, ii);
+                ++ii;
+            }
+            i = ii;
+        }
+    // remove trailling dead code
+    while(helper.size && !helper.insts[helper.size-1].x64.alive) {
+        helper.isize-=helper.insts[helper.size-1].x64.size;
+        --helper.size;
+    }
+    if(!helper.size) {
+        // NULL block after removing dead code, how is that possible?
+        dynarec_log(LOG_INFO, "Warning, null-sized dynarec block after trimming dead code (%p)\n", (void*)addr);
+        CancelBlock64(0);
+        return CreateEmptyBlock(block, addr, is32bits);
+    }
+    updateYmm0s(&helper, 0, 0);
+    UPDATE_SPECIFICS(&helper);
+

    // pass 1, float optimizations, first pass for flags
    native_pass1(&helper, addr, alternate, is32bits);
+    if(helper.abort) {
+        if(box64_dynarec_dump || box64_dynarec_log)dynarec_log(LOG_NONE, "Abort dynablock on pass1\n");
+        CancelBlock64(0);
+        return NULL;
+    }
    
    // pass 2, instruction size
    native_pass2(&helper, addr, alternate, is32bits);
+    if(helper.abort) {
+        if(box64_dynarec_dump || box64_dynarec_log)dynarec_log(LOG_NONE, "Abort dynablock on pass2\n");
+        CancelBlock64(0);
+        return NULL;
+    }
    // keep size of instructions for signal handling
    size_t insts_rsize = (helper.insts_size+2)*sizeof(instsize_t);
    insts_rsize = (insts_rsize+7)&~7;   // round the size...
@@ -593,7 +741,6 @@ void* FillBlock64(dynablock_t* block, uintptr_t addr, int alternate, int is32bit
    helper.instsize = (instsize_t*)instsize;
    *(dynablock_t**)actual_p = block;
    helper.table64cap = helper.table64size;
-    dynaFree(helper.table64);
    helper.table64 = (uint64_t*)helper.tablestart;
    // pass 3, emit (log emit native opcode)
    if(box64_dynarec_dump) {
@@ -604,18 +751,23 @@ void* FillBlock64(dynablock_t* block, uintptr_t addr, int alternate, int is32bit
    int oldtable64size = helper.table64size;
    size_t oldnativesize = helper.native_size;
    size_t oldinstsize = helper.insts_size;
+    int oldsize= helper.size;
    helper.native_size = 0;
    helper.table64size = 0; // reset table64 (but not the cap)
    helper.insts_size = 0;  // reset
    native_pass3(&helper, addr, alternate, is32bits);
+    if(helper.abort) {
+        if(box64_dynarec_dump || box64_dynarec_log)dynarec_log(LOG_NONE, "Abort dynablock on pass3\n");
+        CancelBlock64(0);
+        return NULL;
+    }
+    // no need for jmps anymore
+    helper.jmp_sz = helper.jmp_cap = 0;
+    helper.jmps = NULL;
    // keep size of instructions for signal handling
    block->instsize = instsize;
-    // ok, free the helper now
-    dynaFree(helper.insts);
-    helper.insts = NULL;
    helper.table64 = NULL;
    helper.instsize = NULL;
-    dynaFree(helper.predecessor);
    helper.predecessor = NULL;
    block->size = sz;
    block->isize = helper.size;
@@ -623,6 +775,7 @@ void* FillBlock64(dynablock_t* block, uintptr_t addr, int alternate, int is32bit
    block->jmpnext = next+sizeof(void*);
    block->always_test = helper.always_test;
    block->dirty = block->always_test;
+    block->is32bits = is32bits;
    *(dynablock_t**)next = block;
    *(void**)(next+3*sizeof(void*)) = native_next;
    CreateJmpNext(block->jmpnext, next+3*sizeof(void*));
@@ -632,36 +785,47 @@ void* FillBlock64(dynablock_t* block, uintptr_t addr, int alternate, int is32bit
    __clear_cache(actual_p, actual_p+sz);   // need to clear the cache before execution...
    block->hash = X31_hash_code(block->x64_addr, block->x64_size);
    // Check if something changed, to abort if it is
-    if((block->hash != hash)) {
+    if((helper.abort || (block->hash != hash))) {
        dynarec_log(LOG_DEBUG, "Warning, a block changed while being processed hash(%p:%ld)=%x/%x\n", block->x64_addr, block->x64_size, block->hash, hash);
-        AddHotPage(addr);
        CancelBlock64(0);
        return NULL;
    }
    if((oldnativesize!=helper.native_size) || (oldtable64size<helper.table64size)) {
-        printf_log(LOG_NONE, "BOX64: Warning, size difference in block between pass2 (%zu) & pass3 (%zu)!\n", sz, helper.native_size+helper.table64size*8);
+        printf_log(LOG_NONE, "BOX64: Warning, size difference in block between pass2 (%zu, %d) & pass3 (%zu, %d)!\n", oldnativesize+oldtable64size*8, oldsize, helper.native_size+helper.table64size*8, helper.size);
        uint8_t *dump = (uint8_t*)helper.start;
        printf_log(LOG_NONE, "Dump of %d x64 opcodes:\n", helper.size);
        for(int i=0; i<helper.size; ++i) {
-            printf_log(LOG_NONE, "%p:", dump);
+            printf_log(LOG_NONE, "%s%p:", (helper.insts[i].size2!=helper.insts[i].size)?"=====> ":"", dump);
            for(; dump<(uint8_t*)helper.insts[i+1].x64.addr; ++dump)
                printf_log(LOG_NONE, " %02X", *dump);
-            printf_log(LOG_NONE, "\t%d -> %d\n", helper.insts[i].size2, helper.insts[i].size);
+            printf_log(LOG_NONE, "\t%d -> %d", helper.insts[i].size2, helper.insts[i].size);
+            if(helper.insts[i].ymm0_pass2 || helper.insts[i].ymm0_pass3)
+                printf_log(LOG_NONE, "\t %04x -> %04x", helper.insts[i].ymm0_pass2, helper.insts[i].ymm0_pass3);
+            printf_log(LOG_NONE, "\n");
        }
        printf_log(LOG_NONE, "Table64 \t%d -> %d\n", oldtable64size*8, helper.table64size*8);
        printf_log(LOG_NONE, " ------------\n");
        CancelBlock64(0);
        return NULL;
    }
+    // ok, free the helper now
+    //dynaFree(helper.insts);
+    helper.insts = NULL;
    if(insts_rsize/sizeof(instsize_t)<helper.insts_size) {
        printf_log(LOG_NONE, "BOX64: Warning, insts_size difference in block between pass2 (%zu) and pass3 (%zu), allocated: %zu\n", oldinstsize, helper.insts_size, insts_rsize/sizeof(instsize_t));
    }
    if(!isprotectedDB(addr, end-addr)) {
        dynarec_log(LOG_DEBUG, "Warning, block unprotected while being processed %p:%ld, marking as need_test\n", block->x64_addr, block->x64_size);
-        AddHotPage(addr);
        block->dirty = 1;
        //protectDB(addr, end-addr);
    }
+    if(getProtection(addr)&PROT_NEVERCLEAN) {
+        block->dirty = 1;
+        block->always_test = 1;
+    }
+    if(block->always_test) {
+        dynarec_log(LOG_DEBUG, "Note: block marked as always dirty %p:%ld\n", block->x64_addr, block->x64_size);
+    }
    current_helper = NULL;
    //block->done = 1;
    return (void*)block;
@@ -59,10 +59,20 @@ void native_fpatan(x64emu_t* emu)
 }
 void native_fxtract(x64emu_t* emu)
 {
-    int32_t tmp32s = (ST1.q&0x7ff0000000000000LL)>>52;
-    tmp32s -= 1023;
-    ST1.d /= exp2(tmp32s);
-    ST0.d = tmp32s;
+    int tmp32s;
+    if(isnan(ST1.d)) {
+        ST0.d = ST1.d;
+    } else if(isinf(ST1.d)) {
+        ST0.d = ST1.d;
+        ST1.d = INFINITY;
+    } else if(ST1.d==0.0) {
+        ST0.d = ST1.d;
+        ST1.d = -INFINITY;
+    } else {
+        // LD80bits doesn't have implicit "1" bit, so need to adjust for that
+        ST0.d = frexp(ST1.d, &tmp32s)*2;
+        ST1.d = tmp32s-1;
+    }
 }
 void native_fprem(x64emu_t* emu)
 {
@@ -172,7 +182,7 @@ void native_ud(x64emu_t* emu)
 void native_priv(x64emu_t* emu)
 {
    emu->test.test = 0;
-    emit_signal(emu, SIGSEGV, (void*)R_RIP, 0);
+    emit_signal(emu, SIGSEGV, (void*)R_RIP, 0xbad0);
 }

 void native_int(x64emu_t* emu, int num)
@@ -188,13 +198,13 @@ void native_singlestep(x64emu_t* emu)

 void native_int3(x64emu_t* emu)
 {
-    emit_signal(emu, SIGTRAP, (void*)R_RIP, 128);
+    emit_signal(emu, SIGTRAP, NULL, 3);
 }

 void native_div0(x64emu_t* emu)
 {
    emu->test.test = 0;
-    emit_div0(emu,  (void*)R_RIP, 0);
+    emit_div0(emu,  (void*)R_RIP, 1);
 }

 void native_fsave(x64emu_t* emu, uint8_t* ed)
@@ -204,7 +214,18 @@ void native_fsave(x64emu_t* emu, uint8_t* ed)
    uint8_t* p = ed;
    p += 28;
    for (int i=0; i<8; ++i) {
-        LD2D(p, &ST(i).d);
+        LD2D(p, &emu->x87[7-i].d);
+        p+=10;
+    }
+}
+void native_fsave16(x64emu_t* emu, uint8_t* ed)
+{
+    fpu_savenv(emu, (char*)ed, 1);
+
+    uint8_t* p = ed;
+    p += 14;
+    for (int i=0; i<8; ++i) {
+        LD2D(p, &emu->x87[7-i].d);
        p+=10;
    }
 }
@@ -215,7 +236,19 @@ void native_frstor(x64emu_t* emu, uint8_t* ed)
    uint8_t* p = ed;
    p += 28;
    for (int i=0; i<8; ++i) {
-        D2LD(&ST(i).d, p);
+        D2LD(&emu->x87[7-i].d, p);
+        p+=10;
+    }
+
+}
+void native_frstor16(x64emu_t* emu, uint8_t* ed)
+{
+    fpu_loadenv(emu, (char*)ed, 1);
+
+    uint8_t* p = ed;
+    p += 14;
+    for (int i=0; i<8; ++i) {
+        D2LD(&emu->x87[7-i].d, p);
        p+=10;
    }

@@ -245,23 +278,23 @@ void native_fprem1(x64emu_t* emu)

 static uint8_t ff_mult(uint8_t a, uint8_t b)
 {
-	int retval = 0;
+    int retval = 0;

-	for(int i = 0; i < 8; i++) {
-		if((b & 1) == 1)
-			retval ^= a;
+    for(int i = 0; i < 8; i++) {
+        if((b & 1) == 1)
+            retval ^= a;

-		if((a & 0x80)) {
-			a <<= 1;
-			a  ^= 0x1b;
-		} else {
-			a <<= 1;
-		}
+        if((a & 0x80)) {
+            a <<= 1;
+            a  ^= 0x1b;
+        } else {
+            a <<= 1;
+        }

-		b >>= 1;
-	}
+        b >>= 1;
+    }

-	return retval;
+    return retval;
 }

 void native_aesimc(x64emu_t* emu, int xmm)
@@ -275,6 +308,17 @@ void native_aesimc(x64emu_t* emu, int xmm)
        emu->xmm[xmm].ub[3+j*4] = ff_mult(0x0B, eax1.ub[0+j*4]) ^ ff_mult(0x0D, eax1.ub[1+j*4]) ^ ff_mult(0x09, eax1.ub[2+j*4]) ^ ff_mult(0x0E, eax1.ub[3+j*4]);
    }
 }
+void native_aesimc_y(x64emu_t* emu, int ymm)
+{
+    sse_regs_t eay1 = emu->ymm[ymm];
+
+    for(int j=0; j<4; ++j) {
+        emu->ymm[ymm].ub[0+j*4] = ff_mult(0x0E, eay1.ub[0+j*4]) ^ ff_mult(0x0B, eay1.ub[1+j*4]) ^ ff_mult(0x0D, eay1.ub[2+j*4]) ^ ff_mult(0x09, eay1.ub[3+j*4]);
+        emu->ymm[ymm].ub[1+j*4] = ff_mult(0x09, eay1.ub[0+j*4]) ^ ff_mult(0x0E, eay1.ub[1+j*4]) ^ ff_mult(0x0B, eay1.ub[2+j*4]) ^ ff_mult(0x0D, eay1.ub[3+j*4]);
+        emu->ymm[ymm].ub[2+j*4] = ff_mult(0x0D, eay1.ub[0+j*4]) ^ ff_mult(0x09, eay1.ub[1+j*4]) ^ ff_mult(0x0E, eay1.ub[2+j*4]) ^ ff_mult(0x0B, eay1.ub[3+j*4]);
+        emu->ymm[ymm].ub[3+j*4] = ff_mult(0x0B, eay1.ub[0+j*4]) ^ ff_mult(0x0D, eay1.ub[1+j*4]) ^ ff_mult(0x09, eay1.ub[2+j*4]) ^ ff_mult(0x0E, eay1.ub[3+j*4]);
+    }
+}
 void native_aesmc(x64emu_t* emu, int xmm)
 {
    sse_regs_t eax1 = emu->xmm[xmm];
@@ -286,29 +330,40 @@ void native_aesmc(x64emu_t* emu, int xmm)
        emu->xmm[xmm].ub[3+j*4] = ff_mult(0x03, eax1.ub[0+j*4]) ^               eax1.ub[1+j*4]  ^               eax1.ub[2+j*4]  ^ ff_mult(0x02, eax1.ub[3+j*4]);
    }
 }
+void native_aesmc_y(x64emu_t* emu, int ymm)
+{
+    sse_regs_t eay1 = emu->ymm[ymm];
+
+    for(int j=0; j<4; ++j) {
+        emu->ymm[ymm].ub[0+j*4] = ff_mult(0x02, eay1.ub[0+j*4]) ^ ff_mult(0x03, eay1.ub[1+j*4]) ^               eay1.ub[2+j*4]  ^               eay1.ub[3+j*4] ;
+        emu->ymm[ymm].ub[1+j*4] =               eay1.ub[0+j*4]  ^ ff_mult(0x02, eay1.ub[1+j*4]) ^ ff_mult(0x03, eay1.ub[2+j*4]) ^               eay1.ub[3+j*4] ;
+        emu->ymm[ymm].ub[2+j*4] =               eay1.ub[0+j*4]  ^               eay1.ub[1+j*4]  ^ ff_mult(0x02, eay1.ub[2+j*4]) ^ ff_mult(0x03, eay1.ub[3+j*4]);
+        emu->ymm[ymm].ub[3+j*4] = ff_mult(0x03, eay1.ub[0+j*4]) ^               eay1.ub[1+j*4]  ^               eay1.ub[2+j*4]  ^ ff_mult(0x02, eay1.ub[3+j*4]);
+    }
+}
+                                  //   A0 B1 C2 D3 E4 F5 G6 H7 I8 J9 Ka Lb Mc Nd Oe Pf
+                                  //   A  N  K  H  E  B  O  L  I  F  C  P  M  J  G  D
+static const uint8_t invshiftrows[] = {0,13,10, 7, 4, 1,14,11, 8, 5, 2,15,12, 9, 6, 3};
+static const uint8_t invsubbytes[256] = {
+    0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
+    0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
+    0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
+    0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
+    0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
+    0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
+    0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
+    0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
+    0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
+    0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
+    0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
+    0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
+    0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
+    0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
+    0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
+    0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d,
+};
 void native_aesdlast(x64emu_t* emu, int xmm)
 {
-                            //   A0 B1 C2 D3 E4 F5 G6 H7 I8 J9 Ka Lb Mc Nd Oe Pf
-                            //   A  N  K  H  E  B  O  L  I  F  C  P  M  J  G  D
-    const uint8_t invshiftrows[] = {0,13,10, 7, 4, 1,14,11, 8, 5, 2,15,12, 9, 6, 3};
-    const uint8_t invsubbytes[256] = {
-        0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
-        0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
-        0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
-        0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
-        0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
-        0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
-        0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
-        0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
-        0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
-        0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
-        0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
-        0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
-        0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
-        0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
-        0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
-        0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d,
-    };

    sse_regs_t eax1;
    for(int i=0; i<16; ++i)
@@ -317,6 +372,17 @@ void native_aesdlast(x64emu_t* emu, int xmm)
    for(int i=0; i<16; ++i)
        emu->xmm[xmm].ub[i] = invsubbytes[eax1.ub[i]];

+}
+void native_aesdlast_y(x64emu_t* emu, int ymm)
+{
+
+    sse_regs_t eay1;
+    for(int i=0; i<16; ++i)
+        eay1.ub[i] = emu->ymm[ymm].ub[invshiftrows[i]];
+    //STATE ← InvSubBytes( STATE );
+    for(int i=0; i<16; ++i)
+        emu->ymm[ymm].ub[i] = invsubbytes[eay1.ub[i]];
+
 }
 static const uint8_t shiftrows[] = {0, 5,10,15, 4, 9,14, 3, 8,13, 2, 7,12, 1, 6,11};
 static const uint8_t subbytes[256] = {
@@ -348,16 +414,34 @@ void native_aeselast(x64emu_t* emu, int xmm)
    for(int i=0; i<16; ++i)
        emu->xmm[xmm].ub[i] = subbytes[eax1.ub[i]];
 }
+void native_aeselast_y(x64emu_t* emu, int ymm)
+{
+    sse_regs_t eay1;
+    for(int i=0; i<16; ++i)
+        eay1.ub[i] = emu->ymm[ymm].ub[shiftrows[i]];
+    for(int i=0; i<16; ++i)
+        emu->ymm[ymm].ub[i] = subbytes[eay1.ub[i]];
+}
 void native_aesd(x64emu_t* emu, int xmm)
 {
    native_aesdlast(emu, xmm);
    native_aesimc(emu, xmm);
 }
+void native_aesd_y(x64emu_t* emu, int ymm)
+{
+    native_aesdlast_y(emu, ymm);
+    native_aesimc_y(emu, ymm);
+}
 void native_aese(x64emu_t* emu, int xmm)
 {
    native_aeselast(emu, xmm);
    native_aesmc(emu, xmm);
 }
+void native_aese_y(x64emu_t* emu, int ymm)
+{
+    native_aeselast_y(emu, ymm);
+    native_aesmc_y(emu, ymm);
+}
 void native_aeskeygenassist(x64emu_t* emu, int gx, int ex, void* p, uint32_t u8)
 {
    sse_regs_t *EX = p?((sse_regs_t*)p):&emu->xmm[ex];
@@ -393,6 +477,40 @@ void native_pclmul(x64emu_t* emu, int gx, int ex, void* p, uint32_t u8)
    GX->q[0] = result&0xffffffffffffffffLL;
    GX->q[1] = (result>>64)&0xffffffffffffffffLL;
 }
+void native_pclmul_x(x64emu_t* emu, int gx, int vx, void* p, uint32_t u8)
+{
+
+    sse_regs_t *EX = ((uintptr_t)p<16)?((sse_regs_t*)p):&emu->xmm[(uintptr_t)p];
+    sse_regs_t *GX = &emu->xmm[gx];
+    sse_regs_t *VX = &emu->xmm[vx];
+    int g = (u8&1)?1:0;
+    int e = (u8&0b10000)?1:0;
+    __int128 result = 0;
+    __int128 op2 = EX->q[e];
+    for (int i=0; i<64; ++i)
+        if(VX->q[g]&(1LL<<i))
+            result ^= (op2<<i);
+
+    GX->q[0] = result&0xffffffffffffffffLL;
+    GX->q[1] = (result>>64)&0xffffffffffffffffLL;
+}
+void native_pclmul_y(x64emu_t* emu, int gy, int vy, void* p, uint32_t u8)
+{
+
+    sse_regs_t *EY = ((uintptr_t)p<16)?((sse_regs_t*)p):&emu->ymm[(uintptr_t)p];
+    sse_regs_t *GY = &emu->ymm[gy];
+    sse_regs_t *VY = &emu->ymm[vy];
+    int g = (u8&1)?1:0;
+    int e = (u8&0b10000)?1:0;
+    __int128 result = 0;
+    __int128 op2 = EY->q[e];
+    for (int i=0; i<64; ++i)
+        if(VY->q[g]&(1LL<<i))
+            result ^= (op2<<i);
+
+    GY->q[0] = result&0xffffffffffffffffLL;
+    GY->q[1] = (result>>64)&0xffffffffffffffffLL;
+}

 void native_clflush(x64emu_t* emu, void* p)
 {
@@ -405,7 +523,7 @@ static int flagsCacheNeedsTransform(dynarec_native_t* dyn, int ninst) {
        return 0;
    if(dyn->insts[ninst].f_exit.dfnone)  // flags are fully known, nothing we can do more
        return 0;
-    if(dyn->insts[jmp].f_entry.dfnone && !dyn->insts[ninst].f_exit.dfnone)
+    if(dyn->insts[jmp].f_entry.dfnone && !dyn->insts[ninst].f_exit.dfnone && !dyn->insts[jmp].df_notneeded)
        return 1;
    switch (dyn->insts[jmp].f_entry.pending) {
        case SF_UNKNOWN: return 0;
@@ -476,7 +594,7 @@ uintptr_t fakeed(dynarec_native_t* dyn, uintptr_t addr, int ninst, uint8_t nexto
    }
    return addr;
 }
-// return Ib on a mod/rm opcode without emiting anything
+// return Ib on a mod/rm opcode without emitting anything
 uint8_t geted_ib(dynarec_native_t* dyn, uintptr_t addr, int ninst, uint8_t nextop)
 {
    addr = fakeed(dyn, addr, ninst, nextop);
@@ -484,9 +602,11 @@ uint8_t geted_ib(dynarec_native_t* dyn, uintptr_t addr, int ninst, uint8_t nexto
 }
 #undef F8

-int isNativeCall(dynarec_native_t* dyn, uintptr_t addr, uintptr_t* calladdress, int* retn)
+int isNativeCall(dynarec_native_t* dyn, uintptr_t addr, int is32bits, uintptr_t* calladdress, uint16_t* retn)
 {
    (void)dyn;
+    if(is32bits)
+        addr &= 0xFFFFFFFFLL;

 #define PK(a)       *(uint8_t*)(addr+a)
 #define PK32(a)     *(int32_t*)(addr+a)
@@ -500,7 +620,7 @@ int isNativeCall(dynarec_native_t* dyn, uintptr_t addr, uintptr_t* calladdress,
    if(!addr || !getProtection(addr))
        return 0;
    onebridge_t *b = (onebridge_t*)(addr);
-    if(b->CC==0xCC && b->S=='S' && b->C=='C' && b->w!=(wrapper_t)0 && b->f!=(uintptr_t)PltResolver) {
+    if(b->CC==0xCC && b->S=='S' && b->C=='C' && b->w!=(wrapper_t)0 && b->f!=(uintptr_t)PltResolver64) {
        // found !
        if(retn) *retn = (b->C3==0xC2)?b->N:0;
        if(calladdress) *calladdress = addr+1;
@@ -510,3 +630,43 @@ int isNativeCall(dynarec_native_t* dyn, uintptr_t addr, uintptr_t* calladdress,
 #undef PK32
 #undef PK
 }
+
+// AVX
+void avx_mark_zero(dynarec_native_t* dyn, int ninst, int reg)
+{
+    dyn->ymm_zero |= (1<<reg);
+}
+
+int is_avx_zero(dynarec_native_t* dyn, int ninst, int reg)
+{
+    return (dyn->ymm_zero>>reg)&1;
+}
+int is_avx_zero_unset(dynarec_native_t* dyn, int ninst, int reg)
+{
+    if((dyn->ymm_zero>>reg)&1) {
+        dyn->ymm_zero &= ~(1<<reg);
+        return 1;    
+    }
+    return 0;
+}
+void avx_mark_zero_reset(dynarec_native_t* dyn, int ninst)
+{
+    dyn->ymm_zero = 0;
+}
+
+void avx_unmark_zero(dynarec_native_t* dyn, int ninst, int reg)
+{
+    dyn->ymm_zero &= ~(1<<reg);
+}
+
+void propagate_nodf(dynarec_native_t* dyn, int ninst)
+{
+    while(ninst>=0) {
+        if(dyn->insts[ninst].df_notneeded)
+            return; // already flagged
+        if(dyn->insts[ninst].x64.gen_flags || dyn->insts[ninst].x64.use_flags)
+            return; // flags are use, so maybe it's needed
+        dyn->insts[ninst].df_notneeded = 1;
+        --ninst;       
+    }
+}
@@ -30,16 +30,25 @@ void native_fistp64(x64emu_t* emu, int64_t* ed);
 void native_fistt64(x64emu_t* emu, int64_t* ed);
 void native_fld(x64emu_t* emu, uint8_t* ed);
 void native_fsave(x64emu_t* emu, uint8_t* ed);
+void native_fsave16(x64emu_t* emu, uint8_t* ed);
 void native_frstor(x64emu_t* emu, uint8_t* ed);
+void native_frstor16(x64emu_t* emu, uint8_t* ed);
 void native_fprem1(x64emu_t* emu);

 void native_aesd(x64emu_t* emu, int xmm);
+void native_aesd_y(x64emu_t* emu, int ymm);
 void native_aese(x64emu_t* emu, int xmm);
+void native_aese_y(x64emu_t* emu, int ymm);
 void native_aesdlast(x64emu_t* emu, int xmm);
+void native_aesdlast_y(x64emu_t* emu, int ymm);
 void native_aeselast(x64emu_t* emu, int xmm);
+void native_aeselast_y(x64emu_t* emu, int ymm);
 void native_aesimc(x64emu_t* emu, int xmm);
+void native_aesimc_y(x64emu_t* emu, int ymm);
 void native_aeskeygenassist(x64emu_t* emu, int gx, int ex, void* p, uint32_t u8);
 void native_pclmul(x64emu_t* emu, int gx, int ex, void* p, uint32_t u8);
+void native_pclmul_x(x64emu_t* emu, int gx, int vx, void* p, uint32_t u8);
+void native_pclmul_y(x64emu_t* emu, int gy, int vy, void* p, uint32_t u8);

 void native_clflush(x64emu_t* emu, void* p);

@@ -52,6 +61,8 @@ void native_div0(x64emu_t* emu);

 // Caches transformation (for loops) // Specific, need to be written par backend
 int CacheNeedsTransform(dynarec_native_t* dyn, int i1);
+// propagete defererd to unknow, as state is not needed
+void propagate_nodf(dynarec_native_t* dyn, int ninst);

 // predecessor access
 int isPred(dynarec_native_t* dyn, int ninst, int pred);
@@ -59,11 +70,18 @@ int getNominalPred(dynarec_native_t* dyn, int ninst);

 // Do the GETED, but don't emit anything...
 uintptr_t fakeed(dynarec_native_t* dyn, uintptr_t addr, int ninst, uint8_t nextop);
-// return Ib on a mod/rm opcode without emiting anything
+// return Ib on a mod/rm opcode without emitting anything
 uint8_t geted_ib(dynarec_native_t* dyn, uintptr_t addr, int ninst, uint8_t nextop);

 // Is what pointed at addr a native call? And if yes, to what function?
-int isNativeCall(dynarec_native_t* dyn, uintptr_t addr, uintptr_t* calladdress, int* retn);
+int isNativeCall(dynarec_native_t* dyn, uintptr_t addr, int is32bits, uintptr_t* calladdress, uint16_t* retn);
+
+// AVX utilities
+void avx_mark_zero(dynarec_native_t* dyn, int ninst, int reg);
+int is_avx_zero(dynarec_native_t* dyn, int ninst, int reg);
+int is_avx_zero_unset(dynarec_native_t* dyn, int ninst, int reg);
+void avx_mark_zero_reset(dynarec_native_t* dyn, int ninst);
+void avx_unmark_zero(dynarec_native_t* dyn, int ninst, int reg);

 ADDITIONNAL_DEFINITION()

@@ -26,6 +26,12 @@
 #error No STEP defined
 #endif

+#if STEP == 0
+#ifndef PROT_READ
+#define PROT_READ 0x1
+#endif
+#endif
+
 uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int is32bits)
 {
    int ok = 1;
@@ -34,7 +40,7 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
    uintptr_t ip = addr;
    uintptr_t init_addr = addr;
    rex_t rex;
-    int rep;    // 0 none, 1=F2 prefix, 2=F3 prefix
+    int rep = 0;    // 0 none, 1=F2 prefix, 2=F3 prefix
    int need_epilog = 1;
    // Clean up (because there are multiple passes)
    dyn->f.pending = 0;
@@ -43,14 +49,38 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
    dyn->forward_to = 0;
    dyn->forward_size = 0;
    dyn->forward_ninst = 0;
+    dyn->ymm_zero = 0;
+    #if STEP == 0
+    memset(&dyn->insts[ninst], 0, sizeof(instruction_native_t));
+    #endif
    fpu_reset(dyn);
    ARCH_INIT();
-    int reset_n = -1;
+    int reset_n = -1; // -1 no reset; -2 reset to 0; else reset to the state of reset_n
    dyn->last_ip = (alternate || (dyn->insts && dyn->insts[0].pred_sz))?0:ip;  // RIP is always set at start of block unless there is a predecessor!
    int stopblock = 2+(FindElfAddress(my_context, addr)?0:1); // if block is in elf_memory, it can be extended with box64_dynarec_bigblock==2, else it needs 3
    // ok, go now
    INIT;
+    #if STEP == 0
+    uintptr_t cur_page = (addr)&~(box64_pagesize-1);
+    #endif
    while(ok) {
+        #if STEP == 0
+        if(cur_page != ((addr)&~(box64_pagesize-1))) {
+            cur_page = (addr)&~(box64_pagesize-1);
+            if(!(getProtection(addr)&PROT_READ)) {
+                need_epilog = 1;
+                break;
+            }
+        }
+        // This test is here to prevent things like TABLE64 to be out of range
+        // native_size is not exact at this point, but it should be larger, not smaller, and not by a huge margin anyway
+        // so it's good enough to avoid overflow in relative to PC data fectching
+        if((dyn->native_size >= MAXBLOCK_SIZE) || (ninst >= MAX_INSTS)) {
+            need_epilog = 1;
+            break;
+        }
+        #endif
+        fpu_propagate_stack(dyn, ninst);
        ip = addr;
        if (reset_n!=-1) {
            dyn->last_ip = 0;
@@ -59,6 +89,7 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
                dyn->f.dfnone = 0;
                dyn->f.pending = 0;
                fpu_reset(dyn);
+                ARCH_RESET();
            } else {
                fpu_reset_cache(dyn, ninst, reset_n);
                dyn->f = dyn->insts[reset_n].f_exit;
@@ -73,27 +104,32 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
                }
            }
            reset_n = -1;
-        } else if(ninst && (dyn->insts[ninst].pred_sz>1 || (dyn->insts[ninst].pred_sz==1 && dyn->insts[ninst].pred[0]!=ninst-1)))
-            dyn->last_ip = 0;   // reset IP if some jump are coming here
-        fpu_propagate_stack(dyn, ninst);
-        NEW_INST;
-        #if STEP == 0
-        if(ninst && dyn->insts[ninst-1].x64.barrier_next) {
-            BARRIER(dyn->insts[ninst-1].x64.barrier_next);
        }
+        #if STEP > 0
+        else if(ninst && (dyn->insts[ninst].pred_sz>1 || (dyn->insts[ninst].pred_sz==1 && dyn->insts[ninst].pred[0]!=ninst-1)))
+            dyn->last_ip = 0;   // reset IP if some jump are coming here
        #endif
+        dyn->f.dfnone_here = 0;
+        NEW_INST;
+        MESSAGE(LOG_DUMP, "New Instruction %s:%p, native:%p\n", is32bits?"x86":"x64",(void*)addr, (void*)dyn->block);
        if(!ninst) {
            GOTEST(x1, x2);
        }
        if(dyn->insts[ninst].pred_sz>1) {SMSTART();}
-        fpu_reset_scratch(dyn);
+        #if STEP > 1
+        if (dyn->insts[ninst].lock) {
+            WILLWRITELOCK(dyn->insts[ninst].lock);
+        } else if (dyn->insts[ninst].will_write) {
+            WILLWRITE();
+        }
+        #endif
        if((dyn->insts[ninst].x64.need_before&~X_PEND) && !dyn->insts[ninst].pred_sz) {
            READFLAGS(dyn->insts[ninst].x64.need_before&~X_PEND);
        }
-        if(box64_dynarec_test) {
-            MESSAGE(LOG_DUMP, "TEST INIT ----\n");
+        if(box64_dynarec_test && (!box64_dynarec_test_end || (ip>=box64_dynarec_test_start && ip<box64_dynarec_test_end) )) {
+            MESSAGE(LOG_DUMP, "TEST STEP ----\n");
            fpu_reflectcache(dyn, ninst, x1, x2, x3);
-            GO_TRACE(x64test_init, 1, x5);
+            GO_TRACE(x64test_step, 1, x5);
            fpu_unreflectcache(dyn, ninst, x1, x2, x3);
            MESSAGE(LOG_DUMP, "----------\n");
        }
@@ -132,23 +168,30 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
            }

        addr = dynarec64_00(dyn, addr, ip, ninst, rex, rep, &ok, &need_epilog);
-
+        if(dyn->abort)
+            return ip;
        INST_EPILOG;
-
+        fpu_reset_scratch(dyn);
        int next = ninst+1;
        #if STEP > 0
-        if(!dyn->insts[ninst].x64.has_next && dyn->insts[ninst].x64.jmp && dyn->insts[ninst].x64.jmp_insts!=-1)
-            next = dyn->insts[ninst].x64.jmp_insts;
-        #endif
        if(dyn->insts[ninst].x64.has_next && dyn->insts[next].x64.barrier) {
-            if(dyn->insts[next].x64.barrier&BARRIER_FLOAT)
+            if(dyn->insts[next].x64.barrier&BARRIER_FLOAT) {
+                #ifdef RV64
+                uint8_t tmp1, tmp2, tmp3;
+                if(dyn->insts[next].nat_flags_fusion) get_free_scratch(dyn, next, &tmp1, &tmp2, &tmp3, x1, x2, x3, x4, x5);
+                else { tmp1=x1; tmp2=x2; tmp3=x3; }
+                fpu_purgecache(dyn, ninst, 0, tmp1, tmp2, tmp3);
+                #else
                fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
+                #endif
+            }
            if(dyn->insts[next].x64.barrier&BARRIER_FLAGS) {
                dyn->f.pending = 0;
                dyn->f.dfnone = 0;
                dyn->last_ip = 0;
            }
        }
+        #endif
        #ifndef PROT_READ
        #define PROT_READ 1
        #endif
@@ -156,34 +199,45 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
        if(!ok && !need_epilog && (addr < (dyn->start+dyn->isize))) {
            ok = 1;
            // we use the 1st predecessor here
-            int ii = ninst+1;
-            if(ii<dyn->size && !dyn->insts[ii].pred_sz) {
-                while(ii<dyn->size && (!dyn->insts[ii].pred_sz || (dyn->insts[ii].pred_sz==1 && dyn->insts[ii].pred[0]==ii-1))) {
+            if((ninst+1)<dyn->size && !dyn->insts[ninst+1].x64.alive) {
+                // reset fpu value...
+                dyn->f.dfnone = 0;
+                dyn->f.pending = 0;
+                fpu_reset(dyn);
+                while((ninst+1)<dyn->size && !dyn->insts[ninst+1].x64.alive) {
                    // may need to skip opcodes to advance
                    ++ninst;
                    NEW_INST;
                    MESSAGE(LOG_DEBUG, "Skipping unused opcode\n");
                    INST_NAME("Skipped opcode");
+                    addr += dyn->insts[ninst].x64.size;
                    INST_EPILOG;
-                    addr += dyn->insts[ii].x64.size;
-                    ++ii;
                }
            }
-            if((dyn->insts[ii].x64.barrier&BARRIER_FULL)==BARRIER_FULL)
+            if((dyn->insts[ninst+1].x64.barrier&BARRIER_FULL)==BARRIER_FULL)
                reset_n = -2;    // hack to say Barrier!
            else {
-                reset_n = getNominalPred(dyn, ii);  // may get -1 if no predecessor are available
+                reset_n = getNominalPred(dyn, ninst+1);  // may get -1 if no predecessor are available
                if(reset_n==-1) {
                    reset_n = -2;
-                    MESSAGE(LOG_DEBUG, "Warning, Reset Caches mark not found\n");
+                    if(!dyn->insts[ninst].x64.has_callret) {
+                        MESSAGE(LOG_DEBUG, "Warning, Reset Caches mark not found\n");
+                    }
                }
            }
        }
        #else
+        // check if block need to be stopped, because it's a 00 00 opcode (unreadeable is already checked earlier)
+        if((ok>0) && !dyn->forward && !(*(uint8_t*)addr) && !(*(uint8_t*)(addr+1))) {
+            if(box64_dynarec_dump) dynarec_log(LOG_NONE, "Stopping block at %p reason: %s\n", (void*)addr, "Next opcode is 00 00");
+            ok = 0;
+            need_epilog = 1;
+        }
        if(dyn->forward) {
-            if(dyn->forward_to == addr && !need_epilog) {
+            if(dyn->forward_to == addr && !need_epilog && ok>=0) {
                // we made it!
-                if(box64_dynarec_dump) dynarec_log(LOG_NONE, "Forward extend block for %d bytes %s%p -> %p\n", dyn->forward_to-dyn->forward, dyn->insts[dyn->forward_ninst].x64.has_callret?"(opt. call) ":"", (void*)dyn->forward, (void*)dyn->forward_to);
+                reset_n = get_first_jump_addr(dyn, addr);
+                if(box64_dynarec_dump) dynarec_log(LOG_NONE, "Forward extend block for %d bytes %s%p -> %p (ninst %d - %d)\n", dyn->forward_to-dyn->forward, dyn->insts[dyn->forward_ninst].x64.has_callret?"(opt. call) ":"", (void*)dyn->forward, (void*)dyn->forward_to, reset_n, ninst);
                if(dyn->insts[dyn->forward_ninst].x64.has_callret && !dyn->insts[dyn->forward_ninst].x64.has_next)
                    dyn->insts[dyn->forward_ninst].x64.has_next = 1;  // this block actually continue
                dyn->forward = 0;
@@ -219,8 +273,8 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
                        // and pred table is not ready yet
                        reset_n = get_first_jump(dyn, next);
                    }
-                    if(box64_dynarec_dump) dynarec_log(LOG_NONE, "Extend block %p, %s%p -> %p (ninst=%d, jump from %d)\n", dyn, dyn->insts[ninst].x64.has_callret?"(opt. call) ":"", (void*)addr, (void*)next, ninst, dyn->insts[ninst].x64.has_callret?ninst:reset_n);
-                } else if(next && (next-addr)<box64_dynarec_forward && (getProtection(next)&PROT_READ)/*box64_dynarec_bigblock>=stopblock*/) {
+                    if(box64_dynarec_dump) dynarec_log(LOG_NONE, "Extend block %p, %s%p -> %p (ninst=%d, jump from %d)\n", dyn, dyn->insts[ninst].x64.has_callret?"(opt. call) ":"", (void*)addr, (void*)next, ninst+1, dyn->insts[ninst].x64.has_callret?ninst:reset_n);
+                } else if(next && (int)(next-addr)<box64_dynarec_forward && (getProtection(next)&PROT_READ)/*box64_dynarec_bigblock>=stopblock*/) {
                    if(!((box64_dynarec_bigblock<stopblock) && !isJumpTableDefault64((void*)next))) {
                        if(dyn->forward) {
                            if(next<dyn->forward_to)
@@ -262,12 +316,17 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
            }
            #endif
        }
+        if((ok>0) && dyn->insts[ninst].x64.has_callret)
+            reset_n = -2;
+        if((ok>0) && reset_n==-1 && dyn->insts[ninst+1].purge_ymm)
+            PURGE_YMM();
        ++ninst;
        #if STEP == 0
-        if(ok && (((box64_dynarec_bigblock<stopblock) && !isJumpTableDefault64((void*)addr))
+        memset(&dyn->insts[ninst], 0, sizeof(instruction_native_t));
+        if((ok>0) && (((box64_dynarec_bigblock<stopblock) && !isJumpTableDefault64((void*)addr))
            || (addr>=box64_nodynarec_start && addr<box64_nodynarec_end)))
        #else
-        if(ok && (ninst==dyn->size))
+        if((ok>0) && (ninst==dyn->size))
        #endif
        {
            #if STEP == 0
@@ -297,7 +356,7 @@ uintptr_t native_pass(dynarec_native_t* dyn, uintptr_t addr, int alternate, int
            ++ninst;
            NOTEST(x3);
            fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
-            jump_to_next(dyn, addr, 0, ninst);
+            jump_to_next(dyn, addr, 0, ninst, rex.is32bits);
            ok=0; need_epilog=0;
        }
    }
@@ -8,13 +8,13 @@ void arm64_epilog(void) EXPORTDYN;
 #define native_next         arm64_next
 #define native_prolog       arm64_prolog
 #define native_epilog       arm64_epilog
-#elif defined(LA464)
-void la464_next(void) EXPORTDYN;
-void la464_prolog(x64emu_t* emu, void* addr) EXPORTDYN;
-void la464_epilog(void) EXPORTDYN;
-#define native_next         la464_next
-#define native_prolog       la464_prolog
-#define native_epilog       la464_epilog
+#elif defined(LA64)
+void la64_next(void) EXPORTDYN;
+void la64_prolog(x64emu_t* emu, void* addr) EXPORTDYN;
+void la64_epilog(void) EXPORTDYN;
+#define native_next         la64_next
+#define native_prolog       la64_prolog
+#define native_epilog       la64_epilog
 #elif defined(RV64)
 void rv64_next(void) EXPORTDYN;
 void rv64_prolog(x64emu_t* emu, void* addr) EXPORTDYN;
@@ -24,17 +24,24 @@
 #define SF_SUB      4
 #define SF_SUBSET   (SF_SUB|SF_SET)
 #define SF_SUBSET_PENDING   (SF_SUBSET|SF_PENDING)
+#define SF_DF       8
+#define SF_SET_DF   (SF_SET|SF_DF)
+#define SF_NODF     16
+#define SF_SET_NODF (SF_SET|SF_NODF)
+
+#define NAT_FLAGS_FUSION   0
+#define NAT_FLAGS_NOFUSION 1

 typedef struct instruction_x64_s {
    uintptr_t   addr;       //address of the instruction
    int32_t     size;       // size of the instruction
    uintptr_t   jmp;        // offset to jump to, even if conditionnal (0 if not), no relative offset here
    int         jmp_insts;  // instuction to jump to (-1 if out of the block)
-    uint8_t     jmp_cond;   // 1 of conditionnal jump
-    uint8_t     has_next;   // does this opcode can continue to the next?
+    uint8_t     jmp_cond:1;   // 1 of conditionnal jump
+    uint8_t     has_next:1;   // does this opcode can continue to the next?
+    uint8_t     has_callret:1;    // this instruction have an optimised call setup
+    uint8_t     alive:1;    // this opcode gets executed (0 if dead code in that block)
    uint8_t     barrier;    // next instruction is a jump point, so no optim allowed
-    uint8_t     barrier_next;   // next instruction needs a barrier
-    uint8_t     has_callret;    // this instruction have an optimised call setup
    uint8_t     state_flags;// One of SF_XXX state
    uint8_t     use_flags;  // 0 or combination of X_?F
    uint8_t     set_flags;  // 0 or combination of X_?F
@@ -0,0 +1,438 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "la64_emitter.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+#include "custommem.h"
+
+#include "la64_printer.h"
+#include "dynarec_la64_private.h"
+#include "../dynarec_helper.h"
+#include "dynarec_la64_functions.h"
+
+uintptr_t dynarec64_64(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int seg, int* ok, int* need_epilog)
+{
+    (void)ip;
+    (void)rep;
+    (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop;
+    uint8_t u8;
+    uint8_t gd, ed, eb1, eb2, gb1, gb2;
+    uint8_t gback, wback, wb1, wb2, wb;
+    int64_t i64, j64;
+    uint64_t u64;
+    int v0, v1;
+    int q0;
+    int d0;
+    int64_t fixedaddress, gdoffset;
+    int unscaled;
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(j64);
+    MAYUSE(d0);
+    MAYUSE(q0);
+    MAYUSE(v0);
+    MAYUSE(v1);
+
+    while ((opcode == 0xF2) || (opcode == 0xF3)) {
+        rep = opcode - 0xF1;
+        opcode = F8;
+    }
+
+    GETREX();
+
+    switch (opcode) {
+        case 0x03:
+            INST_NAME("ADD Gd, Seg:Ed");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop = F8;
+            GETGD;
+            GETEDO(x4, 0);
+            emit_add32(dyn, ninst, rex, gd, ed, x3, x4, x5);
+            break;
+        case 0x2B:
+            INST_NAME("SUB Gd, Seg:Ed");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop = F8;
+            GETGD;
+            GETEDO(x4, 0);
+            emit_sub32(dyn, ninst, rex, gd, ed, x3, x4, x5);
+            break;
+        case 0x33:
+            INST_NAME("XOR Gd, Seg:Ed");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop = F8;
+            GETGD;
+            GETEDO(x4, 0);
+            emit_xor32(dyn, ninst, rex, gd, ed, x3, x4);
+            break;
+        case 0x64:
+            addr = dynarec64_64(dyn, addr, ip, ninst, rex, rep, _FS, ok, need_epilog);
+            break;
+        case 0x65:
+            addr = dynarec64_64(dyn, addr, ip, ninst, rex, rep, _GS, ok, need_epilog);
+            break;
+        case 0x66:
+            addr = dynarec64_6664(dyn, addr, ip, ninst, rex, seg, ok, need_epilog);
+            break;
+        case 0x80:
+            nextop = F8;
+            switch ((nextop >> 3) & 7) {
+                case 0: // ADD
+                    INST_NAME("ADD Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_add8c(dyn, ninst, x1, u8, x2, x4, x5);
+                    EBBACK();
+                    break;
+                case 1: // OR
+                    INST_NAME("OR Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_or8c(dyn, ninst, x1, u8, x2, x4, x5);
+                    EBBACK();
+                    break;
+                case 2: // ADC
+                    INST_NAME("ADC Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_adc8c(dyn, ninst, x1, u8, x2, x4, x5, x6);
+                    EBBACK();
+                    break;
+                case 3: // SBB
+                    INST_NAME("SBB Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_sbb8c(dyn, ninst, x1, u8, x2, x4, x5, x6);
+                    EBBACK();
+                    break;
+                case 4: // AND
+                    INST_NAME("AND Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_and8c(dyn, ninst, x1, u8, x2, x4);
+                    EBBACK();
+                    break;
+                case 5: // SUB
+                    INST_NAME("SUB Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_sub8c(dyn, ninst, x1, u8, x2, x4, x5, x6);
+                    EBBACK();
+                    break;
+                case 6: // XOR
+                    INST_NAME("XOR Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_xor8c(dyn, ninst, x1, u8, x2, x4);
+                    EBBACK();
+                    break;
+                case 7: // CMP
+                    INST_NAME("CMP Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    if (u8) {
+                        MOV32w(x2, u8);
+                        emit_cmp8(dyn, ninst, x1, x2, x3, x4, x5, x6);
+                    } else {
+                        emit_cmp8_0(dyn, ninst, x1, x3, x4);
+                    }
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+        case 0x81:
+        case 0x83:
+            nextop = F8;
+            grab_segdata(dyn, addr, ninst, x6, seg);
+            switch ((nextop >> 3) & 7) {
+                case 0:
+                    if (opcode == 0x81) {
+                        INST_NAME("ADD Ed, Id");
+                    } else {
+                        INST_NAME("ADD Ed, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode == 0x81) ? 4 : 1);
+                    if (opcode == 0x81)
+                        i64 = F32S;
+                    else
+                        i64 = F8S;
+                    emit_add32c(dyn, ninst, rex, ed, i64, x3, x4, x5, x7);
+                    WBACKO(x6);
+                    break;
+                case 1:
+                    if (opcode == 0x81) {
+                        INST_NAME("OR Ed, Id");
+                    } else {
+                        INST_NAME("OR Ed, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode == 0x81) ? 4 : 1);
+                    if (opcode == 0x81)
+                        i64 = F32S;
+                    else
+                        i64 = F8S;
+                    emit_or32c(dyn, ninst, rex, ed, i64, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 2:
+                    if (opcode == 0x81) {
+                        INST_NAME("ADC Ed, Id");
+                    } else {
+                        INST_NAME("ADC Ed, Ib");
+                    }
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode == 0x81) ? 4 : 1);
+                    if (opcode == 0x81)
+                        i64 = F32S;
+                    else
+                        i64 = F8S;
+                    MOV64xw(x5, i64);
+                    IFXA (X_ALL, !la64_lbt)
+                        ST_D(x6, xEmu, offsetof(x64emu_t, scratch));
+                    emit_adc32(dyn, ninst, rex, ed, x5, x3, x4, x6, x7);
+                    IFXA (X_ALL, !la64_lbt) {
+                        LD_D(x6, xEmu, offsetof(x64emu_t, scratch));
+                    }
+                    WBACKO(x6);
+                    break;
+                case 3:
+                    if (opcode == 0x81) {
+                        INST_NAME("SBB Ed, Id");
+                    } else {
+                        INST_NAME("SBB Ed, Ib");
+                    }
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode == 0x81) ? 4 : 1);
+                    if (opcode == 0x81)
+                        i64 = F32S;
+                    else
+                        i64 = F8S;
+                    MOV64xw(x5, i64);
+                    emit_sbb32(dyn, ninst, rex, ed, x5, x3, x4, x7);
+                    WBACKO(x6);
+                    break;
+                case 4:
+                    if (opcode == 0x81) {
+                        INST_NAME("AND Ed, Id");
+                    } else {
+                        INST_NAME("AND Ed, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode == 0x81) ? 4 : 1);
+                    if (opcode == 0x81)
+                        i64 = F32S;
+                    else
+                        i64 = F8S;
+                    emit_and32c(dyn, ninst, rex, ed, i64, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 5:
+                    if (opcode == 0x81) {
+                        INST_NAME("SUB Ed, Id");
+                    } else {
+                        INST_NAME("SUB Ed, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode == 0x81) ? 4 : 1);
+                    if (opcode == 0x81)
+                        i64 = F32S;
+                    else
+                        i64 = F8S;
+                    emit_sub32c(dyn, ninst, rex, ed, i64, x3, x4, x5, x7);
+                    WBACKO(x6);
+                    break;
+                case 6:
+                    if (opcode == 0x81) {
+                        INST_NAME("XOR Ed, Id");
+                    } else {
+                        INST_NAME("XOR Ed, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode == 0x81) ? 4 : 1);
+                    if (opcode == 0x81)
+                        i64 = F32S;
+                    else
+                        i64 = F8S;
+                    emit_xor32c(dyn, ninst, rex, ed, i64, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 7:
+                    if (opcode == 0x81) {
+                        INST_NAME("CMP Ed, Id");
+                    } else {
+                        INST_NAME("CMP Ed, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode == 0x81) ? 4 : 1);
+                    if (opcode == 0x81)
+                        i64 = F32S;
+                    else
+                        i64 = F8S;
+                    if (i64) {
+                        MOV64xw(x2, i64);
+                        emit_cmp32(dyn, ninst, rex, ed, x2, x3, x4, x5, x6);
+                    } else
+                        emit_cmp32_0(dyn, ninst, rex, ed, x3, x4);
+                    break;
+            }
+            break;
+        case 0x89:
+            INST_NAME("MOV Seg:Ed, Gd");
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop = F8;
+            GETGD;
+            if (MODREG) { // reg <= reg
+                MVxw(TO_NAT((nextop & 7) + (rex.b << 3)), gd);
+            } else { // mem <= reg
+                if (rex.is32bits) {
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                    ADDz(x4, ed, x4);
+                    SDxw(gd, x4, fixedaddress);
+                } else {
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 0, 0);
+                    SDXxw(gd, ed, x4);
+                }
+                SMWRITE2();
+            }
+            break;
+        case 0x8B:
+            INST_NAME("MOV Gd, Seg:Ed");
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop = F8;
+            GETGD;
+            if (MODREG) { // reg <= reg
+                MVxw(gd, TO_NAT((nextop & 7) + (rex.b << 3)));
+            } else { // mem <= reg
+                SMREAD();
+                if (rex.is32bits) {
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                    ADDz(x4, ed, x4);
+                    LDxw(gd, x4, fixedaddress);
+                } else {
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 0, 0);
+                    LDXxw(gd, ed, x4);
+                }
+            }
+            break;
+        case 0xA1:
+            INST_NAME("MOV EAX, FS:Od");
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            if (rex.is32bits)
+                u64 = F32;
+            else
+                u64 = F64;
+            MOV64z(x1, u64);
+            if (rex.is32bits) {
+                ADDz(x4, x1, x4);
+                LDxw(xRAX, x4, 0);
+            } else
+                LDXxw(xRAX, x4, x1);
+            break;
+        case 0xC6:
+            INST_NAME("MOV Seg:Eb, Ib");
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop = F8;
+            if (MODREG) { // reg <= u8
+                u8 = F8;
+                if (!rex.rex) {
+                    ed = (nextop & 7);
+                    eb1 = TO_NAT(ed & 3);  // Ax, Cx, Dx or Bx
+                    eb2 = (ed & 4) >> 2;   // L or H
+                } else {
+                    eb1 = TO_NAT((nextop & 7) + (rex.b << 3));
+                    eb2 = 0;
+                }
+                MOV32w(x3, u8);
+                BSTRINS_D(eb1, x3, eb2 * 8 + 7, eb2 * 8);
+            } else { // mem <= u8
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, x1, &fixedaddress, rex, NULL, 0, 1);
+                u8 = F8;
+                if (u8) {
+                    ADDI_D(x3, xZR, u8);
+                    ed = x3;
+                } else
+                    ed = xZR;
+                if (rex.is32bits) {
+                    ADDz(x4, wback, x4);
+                    ST_B(ed, x4, 0);
+                } else {
+                    STX_B(ed, wback, x4);
+                }
+                SMWRITE2();
+            }
+            break;
+        case 0xC7:
+            INST_NAME("MOV Seg:Ed, Id");
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop = F8;
+            if (MODREG) { // reg <= i32
+                i64 = F32S;
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                MOV64xw(ed, i64);
+            } else { // mem <= i32
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, x1, &fixedaddress, rex, NULL, 0, 4);
+                i64 = F32S;
+                if (i64) {
+                    MOV64x(x3, i64);
+                    ed = x3;
+                } else
+                    ed = xZR;
+                if (rex.is32bits) {
+                    ADDz(x4, wback, x4);
+                    SDxw(ed, x4, 0);
+                } else {
+                    SDXxw(ed, wback, x4);
+                }
+                SMWRITE2();
+            }
+            break;
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
@@ -0,0 +1,868 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "la64_emitter.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+#include "custommem.h"
+
+#include "la64_printer.h"
+#include "dynarec_la64_private.h"
+#include "../dynarec_helper.h"
+#include "dynarec_la64_functions.h"
+
+
+uintptr_t dynarec64_66(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
+{
+    uint8_t opcode = F8;
+    uint8_t nextop, u8;
+    int16_t i16;
+    uint16_t u16;
+    uint64_t u64;
+    int32_t i32;
+    int64_t j64;
+    uint8_t gd, ed;
+    uint8_t wback, wb1;
+    int64_t fixedaddress;
+    int unscaled;
+    int lock;
+    MAYUSE(u8);
+    MAYUSE(u16);
+    MAYUSE(u64);
+    MAYUSE(j64);
+    MAYUSE(lock);
+
+    while ((opcode == 0x2E) || (opcode == 0x36) || (opcode == 0x66)) // ignoring CS:, SS: or multiple 0x66
+        opcode = F8;
+
+    while ((opcode == 0xF2) || (opcode == 0xF3)) {
+        rep = opcode - 0xF1;
+        opcode = F8;
+    }
+
+    GETREX();
+
+    if (rex.w && !(opcode == 0x0f || opcode == 0xf0 || opcode == 0x64 || opcode == 0x65)) // rex.w cancels "66", but not for 66 0f type of prefix
+        return dynarec64_00(dyn, addr - 1, ip, ninst, rex, rep, ok, need_epilog);         // addr-1, to "put back" opcode
+
+    switch (opcode) {
+        case 0x01:
+            INST_NAME("ADD Ew, Gw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x2);
+            GETEW(x1, 0);
+            emit_add16(dyn, ninst, x1, x2, x4, x5, x6);
+            EWBACK;
+            break;
+        case 0x03:
+            INST_NAME("ADD Gw, Ew");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x1);
+            GETEW(x2, 0);
+            emit_add16(dyn, ninst, x1, x2, x3, x4, x6);
+            GWBACK;
+            break;
+        case 0x05:
+            INST_NAME("ADD AX, Iw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            i32 = F16;
+            BSTRPICK_D(x1, xRAX, 15, 0);
+            MOV32w(x2, i32);
+            emit_add16(dyn, ninst, x1, x2, x3, x4, x6);
+            BSTRINSz(xRAX, x1, 15, 0);
+            break;
+        case 0x09:
+            INST_NAME("OR Ew, Gw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x2);
+            GETEW(x1, 0);
+            emit_or16(dyn, ninst, x1, x2, x4, x5);
+            EWBACK;
+            break;
+        case 0x0B:
+            INST_NAME("OR Gw, Ew");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x1);
+            GETEW(x2, 0);
+            emit_or16(dyn, ninst, x1, x2, x4, x5);
+            GWBACK;
+            break;
+        case 0x0D:
+            INST_NAME("OR AX, Iw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            i32 = F16;
+            BSTRPICK_D(x1, xRAX, 15, 0);
+            MOV32w(x2, i32);
+            emit_or16(dyn, ninst, x1, x2, x3, x4);
+            BSTRINSz(xRAX, x1, 15, 0);
+            break;
+        case 0x0F:
+            switch (rep) {
+                case 0: addr = dynarec64_660F(dyn, addr, ip, ninst, rex, ok, need_epilog); break;
+                default:
+                    DEFAULT;
+            }
+            break;
+        case 0x11:
+            INST_NAME("ADC Ew, Gw");
+            READFLAGS(X_CF);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x2);
+            GETEW(x1, 0);
+            emit_adc16(dyn, ninst, x1, x2, x4, x6, x5);
+            EWBACK;
+            break;
+        case 0x13:
+            INST_NAME("ADC Gw, Ew");
+            READFLAGS(X_CF);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x1);
+            GETEW(x2, 0);
+            emit_adc16(dyn, ninst, x1, x2, x4, x6, x5);
+            GWBACK;
+            break;
+        case 0x15:
+            INST_NAME("ADC AX, Iw");
+            READFLAGS(X_CF);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            u64 = F16;
+            BSTRPICK_D(x1, xRAX, 15, 0);
+            MOV64x(x2, u64);
+            emit_adc16(dyn, ninst, x1, x2, x3, x4, x5);
+            BSTRINSz(xRAX, x1, 15, 0);
+            break;
+        case 0x19:
+            INST_NAME("SBB Ew, Gw");
+            READFLAGS(X_CF);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x2);
+            GETEW(x1, 0);
+            emit_sbb16(dyn, ninst, x1, x2, x4, x5, x6);
+            EWBACK;
+            break;
+        case 0x1B:
+            INST_NAME("SBB Gw, Ew");
+            READFLAGS(X_CF);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x1);
+            GETEW(x2, 0);
+            emit_sbb16(dyn, ninst, x1, x2, x6, x4, x5);
+            GWBACK;
+            break;
+        case 0x1D:
+            INST_NAME("SBB AX, Iw");
+            READFLAGS(X_CF);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            BSTRPICK_D(x1, xRAX, 15, 0);
+            u64 = F16;
+            MOV64x(x2, u64);
+            emit_sbb16(dyn, ninst, x1, x2, x3, x4, x5);
+            BSTRINSz(xRAX, x1, 15, 0);
+            break;
+        case 0x21:
+            INST_NAME("AND Ew, Gw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x2);
+            GETEW(x1, 0);
+            emit_and16(dyn, ninst, x1, x2, x4, x5);
+            EWBACK;
+            break;
+        case 0x23:
+            INST_NAME("AND Gw, Ew");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x1);
+            GETEW(x2, 0);
+            emit_and16(dyn, ninst, x1, x2, x3, x4);
+            GWBACK;
+            break;
+        case 0x25:
+            INST_NAME("AND AX, Iw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            i32 = F16;
+            BSTRPICK_D(x1, xRAX, 15, 0);
+            MOV32w(x2, i32);
+            emit_and16(dyn, ninst, x1, x2, x3, x4);
+            BSTRINSz(xRAX, x1, 15, 0);
+            break;
+        case 0x29:
+            INST_NAME("SUB Ew, Gw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x1);
+            GETEW(x2, 0);
+            emit_sub16(dyn, ninst, x2, x1, x4, x5, x6);
+            EWBACK;
+            break;
+        case 0x2B:
+            INST_NAME("SUB Gw, Ew");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x1);
+            GETEW(x2, 0);
+            emit_sub16(dyn, ninst, x1, x2, x3, x4, x5);
+            GWBACK;
+            break;
+        case 0x2D:
+            INST_NAME("SUB AX, Iw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            i32 = F16;
+            BSTRPICK_D(x1, xRAX, 15, 0);
+            MOV32w(x2, i32);
+            emit_sub16(dyn, ninst, x1, x2, x3, x4, x5);
+            BSTRINSz(xRAX, x1, 15, 0);
+            break;
+        case 0x31:
+            INST_NAME("XOR Ew, Gw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x2);
+            GETEW(x1, 0);
+            emit_xor16(dyn, ninst, x1, x2, x4, x5, x6);
+            EWBACK;
+            break;
+        case 0x33:
+            INST_NAME("XOR Gw, Ew");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x1);
+            GETEW(x2, 0);
+            emit_xor16(dyn, ninst, x1, x2, x3, x4, x5);
+            GWBACK;
+            break;
+        case 0x35:
+            INST_NAME("XOR AX, Iw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            i32 = F16;
+            BSTRPICK_D(x1, xRAX, 15, 0);
+            MOV32w(x2, i32);
+            emit_xor16(dyn, ninst, x1, x2, x3, x4, x5);
+            BSTRINSz(xRAX, x1, 15, 0);
+            break;
+        case 0x39:
+            INST_NAME("CMP Ew, Gw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x2);
+            GETEW(x1, 0);
+            emit_cmp16(dyn, ninst, x1, x2, x3, x4, x5, x6);
+            break;
+        case 0x3B:
+            INST_NAME("CMP Gw, Ew");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x1);
+            GETEW(x2, 0);
+            emit_cmp16(dyn, ninst, x1, x2, x3, x4, x5, x6);
+            break;
+        case 0x3D:
+            INST_NAME("CMP AX, Iw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            i32 = F16;
+            BSTRPICK_D(x1, xRAX, 15, 0);
+            if (i32) {
+                MOV32w(x2, i32);
+                emit_cmp16(dyn, ninst, x1, x2, x3, x4, x5, x6);
+            } else {
+                emit_cmp16_0(dyn, ninst, x1, x3, x4);
+            }
+            break;
+        case 0x64:
+            addr = dynarec64_6664(dyn, addr, ip, ninst, rex, _FS, ok, need_epilog);
+            break;
+        case 0x65:
+            addr = dynarec64_6664(dyn, addr, ip, ninst, rex, _GS, ok, need_epilog);
+            break;
+        case 0x66:
+            addr = dynarec64_66(dyn, addr, ip, ninst, rex, rep, ok, need_epilog);
+            break;
+        case 0x69:
+        case 0x6B:
+            if (opcode == 0x69) {
+                INST_NAME("IMUL Gw,Ew,Iw");
+            } else {
+                INST_NAME("IMUL Gw,Ew,Ib");
+            }
+            SETFLAGS(X_ALL, SF_PENDING);
+            nextop = F8;
+            GETSEW(x1, (opcode == 0x69) ? 2 : 1);
+            if (opcode == 0x69)
+                i32 = F16S;
+            else
+                i32 = F8S;
+            MOV32w(x2, i32);
+            MUL_W(x2, x2, x1);
+            UFLAG_RES(x2);
+            gd = x2;
+            GWBACK;
+            UFLAG_DF(x1, d_imul16);
+            break;
+        case 0x81:
+        case 0x83:
+            nextop = F8;
+            switch ((nextop >> 3) & 7) {
+                case 0: // ADD
+                    if (opcode == 0x81) {
+                        INST_NAME("ADD Ew, Iw");
+                    } else {
+                        INST_NAME("ADD Ew, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEW(x1, (opcode == 0x81) ? 2 : 1);
+                    if (opcode == 0x81)
+                        u64 = F16;
+                    else
+                        u64 = (uint16_t)(int16_t)F8S;
+                    MOV64x(x5, u64);
+                    emit_add16(dyn, ninst, ed, x5, x2, x4, x6);
+                    EWBACK;
+                    break;
+                case 1: // OR
+                    if (opcode == 0x81) {
+                        INST_NAME("OR Ew, Iw");
+                    } else {
+                        INST_NAME("OR Ew, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEW(x1, (opcode == 0x81) ? 2 : 1);
+                    if (opcode == 0x81)
+                        u64 = F16;
+                    else
+                        u64 = (uint16_t)(int16_t)F8S;
+                    MOV64x(x5, u64);
+                    emit_or16(dyn, ninst, x1, x5, x2, x4);
+                    EWBACK;
+                    break;
+                case 2: // ADC
+                    if (opcode == 0x81) {
+                        INST_NAME("ADC Ew, Iw");
+                    } else {
+                        INST_NAME("ADC Ew, Ib");
+                    }
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEW(x1, (opcode == 0x81) ? 2 : 1);
+                    if (opcode == 0x81)
+                        u64 = F16;
+                    else
+                        u64 = (uint16_t)(int16_t)F8S;
+                    MOV64x(x5, u64);
+                    emit_adc16(dyn, ninst, x1, x5, x2, x4, x6);
+                    EWBACK;
+                    break;
+                case 3: // SBB
+                    if (opcode == 0x81) {
+                        INST_NAME("SBB Ew, Iw");
+                    } else {
+                        INST_NAME("SBB Ew, Ib");
+                    }
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEW(x1, (opcode == 0x81) ? 2 : 1);
+                    if (opcode == 0x81)
+                        u64 = F16;
+                    else
+                        u64 = (uint16_t)(int16_t)F8S;
+                    MOV64x(x5, u64);
+                    emit_sbb16(dyn, ninst, x1, x5, x2, x4, x6);
+                    EWBACK;
+                    break;
+                case 4: // AND
+                    if (opcode == 0x81) {
+                        INST_NAME("AND Ew, Iw");
+                    } else {
+                        INST_NAME("AND Ew, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEW(x1, (opcode == 0x81) ? 2 : 1);
+                    if (opcode == 0x81)
+                        u64 = F16;
+                    else
+                        u64 = (uint16_t)(int16_t)F8S;
+                    MOV64x(x5, u64);
+                    emit_and16(dyn, ninst, x1, x5, x2, x4);
+                    EWBACK;
+                    break;
+                case 5: // SUB
+                    if (opcode == 0x81) {
+                        INST_NAME("SUB Ew, Iw");
+                    } else {
+                        INST_NAME("SUB Ew, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEW(x1, (opcode == 0x81) ? 2 : 1);
+                    if (opcode == 0x81)
+                        u64 = F16;
+                    else
+                        u64 = (uint16_t)(int16_t)F8S;
+                    MOV32w(x5, u64);
+                    emit_sub16(dyn, ninst, x1, x5, x2, x4, x6);
+                    EWBACK;
+                    break;
+                case 6: // XOR
+                    if (opcode == 0x81) {
+                        INST_NAME("XOR Ew, Iw");
+                    } else {
+                        INST_NAME("XOR Ew, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEW(x1, (opcode == 0x81) ? 2 : 1);
+                    if (opcode == 0x81)
+                        u64 = F16;
+                    else
+                        u64 = (uint16_t)(int16_t)F8S;
+                    MOV32w(x5, u64);
+                    emit_xor16(dyn, ninst, x1, x5, x2, x4, x6);
+                    EWBACK;
+                    break;
+                case 7: // CMP
+                    if (opcode == 0x81) {
+                        INST_NAME("CMP Ew, Iw");
+                    } else {
+                        INST_NAME("CMP Ew, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEW(x1, (opcode == 0x81) ? 2 : 1);
+                    if (opcode == 0x81)
+                        u64 = F16;
+                    else
+                        u64 = (uint16_t)(int16_t)F8S;
+                    if (u64) {
+                        MOV64x(x2, u64);
+                        emit_cmp16(dyn, ninst, x1, x2, x3, x4, x5, x6);
+                    } else
+                        emit_cmp16_0(dyn, ninst, x1, x3, x4);
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+        case 0x85:
+            INST_NAME("TEST Ew, Gw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETEW(x1, 0);
+            GETGW(x2);
+            emit_test16(dyn, ninst, x1, x2, x3, x4, x5);
+            break;
+        case 0x89:
+            INST_NAME("MOV Ew, Gw");
+            nextop = F8;
+            GETGD;
+            if (MODREG) {
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                if (ed != gd) {
+                    BSTRINSz(ed, gd, 15, 0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, &lock, 1, 0);
+                ST_H(gd, ed, fixedaddress);
+                SMWRITELOCK(lock);
+            }
+            break;
+        case 0x8B:
+            INST_NAME("MOV Gw, Ew");
+            nextop = F8;
+            GETGD;
+            if (MODREG) {
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                if (ed != gd) {
+                    BSTRINSz(gd, ed, 15, 0);
+                }
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, &lock, 1, 0);
+                SMREADLOCK(lock);
+                LD_HU(x1, ed, fixedaddress);
+                BSTRINSz(gd, x1, 15, 0);
+            }
+            break;
+        case 0x90:
+        case 0x91:
+        case 0x92:
+        case 0x93:
+        case 0x94:
+        case 0x95:
+        case 0x96:
+        case 0x97:
+            gd = TO_NAT((opcode & 0x07) + (rex.b << 3));
+            if (gd == xRAX) {
+                INST_NAME("NOP");
+            } else {
+                INST_NAME("XCHG AX, Reg");
+                MV(x2, xRAX);
+                BSTRINSz(xRAX, gd, 15, 0);
+                BSTRINSz(gd, x2, 15, 0);
+            }
+            break;
+        case 0xA4:
+            if (rep) {
+                INST_NAME("REP MOVSB");
+                CBZ_NEXT(xRCX);
+                ANDI(x1, xFlags, 1 << F_DF);
+                BNEZ_MARK2(x1);
+                MARK; // Part with DF==0
+                LD_BU(x1, xRSI, 0);
+                ST_B(x1, xRDI, 0);
+                ADDI_D(xRSI, xRSI, 1);
+                ADDI_D(xRDI, xRDI, 1);
+                ADDI_D(xRCX, xRCX, -1);
+                BNEZ_MARK(xRCX);
+                B_NEXT_nocond;
+                MARK2; // Part with DF==1
+                LD_BU(x1, xRSI, 0);
+                ST_B(x1, xRDI, 0);
+                ADDI_D(xRSI, xRSI, -1);
+                ADDI_D(xRDI, xRDI, -1);
+                ADDI_D(xRCX, xRCX, -1);
+                BNEZ_MARK2(xRCX);
+                // done
+            } else {
+                INST_NAME("MOVSB");
+                GETDIR(x3, x1, 1);
+                LD_BU(x1, xRSI, 0);
+                ST_B(x1, xRDI, 0);
+                ADD_D(xRSI, xRSI, x3);
+                ADD_D(xRDI, xRDI, x3);
+            }
+            break;
+        case 0xA5:
+            if (rep) {
+                INST_NAME("REP MOVSW");
+                CBZ_NEXT(xRCX);
+                ANDI(x1, xFlags, 1 << F_DF);
+                BNEZ_MARK2(x1);
+                MARK; // Part with DF==0
+                LD_H(x1, xRSI, 0);
+                ST_H(x1, xRDI, 0);
+                ADDI_D(xRSI, xRSI, 2);
+                ADDI_D(xRDI, xRDI, 2);
+                ADDI_D(xRCX, xRCX, -1);
+                BNEZ_MARK(xRCX);
+                B_NEXT_nocond;
+                MARK2; // Part with DF==1
+                LD_H(x1, xRSI, 0);
+                ST_H(x1, xRDI, 0);
+                ADDI_D(xRSI, xRSI, -2);
+                ADDI_D(xRDI, xRDI, -2);
+                ADDI_D(xRCX, xRCX, -1);
+                BNEZ_MARK2(xRCX);
+                // done
+            } else {
+                INST_NAME("MOVSW");
+                GETDIR(x3, x1, 2);
+                LD_H(x1, xRSI, 0);
+                ST_H(x1, xRDI, 0);
+                ADD_D(xRSI, xRSI, x3);
+                ADD_D(xRDI, xRDI, x3);
+            }
+            break;
+        case 0xA9:
+            INST_NAME("TEST AX,Iw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            u16 = F16;
+            MOV32w(x2, u16);
+            BSTRPICK_D(x1, xRAX, 15, 0);
+            emit_test16(dyn, ninst, x1, x2, x3, x4, x5);
+            break;
+        case 0xAB:
+            if (rep) {
+                INST_NAME("REP STOSW");
+                CBZ_NEXT(xRCX);
+                ANDI(x1, xFlags, 1 << F_DF);
+                BNEZ_MARK2(x1);
+                MARK; // Part with DF==0
+                ST_H(xRAX, xRDI, 0);
+                ADDI_D(xRDI, xRDI, 2);
+                ADDI_D(xRCX, xRCX, -1);
+                BNEZ_MARK(xRCX);
+                B_NEXT_nocond;
+                MARK2; // Part with DF==1
+                ST_H(xRAX, xRDI, 0);
+                ADDI_D(xRDI, xRDI, -2);
+                ADDI_D(xRCX, xRCX, -1);
+                BNEZ_MARK2(xRCX);
+                // done
+            } else {
+                INST_NAME("STOSW");
+                GETDIR(x3, x1, 2);
+                ST_H(xRAX, xRDI, 0);
+                ADD_D(xRDI, xRDI, x3);
+            }
+            break;
+        case 0xB8:
+        case 0xB9:
+        case 0xBA:
+        case 0xBB:
+        case 0xBC:
+        case 0xBD:
+        case 0xBE:
+        case 0xBF:
+            INST_NAME("MOV Reg16, Iw");
+            u16 = F16;
+            MOV32w(x1, u16);
+            gd = TO_NAT((opcode & 7) + (rex.b << 3));
+            BSTRINSz(gd, x1, 15, 0);
+            break;
+        case 0xC1:
+            nextop = F8;
+            switch ((nextop >> 3) & 7) {
+                case 0:
+                    INST_NAME("ROL Ew, Ib");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    SETFLAGS(X_OF | X_CF, SF_SET_DF);
+                    GETEW(x1, 1);
+                    u8 = F8;
+                    MOV32w(x2, u8);
+                    CALL_(rol16, x1, x3);
+                    EWBACK;
+                    break;
+                case 1:
+                    INST_NAME("ROR Ew, Ib");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    SETFLAGS(X_OF | X_CF, SF_SET_DF);
+                    GETEW(x1, 1);
+                    u8 = F8;
+                    MOV32w(x2, u8);
+                    CALL_(ror16, x1, x3);
+                    EWBACK;
+                    break;
+                case 4:
+                case 6:
+                    INST_NAME("SHL Ew, Ib");
+                    UFLAG_IF { MESSAGE(LOG_DUMP, "Need Optimization for flags\n"); }
+                    SETFLAGS(X_ALL, SF_PENDING);
+                    GETEW(x1, 1);
+                    u8 = F8;
+                    UFLAG_IF { MOV32w(x2, (u8 & 15)); }
+                    UFLAG_OP12(ed, x2)
+                    if (MODREG) {
+                        SLLI_D(ed, ed, 48 + (u8 & 15));
+                        SRLI_D(ed, ed, 48);
+                    } else {
+                        SLLI_D(ed, ed, u8 & 15);
+                    }
+                    EWBACK;
+                    UFLAG_RES(ed);
+                    UFLAG_DF(x3, d_shl16);
+                    break;
+                case 5:
+                    INST_NAME("SHR Ew, Ib");
+                    UFLAG_IF { MESSAGE(LOG_DUMP, "Need Optimization for flags\n"); }
+                    SETFLAGS(X_ALL, SF_PENDING);
+                    GETEW(x1, 1);
+                    u8 = F8;
+                    UFLAG_IF { MOV32w(x2, (u8 & 15)); }
+                    UFLAG_OP12(ed, x2)
+                    SRLI_D(ed, ed, u8 & 15);
+                    EWBACK;
+                    UFLAG_RES(ed);
+                    UFLAG_DF(x3, d_shr16);
+                    break;
+                case 7:
+                    INST_NAME("SAR Ew, Ib");
+                    SETFLAGS(X_ALL, SF_PENDING);
+                    UFLAG_IF { MESSAGE(LOG_DUMP, "Need Optimization for flags\n"); }
+                    GETSEW(x1, 1);
+                    u8 = F8;
+                    UFLAG_IF { MOV32w(x2, (u8 & 15)); }
+                    UFLAG_OP12(ed, x2)
+                    SRAI_D(ed, ed, u8 & 15);
+                    if (MODREG) BSTRPICK_D(ed, ed, 15, 0);
+                    EWBACK;
+                    UFLAG_RES(ed);
+                    UFLAG_DF(x3, d_sar16);
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+        case 0xC7:
+            INST_NAME("MOV Ew, Iw");
+            nextop = F8;
+            if (MODREG) {
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                u16 = F16;
+                MOV32w(x1, u16);
+                BSTRINSz(ed, x1, 15, 0);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, &lock, 1, 2);
+                u16 = F16;
+                MOV32w(x1, u16);
+                ST_H(x1, ed, fixedaddress);
+                SMWRITELOCK(lock);
+            }
+            break;
+        case 0xD1:
+        case 0xD3:
+            nextop = F8;
+            switch ((nextop >> 3) & 7) {
+                case 5:
+                    if (opcode == 0xD1) {
+                        INST_NAME("SHR Ew, 1");
+                        MOV32w(x2, 1);
+                    } else {
+                        INST_NAME("SHR Ew, CL");
+                        ANDI(x2, xRCX, 0x1f);
+                        BEQ_NEXT(x2, xZR);
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING); // some flags are left undefined
+                    if (box64_dynarec_safeflags > 1) MAYSETFLAGS();
+                    GETEW(x1, 0);
+                    emit_shr16(dyn, ninst, x1, x2, x5, x4, x6);
+                    EWBACK;
+                    break;
+                case 4:
+                case 6:
+                    if (opcode == 0xD1) {
+                        INST_NAME("SHL Ew, 1");
+                        MOV32w(x2, 1);
+                    } else {
+                        INST_NAME("SHL Ew, CL");
+                        ANDI(x2, xRCX, 0x1f);
+                        BEQ_NEXT(x2, xZR);
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING); // some flags are left undefined
+                    if (box64_dynarec_safeflags > 1)
+                        MAYSETFLAGS();
+                    GETEW(x1, 0);
+                    emit_shl16(dyn, ninst, x1, x2, x5, x4, x6);
+                    EWBACK;
+                    break;
+                case 7:
+                    if (opcode == 0xD1) {
+                        INST_NAME("SAR Ew, 1");
+                        MOV32w(x2, 1);
+                    } else {
+                        INST_NAME("SAR Ew, CL");
+                        ANDI(x2, xRCX, 0x1f);
+                        BEQ_NEXT(x2, xZR);
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING); // some flags are left undefined
+                    if (box64_dynarec_safeflags > 1)
+                        MAYSETFLAGS();
+                    GETSEW(x1, 0);
+                    emit_sar16(dyn, ninst, x1, x2, x5, x4, x6);
+                    EWBACK;
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+        case 0xF7:
+            nextop = F8;
+            switch ((nextop >> 3) & 7) {
+                case 0:
+                case 1:
+                    INST_NAME("TEST Ew, Iw");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEW(x1, 2);
+                    u16 = F16;
+                    MOV32w(x2, u16);
+                    emit_test16(dyn, ninst, x1, x2, x3, x4, x5);
+                    break;
+                case 3:
+                    INST_NAME("NEG Ew");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEW(x1, 0);
+                    emit_neg16(dyn, ninst, ed, x2, x4);
+                    EWBACK;
+                    break;
+                case 6:
+                    INST_NAME("DIV Ew");
+                    SETFLAGS(X_ALL, SF_SET);
+                    SET_DFNONE();
+                    GETEW(x1, 0);
+                    BSTRPICK_D(x2, xRAX, 15, 0);
+                    SLLI_D(x7, xRDX, 48);
+                    SRLI_D(x7, x7, 32);
+                    OR(x2, x2, x7);
+                    if(box64_dynarec_div0) {
+                        BNE_MARK3(ed, xZR);
+                        GETIP_(ip);
+                        STORE_XEMU_CALL();
+                        CALL(native_div0, -1);
+                        CLEARIP();
+                        LOAD_XEMU_CALL();
+                        jump_to_epilog(dyn, 0, xRIP, ninst);
+                        MARK3;
+                    }
+                    DIV_WU(x7, x2, ed);
+                    MOD_WU(x4, x2, ed);
+                    BSTRINSz(xRAX, x7, 15, 0);
+                    BSTRINSz(xRDX, x4, 15, 0);
+                    break;
+                case 7:
+                    INST_NAME("IDIV Ew");
+                    NOTEST(x1);
+                    SETFLAGS(X_ALL, SF_SET);
+                    SET_DFNONE();
+                    GETSEW(x1, 0);
+                    if (box64_dynarec_div0) {
+                        BNE_MARK3(ed, xZR);
+                        GETIP_(ip);
+                        STORE_XEMU_CALL();
+                        CALL(native_div0, -1);
+                        CLEARIP();
+                        LOAD_XEMU_CALL();
+                        jump_to_epilog(dyn, 0, xRIP, ninst);
+                        MARK3;
+                    }
+                    BSTRPICK_D(x2, xRAX, 15, 0);
+                    SLLI_D(x3, xRDX, 16);
+                    OR(x2, x2, x3);
+                    DIV_W(x3, x2, ed);
+                    MOD_W(x4, x2, ed);
+                    BSTRINSz(xRAX, x3, 15, 0);
+                    BSTRINSz(xRDX, x4, 15, 0);
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+        case 0xFF:
+            nextop = F8;
+            switch ((nextop >> 3) & 7) {
+                case 0:
+                    INST_NAME("INC Ew");
+                    SETFLAGS(X_ALL & ~X_CF, SF_SUBSET_PENDING);
+                    GETEW(x1, 0);
+                    emit_inc16(dyn, ninst, x1, x2, x4, x5);
+                    EWBACK;
+                    break;
+                case 1:
+                    INST_NAME("DEC Ew");
+                    SETFLAGS(X_ALL & ~X_CF, SF_SUBSET_PENDING);
+                    GETEW(x1, 0);
+                    emit_dec16(dyn, ninst, x1, x2, x4, x5, x6);
+                    EWBACK;
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
@@ -0,0 +1,71 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "la64_emitter.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "la64_printer.h"
+#include "dynarec_la64_private.h"
+#include "../dynarec_helper.h"
+#include "dynarec_la64_functions.h"
+
+uintptr_t dynarec64_6664(dynarec_la64_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int seg, int* ok, int* need_epilog)
+{
+    (void)ip;
+    (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop;
+    uint8_t gd, ed;
+    int64_t j64;
+    int v0, v1;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(j64);
+
+    GETREX();
+
+    switch (opcode) {
+        case 0x8B:
+            INST_NAME("MOV Gd, FS:Ed");
+            nextop = F8;
+            GETGD;
+            if (MODREG) { // reg <= reg
+                ed = TO_NAT((nextop & 7) + (rex.b << 3));
+                if (rex.w) {
+                    MV(gd, ed);
+                } else {
+                    if (ed != gd) BSTRINS_D(gd, ed, 15, 0);
+                }
+            } else { // mem <= reg
+                grab_segdata(dyn, addr, ninst, x4, seg);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, x1, &fixedaddress, rex, NULL, 1, 0);
+                ADDz(x4, ed, x4);
+                if (rex.w) {
+                    LD_D(gd, x4, fixedaddress);
+                } else {
+                    LD_HU(x1, x4, fixedaddress);
+                    BSTRINS_D(gd, x1, 15, 0);
+                }
+            }
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}