Bumped to v0.2.0

Merge pull request #309 from heavygabriel/master
Simplified code
2026-11-08 10:10:14 -10:00 · 2021-01-12 19:44:14 +01:00 · 2021-01-11 19:43:05 +01:00 · 2021-01-11 11:45:54 -05:00 · 2021-01-11 11:39:04 -05:00 · 2021-01-11 10:21:01 -05:00
361 changed files with 72359 additions and 17398 deletions
@@ -0,0 +1,12 @@
+# These are supported funding model platforms
+
+github: # Replace with up to 4 GitHub Sponsors-enabled usernames e.g., [user1, user2]
+patreon: # Replace with a single Patreon username
+open_collective: # Replace with a single Open Collective username
+ko_fi: # Replace with a single Ko-fi username
+tidelift: # Replace with a single Tidelift platform-name/package-name e.g., npm/babel
+community_bridge: # Replace with a single Community Bridge project-name e.g., cloud-foundry
+liberapay: # Replace with a single Liberapay username
+issuehunt: # Replace with a single IssueHunt username
+otechie: # Replace with a single Otechie username
+custom: paypal.me/0ptitSeb
@@ -1,4 +1,6 @@
-build
-build*
+build/
+build*/
 .vscode
 .gdb_history
+src/git_head.h
+backup/
@@ -1,3 +1,81 @@
+v0.2.0
+======
+* Improvoment on x86 Flags handling
+* A few more opcode added
+* A few potential BusError fixed
+* Added BOX86_NOVULKAN en. var. disable the wrapping of vulkan libs
+* Improvments on libc O_XXXX flags handling
+* Now use a custom allocator for Dynarec and Hash tables
+* Improvment wrapping of pulse audio
+* Optimisation to a few Dynarec opcode (like SHRD/SHLD)
+* Improved the tracking of memory protection
+* A few more wrapping of libs (like libgssapi_krb5)
+* More function wrapping on libturbojpeg
+* Preliminary support for POWER9 (ppcle) build
+* Many contributed typo and rephrasing of README, COMPILE and USAGE docs
+
+v0.1.8
+======
+* Fixes on some float to int x87 convertions opcodes
+* Reworked all callback mecanisms
+* Added libturbojpeg wrapping (and a hack for zoom to force using native one)
+* Added BOX86_SAFEMMAP env. var.
+* Reworked dynarec memory manager
+* Added a few opcodes
+* Improve elfloader to not force PltResolver all the time (fixing SuperHexagon and maybe other)
+* Reworked Exet and Cancel Thread mecanism
+* Added wrapped libldap_r and liblber library (used by wine)
+* Reworked Dynarec block handling, and remove the "AddMark" mecanism that wasn't efficient enough
+* Added TokiTori 2+ detection and runtime patch on PI
+* Fixes on elfloader with TLS object
+
+v0.1.6
+======
+* Changes in Dynarec to make flags optimizations before CALL and RET opcode less aggressive
+* Added Vulkan wrapper
+* Improved wrapping of SDL_mixer/ SDL2_mixer lib
+* Improved wrapping of some gtk structures
+* Added a quick and dirty wrapping of Gtk3 (based on current gtk2)
+* Improved the signal handling, should be more stable now (the signal handler from syscall still need some works)
+* Added RK3399 profile, and some hints to build the 32bits box86 on 64bits OS
+* Fixed some wrapped printf formating not handled correctly
+* Fixed some buserror with the new LOCK mecanism handling
+* A few more Dynarec opcodes added
+* If winedbg is tried to be launched, exit without launching it (it doesn't work anyway)
+
+v0.1.4
+======
+* Change in Dynarec memory handling, to simplify it (and hopefully optimized it)
+* Even more opcodes added.
+* And some more Dynarec opcodes.
+* Fixed some issue were PltResolver was injected but should not
+* Fixed many Dynarec and non dynarec opcodes
+* Improved Signal handling
+* Added a few more wrapped lib (like curl)
+* Gallium9 is wrapped (thx @icecream95)
+* Fixed and simplied many wrapped functions (especialy the one were a callback is involved)
+* Fixed Dynarec "freeing" a Dynablock somthime corrupting the heap (happens in case of JIT mainly)
+* Optimized the way LOCK prefix work when using Dynarec on ARM
+* Printer of ARM opcode (for dumping Dynarec blocks) improvement (thx @rajdakin)
+
+v0.1.2
+======
+* The Dynarec now handle JIT code
+* Added support for Unity games (not perfect yet)
+* Added support for Wine (not perfect yet). You need an x86 build of Wine to use it
+* Added support for Steam (not perfect yet). Note that steam have limited functionnalities on 32bits (only mini-mode is available)
+* More wrapped libs
+* Added support for "PltResolver", so order of library is less important and many symbol are resolved at runtime
+* Added an option to build box86 as a lib (to wrapped dynamic library)
+* Better Signal handling (not perfect yet)
+* More opcodes added, more opcode fixes.
+* More Dynarec opcodes.
+* Added support for FS:, and creating custom selector (needed by Wine)
+* There is now 1 x86emu_t structure per thread (simplifying/optimising many callback handling)
+* Box86 now have a logo!
+* Added options handling (only version and help for now). Now it's much usefull exept for version printing.
+
+
 v0.1.0
 =======
 * Dynarec!!! Only for ARM (note that dynarec doesn't support JITed code for now)
@@ -1,83 +1,131 @@
-cmake_minimum_required(VERSION 2.6)
-
-project(box86)
-
-enable_testing()
-enable_language(C)
+cmake_minimum_required(VERSION 3.0)

 option(PANDORA "Set to ON if targeting an OpenPandora device" ${PANDORA})
 option(PYRA "Set to ON if targeting an OpenPandora device" ${PYRA})
 option(RPI2 "Set to ON if targeting an RaspberryPI2 device" ${RPI2})
 option(RPI3 "Set to ON if targeting an RaspberryPI3 device" ${RPI3})
 option(RPI4 "Set to ON if targeting an RaspberryPI4 device" ${RPI4})
-option(GAMESHELL "Set to ON if targeting a Gameshell device" ${GAMESHELL})
+option(RPI4ARM64 "Set to ON if targeting an RaspberryPI4 device with multiarch arm64 and armhf" ${RPI4ARM64})
+option(RK3399 "Set to ON if targeting an Rockchip RK3399 based device" ${RK3399})
+option(GAMESHELL "Set to ON if targeting a GameShell device" ${GAMESHELL})
+option(ODROID "Set to ON if targeting an ODroid device" ${ODROID})
+option(POWER9 "Set to ON if targeting a POWER9 processor" ${POWER9})
 option(USE_CCACHE "Set to ON to use ccache if present in the system" ${USE_CCACHE})
+option(HAVE_TRACE "Set to ON to have Trace ability (needs ZydisInfo library)" ${HAVE_TRACE})
+option(NOLOADADDR "Set to ON to avoid fixing the load address of Box86" ${NO_LOADAADR})
+option(NOGETCLOCK "Set to ON to avoid using clock_gettime with CLOCK_MONOTONIC_COARSE for RDTSC opcode (use gltimeofday instead)" ${NOGETCLOCK})
+option(NOGIT "Set to ON if not building from a git clone repo (like when building from a zip download from github)" ${NOGIT})
+if(PANDORA OR PYRA OR RPI2 OR RPI3 OR RPI4 OR GAMESHELL OR ODROID OR RK3399 OR RPI4ARM64)
+    set(LD80BITS OFF CACHE BOOL "")
+    set(NOALIGN OFF CACHE BOOL "")
+    set(ARM_DYNAREC ON CACHE BOOL "")
+endif()
 option(LD80BITS "Set to ON if host device have 80bits long double (i.e. i386)" ${LD80BITS})
 option(NOALIGN "Set to ON if host device doesn't need re-align (i.e. i386)" ${NOALIGN})
-option(HAVE_TRACE "Set to ON to have Trace ability (needs ZydisInfo library)" ${HAVE_TRACE})
-option(USE_FLOAT "Set to ON to use only float, no double, in all x87 Emulation" ${USE_FLOAT})
-option(NOLOADADDR "Set to ON to avoid fixing the load address of Box86" ${NO_LOADAADR})
 option(ARM_DYNAREC "Set to ON to use ARM Dynamic Recompilation (WIP, don't use yet)" ${ARM_DYNAREC})
-option(NOGETCLOCK "Set to ON to avoid using clock_gettime with CLOCK_MONOTONIC_COARSE for RDTSC opcode (use gltimeofday instead)" ${NOGETCLOCK})
+option(POWERPCLE "Set to ON if targeting a little-endian PowerPC device" ${POWERPCLE})
+option(SYSV_VARARG "Set to ON if host device uses SysVR4 vararg calling convention" ${SYSV_VARARG})

-find_package(PythonInterp)
-if(NOT PYTHONINTERP_FOUND)
-    message( FATAL_ERROR "You need a Python interpretor, CMake will exit." )
+if(${CMAKE_VERSION} VERSION_LESS "3.12.2")
+    find_package(PythonInterp 3)
+    if(NOT PYTHONINTERP_FOUND)
+        message( FATAL_ERROR "You need a Python interpretor, CMake will exit." )
+    endif()
+    if(${PYTHON_VERSION_MAJOR} LESS 3)
+        message( FATAL_ERROR "You need a Python 3 interpretor, CMake will exit." )
+    endif()
+else()
+    find_package(Python3)
+    if(NOT Python3_Interpreter_FOUND)
+        message( FATAL_ERROR "You need a Python interpretor, CMake will exit." )
+    endif()
+    set(PYTHON_EXECUTABLE ${Python3_EXECUTABLE} CACHE INTERNAL "The Python3 executable" FORCE)
+endif()
+
+if(RK3399 OR RPI4ARM64)
+    set(CMAKE_C_COMPILER arm-linux-gnueabihf-gcc)
+    #set(CMAKE_ASM_COMPILER arm-linux-gnueabihf-as) #will use gcc in fact
+    set(CMAKE_C_COMPILER_TARGET arm-linux-gnueabihf)
+endif()
+
+project(box86 C ASM)
+
+enable_testing()
+
+set(default_build_type "RelwithDebInfo")
+if(NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES)
+  message(STATUS "Setting build type to '${default_build_type}' as none was specified.")
+  set(CMAKE_BUILD_TYPE "${default_build_type}" CACHE STRING "Choose the type of build." FORCE)
+  set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS "Debug" "Release" "MinSizeRel" "RelWithDebInfo")
 endif()

-# Pandora
 if(PANDORA)
    add_definitions(-DPANDORA)
    #add_definitions(-mcpu=cortex-a8 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize -fsingle-precision-constant -ffast-math)
-    set(ARM_DYNAREC ON)
-    set(LD80BITS OFF)
-    set(NOALIGN OFF)
 endif()
-
-# Gameshell
 if(GAMESHELL)
+    add_definitions(-DGAMEHELL)
    add_definitions(-marm -mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard)
    set(CMAKE_ASM_FLAGS  "-marm -mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard")
-    set(ARM_DYNAREC ON)
-    set(LD80BITS OFF)
-    set(NOALIGN OFF)
 endif()
-
 if(PYRA)
+    add_definitions(-DPYRA)
    add_definitions(-mcpu=cortex-a15 -mfpu=neon -mfloat-abi=hard -marm)
    set(CMAKE_ASM_FLAGS  "-marm -mcpu=cortex-a15 -mfpu=neon -mfloat-abi=hard")
-    set(ARM_DYNAREC ON)
-    set(LD80BITS OFF)
-    set(NOALIGN OFF)
 endif()
-
 if(RPI2)
    add_definitions(-DRPI)
    add_definitions(-DRPI2)
    add_definitions(-marm -mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard)
    set(CMAKE_ASM_FLAGS  "-marm -mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard")
-    set(ARM_DYNAREC ON)
-    set(LD80BITS OFF)
-    set(NOALIGN OFF)
 endif()
 if(RPI3)
    add_definitions(-DRPI)
    add_definitions(-DRPI3)
    add_definitions(-marm -march=armv8-a+crc -mtune=cortex-a53 -mfpu=neon-fp-armv8 -mfloat-abi=hard)
    set(CMAKE_ASM_FLAGS  "-marm -march=armv8-a+crc -mtune=cortex-a53 -mfpu=neon-fp-armv8 -mfloat-abi=hard")
-    set(ARM_DYNAREC ON)
-    set(LD80BITS OFF)
-    set(NOALIGN OFF)
 endif()
 if(RPI4)
    add_definitions(-DRPI)
-    add_definitions(-DRPI3)
+    add_definitions(-DRPI4)
    add_definitions(-marm -march=armv8-a+crc -mtune=cortex-a72 -mfpu=neon-fp-armv8 -mfloat-abi=hard)
    set(CMAKE_ASM_FLAGS  "-marm -march=armv8-a+crc -mtune=cortex-a72 -mfpu=neon-fp-armv8 -mfloat-abi=hard")
-    set(ARM_DYNAREC ON)
-    set(LD80BITS OFF)
-    set(NOALIGN OFF)
 endif()
+if(RPI4ARM64)
+    add_definitions(-DRPI)
+    add_definitions(-DRPI4ARM64)
+    add_definitions(-marm -march=armv8-a+crc -mtune=cortex-a72 -mfpu=neon-fp-armv8 -mfloat-abi=hard)
+    set(CMAKE_ASM_FLAGS  "-marm -march=armv8-a+crc -mtune=cortex-a72 -mfpu=neon-fp-armv8 -mfloat-abi=hard")
+endif()
+if(ODROID)
+    add_definitions(-DODROID)
+    add_definitions(-mcpu=cortex-a9 -mfpu=neon-vfpv4 -mfloat-abi=hard -marm)
+    set(CMAKE_ASM_FLAGS  "-marm -mcpu=cortex-a9 -mfpu=neon-vfpv4 -mfloat-abi=hard")
+endif()
+if(RK3399)
+    add_definitions(-DRK3399)
+    add_definitions(-pipe -march=armv8-a+crc+simd+crypto -mcpu=cortex-a72+crypto)
+    set(CMAKE_ASM_FLAGS  "-pipe -march=armv8-a+crc+simd+crypto -mcpu=cortex-a72+crypto")
+endif()
+
+if(POWER9)
+  add_definitions(-mcpu=power9 -mtune=power9)
+endif()
+
+if(NOGIT)
+    add_definitions(-DNOGIT)
+endif()
+
+if(BOX86LIB)
+    set(BOX86 box86)
+elseif(HAVE_TRACE)
+    set(BOX86 box86t)
+else()
+    set(BOX86 box86)
+endif()
+
+
+set(BOX86_ELF_ADDRESS "0x62800000")

 if(LD80BITS)
    add_definitions(-DHAVE_LD80BITS)
@@ -91,10 +139,6 @@ if(HAVE_TRACE)
    add_definitions(-DHAVE_TRACE)
 endif()

-if(USE_FLOAT)
-    add_definitions(-DUSE_FLOAT)
-endif()
-
 if(ARM_DYNAREC)
    add_definitions(-DDYNAREC)
    add_definitions(-DARM)
@@ -102,22 +146,33 @@ if(ARM_DYNAREC)
    enable_language(ASM)
 endif()

+if(POWERPCLE)
+  add_definitions(-DPOWERPCLE)
+endif()
+
+if(SYSV_VARARG)
+  add_definitions(-DSYSV_VARARG)
+endif()
+
 if(NOGETCLOCK)
    add_definitions(-DNOGETCLOCK)
 endif()

 if(BOX86LIB)
    add_definitions(-DBUILD_LIB)
+    if(BOX86DYNAMIC)
+        add_definitions(-DBUILD_DYNAMIC)
+    endif()
    add_definitions(-fPIC)
    if(NOT BOX86_ROOT)
        message(FATAL_ERROR "BOX86_ROOT not set when build as lib")
    endif()
 else()
-    set(BOX86_ROOT ${CMAKE_HOME_DIRECTORY})
+    set(BOX86_ROOT ${CMAKE_SOURCE_DIR})
 endif()


-add_definitions(-g -std=gnu99 -funwind-tables -O3 -fvisibility=hidden)
+add_definitions(-std=gnu11 -funwind-tables -fvisibility=hidden)

 if(USE_CCACHE)
    find_program(CCACHE_FOUND ccache)
@@ -133,15 +188,25 @@ include_directories(
    "${BOX86_ROOT}/src/wrapped/generated"
 )

+# git_head.h is a generated file
+set_source_files_properties(
+    "${BOX86_ROOT}/src/git_head.h"
+    PROPERTIES GENERATED TRUE
+    HEADER_FILE_ONLY TRUE)
+
 set(ELFLOADER_SRC
    "${BOX86_ROOT}/src/main.c"
    "${BOX86_ROOT}/src/box86context.c"
+    "${BOX86_ROOT}/src/build_info.c"
+    "${BOX86_ROOT}/src/custommem.c"
    "${BOX86_ROOT}/src/tools/bridge.c"
    "${BOX86_ROOT}/src/tools/pathcoll.c"
    "${BOX86_ROOT}/src/tools/fileutils.c"
    "${BOX86_ROOT}/src/tools/callback.c"
    "${BOX86_ROOT}/src/tools/box86stack.c"
+    "${BOX86_ROOT}/src/tools/my_cpuid.c"
    "${BOX86_ROOT}/src/tools/gtkclass.c"
+    "${BOX86_ROOT}/src/tools/wine_tools.c"
    "${BOX86_ROOT}/src/elfs/elfloader.c"
    "${BOX86_ROOT}/src/elfs/elfparser.c"
    "${BOX86_ROOT}/src/elfs/elfload_dump.c"
@@ -150,19 +215,25 @@ set(ELFLOADER_SRC
    "${BOX86_ROOT}/src/emu/x86emu.c"
    "${BOX86_ROOT}/src/emu/x86run.c"
    "${BOX86_ROOT}/src/emu/x86run66.c"
+    "${BOX86_ROOT}/src/emu/x86run660f.c"
    "${BOX86_ROOT}/src/emu/x86run_private.c"
    "${BOX86_ROOT}/src/emu/x86syscall.c"
    "${BOX86_ROOT}/src/emu/x86primop.c"
    "${BOX86_ROOT}/src/emu/x86trace.c"
    "${BOX86_ROOT}/src/emu/x86int3.c"
+    "${BOX86_ROOT}/src/emu/x86tls.c"
    "${BOX86_ROOT}/src/emu/x87emu_private.c"
    "${BOX86_ROOT}/src/emu/x87run.c"
+    "${BOX86_ROOT}/src/libtools/auxval.c"
    "${BOX86_ROOT}/src/libtools/myalign.c"
+    "${BOX86_ROOT}/src/libtools/myalign64.c"
    "${BOX86_ROOT}/src/libtools/myfts.c"
+    "${BOX86_ROOT}/src/libtools/obstack.c"
    "${BOX86_ROOT}/src/libtools/sdl1rwops.c"
    "${BOX86_ROOT}/src/libtools/sdl2rwops.c"
    "${BOX86_ROOT}/src/libtools/signals.c"
    "${BOX86_ROOT}/src/libtools/threads.c"
+    "${BOX86_ROOT}/src/libtools/vkalign.c"
    "${BOX86_ROOT}/src/dynarec/dynarec.c"
    "${BOX86_ROOT}/src/wrapped/generated/wrapper.c"
 )
@@ -184,6 +255,7 @@ set(WRAPPEDS
    "${BOX86_ROOT}/src/wrapped/wrappedsdl2.c"
    "${BOX86_ROOT}/src/wrapped/wrappedsdl2mixer.c"
    "${BOX86_ROOT}/src/wrapped/wrappedsdl2image.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedsdl2ttf.c"
    "${BOX86_ROOT}/src/wrapped/wrappedsmpeg.c"
    "${BOX86_ROOT}/src/wrapped/wrappedsmpeg2.c"
    "${BOX86_ROOT}/src/wrapped/wrappedvorbisfile.c"
@@ -205,16 +277,33 @@ set(WRAPPEDS
    "${BOX86_ROOT}/src/wrapped/wrappedlibxdmcp.c"
    "${BOX86_ROOT}/src/wrapped/wrappedlibx11xcb.c"
    "${BOX86_ROOT}/src/wrapped/wrappedlibxcb.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxcbxfixes.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxcbshape.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxcbshm.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxcbrandr.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxcbimage.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxcbkeysyms.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxcbxtest.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxcbdri2.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxcbdri3.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxcbpresent.c"
    "${BOX86_ROOT}/src/wrapped/wrappedlibxtst.c"
    "${BOX86_ROOT}/src/wrapped/wrappedlibxt.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxcomposite.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxdamage.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibxmu.c"
    "${BOX86_ROOT}/src/wrapped/wrappedlibz.c"
    "${BOX86_ROOT}/src/wrapped/wrappedopenal.c"
    "${BOX86_ROOT}/src/wrapped/wrappedalut.c"
    "${BOX86_ROOT}/src/wrapped/wrappedlibjpeg.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibjpeg62.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedturbojpeg.c"
    "${BOX86_ROOT}/src/wrapped/wrappedcurl.c"
    "${BOX86_ROOT}/src/wrapped/wrappedudev0.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedudev1.c"
    "${BOX86_ROOT}/src/wrapped/wrappeddbus.c"
    "${BOX86_ROOT}/src/wrapped/wrappediconv.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibdrm.c"
    "${BOX86_ROOT}/src/wrapped/wrappedcrypto.c"
    "${BOX86_ROOT}/src/wrapped/wrappedlibssl.c"
    "${BOX86_ROOT}/src/wrapped/wrappedutil.c"
@@ -231,9 +320,14 @@ set(WRAPPEDS
    "${BOX86_ROOT}/src/wrapped/wrappedlibusb1.c"
    "${BOX86_ROOT}/src/wrapped/wrappedlibncursesw.c"
    "${BOX86_ROOT}/src/wrapped/wrappedlibformw.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibncurses.c"
    "${BOX86_ROOT}/src/wrapped/wrappedlibtinfo.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibncurses6.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibtinfo6.c"
    "${BOX86_ROOT}/src/wrapped/wrappedgtkx112.c"
    "${BOX86_ROOT}/src/wrapped/wrappedgdkx112.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedgtk3.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedgdk3.c"
    "${BOX86_ROOT}/src/wrapped/wrappedgdkpixbuf2.c"
    "${BOX86_ROOT}/src/wrapped/wrappedgio2.c"
    "${BOX86_ROOT}/src/wrapped/wrappedgmodule2.c"
@@ -242,6 +336,8 @@ set(WRAPPEDS
    "${BOX86_ROOT}/src/wrapped/wrappedgstreamer010.c"
    "${BOX86_ROOT}/src/wrapped/wrappedgstinterfaces010.c"
    "${BOX86_ROOT}/src/wrapped/wrappeddbusmenugtk.c"
+    "${BOX86_ROOT}/src/wrapped/wrappeddbusmenuglib.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedappindicator.c"
    "${BOX86_ROOT}/src/wrapped/wrappedatk.c"
    "${BOX86_ROOT}/src/wrapped/wrappedpangoft2.c"
    "${BOX86_ROOT}/src/wrapped/wrappedpangocairo.c"
@@ -250,19 +346,55 @@ set(WRAPPEDS
    "${BOX86_ROOT}/src/wrapped/wrappedpango.c"
    "${BOX86_ROOT}/src/wrapped/wrappeddbusglib1.c"
    "${BOX86_ROOT}/src/wrapped/wrappedgudev1.c"
-#    "${BOX86_ROOT}/src/wrapped/wrappedmonounity.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibnm.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedtcmallocminimal.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedmpg123.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedgnutls.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlibcups.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedd3dadapter9.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedvulkan.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedwaylandclient.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedxml2.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedxslt.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedldapr.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlber.c"
+    "${BOX86_ROOT}/src/wrapped/wrappednsl.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedlcms2.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedkrb5.c"
+    "${BOX86_ROOT}/src/wrapped/wrappedgssapikrb5.c"
    "${BOX86_ROOT}/src/wrapped/wrappedldlinux.c"
 )

-set(WRAPPEDS_HEAD "")
+set(WRAPPEDS_HEAD "${BOX86_ROOT}/src/wrapped/wrappedd3dadapter9_gen.h")
 foreach(A ${WRAPPEDS})
    string(REPLACE ".c" "_private.h" B ${A})
    set(WRAPPEDS_HEAD ${WRAPPEDS_HEAD} ${B})
+    set_source_files_properties(${A} PROPERTIES OBJECT_DEPENDS ${B})
 endforeach()

 set(WRAPPER "${BOX86_ROOT}/src/wrapped/generated/wrapper.c" "${BOX86_ROOT}/src/wrapped/generated/wrapper.h")

-add_custom_command(OUTPUT ${WRAPPER} COMMAND "${PYTHON_EXECUTABLE}" "${BOX86_ROOT}/rebuild_wrappers.py" "${BOX86_ROOT}" "PANDORA" "HAVE_LD80BITS" "NOALIGN" "HAVE_TRACE" "USE_FLOAT" MAIN_DEPENDENCY "${BOX86_ROOT}/rebuild_wrappers.py" DEPENDS ${WRAPPEDS} ${WRAPPEDS_HEAD})
+add_custom_command(
+    OUTPUT "${BOX86_ROOT}/src/wrapped/generated/functions_list.txt"
+    COMMAND "${PYTHON_EXECUTABLE}" "${BOX86_ROOT}/rebuild_wrappers.py" 
+    "${BOX86_ROOT}" 
+    "PANDORA" "HAVE_LD80BITS" "NOALIGN" "HAVE_TRACE" "POWERPCLE" "--" 
+    ${WRAPPEDS_HEAD}
+    MAIN_DEPENDENCY "${BOX86_ROOT}/rebuild_wrappers.py"
+    DEPENDS ${WRAPPEDS} ${WRAPPEDS_HEAD}
+    BYPRODUCTS ${WRAPPER}
+)
+
+add_custom_command(
+    OUTPUT "${BOX86_ROOT}/src/dynarec/last_run.txt"
+    COMMAND "${PYTHON_EXECUTABLE}" "${BOX86_ROOT}/rebuild_printer.py" "${BOX86_ROOT}"
+    MAIN_DEPENDENCY "${BOX86_ROOT}/rebuild_printer.py"
+    DEPENDS "${BOX86_ROOT}/src/dynarec/arm_instructions.txt"
+    BYPRODUCTS "${BOX86_ROOT}/src/dynarec/arm_printer.c"
+)
+
+add_custom_target(WRAPPERS DEPENDS "${BOX86_ROOT}/src/wrapped/generated/functions_list.txt")
+add_custom_target(PRINTER DEPENDS "${BOX86_ROOT}/src/dynarec/last_run.txt")

 if(ARM_DYNAREC)
    set(DYNAREC_SRC
@@ -276,13 +408,19 @@ if(ARM_DYNAREC)
        "${BOX86_ROOT}/src/dynarec/arm_epilog.S"
        "${BOX86_ROOT}/src/dynarec/arm_linker.S"
        "${BOX86_ROOT}/src/dynarec/arm_table.S"
+        "${BOX86_ROOT}/src/dynarec/arm_lock_helper.S"
    )

    set(DYNAREC_PASS
    "${BOX86_ROOT}/src/dynarec/dynarec_arm_helper.c"
+    "${BOX86_ROOT}/src/dynarec/dynarec_arm_emit_tests.c"
+    "${BOX86_ROOT}/src/dynarec/dynarec_arm_emit_math.c"
+    "${BOX86_ROOT}/src/dynarec/dynarec_arm_emit_logic.c"
+    "${BOX86_ROOT}/src/dynarec/dynarec_arm_emit_shift.c"
    "${BOX86_ROOT}/src/dynarec/dynarec_arm_pass.c"
    "${BOX86_ROOT}/src/dynarec/dynarec_arm_00.c"
    "${BOX86_ROOT}/src/dynarec/dynarec_arm_0f.c"
+    "${BOX86_ROOT}/src/dynarec/dynarec_arm_64.c"
    "${BOX86_ROOT}/src/dynarec/dynarec_arm_65.c"
    "${BOX86_ROOT}/src/dynarec/dynarec_arm_66.c"
    "${BOX86_ROOT}/src/dynarec/dynarec_arm_67.c"
@@ -312,6 +450,10 @@ if(ARM_DYNAREC)
    set_target_properties(arm_pass2 PROPERTIES COMPILE_FLAGS "-DSTEP=2")
    add_library(arm_pass3 OBJECT ${DYNAREC_PASS})
    set_target_properties(arm_pass3 PROPERTIES COMPILE_FLAGS "-DSTEP=3")
+    add_dependencies(arm_pass0 WRAPPERS)
+    add_dependencies(arm_pass1 WRAPPERS)
+    add_dependencies(arm_pass2 WRAPPERS)
+    add_dependencies(arm_pass3 WRAPPERS)

    add_library(dynarec STATIC 
        $<TARGET_OBJECTS:dynarec_arm> 
@@ -320,30 +462,66 @@ if(ARM_DYNAREC)
        $<TARGET_OBJECTS:arm_pass2>
        $<TARGET_OBJECTS:arm_pass3>
    )
+
+endif()
+
+# creates git_head.h
+if(ARM_DYNAREC)
+    add_custom_command(
+        OUTPUT "${BOX86_ROOT}/src/git_head.h"
+        COMMAND bash -c "echo \\\#define GITREV \\\"$(git rev-parse --short HEAD)\\\">\"${BOX86_ROOT}/src/git_head.h\""
+        DEPENDS dynarec ${ELFLOADER_SRC} ${WRAPPEDS}
+        VERBATIM)
+else()
+    add_custom_command(
+        OUTPUT "${BOX86_ROOT}/src/git_head.h"
+        COMMAND bash -c "echo \\\#define GITREV \\\"$(git rev-parse --short HEAD)\\\">\"${BOX86_ROOT}/src/git_head.h\""
+        DEPENDS ${ELFLOADER_SRC} ${WRAPPEDS}
+        VERBATIM)
 endif()

 if(BOX86LIB)
-#build a static lib...
-add_library(box86 OBJECT ${ELFLOADER_SRC} ${WRAPPEDS})
+#build a static or dynamic lib...
+if(BOX86DYNAMIC)
+    add_library(box86 SHARED ${ELFLOADER_SRC} ${WRAPPEDS} "${BOX86_ROOT}/src/git_head.h")
+else()
+    add_library(${BOX86} OBJECT ${ELFLOADER_SRC} ${WRAPPEDS} "${BOX86_ROOT}/src/git_head.h")
+endif()
+if(ARM_DYNAREC)
+    target_link_libraries(${BOX86} dynarec m dl rt pthread)
+endif()
+if(${CMAKE_VERSION} VERSION_LESS "3.13")
+    set_target_properties(${BOX86} PROPERTIES LINK_FLAGS -rdynamic)
+else()
+    target_link_options(${BOX86} PUBLIC -rdynamic)
+endif()
+add_dependencies(${BOX86} WRAPPERS)
+add_dependencies(${BOX86} PRINTER)
+
+add_custom_target(buildinfo ${BOX86}
+    DEPENDS dynarec ${BOX86} )

 else(BOX86LIB)

-if(USE_FLOAT)
-    set(BOX86 box86f)
-elseif(HAVE_TRACE)
-    set(BOX86 box86t)
-else()
-    set(BOX86 box86)
-endif()
-
-add_executable(${BOX86} ${ELFLOADER_SRC} ${WRAPPEDS})
+add_executable(${BOX86} ${ELFLOADER_SRC} ${WRAPPEDS} "${BOX86_ROOT}/src/git_head.h")
+add_dependencies(${BOX86} WRAPPERS)
+add_dependencies(${BOX86} PRINTER)
 target_link_libraries(${BOX86} m dl rt pthread)
 if(ARM_DYNAREC)
    target_link_libraries(${BOX86} dynarec)
 endif()

-if(NOT NOLOADADDR)
-    target_link_libraries(${BOX86} -Wl,-Ttext-segment,0x03800000)
+if(${CMAKE_VERSION} VERSION_LESS "3.13")
+    if(NOT NOLOADADDR)
+        set_target_properties(${BOX86} PROPERTIES LINK_FLAGS "-rdynamic -Wl,-Ttext-segment,${BOX86_ELF_ADDRESS}")
+    else()
+        set_target_properties(${BOX86} PROPERTIES LINK_FLAGS -rdynamic)
+    endif()
+else()
+    target_link_options(${BOX86} PUBLIC -rdynamic)
+    if(NOT NOLOADADDR)
+        target_link_options(${BOX86} PUBLIC -Wl,-Ttext-segment,${BOX86_ELF_ADDRESS})
+    endif()
 endif()

 string(COMPARE EQUAL "${CMAKE_HOST_SYSTEM_PROCESSOR}" "i686"  _x86)
@@ -352,8 +530,10 @@ string(COMPARE EQUAL "${CMAKE_HOST_SYSTEM_PROCESSOR}" "x86_64"  _x86_64)
 if(NOT _x86 AND NOT _x86_64)
  install(TARGETS ${BOX86}
    RUNTIME DESTINATION bin)
-  install(FILES ${CMAKE_SOURCE_DIR}/system/box86.conf DESTINATION /etc/binfmt.d/)
+  configure_file(system/box86.conf.cmake system/box86.conf)
+  install(FILES ${CMAKE_BINARY_DIR}/system/box86.conf DESTINATION /etc/binfmt.d/)
  install(FILES ${CMAKE_SOURCE_DIR}/x86lib/libstdc++.so.6 DESTINATION /usr/lib/i386-linux-gnu/)
+  install(FILES ${CMAKE_SOURCE_DIR}/x86lib/libstdc++.so.5 DESTINATION /usr/lib/i386-linux-gnu/)
  install(FILES ${CMAKE_SOURCE_DIR}/x86lib/libgcc_s.so.1 DESTINATION /usr/lib/i386-linux-gnu/)
 endif()

@@ -432,7 +612,12 @@ add_test(test13 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX86}
    -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref13.txt
    -P ${CMAKE_SOURCE_DIR}/runTest.cmake )

-    file(GLOB extension_tests "${CMAKE_SOURCE_DIR}/tests/extensions/*.c")
+add_test(test14 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX86} 
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test14 -D TEST_OUTPUT=tmpfile.txt 
+    -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref14.txt
+    -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
+
+file(GLOB extension_tests "${CMAKE_SOURCE_DIR}/tests/extensions/*.c")
 foreach(file ${extension_tests})
    get_filename_component(testname "${file}" NAME_WE)
    add_test(NAME "${testname}" COMMAND ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX86}
@@ -2,31 +2,48 @@ Compiling
 ----
 #### for Pandora

- `mkdir build; cd build; cmake .. -DPANDORA=1; make`
+ `mkdir build; cd build; cmake .. -DPANDORA=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo; make`

 #### for Pyra

- `mkdir build; cd build; cmake .. -DPYRA=1; make`
+ `mkdir build; cd build; cmake .. -DPYRA=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo; make`

 #### for Gameshell

-`mkdir build; cd build; cmake .. -DGAMESHELL=1; make`
+`mkdir build; cd build; cmake .. -DGAMESHELL=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo; make`

 #### for RaspberryPI

  _a build for model 2, 3 and 4 can be done. Model 1 and 0 cannot (at least not with Dynarec, as they lack NEON support)_
 
-`mkdir build; cd build; cmake .. -DRPI4=1; make`
+```
+git clone https://github.com/ptitSeb/box86
+cd box86
+mkdir build; cd build; cmake .. -DRPI4=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+make -j4
+sudo make install
+sudo systemctl restart systemd-binfmt
+```
 
  _For Pi4. Change to RPI2 or RPI3 for other models._

-#### for Other ARM Linux
+#### for ODROID

- `mkdir build; cd build; cmake .. ; make`
+`mkdir build; cd build; cmake .. -DODROID=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo; make`
+
+#### for RK3399
+
+`mkdir build; cd build; cmake .. -DRK3399=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo; make -j4`
+
+As most RK3399 device run AARCH64 OS, you'll need an `armhf` multiarch environment, and an armhf gcc: On debian, install it with `sudo apt install gcc-arm-linux-gnueabihf`.
+
+#### for Other ARM Linux platforms
+
+ `mkdir build; cd build; cmake .. -DARM_DYNAREC=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo; make`

 #### for x86 Linux

- `mkdir build; cd build; cmake .. -DLD80BITS=1 -DNOALIGN=1; make`
+ `mkdir build; cd build; cmake .. -DLD80BITS=1 -DNOALIGN=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo; make`

 #### use ccmake

@@ -34,15 +51,25 @@ Alternatively, you can use the curses-bases ccmake (or any other gui frontend fo

 #### Customize your build

-*use ccache if you have it*
+*use ccache if you have it* 
+
 Add `-DUSE_CCACHE=1` if you have ccache (it's better if you plan to touch the sources)

+*have some debug info* 

-*to have a Trace Enabled build*
-To have a trace enabled build (warning, it will be slower), add `-DHAVE_TRACE=1` but you will need, at runtime, to have the [Zydis library](https://github.com/zyantific/zydis) library in your `LD_LIBRARY_PATH` or in the system lib folders.
+The `-DCMAKE_BUILD_TYPE=RelWithDebInfo` argument makes a build that is both optimized for speed, and has debug information embedded. That way, if you have a crash or try to analyse performance, you'll have some symbols.
+
+*to have a Trace Enabled build* 
+
+To have a trace enabled build ( ***it will be slower***), add `-DHAVE_TRACE=1` but you will need, at runtime, to have the [Zydis library](https://github.com/zyantific/zydis) library in your `LD_LIBRARY_PATH` or in the system library folders.

 *to have ARM Dynarec*
-The Dynarec is only avaiable on ARM Cpu. Notes also that VFPv3 and NEON are required for the Dynarec. Activate it by using `-DARM_DYNAREC=1`. Also, be sure to use `-marm` in compilation flags (because many compileur use Thumb as default, and the dynarec will not work in this mode).
+
+The Dynarec is only available on the ARM architecture(Right now, anyways.). Notes also that VFPv3 and NEON are required for the Dynarec. Activate it by using `-DARM_DYNAREC=1`. Also, be sure to use `-marm` in compilation flags (because many compileur use Thumb as default, and the dynarec will not work in this mode).
+
+*not building from a git clone*
+
+If you are not building from a git clone (for example, downloading a release source zipped from github), you need to activate `-DNOGIT=1` from cmake to be able to build (normal process include git sha1 of HEAD in the version that box86 print).

 ----

@@ -1,21 +1,22 @@
 # box86

+![Official logo](Box86Logo.png "Official Logo")
 Linux Userspace x86 Emulator with a twist

-[![Donate](https://img.shields.io/badge/Donate-PayPal-green.svg)](https://www.paypal.com/cgi-bin/webscr?cmd=_donations&business=LU8Y2T62ZWFHU)
+Box86 lets you run x86 Linux programs (such as games) on non-x86 Linux, like ARM (host system needs to be 32bit little-endian).

-Box86 will let you run x86 Linux programs (games) on non-x86 Linux, like ARM (host system needs to be 32bit little-endian).
+You *NEED* a 32-bit subsystem to run and build Box86. Box86 is useless on 64-bit only systems. Also, you *NEED* a 32-bit toolchain to build Box86. A toolchain that only support 64-bit will not compile Box86, and you'll get errors (typically on aarch64, you get "-marm" not recognized, and you'll need a multiarch or chroot environnement).

-Because Box86 uses the native version for some "system" libraries, like libc, libm, or SDL and OpenGL, it's easy to integrate and use, and performances can be surprinsigly high in some cases.
+Because Box86 uses the native versions of some "system" libraries, like libc, libm, SDL, and OpenGL, it's easy to integrate and use, and performance can be surprisingly high in some cases.

-Most x86 Games need OpenGL, so on ARM platforms, a solution like [gl4es](https://github.com/ptitSeb/gl4es) is probably needed.
+Most x86 Games need OpenGL, so on ARM platforms a solution like [gl4es](https://github.com/ptitSeb/gl4es) is usually necessary(most ARM platforms only support OpenGL ES and/or their OpenGL implementation is dodgy (see OpenGL on Android)) .

-Box86 now integrate a DynaRec for ARM platform, providing a speed boost between 5 to 10 times compared to only the interpretor.
+Box86 now integrates a DynaRec (dynamic recompiler) for the ARM platform, providing a speed boost between 5 to 10 times faster than only using the interpreter.

-Many games already work, like for example: WorldOfGoo, Airline Tycoon Deluxe or FTL. Many of the GameMaker linux games also run fine (there a long list, among them are UNDERTALE, A Risk of Rain, and Cook Server Delicious)
+Many games already work, for example: WorldOfGoo, Airline Tycoon Deluxe, and FTL. Many of the GameMaker Linux games also run fine (there a long list, among them are UNDERTALE, A Risk of Rain, and Cook Server Delicious)

-If you are serious about developing Box86, you should install ccache and activate it's support in the cmake project (use ccmake for example)
-To have TRACE enabled (i.e. dumping to stdout all individual x86 instructions executed, with dump of registers), you'll also need [Zydis library](https://github.com/zyantific/zydis) accessible on your system.
+If you are serious about developing Box86, you should install ccache and activate its support in the cmake project (use ccmake for example)
+To enable TRACE (i.e. dumping to stdout all individual x86 instructions executed, with dump of registers), you'll also need [Zydis library](https://github.com/zyantific/zydis) available on your system.

 Some x86 internal opcodes use parts of "Realmode X86 Emulator Library", see [x86primop.c](src/x86primop.c) for copyright details

@@ -23,46 +24,85 @@ Here are 6 videos, the first 2 of "Airline Tycoon Deluxe" and "Heretic 2" runnin

 [![Play on Youtube](https://img.youtube.com/vi/bLt0hMoFDLk/3.jpg)](https://www.youtube.com/watch?v=bLt0hMoFDLk) [![Play on Youtube](https://img.youtube.com/vi/MM7kWYts7IA/3.jpg)](https://www.youtube.com/watch?v=MM7kWYts7IA) [![Play on Youtube](https://img.youtube.com/vi/8hr71S029Hg/1.jpg)](https://www.youtube.com/watch?v=8hr71S029Hg) [![Play on Youtube](https://img.youtube.com/vi/B4YN37z3-ws/1.jpg)](https://www.youtube.com/watch?v=B4YN37z3-ws) [![Play on Youtube](https://img.youtube.com/vi/xk8Q30mxqPg/1.jpg)](https://www.youtube.com/watch?v=xk8Q30mxqPg) [![Play on Youtube](https://img.youtube.com/vi/_QMRMVvYrqU/1.jpg)](https://www.youtube.com/watch?v=_QMRMVvYrqU)

+You can find many more Box86 video on [PI Lab Channel](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g) [![PI Lab Channel](https://yt3.ggpht.com/a/AATXAJyMeWrgCjs78gr6To6yX4KtDPUCS7hsbX1rRA=s100-c-k-c0xffffffff-no-rj-mo)](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g).
+
+Compatibility list is there: https://github.com/ptitSeb/box86-compatibility-list/issues
+
+<img src="Box86Icon.png" width="96" height="96">
+
+Logo and Icon made by @grayduck, thanks!
+
+Note that this project is not to be mistaken with [86box](https://github.com/86Box/86Box), a nice "Full system" emulator specialized in early (to fairly recent) PC hardware.
+
+----
+
+Discord
+----
+
+If you want to discuss(or have any problems) about box86, there is a Discord friendly server there: [PI Lab Discord](https://discord.gg/Fh8sjmu)
+
+
 ----

 Compiling
 ----
-How to compile can be found [here](COMPILE.md)
+Compilation instructions can be found [here](COMPILE.md)

 ----

 Usage
 ----

-There are a few environment variables to control Box86 behaviour.
+There are a few environment variables  to control the behaviour of Box86.

-See [here](USAGE.md) for all variables and what they do.
+See [here](USAGE.md) for all environment variables and what they do.
+
+Note: Box86's Dynarec uses a mechanism with Memory Protection and a SegFault signal handler to handle JIT code. In simpler terms, if you want to use GDB to debug a running program that use JIT'd code (like mono/Unity3D), you will still have many "normal" segfaults triggering. It is suggested to use something like `handle SIGSEGV nostop` in GDB to not stop at each segfault, and maybe put a breakpoint inside `my_memprotectionhandler` in `signals.c` if you want to trap SegFaults.

 ----

 Version history
 ----

-The change log is [here](CHANGELOG.md)
+The change log is available [here](CHANGELOG.md)

 ----

-A note about 64bits platform
+Notes about 64-bit platforms
 ----

-Because box86 works by directly translating function calls from x86 to host system, the host system (the one box86 is running on) needs to have 32bits library. Box86 doesn't include any 32bits <-> 64bits translation. So basically, to run box86 on, for example, an ARM64 platform, you will need to build box86 for arm 32bits, and also need to have a chroot with 32bits library.
+Because Box86 works by directly translating function calls from x86 to host system, the host system (the one Box86 is running on) needs to have 32-bit libraries. Box86 doesn't include any 32-bit <-> 64-bit translation. So basically, to run Box86 on, for example, an ARM64 platform, you will need to build Box86 for ARM 32-bit, and also need to have a chroot with 32-bit libraries.

-Also note that, even if, on day, there is a box86_64, this one will only be able to run x86_64 binary on 64bits platform. You will still need box86 (and see 32bits chroot) to run x86 binary (in fact, like it is the case on actual x86_64 linux)
+Also note that, even if, on day, there is a Box86_64, this one will only be able to run x86_64 binaries on 64-bit platforms. You will still need Box86 (and a 32-bit chroot) to run x86 binaries (in fact, the same is the case on actual x86_64 Linux).

 ----

 A note about Unity game emulation
 ----

-Running Unity games is not possible for now. Mono itself uses signals that are not well emulated enough. So the solution is to use a native version of the libmono used by Unity. It can be found here: https://github.com/Unity-Technologies/mono and it needs to be built from source. When built copy `libmonosgen-2.0.so` to `libmonounity.so` and put it somewhere it can be dlopen'd (so in `usr/lib` or friend or somewhere in your `LD_LIBRARY_PATH`).
-Note that libmonounity is not completely wrapped yet, and the mechanism to call x86 library from libmonounity is not done yet, so the use of libmonounity is not enable for now. 
+Running Unity games is a hit or miss for now. Unity uses Mono (which uses signals that are not well emulated enough), and a runtime embedded in the main binary. A solution would be to use a native version of the libmono library used by Unity (it can be found here: https://github.com/Unity-Technologies/mono and needs to be built from source). But the wrapping of this lib is tricky, and not done for now, so the only solution is to emulate everything. The tricky part is to emulate the "JIT" code emitted by Mono, however with the new "protected memory" mechanism implemented it should be running with correct performance now.
+You should also note that some Unity3D games require OpenGL 3+ which can be tricky to provide on ARM SBC (single-board computers) for now.

-TL;DR: mono games are not working for now anyway.
+TL;DR: Not all Unity games work and can require a high OpenGL profile, but the speed, for the ones running, should be correct now.
+
+----
+
+Notes about Steam
+----
+
+Linux Steam's can run now with box86. But it's still a bit unstable, and not everything works. First problem is steam crashing after the Sign in window, if you encounter this issue, you may need to add libappindicator. Installing the package on debian `sudo apt install libappindicator1`.
+Once open, Steam will only work on "Small Mode" and in "Big Picture", not in the regular "Large Mode"(This is because some steam component used in the browser view are only 64 bits now.). So go in the "View" menu and switch to Small view, else the list will stay empty.
+Final words, to avoid the "libc.so.6 is absent" message, you can use `STEAMOS=1` and `STEAM_RUNTIME=1` as environment variables. 
+(Steam for Windows installs fine but doesn't work yet)
+Some Steam games (most Source engine games, like "Portal" or "Half-Life 2") use libtcmalloc. Box86 will detect it and will try to LD_PRELOAD it, for better compatibility. While it should work without the aformentionned feature, it is safer to add it to your system if you intend to play those game (something like `sudo apt install libtcmalloc-minimal4` to install it on Debian and Debian's deriatives)
+
+----
+
+Notes about Wine
+----
+
+Wine is now partly supported. Wine integrated program all runs, and some windows programs and games now runs fine. Don't forget most Windows games use Direct3D, this may require a complete OpenGL driver and as high profile as possible (and gl4es with ES2 backend have issue with Wine for now). Also, vulkan is not wrapped on box86, so vk3d is not usable yet, even if supported by the hardware.
+Note: if you plan to use box86 with Wine on Raspberry Pi 3 or earlier, those models use a default OS that have a kernel with a 2/2 Split (meaning 2G of space for user program, and 2G of space for the Kernel). This is not compatible with Wine programs that needs to access memory > 2Gb address. So you'll need to reconfigure your kernel for a 3G/1G split. Use your favorite search engine for instructions on how to do that.

 ----

@@ -1,25 +1,31 @@
+
 Usage
 ----

-There are many environment variable to control Box86 behaviour. 
+There are many environment variables to control Box86 behaviour. 

-##### BOX86_LOG
-Controls the Verbose level of the log
+#### BOX86_LOG
+Controls the Verbosity level of the logs
 * 0
- * NONE : No message (except some fatal error)
+ * NONE : Current default. No message (except some fatal error)
 * 1
- * INFO : Current default. Show some log
+ * INFO : Show some minimum log (like librairies not found)
 * 2
- * DEBUG : Verbose a lot of stuffs (like relocations or function called)
+ * DEBUG : Details a lot of stuff (like relocations or function called)
 * 3
 * DUMP : All DEBUG plus DUMP of all ELF Info

+#### BOX86_NOBANNER
+Control Box86 printing its version and build
+ * 0 : Enable printing
+ * 1 : Disable printing 
+
 #### BOX86_LD_LIBRARY_PATH
-Controls the folder scanned to look for x86 libs. Default is current folder and `lib` in current folder.
+Path to look for x86 libs. Default is current folder and `lib` in current folder.
 Also `/usr/lib/i386-linux-gnu` and `/lib/i386-linux-gnu` are added if they exists

 #### BOX86_PATH
-Controls the folder scanned to look for x86 executable. Default is current folder and `bin` in current folder.
+Path to look for x86 executable. Default is current folder and `bin` in current folder.

 #### BOX86_DLSYM_ERROR
 * 0 : default. Don't log `dlsym` error
@@ -27,16 +33,17 @@ Controls the folder scanned to look for x86 executable. Default is current folde

 #### BOX86_TRACE_FILE
 Send all log and trace to a file instead of `stdout`
+Also, if name contains `%pid` then this is replaced by the actual PID of box86 instance

 #### BOX86_TRACE
-Only on build with trace enabled. Trace allow the logging of all instruction execute, along with register dump
+Only on build with trace enabled. Trace allow the logging of all instruction executed, along with register dump
 * 0 : No trace
-* 1 : Trace enabled. The trace start after the init of all depending libs is done
+* 1 : Trace enabled. Trace start after the initialisation of all depending libraries is done
 * symbolname : Trace only `symbolname` (trace is disable if the symbol is not found)
 * 0xXXXXXXX-0xYYYYYYY : trace only between the 2 addresses

 #### BOX86_TRACE_INIT
-Use BOX86_TRACE_INIT instead of BOX_TRACE to start trace before init of Libs and main program
+Use BOX86_TRACE_INIT instead of BOX_TRACE to start trace before the initialisation of libraries and the running program
 * 0 : No trace
 * 1 : Trace enabled. The trace start with the init of all depending libs is done

@@ -46,28 +53,44 @@ Only on build with trace enabled.

 #### BOX86_TRACE_XMM
 Only on build with trace enabled.
-* 0 : Default, the XMM (i.e. SSE/SSE2) register will not be logged with the general and x87 registers
+* 0 : Default, the XMM (i.e. SSE/SSE2) register will not be logged with the general and x86 registers
 * 1 : Dump the XMM registers

 #### BOX86_LOAD_ADDR
-Try to load at 0xXXXXXX main binaray (if binary is a PIE)
+Try to load at 0xXXXXXX main binary (if binary is a PIE)
 * 0xXXXXXXXX the load address (only active on PIE programs)

 #### BOX86_NOSIGSEGV
-To disable handling of SigSEGV (to ease debugging mainly)
+Disable handling of SigSEGV ( Very useful for debugging.)
 * 0 : default, let x86 program set sighandler for SEGV
 * 1 : disable handling of SigSEGV

+#### BOX86_NOSIGILL
+Disable handling of SigILL (to ease debugging mainly)
+* 0 : default, let x86 program set sighandler for Illegal Instruction
+* 1 : disable handling of SigILL
+
 #### BOX86_X11COLOR16
-PANDORA only: to try convert X11 color from 32 bits to 16 bits (to avoid light green on light cyan windows
+PANDORA only: Try converting X11 color from 32 bits to 16 bits (to avoid light green on light cyan windows)
 * 0 : default, don't touch X11 colors
 * 1 : Change colors arguments in XSetForeground, XSetBackground and XCreateGC

 #### BOX86_X11THREADS
-To call XInitThreads when loading X11 (for old Loki games with Loki_Compat lib)
+Call XInitThreads when loading X11 (for old Loki games with Loki_Compat lib)
 * 0 : default, don't force call XInitThreads
 * 1 : Call XInitThreads as soon as libX11 is loaded

+#### BOX86_X11GLX
+Force libX11 GLX extension to be present.
+* 0 : Disable the force.
+* 1 : default, GLX will always be present when using XQueryExtension
+
+#### BOX86_DYNAREC_DUMP
+ Enables/disables box86's dynarec dump.
+ * 0 : Disable Dynarec blocks dump (default)
+ * 1 : Enable Dynarec blocks dump
+ * 2 : Enable Dynarec blocks dump with some colors
+
 #### BOX86_DYNAREC_LOG
 Set level of DynaRec log
 * 0 :
@@ -77,7 +100,7 @@ Set level of DynaRec log
 * 2 :
 * DEBUG : Debug Log for Dynarec (with detail on block created / executed)
 * 3 :
- * DUMP : All above plus dump of the x86 -> native opcode conversions
+ * VERBOSE : All above plus more

 #### BOX86_DYNAREC
 * 0 : Disable Dynarec
@@ -87,7 +110,12 @@ Set level of DynaRec log
 * 0 : Disable Dynarec Linker (use that on debug, with dynarec log >= 2, to have detail on wich block get executed)
 * 1 : Enable Dynarec Linker (default)

+#### BOX86_DYNAREC_SAFEMMAP
+ * 0 : Default. Some mmp/mmap64 are consider unsafe (depending of flags mainly)
+ * 1 : Consider all mmap/mmap64 safe to use linker (potential speedup, but potential crash for apps using JIT/Dynarec)
+
 #### BOX86_DYNAREC_TRACE
+Enables/Disables trace for generated code
 * 0 : Disable trace for generated code (default)
 * 1 : Enable trace for generated code (like regular Trace, this will slow down a lot and generate huge logs)

@@ -102,11 +130,39 @@ Set level of DynaRec log
 
 #### BOX86_EMULATED_LIBS
 * XXXX[:YYYYY] force lib XXXX (and YYYY...) to be emulated (and not wrapped)
-Some games use old version of some lib, with an ABI incompatible with native version.
-Note that LittleInforno for example is auto detected, and libvorbis.so.0 is automatical added to emulated libs
+Some games uses an old version of some libraries, with an ABI incompatible with native version.
+Note that LittleInferno for example is auto detected, and libvorbis.so.0 is automatical added to emulated libs, and same for Don't Starve (and Together / Server variant) that use an old SDL2 too

 #### BOX86_ALLOWMISSINGLIBS
-Allow box86 to continue even if a lib is missing
- * 0 : default, stop if a lib cannot be loaded
- * 1 : continue even if a needed lib cannot be loaded. Unadvised, this will, in most cases, crash later on.
+Allow box86 to continue even if a library is missing
+ * 0 : default, stop if a library cannot be loaded
+ * 1 : continue even if a needed library cannot be loaded. Unadvised, this will, in most cases, crash later on.

+#### BOX86_NOPULSE
+Disable the load of pulseaudio libraries
+ * 0 : default, load pulseaudio libraries if present
+ * 1 : disable the load of pulse audio libraries (libpulse and libpulse-simple), both native and x86 version
+
+#### BOX86_NOGTK
+Disable the load of wrapped GTK libraries
+ * 0 : default, load wrapped gtk libs if present
+ * 1 : disable the load of wrapped gtk libs (can be used with Steam, along with STEAM_RUNTIME=1 to use i386 versio of gtk)
+
+#### BOX86_NOVULKAN
+Disable the load of vulkan libraries
+ * 0 : default, load vulkan libraries if present
+ * 1 : disable the load of vulkan libraries both native and x86 version (can be usefull on Pi4)
+
+#### BOX86_FIX_64BIT_INODES
+ * 0 : Don't fix 64bit inodes (default)
+ * 1 : Fix 64bit inodes. Helps when running on filesystems with 64bit inodes, the program uses API functions which doesn't support it and the program doesn't use inodes information.
+
+#### BOX86_JITGDB
+* 0 : Just print the Segfault message on segfault (default)
+* 1 : Launch `gdb` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process, and go in an endless loop, waiting.
+        When in gdb, you need to find the correct thread yourself (the one with `my_box86signalhandler` in is stack)
+        then probably need to `finish` 1 or 2 functions (inside `usleep(..)`) and then you'll be in `my_box86signalhandler`, 
+        just before the printf of the Segfault message. Then simply `set waiting=0` to exit the infinite loop.
+* 2 : Launch `gdbserver` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process, and go in an endless loop, waiting.
+        Use `gdb /PATH/TO/box86` and then `target remote 127.0.0.1:1234` to connect to the gdbserver (or use actual IP if not on the machine). After that, the procedure is the same as with ` BOX86_JITGDB=1`.
+        This mode can be usefull when program redirect all console output to a file (like Unity3D Games)
@@ -0,0 +1 @@
+theme: jekyll-theme-hacker
@@ -0,0 +1,44 @@
+# Maintainer: SpacingBat3 <[email protected]>
+# Contributor: Sebastien Chevalier <[email protected]>
+pkgname=box86-arm-git
+pkgver=r2798.0edc0374
+pkgrel=1
+pkgdesc="Linux Userspace x86 Emulator with a twist, targeted at ARM Linux devices."
+arch=('armv7h')
+url="https://github.com/ptitSeb/box86"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${_pkgname%-arm-git}-git" "${_pkgname%-arm-git}")
+conflicts=("${pkgname%-git}" "${_pkgname%-arm-git}-git" "${_pkgname%-arm-git}")
+source=('git+https://github.com/ptitSeb/box86')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-arm-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-arm-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DARM_DYNAREC=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-arm-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-arm-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}
@@ -0,0 +1,44 @@
+# Maintainer: SpacingBat3 <[email protected]>
+# Contributor: Sebastien Chevalier <[email protected]>
+pkgname=box86-gameshell-git
+pkgver=r2798.0edc0374
+pkgrel=1
+pkgdesc="Linux Userspace x86 Emulator with a twist, targeted at ARM Linux devices."
+arch=('armv7h')
+url="https://github.com/ptitSeb/box86"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-gameshell-git}-git" "${pkgname%-gameshell-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-gameshell-git}-git" "${pkgname%-gameshell-git}")
+source=('git+https://github.com/ptitSeb/box86')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-gameshell-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-gameshell-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DGAMESHELL=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-gameshell-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-gameshell-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}
@@ -0,0 +1,44 @@
+# Maintainer: SpacingBat3 <[email protected]>
+# Contributor: Sebastien Chevalier <[email protected]>
+pkgname=box86-odroid-git
+pkgver=r2798.0edc0374
+pkgrel=1
+pkgdesc="Linux Userspace x86 Emulator with a twist, targeted at ARM Linux devices."
+arch=('armv7h')
+url="https://github.com/ptitSeb/box86"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${_pkgname%-odroid-git}-git" "${_pkgname%-odroid-git}")
+conflicts=("${pkgname%-git}" "${_pkgname%-odroid-git}-git" "${_pkgname%-odroid-git}")
+source=('git+https://github.com/ptitSeb/box86')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-odroid-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-odroid-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DODROID=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-odroid-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-odroid-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}
@@ -0,0 +1,45 @@
+# Maintainer: SpacingBat3 <[email protected]>
+# Contributor: Sebastien Chevalier <[email protected]>
+pkgname=box86-pandora-git
+_pkgname=box86-git
+pkgver=r2798.0edc0374
+pkgrel=1
+pkgdesc="Linux Userspace x86 Emulator with a twist, targeted at ARM Linux devices."
+arch=('armv7h')
+url="https://github.com/ptitSeb/box86"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-pandora-git}"-git "${pkgname%-pandora-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-pandora-git}"-git "${pkgname%-pandora-git}")
+source=('git+https://github.com/ptitSeb/box86')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-pandora-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-pandora-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DPANDORA=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-pandora-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}
@@ -0,0 +1,45 @@
+# Maintainer: SpacingBat3 <[email protected]>
+# Contributor: Sebastien Chevalier <[email protected]>
+pkgname=box86-pyra-git
+_pkgname=box86-git
+pkgver=r2798.0edc0374
+pkgrel=1
+pkgdesc="Linux Userspace x86 Emulator with a twist, targeted at ARM Linux devices."
+arch=('armv7h')
+url="https://github.com/ptitSeb/box86"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-pyra-git}-git" "${pkgname%-pyra-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-pyra-git}-git" "${pkgname%-pyra-git}")
+source=('git+https://github.com/ptitSeb/box86')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-pyra-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-pyra-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DPYRA=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-pyra-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-pyra-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}
@@ -0,0 +1,60 @@
+# Maintainer: SpacingBat3 <[email protected]>
+# Contributor: Sebastien Chevalier <[email protected]>
+pkgname=box86-rpi-git
+_pkgname=box86-git
+pkgver=r2798.0edc0374
+pkgrel=1
+pkgdesc="Linux Userspace x86 Emulator with a twist, targeted at ARM Linux devices."
+arch=('armv7h')
+url="https://github.com/ptitSeb/box86"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-rpi-git}-git" "${pkgname%--rpi-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-rpi-git}-git" "${pkgname%--rpi-git}")
+source=('git+https://github.com/ptitSeb/box86')
+md5sums=('SKIP')
+_pimodel=`tr -d '\0' < /sys/firmware/devicetree/base/model`
+
+pkgver() {
+	cd "$srcdir/${pkgname%-rpi-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-rpi-git}"
+	# Check for Pi version number
+	if [[ ${_pimodel} =~ "Raspberry Pi 4" ]]; then
+		_piversion=4
+	elif [[ ${_pimodel} =~ "Raspberry Pi 3" ]]; then
+		_piversion=3
+	elif [[ ${_pimodel} =~ "Raspberry Pi 2" ]]; then
+		_piversion=2
+	else
+		# This RPI is not supported or this device is not a pi.
+		# We should cancel then the build.
+		echo -e "\033[01m\033[01;31m==> ERROR:\033[00;01m Your device is not supported! This script is for RPi model 4/3/2 (1/0 isn't supported yet).\033[00m"
+		exit 1
+	fi
+	echo -e "\033[01m\033[01;34m==> INFO:\033[00;01m Your detected Pi verion number is: \033[01;31m${_piversion}\033[01m.\033[00m"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DRPI${_piversion}=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-rpi-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-rpi-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}
@@ -0,0 +1,39 @@
+# Maintainer: SpacingBat3 <[email protected]>
+# Contributor: Sebastien Chevalier <[email protected]>
+pkgname=box86-rk3399-git
+_pkgname=box86-git
+pkgver=r2798.0edc0374
+pkgrel=1
+pkgdesc="Linux Userspace x86 Emulator with a twist, targeted at ARM Linux devices."
+arch=('armv7h')
+url="https://github.com/ptitSeb/box86"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-rk3399-git}-git" "${pkgname%-rk3399-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-rk3399-git}-git" "${pkgname%-rk3399-git}")
+source=('git+https://github.com/ptitSeb/box86')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-rk3399-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-rk3399-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DRK3399=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-rk3399-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-rk3399-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}
@@ -0,0 +1,44 @@
+# Maintainer: SpacingBat3 <[email protected]>
+# Contributor: Sebastien Chevalier <[email protected]>
+pkgname=box86-x86-git
+_pkgname=box86-git
+pkgver=r2798.0edc0374
+pkgrel=1
+pkgdesc="Linux Userspace x86 Emulator with a twist, targeted at ARM Linux devices."
+arch=('i386')
+url="https://github.com/ptitSeb/box86"
+license=('MIT')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-x86-git}")
+conflicts=("${pkgname%-x86-git}")
+source=('git+https://github.com/ptitSeb/box86')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-x86-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-x86-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DLD80BITS=1 -DNOALIGN=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-x86-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-x86-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}
@@ -0,0 +1,21 @@
+# The directory containing all PKGBUILDs for BOX86
+## FAQ
+### 1. How to use it?
+Just download the `PKGBUILD-<your-platform>` (no need to download the whole repository), go to directory where you downloaded and type:
+```sh
+mv ./PKGBUILD-<your-platform> ./PKGBUILD
+cd ..
+makepkg -si
+```
+This will copy the PKGBUILD for your platform (where you type your platform name instead of `<your-platform>`), build it and install the PKGBUILD on 32-bit Archlinux ARM.
+
+In the future, I might try to do an unified PKGBUILD for all platforms that will recognize your platform automatically.
+
+### 2. What platforms are currently supported.
+All specified in [COMPILE.md](../COMPILE.md).
+
+### 3. Any advantages with that sollution?
+This might give you some advantages like those:
+- automatic updates (with some AUR frontends like [`pamac-aur`](https://aur.archlinux.org/packages/pamac-aur/) or [`yay`](https://aur.archlinux.org/packages/yay));
+- easily uninstall with `pacman -R` when no needed (no need other scripts nor Makefile to do this);
+- your `box86` installation is recognized as a package (where it wasn't when installing with `make install`).
@@ -1,19 +1,17 @@
 #!/usr/bin/env python

 import os
-import glob
 import sys

-values = ['E', 'e', 'v', 'c', 'w', 'i', 'I', 'C', 'W', 'u', 'U', 'f', 'd', 'D', 'K', 'l', 'L', 'p', 'V', "O", "S"]
+values = ['E', 'e', 'v', 'c', 'w', 'i', 'I', 'C', 'W', 'u', 'U', 'f', 'd', 'D', 'K', 'l', 'L', 'p', 'V', 'O', 'S', '2', 'P', 'G', 'N', 'M']
 def splitchar(s):
-	ret = [len(s)]
-	i = 0
-	for c in s:
-		i = i + 1
-		if i == 2:
-			continue
-		ret.append(values.index(c))
-	return ret
+	try:
+		ret = [len(s), values.index(s[0])]
+		for c in s[2:]:
+			ret.append(values.index(c))
+		return ret
+	except ValueError as e:
+		raise ValueError("Value is " + s) from e

 def value(define):
 	return define[9:-1] if define.startswith("!") else define[8:-1]
@@ -36,16 +34,16 @@ def splitdef(dnf, defines):
 def invert(define):
 	return define[1:] if define.startswith("!") else ("!" + define)

-def main(root, defines, ver):
-	# Initialize variables: gbl for all values, vals for file-per-file values, redirects for redirections
+def main(root, defines, files, ver):
+	global values
+	
+	# Initialize variables: gbl for all values, redirects for redirections
 	gbl = {}
-	vals = {}
 	redirects = {}
 	
 	# First read the files inside the headers
-	for filepath in glob.glob(os.path.join(root, "src/wrapped/", "wrapped*_private.h")):
+	for filepath in files:
 		filename = filepath.split("/")[-1]
-		locval = {}
 		dependants = []
 		with open(filepath, 'r') as file:
 			for line in file:
@@ -68,8 +66,8 @@ def main(root, defines, ver):
 								raise KeyError(preproc_cmd[5:].strip())
 							dependants.append("defined(" + preproc_cmd[5:].strip() + ")")
 						elif preproc_cmd.startswith("ifndef"):
-							if preproc_cmd[5:].strip() not in defines:
-								raise KeyError(preproc_cmd[5:].strip())
+							if preproc_cmd[6:].strip() not in defines:
+								raise KeyError(preproc_cmd[6:].strip())
 							dependants.append("!defined(" + preproc_cmd[6:].strip() + ")")
 						elif preproc_cmd.startswith("else"):
 							dependants[-1] = invert(dependants[-1])
@@ -91,29 +89,20 @@ def main(root, defines, ver):
 					if any(c not in values for c in ln[2:]) or (('v' in ln[2:]) and (len(ln) > 3)):
 						old = ln
 						# This needs more work
-						acceptables = ['v', 'o', '0', '1'] + values
+						acceptables = ['v', '0', '1'] + values
 						if any(c not in acceptables for c in ln[2:]):
 							raise NotImplementedError("{0} ({1}:{2})".format(ln[2:], filename, line[:-1]))
-						# Ok, this is acceptable: there is 0, 1, stdout and void
+						# Ok, this is acceptable: there is 0, 1 and/or void
 						ln = (ln
 							.replace("v", "")   # void   -> nothing
-							.replace("o", "p")  # stdout -> pointer
 							.replace("0", "p")  # 0      -> pointer
 							.replace("1", "i")) # 1      -> integer
 						redirects.setdefault(" && ".join(dependants), {})
 						redirects[" && ".join(dependants)][old] = ln
 					# Simply append the function name if it's not yet existing
-					locval.setdefault(" && ".join(dependants), [])
 					gbl.setdefault(" && ".join(dependants), [])
-					if ln not in locval[" && ".join(dependants)]:
-						locval[" && ".join(dependants)].append(ln)
 					if ln not in gbl[" && ".join(dependants)]:
 						gbl[" && ".join(dependants)].append(ln)
-		
-		# Sort the file local values and add it to the dictionary
-		for k in locval:
-			locval[k].sort(key=splitchar)
-		vals[filename] = locval
 	
 	gbl_vals = {}
 	for k in gbl:
@@ -180,24 +169,44 @@ def main(root, defines, ver):
 	redirects_idxs = []
 	for k, v in redirects_vals:
 		key = "(" + (") || (".join(redirects_vals[(k, v)])) + ")"
-		val = redirects.get(key, {})
-		val[k] = v
-		redirects[key] = val
+		if key in redirects:
+			redirects[key].append([k, v])
+		else:
+			redirects[key] = [[k, v]]
 		if (key not in redirects_idxs) and (key != "()"):
 			redirects_idxs.append(key)
 	redirects_idxs.sort(key=lambda v: splitdef(v, defines))
 	
-	# Sort the table
+	# Sort the tables
 	for k in gbl:
 		gbl[k].sort(key=lambda v: splitchar(v))
+	values = values + ['0', '1']
+	for k in redirects:
+		redirects[k].sort(key=lambda v: splitchar(v[0]) + [0] + splitchar(v[1]))
+	values = values[:-2]
 	
-	def length(s):
-		l = len(s)
-		if l < 10:
-			ret = "0" + str(l)
-		else:
-			ret = str(l)
-		return ret
+	# Check if there was any new functions
+	functions_list = ""
+	for k in ["()"] + gbl_idxs:
+		for v in gbl[k]:
+			functions_list = functions_list + "#" + k + " " + v + "\n"
+	for k in ["()"] + redirects_idxs:
+		for v in redirects[k]:
+			functions_list = functions_list + "#" + k + " " + v[0] + " -> " + v[1] + "\n"
+	
+	# functions_list is a unique string, compare it with the last run
+	try:
+		last_run = ""
+		with open(os.path.join(root, "src", "wrapped", "generated", "functions_list.txt"), 'r') as file:
+			last_run = file.read()
+		if last_run == functions_list:
+			# Mark as OK for CMake
+			with open(os.path.join(root, "src", "wrapped", "generated", "functions_list.txt"), 'w') as file:
+				file.write(functions_list)
+			#return 0
+	except IOError:
+		# The file does not exist yet, first run
+		pass
 	
 	# Now the files rebuilding part
 	# File headers and guards
@@ -221,6 +230,11 @@ typedef union ui64_s {
    uint32_t    d[2];
 } ui64_t;

+typedef struct _2uint_struct_s {
+	uint32_t	a;
+	uint32_t	b;
+} _2uint_struct_t;
+
 extern void* my__IO_2_1_stderr_;
 extern void* my__IO_2_1_stdin_ ;
 extern void* my__IO_2_1_stdout_;
@@ -238,16 +252,36 @@ static void* io_convert(void* v)
 	return v;
 }

-#ifdef USE_FLOAT
-#define ST0val ST0.f
-#else
+typedef struct my_GValue_s
+{
+  int         g_type;
+  union {
+    int        v_int;
+    int64_t    v_int64;
+    uint64_t   v_uint64;
+    float      v_float;
+    double     v_double;
+    void*      v_pointer;
+  } data[2];
+} my_GValue_t;
+
+static void alignGValue(my_GValue_t* v, void* value)
+{
+    v->g_type = *(int*)value;
+    memcpy(v->data, value+4, 2*sizeof(double));
+}
+static void unalignGValue(void* value, my_GValue_t* v)
+{
+    *(int*)value = v->g_type;
+    memcpy(value+4, v->data, 2*sizeof(double));
+}
+
+void* VulkanFromx86(void* src, void** save);
+void VulkanTox86(void* src, void* save);
+
 #define ST0val ST0.d
-#endif
-#ifndef NOALIGN
-int of_convert(int flag) { return (flag&~0740000) | ((flag&0140000)<<2) | ((flag&0600000)>>2);}
-#else
-int of_convert(int flag) { return flag; }
-#endif
+
+int of_convert(int);
 """,
 		"wrapper.h": """/*****************************************************************
 * File automatically generated by rebuild_wrappers.py (v%s)
@@ -255,6 +289,7 @@ int of_convert(int flag) { return flag; }
 #ifndef __WRAPPER_H_
 #define __WRAPPER_H_
 #include <stdint.h>
+#include <string.h>

 typedef struct x86emu_s x86emu_t;

@@ -274,7 +309,11 @@ typedef void (*wrapper_t)(x86emu_t* emu, uintptr_t fnc);
 // O = libc O_ flags bitfield
 // S = _IO_2_1_stdXXX_ pointer (or FILE*)
 // Q = ...
-// S8 = struct, 8 bytes
+// 2 = struct of 2 uint
+// P = Vulkan struture pointer
+// G = a single GValue pointer
+// N = ... automatically sending 1 arg
+// M = ... automatically sending 2 args

 """
 	}
@@ -284,61 +323,122 @@ typedef void (*wrapper_t)(x86emu_t* emu, uintptr_t fnc);
 """
 	}
 	
-	# Transform strings into arrays
-	for k in gbl:
-		gbl[k] = [[c for c in v] for v in gbl[k]]
-	
 	# Rewrite the wrapper.h file:
-	with open(os.path.join(root, "src/wrapped/generated/", "wrapper.h"), 'w') as file:
+	with open(os.path.join(root, "src", "wrapped", "generated", "wrapper.h"), 'w') as file:
 		file.write(files_headers["wrapper.h"] % ver)
 		for v in gbl["()"]:
-			file.write("void " + ''.join(v) + "(x86emu_t *emu, uintptr_t fnc);\n")
+			file.write("void " + v + "(x86emu_t *emu, uintptr_t fnc);\n")
 		for k in gbl_idxs:
-			if k != "()":
-				file.write("\n#if " + k + "\n")
-				for v in gbl[k]:
-					file.write("void " + ''.join(v) + "(x86emu_t *emu, uintptr_t fnc);\n")
-				file.write("#endif\n")
+			file.write("\n#if " + k + "\n")
+			for v in gbl[k]:
+				file.write("void " + v + "(x86emu_t *emu, uintptr_t fnc);\n")
+			file.write("#endif\n")
 		file.write("\n")
 		for v in redirects["()"]:
-			file.write("void " + ''.join(v) + "(x86emu_t *emu, uintptr_t fnc);\n")
+			file.write("void " + v[0] + "(x86emu_t *emu, uintptr_t fnc);\n")
 		for k in redirects_idxs:
-			if k != "()":
-				file.write("\n#if " + k + "\n")
-				for v in redirects[k]:
-					file.write("void " + ''.join(v) + "(x86emu_t *emu, uintptr_t fnc);\n")
-				file.write("#endif\n")
+			file.write("\n#if " + k + "\n")
+			for v in redirects[k]:
+				file.write("void " + v[0] + "(x86emu_t *emu, uintptr_t fnc);\n")
+			file.write("#endif\n")
 		file.write(files_guards["wrapper.h"])
 	
 	# Rewrite the wrapper.c file:
-	with open(os.path.join(root, "src/wrapped/generated/", "wrapper.c"), 'w') as file:
+	with open(os.path.join(root, "src", "wrapped", "generated", "wrapper.c"), 'w') as file:
 		file.write(files_headers["wrapper.c"] % ver)
 		
 		# First part: typedefs
 		for v in gbl["()"]:
-			#         E            e             v       c         w          i          I          C          W           u           U           f        d         D              K         l           L            p        V			O        S
-			types = ["x86emu_t*", "x86emu_t**", "void", "int8_t", "int16_t", "int32_t", "int64_t", "uint8_t", "uint16_t", "uint32_t", "uint64_t", "float", "double", "long double", "double", "intptr_t", "uintptr_t", "void*", "void*", "int32_t", "void*"]
+			#         E            e             v       c         w          i          I          C          W           u           U           f        d         D              K         l           L            p        V        O          S        2         		 P        G        N      M
+			types = ["x86emu_t*", "x86emu_t**", "void", "int8_t", "int16_t", "int32_t", "int64_t", "uint8_t", "uint16_t", "uint32_t", "uint64_t", "float", "double", "long double", "double", "intptr_t", "uintptr_t", "void*", "void*", "int32_t", "void*", "_2uint_struct_t", "void*", "void*", "...", "..."]
 			if len(values) != len(types):
 					raise NotImplementedError("len(values) = {lenval} != len(types) = {lentypes}".format(lenval=len(values), lentypes=len(types)))
 			
-			file.write("typedef " + types[values.index(v[0])] + " (*" + ''.join(v) + "_t)"
+			file.write("typedef " + types[values.index(v[0])] + " (*" + v + "_t)"
 				+ "(" + ', '.join(types[values.index(t)] for t in v[2:]) + ");\n")
 		for k in gbl_idxs:
-			if k != "()":
-				file.write("\n#if " + k + "\n")
-				for v in gbl[k]:
-					#         E            e             v       c         w          i          I          C          W           u           U           f        d         D              K         l           L            p        V			O        S
-					types = ["x86emu_t*", "x86emu_t**", "void", "int8_t", "int16_t", "int32_t", "int64_t", "uint8_t", "uint16_t", "uint32_t", "uint64_t", "float", "double", "long double", "double", "intptr_t", "uintptr_t", "void*", "void*", "int32_t", "void*"]
-					if len(values) != len(types):
-							raise NotImplementedError("len(values) = {lenval} != len(types) = {lentypes}".format(lenval=len(values), lentypes=len(types)))
-					
-					file.write("typedef " + types[values.index(v[0])] + " (*" + ''.join(v) + "_t)"
-						+ "(" + ', '.join(types[values.index(t)] for t in v[2:]) + ");\n")
-				file.write("#endif\n")
+			file.write("\n#if " + k + "\n")
+			for v in gbl[k]:
+				#         E            e             v       c         w          i          I          C          W           u           U           f        d         D              K         l           L            p        V        O          S        2      			 P        G        N      M
+				types = ["x86emu_t*", "x86emu_t**", "void", "int8_t", "int16_t", "int32_t", "int64_t", "uint8_t", "uint16_t", "uint32_t", "uint64_t", "float", "double", "long double", "double", "intptr_t", "uintptr_t", "void*", "void*", "int32_t", "void*", "_2uint_struct_t", "void*", "void*", "...", "..."]
+				if len(values) != len(types):
+						raise NotImplementedError("len(values) = {lenval} != len(types) = {lentypes}".format(lenval=len(values), lentypes=len(types)))
+				
+				file.write("typedef " + types[values.index(v[0])] + " (*" + v + "_t)"
+					+ "(" + ', '.join(types[values.index(t)] for t in v[2:]) + ");\n")
+			file.write("#endif\n")
 		
 		file.write("\n")
+		
 		# Next part: function definitions
 		
+		# Helper variables
+		arg = [
+			"emu, ",                                  # E
+			"&emu, ",                                 # e
+			"",                                       # v
+			"*(int8_t*)(R_ESP + {p}), ",              # c
+			"*(int16_t*)(R_ESP + {p}), ",             # w
+			"*(int32_t*)(R_ESP + {p}), ",             # i
+			"*(int64_t*)(R_ESP + {p}), ",             # I
+			"*(uint8_t*)(R_ESP + {p}), ",             # C
+			"*(uint16_t*)(R_ESP + {p}), ",            # W
+			"*(uint32_t*)(R_ESP + {p}), ",            # u
+			"*(uint64_t*)(R_ESP + {p}), ",            # U
+			"*(float*)(R_ESP + {p}), ",               # f
+			"*(double*)(R_ESP + {p}), ",              # d
+			"*(long double*)(R_ESP + {p}), ",         # D
+			"FromLD((void*)(R_ESP + {p})), ",         # K
+			"*(intptr_t*)(R_ESP + {p}), ",            # l
+			"*(uintptr_t*)(R_ESP + {p}), ",           # L
+			"*(void**)(R_ESP + {p}), ",               # p
+			"(void*)(R_ESP + {p}), ",                 # V
+			"of_convert(*(int32_t*)(R_ESP + {p})), ", # O
+			"io_convert(*(void**)(R_ESP + {p})), ",   # S
+			"(_2uint_struct_t){{*(uintptr_t*)(R_ESP + {p}),*(uintptr_t*)(R_ESP + {p} + 4)}}, ",	# 2
+			"arg{p}, ",                               # P
+			"&arg{p}, ",                              # G
+			"*(void**)(R_ESP + {p}), ",				  # N
+			"*(void**)(R_ESP + {p}),*(void**)(R_ESP + {p} + 4), ",	# M
+		]
+		#         E  e  v  c  w  i  I  C  W  u  U  f  d  D   K   l  L  p  V  O  S  2  P  G  N, M
+		deltas = [0, 0, 4, 4, 4, 4, 8, 4, 4, 4, 8, 4, 8, 12, 12, 4, 4, 4, 0, 4, 4, 8, 4, 4, 0, 0]
+		vals = [
+			"\n#error Invalid return type: emulator\n",                     # E
+			"\n#error Invalid return type: &emulator\n",                    # e
+			"fn({0});",                                                     # v
+			"R_EAX=fn({0});",                                               # c
+			"R_EAX=fn({0});",                                               # w
+			"R_EAX=fn({0});",                                               # i
+			"ui64_t r; r.i=fn({0}); R_EAX=r.d[0]; R_EDX=r.d[1];",           # I
+			"R_EAX=(unsigned char)fn({0});",                                # C
+			"R_EAX=(unsigned short)fn({0});",                               # W
+			"R_EAX=(uint32_t)fn({0});",                                     # u
+			"ui64_t r; r.u=(uint64_t)fn({0}); R_EAX=r.d[0]; R_EDX=r.d[1];", # U
+			"float fl=fn({0}); fpu_do_push(emu); ST0val = fl;",             # f
+			"double db=fn({0}); fpu_do_push(emu); ST0val = db;",            # d
+			"long double ld=fn({0}); fpu_do_push(emu); ST0val = ld;",       # D
+			"double db=fn({0}); fpu_do_push(emu); ST0val = db;",            # K
+			"R_EAX=(intptr_t)fn({0});",                                     # l
+			"R_EAX=(uintptr_t)fn({0});",                                    # L
+			"R_EAX=(uintptr_t)fn({0});",                                    # p
+			"\n#error Invalid return type: va_list\n",                      # V
+			"\n#error Invalid return type: at_flags\n",                     # O
+			"\n#error Invalid return type: _io_file*\n",                    # S
+			"\n#error Invalid return type: _2uint_struct\n",                # 2
+			"\n#error Invalid return type: Vulkan Struct\n",                # P
+			"\n#error Invalid return type: GValue Pointer\n",               # G
+			"\n#error Invalid return type: ... with 1 arg\n",               # N
+			"\n#error Invalid return type: ... with 2 args\n",              # M
+		]
+		# Asserts
+		if len(values) != len(arg):
+			raise NotImplementedError("len(values) = {lenval} != len(arg) = {lenarg}".format(lenval=len(values), lenarg=len(arg)))
+		if len(values) != len(deltas):
+			raise NotImplementedError("len(values) = {lenval} != len(deltas) = {lendeltas}".format(lenval=len(values), lendeltas=len(deltas)))
+		if len(values) != len(vals):
+			raise NotImplementedError("len(values) = {lenval} != len(vals) = {lenvals}".format(lenval=len(values), lenvals=len(vals)))
+		
 		# Helper functions to write the function definitions
 		def function_args(args, d=4):
 			if len(args) == 0:
@@ -351,89 +451,61 @@ typedef void (*wrapper_t)(x86emu_t* emu, uintptr_t fnc);
 			elif args[0] == "1":
 				return "1, " + function_args(args[1:], d)
 			
-			arg = [
-				"emu, ",                          # E
-				"&emu, ",                         # e
-				"",                               # v
-				"*(int8_t*)(R_ESP + {p}), ",      # c
-				"*(int16_t*)(R_ESP + {p}), ",     # w
-				"*(int32_t*)(R_ESP + {p}), ",     # i
-				"*(int64_t*)(R_ESP + {p}), ",     # I
-				"*(uint8_t*)(R_ESP + {p}), ",     # C
-				"*(uint16_t*)(R_ESP + {p}), ",    # W
-				"*(uint32_t*)(R_ESP + {p}), ",    # u
-				"*(uint64_t*)(R_ESP + {p}), ",    # U
-				"*(float*)(R_ESP + {p}), ",       # f
-				"*(double*)(R_ESP + {p}), ",      # d
-				"*(long double*)(R_ESP + {p}), ", # D
-				"FromLD((void*)(R_ESP + {p})), ", # K
-				"*(intptr_t*)(R_ESP + {p}), ",    # l
-				"*(uintptr_t*)(R_ESP + {p}), ",   # L
-				"*(void**)(R_ESP + {p}), ",       # p
-				"(void*)(R_ESP + {p}), ",         # V
-				"of_convert(*(int32_t*)(R_ESP + {p})), ",         # O
-				"io_convert(*(void**)(R_ESP + {p})), ",         # S
-			]
-			#         E  e  v  c  w  i  I  C  W  u  U  f  d  D   K   l  L  p  V  O  S
-			deltas = [0, 0, 4, 4, 4, 4, 8, 4, 4, 4, 8, 4, 8, 12, 12, 4, 4, 4, 0, 4, 4]
-			if len(values) != len(arg):
-				raise NotImplementedError("len(values) = {lenval} != len(arg) = {lenarg}".format(lenval=len(values), lenarg=len(arg)))
-			if len(values) != len(deltas):
-				raise NotImplementedError("len(values) = {lenval} != len(deltas) = {lendeltas}".format(lenval=len(values), lendeltas=len(deltas)))
 			return arg[values.index(args[0])].format(p=d) + function_args(args[1:], d + deltas[values.index(args[0])])
 		
 		def function_writer(f, N, W, rettype, args):
 			f.write("void {0}(x86emu_t *emu, uintptr_t fcn) {2} {1} fn = ({1})fcn; ".format(N, W, "{"))
-			vals = [
-				"\n#error Invalid return type: emulator\n",                     # E
-				"\n#error Invalid return type: &emulator\n",                    # e
-				"fn({0});",                                                     # v
-				"R_EAX=fn({0});",                                               # c
-				"R_EAX=fn({0});",                                               # w
-				"R_EAX=fn({0});",                                               # i
-				"ui64_t r; r.i=fn({0}); R_EAX=r.d[0]; R_EDX=r.d[1];",           # I
-				"R_EAX=(unsigned char)fn({0});",                                # C
-				"R_EAX=(unsigned short)fn({0});",                               # W
-				"R_EAX=(uint32_t)fn({0});",                                     # u
-				"ui64_t r; r.u=(uint64_t)fn({0}); R_EAX=r.d[0]; R_EDX=r.d[1];", # U
-				"float fl=fn({0}); fpu_do_push(emu); ST0val = fl;",             # f
-				"double db=fn({0}); fpu_do_push(emu); ST0val = db;",            # d
-				"long double ld=fn({0}); fpu_do_push(emu); ST0val = ld;",       # D
-				"double db=fn({0}); fpu_do_push(emu); ST0val = db;",            # K
-				"R_EAX=(intptr_t)fn({0});",                                     # l
-				"R_EAX=(uintptr_t)fn({0});",                                    # L
-				"R_EAX=(uintptr_t)fn({0});",                                    # p
-				"\n#error Invalid return type: va_list\n",                      # V
-				"\n#error Invalid return type: at_flags\n",                     # O
-				"\n#error Invalid return type: _io_file*\n",                    # S
-			]
-			if len(values) != len(vals):
-				raise NotImplementedError("len(values) = {lenval} != len(vals) = {lenvals}".format(lenval=len(values), lenvals=len(vals)))
-			f.write(vals[values.index(rettype)].format(function_args(args)[:-2]) + " }\n")
+			if any(cc in 'PG' for cc in args):
+				# Vulkan struct or GValue pointer, need to unwrap functions at the end
+				delta = 4
+				for c in args:
+					if c == 'P':
+						f.write("void* save{d}=NULL; void *arg{d} = VulkanFromx86(*(void**)(R_ESP + {d}), &save{d}); ".format(d=delta))
+					if c == 'G':
+    						f.write("my_GValue_t arg{d}; alignGValue(&arg{d}, *(void**)(R_ESP + {d})); ".format(d=delta))
+					delta = delta + deltas[values.index(c)]
+				f.write(vals[values.index(rettype)].format(function_args(args)[:-2]) + " ")
+				delta = 4
+				for c in args:
+					if c == 'P':
+						f.write("VulkanTox86(arg{d}, save{d}); ".format(d=delta))
+					if c == 'G':
+						f.write("unalignGValue(*(void**)(R_ESP + {d}), &arg{d}); ".format(d=delta))
+					delta = delta + deltas[values.index(c)]
+				f.write("}\n")
+			else:
+				# Generic function
+				f.write(vals[values.index(rettype)].format(function_args(args)[:-2]) + " }\n")
 		
 		for v in gbl["()"]:
-			function_writer(file, ''.join(v), ''.join(v) + "_t", v[0], v[2:])
+			function_writer(file, v, v + "_t", v[0], v[2:])
 		for k in gbl_idxs:
-			if k != "()":
-				file.write("\n#if " + k + "\n")
-				for v in gbl[k]:
-					function_writer(file, ''.join(v), ''.join(v) + "_t", v[0], v[2:])
-				file.write("#endif\n")
+			file.write("\n#if " + k + "\n")
+			for v in gbl[k]:
+				function_writer(file, v, v + "_t", v[0], v[2:])
+			file.write("#endif\n")
 		file.write("\n")
 		for v in redirects["()"]:
-			function_writer(file, v, redirects["()"][v] + "_t", v[0], v[2:])
+			function_writer(file, v[0], v[1] + "_t", v[0][0], v[0][2:])
 		for k in redirects_idxs:
-			if k != "()":
-				file.write("\n#if " + k + "\n")
-				for v in redirects[k]:
-					function_writer(file, v, redirects[k][v] + "_t", v[0], v[2:])
-				file.write("#endif\n")
+			file.write("\n#if " + k + "\n")
+			for v in redirects[k]:
+				function_writer(file, v[0], v[1] + "_t", v[0][0], v[0][2:])
+			file.write("#endif\n")
 		
 		file.write(files_guards["wrapper.c"])
 	
+	# Save the string for the next iteration, writing was successful
+	with open(os.path.join(root, "src", "wrapped", "generated", "functions_list.txt"), 'w') as file:
+		file.write(functions_list)
+	
 	return 0

 if __name__ == '__main__':
-	if main(sys.argv[1], sys.argv[2:], "1.1.1.06") != 0:
+	limit = []
+	for i, v in enumerate(sys.argv):
+		if v == "--":
+			limit.append(i)
+	if main(sys.argv[1], sys.argv[2:limit[0]], sys.argv[limit[0]+1:], "1.2.0.09") != 0:
 		exit(2)
 	exit(0)
@@ -13,7 +13,15 @@ if( NOT TEST_REFERENCE )
 endif( NOT TEST_REFERENCE )

 set(ENV{BOX86_LOG} 0)
-set(ENV{LD_LIBRARY_PATH} ${CMAKE_SOURCE_DIR}/x86lib)
+set(ENV{BOX86_NOBANNER} 1)
+if( EXISTS ${CMAKE_SOURCE_DIR}/x86lib )
+  # we are inside box86 folder
+  set(ENV{LD_LIBRARY_PATH} ${CMAKE_SOURCE_DIR}/x86lib)
+else()
+  # we are inside build folder
+  set(ENV{LD_LIBRARY_PATH} ${CMAKE_SOURCE_DIR}/../x86lib)
+endif( EXISTS ${CMAKE_SOURCE_DIR}/x86lib )
+
 # run the test program, capture the stdout/stderr and the result var
 execute_process(
  COMMAND ${TEST_PROGRAM} ${TEST_ARGS} ${TEST_ARGS2}
@@ -16,49 +16,112 @@
 #include "callback.h"
 #include "wrapper.h"
 #include "myfts.h"
-#ifdef DYNAREC
+#include "threads.h"
+#include "x86trace.h"
+#include "signals.h"
 #include <sys/mman.h>
+#include "custommem.h"
+#ifdef DYNAREC
 #include "dynablock.h"
+#include "dynarec/arm_lock_helper.h"
+#endif

-typedef struct mmaplist_s {
-    void*         block;
-    uintptr_t     offset;           // offset in the block
-} mmaplist_t;

-#define MMAPSIZE (4*1024*1024)       // allocate 4Mo sized blocks
-
-uintptr_t AllocDynarecMap(box86context_t *context, int size)
+#ifdef DYNAREC
+// Remove the Write flag from an adress range, so DB can be executed
+// no log, as it can be executed inside a signal handler
+void protectDB(uintptr_t addr, uintptr_t size)
 {
-    // make size 0x10 bytes aligned
-    size = (size+0x0f)&~0x0f;
-    pthread_mutex_lock(&context->mutex_mmap);
-    // look for free space
-    for(int i=0; i<context->mmapsize; ++i) {
-        if(context->mmaplist[i].offset+size < MMAPSIZE) {
-            uintptr_t ret = context->mmaplist[i].offset + (uintptr_t)context->mmaplist[i].block;
-            context->mmaplist[i].offset+=size;
-            pthread_mutex_unlock(&context->mutex_mmap);
-            return ret;
+    uintptr_t idx = (addr>>DYNAMAP_SHIFT);
+    uintptr_t end = ((addr+size-1)>>DYNAMAP_SHIFT);
+    for (uintptr_t i=idx; i<=end; ++i) {
+        uint32_t prot;
+        do {
+            prot=arm_lock_read_d(&my_context->memprot[i]);
+            if(!prot)
+                prot = PROT_READ | PROT_WRITE;    // comes from malloc & co, so should not be able to execute
+        } while(arm_lock_write_d(&my_context->memprot[i], prot|PROT_DYNAREC));
+        if(!(prot&PROT_DYNAREC))
+            mprotect((void*)(i<<DYNAMAP_SHIFT), 1<<DYNAMAP_SHIFT, prot&~PROT_WRITE);
+    }
+}
+
+// Add the Write flag from an adress range, and mark all block as dirty
+// no log, as it can be executed inside a signal handler
+void unprotectDB(uintptr_t addr, uintptr_t size)
+{
+    uintptr_t idx = (addr>>DYNAMAP_SHIFT);
+    uintptr_t end = ((addr+size-1)>>DYNAMAP_SHIFT);
+    for (uintptr_t i=idx; i<=end; ++i) {
+        uint32_t prot;
+        do {
+            prot=arm_lock_read_d(&my_context->memprot[i]);
+        } while(arm_lock_write_d(&my_context->memprot[i], prot&~PROT_DYNAREC));
+        if(prot&PROT_DYNAREC) {
+            mprotect((void*)(i<<DYNAMAP_SHIFT), 1<<DYNAMAP_SHIFT, prot&~PROT_DYNAREC);
+            cleanDBFromAddressRange((i<<DYNAMAP_SHIFT), 1<<DYNAMAP_SHIFT, 0);
        }
    }
-    // no luck, add a new one !
-    int i = context->mmapsize++;    // yeah, usefull post incrementation
-    dynarec_log(LOG_DEBUG, "Ask for DynaRec Block Alloc #%d\n", context->mmapsize);
-    context->mmaplist = (mmaplist_t*)realloc(context->mmaplist, context->mmapsize*sizeof(mmaplist_t));
-    void* p = mmap(NULL, MMAPSIZE, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
-    if(p==MAP_FAILED) {
-        dynarec_log(LOG_INFO, "Cannot create memory map of %d byte for dynarec block #%d\n", MMAPSIZE, i);
-        --context->mmapsize;
-        pthread_mutex_unlock(&context->mutex_mmap);
-        return 0;
-    }
-    context->mmaplist[i].block = p;
-    context->mmaplist[i].offset=size;
-    pthread_mutex_unlock(&context->mutex_mmap);
-    return (uintptr_t)p;
 }
+
 #endif

+void updateProtection(uintptr_t addr, uintptr_t size, uint32_t prot)
+{
+    const uintptr_t idx = (addr>>DYNAMAP_SHIFT);
+    const uintptr_t end = ((addr+size-1)>>DYNAMAP_SHIFT);
+    for (uintptr_t i=idx; i<=end; ++i) {
+        #ifdef DYNAREC
+        uint32_t dyn;
+        do {
+            dyn=arm_lock_read_d(&my_context->memprot[i])&PROT_DYNAREC;
+        } while(arm_lock_write_d(&my_context->memprot[i], prot|dyn));
+        if(dyn && (prot&PROT_WRITE))    // need to remove the write protection from this block
+            mprotect((void*)(i<<DYNAMAP_SHIFT), 1<<DYNAMAP_SHIFT, prot&~PROT_WRITE);
+        #else
+        uint32_t dyn=(my_context->memprot[i]&PROT_DYNAREC);
+        if(dyn && (prot&PROT_WRITE))    // need to remove the write protection from this block
+            mprotect((void*)(i<<DYNAMAP_SHIFT), 1<<DYNAMAP_SHIFT, prot&~PROT_WRITE);
+        my_context->memprot[i] = prot|dyn;
+        #endif
+    }
+}
+
+uint32_t getProtection(uintptr_t addr)
+{
+    const uintptr_t idx = (addr>>DYNAMAP_SHIFT);
+    return my_context->memprot[idx];
+}
+
+EXPORTDYN
+void initAllHelpers(box86context_t* context)
+{
+    static int inited = 0;
+    if(inited)
+        return;
+    my_context = context;
+    init_pthread_helper();
+    init_signal_helper(context);
+    #ifdef DYNAREC
+    if(box86_dynarec)
+        DynablockEmuMarker(context);
+    #endif
+    inited = 1;
+}
+
+EXPORTDYN
+void finiAllHelpers(box86context_t* context)
+{
+    static int finied = 0;
+    if(finied)
+        return;
+    fini_pthread_helper(context);
+    fini_signal_helper();
+    cleanAlternate();
+    fini_custommem_helper(context);
+    finied = 1;
+}
+
 void x86Syscall(x86emu_t *emu);

 /// maxval not inclusive
@@ -66,11 +129,11 @@ int getrand(int maxval)
 {
    if(maxval<1024) {
        return ((random()&0x7fff)*maxval)/0x7fff;
-    } else {
+    } 
        uint64_t r = random();
        r = (r*maxval) / RAND_MAX;
        return r;
-    }
+
 }

 void free_tlsdatasize(void* p)
@@ -82,14 +145,31 @@ void free_tlsdatasize(void* p)
    free(p);
 }

+EXPORTDYN
 box86context_t *NewBox86Context(int argc)
 {
+#ifdef BUILD_DYNAMIC
+    if(my_context) {
+        ++my_context->count;
+        return my_context;
+    }
+#endif
    // init and put default values
-    box86context_t *context = (box86context_t*)calloc(1, sizeof(box86context_t));
+    box86context_t *context = my_context = (box86context_t*)calloc(1, sizeof(box86context_t));

+#ifdef BUILD_LIB
+    context->deferedInit = 0;
+#else
    context->deferedInit = 1;
+#endif
+    context->sel_serial = 1;

-    context->maplib = NewLibrarian(context);
+    init_custommem_helper(context);
+
+    context->memprot = (uint32_t*)calloc(DYNAMAP_SIZE, sizeof(uint32_t));
+
+    context->maplib = NewLibrarian(context, 1);
+    context->local_maplib = NewLibrarian(context, 1);
    context->system = NewBridge();
    // create vsyscall
    context->vsyscall = AddBridge(context->system, vFv, x86Syscall, 0);
@@ -100,132 +180,147 @@ box86context_t *NewBox86Context(int argc)
 #endif
    context->dlprivate = NewDLPrivate();

-    context->callbacks = NewCallbackList();
-
    context->argc = argc;
    context->argv = (char**)calloc(context->argc+1, sizeof(char*));

    pthread_mutex_init(&context->mutex_once, NULL);
    pthread_mutex_init(&context->mutex_once2, NULL);
    pthread_mutex_init(&context->mutex_trace, NULL);
+#ifndef DYNAREC
    pthread_mutex_init(&context->mutex_lock, NULL);
-
+#else
+    pthread_mutex_init(&context->mutex_dyndump, NULL);
+#endif
+    pthread_mutex_init(&context->mutex_tls, NULL);
+    pthread_mutex_init(&context->mutex_thread, NULL);
    pthread_key_create(&context->tlskey, free_tlsdatasize);

-#ifdef DYNAREC
-    pthread_mutex_init(&context->mutex_blocks, NULL);
-    pthread_mutex_init(&context->mutex_mmap, NULL);
-    context->dynablocks = NewDynablockList(0, 0, 0);
-#endif
    InitFTSMap(context);

    for (int i=0; i<4; ++i) context->canary[i] = 1 +  getrand(255);
    context->canary[getrand(4)] = 0;
    printf_log(LOG_DEBUG, "Setting up canary (for Stack protector) at GS:0x14, value:%08X\n", *(uint32_t*)context->canary);

+    initAllHelpers(context);
+
    return context;
 }

+EXPORTDYN
 void FreeBox86Context(box86context_t** context)
 {
+#ifdef BUILD_DYNAMIC
+    if(--(*context)->count)
+        return;
+#endif
    if(!context)
        return;
    
    if(--(*context)->forked >= 0)
        return;

-    FreeFTSMap(*context);
+    box86context_t* ctx = *context;   // local copy to do the cleanning

-    if((*context)->maplib)
-        FreeLibrarian(&(*context)->maplib);
-
-#ifdef DYNAREC
-    dynarec_log(LOG_INFO, "Free global Dynarecblocks\n");
-    if((*context)->dynablocks)
-        FreeDynablockList(&(*context)->dynablocks);
-    for (int i=0; i<(*context)->mmapsize; ++i)
-        if((*context)->mmaplist[i].block)
-            munmap((*context)->mmaplist[i].block, MMAPSIZE);
-    free((*context)->mmaplist);
-    pthread_mutex_destroy(&(*context)->mutex_blocks);
-    pthread_mutex_destroy(&(*context)->mutex_mmap);
-#endif
-    
-    if((*context)->emu)
-        FreeX86Emu(&(*context)->emu);
-
-    FreeCollection(&(*context)->box86_path);
-    FreeCollection(&(*context)->box86_ld_lib);
-    FreeCollection(&(*context)->box86_emulated_libs);
-    if((*context)->zydis)
-        DeleteX86Trace(*context);
-
-    if((*context)->deferedInitList)
-        free((*context)->deferedInitList);
-
-#ifndef BUILD_LIB
-    if((*context)->box86lib)
-        dlclose((*context)->box86lib);
-#endif
-
-    FreeDLPrivate(&(*context)->dlprivate);
-
-    for(int i=0; i<(*context)->argc; ++i)
-        free((*context)->argv[i]);
-    free((*context)->argv);
-    
-    for (int i=0; i<(*context)->envc; ++i)
-        free((*context)->envv[i]);
-    free((*context)->envv);
-
-    for(int i=0; i<(*context)->elfsize; ++i) {
-        FreeElfHeader(&(*context)->elfs[i]);
+    for(int i=0; i<ctx->elfsize; ++i) {
+        FreeElfHeader(&ctx->elfs[i]);
    }
-    free((*context)->elfs);
+    free(ctx->elfs);

-    free((*context)->stack);
+    FreeFTSMap(ctx);

-    free((*context)->fullpath);
-    free((*context)->box86path);
+    if(ctx->maplib)
+        FreeLibrarian(&ctx->maplib);
+    if(ctx->local_maplib)
+        FreeLibrarian(&ctx->local_maplib);

-    FreeBridge(&(*context)->system);
+    FreeCollection(&ctx->box86_path);
+    FreeCollection(&ctx->box86_ld_lib);
+    FreeCollection(&ctx->box86_emulated_libs);
+    // stop trace now
+    if(ctx->dec)
+        DeleteX86TraceDecoder(&ctx->dec);
+    if(ctx->zydis)
+        DeleteX86Trace(ctx);

-    if((*context)->glwrappers)
-        freeProcWrapper(&(*context)->glwrappers);
-    if((*context)->alwrappers)
-        freeProcWrapper(&(*context)->alwrappers);
+    if(ctx->deferedInitList)
+        free(ctx->deferedInitList);

-    FreeCallbackList(&(*context)->callbacks);
+    free(ctx->argv);
+    
+    for (int i=0; i<ctx->envc; ++i)
+        free(ctx->envv[i]);
+    free(ctx->envv);

-    void* ptr;
-    if ((ptr = pthread_getspecific((*context)->tlskey)) != NULL) {
-        free_tlsdatasize(ptr);
-        pthread_setspecific((*context)->tlskey, NULL);
-    }
-    pthread_key_delete((*context)->tlskey);
-
-    if((*context)->tlsdata)
-        free((*context)->tlsdata);
-
-    pthread_mutex_destroy(&(*context)->mutex_once);
-    pthread_mutex_destroy(&(*context)->mutex_once2);
-    pthread_mutex_destroy(&(*context)->mutex_trace);
-    pthread_mutex_destroy(&(*context)->mutex_lock);
-
-    if((*context)->atfork_sz) {
-        free((*context)->atforks);
-        (*context)->atforks = NULL;
-        (*context)->atfork_sz = (*context)->atfork_cap = 0;
+    if(ctx->atfork_sz) {
+        free(ctx->atforks);
+        ctx->atforks = NULL;
+        ctx->atfork_sz = ctx->atfork_cap = 0;
    }

    for(int i=0; i<MAX_SIGNAL; ++i)
-        if((*context)->signals[i]!=0 && (*context)->signals[i]!=1) {
+        if(ctx->signals[i]!=0 && ctx->signals[i]!=1) {
            signal(i, SIG_DFL);
        }

+    *context = NULL;                // bye bye my_context

-    free(*context);
-    *context = NULL;
+    CleanStackSize(ctx);
+
+#ifndef BUILD_LIB
+    if(ctx->box86lib)
+        dlclose(ctx->box86lib);
+#endif
+
+    FreeDLPrivate(&ctx->dlprivate);
+
+    free(ctx->stack);
+
+    free(ctx->fullpath);
+    free(ctx->box86path);
+
+    FreeBridge(&ctx->system);
+
+    freeGLProcWrapper(ctx);
+    freeALProcWrapper(ctx);
+
+    void* ptr;
+    if ((ptr = pthread_getspecific(ctx->tlskey)) != NULL) {
+        free_tlsdatasize(ptr);
+        pthread_setspecific(ctx->tlskey, NULL);
+    }
+    pthread_key_delete(ctx->tlskey);
+
+    if(ctx->tlsdata)
+        free(ctx->tlsdata);
+
+    for(int i=0; i<3; ++i) {
+        if(ctx->segtls[i].present) {
+            // key content not handled by box86, so not doing anything with it
+            pthread_key_delete(ctx->segtls[i].key);
+        }
+    }
+
+    pthread_mutex_destroy(&ctx->mutex_once);
+    pthread_mutex_destroy(&ctx->mutex_once2);
+    pthread_mutex_destroy(&ctx->mutex_trace);
+#ifndef DYNAREC
+    pthread_mutex_destroy(&ctx->mutex_lock);
+#else
+    pthread_mutex_destroy(&ctx->mutex_dyndump);
+#endif
+    pthread_mutex_destroy(&ctx->mutex_tls);
+    pthread_mutex_destroy(&ctx->mutex_thread);
+    free(ctx->memprot);
+    ctx->memprot = NULL;
+
+    free_neededlib(&ctx->neededlibs);
+
+    if(ctx->emu_sig)
+        FreeX86Emu(&ctx->emu_sig);
+
+    finiAllHelpers(ctx);
+
+    free(ctx);
 }

 int AddElfHeader(box86context_t* ctx, elfheader_t* head) {
@@ -242,7 +337,39 @@ int AddElfHeader(box86context_t* ctx, elfheader_t* head) {
 }

 int AddTLSPartition(box86context_t* context, int tlssize) {
+    int oldsize = context->tlssize;
    context->tlssize += tlssize;
    context->tlsdata = realloc(context->tlsdata, context->tlssize);
+    memmove(context->tlsdata+tlssize, context->tlsdata, oldsize);   // move to the top, using memmove as regions will probably overlap
+    memset(context->tlsdata, 0, tlssize);           // fill new space with 0 (not mandatory)
+    // clean GS segment for current emu
+    if(my_context) {
+        ResetSegmentsCache(thread_get_emu());
+        if(!(++context->sel_serial))
+            ++context->sel_serial;
+    }
+
    return -context->tlssize;   // negative offset
-}
+}
+
+void add_neededlib(needed_libs_t* needed, library_t* lib)
+{
+    if(!needed)
+        return;
+    if(needed->size == needed->cap) {
+        needed->cap += 8;
+        needed->libs = (library_t**)realloc(needed->libs, needed->cap*sizeof(library_t*));
+    }
+    needed->libs[needed->size++] = lib;
+}
+
+void free_neededlib(needed_libs_t* needed)
+{
+    if(!needed)
+        return;
+    needed->cap = 0;
+    needed->size = 0;
+    if(needed->libs)
+        free(needed->libs);
+    needed->libs = NULL;
+}
@@ -2,7 +2,7 @@
 #define __BOX86_VERSION_H_

 #define BOX86_MAJOR 0
-#define BOX86_MINOR 1
+#define BOX86_MINOR 2
 #define BOX86_REVISION 0

 #endif //__BOX86_VERSION_H_
@@ -0,0 +1,27 @@
+#include <stdio.h>
+#include "debug.h"
+#include "box86version.h"
+#ifdef NOGIT
+#define GITREV "nogit"
+#else
+#include "git_head.h"
+#endif
+
+void PrintBox86Version()
+{
+    printf("Box86%s%s v%d.%d.%d %s built on %s %s\n", 
+    #ifdef HAVE_TRACE
+        " with trace",
+    #else
+        "",
+    #endif
+    #ifdef DYNAREC
+        " with Dynarec",
+    #else
+        "",
+    #endif
+        BOX86_MAJOR, BOX86_MINOR, BOX86_REVISION,
+        GITREV,
+        __DATE__, __TIME__);
+}
+
@@ -0,0 +1,6 @@
+#ifndef __BUILD_INFO_H__
+#define __BUILD_INFO_H__
+
+void PrintBox86Version();
+
+#endif //__BUILD_INFO_H__
@@ -0,0 +1,530 @@
+#define _GNU_SOURCE         /* See feature_test_macros(7) */
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <dlfcn.h>
+#include <signal.h>
+
+#include "box86context.h"
+#include "elfloader.h"
+#include "debug.h"
+#include "x86trace.h"
+#include "x86emu.h"
+#include "librarian.h"
+#include "bridge.h"
+#include "library.h"
+#include "callback.h"
+#include "wrapper.h"
+#include "myfts.h"
+#include "threads.h"
+#include "x86trace.h"
+#include "signals.h"
+#include <sys/mman.h>
+#include "custommem.h"
+#ifdef DYNAREC
+#include "dynablock.h"
+#include "dynarec/arm_lock_helper.h"
+#include "khash.h"
+
+
+// init inside dynablocks.c
+KHASH_MAP_INIT_INT(dynablocks, dynablock_t*)
+static dynablocklist_t**   dynmap;     // 4G of memory mapped by 4K block
+static pthread_mutex_t     mutex_mmap;
+static mmaplist_t          *mmaplist;
+static int                 mmapsize;
+static kh_dynablocks_t     *dblist_oversized;      // store the list of oversized dynablocks (normal sized are inside mmaplist)
+#endif
+
+typedef struct blocklist_s {
+    void*               block;
+    int                 maxfree;
+    size_t              size;
+} blocklist_t;
+
+#define MMAPSIZE (256*1024)      // allocate 256kb sized blocks
+
+static pthread_mutex_t     mutex_blocks = PTHREAD_MUTEX_INITIALIZER;
+static int                 n_blocks = 0;       // number of blocks for custom malloc
+static blocklist_t*        p_blocks = NULL;    // actual blocks for custom malloc
+
+typedef union mark_s {
+    struct {
+        unsigned int    fill:1;
+        unsigned int    size:31;
+    };
+    uint32_t            x32;
+} mark_t;
+typedef struct blockmark_s {
+    mark_t  prev;
+    mark_t  next;
+} blockmark_t;
+
+
+// get first subblock free in block, stating at start (from block). return NULL if no block, else first subblock free (mark included), filling size
+static void* getFirstBlock(void* block, int maxsize, int* size)
+{
+    // get start of block
+    blockmark_t *m = (blockmark_t*)block;
+    while(m->next.x32) {    // while there is a subblock
+        if(!m->next.fill && m->next.size>=maxsize+sizeof(blockmark_t)) {
+            *size = m->next.size;
+            return m;
+        }
+        m = (blockmark_t*)((uintptr_t)m + m->next.size);
+    }
+
+    return NULL;
+}
+
+static int getMaxFreeBlock(void* block, size_t block_size)
+{
+    // get start of block
+    blockmark_t *m = (blockmark_t*)((uintptr_t)block+block_size-sizeof(blockmark_t)); // styart with the end
+    int maxsize = 0;
+    while(m->prev.x32) {    // while there is a subblock
+        if(!m->prev.fill && m->prev.size>maxsize) {
+            maxsize = m->prev.size;
+            if((uintptr_t)block+maxsize>(uintptr_t)m)
+                return maxsize; // no block large enough left...
+        }
+        m = (blockmark_t*)((uintptr_t)m - m->prev.size);
+    }
+    return maxsize;
+}
+
+static void* allocBlock(void* block, void *sub, int size)
+{
+    blockmark_t *s = (blockmark_t*)sub;
+    blockmark_t *n = (blockmark_t*)((uintptr_t)s + s->next.size);
+
+    s->next.fill = 1;
+    s->next.size = size+sizeof(blockmark_t);
+    blockmark_t *m = (blockmark_t*)((uintptr_t)s + s->next.size);   // this is new n
+    m->prev.fill = 1;
+    m->prev.size = s->next.size;
+    if(n!=m) {
+        // new mark
+        m->prev.fill = 1;
+        m->prev.size = s->next.size;
+        m->next.fill = 0;
+        m->next.size = (uintptr_t)n - (uintptr_t)m;
+        n->prev.fill = 0;
+        n->prev.size = m->next.size;
+    }
+
+    return (void*)((uintptr_t)sub + sizeof(blockmark_t));
+}
+static void freeBlock(void *block, void* sub)
+{
+    blockmark_t *m = (blockmark_t*)block;
+    blockmark_t *s = (blockmark_t*)sub;
+    blockmark_t *n = (blockmark_t*)((uintptr_t)s + s->next.size);
+    if(block!=sub)
+        m = (blockmark_t*)((uintptr_t)s - s->prev.size);
+    s->next.fill = 0;
+    n->prev.fill = 0;
+    // check if merge with previous
+    if (s->prev.x32 && !s->prev.fill) {
+        // remove s...
+        m->next.size += s->next.size;
+        n->prev.size = m->next.size;
+        s = m;
+    }
+    // check if merge with next
+    if(n->next.x32 && !n->next.fill) {
+        blockmark_t *n2 = (blockmark_t*)((uintptr_t)n + n->next.size);
+        //remove n
+        s->next.size += n->next.size;
+        n2->prev.size = s->next.size;
+    }
+}
+// return 1 if block has been expanded to new size, 0 if not
+static int expandBlock(void* block, void* sub, int newsize)
+{
+    newsize = (newsize+3)&~3;
+    blockmark_t *s = (blockmark_t*)sub;
+    blockmark_t *n = (blockmark_t*)((uintptr_t)s + s->next.size);
+    if(s->next.fill)
+        return 0;   // next block is filled
+    if(s->next.size + n->next.size < newsize)
+        return 0;   // free space too short
+    // ok, doing the alloc!
+    s->next.size = newsize+sizeof(blockmark_t);
+    blockmark_t *m = (blockmark_t*)((uintptr_t)s + s->next.size);   // this is new n
+    m->prev.fill = 1;
+    m->prev.size = s->next.size;
+    if(n!=m) {
+        // new mark
+        m->prev.fill = 1;
+        m->prev.size = s->next.size;
+        m->next.fill = 0;
+        m->next.size = (uintptr_t)n - (uintptr_t)m;
+        n->prev.fill = 0;
+        n->prev.size = m->next.size;
+    }
+    return 1;
+}
+// return size of block
+static int sizeBlock(void* sub)
+{
+    blockmark_t *s = (blockmark_t*)sub;
+    return s->next.size;
+}
+
+void* customMalloc(size_t size)
+{
+    // look for free space
+    void* sub = NULL;
+    pthread_mutex_lock(&mutex_blocks);
+    for(int i=0; i<n_blocks; ++i) {
+        if(p_blocks[i].maxfree>=size) {
+            int rsize = 0;
+            sub = getFirstBlock(p_blocks[i].block, size, &rsize);
+            if(sub) {
+                void* ret = allocBlock(p_blocks[i].block, sub, size);
+                if(rsize==p_blocks[i].maxfree)
+                    p_blocks[i].maxfree = getMaxFreeBlock(p_blocks[i].block, p_blocks[i].size);
+                pthread_mutex_unlock(&mutex_blocks);
+                return ret;
+            }
+        }
+    }
+    // add a new block
+    int i = n_blocks++;
+    p_blocks = (blocklist_t*)realloc(p_blocks, n_blocks*sizeof(blocklist_t));
+    size_t allocsize = MMAPSIZE;
+    if(size+2*sizeof(blockmark_t)>allocsize)
+        allocsize = size+2*sizeof(blockmark_t);
+    void* p = calloc(1, allocsize);
+    p_blocks[i].block = p;
+    p_blocks[i].size = allocsize;
+    // setup marks
+    blockmark_t* m = (blockmark_t*)p;
+    m->prev.x32 = 0;
+    m->next.fill = 0;
+    m->next.size = allocsize-sizeof(blockmark_t);
+    m = (blockmark_t*)(p+allocsize-sizeof(blockmark_t));
+    m->next.x32 = 0;
+    m->prev.fill = 0;
+    m->prev.size = allocsize-sizeof(blockmark_t);
+    // alloc 1st block
+    void* ret  = allocBlock(p_blocks[i].block, p, size);
+    p_blocks[i].maxfree = getMaxFreeBlock(p_blocks[i].block, p_blocks[i].size);
+    pthread_mutex_unlock(&mutex_blocks);
+    return ret;
+}
+void* customCalloc(size_t n, size_t size)
+{
+    size_t newsize = n*size;
+    void* ret = customMalloc(newsize);
+    memset(ret, 0, newsize);
+    return ret;
+}
+void* customRealloc(void* p, size_t size)
+{
+    if(!p)
+        return customMalloc(size);
+    uintptr_t addr = (uintptr_t)p;
+    pthread_mutex_lock(&mutex_blocks);
+    for(int i=0; i<n_blocks; ++i) {
+        if ((addr>(uintptr_t)p_blocks[i].block) 
+         && (addr<((uintptr_t)p_blocks[i].block+p_blocks[i].size))) {
+            void* sub = (void*)(addr-sizeof(blockmark_t));
+            if(expandBlock(p_blocks[i].block, sub, size)) {
+                p_blocks[i].maxfree = getMaxFreeBlock(p_blocks[i].block, p_blocks[i].size);
+                pthread_mutex_unlock(&mutex_blocks);
+                return p;
+            }
+                pthread_mutex_unlock(&mutex_blocks);
+                void* newp = customMalloc(size);
+                memcpy(newp, p, sizeBlock(sub));
+                customFree(p);
+                return newp;
+            
+        }
+    }
+    pthread_mutex_unlock(&mutex_blocks);
+    if(n_blocks)
+        dynarec_log(LOG_NONE, "Warning, block %p not found in p_blocks for Realloc, Malloc'ng again without free\n", (void*)addr);
+    return customMalloc(size);
+}
+void customFree(void* p)
+{
+    if(!p)
+        return;
+    uintptr_t addr = (uintptr_t)p;
+    pthread_mutex_lock(&mutex_blocks);
+    for(int i=0; i<n_blocks; ++i) {
+        if ((addr>(uintptr_t)p_blocks[i].block) 
+         && (addr<((uintptr_t)p_blocks[i].block+p_blocks[i].size))) {
+            void* sub = (void*)(addr-sizeof(blockmark_t));
+            freeBlock(p_blocks[i].block, sub);
+            p_blocks[i].maxfree = getMaxFreeBlock(p_blocks[i].block, p_blocks[i].size);
+            pthread_mutex_unlock(&mutex_blocks);
+            return;
+        }
+    }
+    pthread_mutex_unlock(&mutex_blocks);
+    if(n_blocks)
+        dynarec_log(LOG_NONE, "Warning, block %p not found in p_blocks for Free\n", (void*)addr);
+}
+
+#ifdef DYNAREC
+typedef struct mmaplist_s {
+    void*               block;
+    int                 maxfree;
+    size_t              size;
+    kh_dynablocks_t*    dblist;
+} mmaplist_t;
+
+uintptr_t FindFreeDynarecMap(dynablock_t* db, int size)
+{
+    // look for free space
+    void* sub = NULL;
+    for(int i=0; i<mmapsize; ++i) {
+        if(mmaplist[i].maxfree>=size) {
+            int rsize = 0;
+            sub = getFirstBlock(mmaplist[i].block, size, &rsize);
+            if(sub) {
+                uintptr_t ret = (uintptr_t)allocBlock(mmaplist[i].block, sub, size);
+                if(rsize==mmaplist[i].maxfree)
+                    mmaplist[i].maxfree = getMaxFreeBlock(mmaplist[i].block, mmaplist[i].size);
+                kh_dynablocks_t *blocks = mmaplist[i].dblist;
+                if(!blocks) {
+                    blocks = mmaplist[i].dblist = kh_init(dynablocks);
+                    kh_resize(dynablocks, blocks, 64);
+                }
+                khint_t k;
+                int r;
+                k = kh_put(dynablocks, blocks, (uintptr_t)db, &r);
+                kh_value(blocks, k) = db;
+                return ret;
+            }
+        }
+    }
+    return 0;
+}
+
+uintptr_t AddNewDynarecMap(dynablock_t* db, int size)
+{
+    int i = mmapsize++;    // yeah, useful post incrementation
+    dynarec_log(LOG_DEBUG, "Ask for DynaRec Block Alloc #%d\n", mmapsize);
+    mmaplist = (mmaplist_t*)realloc(mmaplist, mmapsize*sizeof(mmaplist_t));
+    void *p = NULL;
+    if(posix_memalign(&p, box86_pagesize, MMAPSIZE)) {
+        dynarec_log(LOG_INFO, "Cannot create memory map of %d byte for dynarec block #%d\n", MMAPSIZE, i);
+        --mmapsize;
+        return 0;
+    }
+    mprotect(p, MMAPSIZE, PROT_READ | PROT_WRITE | PROT_EXEC);
+    updateProtection((uintptr_t)p, MMAPSIZE, PROT_READ | PROT_WRITE | PROT_EXEC);
+
+    mmaplist[i].block = p;
+    mmaplist[i].size = MMAPSIZE;
+    // setup marks
+    blockmark_t* m = (blockmark_t*)p;
+    m->prev.x32 = 0;
+    m->next.fill = 0;
+    m->next.size = MMAPSIZE-sizeof(blockmark_t);
+    m = (blockmark_t*)(p+MMAPSIZE-sizeof(blockmark_t));
+    m->next.x32 = 0;
+    m->prev.fill = 0;
+    m->prev.size = MMAPSIZE-sizeof(blockmark_t);
+    // alloc 1st block
+    uintptr_t sub  = (uintptr_t)allocBlock(mmaplist[i].block, p, size);
+    mmaplist[i].maxfree = getMaxFreeBlock(mmaplist[i].block, mmaplist[i].size);
+    kh_dynablocks_t *blocks = mmaplist[i].dblist = kh_init(dynablocks);
+    kh_resize(dynablocks, blocks, 64);
+    khint_t k;
+    int ret;
+    k = kh_put(dynablocks, blocks, (uintptr_t)db, &ret);
+    kh_value(blocks, k) = db;
+    return sub;
+}
+
+void ActuallyFreeDynarecMap(dynablock_t* db, uintptr_t addr, int size)
+{
+    if(!addr || !size)
+        return;
+    for(int i=0; i<mmapsize; ++i) {
+        if ((addr>(uintptr_t)mmaplist[i].block) 
+         && (addr<((uintptr_t)mmaplist[i].block+mmaplist[i].size))) {
+            void* sub = (void*)(addr-sizeof(blockmark_t));
+            freeBlock(mmaplist[i].block, sub);
+            mmaplist[i].maxfree = getMaxFreeBlock(mmaplist[i].block, mmaplist[i].size);
+            kh_dynablocks_t *blocks = mmaplist[i].dblist;
+            if(blocks) {
+                khint_t k = kh_get(dynablocks, blocks, (uintptr_t)db);
+                if(k!=kh_end(blocks))
+                    kh_del(dynablocks, blocks, k);
+            }
+            return;
+        }
+    }
+    if(mmapsize)
+        dynarec_log(LOG_NONE, "Warning, block %p (size %d) not found in mmaplist for Free\n", (void*)addr, size);
+}
+
+dynablock_t* FindDynablockFromNativeAddress(void* addr)
+{
+    // look in actual list
+    for(int i=0; i<mmapsize; ++i) {
+        if ((uintptr_t)addr>=(uintptr_t)mmaplist[i].block 
+        && ((uintptr_t)addr<(uintptr_t)mmaplist[i].block+mmaplist[i].size))
+            return FindDynablockDynablocklist(addr, mmaplist[i].dblist);
+    }
+    // look in oversized
+    return FindDynablockDynablocklist(addr, dblist_oversized);
+}
+
+uintptr_t AllocDynarecMap(dynablock_t* db, int size)
+{
+    if(!size)
+        return 0;
+    if(size>MMAPSIZE-2*sizeof(blockmark_t)) {
+        void *p = NULL;
+        if(posix_memalign(&p, box86_pagesize, size)) {
+            dynarec_log(LOG_INFO, "Cannot create dynamic map of %d bytes\n", size);
+            return 0;
+        }
+        mprotect(p, size, PROT_READ | PROT_WRITE | PROT_EXEC);
+        updateProtection((uintptr_t)p, size, PROT_READ | PROT_WRITE | PROT_EXEC);
+        kh_dynablocks_t *blocks = dblist_oversized;
+        if(!blocks) {
+            blocks = dblist_oversized = kh_init(dynablocks);
+            kh_resize(dynablocks, blocks, 64);
+        }
+        khint_t k;
+        int ret;
+        k = kh_put(dynablocks, blocks, (uintptr_t)db, &ret);
+        kh_value(blocks, k) = db;
+        return (uintptr_t)p;
+    }
+    
+    if(pthread_mutex_trylock(&mutex_mmap)) {
+        sched_yield();  // give it a chance
+        if(pthread_mutex_trylock(&mutex_mmap))
+            return 0;   // cannot lock, baillout
+    }
+
+    uintptr_t ret = FindFreeDynarecMap(db, size);
+    if(!ret)
+        ret = AddNewDynarecMap(db, size);
+
+    pthread_mutex_unlock(&mutex_mmap);
+
+    return ret;
+}
+
+void FreeDynarecMap(dynablock_t* db, uintptr_t addr, uint32_t size)
+{
+    if(size>MMAPSIZE) {
+        munmap((void*)addr, size);
+        kh_dynablocks_t *blocks = dblist_oversized;
+        if(blocks) {
+            khint_t k = kh_get(dynablocks, blocks, (uintptr_t)db);
+            if(k!=kh_end(blocks))
+                kh_del(dynablocks, blocks, k);
+        }
+        return;
+    }
+    pthread_mutex_lock(&mutex_mmap);
+    ActuallyFreeDynarecMap(db, addr, size);
+    pthread_mutex_unlock(&mutex_mmap);
+}
+
+dynablocklist_t* getDB(uintptr_t idx)
+{
+    return dynmap[idx];
+}
+
+// each dynmap is 64k of size
+
+void addDBFromAddressRange(uintptr_t addr, uintptr_t size, int nolinker)
+{
+    dynarec_log(LOG_DEBUG, "addDBFromAddressRange %p -> %p\n", (void*)addr, (void*)(addr+size-1));
+    uintptr_t idx = (addr>>DYNAMAP_SHIFT);
+    uintptr_t end = ((addr+size-1)>>DYNAMAP_SHIFT);
+    for (uintptr_t i=idx; i<=end; ++i) {
+        if(!dynmap[i]) {
+            dynmap[i] = NewDynablockList(i<<DYNAMAP_SHIFT, 1<<DYNAMAP_SHIFT, nolinker, 0);
+        }
+    }
+}
+
+void cleanDBFromAddressRange(uintptr_t addr, uintptr_t size, int destroy)
+{
+    dynarec_log(LOG_DEBUG, "cleanDBFromAddressRange %p -> %p %s\n", (void*)addr, (void*)(addr+size-1), destroy?"destroy":"mark");
+    uintptr_t idx = (addr>box86_dynarec_largest && !destroy)?((addr-box86_dynarec_largest)>>DYNAMAP_SHIFT):(addr>>DYNAMAP_SHIFT);
+    uintptr_t end = ((addr+size-1)>>DYNAMAP_SHIFT);
+    for (uintptr_t i=idx; i<=end; ++i) {
+        dynablocklist_t* dblist = dynmap[i];
+        if(dblist) {
+            uintptr_t startdb = StartDynablockList(dblist);
+            uintptr_t enddb = EndDynablockList(dblist);
+            uintptr_t startaddr = addr;
+            if(startaddr<startdb) startaddr = startdb;
+            uintptr_t endaddr = addr + size - 1;
+            if(endaddr>enddb) endaddr = enddb;
+            if(destroy)
+                FreeRangeDynablock(dblist, startaddr, endaddr-startaddr+1);
+            else
+                MarkRangeDynablock(dblist, startaddr, endaddr-startaddr+1);
+        }
+    }
+}
+#endif
+
+void init_custommem_helper(box86context_t* ctx)
+{
+#ifdef DYNAREC
+    if(dynmap) // already initialized
+        return;
+    pthread_mutex_init(&mutex_mmap, NULL);
+    dynmap = (dynablocklist_t**)calloc(DYNAMAP_SIZE, sizeof(dynablocklist_t*));
+#endif
+}
+
+void fini_custommem_helper(box86context_t *ctx)
+{
+#ifdef DYNAREC
+    dynarec_log(LOG_DEBUG, "Free global Dynarecblocks\n");
+    for (int i=0; i<mmapsize; ++i) {
+        if(mmaplist[i].block)
+            free(mmaplist[i].block);
+        if(mmaplist[i].dblist) {
+            kh_destroy(dynablocks, mmaplist[i].dblist);
+            mmaplist[i].dblist = NULL;
+        }
+    }
+    if(dblist_oversized) {
+        kh_destroy(dynablocks, dblist_oversized);
+        dblist_oversized = NULL;
+    }
+    mmapsize = 0;
+    dynarec_log(LOG_DEBUG, "Free dynamic Dynarecblocks\n");
+    uintptr_t idx = 0;
+    uintptr_t end = ((0xFFFFFFFF)>>DYNAMAP_SHIFT);
+    for (uintptr_t i=idx; i<=end; ++i) {
+        dynablocklist_t* dblist = dynmap[i];
+        if(dblist) {
+            uintptr_t startdb = StartDynablockList(dblist);
+            uintptr_t enddb = EndDynablockList(dblist);
+            uintptr_t startaddr = 0;
+            if(startaddr<startdb) startaddr = startdb;
+            uintptr_t endaddr = 0xFFFFFFFF;
+            if(endaddr>enddb) endaddr = enddb;
+            FreeRangeDynablock(dblist, startaddr, endaddr-startaddr+1);
+        }
+    }
+    pthread_mutex_destroy(&mutex_mmap);
+    free(mmaplist);
+    free(dynmap);
+    dynmap = NULL;
+#endif
+    for(int i=0; i<n_blocks; ++i)
+        free(p_blocks[i].block);
+    free(p_blocks);
+    pthread_mutex_destroy(&mutex_blocks);
+}
@@ -21,28 +21,29 @@ Op is 20-27
 #define xEBP    9
 #define xESI    10
 #define xEDI    11
-#define xEIP    12
+#define xFlags  12
+#define xEIP    14
 // scratch registers
 #define x1      1
 #define x2      2
 #define x3      3
-#define x12     12
+#define x14     14
 // emu is r0
 #define xEmu    0
 // ARM SP is r13
 #define xSP     13      

 // barel roll operations (4 possibles)
-#define brLSL(i, r) (0<<4 | 0<<5 | ((i&31)<<7) | r)
-#define brLSR(i, r) (0<<4 | 1<<5 | ((i&31)<<7) | r)
-#define brASR(i, r) (0<<4 | 2<<5 | ((i&31)<<7) | r)
-#define brROR(i, r) (0<<4 | 3<<5 | ((i&31)<<7) | r)
+#define brLSL(i, r) (0<<4 | 0<<5 | (((i)&31)<<7) | (r))
+#define brLSR(i, r) (0<<4 | 1<<5 | (((i)&31)<<7) | (r))
+#define brASR(i, r) (0<<4 | 2<<5 | (((i)&31)<<7) | (r))
+#define brROR(i, r) (0<<4 | 3<<5 | (((i)&31)<<7) | (r))
 #define brIMM(r)    (abs(r))
 // barel roll with a register
-#define brRLSL(i, r) (1<<4 | 0<<5 | ((i&15)<<8) | r)
-#define brRLSR(i, r) (1<<4 | 1<<5 | ((i&15)<<8) | r)
-#define brRASR(i, r) (1<<4 | 2<<5 | ((i&15)<<8) | r)
-#define brRROR(i, r) (1<<4 | 3<<5 | ((i&15)<<8) | r)
+#define brRLSL(i, r) (1<<4 | 0<<5 | (((i)&15)<<8) | (r))
+#define brRLSR(i, r) (1<<4 | 1<<5 | (((i)&15)<<8) | (r))
+#define brRASR(i, r) (1<<4 | 2<<5 | (((i)&15)<<8) | (r))
+#define brRROR(i, r) (1<<4 | 3<<5 | (((i)&15)<<8) | (r))


 // conditions
@@ -79,12 +80,12 @@ Op is 20-27
 // pseudo insruction: mov reg, #imm with imm a 32bits value
 #define MOV32(dst, imm32)                   \
    MOVW(dst, ((uint32_t)imm32)&0xffff);    \
-    if (((uint32_t)imm32)>>16) {            \
+    if (((uint32_t)(imm32))>>16) {            \
        MOVT(dst, (((uint32_t)imm32)>>16)); }
 // pseudo insruction: mov reg, #imm with imm a 32bits value, fixed size
 #define MOV32_(dst, imm32)                   \
-    MOVW(dst, ((uint32_t)imm32)&0xffff);    \
-    MOVT(dst, (((uint32_t)imm32)>>16))
+    MOVW(dst, ((uint32_t)(imm32))&0xffff);    \
+    MOVT(dst, (((uint32_t)(imm32))>>16))
 // movw.cond dst, #imm16
 #define MOVW_COND(cond, dst, imm16) EMIT(cond | 0x03000000 | ((dst) << 12) | (((imm16) & 0xf000) << 4) | brIMM((imm16) & 0x0fff) )
 // mov dst #imm8 ror imm4*2
@@ -93,46 +94,66 @@ Op is 20-27
 #define MOV_IMM_COND(cond, dst, imm8, rimm4) EMIT(cond | 0x03a00000 | ((dst) << 12) | (imm8) | ((rimm4) << 8) )

 // mov dst, src lsl imm5
-#define MOV_REG_LSL_IMM5(dst, src, imm5) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (0<<4) | (0<<5) | (imm5<<7))
+#define MOV_REG_LSL_IMM5(dst, src, imm5) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (0<<4) | (0<<5) | ((imm5)<<7))
 // mov dst, src lsr imm5
-#define MOV_REG_LSR_IMM5(dst, src, imm5) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (0<<4) | (1<<5) | (imm5<<7))
+#define MOV_REG_LSR_IMM5(dst, src, imm5) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (0<<4) | (1<<5) | ((imm5)<<7))
 // mov dst, src asr imm5
-#define MOV_REG_ASR_IMM5(dst, src, imm5) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (0<<4) | (2<<5) | (imm5<<7))
+#define MOV_REG_ASR_IMM5(dst, src, imm5) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (0<<4) | (2<<5) | ((imm5)<<7))
 // mov dst, src ror imm5
-#define MOV_REG_ROR_IMM5(dst, src, imm5) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (0<<4) | (3<<5) | (imm5<<7))
+#define MOV_REG_ROR_IMM5(dst, src, imm5) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (0<<4) | (3<<5) | ((imm5)<<7))
+// mov.s dst, src lsl imm5
+#define MOVS_REG_LSL_IMM5(dst, src, imm5) EMIT(0xe1b00000 | ((dst) << 12) | (src) | (0<<4) | (0<<5) | ((imm5)<<7))
+// mov.s dst, src lsr imm5
+#define MOVS_REG_LSR_IMM5(dst, src, imm5) EMIT(0xe1b00000 | ((dst) << 12) | (src) | (0<<4) | (1<<5) | ((imm5)<<7))
+// mov.s dst, src asr imm5
+#define MOVS_REG_ASR_IMM5(dst, src, imm5) EMIT(0xe1b00000 | ((dst) << 12) | (src) | (0<<4) | (2<<5) | ((imm5)<<7))
+// mov.s dst, src ror imm5
+#define MOVS_REG_ROR_IMM5(dst, src, imm5) EMIT(0xe1b00000 | ((dst) << 12) | (src) | (0<<4) | (3<<5) | ((imm5)<<7))

 // mov dst, src lsl rs
-#define MOV_REG_LSL_REG(dst, src, rs) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (1<<4) | (0<<5) | (rs<<8))
+#define MOV_REG_LSL_REG(dst, src, rs) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (1<<4) | (0<<5) | ((rs)<<8))
 // mov dst, src lsr rs
-#define MOV_REG_LSR_REG(dst, src, rs) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (1<<4) | (1<<5) | (rs<<8))
+#define MOV_REG_LSR_REG(dst, src, rs) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (1<<4) | (1<<5) | ((rs)<<8))
 // mov dst, src asr rs
-#define MOV_REG_ASR_REG(dst, src, rs) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (1<<4) | (2<<5) | (rs<<8))
+#define MOV_REG_ASR_REG(dst, src, rs) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (1<<4) | (2<<5) | ((rs)<<8))
 // mov dst, src ror rs
-#define MOV_REG_ROR_REG(dst, src, rs) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (1<<4) | (3<<5) | (rs<<8))
+#define MOV_REG_ROR_REG(dst, src, rs) EMIT(0xe1a00000 | ((dst) << 12) | (src) | (1<<4) | (3<<5) | ((rs)<<8))

 // sub dst, src, #(imm8)
 #define SUB_IMM8(dst, src, imm8) \
    EMIT(0xe2400000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
 // sub cond dst, src, #(imm8)
-#define SUB_COND_IMM8(dst, src, imm8) \
+#define SUB_COND_IMM8(cond, dst, src, imm8) \
    EMIT((cond) | 0x02400000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
 // sub.s dst, src, #(imm8)
 #define SUBS_IMM8(dst, src, imm8) \
    EMIT(0xe2500000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
-// add dst, src1, src2, lsl #imm
-#define SUB_REG_LSL_IMM8(dst, src1, src2, imm8) \
-    EMIT(0xe0400000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm8, src2) )
-// add.s dst, src1, src2, lsl #imm
-#define SUBS_REG_LSL_IMM8(dst, src1, src2, imm8) \
-    EMIT(0xe0500000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm8, src2) )
+// sub dst, src1, src2, lsl #imm
+#define SUB_REG_LSL_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe0400000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
+// sub.s dst, src1, src2, lsl #imm
+#define SUBS_REG_LSL_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe0500000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )

 // sbc dst, src, #(imm8)
 #define SBC_IMM8(dst, src, imm8) \
    EMIT(0xe2c00000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
+// sbc.s dst, src, #(imm8)
+#define SBCS_IMM8(dst, src, imm8) \
+    EMIT(0xe2d00000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
+// sbc dst, src1, src2, lsl #imm
+#define SBC_REG_LSL_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe0c00000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
+// sbc.s dst, src1, src2, lsl #imm
+#define SBCS_REG_LSL_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe0d00000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )

 // rsb dst, src, #(imm8)
 #define RSB_IMM8(dst, src, imm8) \
    EMIT(0xe2600000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
+// rsb.s dst, src, #(imm8)
+#define RSBS_IMM8(dst, src, imm8) \
+    EMIT(0xe2700000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
 // rsb cond dst, src, #(imm8)
 #define RSB_COND_IMM8(cond, dst, src, imm8) \
    EMIT((cond) | 0x02600000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
@@ -152,30 +173,56 @@ Op is 20-27
 // and.s dst, src, #(imm8)
 #define ANDS_IMM8(dst, src, imm8) \
    EMIT(0xe2100000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
+// and.s dst, src1, #imm ror rot*2
+#define ANDS_IMM8_ROR(src, imm8, rot) \
+    EMIT(0xe2100000 | ((dst) << 12) | ((src) << 16) | ((rot)<<8) | brIMM(imm8) )
 // add dst, src, #(imm8)
 #define ADD_IMM8(dst, src, imm8) \
    EMIT(0xe2800000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
+// add dst, src, #imm8 ror rot*2
+#define ADD_IMM8_ROR(dst, src, imm8, rot) \
+    EMIT(0xe2800000 | ((dst) << 12) | ((src) << 16) | ((rot)<<8) | brIMM((imm8)) )
 // add.s dst, src, #(imm8)
 #define ADDS_IMM8(dst, src, imm8) \
    EMIT(0xe2900000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
+// add.c dst, src, #(imm8)
+#define ADD_IMM8_cond(cond, dst, src, imm8) \
+    EMIT((cond) | 0x02800000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
 // add dst, src1, src2, lsl #imm
 #define ADD_REG_LSL_IMM5(dst, src1, src2, imm5) \
    EMIT(0xe0800000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
 // add.s dst, src1, src2, lsl #imm
-#define ADDS_REG_LSL_IMM5(dst, src1, src2, imm8) \
+#define ADDS_REG_LSL_IMM5(dst, src1, src2, imm5) \
    EMIT(0xe0900000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
 // add dst, src1, src2, lsr #imm
 #define ADD_REG_LSR_IMM5(dst, src1, src2, imm5) \
    EMIT(0xe0800000 | ((dst) << 12) | ((src1) << 16) | brLSR(imm5, src2) )
+#define ADC_IMM8(dst, src, imm8) \
+    EMIT(0xe2a00000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
+// add.s dst, src, #(imm8)
+#define ADCS_IMM8(dst, src, imm8) \
+    EMIT(0xe2b00000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
+// add dst, src1, src2, lsl #imm
+#define ADC_REG_LSL_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe0a00000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
+// add.s dst, src1, src2, lsl #imm
+#define ADCS_REG_LSL_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe0b00000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
 // cmp.s dst, src1, src2, lsl #imm
 #define CMPS_REG_LSL_IMM5(src1, src2, imm5) \
    EMIT(0xe1500000 | ((0) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
+// cmp.cond.s dst, src1, src2, lsl #imm
+#define CMPS_REG_LSL_IMM5_COND(cond, src1, src2, imm5) \
+    EMIT((cond) | 0x01500000 | ((0) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
+// cmp.s dst, src, #imm
+#define CMPS_IMM8_COND(cond, src, imm8) \
+    EMIT((cond) | 0x03500000 | ((0) << 12) | ((src) << 16) | brIMM(imm8) )
 // cmp.s dst, src, #imm
 #define CMPS_IMM8(src, imm8) \
    EMIT(0xe3500000 | ((0) << 12) | ((src) << 16) | brIMM(imm8) )
 // tst.s dst, src1, src2, lsl #imm
-#define TSTS_REG_LSL_IMM8(src1, src2, imm8) \
-    EMIT(0xe1100000 | ((0) << 12) | ((src1) << 16) | brLSL(imm8, src2) )
+#define TSTS_REG_LSL_IMM5(src1, src2, imm5) \
+    EMIT(0xe1100000 | ((0) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
 // tst.s dst, src1, #imm
 #define TSTS_IMM8(src, imm8) \
    EMIT(0xe3100000 | ((0) << 12) | ((src) << 16) | brIMM(imm8) )
@@ -183,26 +230,42 @@ Op is 20-27
 #define TSTS_IMM8_ROR(src, imm8, rot) \
    EMIT(0xe3100000 | ((0) << 12) | ((src) << 16) | ((rot)<<8) | brIMM(imm8) )
 // orr dst, src1, src2, lsl #imm
-#define ORR_REG_LSL_IMM8(dst, src1, src2, imm8) \
-    EMIT(0xe1800000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm8, src2) )
+#define ORR_REG_LSL_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe1800000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
 // orr.s dst, src1, src2, lsl #imm
-#define ORRS_REG_LSL_IMM8(dst, src1, src2, imm8) \
-    EMIT(0xe1900000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm8, src2) )
+#define ORRS_REG_LSL_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe1900000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
+// orr dst, src1, src2, lsr #imm
+#define ORR_REG_LSR_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe1800000 | ((dst) << 12) | ((src1) << 16) | brLSR(imm5, src2) )
+// orr.s dst, src1, src2, lsr #imm
+#define ORRS_REG_LSR_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe1900000 | ((dst) << 12) | ((src1) << 16) | brLSR(imm5, src2) )
 // orr dst, src1, #imm8
 #define ORR_IMM8(dst, src, imm8, rot) \
    EMIT(0xe3800000 | ((dst) << 12) | ((src) << 16) | ((rot)<<8) | imm8 )
-// orr dst, src1, src2, lsl #rs
+// orr.s dst, src1, #imm8
+#define ORRS_IMM8(dst, src, imm8, rot) \
+    EMIT(0xe3900000 | ((dst) << 12) | ((src) << 16) | ((rot)<<8) | imm8 )
+// orr.cond dst, src1, #imm8
+#define ORR_IMM8_COND(cond, dst, src, imm8, rot) \
+    EMIT((cond) | 0x03800000 | ((dst) << 12) | ((src) << 16) | ((rot)<<8) | imm8 )
+// orr dst, src1, src2, lsl rs
 #define ORR_REG_LSL_REG(dst, src1, src2, rs) \
    EMIT(0xe1800000 | ((dst) << 12) | ((src1) << 16) | brRLSL(rs, src2) )
 // xor dst, src1, src2, lsl #imm
-#define XOR_REG_LSL_IMM8(dst, src1, src2, imm8) \
-    EMIT(0xe0200000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm8, src2) )
+#define XOR_REG_LSL_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe0200000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
 // xor.s dst, src1, src2, lsl #imm
-#define XORS_REG_LSL_IMM8(dst, src1, src2, imm8) \
-    EMIT(0xe0300000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm8, src2) )
+#define XORS_REG_LSL_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe0300000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
+#define XOR_REG_LSL_IMM5_COND(cond, dst, src1, src2, imm5) \
+    EMIT((cond) | 0x00200000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
 // xor dst, src, #(imm8)
 #define XOR_IMM8(dst, src, imm8) \
    EMIT(0xe2200000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
+#define XORS_IMM8(dst, src, imm8) \
+    EMIT(0xe2300000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
 // xor.cond dst, src, #(imm8)
 #define XOR_IMM8_COND(cond, dst, src, imm8) \
    EMIT(cond | 0x02200000 | ((dst) << 12) | ((src) << 16) | brIMM(imm8) )
@@ -213,17 +276,23 @@ Op is 20-27
 #define XOR_REG_LSR_IMM8(dst, src1, src2, imm8) \
    EMIT(0xe0200000 | ((dst) << 12) | ((src1) << 16) | brLSR(imm8, src2) )
 // bic dst, src1, src2, lsl #imm
-#define BIC_REG_LSL_IMM8(dst, src1, src2, imm8) \
-    EMIT(0xe1c00000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm8, src2) )
+#define BIC_REG_LSL_IMM5(dst, src1, src2, imm5) \
+    EMIT(0xe1c00000 | ((dst) << 12) | ((src1) << 16) | brLSL(imm5, src2) )
 // bic dst, src, IMM8
 #define BIC_IMM8(dst, src, imm8, rot) \
    EMIT(0xe3c00000 | ((dst) << 12) | ((src) << 16) | ((rot)<<8) | imm8 )
+// bic.cond dst, src, IMM8
+#define BIC_IMM8_COND(cond, dst, src, imm8, rot) \
+    EMIT((cond) | 0x03c00000 | ((dst) << 12) | ((src) << 16) | ((rot)<<8) | imm8 )
+// bic.s dst, src1, #imm ror rot*2
+#define BICS_IMM8_ROR(dst, src, imm8, rot) \
+    EMIT(0xe3d00000 | ((dst) << 12) | ((src) << 16) | ((rot)<<8) | brIMM(imm8) )
 // bic dst, src1, src2, lsl #imm
 #define BIC_REG_LSL_REG(dst, src1, src2, rs) \
    EMIT(0xe1c00000 | ((dst) << 12) | ((src1) << 16) | brRLSL(rs, src2) )
 // mvn dst, src1, src2, lsl #imm
-#define MVN_REG_LSL_IMM8(dst, rm, imm8) \
-    EMIT(0xe1e00000 | ((dst) << 12) | (0 << 16) | brLSL(imm8, rm) )
+#define MVN_REG_LSL_IMM5(dst, rm, imm5) \
+    EMIT(0xe1e00000 | ((dst) << 12) | (0 << 16) | brLSL(imm5, rm) )
 // mvn dst, src, IMM8
 #define MVN_IMM8(dst, src, imm8, rot) \
    EMIT(0xe3e00000 | ((dst) << 12) | ((src) << 16) | ((rot)<<8) | imm8 )
@@ -234,8 +303,8 @@ Op is 20-27
 #define MVN_REG_LSR_REG(dst, rm, rs) \
    EMIT(0xe1e00000 | ((dst) << 12) | (0 << 16) | (1<<4) | (1<<5) | (rs<<8) | (rm) )
 // mvn with condition dst, src1, src2, lsl #imm
-#define MVN_COND_REG_LSL_IMM8(cond, dst, rm, imm8) \
-    EMIT(cond | 0x01e00000 | ((dst) << 12) | (0 << 16) | brLSL(imm8, rm) )
+#define MVN_COND_REG_LSL_IMM5(cond, dst, rm, imm5) \
+    EMIT(cond | 0x01e00000 | ((dst) << 12) | (0 << 16) | brLSL(imm5, rm) )

 // Single data transfert construction
 #define SDT_REG(Cond, P, U, B, W, L, Rn, Rd, ShiftRm) (Cond | (0b00<<26) | (1<<25) | (P<<24) | (U<<23) | (B<<22) | (U<<23) | (W<<21) | (L<<20) | (Rn<<16) | (Rd<<12) | ShiftRm)
@@ -264,9 +333,15 @@ Op is 20-27
 #define LDRBAI_REG_LSL_IMM5(reg, addr, rm, imm5) EMIT(0xe6d00000 | ((reg) << 12) | ((addr) << 16) | (1<<25) | brLSL(imm5, rm) )
 // ldrd reg, reg+1, [addr, #+/-imm9], reg must be even, reg+1 is implicit
 #define LDRD_IMM8(reg, addr, imm8) EMIT(c__ | 0b000<<25 | 1<<24  | (((imm8)<0)?0:1)<<23 | 1<<22 | 0<<21 | 0<<20 | ((reg) << 12) | ((addr) << 16) | ((abs(imm8))&0xf0)<<(8-4) | (0b1101<<4) | ((abs(imm8))&0x0f) )
+// ldrd reg, reg+1, [addr, +rm], reg must be even, reg+1 is implicit
+#define LDRD_REG(reg, addr, rm) EMIT(c__ | 0b000<<25 | 1<<24  | 1<<23 | 0<<22 | 0<<21 | 0<<20 | ((reg) << 12) | ((addr) << 16) | 0b1101<<4 | (rm) )

 // str reg, [addr, #+/-imm9]
 #define STR_IMM9(reg, addr, imm9) EMIT(0xe5000000 | (((imm9)<0)?0:1)<<23 | ((reg) << 12) | ((addr) << 16) | brIMM(imm9) )
+// str with cond reg, [addr, #+/-imm9]
+#define STR_IMM9_COND(cond, reg, addr, imm9) EMIT(cond | 0x05000000 | (((imm9)<0)?0:1)<<23 | ((reg) << 12) | ((addr) << 16) | brIMM(imm9) )
+// str reg, [addr, #+/-imm9]!
+#define STR_IMM9_W(reg, addr, imm9) EMIT(0xe5200000 | (((imm9)<0)?0:1)<<23 | ((reg) << 12) | ((addr) << 16) | brIMM(imm9) )
 // strb reg, [addr, #+/-imm9]
 #define STRB_IMM9(reg, addr, imm9) EMIT(0xe5400000 | (((imm9)<0)?0:1)<<23 | ((reg) << 12) | ((addr) << 16) | brIMM(imm9) )
 // str reg, [addr], #+/-imm9
@@ -283,6 +358,8 @@ Op is 20-27
 #define STRBAI_REG_LSL_IMM5(reg, addr, rm, imm5) EMIT(0xe6c00000 | ((reg) << 12) | ((addr) << 16) | (1<<25) | brLSL(imm5, rm) )
 // strd reg, reg+1, [addr, #+/-imm8], reg must be even, reg+1 is implicit
 #define STRD_IMM8(reg, addr, imm8) EMIT(c__ | 0b000<<25 | 1<<24 | (((imm8)<0)?0:1)<<23 | 1<<22 | 0<<21 | 0<<20 | ((reg) << 12) | ((addr) << 16) | ((abs(imm8))&0xf0)<<(8-4) | (0b1111<<4) | ((abs(imm8))&0x0f) )
+// strd reg, reg+1, [addr, +rm], reg must be even, reg+1 is implicit
+#define STRD_REG(reg, addr, rm) EMIT(c__ | 0b000<<25 | 1<<24 | 1<<23 | 0<<22 | 0<<21 | 0<<20 | ((reg) << 12) | ((addr) << 16) | 0b1111<<4 | (rm) )

 // bx reg
 #define BX(reg) EMIT(0xe12fff10 | (reg) )
@@ -293,33 +370,39 @@ Op is 20-27
 #define BLX(reg) EMIT(0xe12fff30 | (reg) )

 // b cond offset
-#define Bcond(C, O) EMIT(C | (0b101<<25) | (0<<24) | ((O)>>2)&0xffffff)
+#define Bcond(C, O) EMIT(C | (0b101<<25) | (0<<24) | (((O)>>2)&0xffffff))

 // bl cond offset
-#define BLcond(C, O) EMIT(C | (0b101<<25) | (1<<24) | ((O)>>2)&0xffffff)
+#define BLcond(C, O) EMIT(C | (0b101<<25) | (1<<24) | (((O)>>2)&0xffffff))

 // push reg!, {list}
 //                           all |    const    |pre-index| subs    | no PSR  |writeback| store   |   base    |reg list
-#define PUSH(reg, list) EMIT(c__ | (0b100<<25) | (1<<24) | (0<<23) | (0<<22) | (1<<21) | (0<<20) | (reg<<16) | (list))
+#define PUSH(reg, list) EMIT(c__ | (0b100<<25) | (1<<24) | (0<<23) | (0<<22) | (1<<21) | (0<<20) | ((reg)<<16) | (list))
+
+// push reg to xESP
+#define PUSH1(reg)   STR_IMM9_W(reg, xESP, -4)

 // pop reg!, {list}
 //                           all |    const    |postindex|  add    | no PSR  |writeback|  load   |   base    |reg list
-#define POP(reg, list)  EMIT(c__ | (0b100<<25) | (0<<24) | (1<<23) | (0<<22) | (1<<21) | (1<<20) | (reg<<16) | (list))
+#define POP(reg, list)  EMIT(c__ | (0b100<<25) | (0<<24) | (1<<23) | (0<<22) | (1<<21) | (1<<20) | ((reg)<<16) | (list))
+
+// pop reg from xESP
+#define POP1(reg)   LDRAI_IMM9_W(reg, xESP, 4)

 // STMDB reg, {list}
 //                            all |    const    |pre-index| subs    | no PSR  |  no wb  | store   |   base    |reg list
-#define STMDB(reg, list) EMIT(c__ | (0b100<<25) | (1<<24) | (0<<23) | (0<<22) | (0<<21) | (0<<20) | (reg<<16) | (list))
+#define STMDB(reg, list) EMIT(c__ | (0b100<<25) | (1<<24) | (0<<23) | (0<<22) | (0<<21) | (0<<20) | ((reg)<<16) | (list))
 // STMia reg, {list}
 //                          all |    const    |postindex|   add   | no PSR  |  no wb  |  store  |   base    |reg list
-#define STM(reg, list) EMIT(c__ | (0b100<<25) | (0<<24) | (1<<23) | (0<<22) | (0<<21) | (0<<20) | (reg<<16) | (list))
+#define STM(reg, list) EMIT(c__ | (0b100<<25) | (0<<24) | (1<<23) | (0<<22) | (0<<21) | (0<<20) | ((reg)<<16) | (list))
 // LDMia reg, {list}
 //                          all |    const    |postindex|   add   | no PSR  |  no wb  |  load   |   base    |reg list
-#define LDM(reg, list) EMIT(c__ | (0b100<<25) | (0<<24) | (1<<23) | (0<<22) | (0<<21) | (1<<20) | (reg<<16) | (list))
+#define LDM(reg, list) EMIT(c__ | (0b100<<25) | (0<<24) | (1<<23) | (0<<22) | (0<<21) | (1<<20) | ((reg)<<16) | (list))


 // Half Word and signed data transfert construction
-#define HWS_REG(Cond, P, U, W, L, Rn, Rd, S, H, Rm)     (Cond | (0b000<<25) | (P<<24) | (U<<23) | (0<<22) | (W<<21) | (L<<20) | (Rn<<16) | (Rd<<12) | (1<<7) | (S<<6) | (H<<5) | (1<<4) | Rm)
-#define HWS_OFF(Cond, P, U, W, L, Rn, Rd, S, H, Imm8)   (Cond | (0b000<<25) | (P<<24) | (U<<23) | (1<<22) | (W<<21) | (L<<20) | (Rn<<16) | (Rd<<12) | ((Imm8&0xf0)<<(8-4)) | (1<<7) | (S<<6) | (H<<5) | (1<<4) | (Imm8&0x0f))
+#define HWS_REG(Cond, P, U, W, L, Rn, Rd, S, H, Rm)     (Cond | 0b000<<25 | (P)<<24 | (U)<<23 | 0<<22 | (W)<<21 | (L)<<20 | (Rn)<<16 | (Rd)<<12 | 1<<7 | (S)<<6 | (H)<<5 | 1<<4 | (Rm))
+#define HWS_OFF(Cond, P, U, W, L, Rn, Rd, S, H, Imm8)   (Cond | 0b000<<25 | (P)<<24 | (U)<<23 | 1<<22 | (W)<<21 | (L)<<20 | (Rn)<<16 | (Rd)<<12 | ((Imm8)&0xf0)<<(8-4) | 1<<7 | (S)<<6 | (H)<<5 | 1<<4 | ((Imm8)&0x0f))

 #define LDRSB_IMM8(reg, addr, imm8) EMIT(HWS_OFF(c__, 1, (((imm8)<0)?0:1), 0, 1, addr, reg, 1, 0, abs(imm8)))
 #define LDRSH_IMM8(reg, addr, imm8) EMIT(HWS_OFF(c__, 1, (((imm8)<0)?0:1), 0, 1, addr, reg, 1, 1, abs(imm8)))
@@ -328,17 +411,26 @@ Op is 20-27
 #define STRH_IMM8(reg, addr, imm8) EMIT(HWS_OFF(c__, 1, (((imm8)<0)?0:1), 0, 0, addr, reg, 0, 1, abs(imm8)))
 #define STRSH_IMM8(reg, addr, imm8) EMIT(HWS_OFF(c__, 1, (((imm8)<0)?0:1), 0, 0, addr, reg, 1, 1, abs(imm8)))

-#define LDRHAI_REG_LSL_IMM5(reg, addr, rm) EMIT(HWS_REG(c__, 0, 1, 0, 1, addr, reg, 0, 1, rm))
-#define STRHAI_REG_LSL_IMM5(reg, addr, rm) EMIT(HWS_REG(c__, 0, 1, 0, 0, addr, reg, 0, 1, rm))
+#define LDRH_REG(reg, addr, rm) EMIT(HWS_REG(c__, 1, 1, 0, 1, addr, reg, 0, 1, rm))
+#define STRH_REG(reg, addr, rm) EMIT(HWS_REG(c__, 1, 1, 0, 0, addr, reg, 0, 1, rm))
+
+#define LDRHAI_REG_LSL_IMM5(reg, addr, rm)  EMIT(HWS_REG(c__, 0, 1, 0, 1, addr, reg, 0, 1, rm))
+#define STRHAI_REG_LSL_IMM5(reg, addr, rm)  EMIT(HWS_REG(c__, 0, 1, 0, 0, addr, reg, 0, 1, rm))
+#define LDRHB_IMM8(reg, addr, imm8)         EMIT(HWS_OFF(c__, 1, (((imm8)<0)?0:1), 1, 1, addr, reg, 0, 1, abs(imm8)))
+#define LDRHA_IMM8(reg, addr, imm8)         EMIT(HWS_OFF(c__, 0, (((imm8)<0)?0:1), 0, 1, addr, reg, 0, 1, abs(imm8)))
+#define STRHB_IMM8(reg, addr, imm8)         EMIT(HWS_OFF(c__, 1, (((imm8)<0)?0:1), 1, 0, addr, reg, 0, 1, abs(imm8)))
+#define STRHA_IMM8(reg, addr, imm8)         EMIT(HWS_OFF(c__, 0, (((imm8)<0)?0:1), 0, 0, addr, reg, 0, 1, abs(imm8)))
+#define PUSH16(reg, addr)                   EMIT(HWS_OFF(c__, 1, 0, 1, 0, addr, reg, 0, 1, 2))
+#define POP16(reg, addr)                    EMIT(HWS_OFF(c__, 0, 1, 0, 1, addr, reg, 0, 1, 2))

 // Mul Long construction
-#define MULLONG(Cond, U, A, S, RdHi, RdLo, Rs, Rm)     (Cond | (0b00001<<23) | (U<<22) | (A<<21) | (S<<20) | (RdHi<<16) | (RdLo<<12) | (Rs<<8) | (0b1001<<4) | (Rm))
+#define MULLONG(Cond, U, A, S, RdHi, RdLo, Rs, Rm)     (Cond | 0b00001<<23 | (U)<<22 | (A)<<21 | (S)<<20 | (RdHi)<<16 | (RdLo)<<12 | (Rs)<<8 | 0b1001<<4 | (Rm))

 #define UMULL(RdHi, RdLo, Rs, Rm)   EMIT(MULLONG(c__, 0, 0, 0, RdHi, RdLo, Rs, Rm))
 #define SMULL(RdHi, RdLo, Rs, Rm)   EMIT(MULLONG(c__, 1, 0, 0, RdHi, RdLo, Rs, Rm))

 // Mul and MulA
-#define MULMULA(Cond, A, S, Rd, Rn, Rs, Rm)     (Cond | (0b000000<<22) | (A<<21) | (S<<20) | (Rd<<16) | (Rn<<12) | (Rs<<8) | (0b1001<<4) | (Rm))
+#define MULMULA(Cond, A, S, Rd, Rn, Rs, Rm)     (Cond | 0b000000<<22 | (A)<<21 | (S)<<20 | (Rd)<<16 | (Rn)<<12 | (Rs)<<8 | 0b1001<<4 | (Rm))
 #define MUL(Rd, Rm, Rn)     EMIT(MULMULA(c__, 0, 0, (Rd), 0, (Rm), (Rn)))

 #define SMUL_16_gen(cond, Rd, Rm, M, N, Rn) (cond | 0b00010110<<20 | (Rd)<<16 | (Rm)<<8 | 1<<7 | (M)<<6 | (N)<<5 | (Rn))
@@ -362,12 +454,20 @@ Op is 20-27
 // BFI_COND: Bit Field Insert with condition: copy any number of low order bit from Rn to any position of Rd
 #define BFI_COND(cond, rd, rn, lsb, width) EMIT(cond | (0b0111110<<21) | (((lsb)+(width)-1)<<16) | ((rd)<<12) | ((lsb)<<7) | (0b001<<4) | (rn))

+// BFC: Bit Field Clear: clear any number of adjacent bit from Rd
+#define BFC(rd, lsb, width) EMIT(c__ | (0b0111110<<21) | (((lsb)+(width)-1)<<16) | ((rd)<<12) | ((lsb)<<7) | (0b001<<4) | 0b1111)
+// BFC_COND: Bit Field Clear with condition: clear any number of adjacent bit from Rd
+#define BFC_COND(cond, rd, lsb, width) EMIT(cond | (0b0111110<<21) | (((lsb)+(width)-1)<<16) | ((rd)<<12) | ((lsb)<<7) | (0b001<<4) | 0b1111)
+
 // REV: Reverse byte of a 32bits word
 #define REV(rd, rm) EMIT(c__ | (0b01101<<23) | (0<<22) | (0b11<<20) | (0b1111<<16) | ((rd)<<12) | (0b1111<<8) | (0b0011<<4) | (rm))

 #define SSAT_gen(cond, sat_imm, Rd, imm5, sh, Rn) (cond | 0b0110101<<21 | (sat_imm)<<16 | (Rd)<<12 | (imm5)<<7 | (sh)<<6 | 0b01<<4 | (Rn))
 // Signed Staturate Rn to 2^(staturate_to-1) into Rd. Optionnaly shift left Rn before saturate
 #define SSAT_REG_LSL_IMM5(Rd, saturate_to, Rn, shift)   EMIT(SSAT_gen(c__, (saturate_to)-1, Rd, shift, 0, Rn))
+// Signed Staturate Rn to 2^(staturate_to-1) into Rd. Optionnaly shift left Rn before saturate
+#define SSAT_REG_LSL_IMM5_COND(cond, Rd, saturate_to, Rn, shift)   EMIT(SSAT_gen((cond), (saturate_to)-1, Rd, shift, 0, Rn))
+
 #define USAT_gen(cond, sat_imm, Rd, imm5, sh, Rn) (cond | 0b0110111<<21 | (sat_imm)<<16 | (Rd)<<12 | (imm5)<<7 | (sh)<<6 | 0b01<<4 | (Rn))
 // Unsigned Staturate Rn to 2^(staturate_to-1) into Rd. Optionnaly shift left Rn before saturate
 #define USAT_REG_LSL_IMM5(Rd, saturate_to, Rn, shift)   EMIT(SSAT_gen(c__, (saturate_to), Rd, shift, 0, Rn))
@@ -384,11 +484,33 @@ Op is 20-27

 #define LDREXD_gen(cond, Rn, Rt) (cond | 0b000<<25 | 0b11011<<20 | (Rn)<<16 | (Rt)<<12 | 0b1111<<8 | 0b1001<<4 | 0b1111)
 // Load Exclusive Rt/Rt+1 from Rn (tagging the memory)
-#define LDREXD(Rn, Rt)  EMIT(LDREXD_gen(c__, Rn, Rt))
+#define LDREXD(Rt, Rn)  EMIT(LDREXD_gen(c__, Rn, Rt))
+#define LDREXD_COND(cond, Rt, Rn)  EMIT(LDREXD_gen(cond, Rn, Rt))

 #define STREXD_gen(cond, Rd, Rn, Rt)   (cond | 0b000<<25 | 0b11010<<20 | (Rn)<<16 | (Rd)<<12 | 0b1111<<8 | 0b1001<<4 | (Rt))
 // Store Exclusive Rt/Rt+1 to Rn, with result in Rd if tag is ok (Rd!=Rn && Rd!=Rt && Rd!=Rt+1), Rd==1 if store failed
-#define STREXD(Rd, Rn, Rt)  EMIT(STREXD_gen(c__, Rd, Rn, Rt))
+#define STREXD(Rd, Rt, Rn)  EMIT(STREXD_gen(c__, Rd, Rn, Rt))
+#define STREXD_COND(cond, Rd, Rt, Rn)  EMIT(STREXD_gen(cond, Rd, Rn, Rt))
+
+#define LDREX_gen(cond, Rn, Rt)     (cond | 0b0001100<<21 | 1<<20 | (Rn)<<16 | (Rt)<<12 | 0b1111<<8 | 0b1001<<4 | 0b1111)
+// Load Exclusive Rt from Rn (tagging the memory)
+#define LDREX(Rt, Rn)       EMIT(LDREX_gen(c__, Rn, Rt))
+#define LDREX_COND(cond, Rt, Rn)       EMIT(LDREX_gen(cond, Rn, Rt))
+
+#define STREX_gen(cond, Rd, Rn, Rt) (cond | 0b0001100<<21 | 0<<20 | (Rn)<<16 | (Rd)<<12 | 0b1111<<8 | 0b1001<<4 | (Rt))
+// Store Exclusive Rt to Rn, with result in Rd=0 if tag is ok, Rd==1 if store failed (Rd!=Rn && Rd!=Rt)
+#define STREX(Rd, Rt, Rn)   EMIT(STREX_gen(c__, Rd, Rn, Rt))
+#define STREX_COND(cond, Rd, Rt, Rn)   EMIT(STREX_gen(cond, Rd, Rn, Rt))
+
+#define LDREXB_gen(cond, Rn, Rt)        (cond | 0b0001110<<21 | 1<<20 | (Rn)<<16 | (Rt)<<12 | 0b1111<<8 | 0b1001<<4 | 0b1111)
+// Load Exclusive Byte Rt from Rn (tagging the memory)
+#define LDREXB(Rt, Rn)      EMIT(LDREXB_gen(c__, Rn, Rt))
+#define LDREXB_COND(cond, Rt, Rn)      EMIT(LDREXB_gen(cond, Rn, Rt))
+
+#define STREXB_gen(cond, Rd, Rn, Rt)    (cond | 0b0001110<<21 | 0<<20 | (Rn)<<16 | (Rd)<<12 | 0b1111<<8 | 0b1001<<4 | (Rt))
+// Store Exclusive byte Rt to Rn, with result in Rd=0 if tag is ok, Rd==1 if store failed (Rd!=Rn && Rd!=Rt)
+#define STREXB(Rd, Rt, Rn)  EMIT(STREXB_gen(c__, Rd, Rn, Rt))
+#define STREXB_COND(cond, Rd, Rt, Rn)  EMIT(STREXB_gen(cond, Rd, Rn, Rt))

 // Count leading 0 bit of Rm, store result in Rd
 #define CLZ(Rd, Rm)  EMIT(c__ | 0b00010110<<20 | 0b1111<<16 | (Rd)<<12 | 0b1111<<8 | 0b0001<<4 | (Rm))
@@ -401,6 +523,23 @@ Op is 20-27
 // Preload Cache Rn-Rm
 #define PLDn(Rn, Rm) EMIT(PLD_gen(0, 1, Rn, 0, 0, Rm))

+#define SWP_gen(cond, B, Rn, Rt, Rt2)   (cond | 0b0001<<24 | (B)<<22 | (Rn)<<16 | (Rt)<<12 | 0b1001<<4 | (Rt2))
+// SWAP (atomic) [Rn]->Rt2 / Rt->[Rn], Rt can be same as Rt2
+#define SWP(Rt, Rt2, Rn)    EMIT(SWP_gen(c__, 0, Rn, Rt, Rt2))
+// SWAP Byte (atomic) [Rn]->Rt2 / Rt->[Rn], Rt can be same as Rt2, Byte is zero extended
+#define SWPB(Rt, Rt2, Rn)   EMIT(SWP_gen(c__, 1, Rn, Rt, Rt2))
+
+#define SDIV_gen(cond, Rd, Rm, Rn)  (cond | 0b0111<<24 | 0b0001<<20 | (Rd)<<16 | 0b1111<<12 | (Rm)<<8 | 0b0001<<4 | (Rn))
+// Signed Div Rd <- Rn/Rm
+#define SDIV(Rd, Rm, Rn)    EMIT(SDIV_gen(c__, Rd, Rm, Rn))
+
+#define UDIV_gen(cond, Rd, Rm, Rn)  (cond | 0b0111<<24 | 0b0011<<20 | (Rd)<<16 | 0b1111<<12 | (Rm)<<8 | 0b0001<<4 | (Rn))
+// Unsigned Div Rd <- Rn/Rm
+#define UDIV(Rd, Rm, Rn)    EMIT(UDIV_gen(c__, Rd, Rm, Rn))
+
+// Yield
+#define YIELD(cond) EMIT(cond | 0b00110010<<20 | 0b1111<<12 | 1)
+
 // VFPU
 #define TRANSFERT64(C, op) ((0b1100<<24) | (0b010<<21) | (0b101<<9) | ((C)<<8) | ((op)<<4))

@@ -485,21 +624,21 @@ Op is 20-27
 // Convert from int32 Sm to single Dd
 #define VCVT_F32_S32(Sd, Sm)    EMIT(c__ | (0b1110<<24) | (1<<23) | (((Sd)&1)<<22) | (0b111<<19) | (0b000<<16) | ((((Sd)>>1)&15)<<12) | (0b101<<9) | (0<<8) | (1<<7) | (1<<6) | (((Sm)&1)<<5) | (((Sm)>>1)&15) )

-#define VCVT_16_gen(cond, D, op, U, Vd, sf, sx, i, imm4)   (cond | 0b1110<<24 | 1<<23 | (D)<<22 | 0b11<<20 | 1<<19 | (op)<<18 | 1<<17 | (U)<<16 | (Vd)<<12 | 0b101<<9 | (sf)<<8 | (sx)<<7 | 1<<6 | (i)<<5 | (imm4))
+#define VCVT_FP_gen(cond, D, op, U, Vd, sf, sx, i, imm4)   (cond | 0b1110<<24 | 1<<23 | (D)<<22 | 0b11<<20 | 1<<19 | (op)<<18 | 1<<17 | (U)<<16 | (Vd)<<12 | 0b101<<9 | (sf)<<8 | (sx)<<7 | 1<<6 | (i)<<5 | (imm4))
 // Inplace convert from F64 to S16. Rounding is not selectable
-#define VCVT_S16_F64(Dd)    EMIT(VCVT_16_gen(c__, ((Dd)>>4)&1, 1, 0, (Dd)&15, 1, 0, 16&1, (16>>1)&15))
+#define VCVT_S16_F64(Dd)    EMIT(VCVT_FP_gen(c__, ((Dd)>>4)&1, 1, 0, (Dd)&15, 1, 0, 16&1, (16>>1)&15))

 // Mutiply F64 Dd = Dn*Dm
-#define VMUL_F64(Dd, Dn, Dm)    EMIT(c__ | (0b1110<<24) | (0<<23) | ((((Dd)>>4)&1)<<22) | (0b10<<20) | (((Dn)&15)<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | (((Dn>>4)&1)<<7) | (((Dm>>4)&1)<<5) | ((Dm)&15) )
+#define VMUL_F64(Dd, Dn, Dm)    EMIT(c__ | (0b1110<<24) | (0<<23) | ((((Dd)>>4)&1)<<22) | (0b10<<20) | (((Dn)&15)<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | ((((Dn)>>4)&1)<<7) | ((((Dm)>>4)&1)<<5) | ((Dm)&15) )

 // Divide F64 Dd = Dn/Dm
-#define VDIV_F64(Dd, Dn, Dm)    EMIT(c__ | (0b1110<<24) | (1<<23) | ((((Dd)>>4)&1)<<22) | (0b00<<20) | (((Dn)&15)<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | (((Dn>>4)&1)<<7) | (((Dm>>4)&1)<<5) | ((Dm)&15) )
+#define VDIV_F64(Dd, Dn, Dm)    EMIT(c__ | (0b1110<<24) | (1<<23) | ((((Dd)>>4)&1)<<22) | (0b00<<20) | (((Dn)&15)<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | ((((Dn)>>4)&1)<<7) | ((((Dm)>>4)&1)<<5) | ((Dm)&15) )

 // Add F64 Dd = Dn + Dm
-#define VADD_F64(Dd, Dn, Dm)    EMIT(c__ | (0b1110<<24) | (0<<23) | ((((Dd)>>4)&1)<<22) | (0b11<<20) | (((Dn)&15)<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | (((Dn>>4)&1)<<7) | (0<<6) | (((Dm>>4)&1)<<5) | ((Dm)&15) )
+#define VADD_F64(Dd, Dn, Dm)    EMIT(c__ | (0b1110<<24) | (0<<23) | ((((Dd)>>4)&1)<<22) | (0b11<<20) | (((Dn)&15)<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | ((((Dn)>>4)&1)<<7) | (0<<6) | ((((Dm)>>4)&1)<<5) | ((Dm)&15) )

 // Sub F64 Dd = Dn + Dm
-#define VSUB_F64(Dd, Dn, Dm)    EMIT(c__ | (0b1110<<24) | (0<<23) | ((((Dd)>>4)&1)<<22) | (0b11<<20) | (((Dn)&15)<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | (((Dn>>4)&1)<<7) | (1<<6) | (((Dm>>4)&1)<<5) | ((Dm)&15) )
+#define VSUB_F64(Dd, Dn, Dm)    EMIT(c__ | (0b1110<<24) | (0<<23) | ((((Dd)>>4)&1)<<22) | (0b11<<20) | (((Dn)&15)<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | ((((Dn)>>4)&1)<<7) | (1<<6) | ((((Dm)>>4)&1)<<5) | ((Dm)&15) )

 // Mutiply F32 Sd = Sn*Sm
 #define VMUL_F32(Sd, Sn, Sm)    EMIT(c__ | (0b1110<<24) | (0<<23) | (((Sd)&1)<<22) | (0b10<<20) | ((((Sn)>>1)&15)<<16) | ((((Sd)>>1)&15)<<12) | (0b101<<9) | (0<<8) | (((Sn)&1)<<7) | (((Sm)&1)<<5) | (((Sm)>>1)&15) )
@@ -514,7 +653,7 @@ Op is 20-27
 #define VSUB_F32(Sd, Sn, Sm)    EMIT(c__ | (0b1110<<24) | (0<<23) | (((Sd)&1)<<22) | (0b11<<20) | ((((Sn)>>1)&15)<<16) | ((((Sd)>>1)&15)<<12) | (0b101<<9) | (0<<8) | (((Sn)&1)<<7) | (1<<6) | (((Sm)&1)<<5) | (((Sm)>>1)&15) )

 // Cmp between 2 double Dd and Dm
-#define VCMP_F64(Dd, Dm)    EMIT(c__ | (0b1110<<24) | (1<<23) | ((((Dd)>>4)&1)<<22) | (0b11<<20) | (0b0100<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | (0<<7) | (1<<6) | (((Dm>>4)&1)<<5) | ((Dm)&15) )
+#define VCMP_F64(Dd, Dm)    EMIT(c__ | (0b1110<<24) | (1<<23) | ((((Dd)>>4)&1)<<22) | (0b11<<20) | (0b0100<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | (0<<7) | (1<<6) | ((((Dm)>>4)&1)<<5) | ((Dm)&15) )
 // Cmp between 1 double Dd and 0.0
 #define VCMP_F64_0(Dd)      EMIT(c__ | (0b1110<<24) | (1<<23) | ((((Dd)>>4)&1)<<22) | (0b11<<20) | (0b0101<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | (0<<7) | (1<<6) | (0<<5) | (0) )
 // Cmp between 2 single Sd and Sm
@@ -523,10 +662,10 @@ Op is 20-27
 #define VCMP_F32_0(Sd)      EMIT(c__ | (0b1110<<24) | (1<<23) | (((Sd)&1)<<22) | (0b11<<20) | (0b0101<<16) | ((((Sd)>>1)&15)<<12) | (0b101<<9) | (0<<8) | (0<<7) | (1<<6) | (0<<5) | (0) )

 // Neg F64 Dd = - Dm
-#define VNEG_F64(Dd, Dm)    EMIT(c__ | (0b1110<<24) | (1<<23) | ((((Dd)>>4)&1)<<22) | (0b11<<20) | (0b0001<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | (0b01<<6) | (((Dm>>4)&1)<<5) | ((Dm)&15) )
+#define VNEG_F64(Dd, Dm)    EMIT(c__ | (0b1110<<24) | (1<<23) | ((((Dd)>>4)&1)<<22) | (0b11<<20) | (0b0001<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | (0b01<<6) | ((((Dm)>>4)&1)<<5) | ((Dm)&15) )

 // Sqrt F64 Dd = - Dm
-#define VSQRT_F64(Dd, Dm)    EMIT(c__ | (0b1110<<24) | (1<<23) | ((((Dd)>>4)&1)<<22) | (0b11<<20) | (0b0001<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | (0b11<<6) | (((Dm>>4)&1)<<5) | ((Dm)&15) )
+#define VSQRT_F64(Dd, Dm)    EMIT(c__ | (0b1110<<24) | (1<<23) | ((((Dd)>>4)&1)<<22) | (0b11<<20) | (0b0001<<16) | (((Dd)&15)<<12) | (0b101<<9) | (1<<8) | (0b11<<6) | ((((Dm)>>4)&1)<<5) | ((Dm)&15) )
 // Sqrt F32 Dd = - Dm
 #define VSQRT_F32(Sd, Sm)    EMIT(c__ | (0b1110<<24) | (1<<23) | (((Sd)&1)<<22) | (0b11<<20) | (0b0001<<16) | ((((Sd)>>1)&15)<<12) | (0b101<<9) | (0<<8) | (0b11<<6) | (((Sm)&1)<<5) | (((Sm)>>1)&15) )

@@ -590,12 +729,26 @@ Op is 20-27
 #define VEORQ(Dd, Dn, Dm)   EMIT(VEOR_gen(((Dd)>>4)&1, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))

 #define VMOVL_gen(U, D, imm3, Vd, M, Vm) (0b1111<<28 | 0b001<<25 | (U)<<24 | 1<<23 | (D)<<22 | (imm3)<<19 | (Vd)<<12 | 0b1010<<8 | (M)<<5 | 1<<4 | (Vm))
+#define VMOVL_S8(Dd, Dm)    EMIT(VMOVL_gen(0, ((Dd)>>4)&1, 0b001, (Dd)&15, ((Dm)>>4)&1, (Dm)&15))
+#define VMOVL_U8(Dd, Dm)    EMIT(VMOVL_gen(1, ((Dd)>>4)&1, 0b001, (Dd)&15, ((Dm)>>4)&1, (Dm)&15))
 #define VMOVL_S32(Dd, Dm)   EMIT(VMOVL_gen(0, ((Dd)>>4)&1, 0b100, (Dd)&15, ((Dm)>>4)&1, (Dm)&15))
 #define VMOVL_U32(Dd, Dm)   EMIT(VMOVL_gen(1, ((Dd)>>4)&1, 0b100, (Dd)&15, ((Dm)>>4)&1, (Dm)&15))

 #define VMOV_gen(D,Vd, M, Vm, Q) (0b1111<<28 | 0b0010<<24 | 0<<23 | (D)<<22 | 0b10<<20 | (Vm)<<16 | (Vd)<<12 | 0b0001<<8 | (M)<<7 | (Q)<<6 | (M)<<5 | 1<<4 | (Vm))
-#define VMOVD(Dd, Dm) EMIT(VMOV_gen(((Dd)>>4)&1, (Dd)&15, ((Dm)>>4)&1, (Dm)&15, 0))
-#define VMOVQ(Dd, Dm) EMIT(VMOV_gen(((Dd)>>4)&1, (Dd)&15, ((Dm)>>4)&1, (Dm)&15, 1))
+#define VMOVD(Dd, Dm) if((Dd)!=(Dm)) {EMIT(VMOV_gen(((Dd)>>4)&1, (Dd)&15, ((Dm)>>4)&1, (Dm)&15, 0));}
+#define VMOVQ(Dd, Dm) if((Dd)!=(Dm)) {EMIT(VMOV_gen(((Dd)>>4)&1, (Dd)&15, ((Dm)>>4)&1, (Dm)&15, 1));}
+
+#define VMOV_igen(i, D, imm3, Vd, cmode, Q, op, imm4)   (0b1111<<28 | 0b001<<25 | (i)<<24 | 1<<23 | (D)<<22 | (imm3)<<16 | (Vd)<<12 | (cmode)<<8 | (Q)<<6 | (op)<<5 | 1<<4 | (imm4))
+#define VMOV_8(Dd, imm)     EMIT(VMOV_igen(((imm)>>7)&1, ((Dd)>>4)&1, ((imm)>>4)&7, (Dd)&15, 0b1110, 0, 0, (imm)&15))
+#define VMOVQ_8(Dd, imm)    EMIT(VMOV_igen(((imm)>>7)&1, ((Dd)>>4)&1, ((imm)>>4)&7, (Dd)&15, 0b1110, 1, 0, (imm)&15))
+// Dd <= imm8 in high bits
+#define VMOV_H32(Dd, imm8)  EMIT(VMOV_igen(((imm8)>>7)&1, ((Dd)>>4)&1, ((imm8)>>4)&7, (Dd)&15, 0b0110, 0, 0, (imm8)&15))
+// Dd <= imm8 in high bits
+#define VMOV_H16(Dd, imm8)  EMIT(VMOV_igen(((imm8)>>7)&1, ((Dd)>>4)&1, ((imm8)>>4)&7, (Dd)&15, 0b1010, 0, 0, (imm8)&15))
+// Qd <= imm8 in high bits
+#define VMOVQ_H32(Dd, imm8) EMIT(VMOV_igen(((imm8)>>7)&1, ((Dd)>>4)&1, ((imm8)>>4)&7, (Dd)&15, 0b0110, 1, 0, (imm8)&15))
+// Qd <= imm8 in high bits
+#define VMOVQ_H16(Dd, imm8) EMIT(VMOV_igen(((imm8)>>7)&1, ((Dd)>>4)&1, ((imm8)>>4)&7, (Dd)&15, 0b1010, 1, 0, (imm8)&15))

 #define VLD1LANE_gen(D, Rn, Vd, size, index_align, Rm) (0b1111<<28 | 0b0100<<24 | 1<<23 | (D)<<22 | 0b10<<20 | (Rn)<<16 | (Vd)<<12 | (size)<<10 | (index_align)<<4 | (Rm))
 #define VLD1LANE_8(Dd, Rn, index)    EMIT(VLD1LANE_gen(((Dd)>>4)&1, Rn, (Dd)&15, 0, (index)<<1, 15))
@@ -644,6 +797,9 @@ Op is 20-27
 #define VBICD(Dd, Dn, Dm) EMIT(VBIC_gen(((Dd)>>4)&1, (Dd)&15, ((Dn)>>4)&1, (Dn)&15, ((Dm)>>4)&1, (Dm)&15, 0))
 #define VBICQ(Dd, Dn, Dm) EMIT(VBIC_gen(((Dd)>>4)&1, (Dd)&15, ((Dn)>>4)&1, (Dn)&15, ((Dm)>>4)&1, (Dm)&15, 1))

+#define VBIC_igen(i, D, imm3, Vd, cmode, Q, imm4)  (0b1111<<28 | 0b001<<25 | (i)<<24 | 1<<23 | (D)<<22 | (imm3)<<16 | (Vd)<<12 | (cmode)<<8 | (Q)<<6 | 0b11<<4 | (imm4))
+#define VBICQ_16_imm(Dd, imm)   EMIT(VBIC_16_imm(((imm)>>7)&1, (Dd>>4)&1, ((imm)>>4)&7, (Dd)&15, 0b1001, 1, (imm)&15))
+
 #define VCEQ_I_gen(size, D, Vn, Vd, N, Q, M, Vm) (0b1111<<28 | 0b0011<<24 | 0<<23 | (D)<<22 | (size)<<20 | (Vn)<<16 | (Vd)<<12 | 0b1000<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | 1<<4 | (Vm))
 #define VCEQ_8(Dd, Dn, Dm)     EMIT(VCEQ_I_gen(0, ((Dd)>>4)&1, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
 #define VCEQQ_8(Dd, Dn, Dm)    EMIT(VCEQ_I_gen(0, ((Dd)>>4)&1, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
@@ -657,6 +813,14 @@ Op is 20-27
 #define VCEQ_F32(Dd, Dn, Dm)    EMIT(VCEQ_F_gen(0, ((Dd)>>4)&1, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
 #define VCEQQ_F32(Dd, Dn, Dm)   EMIT(VCEQ_F_gen(0, ((Dd)>>4)&1, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))

+#define VCEQ_0_gen(D, size, Vd, F, Q, M, Vm)    (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (size)<<18 | 0b01<<16 | (Vd)<<12 | (F)<<10 | 0b010<<7 | (Q)<<6 | (M)<<5 | (Vm))
+#define VCEQ_0_8(Dd, Dm)        EMIT(VCEQ_0_gen(((Dd)>>4)&1, 0, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VCEQ_0_16(Dd, Dm)       EMIT(VCEQ_0_gen(((Dd)>>4)&1, 1, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VCEQ_0_32(Dd, Dm)       EMIT(VCEQ_0_gen(((Dd)>>4)&1, 2, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VCEQQ_0_8(Dd, Dm)       EMIT(VCEQ_0_gen(((Dd)>>4)&1, 0, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VCEQQ_0_16(Dd, Dm)      EMIT(VCEQ_0_gen(((Dd)>>4)&1, 1, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VCEQQ_0_32(Dd, Dm)      EMIT(VCEQ_0_gen(((Dd)>>4)&1, 2, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+
 #define VCGT_I_gen(U, D, size, Vn, Vd, N, Q, M, Vm) (0b1111<<28 | 0b001<<25 | (U)<<24 | 0<<23 | (D)<<22 | (size)<<20 | (Vn)<<16 | (Vd)<<12 | 0b0011<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | (Vm))
 #define VCGT_U8(Dd, Dn, Dm)     EMIT(VCGT_I_gen(1, ((Dd)>>4)&1, 0, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
 #define VCGTQ_U8(Dd, Dn, Dm)    EMIT(VCGT_I_gen(1, ((Dd)>>4)&1, 0, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
@@ -682,6 +846,15 @@ Op is 20-27
 #define VCGE_F32(Dd, Dn, Dm)    EMIT(VCGE_F_gen(((Dd)>>4)&1, 0, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
 #define VCGEQ_F32(Dd, Dn, Dm)   EMIT(VCGE_F_gen(((Dd)>>4)&1, 0, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))

+#define VCLT_0_gen(D, size, Vd, F, Q, M, Vm)    (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (size)<<18 | 0b01<<16 | (Vd)<<12 | (F)<<10 | 0b100<<7 | (Q)<<6 | (M)<<5 | (Vm))
+#define VCLT_0_8(Dd, Dm)        EMIT(VCLT_0_gen(((Dd)>>4)&1, 0, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VCLT_0_16(Dd, Dm)       EMIT(VCLT_0_gen(((Dd)>>4)&1, 1, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VCLT_0_32(Dd, Dm)       EMIT(VCLT_0_gen(((Dd)>>4)&1, 2, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VCLTQ_0_8(Dd, Dm)       EMIT(VCLT_0_gen(((Dd)>>4)&1, 0, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VCLTQ_0_16(Dd, Dm)      EMIT(VCLT_0_gen(((Dd)>>4)&1, 1, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VCLTQ_0_32(Dd, Dm)      EMIT(VCLT_0_gen(((Dd)>>4)&1, 2, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+
+
 #define VSHR_gen(U, D, imm6, Vd, L, Q, M, Vm) (0b1111<<28 | 0b001<<25 | (U)<<24 | 1<<23 | (D)<<22 | (imm6)<<16 | (Vd)<<12 | (L)<<7 | (Q)<<6 | (M)<<5 | 1<<4 | (Vm))
 #define VSHR_U8(Dd, Dm, imm3)    EMIT(VSHR_gen(1, ((Dd)>>4)&1, 0b001<<3 | (8-(imm3)), (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
 #define VSHR_S8(Dd, Dm, imm3)    EMIT(VSHR_gen(0, ((Dd)>>4)&1, 0b001<<3 | (8-(imm3)), (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
@@ -728,6 +901,11 @@ Op is 20-27
 #define VSHLQ_S32(Dd, Dm, Dn)   EMIT(VSHLR_gen(0, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
 #define VSHLQ_S64(Dd, Dm, Dn)   EMIT(VSHLR_gen(0, ((Dd)>>4)&1, 0b11, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))

+#define VSHRN_gen(D, imm6, Vd, M, Vm)   (0b1111<<28 | 0b0010<<24 | 1<<23 | (D)<<22 | (imm6)<<16 | (Vd)<<12 | 1<<11 | (M)<<5 | 1<<4 | (Vm))
+#define VSHRN_16(Dd, Dm, imm3)          EMIT(VSHRN_gen(((Dd)>>4)&1, 0b001<<3 | (8-(imm3)), (Dd)&15, ((Dm)>>4)&1, (Dm)&15))
+#define VSHRN_32(Dd, Dm, imm4)          EMIT(VSHRN_gen(((Dd)>>4)&1, 0b01<<4  | (16-(imm4)), (Dd)&15, ((Dm)>>4)&1, (Dm)&15))
+#define VSHRN_64(Dd, Dm, imm5)          EMIT(VSHRN_gen(((Dd)>>4)&1, 0b1<<5   | (32-(imm5)), (Dd)&15, ((Dm)>>4)&1, (Dm)&15))
+
 #define VTRN_gen(D, size, Vd, Q, M, Vm) (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (size)<<18 | 0b10<<16 | (Vd)<<12 | 0b0000<<8 | 1<<7 | (Q)<<6 | (M)<<5 | (Vm))
 #define VTRN_32(Dd, Dm)     EMIT(VTRN_gen(((Dd)>>4)&1, 2, (Dd)&15, 0, ((Dm)>>4)&1, (Dm)&15))

@@ -766,6 +944,8 @@ Op is 20-27
 #define VCVTn_S32_F32(Dd, Dm)   EMIT(VCVT_NEON_gen(((Dd)>>4)&1, 2, (Dd)&15, 0b10, 0, ((Dm)>>4)&1, (Dm)&15))

 #define VMULL_NEON_gen(U, D, size, Vn, Vd, op, N, M, Vm)    (0b1111<<28 | 0b001<<25 | (U)<<24 | 1<<23 | (D)<<22 | (size)<<20 | (Vn)<<16 | (Vd)<<12 | 0b11<<10 | (op)<<9 | (N)<<7 | (M)<<5 | (Vm))
+#define VMULL_S16_S8(Dd, Dn, Dm)    EMIT(VMULL_NEON_gen(0, ((Dd)>>4)&1, 0, (Dn)&15, (Dd)&15, 0, ((Dn)>>4)&1, ((Dm)>>4)&1, (Dm)&15))
+#define VMULL_U16_U8(Dd, Dn, Dm)    EMIT(VMULL_NEON_gen(1, ((Dd)>>4)&1, 0, (Dn)&15, (Dd)&15, 0, ((Dn)>>4)&1, ((Dm)>>4)&1, (Dm)&15))
 #define VMULL_S32_S16(Dd, Dn, Dm)   EMIT(VMULL_NEON_gen(0, ((Dd)>>4)&1, 1, (Dn)&15, (Dd)&15, 0, ((Dn)>>4)&1, ((Dm)>>4)&1, (Dm)&15))
 #define VMULL_U32_U16(Dd, Dn, Dm)   EMIT(VMULL_NEON_gen(1, ((Dd)>>4)&1, 1, (Dn)&15, (Dd)&15, 0, ((Dn)>>4)&1, ((Dm)>>4)&1, (Dm)&15))
 #define VMULL_S64_S32(Dd, Dn, Dm)   EMIT(VMULL_NEON_gen(0, ((Dd)>>4)&1, 2, (Dn)&15, (Dd)&15, 0, ((Dn)>>4)&1, ((Dm)>>4)&1, (Dm)&15))
@@ -778,8 +958,8 @@ Op is 20-27
 #define VMUL_16(Dd, Dn, Dm)      EMIT(VMUL_NEON_gen(0, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))

 #define VEXT_gen(D, Vn, Vd, imm4, N, Q, M, Vm)  (0b1111<<28 | 0b0010<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (Vn)<<16 | (Vd)<<12 | (imm4)<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | (Vm))
-#define VEXT_8(Dd, Dn, Dm, imm4)    EMIT(VEXT_gen(((Dd)>>4)&1, (Dn)&15, (Dd)&15, imm4, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
-#define VEXTQ_8(Dd, Dn, Dm, imm4)   EMIT(VEXT_gen(((Dd)>>4)&1, (Dn)&15, (Dd)&15, imm4, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VEXT_8(Dd, Dn, Dm, imm4)    EMIT(VEXT_gen(((Dd)>>4)&1, (Dn)&15, (Dd)&15, (imm4)&0xf, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VEXTQ_8(Dd, Dn, Dm, imm4)   EMIT(VEXT_gen(((Dd)>>4)&1, (Dn)&15, (Dd)&15, (imm4)&0xf, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))

 #define VMVN_gen(D, size, Vd, Q, M, Vm) (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (size)<<18 | (Vd)<<12 | 0b1011<<7 | (Q)<<6 | (M)<<5 | 0<<4 | (Vm))
 #define VMVNQ(Dd, Dm)       EMIT(VMVN_gen(((Dd)>>4)&1, 0, (Dd)&15, 1, ((Dm)>>4)&1, (Dm)&15))
@@ -809,6 +989,10 @@ Op is 20-27
 #define VTBL1_8(Dd, Dn, Dm) EMIT(VTBL_gen(((Dd)>>4)&1, (Dn)&15, (Dd)&15, 0b00, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
 // Vector Table lookup, take elements from Dn/Dn+1, and using lookup table Dm, put elements in Dd
 #define VTBL2_8(Dd, Dn, Dm) EMIT(VTBL_gen(((Dd)>>4)&1, (Dn)&15, (Dd)&15, 0b01, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+// Vector Table lookup eXtension, take elements from Dn, and using lookup table Dm, put elements in Dd, outer element untouched
+#define VTBLX1_8(Dd, Dn, Dm) EMIT(VTBL_gen(((Dd)>>4)&1, (Dn)&15, (Dd)&15, 0b00, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+// Vector Table lookup eXtension, take elements from Dn/Dn+1, and using lookup table Dm, put elements in Dd, outer element untouched
+#define VTBLX2_8(Dd, Dn, Dm) EMIT(VTBL_gen(((Dd)>>4)&1, (Dn)&15, (Dd)&15, 0b01, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))

 #define VRECPE_gen(D, size, Vd, F, Q, M, Vm) (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (size)<<18 | 0b11<<16 | (Vd)<<12 | 0b010<<9 | (F)<<8 | (Q)<<6 | (M)<<5 | (Vm))
 // Vector Reciprocal Estimate of Dm to Dd
@@ -818,11 +1002,20 @@ Op is 20-27
 // Vector Reciprocal Step of Dn and Dm to Dd
 #define VRECPSQ_F32(Dd, Dn, Dm) EMIT(VRECPS_gen(((Dd)>>4)&1, 0, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))

-#define VSWAP_gen(D, size, Vd, Q, M, Vm)    (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<20 | (size)<<18 | 0b10<<16 | (Vd)<<12 | 0b0000<<7 | (Q)<<6 | (M)<<5 | (Vm))
+#define VRSQRTE_gen(D, size, Vd, F, Q, M, Vm) (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (size)<<18 | 0b11<<16 | (Vd)<<12 | 0b010<<9 | (F)<<8 | 1<<7 | (Q)<<6 | (M)<<5 | (Vm))
+// Vector Reciprocal Square Root Estimate of Dm to Dd
+#define VRSQRTEQ_F32(Dd, Dm) EMIT(VRSQRTE_gen(((Dd)>>4)&1, 0b10, (Dd)&15, 1, 1, ((Dm)>>4)&1, (Dm)&15))
+
+#define VRSQRTS_gen(D, size, Vn, Vd, N, Q, M, Vm) (0b1111<<28 | 0b0010<<24 | 0<<23 | (D)<<22 | 1<<21 | (size)<<20 | (Vn)<<16 | (Vd)<<12 | 0b1111<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | 1<<4 | (Vm))
+// Vector Reciprocal Square Root Step of Dn and Dm to Dd
+#define VRSQRTSQ_F32(Dd, Dn, Dm) EMIT(VRSQRTS_gen(((Dd)>>4)&1, 0, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+
+
+#define VSWP_gen(D, size, Vd, Q, M, Vm)    (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (size)<<18 | 0b10<<16 | (Vd)<<12 | 0b0000<<7 | (Q)<<6 | (M)<<5 | (Vm))
 // Swap Double vectors content
-#define VSWAP(Dd, Dm)   EMIT(VSWAP_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 0, ((Dm)>>4)&1, (Dm)&15)))
+#define VSWP(Dd, Dm)   EMIT(VSWP_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 0, ((Dm)>>4)&1, (Dm)&15))
 // Swap Quad vectors content
-#define VSWAPQ(Dd, Dm)  EMIT(VSWAP_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 1, ((Dm)>>4)&1, (Dm)&15)))
+#define VSWPQ(Dd, Dm)  EMIT(VSWP_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 1, ((Dm)>>4)&1, (Dm)&15))

 #define VQADD_gen(U, D, size, Vn, Vd, N, Q, M, Vm)  (0b1111<<28 | 0b001<<25 | (U)<<24 | (D)<<22 | (size)<<20 | (Vn)<<16 | (Vd)<<12  | 0b0000<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | 1<<4 | (Vm))
 // Add with saturation unsigned 8bits
@@ -903,4 +1096,145 @@ Op is 20-27
 #define VNEGN_F32(Dd, Dm)   EMIT(VNEGN_gen(((Dd)>>4)&1, 0b10, (Dd)&15, 1, 0, ((Dm)>>4)&1, (Dm)&15))
 #define VNEGNQ_F32(Dd, Dm)  EMIT(VNEGN_gen(((Dd)>>4)&1, 0b10, (Dd)&15, 1, 1, ((Dm)>>4)&1, (Dm)&15))

+#define VMINMAXF_gen(D, op, sz, Vn, Vd, N, Q, M, Vm)    (0b1111<<28 | 0b0010<<24 | (D)<<22 | (op)<<21 | (sz)<<20 | (Vn)<<16 | (Vd)<<12 | 0b1111<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | (Vm))
+#define VMINQ_F32(Dd, Dn, Dm)   EMIT(VMINMAXF_gen(((Dd)>>4)&1, 1, 0, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VMAXQ_F32(Dd, Dn, Dm)   EMIT(VMINMAXF_gen(((Dd)>>4)&1, 0, 0, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+
+#define VABD_gen(U, D, size, Vn, Vd, N, Q, M, Vm)   (0b1111<<28 | 1<<25 | (U)<<24 | 0<<23 | (D)<<22 | (size)<<20 | (Vn)<<16 | (Vd)<<12 | 0b0111<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | (Vm))
+// Compute absolute difference of U8
+#define VABD_U8(Dd, Dn, Dm)     EMIT(VABD_gen(1, ((Dd)>>4)&1, 0, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VABDQ_U8(Dd, Dn, Dm)    EMIT(VABD_gen(1, ((Dd)>>4)&1, 0, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+
+#define VPADAL_gen(D, size, Vd, op, Q, M, Vm)   (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (size)<<18 | (Vd)<<12 | 0b0110<<8 | (op)<<7 | (Q)<<6 | (M)<<5 | (Vm))
+// Add pair of U8 from Dm, Add result in U16 in Dd (some position as U8U8)
+#define VPADAL_U8(Dd, Dm)   EMIT(VPADAL_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 1, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of U16 from Dm, Add result in U32 in Dd
+#define VPADAL_U16(Dd, Dm)  EMIT(VPADAL_gen(((Dd)>>4)&1, 0b01, (Dd)&15, 1, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of U32 from Dm, Add result in U64 in Dd
+#define VPADAL_U32(Dd, Dm)  EMIT(VPADAL_gen(((Dd)>>4)&1, 0b10, (Dd)&15, 1, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S8 from Dm, Add result in S16 in Dd (some position as S8S8)
+#define VPADAL_S8(Dd, Dm)   EMIT(VPADAL_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S16 from Dm, Add result in S32 in Dd
+#define VPADAL_S16(Dd, Dm)  EMIT(VPADAL_gen(((Dd)>>4)&1, 0b01, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S32 from Dm, Add result in S64 in Dd
+#define VPADAL_S32(Dd, Dm)  EMIT(VPADAL_gen(((Dd)>>4)&1, 0b10, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of U8 from Dm, Add result in U16 in Dd (some position as U8U8)
+#define VPADALQ_U8(Dd, Dm)  EMIT(VPADAL_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 1, 1, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of U16 from Dm, Add result in U32 in Dd
+#define VPADALQ_U16(Dd, Dm) EMIT(VPADAL_gen(((Dd)>>4)&1, 0b01, (Dd)&15, 1, 1, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of U32 from Dm, Add result in U64 in Dd
+#define VPADALQ_U32(Dd, Dm) EMIT(VPADAL_gen(((Dd)>>4)&1, 0b10, (Dd)&15, 1, 1, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S8 from Dm, Add result in S16 in Dd (some position as S8S8)
+#define VPADALQ_S8(Dd, Dm)  EMIT(VPADAL_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S16 from Dm, Add result in S32 in Dd
+#define VPADALQ_S16(Dd, Dm) EMIT(VPADAL_gen(((Dd)>>4)&1, 0b01, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S32 from Dm, Add result in S64 in Dd
+#define VPADALQ_S32(Dd, Dm) EMIT(VPADAL_gen(((Dd)>>4)&1, 0b10, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+
+#define VPADDL_gen(D, size, Vd, op, Q, M, Vm)   (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (size)<<18 | (Vd)<<12 | 0b0010<<8 | (op)<<7 | (Q)<<6 | (M)<<5 | (Vm))
+// Add pair of U8, store result in U16
+#define VPADDL_U8(Dd, Dm)   EMIT(VPADDL_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 1, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of U16, store result in U32
+#define VPADDL_U16(Dd, Dm)  EMIT(VPADDL_gen(((Dd)>>4)&1, 0b01, (Dd)&15, 1, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of U32, store result in U64
+#define VPADDL_U32(Dd, Dm)  EMIT(VPADDL_gen(((Dd)>>4)&1, 0b10, (Dd)&15, 1, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S8, store result in S16
+#define VPADDL_S8(Dd, Dm)   EMIT(VPADDL_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S16, store result in S32
+#define VPADDL_S16(Dd, Dm)  EMIT(VPADDL_gen(((Dd)>>4)&1, 0b01, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S32, store result in S64
+#define VPADDL_S32(Dd, Dm)  EMIT(VPADDL_gen(((Dd)>>4)&1, 0b10, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of U8, store result in U16
+#define VPADDLQ_U8(Dd, Dm)  EMIT(VPADDL_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 1, 1, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of U16, store result in U32
+#define VPADDLQ_U16(Dd, Dm) EMIT(VPADDL_gen(((Dd)>>4)&1, 0b01, (Dd)&15, 1, 1, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of U32, store result in U64
+#define VPADDLQ_U32(Dd, Dm) EMIT(VPADDL_gen(((Dd)>>4)&1, 0b10, (Dd)&15, 1, 1, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S8, store result in S16
+#define VPADDLQ_S8(Dd, Dm)  EMIT(VPADDL_gen(((Dd)>>4)&1, 0b00, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S16, store result in S32
+#define VPADDLQ_S16(Dd, Dm) EMIT(VPADDL_gen(((Dd)>>4)&1, 0b01, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+// Add pair of S32, store result in S64
+#define VPADDLQ_S32(Dd, Dm) EMIT(VPADDL_gen(((Dd)>>4)&1, 0b10, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+
+#define VPADD_gen(D, size, Vn, Vd, N, Q, M, Vm)    (0b1111<<28 | 0b0010<<24 | (D)<<22 | (size)<<20 | (Vn)<<16 | (Vd)<<12 | 0b1011<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | 1<<4 | (Vm))
+#define VPADD_8(Dd, Dn, Dm)     EMIT(VPADD_gen(((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VPADD_16(Dd, Dn, Dm)    EMIT(VPADD_gen(((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VPADD_32(Dd, Dn, Dm)    EMIT(VPADD_gen(((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+// NO VPADDQ....
+
+#define VPADD_Fgen(D, size, Vn, Vd, N, Q, M, Vm)   (0b1111<<28 | 0b0011<<24 | (D)<<22 | (size)<<20 | (Vn)<<16 | (Vd)<<12 | 0b1101<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | 0<<4 | (Vm))
+// Add pair of F32, store result in F32
+#define VPADD_F32(Dd, Dn, Dm)   EMIT(VPADD_Fgen(((Dd)>>4)&1, 0, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+
+#define VMINMAX_gen(U, D, size, Vn, Vd, N, Q, M, op, Vm)    (0b1111<<28 | 0b001<<25 | (U)<<24 | (D)<<22 | (size)<<20 | (Vn)<<16 | (Vd)<<12 | 0b110<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | (op)<<4 | (Vm))
+#define VMIN_U8(Dd, Dn, Dm)     EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMIN_U16(Dd, Dn, Dm)    EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMIN_U32(Dd, Dn, Dm)    EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMIN_U64(Dd, Dn, Dm)    EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b11, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMIN_S8(Dd, Dn, Dm)     EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMIN_S16(Dd, Dn, Dm)    EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMIN_S32(Dd, Dn, Dm)    EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMIN_S64(Dd, Dn, Dm)    EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b11, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMINQ_U8(Dd, Dn, Dm)    EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMINQ_U16(Dd, Dn, Dm)   EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMINQ_U32(Dd, Dn, Dm)   EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMINQ_U64(Dd, Dn, Dm)   EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b11, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMINQ_S8(Dd, Dn, Dm)    EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMINQ_S16(Dd, Dn, Dm)   EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMINQ_S32(Dd, Dn, Dm)   EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMINQ_S64(Dd, Dn, Dm)   EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b11, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 1, (Dm)&15))
+#define VMAX_U8(Dd, Dn, Dm)     EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAX_U16(Dd, Dn, Dm)    EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAX_U32(Dd, Dn, Dm)    EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAX_U64(Dd, Dn, Dm)    EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b11, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAX_S8(Dd, Dn, Dm)     EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAX_S16(Dd, Dn, Dm)    EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAX_S32(Dd, Dn, Dm)    EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAX_S64(Dd, Dn, Dm)    EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b11, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAXQ_U8(Dd, Dn, Dm)    EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAXQ_U16(Dd, Dn, Dm)   EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAXQ_U32(Dd, Dn, Dm)   EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAXQ_U64(Dd, Dn, Dm)   EMIT(VMINMAX_gen(1, ((Dd)>>4)&1, 0b11, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAXQ_S8(Dd, Dn, Dm)    EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAXQ_S16(Dd, Dn, Dm)   EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAXQ_S32(Dd, Dn, Dm)   EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 0, (Dm)&15))
+#define VMAXQ_S64(Dd, Dn, Dm)   EMIT(VMINMAX_gen(0, ((Dd)>>4)&1, 0b11, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, 0, (Dm)&15))
+
+#define VRHADD_gen(U, D, size, Vn, Vd, N, Q, M, Vm) (0b1111<<28 | 1<<25 | (U)<<24 | (D)<<22 | (size)<<20 | (Vn)<<16 | (Vd)<<12 | 0b0001<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | (Vm))
+// Dd <= (Dn + Dm + 1)>>1
+#define VRHADD_U8(Dd, Dn, Dm)   EMIT(VRHADD_gen(1, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VRHADD_U16(Dd, Dn, Dm)  EMIT(VRHADD_gen(1, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VRHADD_U32(Dd, Dn, Dm)  EMIT(VRHADD_gen(1, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VRHADD_S8(Dd, Dn, Dm)   EMIT(VRHADD_gen(0, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VRHADD_S16(Dd, Dn, Dm)  EMIT(VRHADD_gen(0, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VRHADD_S32(Dd, Dn, Dm)  EMIT(VRHADD_gen(0, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VRHADDQ_U8(Dd, Dn, Dm)  EMIT(VRHADD_gen(1, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VRHADDQ_U16(Dd, Dn, Dm) EMIT(VRHADD_gen(1, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VRHADDQ_U32(Dd, Dn, Dm) EMIT(VRHADD_gen(1, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VRHADDQ_S8(Dd, Dn, Dm)  EMIT(VRHADD_gen(0, ((Dd)>>4)&1, 0b00, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VRHADDQ_S16(Dd, Dn, Dm) EMIT(VRHADD_gen(0, ((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VRHADDQ_S32(Dd, Dn, Dm) EMIT(VRHADD_gen(0, ((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+
+#define VQRDMULH_gen(D, size, Vn, Vd, N, Q, M, Vm)  (0b1111<<28 | 0b0011 <<24 | (D)<<22 | (size)<<20 | (Vn)<<16 | (Vd)<<12 | 0b1011<<8 | (N)<<7 | (Q)<<6 | (M)<<5 | (Vm))
+// Dd <= (2*Dn*Dm + 1<<(size-1))>>size
+#define VQRDMULH_S16(Dd, Dn, Dm)    EMIT(VQRDMULH_gen(((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VQRDMULH_S32(Dd, Dn, Dm)    EMIT(VQRDMULH_gen(((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VQRDMULHQ_S16(Dd, Dn, Dm)   EMIT(VQRDMULH_gen(((Dd)>>4)&1, 0b01, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VQRDMULHQ_S32(Dd, Dn, Dm)   EMIT(VQRDMULH_gen(((Dd)>>4)&1, 0b10, (Dn)&15, (Dd)&15, ((Dn)>>4)&1, 1, ((Dm)>>4)&1, (Dm)&15))
+
+#define VDUP_sgen(D, imm4, Vd, Q, M, Vm)    (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (imm4)<<16 | (Vd)<<12 | 0b1100<<8 | (Q)<<6 | (M)<<5 | (Vm))
+// Dd <= Dup(Dm[x])
+#define VDUP_32(Dd, Dm, x)      EMIT(VDUP_sgen(((Dd)>>4)&1, (((x)<<3)|0b100), (Dd)&15, 0, ((Dm)>>4)&1, (Dm)&15))
+
+#define VABS_vgen(D, size, Vd, F, Q, M, Vm) (0b1111<<28 | 0b0011<<24 | 1<<23 | (D)<<22 | 0b11<<20 | (size)<<18 | 0b01<<16 | (Vd)<<12 | (F)<<10 | 0b110<<7 | (Q)<<6 | (M)<<5 | (Vm))
+#define VABS_S32(Dd, Dm)        EMIT(VABS_vgen(((Dd)>>4)&1, 2, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VABS_S16(Dd, Dm)        EMIT(VABS_vgen(((Dd)>>4)&1, 1, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VABS_S8(Dd, Dm)         EMIT(VABS_vgen(((Dd)>>4)&1, 0, (Dd)&15, 0, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VABS_F(Dd, Dm)          EMIT(VABS_vgen(((Dd)>>4)&1, 2, (Dd)&15, 1, 0, ((Dm)>>4)&1, (Dm)&15))
+#define VABSQ_S32(Dd, Dm)       EMIT(VABS_vgen(((Dd)>>4)&1, 2, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VABSQ_S16(Dd, Dm)       EMIT(VABS_vgen(((Dd)>>4)&1, 1, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VABSQ_S8(Dd, Dm)        EMIT(VABS_vgen(((Dd)>>4)&1, 0, (Dd)&15, 0, 1, ((Dm)>>4)&1, (Dm)&15))
+#define VABSQ_F(Dd, Dm)         EMIT(VABS_vgen(((Dd)>>4)&1, 2, (Dd)&15, 1, 1, ((Dm)>>4)&1, (Dm)&15))
+
 #endif  //__ARM_EMITTER_H__
@@ -10,7 +10,16 @@
 arm_epilog:
    //update register -> emu
    //pop     {r0}
-    stm     r0, {r4-r12}   // put back reg value in emu, including EIP (so r12 must be EIP now)
+    stm     r0, {r4-r12,r14}   // put back reg value in emu, including EIP (so r14 must be EIP now)
+    //restore all used register
+    //vpop     {d8-d15}
+    pop     {r4-r11, pc}
+    //end, return...
+    //bx      lr
+
+
+.global arm_epilog_fast
+arm_epilog_fast:
    //restore all used register
    //vpop     {d8-d15}
    pop     {r4-r11, pc}
@@ -0,0 +1,594 @@
+; TYPE fields separated by spaces Assembler syntax
+; When there are mutiple assembler syntax (like for LDR (immediate)), separate them based on the bytes
+; E.G. for LDR (immediate), there are 3 lines with the 3 different asm syntaxes
+
+# Field options:
+# --------------
+# Syntax: ... field/coption1(coption2)* ... (inside fields)
+# Where each c correspond to the option character
+#  and optionN to the Nth option value
+# ---
+# c = '0'..'9'/'A'..'F': option=[01]
+# Force the cth bit (hex) of the field (starting from LSB) to be <option>
+# c = '=': option=[01x]{field_len}
+# Force the field to have the given bits (where x = anything, starts from MSB)
+
+# Post-fields option:
+# -------------------
+# Syntax: [fields] @ typeoption1 args1 typeoption2 args2 @ [Assembler syntax]
+# ---
+# typeoption contains '=' (l=r): args1=((.*) )?([^, ]*),([^, ]*),([^, ]*)@
+# Changes a value between two other depending on whether l == r
+
+# \2 is init (suffixed by ';', optional), \3 is set to \4 if true or \5 if false
+# (cf VMOV/VORR aka V\op\, VEOR/VBIF/VBIT/VBSL aka V\op\)
+
+# The 'true regex' is typeoption=([^= ]*)(=([^= ]*))+
+# args1=((.*) )?([^, ]*),(([^, ]*),)+([^, ]*)@
+# with the number of typeoption:\2 being equal to the number of args1:\4
+# <a>=<b>[=<c>...] <initialization> <variable-changed>,<changed-into-if-a=b>[,<changed-into-if-a=c>...],<changed-into-else>@
+
+# OR
+
+# typeoption is discarded and must be set to '=', args1=((.*) )?(@@ (( ?.*[^@])*)@ )+([^, ]*),(([^, ]*),)+([^, ]*)
+# \2 is init (suffixed by ';', optional), \6 is set to \7 if true or \8 if false
+# The difference with the simple switch is that \4 is the test (inside the `if`)
+# If there are multiple @@s, there are multiple `if`s (separated by `else`s)
+
+# The 'true regex' is [DISCARDED]typeoption==
+# args1=((.*) )?(@@ (( ?.*[^@])*)@ )+([^, ]*),([^, ]*),([^, ]*)
+# <.>=<.>[=<c>...] <initialization> @@ <test>@[ @@ <test2>@...] <variable-changed>,<changed-into-if-a=b>,<changed-into-else>
+
+# OR
+
+# args1=((.*) )?!@(( [^%]*[^%@])*)%(( ?[^%]*[^%@])*)@(( .*[^@])*)@(( .*[^@])*)@
+# Replaced by '\1; if (<equality>) { \3\7\5; } else { \3\9\5; }'
+# Meaning, <.=.> <initialization> !@ <common-left-part>%<common-right-part>@ <substitute-true>@ <substitute-false>@ <...>
+# (cf VMOV/VORR, aka V\op\ with the lastop variable)
+# You can also add more '=' with corresponding substitutes.
+# You can also add more '%' with corresponding substitutes.
+
+# ----
+# Inside the assembler syntax, you can add \var\ to mark a variable to be replaced
+# (Meaning, %s and `var` as argument to printf)
+# Full syntax: \\(%[0-9+]*.)?(.*)\\
+# If \1 != "", add \1 to the string in printf, and in any case append \2 as argument to printf
+
+! HACKS: (list of notable differences between the doc and this file)
+! ------
+! In theory, (0) and (1) bits are as important as 0 and 1:
+! > An instruction is UNPREDICTABLE if:
+! > • It is declared as UNPREDICTABLE in an instruction description or in this chapter.
+! > • The pseudocode for that encoding does not indicate that a different special case applies, and a bit marked (0)
+!     or (1) in the encoding diagram of an instruction is not 0 or 1 respectively.
+! - ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
+! In practice, they are ignored here.
+
+! SWP, SWPB, VMOV  (VFPU): Rt2 (field and assembly) -> Rn (field and assembly)
+! BKPT: must be AL, so cond (field) -> cond/=1110 (constrained field)
+! PKHBT and PKHTB: {, LSL/ASR #<imm>} (assembly) -> {, <shift>} (assembly)
+! PKHBT and PKHTB: immediate shift but shift & 1 -> ARMs (type)
+! All NEON operations (advanced SIMD): limited, so multiply the lines
+! VMOV (register): Vm ... Vm VMOV (field, assembly) -> Vn ... Vm @ m=n ...@ @ V\op\ (field, switchable var, assembly)
+! VMOV is VORR constrained -> (removed VORR)
+! VEOR, VBSL, VBIT, VBIF differ only depending on 2 bits: 0/1 0/1 ... VEOR -> @<2> ... @ ... @ V\op\ (field, switchable var, assembly)
+! Three registers of different lengths (when having L and W variants): op (field) -> Q (field)
+
+; ========== BEGINNING OF REGISTERED INSTRUCTIONS =========
+
+# This instruction changes the instruction set to Thumb! Disabled (but valid)
+#ARM_ 1 1 1 1 1 0 1 @<1> imm24 @ set imm24 = (imm24 << 2) + (param << 1)@ @ BLX <label>
+
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 op 0 N Q M 0 Vm VH\(op ? "SUB" : "ADD")\<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 0 0 N Q M 1 Vm VQADD<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 0 1 N Q M 0 Vm VRHADD<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 0 0 Vn Vd 0 0 0 1 N Q M 1 Vm VAND<c> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 0 1 Vn Vd 0 0 0 1 N Q M 1 Vm VBIC<c> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 1 0 Vn Vd 0 0 0 1 N Q M 1 Vm @ m=n const char* op op,"MOV","ORR"@ m=n char lastop[6] !@ %@ lastop[0] = '\0'@ sprintf(lastop, ", %s", vecname[(q << 5) + 0x20 + n])@ @ V\op\<c> <Qd>, <Qm>\lastop\
+NEON 1 1 1 1 0 0 1 0 0 D 1 1 Vn Vd 0 0 0 1 N Q M 1 Vm VORN<c> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D @<2> Vn Vd 0 0 0 1 N Q M 1 Vm @ param=0b00=0b01=0b10 const char* op op,"EOR","BSL","BIT","BIF"@ @ V\op\<c> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 1 0 N Q M 1 Vm VQSUB<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 1 1 N Q M op Vm @ op=0 const char* strict strict,"T","E"@ @ VCG\strict\<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 0 0 N Q M 0 Vm VSHL<c>.<dt> <Qd>, <Qm>, <Qn>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 0 0 N Q M 1 Vm VQSHL<c>.<dt> <Qd>, <Qm>, <Qn>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 0 1 N Q M 0 Vm VRSHL<c>.<dt> <Qd>, <Qm>, <Qn>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 0 1 N Q M 1 Vm VQRSHL<c>.<dt> <Qd>, <Qm>, <Qn>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 1 0 N Q M op Vm @ op=0 const char* opname opname,"MAX","MIN"@ @ V\opname\<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 1 1 N Q M 0 Vm VABD<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 1 1 N Q M 1 Vm VABA<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 op 0 D size Vn Vd 1 0 0 0 N Q M 0 Vm @ op=0 const char* opname opname,"ADD","SUB"@ @ V\opname\<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D size Vn Vd 1 0 0 0 N Q M 1 Vm VTST<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D size Vn Vd 1 0 0 0 N Q M 1 Vm VCEQ<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 1 0 0 1 N Q M 0 Vm @ set size = 8 << size@ @ VML\(u ? "S" : "A")\<c>.I\%dsize\ <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 1 0 0 1 N Q M 1 Vm VMUL<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 1 0 1 0 N Q M op Vm @ op=0 const char* opname opname,"MAX","MIN"@ @ VP\opname\<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D size Vn Vd 1 0 1 1 N Q M 0 Vm VQDMULH<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D size Vn Vd 1 0 1 1 N Q M 0 Vm VQRDMULH<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D size Vn Vd 1 0 1 1 N Q/=0 M 1 Vm VPADD<c>.<dt> <Dd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 0 0 D U sz/=0 Vn Vd 1 1 0 0 N Q M 1 Vm @ u=0 const char* y y,"A","S"@ @ VFM\y\<c>.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D U sz/=0 Vn Vd 1 1 0 1 N Q M 0 Vm @ u=0 const char* op op,"ADD","SUB"@ @ V\op\<c>.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D 0 sz/=0 Vn Vd 1 1 0 1 N Q/=0 M 0 Vm VPADD.F32 <Dd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 1 0 D 1 sz/=0 Vn Vd 1 1 0 1 N Q M 0 Vm VABD.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D op sz/=0 Vn Vd 1 1 0 1 N Q M 1 Vm VML\(op ? "S" : "A")\<c>.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D 0 sz/=0 Vn Vd 1 1 0 1 N Q M 1 Vm VMUL.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 0 sz/=0 Vn Vd 1 1 1 0 N Q M 0 Vm VCEQ.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D op sz/=0 Vn Vd 1 1 1 0 N Q M 0 Vm @ op=1 const char* strict strict,"T","E"@ @ VCG\strict\.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D op sz/=0 Vn Vd 1 1 1 0 N Q M 1 Vm @ op=1 const char* strict strict,"T","E"@ @ VACG\strict\.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D op sz/=0 Vn Vd 1 1 1 1 N Q M 0 Vm @ op=0 const char* opname opname,"MAX","MIN"@ @ V\opname\.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D op sz/=0 Vn Vd 1 1 1 1 N Q M 0 Vm @ op=0 const char* opname opname,"MAX","MIN"@ @ VP\opname\.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 0 sz/=0 Vn Vd 1 1 1 1 N Q M 1 Vm VRECPS.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 1 sz/=0 Vn Vd 1 1 1 1 N Q M 1 Vm VRSQRTS.F32 <Qd>, <Qn>, <Qm>
+INVALIDATE 1 1 1 1 0 0 1 <1> 0 <23>
+
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=0xx0 0 Q op/=0 1 imm4 VMOV<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=0xx1 0 Q op/=0 1 imm4 VORR<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=10x0 0 Q op/=0 1 imm4 VMOV<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=10x1 0 Q op/=0 1 imm4 VORR<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=11xx 0 Q op/=0 1 imm4 VMOV<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=0xx0 0 Q op/=1 1 imm4 VMVN<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=0xx1 0 Q op/=1 1 imm4 VBIC<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=10x0 0 Q op/=1 1 imm4 VMVN<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=10x1 0 Q op/=1 1 imm4 BIC<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=110x 0 Q op/=1 1 imm4 VMVN<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=1110 0 Q op/=1 1 imm4 VMOV<c>.<dt> <Qd>, #<imm>
+;INVALIDATE 1 1 1 1 0 0 1 <1> 1 <1> 0 0 0 <3> <4> <4>/=1111 0 <1> <1>/=1 1 <4>
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <1> 0 0 0 <11> 0 <2> 1 <4>
+
+# Special case for VMOVL (harder to do it on the documented place)
+NEON 1 1 1 1 0 0 1 0 1 D 0 0 1 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.S8 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D 0 1 0 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.S16 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D 1 0 0 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.S32 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 1 1 D 0 0 1 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.U8 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 1 1 D 0 1 0 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.U16 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 0 0 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.U32 <Qd>, <Dm>
+
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 0 0 0 0 L Q M 1 Vm VSHR<c>.<dt> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 0 0 0 1 L Q M 1 Vm VSRA<c>.<dt> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 0 0 1 0 L Q M 1 Vm VRSHR<c>.<dt> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 0 0 1 1 L Q M 1 Vm VRSRA<c>.<dt> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 1 1 D imm6 Vd 0 1 0 0 L Q M 1 Vm VSRI<c>.<size> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 0 1 D Imm6 Vd 0 1 0 1 L Q M 1 Vm VSHL<c>.I<size> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 1 1 D Imm6 Vd 0 1 0 1 L Q M 1 Vm VSLI<c>.<size> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D Imm6 Vd 0 1 1 op L Q M 1 Vm VQSHL\((u & op) ? "U" : "")\<c>.<dt> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 0 1 D imm6 Vd 1 0 0 0 0 0 M 1 Vm @ set ++size@ @ VSHRN<c>.I<size> <Dd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 0 1 D imm6 Vd 1 0 0 0 0 1 M 1 Vm VRSHRN<c>.I<size> <Dd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 1 0 0 op 0 0 M 1 Vm VQSHR\((u & op) ? "U" : "")\N<c>.<dt> <Dd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 1 0 0 op 0 1 M 1 Vm VQRSHR\((u & op) ? "U" : "")\N<c>.<dt> <Dd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 1 1 0 0 M 1 Vm VSHLL<c>.<dt> <Qd>, <Dm>, #\%d8 &l&l size\
+NEON 1 1 1 1 0 0 1 U 1 D Imm6 Vd 1 0 1 0 0 0 M 1 Vm VSHLL<c>.<dt> <Qd>, <Dm>, #<imm>
+; VCVT: if imm6 IN "0xxxxx" then UNDEFINED;
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <1> 0 <9> 1 1 1 <1> 0 <2> 1 <4>
+NEON 1 1 1 1 0 0 1 0 1 D IMM6 Vd 1 1 1 0 0 Q M 1 Vm VCVT<c>.F32.S32 <Qd>, <Qm>, #<fbits>
+NEON 1 1 1 1 0 0 1 0 1 D IMM6 Vd 1 1 1 1 0 Q M 1 Vm VCVT<c>.S32.F32 <Qd>, <Qm>, #<fbits>
+NEON 1 1 1 1 0 0 1 1 1 D IMM6 Vd 1 1 1 0 0 Q M 1 Vm VCVT<c>.F32.U32 <Qd>, <Qm>, #<fbits>
+NEON 1 1 1 1 0 0 1 1 1 D IMM6 Vd 1 1 1 1 0 Q M 1 Vm VCVT<c>.U32.F32 <Qd>, <Qm>, #<fbits>
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <18> 1 <4>
+
+NEON 1 1 1 1 0 0 1 0 1 D 1 1 Vn Vd IMM4 N Q M 0 Vm VEXT<c>.8 <Qd>, <Qn>, <Qm>, #<imm>
+
+# size + param < 3
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <2>/=11 0 0 <4> 0 0 0 <2> <2> 0 <4>
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <2>/=10 0 0 <4> 0 0 0 <2>/11 <2> 0 <4>
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <2>/=10 0 0 <4> 0 0 0 <2>/01 <2> 0 <4>
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <2>/=01 0 0 <4> 0 0 0 <2>/11 <2> 0 <4>
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <2>/=00 0 0 <4> 0 0 0 <2>/=11 <2> 0 <4>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 0 0 @<2> Q M 0 Vm VREV\%d16 &l&l param\<c>.\%d8 &l&l size\ <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 0 1 0 U Q M 0 Vm VPADDL<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 0 0 0 Q M 0 Vm VCLS<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 0 0 1 Q M 0 Vm VCLZ<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=00 0 0 Vd 0 1 0 1 0 Q M 0 Vm VCNT<c>.8 <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=00 0 0 Vd 0 1 0 1 1 Q M 0 Vm VMVN<c> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 1 0 U Q M 0 Vm VPADAL<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 1 1 0 Q M 0 Vm VQABS<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 1 1 1 Q M 0 Vm VQNEG<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 0 0 0 Q M 0 Vm VCGT<c>.<dt> <Qd>, <Qm>, #0
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 0 0 1 Q M 0 Vm VCGE<c>.<dt> <Qd>, <Qm>, #0
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 0 1 0 Q M 0 Vm VCEQ<c>.<dt> <Qd>, <Qm>, #0
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 0 1 1 Q M 0 Vm VCLE<c>.<dt> <Qd>, <Qm>, #0
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 1 0 0 Q M 0 Vm VCLT<c>.<dt> <Qd>, <Qm>, #0
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 1 1 0 Q M 0 Vm VABS<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 1 1 1 Q M 0 Vm VNEG<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=00 1 0 Vd 0 0 0 0 0 Q M 0 Vm VSWP<c> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 0 0 1 Q M 0 Vm VTRN<c>.\%d8 &l&l size\ <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 0 1 0 Q M 0 Vm VUZP<c>.\%d8 &l&l size\ <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 0 1 1 Q M 0 Vm VZIP<c>.\%d8 &l&l size\ <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 1 0 0 0 M 0 Vm VMOVN<c>.<dt> <Dd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 1 0 0 1 M 0 Vm VQMOVUN<c>.S\%d16 &l&l size\ <Dd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 1 0 1 U M 0 Vm @ set ++size@ @ VQMOVN<c>.<dt> <Dd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 1 1 0 0 M 0 Vm VSHLL<c>.I\%d8 &l&l size\ <Qd>, <Dm>, #\%d8 &l&l size\
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=01 1 0 Vd 0 1 1 0 0 0 M 0 Vm VCVT<c>.F16.F32 <Dd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=01 1 0 Vd 0 1 1 1 0 0 M 0 Vm VCVT<c>.F32.F16 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 1 Vd 0 1 0 F 0 Q M 0 Vm VRECPE<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 1 Vd 0 1 0 F 1 Q M 0 Vm VRSQRTE<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=10 1 1 Vd 0 1 1 0 0 Q M 0 Vm VCVT<c>.F32.S32 <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=10 1 1 Vd 0 1 1 0 1 Q M 0 Vm VCVT<c>.S32.F32 <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=10 1 1 Vd 0 1 1 1 0 Q M 0 Vm VCVT<c>.F32.U32 <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=10 1 1 Vd 0 1 1 1 1 Q M 0 Vm VCVT<c>.U32.F32 <Qd>, <Qm>
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <8> 0 <6> 0 <4>
+
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 Vn Vd 1 0 @<2> N op M 0 Vm @ param=0b00 char list[10] !@ sprintf(list, %)@ "{%s}", vecname[0x20 + n]@ "{%s-%s}", vecname[0x20 + n], vecname[0x20 + n + param]@ @ VTB\(op ? "X" : "L")\<c>.8 <Dd>, \list\, <Dm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 imm4 Vd 1 1 0 0 0 Q M 0 Vm VDUP<c>.\%dsize\ <Qd>, <Dm[x]>
+
+; size != 11
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <1> 1 1 <13> 0 <1> 0 <4>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 0 0 0 Q N 0 M 0 Vm VADD\(q ? "W" : "L")\<c>.<dt> <qd>, <Qn>, <Dm>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 0 0 1 Q N 0 M 0 Vm VSUB\(q ? "W" : "L")\<c>.<dt> <qd>, <Qn>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 0 1 0 0 N 0 M 0 Vm @ set size = 16 << size@ @ VADDHN<c>.I\%dsize\ <Dd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D size Vn Vd 0 1 0 0 N 0 M 0 Vm VRADDHN<c>.<dt> <Dd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 0 1 0 1 N 0 M 0 Vm VABAL<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 0 1 1 0 N 0 M 0 Vm VSUBHN<c>.<dt> <Dd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D size Vn Vd 0 1 1 0 N 0 M 0 Vm VRSUBHN<c>.<dt> <Dd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 0 1 1 1 N 0 M 0 Vm VABDL<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 1 0 op 0 N 0 M 0 Vm VML\(op ? "S" : "A")\L<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 1 0 op 1 N 0 M 0 Vm VQDML\(op ? "S" : "A")\L<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 1 1 0 0 N 0 M 0 Vm VMULL<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 1 1 0 1 N 0 M 0 Vm VQDMULL<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 U/=0 1 D size/=00 Vn Vd 1 1 1 0 N 0 M 0 Vm @ set uint8_t size = 0@ @ VMULL<c>.<dt> <Qd>, <Dn>, <Dm>
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <16> 0 <1> 0 <4>
+
+; Put after, otherwise some instructions are shadowed
+NEON 1 1 1 1 0 0 1 Q 1 D size Vn Vd 0 op 0 F N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VML\(op ? "S" : "A")\<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 0 op 1 0 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VML\(op ? "S" : "A")\L<c>.<dt> <Qd>, <Dn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 0 op 1 1 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VQDML\(op ? "S" : "A")\L<c>.<dt> <Qd>, <Dn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 Q 1 D size Vn Vd 1 0 0 F N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VMUL<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 1 0 1 0 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VMULL<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 1 0 1 1 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VQDMULL<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 Q 1 D size Vn Vd 1 1 0 0 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VQDMULH<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 Q 1 D size Vn Vd 1 1 0 1 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VQRDMULH<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <16> 0 <1> 0 <4>
+
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 0 size @<2> Rm @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 1 size @<2> Rm @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\], <Rm>
+;INVALIDATE 1 1 1 1 0 1 0 0 0 <1> 0 0 <22>
+INVALIDATE 1 1 1 1 0 1 0 0 1 <1> 0 0 <8> 1 1 <10>
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 0 @<4> 1 1 1 1 @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 0 @<4> 1 1 0 1 @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 0 @<4> Rm @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> Rm @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>]
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>]!
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> Rm @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> Rm @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\], <Rm>
+;INVALIDATE 1 1 1 1 0 1 0 0 1 <1> 0 0 <20>
+;INVALIDATE 1 1 1 1 0 1 0 0 <2> 0 0 <20>
+
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 0 size @<2> Rm @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 1 size @<2> Rm @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\], <Rm>
+;INVALIDATE 1 1 1 1 0 1 0 0 0 <1> 1 0 <22>
+INVALIDATE 1 1 1 1 0 1 0 0 1 <1> 1 0 <8> 1 1 <10>
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 0 @<4> 1 1 1 1 @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 0 @<4> 1 1 0 1 @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 0 @<4> Rm @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> Rm @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>]
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>]!
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> Rm @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> Rm @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\], <Rm>
+;INVALIDATE 1 1 1 1 0 1 0 0 1 <1> 1 0 <20>
+;INVALIDATE 1 1 1 1 0 1 0 0 <2> 1 0 <20>
+INVALIDATE 1 1 1 1 0 1 0 0 <3> 0 <20>
+
+; ===== No more 1 1 1 1 ..., so invalidate all of them ====
+INVALIDATE 1 1 1 1 <28>
+
+
+ARMS cond 0 0 0 0 0 0 0 S Rn Rd imm5 type 0 Rm AND{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 0 0 0 S Rd (0) (0) (0) (0) Rm 1 0 0 1 Rn MUL{S}<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 0 0 0 U 0 0 0 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm STRH<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 0 0 Rn Rt (0) (0) (0) (0) 1 1 0 1 Rm LDRD<c> <Rt>, <Rt2>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 0 0 Rn Rt (0) (0) (0) (0) 1 1 1 1 Rm STRD<c> <Rt>, <Rt2>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 0 1 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm LDRH<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 0 1 Rn Rt (0) (0) (0) (0) 1 1 0 1 Rm LDRSB<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 0 1 Rn Rt (0) (0) (0) (0) 1 1 1 1 Rm LDRSH<c> <Rt>, [<Rn>], +/-<Rm>
+ARMS cond 0 0 0 0 0 0 1 S Rn Rd imm5 type 0 Rm EOR{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 0 0 1 S Rd Ra Rm 1 0 0 1 Rn MLA{S}<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 0 U 0 1 0 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm STRHT<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 1 1 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm LDRHT<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 1 1 Rn Rt (0) (0) (0) (0) 1 1 0 1 Rm LDRSBT<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 1 1 Rn Rt (0) (0) (0) (0) 1 1 1 1 Rm LDRSHT<c> <Rt>, [<Rn>], +/-<Rm>
+ARMS cond 0 0 0 0 0 1 0 S Rn Rd imm5 type 0 Rm SUB{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 0 1 0 0 RdHi RdLo Rm 1 0 0 1 Rn UMAAL<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+ARM_ cond 0 0 0 0 U 1 0 0 Rn Rt imm4H 1 0 1 1 imm4L STRH<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 0 0 Rn Rt imm4H 1 1 0 1 imm4L LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 0 0 Rn Rt imm4H 1 1 1 1 imm4L STRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 0 1 Rn Rt imm4H 1 0 1 1 imm4L LDRH<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 0 1 Rn Rt imm4H 1 1 0 1 imm4L LDRSB<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 0 1 Rn Rt imm4H 1 1 1 1 imm4L LDRSH<c> <Rt>, [<Rn>], #+/-<imm8>
+ARMS cond 0 0 0 0 0 1 1 S Rn Rd imm5 type 0 Rm RSB{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 0 1 1 0 Rd Ra Rm 1 0 0 1 Rn MLS<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 0 U 1 1 0 Rn Rt imm4H 1 0 1 1 imm4L STRHT<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 1 1 Rn Rt imm4H 1 0 1 1 imm4L LDRHT<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 1 1 Rn Rt imm4H 1 1 0 1 imm4L LDRSBT<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 1 1 Rn Rt imm4H 1 1 1 1 imm4L LDRSHT<c> <Rt>, [<Rn>], #+/-<imm8>
+ARMS cond 0 0 0 0 1 0 0 S Rn Rd imm5 type 0 Rm ADD{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 1 0 0 S RdHi RdLo Rm 1 0 0 1 Rn UMULL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+ARMS cond 0 0 0 0 1 0 1 S Rn Rd imm5 type 0 Rm ADC{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 1 0 1 S RdHi RdLo Rm 1 0 0 1 Rn UMLAL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+ARMS cond 0 0 0 0 1 1 0 S Rn Rd imm5 type 0 Rm SBC{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 1 1 0 S RdHi RdLo Rm 1 0 0 1 Rn SMULL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+ARMS cond 0 0 0 0 1 1 1 S Rn Rd imm5 type 0 Rm RSC{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 1 1 1 S RdHi RdLo Rm 1 0 0 1 Rn SMLAL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+ARM_ cond 0 0 0 1 0 0 0 0 Rd Ra Rm 1 0 0 0 Rn SMLABB<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 1 0 0 0 0 Rd Ra Rm 1 0 1 0 Rn SMLATB<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 1 0 0 0 0 Rd Ra Rm 1 1 0 0 Rn SMLABT<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 1 0 0 0 0 Rd Ra Rm 1 1 1 0 Rn SMLATT<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 1 0 0 0 0 Rn Rt (0) (0) (0) (0) 1 0 0 1 Rm SWP<c> <Rt>, <Rm>, [<Rn>]
+ARM_ cond 0 0 0 1 U 0 W 0 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm STRH<c> <Rt>, [<Rn>, +/-<Rm>]{!}
+ARM_ cond 0 0 0 1 U 0 W 0 Rn Rt (0) (0) (0) (0) 1 1 0 1 Rm LDRD<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}
+ARM_ cond 0 0 0 1 U 0 W 0 Rn Rt (0) (0) (0) (0) 1 1 1 1 Rm STRD<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}
+ARMS cond 0 0 0 1 0 0 0 1 Rn (0) (0) (0) (0) imm5 type 0 Rm TST<c> <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 U 0 W 1 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm LDRH<c> <Rt>, [<Rn>, +/-<Rm>]{!}
+ARM_ cond 0 0 0 1 U 0 W 1 Rn Rt (0) (0) (0) (0) 1 1 0 1 Rm LDRSB<c> <Rt>, [<Rn>, +/-<Rm>]{!}
+ARM_ cond 0 0 0 1 U 0 W 1 Rn Rt (0) (0) (0) (0) 1 1 1 1 Rm LDRSH<c> <Rt>, [<Rn>, +/-<Rm>]{!}
+ARM_ cond 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 0 1 Rm BX<c> <Rm>
+ARM_ cond 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 0 Rm BXJ<c> <Rm>
+ARM_ cond 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 1 Rm BLX<c> <Rm>
+ARM_ cond/=1110 0 0 0 1 0 0 1 0 imm12 0 1 1 1 imm4 BKPT #<imm16>
+ARMS cond 0 0 0 1 0 0 1 1 Rn (0) (0) (0) (0) imm5 type 0 Rm TEQ<c> <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 0 1 0 0 Rn Rt (0) (0) (0) (0) 1 0 0 1 Rm SWPB<c> <Rt>, <Rm>, [<Rn>]
+ARM_ cond 0 0 0 1 U 1 W 0 Rn Rt imm4H 1 0 1 1 imm4L STRH<c> <Rt>, [<Rn>, #+/-<imm8>]{!}
+ARM_ cond 0 0 0 1 U 1 W 0 Rn Rt imm4H 1 1 0 1 imm4L LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm8>]{!}
+ARM_ cond 0 0 0 1 U 1 W 0 Rn Rt imm4H 1 1 1 1 imm4L STRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm8>]{!}
+ARMS cond 0 0 0 1 0 1 0 1 Rn (0) (0) (0) (0) imm5 type 0 Rm CMP<c> <Rn>, <Rm>{, <shift>}
+ARMS cond 0 0 0 1 0 1 1 1 Rn (0) (0) (0) (0) imm5 type 0 Rm CMN<c> <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 U 1 W 1 Rn Rt imm4H 1 0 1 1 imm4L LDRH<c> <Rt>, [<Rn>, #+/-<imm8>]{!}
+ARM_ cond 0 0 0 1 U 1 W 1 Rn Rt imm4H 1 1 0 1 imm4L LDRSB<c> <Rt>, [<Rn>, #+/-<imm8>]{!}
+ARM_ cond 0 0 0 1 U 1 W 1 Rn Rt imm4H 1 1 1 1 imm4L LDRSH<c> <Rt>, [<Rn>, #+/-<imm8>]{!}
+ARMS cond 0 0 0 1 1 0 0 S Rn Rd imm5 type 0 Rm ORR{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 1 0 0 0 Rn Rd (1) (1) (1) (1) 1 0 0 1 Rt STREX<c> <Rd>, <Rt>, [<Rn>]
+ARM_ cond 0 0 0 1 1 0 0 1 Rn Rt (1) (1) (1) (1) 1 0 0 1 (1) (1) (1) (1) LDREX<c> <Rt>, [<Rn>]
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd 0 0 0 0 0 0 0 0 Rm MOV{S}<c> <Rd>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd imm5 0 0 0 Rm LSL{S}<c> <Rd>, <Rm>, #<imm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd Rm 0 0 0 1 Rn LSL{S}<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd imm5 0 1 0 Rm LSR{S}<c> <Rd>, <Rm>, #<imm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd Rm 0 0 1 1 Rn LSR{S}<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd imm5 1 0 0 Rm ASR{S}<c> <Rd>, <Rm>, #<imm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd Rm 0 1 0 1 Rn ASR{S}<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd 0 0 0 0 0 1 1 0 Rm RRX{S}<c> <Rd>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd imm5 1 1 0 Rm ROR{S}<c> <Rd>, <Rm>, #<imm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd Rm 0 1 1 1 Rn ROR{S}<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 0 Rn Rd (1) (1) (1) (1) 1 0 0 1 Rt STREXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>]
+ARM_ cond 0 0 0 1 1 0 1 1 Rn Rt (1) (1) (1) (1) 1 0 0 1 (1) (1) (1) (1) LDREXD<c> <Rt>, <Rt2>, [<Rn>]
+ARMS cond 0 0 0 1 1 1 0 S Rn Rd imm5 type 0 Rm BIC{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 1 1 0 0 Rn Rd (1) (1) (1) (1) 1 0 0 1 Rt STREXB<c> <Rd>, <Rt>, [<Rn>]
+ARM_ cond 0 0 0 1 1 1 0 1 Rn Rt (1) (1) (1) (1) 1 0 0 1 (1) (1) (1) (1) LDREXB<c> <Rt>, [<Rn>]
+ARMS cond 0 0 0 1 1 1 1 S (0) (0) (0) (0) Rd imm5 type 0 Rm MVN{S}<c> <Rd>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 1 1 1 0 Rn Rd (1) (1) (1) (1) 1 0 0 1 Rt STREXH<c> <Rd>, <Rt>, [<Rn>]
+ARM_ cond 0 0 0 1 1 1 1 1 Rn Rt (1) (1) (1) (1) 1 0 0 1 (1) (1) (1) (1) LDREXH<c> <Rt>, [<Rn>]
+ARM_ cond 0 0 1 0 0 0 0 S Rn Rd imm12 AND{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 0 0 1 S Rn Rd imm12 EOR{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 0 1 0 S Rn Rd imm12 SUB{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 0 1 1 S Rn Rd imm12 RSB{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 1 0 0 S Rn Rd imm12 ADD{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 1 0 1 S Rn Rd imm12 ADC{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 1 1 0 S Rn Rd imm12 SBC{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 1 1 1 S Rn Rd imm12 RSC{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 1 0 0 0 0 imm4 Rd imm12 MOVW<c> <Rd>, #<imm16>
+ARM_ cond 0 0 1 1 0 0 0 1 Rn (0) (0) (0) (0) imm12 TST<c> <Rn>, #<const>
+ARM_ cond 0 0 1 1 0 0 1 0 0 0 0 0 (1) (1) (1) (1) (0) (0) (0) (0) 0 0 0 0 0 0 0 0 NOP<c>
+ARM_ cond 0 0 1 1 0 0 1 1 Rn (0) (0) (0) (0) imm12 TEQ<c> <Rn>, #<const>
+ARM_ cond 0 0 1 1 0 1 0 0 imm4 Rd imm12 MOVT<c> <Rd>, #<imm16>
+ARM_ cond 0 0 1 1 0 1 0 1 Rn (0) (0) (0) (0) imm12 CMP<c> <Rn>, #<const>
+ARM_ cond 0 0 1 1 0 1 1 1 Rn (0) (0) (0) (0) imm12 CMN<c> <Rn>, #<const>
+ARM_ cond 0 0 1 1 1 0 0 S Rn Rd imm12 ORR{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 1 1 0 1 S (0) (0) (0) (0) Rd imm12 MOV{S}<c> <Rd>, #<const>
+ARM_ cond 0 0 1 1 1 1 0 S Rn Rd imm12 BIC{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 1 1 1 1 S (0) (0) (0) (0) Rd imm12 MVN{S}<c> <Rd>, #<const>
+ARM_ cond 0 1 0 0 1 0 0 1 1 1 0 1 Rt 0 0 0 0 0 0 0 0 0 1 0 0 POP<c> {<Rt>}
+ARM_ cond 0 1 0 0 U 0 0 0 Rn Rt imm12 STR<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 0 0 1 Rn Rt imm12 LDR<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 0 1 0 Rn Rt imm12 STRT<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 0 1 1 Rn Rt imm12 LDRT<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 1 0 0 Rn Rt imm12 STRB<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 1 0 1 Rn Rt imm12 LDRB<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 1 1 0 Rn Rt imm12 STRBT<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 1 1 1 Rn Rt imm12 LDRBT<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 1 0 0 1 0 1 1 0 1 Rt 0 0 0 0 0 0 0 0 0 1 0 0 PUSH<c> {<Rt>}
+ARM_ cond 0 1 0 1 U 0 W 0 Rn Rt imm12 STR<c> <Rt>, [<Rn>, #+/-<imm12>]{!}
+ARM_ cond 0 1 0 1 U 0 W 1 Rn Rt imm12 LDR<c> <Rt>, [<Rn>, #+/-<imm12>]{!}
+ARM_ cond 0 1 0 1 U 1 W 0 Rn Rt imm12 STRB<c> <Rt>, [<Rn>, #+/-<imm12>]{!}
+ARM_ cond 0 1 0 1 U 1 W 1 Rn Rt imm12 LDRB<c> <Rt>, [<Rn>, #+/-<imm12>]{!}
+ARM_ cond 0 1 1 0 0 0 0 1 Rn Rd (1) (1) (1) (1) 0 1 0 1 Rm SSAX<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 0 0 0 0 1 Rn Rd (1) (1) (1) (1) 0 1 1 1 Rm SSUB16<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 0 0 0 0 1 Rn Rd (1) (1) (1) (1) 1 1 1 1 Rm SSUB8<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 0 0 1 0 1 Rn Rd (1) (1) (1) (1) 0 1 0 1 Rm USAX<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 0 0 1 0 1 Rn Rd (1) (1) (1) (1) 0 1 1 1 Rm USUB16<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 0 0 1 0 1 Rn Rd (1) (1) (1) (1) 1 1 1 1 Rm USUB8<c> <Rd>, <Rn>, <Rm>
+ARMs cond 0 1 1 0 1 0 0 0 Rn Rd imm5 0 0 1 Rm PKHBT<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARMs cond 0 1 1 0 1 0 0 0 Rn Rd imm5 1 0 1 Rm PKHTB<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 1 1 0 1 0 0 0 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm SXTB16<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 0 0 0 Rn Rd rotate (0) (0) 0 1 1 1 Rm SXTAB16<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARMs cond 0 1 1 0 1 0 1 sat_imm Rd imm5 sh 0 1 Rn SSAT<c> <Rd>, #<imm>, <Rn>{, <shift>}
+ARM_ cond 0 1 1 0 1 0 1 0 sat_imm Rd (1) (1) (1) (1) 0 0 1 1 Rn SSAT16<c> <Rd>, #<imm>, <Rn>
+ARM_ cond 0 1 1 0 1 0 1 0 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm SXTB<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 0 1 0 Rn Rd rotate (0) (0) 0 1 1 1 Rm SXTAB<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 0 1 1 (1) (1) (1) (1) Rd (1) (1) (1) (1) 0 0 1 1 Rm REV<c> <Rd>, <Rm>
+ARM_ cond 0 1 1 0 1 0 1 1 (1) (1) (1) (1) Rd (1) (1) (1) (1) 1 0 1 1 Rm REV16<c> <Rd>, <Rm>
+ARM_ cond 0 1 1 0 1 0 1 1 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm SXTH<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 0 1 1 Rn Rd rotate (0) (0) 0 1 1 1 Rm SXTAH<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 1 0 0 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm UXTB16<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 1 0 0 Rn Rd rotate (0) (0) 0 1 1 1 Rm UXTAB16<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARMs cond 0 1 1 0 1 1 1 sat_imm Rd imm5 sh 0 1 Rn USAT<c> <Rd>, #<imm>, <Rn>{, <shift>}
+ARM_ cond 0 1 1 0 1 1 1 0 sat_imm Rd (1) (1) (1) (1) 0 0 1 1 Rn USAT16<c> <Rd>, #<imm>, <Rn>
+ARM_ cond 0 1 1 0 1 1 1 0 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm UXTB<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 1 1 0 Rn Rd rotate (0) (0) 0 1 1 1 Rm UXTAB<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 1 1 1 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm UXTH<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 1 1 1 (1) (1) (1) (1) Rd (1) (1) (1) (1) 1 0 1 1 Rm REVSH<c> <Rd>, <Rm>
+ARM_ cond 0 1 1 0 1 1 1 1 Rn Rd rotate (0) (0) 0 1 1 1 Rm UXTAH<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARMs cond 0 1 1 0 U 0 0 0 Rn Rt imm5 type 0 Rm STR<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 0 0 1 Rn Rt imm5 type 0 Rm LDR<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 0 1 0 Rn Rt imm5 type 0 Rm STRT<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 0 1 1 Rn Rt imm5 type 0 Rm LDRT<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 1 0 0 Rn Rt imm5 type 0 Rm STRB<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 1 0 1 Rn Rt imm5 type 0 Rm LDRB<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 1 1 0 Rn Rt imm5 type 0 Rm STRBT<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 1 1 1 Rn Rt imm5 type 0 Rm LDRBT<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 1 U 0 W 0 Rn Rt imm5 type 0 Rm STR<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
+ARMs cond 0 1 1 1 U 0 W 1 Rn Rt imm5 type 0 Rm LDR<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
+ARMs cond 0 1 1 1 U 1 W 0 Rn Rt imm5 type 0 Rm STRB<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
+ARMs cond 0 1 1 1 U 1 W 1 Rn Rt imm5 type 0 Rm LDRB<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
+ARM_ cond 0 1 1 1 1 0 0 0 Rd 1 1 1 1 Rm 0 0 0 1 Rn USAD8<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 1 1 0 0 0 Rd Ra Rm 0 0 0 1 Rn USADA8<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 1 1 1 1 1 0 msb Rd lsb 0 0 1 1 1 1 1 BFC<c> <Rd>, #<lsb>, #<width>
+ARM_ cond 0 1 1 1 1 1 0 msb Rd lsb 0 0 1 Rn BFI<c> <Rd>, <Rn>, #<lsb>, #<width>
+ARM_ cond 0 1 1 1 1 1 1 widthm1 Rd lsb 1 0 1 Rn UBFX<c> <Rd>, <Rn>, #<lsb>, #<width>
+ARM_ cond 1 0 0 0 0 0 W 0 Rn/=1101 register_list STMED<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 0 0 W 0 Rn register_list STMDA<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 0 0 W 1 Rn/=1101 register_list LDMED<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 0 0 W 1 Rn register_list LDMDA<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 1 0 W 0 Rn/=1101 register_list STMEA<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 1 0 W 0 Rn register_list STM<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 1 0 0 1 Rn/=1101 register_list LDMEA<c> <Rn>, <registers>
+ARM_ cond 1 0 0 0 1 0 1 1 1 1 0 1 register_list @ = const char* op @@ (reglist != 0) && ((reglist & (reglist - 1)) == 0)@ op,"POP","LDMEA"@ @ \op\<c> <registers>
+ARM_ cond 1 0 0 0 1 0 W 1 Rn register_list LDM<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 0 0 0 0 Rn/=1101 register_list STMFD<c> <Rn>, <registers>
+ARM_ cond 1 0 0 1 0 0 1 0 1 1 0 1 register_list @ = const char* op @@ (reglist != 0) && ((reglist & (reglist - 1)) == 0)@ op,"PUSH","STMFD"@ @ \op\<c> <registers>
+ARM_ cond 1 0 0 1 0 0 W 0 Rn register_list STMDB<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 0 0 W 1 Rn/=1101 register_list LDMFD<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 0 0 W 1 Rn register_list LDMDB<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 1 0 W 0 Rn/=1101 register_list STMFA<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 1 0 W 0 Rn register_list STMIB<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 1 0 W 1 Rn/=1101 register_list LDMFA<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 1 0 W 1 Rn register_list LDMIB<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 1 0 imm24 B<c> <label>
+ARM_ cond 1 0 1 1 imm24 BL<c> <label>
+
+VFPU cond 1 1 0 0 0 1 0 0 Rn Rt 1 0 1 0 0 0 M 1 Vm VMOV<c> <Sm>, <Sm1>, <Rt>, <Rn>
+VFPU cond 1 1 0 0 0 1 0 1 Rn Rt 1 0 1 0 0 0 M 1 Vm VMOV<c> <Rt>, <Rn>, <Sm>, <Sm1>
+VFPU cond 1 1 0 0 0 1 0 0 Rn Rt 1 0 1 1 0 0 M 1 Vm VMOV<c> <Dm>, <Rt>, <Rn>
+VFPU cond 1 1 0 0 0 1 0 1 Rn Rt 1 0 1 1 0 0 M 1 Vm VMOV<c> <Rt>, <Rn>, <Dm>
+;INVALIDATE <4> 1 1 0 0 0 1 0 <9> 1 0 1 <9>
+
+INVALIDATE <4> 1 1 0 0 0 <11> 1 0 1 <9>
+INVALIDATE <4> 1 1 0 0 0 <11> 1 0 1 <9>
+INVALIDATE <4> 1 1 0 1 1 <1> 1 <9> 1 0 1 <9>
+INVALIDATE <4> 1 1 0 1 1 <1> 1 <9> 1 0 1 <9>
+VFPU cond 1 1 0 1 0 D 1 0 1 1 0 1 Vd 1 0 1 1 imm8/01 @ set --imm8@ @ FSTMX<c> <LIst>
+VFPU cond 1 1 0 1 0 D 1 0 1 1 0 1 Vd 1 0 1 sz imm8 VPUSH<c> <list>
+VFPU cond 1 1 0 1 U D 0 0 Rn Vd 1 0 1 sz imm8 VSTR<c> <Dd>, [<Rn>{, #+/-<imm>}]
+VFPU cond 1 1 0 @<2> D W 0 Rn Vd 1 0 1 1 imm8/01 @ set --imm8@ @ FSTM\(param == 0b01 ? "IA" : "DB")\X<c> <Rn>{!}, <LIst>
+VFPU cond 1 1 0 @<2> D W 0 Rn Vd 1 0 1 sz imm8 VSTM\(param == 0b01 ? "IA" : "DB")\<c> <Rn>{!}, <list>
+VFPU cond 1 1 0 0 1 D 1 1 1 1 0 1 Vd 1 0 1 1 imm8/01 @ set --imm8@ @ FLDMX<c> <LIst>
+VFPU cond 1 1 0 0 1 D 1 1 1 1 0 1 Vd 1 0 1 sz imm8 VPOP<c> <list>
+VFPU cond 1 1 0 1 0 D 0 1 1 1 1 1 Vd 1 0 1 sz 0 0 0 0 0 0 0 0 VLDR<c> <Dd>, [PC, #-0]
+VFPU cond 1 1 0 1 U D 0 1 1 1 1 1 Vd 1 0 1 sz imm8 VLDR<c> <Dd>, <label>
+VFPU cond 1 1 0 1 U D 0 1 Rn Vd 1 0 1 sz imm8 VLDR<c> <Dd>, [<Rn>{, #+/-<imm>}]
+VFPU cond 1 1 0 @<2> D W 1 Rn Vd 1 0 1 1 imm8/01 @ set --imm8@ @ FLDM\(param == 0b01 ? "IA" : "DB")\X<c> <Rn>{!}, <LIst>
+VFPU cond 1 1 0 @<2> D W 1 Rn Vd 1 0 1 sz imm8 VLDM\(param == 0b01 ? "IA" : "DB")\<c> <Rn>{!}, <list>
+INVALIDATE <4> 1 1 0 <25>
+
+INVALIDATE <4> 1 1 1 0 0 0 <1> 0 <8> 1 0 1 1 <1> 1 0 1 (0) (0) (0) (0)
+;INVALIDATE <4> 1 1 1 0 1 <2> 0 <8> 1 0 1 1 <1> 0 <1> 1 (0) (0) (0) (0)
+VFPU cond 1 1 1 0 0 0 0 0 Vn Rt 1 0 1 0 N (0) (0) 1 (0) (0) (0) (0) VMOV<c> <Sn>, <Rt>
+VFPU cond 1 1 1 0 1 1 1 0 0 0 0 1 Rt 1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0) VMSR<c> FPSCR, <Rt>
+VFPU cond 1 1 1 0 0 @<2> 0 Vd Rt 1 0 1 1 D @<2> 1 (0) (0) (0) (0) @ set uint8_t opc = (param1_2 << 2) + param2_2@ = uint8_t shift @@ (opc & 0b1000) == 0b1000@ @@ (opc & 0b1001) == 0b0001@ @@ (opc & 0b1011) == 0b0000@ shift,0,1,2,0xFF@ set uint8_t decodedImm = (opc & 0x7) >> shift@ @ VMOV<c>.\%d8 &l&l shift\ <Dd[x]>, <Rt>
+VFPU cond 1 1 1 0 1 0 Q 0 Vd Rt 1 0 1 1 D 0 0 1 (0) (0) (0) (0) VDUP<c>.32 <Qd>, <Rt>
+VFPU cond 1 1 1 0 1 0 Q 0 Vd Rt 1 0 1 1 D 0 1 1 (0) (0) (0) (0) VDUP<c>.16 <Qd>, <Rt>
+VFPU cond 1 1 1 0 1 1 Q 0 Vd Rt 1 0 1 1 D 0 0 1 (0) (0) (0) (0) VDUP<c>.8 <Qd>, <Rt>
+VFPU cond 1 1 1 0 0 0 0 1 Vn Rt 1 0 1 0 N (0) (0) 1 (0) (0) (0) (0) VMOV<c> <Rt>, <Sn>
+VFPU cond 1 1 1 0 1 1 1 1 0 0 0 1 Rt 1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0) VMRS<c> <Rt>, FPSCR
+VFPU cond 1 1 1 0 U @<2> 1 Vn Rt 1 0 1 1 N @<2> 1 (0) (0) (0) (0) @ set uint8_t opc = (u << 4) + (param1_2 << 2) + param2_2@ = uint8_t shift, size @@ (opc & 0b01000) == 0b01000@ @@ (opc & 0b01001) == 0b00001@ @@ (opc & 0b11011) == 0b00000@ shift,0,1,2,0xFF;size,0,1,2,4@ set uint8_t decodedImm = (opc & 0x7) >> shift@ @ VMOV<c>.<dt> <Rt>, <Dn[x]>
+INVALIDATE <4> 1 1 1 0 <12> 1 0 1 <4> 1 <4>
+
+VFPU cond 1 1 1 0 0 D 0 0 Vn Vd 1 0 1 sz N op M 0 Vm VML\(op ? "S" : "A")\<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 0 D 0 1 Vn Vd 1 0 1 sz N op M 0 Vm VNML\(op ? "S" : "A")\<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 0 D 1 0 Vn Vd 1 0 1 sz N 0 M 0 Vm VMUL<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 0 D 1 0 Vn Vd 1 0 1 sz N 1 M 0 Vm VNMUL<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 0 D 1 1 Vn Vd 1 0 1 sz N 0 M 0 Vm VADD<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 0 D 1 1 Vn Vd 1 0 1 sz N 1 M 0 Vm VSUB<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 1 D 0 0 Vn Vd 1 0 1 sz N 0 M 0 Vm VDIV<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 1 D 0 1 Vn Vd 1 0 1 sz N op M 0 Vm VFNM\(op ? "A" : "S")\<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 0 Vn Vd 1 0 1 sz N op M 0 Vm VFM\(op ? "S" : "A")\<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+
+!/VFPU cond 1 1 1 0 1 x 1 1 opc2 <4> 1 0 1 <1> - - <1> 0 opc4 Table A7-17
+VFPU cond 1 1 1 0 1 D 1 1 @<4> Vd 1 0 1 0 (0) 0 (0) 0 @<4> @ set int8_t sign = (param1_4 >> 3) ? -1 : 1@ set uint8_t exp = ((param1_4 & 0b111) ^ 0b100)@ set float mantissa = 16 + param2_4@ set float imm = sign * (1 << exp) * mantissa / 128.@ @ VMOV<c>.F32 <Sd>, #\%fimm\
+VFPU cond 1 1 1 0 1 D 1 1 @<4> Vd 1 0 1 1 (0) 0 (0) 0 @<4> @ set int8_t sign = (param1_4 >> 3) ? -1 : 1@ set uint8_t exp = ((param1_4 & 0b111) ^ 0b100)@ set double mantissa = 16 + param2_4@ set double imm = sign * (1 << exp) * mantissa / 128.@ @ VMOV<c>.F64 <Dd>, #\%fimm\
+VFPU cond 1 1 1 0 1 D 1 1 0 0 0 0 Vd 1 0 1 sz 0 1 M 0 Vm VMOV<c>.F\(size ? "64" : "32")\ <Dd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 0 0 0 0 Vd 1 0 1 sz 1 1 M 0 Vm VABS<c>.F\(size ? "64" : "32")\ <Dd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 0 0 0 1 Vd 1 0 1 sz 0 1 M 0 Vm VNEG<c>.F\(size ? "64" : "32")\ <Dd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 0 0 0 1 Vd 1 0 1 sz 1 1 M 0 Vm VSQRT<c>.F\(size ? "64" : "32")\ <Dd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 0 0 1 0 Vd 1 0 1 (0) @<1> 1 M 0 Vm VCVT\(param ? "T" : "B")\<c>.F32.F16 <Sd>, <Sm>
+VFPU cond 1 1 1 0 1 D 1 1 0 0 1 1 Vd 1 0 1 (0) @<1> 1 M 0 Vm VCVT\(param ? "T" : "B")\<c>.F16.F32 <Sd>, <Sm>
+VFPU cond 1 1 1 0 1 D 1 1 0 1 0 0 Vd 1 0 1 sz op 1 M 0 Vm VCMP\(op ? "E" : "")\<c>.F\(size ? "64" : "32")\ <Dd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 0 1 0 1 Vd 1 0 1 sz op 1 (0) 0 (0) (0) (0) (0) VCMP\(op ? "E" : "")\<c>.F\(size ? "64" : "32")\ <Dd>, #0.0
+VFPU cond 1 1 1 0 1 D 1 1 0 1 1 1 Vd 1 0 1 0 1 1 M 0 Vm VCVT<c>.F64.F32 <Dd>, <Sm>
+VFPU cond 1 1 1 0 1 D 1 1 0 1 1 1 Vd 1 0 1 1 1 1 M 0 Vm VCVT<c>.F32.F64 <Sd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 1 0 0 0 Vd 1 0 1 sz op 1 M 0 Vm VCVT<c>.F\(size ? "64" : "32")\.\(op ? "S" : "U")\32 <Dd>, <Sm>
+VFPU cond 1 1 1 0 1 D 1 1 1 0 1 U Vd 1 0 1 sz op 1 i 0 imm4 @ set uint8_t td = (u << 2) + op + 1@ td=0b001=0b010=0b101 const char* Td Td,"S16","U16","S32","U32"@ set imm5 = (16 << op) - (imm5 >> 4) - ((imm5 & 0xF) << 1)@ @ VCVT<c>.F\(size ? "64" : "32")\.\Td\ <Dd>, <Dd>, #<imm>
+VFPU cond 1 1 1 0 1 D 1 1 1 1 0 U Vd 1 0 1 sz op 1 M 0 Vm VCVT\(op ? "" : "R")\<c>.\(u ? "U" : "S")\32.F\(size ? "64" : "32")\ <Sd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 1 1 1 U Vd 1 0 1 sz op 1 i 0 imm4 @ set uint8_t td = (u << 2) + op + 1@ td=0b001=0b010=0b101 const char* Td Td,"S16","U16","S32","U32"@ set imm5 = (16 << op) - (imm5 >> 4) - ((imm5 & 0xF) << 1)@ @ VCVT<c>.\Td\.F\(size ? "64" : "32")\ <Dd>, <Dd>, #<imm>
+;INVALIDATE <4> 1 1 1 0 1 <1> 1 1 <8> 1 0 1 <4> 0 <4>
+;INVALIDATE <4> 1 1 1 0 <12> 1 0 1 <4> 0 <4>
+
+; ============= END OF REGISTERED INSTRUCTIONS ============
+INVALIDATE <32>
@@ -7,18 +7,33 @@
 .align 4

 .extern UpdateLinkTable
+.extern LinkNext

 .global arm_linker
 arm_linker:
    // emu is r0
+    stm     r0, {r4-r12,r14}   // put back reg value in emu, including EIP (easier debugging, and safer)
    // table offset is r1
-    // IP address is r12
-    push    {r0, r1, r12}
-    mov     r2, r12
+    // IP address is r14
+    push    {r0, r1, r12, r14}
+    mov     r2, r14
    // call the function
    bl      UpdateLinkTable
    // return offset is jump address
    mov     r3, r0
-    pop     {r0, r1, r12}
+    pop     {r0, r1, r12, r14}
+    bx      r3
+
+.global arm_next
+arm_next:
+    // emu is r0
+    //stm     r0, {r4-r12,r14}   // don't put put back reg value in emu, faster but more tricky to debug
+    // IP address is r1
+    push    {r0, r1, r12, r14}
+    // call the function
+    bl      LinkNext
+    // return offset is jump address
+    mov     r3, r0
+    pop     {r0, r1, r12, r14}
    bx      r3

@@ -0,0 +1,89 @@
+//arm lock helper
+//there is 2 part: read and write
+// write return 0 on success, 1 on fail (value has been changed)
+
+.text
+.align 4
+
+.global arm_lock_read_b
+.global arm_lock_write_b
+.global arm_lock_read_h
+.global arm_lock_write_h
+.global arm_lock_read_d
+.global arm_lock_write_d
+.global arm_lock_read_dd
+.global arm_lock_write_dd
+.global arm_lock_xchg
+.global arm_lock_storeifnull
+
+
+arm_lock_read_b:
+    // address is r0, return is r0
+    ldrexb  r0, [r0]
+    bx      lr
+
+arm_lock_write_b:
+    // address is r0, value is r1, return is r0
+    mov     r2, r0
+    strexb  r0, r1, [r2]
+    bx      lr
+
+arm_lock_read_h:
+    // address is r0, return is r0
+    ldrexh  r0, [r0]
+    bx      lr
+
+arm_lock_write_h:
+    // address is r0, value is r1, return is r0
+    mov     r2, r0
+    strexh  r0, r1, [r2]
+    bx      lr
+
+arm_lock_read_d:
+    // address is r0, return is r0
+    // r0 needs to be aligned
+    ldrex   r0, [r0]
+    bx      lr
+
+arm_lock_write_d:
+    // address is r0, value is r1, return is r0
+    // r0 needs to be aligned
+    mov     r2, r0
+    strex   r0, r1, [r2]
+    bx      lr
+
+arm_lock_read_dd:
+    // address is r2, return is r0, r1
+    ldrexd  r2, r3, [r2]
+    str     r2, [r0]
+    str     r3, [r1]
+    bx      lr
+
+arm_lock_write_dd:
+    // address is r2, value is r0, r1, return is r0
+    // r0 needs to be aligned
+    strexd  r3, r0, r1, [r2]
+    mov     r0, r3
+    bx      lr
+
+arm_lock_xchg:
+    // address is r0, value is r1, return old value in r0
+    // r0 needs to be aligned
+    ldrex   r2, [r0]
+    strex   r3, r1, [r0]
+    cmp     r3, #1
+    beq     arm_lock_xchg
+    mov     r0, r2
+    bx      lr
+
+arm_lock_storeifnull:
+    // address is r0, value is r1, r1 store to r0 only if [r0] is 0. return new [r0] value (so r1 or old value)
+    // r0 needs to be aligned
+    ldrex   r2, [r0]
+    cmp     r2, #0
+    moveq   r2, r1
+    strex   r3, r2, [r0]
+    cmp     r3, #1
+    beq     arm_lock_storeifnull
+    mov     r0, r2
+    bx      lr
@@ -0,0 +1,31 @@
+#ifndef __ARM_LOCK_HELPER__H__
+#define __ARM_LOCK_HELPER__H__
+#include <stdint.h>
+
+// LDREXB of ADDR
+extern uint8_t arm_lock_read_b(void* addr);
+// STREXB of ADDR, return 0 if ok, 1 if not
+extern int arm_lock_write_b(void* addr, uint8_t val);
+
+// LDREXH of ADDR
+extern uint16_t arm_lock_read_h(void* addr);
+// STREXH of ADDR, return 0 if ok, 1 if not
+extern int arm_lock_write_h(void* addr, uint16_t val);
+
+// LDREX of ADDR
+extern uint32_t arm_lock_read_d(void* addr);
+// STREX of ADDR, return 0 if ok, 1 if not
+extern int arm_lock_write_d(void* addr, uint32_t val);
+
+// LDREXD of ADDR
+extern void arm_lock_read_dd(uint32_t* a, uint32_t* b, void* addr);
+// STREX of ADDR, return 0 if ok, 1 if not
+extern int arm_lock_write_dd(uint32_t a, uint32_t b, void* addr);
+
+// Atomicaly exchange value at [p] with val, return old p
+extern uintptr_t arm_lock_xchg(void* p, uintptr_t val);
+
+// Atomicaly store value to [p] only if [p] is NULL. Return new [p] value (so val or old)
+extern void* arm_lock_storeifnull(void*p, void* val);
+
+#endif  //__ARM_LOCK_HELPER__H__
@@ -13,7 +13,7 @@ arm_prolog:
    //vpush     {d8-d15}
    //setup emu -> register
    //push     {r0}
-    ldm      r0, {r4-r11}    // all 8 register in direct access, no EIP (so r12 can be used as scratch)
+    ldm      r0, {r4-r12}    // all 8 register in direct access, plus flags, no EIP (so r14 can be used as scratch)
    //TODO
    //jump to function
    bx       r1
@@ -3,7 +3,6 @@
 #include <pthread.h>
 #include <errno.h>

-
 #include "debug.h"
 #include "box86context.h"
 #include "dynarec.h"
@@ -17,163 +16,448 @@
 #include "x86trace.h"
 #include "dynablock.h"
 #include "dynablock_private.h"
+#include "dynarec_private.h"
 #include "elfloader.h"
 #ifdef ARM
 #include "dynarec_arm.h"
+#include "arm_lock_helper.h"
 #else
 #error Unsupported architecture!
 #endif
-
+#include "custommem.h"
 #include "khash.h"

 KHASH_MAP_INIT_INT(dynablocks, dynablock_t*)

-
-dynablocklist_t* NewDynablockList(uintptr_t base, uintptr_t text, int textsz)
+uint32_t X31_hash_code(void* addr, int len)
 {
+    if(!len) return 0;
+    uint8_t* p = (uint8_t*)addr;
+	int32_t h = *p;
+	for (--len, ++p; len; --len, ++p) h = (h << 5) - h + (int32_t)*p;
+	return (uint32_t)h;
+}
+
+dynablocklist_t* NewDynablockList(uintptr_t text, int textsz, int nolinker, int direct)
+{
+    if(!textsz) {
+        printf_log(LOG_NONE, "Error, creating a NULL sized Dynablock\n");
+        return NULL;
+    }
    dynablocklist_t* ret = (dynablocklist_t*)calloc(1, sizeof(dynablocklist_t));
-    ret->blocks = kh_init(dynablocks);
-    ret->base = base;
    ret->text = text;
    ret->textsz = textsz;
-    pthread_rwlock_init(&ret->rwlock_blocks, NULL);
-
+    ret->nolinker = nolinker;
+    if(direct && textsz) {
+        ret->direct = (dynablock_t**)calloc(textsz, sizeof(dynablock_t*));
+        if(!ret->direct) {printf_log(LOG_NONE, "Warning, fail to create direct block for dynablock @%p\n", (void*)text);}
+    }
    return ret;
 }

+void FreeDynablock(dynablock_t* db)
+{
+    if(db) {
+        dynarec_log(LOG_DEBUG, "FreeDynablock(%p), db->block=%p x86=%p:%p father=%p, tablesz=%d, with %d son(s) already gone=%d\n", db, db->block, db->x86_addr, db->x86_addr+db->x86_size, db->father, db->tablesz, db->sons_size, db->gone);
+        if(db->gone)
+            return; // already in the process of deletion!
+        db->done = 0;
+        db->gone = 1;
+        // remove from direct if there
+        uintptr_t startdb = db->parent->text;
+        uintptr_t enddb = db->parent->text + db->parent->textsz;
+        if(db->parent->direct) {
+            uintptr_t addr = (uintptr_t)db->x86_addr;
+            if(addr>=startdb && addr<enddb)
+                db->parent->direct[addr-startdb] = NULL;
+        }
+        // remove and free the sons
+        for (int i=0; i<db->sons_size; ++i) {
+            dynablock_t *son = (dynablock_t*)arm_lock_xchg(&db->sons[i], 0);
+            FreeDynablock(son);
+        }
+        // only the father free the DynarecMap
+        if(!db->father) {
+            dynarec_log(LOG_DEBUG, " -- FreeDyrecMap(%p, %d)\n", db->block, db->size);
+            FreeDynarecMap(db, (uintptr_t)db->block, db->size);
+        }
+        free(db->sons);
+        free(db->table);
+        free(db->instsize);
+        free(db);
+    }
+}
+
 void FreeDynablockList(dynablocklist_t** dynablocks)
 {
    if(!dynablocks)
        return;
    if(!*dynablocks)
        return;
-    dynarec_log(LOG_INFO, "Free %d Blocks from Dynablocklist (with %d buckets)%s\n", kh_size((*dynablocks)->blocks), kh_n_buckets((*dynablocks)->blocks), ((*dynablocks)->direct)?" With Direct mapping enabled":"");
-    dynablock_t* db;
-    kh_foreach_value((*dynablocks)->blocks, db,
-        free(db->table);
-        free(db);
-    );
-    kh_destroy(dynablocks, (*dynablocks)->blocks);
-    if((*dynablocks)->direct)
+    dynarec_log(LOG_DEBUG, "Free Direct Blocks %p from Dynablocklist nolinker=%d\n", (*dynablocks)->direct, (*dynablocks)->nolinker);
+    if((*dynablocks)->direct) {
+        for (int i=0; i<(*dynablocks)->textsz; ++i) {
+            if((*dynablocks)->direct[i] && !(*dynablocks)->direct[i]->father) 
+                FreeDynablock((*dynablocks)->direct[i]);
+        }
        free((*dynablocks)->direct);
-    (*dynablocks)->direct = 0;
-
-    pthread_rwlock_destroy(&(*dynablocks)->rwlock_blocks);
+    }
+    (*dynablocks)->direct = NULL;

    free(*dynablocks);
    *dynablocks = NULL;
 }

-void ConvertHash2Direct(dynablocklist_t* dynablocks)
+void MarkDynablock(dynablock_t* db)
 {
-    if(dynablocks->textsz==0 || dynablocks->text==0)
-        return; // nothing to do
-    // create the new set
-    dynablock_t **direct = (dynablock_t**)calloc(dynablocks->textsz, sizeof(dynablock_t*));
-    kh_dynablocks_t *blocks = kh_init(dynablocks);
-    // transfert
-    int ret;
-    khint_t k;
+    if(db) {
+        if(db->father)
+            db = db->father;    // mark only father
+        if(db->nolinker)
+            db->need_test = 1;  // test only blocks that can be marked (and so deleted)
+    }
+}
+
+void ProtectDynablock(dynablock_t* db)
+{
+    if(db) {
+        if(db->father)
+            return;    // protect only father, child(ren) will be automatically
+        protectDB((uintptr_t)db->x86_addr, db->x86_size);
+    }
+}
+
+void MarkDynablockList(dynablocklist_t** dynablocks)
+{
+    if(!dynablocks)
+        return;
+    if(!*dynablocks)
+        return;
+    if(!(*dynablocks)->nolinker)
+        return;
+    dynarec_log(LOG_DEBUG, "Marked Blocks from Dynablocklist nolinker=%d %p:0x%x\n", (*dynablocks)->nolinker, (void*)(*dynablocks)->text, (*dynablocks)->textsz);
    dynablock_t* db;
-    uintptr_t key;
-    uintptr_t start = dynablocks->text-dynablocks->base;
-    uintptr_t end = dynablocks->text + dynablocks->textsz-dynablocks->base;
-    kh_foreach(dynablocks->blocks, key, db,
-        if(key>=start && key<end)
-            direct[key-start] = db;
-        else {
-            k = kh_put(dynablocks, blocks, key, &ret);
-            if(ret) {   // don't try to insert if already done...
-                kh_value(blocks, k) = db;
-            }
+    if((*dynablocks)->direct) {
+        for (int i=0; i<(*dynablocks)->textsz; ++i) {
+            db = (*dynablocks)->direct[i];
+            if(db)
+                MarkDynablock(db);
        }
-    );
-    // destroy old and do the swap (should swap before destroy, but hash access is always behind mutex)
-    kh_destroy(dynablocks, dynablocks->blocks);
-    dynablocks->blocks = blocks;
-    dynablocks->direct = direct;
+    }
+}
+
+void ProtectDynablockList(dynablocklist_t** dynablocks)
+{
+    if(!dynablocks)
+        return;
+    if(!*dynablocks)
+        return;
+    dynarec_log(LOG_DEBUG, "Protect Blocks from Dynablocklist nolinker=%d %p:0x%x\n", (*dynablocks)->nolinker, (void*)(*dynablocks)->text, (*dynablocks)->textsz);
+    dynablock_t* db;
+    if((*dynablocks)->direct) {
+        for (int i=0; i<(*dynablocks)->textsz; ++i) {
+            db = (*dynablocks)->direct[i];
+            if(db)
+                ProtectDynablock(db);
+        }
+    }
+}
+
+uintptr_t StartDynablockList(dynablocklist_t* db)
+{
+    if(db)
+        return db->text;
+    return 0;
+}
+uintptr_t EndDynablockList(dynablocklist_t* db)
+{
+    if(db)
+        return db->text+db->textsz-1;
+    return 0;
+}
+
+int IntervalIntersects(uintptr_t start1, uintptr_t end1, uintptr_t start2, uintptr_t end2)
+{
+    if(start1 > end2 || start2 > end1)
+        return 0;
+    return 1;
+}
+
+void MarkDirectDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t size)
+{
+    if(!dynablocks)
+        return;
+    if(!dynablocks->nolinker || !dynablocks->direct)
+        return;
+    uintptr_t startdb = dynablocks->text;
+    uintptr_t enddb = startdb + dynablocks->textsz -1;
+    int maxsz = dynablocks->maxsz;
+    uintptr_t start = addr - maxsz;
+    uintptr_t end = addr+size-1;
+    if(start<startdb)
+        start = startdb;
+    if(end>enddb)
+        end = enddb;
+    dynablock_t *db;
+    if(end>startdb && start<enddb)
+        for(uintptr_t i = start; i<end; ++i)
+            if((db=dynablocks->direct[i-startdb]))
+                if(IntervalIntersects((uintptr_t)db->x86_addr, (uintptr_t)db->x86_addr+db->x86_size-1, addr, addr+size+1))
+                    MarkDynablock(db);
+}
+
+void ProtectDirectDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t size)
+{
+    if(!dynablocks)
+        return;
+    uintptr_t startdb = dynablocks->text;
+    uintptr_t enddb = startdb + dynablocks->textsz;
+    uintptr_t start = addr;
+    uintptr_t end = addr+size;
+    if(start<startdb)
+        start = startdb;
+    if(end>enddb)
+        end = enddb;
+    if(end>startdb && start<enddb)
+        protectDB(start, end-start); //no +1; as end/enddb is exclusive and not inclusive
+}
+
+void FreeRangeDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t size)
+{
+    if(!dynablocks)
+        return;
+
+    if(dynablocks->direct) {
+        dynablock_t* db;
+        int ret;
+        khint_t k;
+        kh_dynablocks_t *blocks = kh_init(dynablocks);
+        // copy in a temporary list
+        if(dynablocks->direct) {
+            uintptr_t startdb = dynablocks->text;
+            uintptr_t enddb = startdb + dynablocks->textsz;
+            uintptr_t start = addr;
+            uintptr_t end = addr+size;
+            if(start<startdb)
+                start = startdb;
+            if(end>enddb)
+                end = enddb;
+            if(end>startdb && start<enddb)
+                for(uintptr_t i = start; i<end; ++i) {
+                    db = (dynablock_t*)arm_lock_xchg(&dynablocks->direct[i-startdb], 0);
+                    if(db) {
+                        if(db->father)
+                            db = db->father;
+                        if(db->parent==dynablocks) {
+                            k = kh_put(dynablocks, blocks, (uintptr_t)db, &ret);
+                            kh_value(blocks, k) = db;
+                        }
+                    }
+                }
+        }
+        // purge the list
+        kh_foreach_value(blocks, db,
+            FreeDynablock(db);
+        );
+        kh_destroy(dynablocks, blocks);
+    }
+}
+void MarkRangeDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t size)
+{
+    if(!dynablocks)
+        return;
+    if(!dynablocks->nolinker)
+        return;
+    if(dynablocks->direct) {
+        MarkDirectDynablock(dynablocks, addr, size);
+        // the blocks check before
+        for(int idx=(addr-dynablocks->maxsz)>>DYNAMAP_SHIFT; idx<addr>>DYNAMAP_SHIFT; ++idx)
+            MarkDirectDynablock(getDB(idx), addr, size);
+    }
+}
+
+dynablock_t* FindDynablockDynablocklist(void* addr, kh_dynablocks_t* dynablocks)
+{
+    if(!dynablocks)
+        return NULL;
+    dynablock_t* db;
+    kh_foreach_value(dynablocks, db, 
+        uintptr_t s = (uintptr_t)db->block;
+        uintptr_t e = (uintptr_t)db->block+db->size;
+        if((uintptr_t)addr>=s && (uintptr_t)addr<e)
+            return db->father?db->father:db;
+    )
+    return NULL;
+}
+
+static dynablocklist_t* getDBFromAddress(uintptr_t addr)
+{
+    const int idx = (addr>>DYNAMAP_SHIFT);
+    return getDB(idx);
+}
+
+dynablock_t *AddNewDynablock(dynablocklist_t* dynablocks, uintptr_t addr, int* created)
+{
+    if(!dynablocks) {
+        dynarec_log(LOG_INFO, "Warning: Ask to create a dynablock with a NULL dynablocklist (addr=%p)\n", (void*)addr);
+        *created = 0;
+        return NULL;
+    }
+    if((addr<dynablocks->text) || (addr>=(dynablocks->text+dynablocks->textsz))) {
+        // this should be useless
+        //dynarec_log(LOG_INFO, "Warning: Refused to create a Direct Block that is out-of-bound: dynablocks=%p (%p:%p), addr=%p\n", dynablocks, (void*)(dynablocks->text), (void*)(dynablocks->text+dynablocks->textsz), (void*)addr);
+        //*created = 0;
+        //return NULL;
+        return AddNewDynablock(getDBFromAddress(addr), addr, created);
+    }
+    dynablock_t* block = NULL;
+    // first, check if it exist in direct access mode
+    if(dynablocks->direct) {
+        block = dynablocks->direct[addr-dynablocks->text];
+        if(block) {
+            dynarec_log(LOG_DUMP, "Block already exist in Direct Map\n");
+            *created = 0;
+            return block;
+        }
+    }
+    
+    if (!*created)
+        return block;
+    
+    if(!dynablocks->direct)
+        dynablocks->direct = (dynablock_t**)calloc(dynablocks->textsz, sizeof(dynablock_t*));
+
+    // create and add new block
+    dynarec_log(LOG_DUMP, "Ask for DynaRec Block creation @%p\n", (void*)addr);
+
+    block = (dynablock_t*)calloc(1, sizeof(dynablock_t));
+    dynablock_t* tmp = (dynablock_t*)arm_lock_storeifnull(&dynablocks->direct[addr-dynablocks->text], block);
+    if(tmp !=  block) {
+        // a block appeard!
+        free(block);
+        *created = 0;
+        return tmp;
+    }
+
+    block->parent = dynablocks;
+
+    *created = 1;
+    return block;
 }

-#define MAGIC_SIZE 256
 /* 
    return NULL if block is not found / cannot be created. 
    Don't create if create==0
 */
-dynablock_t* DBGetBlock(x86emu_t* emu, uintptr_t addr, int create, dynablock_t* current)
+static dynablock_t* internalDBGetBlock(x86emu_t* emu, uintptr_t addr, uintptr_t filladdr, int create, dynablock_t* current)
 {
    // try the quickest way first: get parent of current and check if ok!
    dynablocklist_t *dynablocks = NULL;
    dynablock_t* block = NULL;
    if(current) {
-        dynablocks = current->parent;    
-        if(dynablocks->direct && addr>=dynablocks->text && addr<=dynablocks->text+dynablocks->textsz) {
-            block = dynablocks->direct[addr-dynablocks->text];
-            if(block)
-                return block;
-        }
-        if(!(addr>=dynablocks->text && addr<=dynablocks->text+dynablocks->textsz))
+        dynablocks = current->parent;
+        if(dynablocks && !(addr>=dynablocks->text && addr<(dynablocks->text+dynablocks->textsz)))
            dynablocks = NULL;
    }
    // nope, lets do the long way
-    if(!dynablocks)
-        dynablocks = GetDynablocksFromAddress(emu->context, addr);
-    if(!dynablocks)
-        return NULL;
-    // check direct first, without lock
-    if(dynablocks->direct && addr>=dynablocks->text && addr<=dynablocks->text+dynablocks->textsz)
-        block = dynablocks->direct[addr-dynablocks->text];
-    if(block)
-        return block;
-    // nope, put rwlock in read mode and check hash
-    pthread_rwlock_rdlock(&dynablocks->rwlock_blocks);
-    // but first, check again just in case it has been created while waiting for mutex
-    if(dynablocks->direct && addr>=dynablocks->text && addr<=dynablocks->text+dynablocks->textsz)
-        block = dynablocks->direct[addr-dynablocks->text];
-    if(block) {
-        pthread_rwlock_unlock(&dynablocks->rwlock_blocks);
-        return block;
-    }
-    // check if the block exist
-    int ret;
-    khint_t k = kh_get(dynablocks, dynablocks->blocks, addr-dynablocks->base);
-    if(k!=kh_end(dynablocks->blocks)) {
-        /*atomic_store(&dynalock, 0);*/
-        block = kh_value(dynablocks->blocks, k);
-        pthread_rwlock_unlock(&dynablocks->rwlock_blocks);
-        return block;
-    }
-    // unlock now
-    pthread_rwlock_unlock(&dynablocks->rwlock_blocks);
-    // Blocks doesn't exist. If creation is not allow, just return NULL
-    if(!create)
-        return block;
-    // Lock as write now!
-    pthread_rwlock_wrlock(&dynablocks->rwlock_blocks);
-    // create and add new block
-    dynarec_log(LOG_DEBUG, "Ask for DynaRec Block creation @%p\n", addr);
-    if(dynablocks->direct && addr>=dynablocks->text && addr<=dynablocks->text+dynablocks->textsz)
-    {
-        block = dynablocks->direct[addr-dynablocks->text] = (dynablock_t*)calloc(1, sizeof(dynablock_t));
-    } else {
-        k = kh_put(dynablocks, dynablocks->blocks, addr-dynablocks->base, &ret);
-        if(!ret) {
-            // Ooops, block is already there? retreive it and bail out
-            block = kh_value(dynablocks->blocks, k);    
-            pthread_rwlock_unlock(&dynablocks->rwlock_blocks);
-            return block;
+    if(!dynablocks) {
+        dynablocks = getDBFromAddress(addr);
+        if(!dynablocks) {
+            dynablocks = GetDynablocksFromAddress(emu->context, addr);
+            if(!dynablocks)
+                return NULL;
        }
-        block = kh_value(dynablocks->blocks, k) = (dynablock_t*)calloc(1, sizeof(dynablock_t));
-        // check if size of hash map == magic size, if yes, convert to direct before unlocking
-        if(!dynablocks->direct && kh_size(dynablocks->blocks)==MAGIC_SIZE)
-            ConvertHash2Direct(dynablocks);
    }
-    block->parent = dynablocks;
-    // create an empty block first, so if other thread want to execute the same block, they can, but using interpretor path
-    pthread_rwlock_unlock(&dynablocks->rwlock_blocks);
+    // check direct first, without lock
+    if(dynablocks->direct/* && (addr>=dynablocks->text) && (addr<(dynablocks->text+dynablocks->textsz))*/)
+        if((block = dynablocks->direct[addr-dynablocks->text]))
+            return block;

+    int created = create;
+    block = AddNewDynablock(dynablocks, addr, &created);
+    if(!created)
+        return block;   // existing block...
+
+    if(box86_dynarec_dump)
+        pthread_mutex_lock(&my_context->mutex_dyndump);
    // fill the block
-    FillBlock(emu, block, addr);
-    dynarec_log(LOG_DEBUG, " --- DynaRec Block created @%p (%p, 0x%x bytes)\n", addr, block->block, block->size);
+    block->x86_addr = (void*)addr;
+    if(!FillBlock(block, filladdr)) {
+        void* old = (void*)arm_lock_xchg(&dynablocks->direct[addr-dynablocks->text], 0);
+        if(old!=block) {// put it back in place, strange things are happening here!
+            dynarec_log(LOG_NONE, "Warning, a wild block appeared at %p: %p\n", (void*)addr, old);
+            arm_lock_xchg(&dynablocks->direct[addr-dynablocks->text], (uintptr_t)old);
+        }
+        free(block);
+        block = NULL;
+    }
+    if(box86_dynarec_dump)
+        pthread_mutex_unlock(&my_context->mutex_dyndump);
+    // check size
+    if(block) {
+        int blocksz = block->x86_size;
+        if(dynablocks->maxsz<blocksz) {
+            dynablocks->maxsz = blocksz;
+            for(int idx=(addr>>DYNAMAP_SHIFT)+1; idx<=((addr+blocksz)>>DYNAMAP_SHIFT); ++idx) {
+                dynablocklist_t* dblist;
+                if((dblist = getDB(idx)))
+                    if(dblist->maxsz<blocksz)
+                        dblist->maxsz = blocksz;
+            }
+        }
+
+        if(block->parent->nolinker)
+            protectDB((uintptr_t)block->x86_addr, block->x86_size);
+    }
+
+    dynarec_log(LOG_DEBUG, " --- DynaRec Block %s @%p:%p (%p, 0x%x bytes, with %d son(s))\n", created?"created":"recycled", (void*)addr, (void*)(addr+((block)?block->x86_size:0)), (block)?block->block:0, (block)?block->size:0, (block)?block->sons_size:0);

    return block;
 }
+
+dynablock_t* DBGetBlock(x86emu_t* emu, uintptr_t addr, int create, dynablock_t** current)
+{
+    dynablock_t *db = internalDBGetBlock(emu, addr, addr, create, *current);
+    if(db && (db->need_test || (db->father && db->father->need_test))) {
+        dynablock_t *father = db->father?db->father:db;
+        uint32_t hash = father->nolinker?X31_hash_code(father->x86_addr, father->x86_size):0;
+        if(hash!=father->hash) {
+            dynarec_log(LOG_DEBUG, "Invalidating block %p from %p:%p (hash:%X/%X) with %d son(s)\n", father, father->x86_addr, father->x86_addr+father->x86_size, hash, father->hash, father->sons_size);
+            // no more current if it gets invalidated too
+            if(*current && father->x86_addr>=(*current)->x86_addr && (father->x86_addr+father->x86_size)<(*current)->x86_addr)
+                *current = NULL;
+            // Free father, it's now invalid!
+            FreeDynablock(father);
+            // start again... (will create a new block)
+            db = internalDBGetBlock(emu, addr, addr, create, *current);
+        } else {
+            father->need_test = 0;
+            if(father->nolinker)
+                protectDB((uintptr_t)father->x86_addr, father->x86_size);
+        }
+    } 
+    return db;
+}
+
+dynablock_t* DBAlternateBlock(x86emu_t* emu, uintptr_t addr, uintptr_t filladdr)
+{
+    dynarec_log(LOG_DEBUG, "Creating AlternateBlock at %p for %p\n", (void*)addr, (void*)filladdr);
+    int create = 1;
+    dynablock_t *db = internalDBGetBlock(emu, addr, filladdr, create, NULL);
+    if(db && (db->need_test || (db->father && db->father->need_test))) {
+        dynablock_t *father = db->father?db->father:db;
+        uint32_t hash = father->nolinker?X31_hash_code(father->x86_addr, father->x86_size):0;
+        if(hash!=father->hash) {
+            dynarec_log(LOG_DEBUG, "Invalidating block %p from %p:%p (hash:%X/%X) with %d son(s)\n", father, father->x86_addr, father->x86_addr+father->x86_size, hash, father->hash, father->sons_size);
+            // Free father, it's now invalid!
+            FreeDynablock(father);
+            // start again... (will create a new block)
+            db = internalDBGetBlock(emu, addr, filladdr, create, NULL);
+        } else {
+            father->need_test = 0;
+            if(father->nolinker)
+                protectDB((uintptr_t)father->x86_addr, father->x86_size);
+        }
+    } 
+    return db;
+}
@@ -1,26 +1,39 @@
 #ifndef __DYNABLOCK_PRIVATE_H_
 #define __DYNABLOCK_PRIVATE_H_

-typedef struct dynablocklist_s dynablocklist_t;
+typedef struct dynablocklist_s  dynablocklist_t;
+
+typedef struct instsize_s {
+    unsigned int x86:4;
+    unsigned int nat:4;
+} instsize_t;

 typedef struct dynablock_s {
-    dynablocklist_t *parent;
-    void*       block;
-    int         size;
-    uintptr_t*  table;
-    int         tablesz;
-    int         done;
+    dynablocklist_t* parent;
+    void*           block;
+    int             size;
+    void*           x86_addr;
+    uintptr_t       x86_size;
+    uint32_t        hash;
+    uintptr_t*      table;
+    int             tablesz;
+    uint8_t         need_test;
+    uint8_t         done;
+    uint8_t         gone;
+    uint8_t         nolinker;
+    int             isize;
+    dynablock_t**   sons;   // sons (kind-of dummy dynablock...)
+    int             sons_size;
+    dynablock_t*    father; // set only in the case of a son
+    instsize_t*     instsize;
 } dynablock_t;

-typedef struct kh_dynablocks_s kh_dynablocks_t;
-
 typedef struct dynablocklist_s {
-    kh_dynablocks_t     *blocks;
-    pthread_rwlock_t    rwlock_blocks;
-    uintptr_t           base;
    uintptr_t           text;
    int                 textsz;
-    dynablock_t         **direct;    // direct mapping (waste of space, so not always there)
+    int                 maxsz;     // maxblock size (for this block or previous block)
+    int                 nolinker;  // in case this dynablock can be deleted
+    dynablock_t**       direct;    // direct mapping (waste of space, so the array is created at first write)
 } dynablocklist_t;

 #endif //__DYNABLOCK_PRIVATE_H_
@@ -2,6 +2,7 @@
 #include <stdlib.h>
 #include <pthread.h>
 #include <errno.h>
+#include <setjmp.h>

 #include "debug.h"
 #include "box86context.h"
@@ -14,69 +15,117 @@
 #include "callback.h"
 #include "emu/x86run_private.h"
 #include "x86trace.h"
+#include "threads.h"
 #ifdef DYNAREC
 #include "dynablock.h"
 #include "dynablock_private.h"
 #endif

 #ifdef ARM
-void arm_prolog(x86emu_t* emu, void* addr);
-void arm_epilog();
-void arm_linker();
-int arm_tableupdate(void* jump, uintptr_t addr, void** table);
+void arm_prolog(x86emu_t* emu, void* addr) EXPORTDYN;
+void arm_epilog() EXPORTDYN;
+void arm_epilog_fast() EXPORTDYN;
+void arm_linker() EXPORTDYN;
+int arm_tableupdate(void* jump, uintptr_t addr, void** table) EXPORTDYN;
 #endif

+void tableupdate(void* jumpto, uintptr_t ref, void** table)
+{
+    #ifdef ARM
+    if(arm_tableupdate(jumpto, ref, table))
+    #endif
+    {
+        table[0] = jumpto;
+        table[1] = (void*)ref;
+    }
+}
+
+void resettable(void** table)
+{
+    void* p = table[1];
+    #ifdef ARM
+    tableupdate(arm_linker, (uintptr_t)p, table);
+    #endif
+    //table[2] = own_dynablock // unchanged
+    table[3] = NULL;    // removed "linked" information
+}
+
 #ifdef DYNAREC
 void* UpdateLinkTable(x86emu_t* emu, void** table, uintptr_t addr)
 {
-    dynablock_t* block = DBGetBlock(emu, addr, 1, NULL);    // keep a copy of parent block?
-    int r;
-    if(block==0) {
-        // no block, don't try again, ever
-        #ifdef ARM
-        r = arm_tableupdate(arm_epilog, addr, table);
-        if(r) dynarec_log(LOG_DEBUG, "Linker: failed to set table data @%p, for emu=%p\n", table, emu);
-        #else
-        table[0] = arm_epilog;
-        table[1] = addr;
-        #endif
+    dynablock_t* current = (dynablock_t*)table[2];
+    if(current->father)
+        current = current->father;
+    void * jblock;
+    dynablock_t* block = DBGetBlock(emu, addr, 1, &current);
+    if(!current)  {  // current has been invalidated, stop running it...
+        //dynarec_log(LOG_DEBUG, "--- Current invalidated while linking.\n");
+        return arm_epilog_fast;
+    }
+    if(!block) {
+        // no block, let link table as is...
+        //tableupdate(arm_epilog, addr, table);
+        return arm_epilog_fast;
+    }
+    if(!block->done) {
+        // not finished yet... leave linker
+        //tableupdate(arm_linker, addr, table);
+        return arm_epilog_fast;
+    }
+    if(!(jblock=block->block)) {
+        // null block, but done: go to epilog, no linker here
+        tableupdate(arm_epilog, addr, table);
+        return arm_epilog_fast;
+    }
+    //dynablock_t *father = block->father?block->father:block;
+    if(!block->parent->nolinker) {
+        //dynarec_log(LOG_DEBUG, "--- Linking %p/%p to %p (table=%p[%p/%p/%p/%p])\n", block, block->block, current, table, table[0], table[1], table[2], table[3]);
+        // only update block if linker is allowed
+        tableupdate(jblock, addr, table);
+    }
+    return jblock;
+}
+void* LinkNext(x86emu_t* emu, uintptr_t addr)
+{
+    dynablock_t* current = NULL;
+    void * jblock;
+    dynablock_t* block = DBGetBlock(emu, addr, 1, &current);
+    if(!block) {
+        // no block, let link table as is...
+        //tableupdate(arm_epilog, addr, table);
        return arm_epilog;
    }
    if(!block->done) {
        // not finished yet... leave linker
-        #ifdef ARM
-        r = arm_tableupdate(arm_linker, addr, table);
-        if(r) dynarec_log(LOG_DEBUG, "Linker: failed to set table data @%p, for emu=%p\n", table, emu);
-        #else
-        table[0] = arm_linker;
-        table[1] = addr;
-        #endif
+        //tableupdate(arm_linker, addr, table);
        return arm_epilog;
    }
-    if(!block->block) {
-        // null block, but done, go to epilog
-        #ifdef ARM
-        r = arm_tableupdate(arm_epilog, addr, table);
-        if(r) dynarec_log(LOG_DEBUG, "Linker: failed to set table data @%p, for emu=%p\n", table, emu);
-        #else
-        table[0] = arm_epilog;
-        table[1] = addr;
-        #endif
+    if(!(jblock=block->block)) {
+        // null block, but done: go to epilog, no linker here
        return arm_epilog;
    }
-    #ifdef ARM
-    r = arm_tableupdate(block->block, addr, table);
-    if(r) dynarec_log(LOG_DEBUG, "Linker: failed to set table data @%p, for emu=%p\n", table, emu);
-    #else
-    table[0] = block->block;
-    table[1] = addr;
-    #endif
-    return block->block;
+    //dynablock_t *father = block->father?block->father:block;
+    return jblock;
 }
 #endif

 void DynaCall(x86emu_t* emu, uintptr_t addr)
 {
+    // prepare setjump for signal handling
+    emu_jmpbuf_t *ejb = NULL;
+    int jmpbuf_reset = 0;
+    if(emu->type == EMUTYPE_MAIN) {
+        ejb = GetJmpBuf();
+        if(!ejb->jmpbuf_ok) {
+            ejb->emu = emu;
+            ejb->jmpbuf_ok = 1;
+            jmpbuf_reset = 1;
+            if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf)) {
+                printf_log(LOG_DEBUG, "Setjmp DynaCall, fs=0x%x\n", ejb->emu->segs[_FS]);
+                addr = R_EIP;   // not sure if it should still be inside DynaCall!
+            }
+        }
+    }
 #ifdef DYNAREC
    if(!box86_dynarec)
 #endif
@@ -93,15 +142,17 @@ void DynaCall(x86emu_t* emu, uintptr_t addr)
        R_EIP = addr;
        emu->df = d_none;
        dynablock_t* block = NULL;
+        dynablock_t* current = NULL;
        while(!emu->quit) {
-            block = DBGetBlock(emu, R_EIP, 1, block);
+            block = DBGetBlock(emu, R_EIP, 1, &current);
+            current = (block && !block->parent->nolinker)?block:NULL;
            if(!block || !block->block || !block->done) {
                // no block, of block doesn't have DynaRec content (yet, temp is not null)
                // Use interpreter (should use single instruction step...)
-                dynarec_log(LOG_DEBUG, "Calling Interpretor @%p, emu=%p\n", R_EIP, emu);
+                dynarec_log(LOG_DEBUG, "Calling Interpretor @%p, emu=%p\n", (void*)R_EIP, emu);
                Run(emu, 1);
            } else {
-                dynarec_log(LOG_DEBUG, "Calling DynaRec Block @%p (%p) emu=%p\n", R_EIP, block->block, emu);
+                dynarec_log(LOG_DEBUG, "Calling DynaRec Block @%p (%p) of %d x86 instructions (nolinker=%d, father=%p) emu=%p\n", (void*)R_EIP, block->block, block->isize ,block->parent->nolinker, block->father, emu);
                CHECK_FLAGS(emu);
                // block is here, let's run it!
                #ifdef ARM
@@ -113,6 +164,16 @@ void DynaCall(x86emu_t* emu, uintptr_t addr)
                emu->quit = 0;
                emu->fork = 0;
                emu = x86emu_fork(emu, forktype);
+                if(emu->type == EMUTYPE_MAIN) {
+                    ejb = GetJmpBuf();
+                    ejb->emu = emu;
+                    ejb->jmpbuf_ok = 1;
+                    jmpbuf_reset = 1;
+                    if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf)) {
+                        printf_log(LOG_DEBUG, "Setjmp inner DynaCall, fs=0x%x\n", ejb->emu->segs[_FS]);
+                        addr = R_EIP;
+                    }
+                }
            }
        }
        emu->quit = 0;  // reset Quit flags...
@@ -129,10 +190,26 @@ void DynaCall(x86emu_t* emu, uintptr_t addr)
        }
    }
 #endif
+    // clear the setjmp
+    if(ejb && jmpbuf_reset)
+        ejb->jmpbuf_ok = 0;
 }

 int DynaRun(x86emu_t* emu)
 {
+    // prepare setjump for signal handling
+    emu_jmpbuf_t *ejb = NULL;
+    int jmpbuf_reset = 1;
+    if(emu->type == EMUTYPE_MAIN) {
+        ejb = GetJmpBuf();
+        if(!ejb->jmpbuf_ok) {
+            ejb->emu = emu;
+            ejb->jmpbuf_ok = 1;
+            jmpbuf_reset = 1;
+            if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf))
+                printf_log(LOG_DEBUG, "Setjmp DynaRun, fs=0x%x\n", ejb->emu->segs[_FS]);
+        }
+    }
 #ifdef DYNAREC
    if(!box86_dynarec)
 #endif
@@ -140,15 +217,17 @@ int DynaRun(x86emu_t* emu)
 #ifdef DYNAREC
    else {
        dynablock_t* block = NULL;
+        dynablock_t* current = NULL;
        while(!emu->quit) {
-            block = DBGetBlock(emu, R_EIP, 1, block);
+            block = DBGetBlock(emu, R_EIP, 1, &current);
+            current = (block && !block->parent->nolinker)?block:NULL;
            if(!block || !block->block || !block->done) {
                // no block, of block doesn't have DynaRec content (yet, temp is not null)
                // Use interpreter (should use single instruction step...)
-                dynarec_log(LOG_DEBUG, "Running Interpretor @%p, emu=%p\n", R_EIP, emu);
+                dynarec_log(LOG_DEBUG, "Running Interpretor @%p, emu=%p\n", (void*)R_EIP, emu);
                Run(emu, 1);
            } else {
-                dynarec_log(LOG_DEBUG, "Running DynaRec Block @%p (%p) emu=%p\n", R_EIP, block->block, emu);
+                dynarec_log(LOG_DEBUG, "Running DynaRec Block @%p (%p) of %d x86 insts (nolinker=%d, father=%p) emu=%p\n", (void*)R_EIP, block->block, block->isize, block->parent->nolinker, block->father, emu);
                // block is here, let's run it!
                #ifdef ARM
                arm_prolog(emu, block->block);
@@ -159,9 +238,20 @@ int DynaRun(x86emu_t* emu)
                emu->quit = 0;
                emu->fork = 0;
                emu = x86emu_fork(emu, forktype);
+                if(emu->type == EMUTYPE_MAIN) {
+                    ejb = GetJmpBuf();
+                    ejb->emu = emu;
+                    ejb->jmpbuf_ok = 1;
+                    jmpbuf_reset = 1;
+                    if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf))
+                        printf_log(LOG_DEBUG, "Setjmp inner DynaRun, fs=0x%x\n", ejb->emu->segs[_FS]);
+                }
            }
        }
    }
+    // clear the setjmp
+    if(ejb && jmpbuf_reset)
+        ejb->jmpbuf_ok = 0;
    return 0;
 #endif
 }
@@ -2,9 +2,11 @@
 #include <stdlib.h>
 #include <pthread.h>
 #include <errno.h>
+#include <string.h>

 #include "debug.h"
 #include "box86context.h"
+#include "custommem.h"
 #include "dynarec.h"
 #include "emu/x86emu_private.h"
 #include "tools/bridge_private.h"
@@ -18,27 +20,289 @@
 #include "dynablock_private.h"
 #include "dynarec_arm.h"
 #include "dynarec_arm_private.h"
+#include "dynarec_arm_functions.h"
+#include "elfloader.h"

 void printf_x86_instruction(zydis_dec_t* dec, instruction_x86_t* inst, const char* name) {
    uint8_t *ip = (uint8_t*)inst->addr;
    if(ip[0]==0xcc && ip[1]=='S' && ip[2]=='C') {
        uint32_t a = *(uint32_t*)(ip+3);
        if(a==0) {
-            dynarec_log(LOG_NONE, "%p: Exit x86emu\n", (void*)ip);
+            dynarec_log(LOG_NONE, "%s%p: Exit x86emu%s\n", (box86_dynarec_dump>1)?"\e[1m":"", (void*)ip, (box86_dynarec_dump>1)?"\e[m":"");
        } else {
-            dynarec_log(LOG_NONE, "%p: Native call to %p\n", (void*)ip, (void*)a);
+            dynarec_log(LOG_NONE, "%s%p: Native call to %p%s\n", (box86_dynarec_dump>1)?"\e[1m":"", (void*)ip, (void*)a, (box86_dynarec_dump>1)?"\e[m":"");
        }
    } else {
        if(dec) {
-            dynarec_log(LOG_NONE, "%p: %s\n", inst->addr, DecodeX86Trace(dec, inst->addr));
+            dynarec_log(LOG_NONE, "%s%p: %s", (box86_dynarec_dump>1)?"\e[1m":"", ip, DecodeX86Trace(dec, inst->addr));
        } else {
-            dynarec_log(LOG_NONE, "%p: ", inst->addr);
+            dynarec_log(LOG_NONE, "%s%p: ", (box86_dynarec_dump>1)?"\e[1m":"", ip);
            for(int i=0; i<inst->size; ++i) {
                dynarec_log(LOG_NONE, "%02X ", ip[i]);
            }
-            dynarec_log(LOG_NONE, " %s\n", name);
+            dynarec_log(LOG_NONE, " %s", name);
+        }
+        // print Call function name if possible
+        if(ip[0]==0xE8 || ip[0]==0xE9) { // Call / Jmp
+            uintptr_t nextaddr = (uintptr_t)ip + 5 + *((int32_t*)(ip+1));
+            printFunctionAddr(nextaddr, "=> ");
+        } else if(ip[0]==0xFF) {
+            if(ip[1]==0x25) {
+                uintptr_t nextaddr = (uintptr_t)ip + 6 + *((int32_t*)(ip+2));
+                printFunctionAddr(nextaddr, "=> ");
+            }
+        }
+        // end of line and colors
+        dynarec_log(LOG_NONE, "%s\n", (box86_dynarec_dump>1)?"\e[m":"");
+    }
+}
+
+void add_next(dynarec_arm_t *dyn, uintptr_t addr) {
+    if(dyn->next_sz == dyn->next_cap) {
+        dyn->next_cap += 16;
+        dyn->next = (uintptr_t*)realloc(dyn->next, dyn->next_cap*sizeof(uintptr_t));
+    }
+    for(int i=0; i<dyn->next_sz; ++i)
+        if(dyn->next[i]==addr)
+            return;
+    dyn->next[dyn->next_sz++] = addr;
+}
+uintptr_t get_closest_next(dynarec_arm_t *dyn, uintptr_t addr) {
+    // get closest, but no addresses befores
+    uintptr_t best = 0;
+    int i = 0;
+    while((i<dyn->next_sz) && (best!=addr)) {
+        if(dyn->next[i]<addr) { // remove the address, it's before current address
+            memmove(dyn->next+i, dyn->next+i+1, (dyn->next_sz-i-1)*sizeof(uintptr_t));
+            --dyn->next_sz;
+        } else {
+            if((dyn->next[i]<best) || !best)
+                best = dyn->next[i];
+            ++i;
        }
    }
+    return best;
+}
+#define PK(A) (*((uint8_t*)(addr+(A))))
+int is_nops(dynarec_arm_t *dyn, uintptr_t addr, int n)
+{
+    if(!n)
+        return 1;
+    if(PK(0)==0x90)
+        return is_nops(dyn, addr+1, n-1);
+    if(n>1 && PK(0)==0x66)  // if opcode start with 0x66, and there is more after, than is *can* be a NOP
+        return is_nops(dyn, addr+1, n-1);
+    if(n>2 && PK(0)==0x0f && PK(1)==0x1f && PK(2)==0x00)
+        return is_nops(dyn, addr+3, n-3);
+    if(n>2 && PK(0)==0x8d && PK(1)==0x76 && PK(2)==0x00)    // lea esi, [esi]
+        return is_nops(dyn, addr+3, n-3);
+    if(n>3 && PK(0)==0x0f && PK(1)==0x1f && PK(2)==0x40 && PK(3)==0x00)
+        return is_nops(dyn, addr+4, n-4);
+    if(n>3 && PK(0)==0x8d && PK(1)==0x74 && PK(2)==0x26 && PK(3)==0x00)
+        return is_nops(dyn, addr+4, n-4);
+    if(n>4 && PK(0)==0x0f && PK(1)==0x1f && PK(2)==0x44 && PK(3)==0x00 && PK(4)==0x00)
+        return is_nops(dyn, addr+5, n-5);
+    if(n>5 && PK(0)==0x8d && PK(1)==0xb6 && PK(2)==0x00 && PK(3)==0x00 && PK(4)==0x00 && PK(5)==0x00)
+        return is_nops(dyn, addr+6, n-6);
+    if(n>6 && PK(0)==0x0f && PK(1)==0x1f && PK(2)==0x80 && PK(3)==0x00 && PK(4)==0x00 && PK(5)==0x00 && PK(6)==0x00)
+        return is_nops(dyn, addr+7, n-7);
+    if(n>6 && PK(0)==0x8d && PK(1)==0xb4 && PK(2)==0x26 && PK(3)==0x00 && PK(4)==0x00 && PK(5)==0x00 && PK(6)==0x00) // lea esi, [esi+0]
+        return is_nops(dyn, addr+7, n-7);
+    if(n>7 && PK(0)==0x0f && PK(1)==0x1f && PK(2)==0x84 && PK(3)==0x00 && PK(4)==0x00 && PK(5)==0x00 && PK(6)==0x00 && PK(7)==0x00)
+        return is_nops(dyn, addr+8, n-8);
+    return 0;
+}
+
+// return size of next instuciton, -1 is unknown
+// not all instrction are setup
+int next_instruction(dynarec_arm_t *dyn, uintptr_t addr)
+{
+    uint8_t opcode = PK(0);
+    uint8_t nextop;
+    switch (opcode) {
+        case 0x66:
+            opcode = PK(1);
+            switch(opcode) {
+                case 0x90:
+                    return 2;
+            }
+            break;
+        case 0x81:
+            nextop = PK(1);
+            return fakeed(dyn, addr+2, 0, nextop)-addr + 4;
+        case 0x83:
+            nextop = PK(1);
+            return fakeed(dyn, addr+2, 0, nextop)-addr + 1;
+        case 0x84:
+        case 0x85:
+        case 0x88:
+        case 0x89:
+        case 0x8A:
+        case 0x8B:
+        case 0x8C:
+        case 0x8D:
+        case 0x8E:
+        case 0x8F:
+            nextop = PK(1);
+            return fakeed(dyn, addr+2, 0, nextop)-addr;
+        case 0x50:
+        case 0x51:
+        case 0x52:
+        case 0x53:
+        case 0x54:
+        case 0x55:
+        case 0x56:
+        case 0x57:
+        case 0x58:
+        case 0x59:
+        case 0x5A:
+        case 0x5B:
+        case 0x5C:
+        case 0x5D:
+        case 0x5E:
+        case 0x5F:
+        case 0x90:
+        case 0x91:
+        case 0x92:
+        case 0x93:
+        case 0x94:
+        case 0x95:
+        case 0x96:
+        case 0x97:
+        case 0x98:
+        case 0x99:
+        case 0x9B:
+        case 0x9C:
+        case 0x9D:
+        case 0x9E:
+        case 0x9F:
+            return 1;
+        case 0xA0:
+        case 0xA1:
+        case 0xA2:
+        case 0xA3:
+            return 5;
+        case 0xB0:
+        case 0xB1:
+        case 0xB2:
+        case 0xB3:
+        case 0xB4:
+        case 0xB5:
+        case 0xB6:
+        case 0xB7:
+            return 2;
+        case 0xB8:
+        case 0xB9:
+        case 0xBA:
+        case 0xBB:
+        case 0xBC:
+        case 0xBD:
+        case 0xBE:
+        case 0xBF:
+            return 5;
+        case 0xFF:
+            nextop = PK(1);
+            switch((nextop>>3)&7) {
+                case 0: // INC Ed
+                case 1: //DEC Ed
+                case 2: // CALL Ed
+                case 4: // JMP Ed
+                case 6: // Push Ed
+                    return fakeed(dyn, addr+2, 0, nextop)-addr;
+            }
+            break;
+        default:
+            break;
+    }
+    return -1;
+}
+#undef PK
+
+int is_instructions(dynarec_arm_t *dyn, uintptr_t addr, int n)
+{
+    int i = 0;
+    while(i<n) {
+        int j=next_instruction(dyn, addr+i);
+        if(j<=0) return 0;
+        i+=j;
+    }
+    return (i==n)?1:0;
+}
+
+uint32_t needed_flags(dynarec_arm_t *dyn, int ninst, uint32_t setf, int recurse)
+{
+    if(recurse == 10)
+        return X_PEND;
+    if(ninst == dyn->size)
+        return X_PEND; // no more instructions, or too many jmp loop, stop
+    
+    uint32_t needed = dyn->insts[ninst].x86.use_flags;
+    if(needed) {
+        setf &= ~needed;
+        if(!setf)   // all flags already used, no need to continue
+            return needed;
+    }
+
+    if(!needed && !dyn->insts[ninst].x86.set_flags && !dyn->insts[ninst].x86.jmp_insts) {
+        int start = ninst;
+        int end = ninst;
+        while(end<dyn->size && !dyn->insts[end].x86.use_flags && !dyn->insts[end].x86.set_flags && !dyn->insts[end].x86.jmp_insts)
+            ++end;
+        needed = needed_flags(dyn, end, setf, recurse);
+        for(int i=start; i<end; ++i)
+            dyn->insts[i].x86.need_flags = needed;
+        return needed;
+    }
+
+    if(dyn->insts[ninst].x86.set_flags && (dyn->insts[ninst].x86.state_flags!=SF_MAYSET)) {
+        if((setf & ~dyn->insts[ninst].x86.set_flags) == 0)
+            return needed;    // all done, gives all the flags needed
+        setf |= dyn->insts[ninst].x86.set_flags;    // add new flags to continue
+    }
+
+    int jinst = dyn->insts[ninst].x86.jmp_insts;
+    if(dyn->insts[ninst].x86.jmp) {
+        dyn->insts[ninst].x86.need_flags = (jinst==-1)?X_PEND:needed_flags(dyn, jinst, setf, recurse+1);
+        if(dyn->insts[ninst].x86.use_flags)  // conditionnal jump
+             dyn->insts[ninst].x86.need_flags |= needed_flags(dyn, ninst+1, setf, recurse);
+    } else
+        dyn->insts[ninst].x86.need_flags = needed_flags(dyn, ninst+1, setf, recurse);
+    if(dyn->insts[ninst].x86.state_flags==SF_MAYSET)
+        needed |= dyn->insts[ninst].x86.need_flags;
+    else
+        needed |= (dyn->insts[ninst].x86.need_flags & ~dyn->insts[ninst].x86.set_flags);
+    if(needed == (X_PEND|X_ALL))
+        needed = X_ALL;
+    return needed;
+}
+
+instsize_t* addInst(instsize_t* insts, size_t* size, size_t* cap, int x86_size, int arm_size)
+{
+    // x86 instruction is <16 bytes
+    int toadd;
+    if(x86_size>arm_size)
+        toadd = 1 + x86_size/15;
+    else
+        toadd = 1 + arm_size/15;
+    if((*size)+toadd>(*cap)) {
+        *cap = (*size)+toadd;
+        insts = (instsize_t*)realloc(insts, (*cap)*sizeof(instsize_t));
+    }
+    while(toadd) {
+        if(x86_size>15)
+            insts[*size].x86 = 15;    
+        else
+            insts[*size].x86 = x86_size;
+        x86_size -= insts[*size].x86;
+        if(arm_size>15)
+            insts[*size].nat = 15;
+        else
+            insts[*size].nat = arm_size;
+        arm_size -= insts[*size].nat;
+        ++(*size);
+        --toadd;
+    }
+    return insts;
 }

 void arm_pass0(dynarec_arm_t* dyn, uintptr_t addr);
@@ -46,15 +310,17 @@ void arm_pass1(dynarec_arm_t* dyn, uintptr_t addr);
 void arm_pass2(dynarec_arm_t* dyn, uintptr_t addr);
 void arm_pass3(dynarec_arm_t* dyn, uintptr_t addr);

-void FillBlock(x86emu_t* emu, dynablock_t* block, uintptr_t addr) {
+void* FillBlock(dynablock_t* block, uintptr_t addr) {
    // init the helper
    dynarec_arm_t helper = {0};
-    helper.emu = emu;
+    helper.nolinker = box86_dynarec_linker?(block->parent->nolinker):1;
+    helper.start = addr;
    arm_pass0(&helper, addr);
    if(!helper.size) {
        dynarec_log(LOG_DEBUG, "Warning, null-sized dynarec block (%p)\n", (void*)addr);
        block->done = 1;
-        return;
+        free(helper.next);
+        return (void*)block;
    }
    helper.cap = helper.size+3; // needs epilog handling
    helper.insts = (instruction_arm_t*)calloc(helper.cap, sizeof(instruction_arm_t));
@@ -80,44 +346,111 @@ void FillBlock(x86emu_t* emu, dynablock_t* block, uintptr_t addr) {
                helper.insts[i].x86.jmp_insts = k;
            }
        }
-    // remove useless flags calulation
    for(int i=0; i<helper.size; ++i)
-        if(helper.insts[i].x86.flags==X86_FLAGS_CHANGE) {
-            int done = 0;
-            for(int i2=i+1; i2<helper.size+1 && done==0; ++i2) {
-                if(helper.insts[i2].x86.barrier || helper.insts[i2].x86.jmp)
-                    done = 1;
-                else if(helper.insts[i2].x86.flags==X86_FLAGS_USE)
-                    done = 1;
-                else if(helper.insts[i2].x86.flags==X86_FLAGS_CHANGE) {
-                    done = 1;
-                    helper.insts[i].x86.flags=X86_FLAGS_NONE;
-                }
-            }
+        if(helper.insts[i].x86.set_flags && !helper.insts[i].x86.need_flags) {
+            helper.insts[i].x86.need_flags = needed_flags(&helper, i+1, helper.insts[i].x86.set_flags, 0);
+            if((helper.insts[i].x86.need_flags&X_PEND) && (helper.insts[i].x86.state_flags==SF_MAYSET))
+                helper.insts[i].x86.need_flags = X_ALL;
        }
+    
    // pass 2, instruction size
    arm_pass2(&helper, addr);
    // ok, now allocate mapped memory, with executable flag on
    int sz = helper.arm_size;
-    void* p = (void*)AllocDynarecMap(emu->context, sz);
+    void* p = (void*)AllocDynarecMap(block, sz);
    if(p==NULL) {
+        dynarec_log(LOG_DEBUG, "AllocDynarecMap(%p, %d) failed, cancelling block\n", block, sz);
        free(helper.insts);
-        return;
+        free(helper.next);
+        return NULL;
    }
    helper.block = p;
+    helper.arm_start = (uintptr_t)p;
    helper.tablesz = helper.tablei;
    if(helper.tablesz)
        helper.table = (uintptr_t*)calloc(helper.tablesz, sizeof(uintptr_t));
+    if(helper.sons_size) {
+        helper.sons_x86 = (uintptr_t*)calloc(helper.sons_size, sizeof(uintptr_t));
+        helper.sons_arm = (void**)calloc(helper.sons_size, sizeof(void*));
+    }
    // pass 3, emit (log emit arm opcode)
-    dynarec_log(LOG_DEBUG, "Emitting %d bytes for %d x86 bytes\n", helper.arm_size, helper.isize);
+    if(box86_dynarec_dump) {
+        dynarec_log(LOG_NONE, "%sEmitting %d bytes for %d x86 bytes", (box86_dynarec_dump>1)?"\e[01;36m":"", helper.arm_size, helper.isize); 
+        printFunctionAddr(helper.start, " => ");
+        dynarec_log(LOG_NONE, "%s\n", (box86_dynarec_dump>1)?"\e[m":"");
+    }
    helper.arm_size = 0;
    arm_pass3(&helper, addr);
+    if(sz!=helper.arm_size) {
+        printf_log(LOG_NONE, "BOX86: Warning, size difference in block between pass2 (%d) & pass3 (%d)!\n", sz, helper.arm_size);
+        uint8_t *dump = (uint8_t*)helper.start;
+        printf_log(LOG_NONE, "Dump of %d x86 opcodes:\n", helper.size);
+        for(int i=0; i<helper.size; ++i) {
+            printf_log(LOG_NONE, "%p:", dump);
+            for(; dump<(uint8_t*)helper.insts[i+1].x86.addr; ++dump)
+                printf_log(LOG_NONE, " %02X", *dump);
+            printf_log(LOG_NONE, "\t%d -> %d\n", helper.insts[i].size2, helper.insts[i].size);
+        }
+        printf_log(LOG_NONE, " ------------\n");
+    }
    // all done...
-    __builtin___clear_cache(p, p+helper.arm_size);   // need to clear the cache before execution...
+    __clear_cache(p, p+sz);   // need to clear the cache before execution...
+    // keep size of instructions for signal handling
+    {
+        size_t cap = 1;
+        for(int i=0; i<helper.size; ++i)
+            cap += 1 + ((helper.insts[i].x86.size>helper.insts[i].size)?helper.insts[i].x86.size:helper.insts[i].size)/15;
+        size_t size = 0;
+        block->instsize = (instsize_t*)calloc(cap, sizeof(instsize_t));
+        for(int i=0; i<helper.size; ++i)
+            block->instsize = addInst(block->instsize, &size, &cap, helper.insts[i].x86.size, helper.insts[i].size/4);
+        block->instsize = addInst(block->instsize, &size, &cap, 0, 0);    // add a "end of block" mark, just in case
+    }
+    // ok, free the helper now
    free(helper.insts);
+    free(helper.next);
    block->table = helper.table;
    block->tablesz = helper.tablesz;
+    for (int i=0; i<helper.tablesz/4; ++i)
+        block->table[i*4+2] = (uintptr_t)block;
    block->size = sz;
+    block->isize = helper.size;
    block->block = p;
+    block->nolinker = helper.nolinker;
+    block->need_test = 0;
+    //block->x86_addr = (void*)start;
+    block->x86_size = end-start;
+    if(box86_dynarec_largest<block->x86_size)
+        box86_dynarec_largest = block->x86_size;
+    block->hash = (helper.nolinker)?X31_hash_code(block->x86_addr, block->x86_size):0;
+    // fill sons if any
+    dynablock_t** sons = NULL;
+    int sons_size = 0;
+    if(helper.sons_size) {
+        sons = (dynablock_t**)calloc(helper.sons_size, sizeof(dynablock_t*));
+        for (int i=0; i<helper.sons_size; ++i) {
+            int created = 1;
+            dynablock_t *son = AddNewDynablock(block->parent, helper.sons_x86[i], &created);
+            if(created || !son->parent) {    // avoid breaking a working block! also, block could be outside this parent...
+                son->block = helper.sons_arm[i];
+                son->x86_addr = (void*)helper.sons_x86[i];
+                son->x86_size = end-helper.sons_x86[i];
+                if(!son->x86_size) {printf_log(LOG_NONE, "Warning, son with null x86 size! (@%p / ARM=%p)", son->x86_addr, son->block);}
+                son->father = block;
+                son->done = 1;
+                sons[sons_size++] = son;
+                if(!son->parent)
+                    son->parent = block->parent;
+            }
+        }
+        if(sons_size) {
+            block->sons = sons;
+            block->sons_size = sons_size;
+        } else
+            free(sons);
+    }
+    free(helper.sons_x86);
+    free(helper.sons_arm);
    block->done = 1;
+    return (void*)block;
 }
@@ -0,0 +1,325 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <pthread.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box86context.h"
+#include "dynarec.h"
+#include "emu/x86emu_private.h"
+#include "emu/x86run_private.h"
+#include "x86run.h"
+#include "x86emu.h"
+#include "box86stack.h"
+#include "callback.h"
+#include "emu/x86run_private.h"
+#include "x86trace.h"
+#include "dynarec_arm.h"
+#include "dynarec_arm_private.h"
+#include "arm_printer.h"
+
+#include "dynarec_arm_helper.h"
+
+uintptr_t dynarecFS(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
+{
+    uint8_t opcode = F8;
+    uint8_t nextop;
+    int32_t i32, j32;
+    uint32_t u32;
+    uint8_t gd, ed;
+    uint8_t wback;
+    int fixedaddress;
+
+    MAYUSE(j32);
+
+    switch(opcode) {
+
+        case 0x03:
+            INST_NAME("ADD Gd, FS:Ed");
+            SETFLAGS(X_ALL, SF_SET);
+            grab_fsdata(dyn, addr, ninst, x14);
+            nextop = F8;
+            GETGD;
+            GETEDO(x14);
+            emit_add32(dyn, ninst, gd, ed, x3, x14);
+            break;
+
+        case 0x2B:
+            INST_NAME("SUB Gd, FS:Ed");
+            SETFLAGS(X_ALL, SF_SET);
+            grab_fsdata(dyn, addr, ninst, x14);
+            nextop = F8;
+            GETGD;
+            GETEDO(x14);
+            emit_sub32(dyn, ninst, gd, ed, x3, x14);
+            break;
+
+        case 0x33:
+            INST_NAME("XOR Gd, FS:Ed");
+            SETFLAGS(X_ALL, SF_SET);
+            grab_fsdata(dyn, addr, ninst, x14);
+            nextop = F8;
+            GETGD;
+            GETEDO(x14);
+            emit_xor32(dyn, ninst, gd, ed, x3, x14);
+            break;
+
+        case 0x3B:
+            INST_NAME("CMP Gd, FS:Ed");
+            SETFLAGS(X_ALL, SF_SET);
+            grab_fsdata(dyn, addr, ninst, x14);
+            nextop = F8;
+            GETGD;
+            GETEDO(x14);
+            emit_cmp32(dyn, ninst, gd, ed, x3, x14);
+            break;
+
+        case 0x67:
+            // reduced EA size...
+            opcode = F8;
+            switch(opcode) {
+                case 0x89:
+                    INST_NAME("MOV FS:Ew16, Gw");
+                    nextop = F8;
+                    grab_fsdata(dyn, addr, ninst, x14);
+                    GETGD;  // don't need GETGW here
+                    if((nextop&0xC0)==0xC0) {
+                        ed = xEAX+(nextop&7);
+                        if(ed!=gd) {
+                            BFI(ed, gd, 0, 16);
+                        }
+                    } else {
+                        addr = geted16(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                        STRH_REG(gd, x14, ed);
+                    }
+                    break;
+
+                case 0x8B:
+                    INST_NAME("MOV Gd, FS:Ew16");
+                    nextop=F8;
+                    grab_fsdata(dyn, addr, ninst, x14);
+                    GETGD;
+                    if((nextop&0xC0)==0xC0) {   // reg <= reg
+                        MOV_REG(gd, xEAX+(nextop&7));
+                    } else {                    // mem <= reg
+                        addr = geted16(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                        LDR_REG_LSL_IMM5(gd, ed, x14, 0);
+                    }
+                    break;
+
+                case 0x8F:
+                    INST_NAME("POP FS:Ew16");
+                    nextop=F8;
+                    grab_fsdata(dyn, addr, ninst, x14);
+                    if((nextop&0xC0)==0xC0) {
+                        POP1(xEAX+(nextop&7));  // 67 ignored
+                    } else {
+                        addr = geted16(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0);
+                        POP1(x2);
+                        STR_REG_LSL_IMM5(x2, x1, x14, 0);
+                    }
+                    break;
+
+                case 0xA1:
+                    INST_NAME("MOV EAX, FS:Ow");
+                    grab_fsdata(dyn, addr, ninst, x1);
+                    u32 = F16;
+                    if(u32) {
+                        MOV32(x2, u32);
+                        ADD_REG_LSL_IMM5(x1, x1, x2, 0);
+                    }
+                    LDR_IMM9(xEAX, x1, 0);
+                    break;
+
+                case 0xA3:
+                    INST_NAME("MOV FS:Ow, EAX");
+                    grab_fsdata(dyn, addr, ninst, x1);
+                    u32 = F16;
+                    if(u32) {
+                        MOV32(x2, u32);
+                        ADD_REG_LSL_IMM5(x1, x1, x2, 0);
+                    }
+                    STR_IMM9(xEAX, x1, 0);
+                    break;
+
+                case 0xFF:
+                    nextop = F8;
+                    grab_fsdata(dyn, addr, ninst, x14);
+                    switch((nextop>>3)&7) {
+                        case 6: // Push Ed
+                            INST_NAME("PUSH FS:Ew");
+                            if((nextop&0xC0)==0xC0) {   // reg
+                                DEFAULT;
+                            } else {                    // mem <= i32
+                                addr = geted16(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                                LDR_REG_LSL_IMM5(x3, ed, x14, 0);
+                                PUSH1(x3);
+                            }
+                            break;
+                        default:
+                            DEFAULT;
+                    }
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+
+        case 0x89:
+            INST_NAME("MOV FS:Ed, Gd");
+            grab_fsdata(dyn, addr, ninst, x14);
+            nextop=F8;
+            GETGD;
+            if((nextop&0xC0)==0xC0) {   // reg <= reg
+                MOV_REG(xEAX+(nextop&7), gd);
+            } else {                    // mem <= reg
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                STR_REG_LSL_IMM5(gd, ed, x14, 0);
+            }
+            break;
+
+        case 0x8B:
+            INST_NAME("MOV Gd, FS:Ed");
+            grab_fsdata(dyn, addr, ninst, x14);
+            nextop=F8;
+            GETGD;
+            if((nextop&0xC0)==0xC0) {   // reg <= reg
+                MOV_REG(gd, xEAX+(nextop&7));
+            } else {                    // mem <= reg
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                LDR_REG_LSL_IMM5(gd, ed, x14, 0);
+            }
+            break;
+
+        case 0x8F:
+            INST_NAME("POP FS:Ed");
+            grab_fsdata(dyn, addr, ninst, x14);
+            nextop = F8;
+            if((nextop&0xC0)==0xC0) {
+                POP1(xEAX+(nextop&7));
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0);
+                POP1(x2);
+                STR_REG_LSL_IMM5(x2, ed, x14, 0);
+            }
+            break;
+
+        case 0xA0:
+            INST_NAME("MOV AL, FS:Id");
+            grab_fsdata(dyn, addr, ninst, x1);
+            i32 = F32S;
+            if(i32>-4096 && i32<4096) {
+                LDRB_IMM9(xEAX, x1, i32);
+            } else {
+                MOV32(x2, i32);
+                LDRB_REG_LSL_IMM5(xEAX, x1, x2, 0);
+            }
+            break;
+        case 0xA1:
+            INST_NAME("MOV EAX, FS:Id");
+            grab_fsdata(dyn, addr, ninst, x1);
+            i32 = F32S;
+            if(i32>-4096 && i32<4096) {
+                LDR_IMM9(xEAX, x1, i32);
+            } else {
+                MOV32(x2, i32);
+                LDR_REG_LSL_IMM5(xEAX, x1, x2, 0);
+            }
+            break;
+        case 0xA2:
+            INST_NAME("MOV FS:Od, AL");
+            grab_fsdata(dyn, addr, ninst, x1);
+            i32 = F32S;
+            if(i32>-4096 && i32<4096) {
+                STRB_IMM9(xEAX, x1, i32);
+            } else {
+                MOV32(x2, i32);
+                STRB_REG_LSL_IMM5(xEAX, x1, x2, 0);
+            }
+            break;
+        case 0xA3:
+            INST_NAME("MOV FS:Od, EAX");
+            grab_fsdata(dyn, addr, ninst, x1);
+            i32 = F32S;
+            if(i32>-4096 && i32<4096) {
+                STR_IMM9(xEAX, x1, i32);
+            } else {
+                MOV32(x2, i32);
+                STR_REG_LSL_IMM5(xEAX, x2, x1, 0);
+            }
+            break;
+
+        case 0xC7:
+            INST_NAME("MOV FS:Ed, Id");
+            grab_fsdata(dyn, addr, ninst, x14);
+            nextop=F8;
+            if((nextop&0xC0)==0xC0) {   // reg <= i32
+                i32 = F32S;
+                ed = xEAX+(nextop&7);
+                MOV32(ed, i32);
+            } else {                    // mem <= i32
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                i32 = F32S;
+                MOV32(x3, i32);
+                STR_REG_LSL_IMM5(x3, ed, x14, 0);
+            }
+            break;
+            
+        case 0xE9:
+        case 0xEB:
+            INST_NAME("(ignored) FS:");
+            --addr;
+            break;
+
+        case 0xFF:
+            nextop = F8;
+            grab_fsdata(dyn, addr, ninst, x14);
+            switch((nextop>>3)&7) {
+                case 2: // CALL Ed
+                    INST_NAME("CALL Ed");
+                    PASS2IF(ninst && dyn->insts && dyn->insts[ninst-1].x86.set_flags, 1) {
+                        READFLAGS(X_PEND);          // that's suspicious
+                    } else {
+                        SETFLAGS(X_ALL, SF_SET);    //Hack to put flag in "don't care" state
+                    }
+                    if((nextop&0xC0)==0xC0) {   // reg
+                        MOV_REG(xEIP, xEAX+(nextop&7));
+                    } else {                    // mem
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                        LDR_REG_LSL_IMM5(xEIP, ed, x14, 0);
+                    }
+                    BARRIER(1);
+                    BARRIER_NEXT(1);
+                    if(!dyn->nolinker && (!dyn->insts || ninst!=dyn->size-1)) {
+                        PASS2(cstack_push(dyn, ninst, addr, dyn->insts[ninst+1].address, x1, x2);)
+                    } else {
+                        PASS2(cstack_push(dyn, ninst, 0, 0, x1, x2);)
+                        *need_epilog = 0;
+                        *ok = 0;
+                        MOV32(x2, addr);
+                    }
+                    PUSH1(x2);
+                    jump_to_linker(dyn, 0, xEIP, ninst);  // smart linker
+                    break;
+                case 6: // Push Ed
+                    INST_NAME("PUSH FS:Ed");
+                    if((nextop&0xC0)==0xC0) {   // reg
+                        DEFAULT;
+                    } else {                    // mem <= i32
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                        LDR_REG_LSL_IMM5(x3, ed, x14, 0);
+                        PUSH1(x3);
+                    }
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}
+
@@ -25,53 +25,186 @@ uintptr_t dynarecGS(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
 {
    uint8_t opcode = F8;
    uint8_t nextop;
-    int32_t i32;
+    int32_t i32, j32;
    uint32_t u32;
    uint8_t gd, ed;
    uint8_t wback, wb1, wb2;
+    uint8_t u8;
    int fixedaddress;
+
+    MAYUSE(j32);
+    MAYUSE(wback);
+    MAYUSE(wb2);
+    
    switch(opcode) {
-        case 0x33:
-            grab_tlsdata(dyn, addr, ninst, x12);
-            INST_NAME("GS:XOR Gd, Ed");
+
+        case 0x03:
+            INST_NAME("ADD Gd, GS:Ed");
+            SETFLAGS(X_ALL, SF_SET);
+            grab_tlsdata(dyn, addr, ninst, x14);
            nextop = F8;
            GETGD;
-            GETEDO(x12);
-            XOR_REG_LSL_IMM8(gd, gd, ed, 0);
-            UFLAG_RES(gd);
-            UFLAG_DF(1, d_xor32);
-            UFLAGS(0);
+            GETEDO(x14);
+            emit_add32(dyn, ninst, gd, ed, x3, x14);
            break;

+        case 0x2B:
+            INST_NAME("SUB Gd, GS:Ed");
+            SETFLAGS(X_ALL, SF_SET);
+            grab_tlsdata(dyn, addr, ninst, x14);
+            nextop = F8;
+            GETGD;
+            GETEDO(x14);
+            emit_sub32(dyn, ninst, gd, ed, x3, x14);
+            break;
+
+        case 0x33:
+            INST_NAME("XOR Gd, GS:Ed");
+            SETFLAGS(X_ALL, SF_SET);
+            grab_tlsdata(dyn, addr, ninst, x14);
+            nextop = F8;
+            GETGD;
+            GETEDO(x14);
+            emit_xor32(dyn, ninst, gd, ed, x3, x14);
+            break;
+
+        case 0x3B:
+            INST_NAME("CMP Gd, GS:Ed");
+            SETFLAGS(X_ALL, SF_SET);
+            grab_tlsdata(dyn, addr, ninst, x14);
+            nextop = F8;
+            GETGD;
+            GETEDO(x14);
+            emit_cmp32(dyn, ninst, gd, ed, x3, x14);
+            break;
+
+        case 0x80:
+        case 0x82:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 0: //ADD
+                    INST_NAME("ADD GS:Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET);
+                    grab_tlsdata(dyn, addr, ninst, x1);
+                    GETEBO(x1);
+                    u8 = F8;
+                    emit_add8c(dyn, ninst, x1, u8, x2, x14);
+                    EBBACK;
+                    break;
+                case 1: //OR
+                    INST_NAME("OR GS:Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET);
+                    grab_tlsdata(dyn, addr, ninst, x1);
+                    GETEBO(x1);
+                    u8 = F8;
+                    emit_or8c(dyn, ninst, x1, u8, x2, x14);
+                    EBBACK;
+                    break;
+                case 2: //ADC
+                    INST_NAME("ADC GS:Eb, Ib");
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET);
+                    grab_tlsdata(dyn, addr, ninst, x1);
+                    GETEBO(x1);
+                    u8 = F8;
+                    emit_adc8c(dyn, ninst, x1, u8, x2, x14);
+                    EBBACK;
+                    break;
+                case 3: //SBB
+                    INST_NAME("SBB GS:Eb, Ib");
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET);
+                    grab_tlsdata(dyn, addr, ninst, x1);
+                    GETEBO(x1);
+                    u8 = F8;
+                    emit_sbb8c(dyn, ninst, x1, u8, x2, x14);
+                    EBBACK;
+                    break;
+                case 4: //AND
+                    INST_NAME("AND GS:Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET);
+                    grab_tlsdata(dyn, addr, ninst, x1);
+                    GETEBO(x1);
+                    u8 = F8;
+                    emit_and8c(dyn, ninst, x1, u8, x2, x14);
+                    EBBACK;
+                    break;
+                case 5: //SUB
+                    INST_NAME("SUB GS:Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET);
+                    grab_tlsdata(dyn, addr, ninst, x1);
+                    GETEBO(x1);
+                    u8 = F8;
+                    emit_sub8c(dyn, ninst, x1, u8, x2, x14);
+                    EBBACK;
+                    break;
+                case 6: //XOR
+                    INST_NAME("XOR GS:Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET);
+                    grab_tlsdata(dyn, addr, ninst, x1);
+                    GETEBO(x1);
+                    u8 = F8;
+                    emit_xor8c(dyn, ninst, x1, u8, x2, x14);
+                    EBBACK;
+                    break;
+                case 7: //CMP
+                    INST_NAME("CMP GS:Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET);
+                    grab_tlsdata(dyn, addr, ninst, x1);
+                    GETEBO(x1);
+                    u8 = F8;
+                    if(u8) {
+                        MOVW(x2, u8);
+                        emit_cmp8(dyn, ninst, x1, x2, x3, x14);
+                    } else {
+                        emit_cmp8_0(dyn, ninst, x1, x3, x14);
+                    }
+                    break;
+            }
+            break;
+            
        case 0x89:
-            grab_tlsdata(dyn, addr, ninst, x12);
            INST_NAME("MOV GS:Ed, Gd");
+            grab_tlsdata(dyn, addr, ninst, x14);
            nextop=F8;
            GETGD;
            if((nextop&0xC0)==0xC0) {   // reg <= reg
                MOV_REG(xEAX+(nextop&7), gd);
            } else {                    // mem <= reg
                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
-                STR_REG_LSL_IMM5(gd, ed, x12, 0);
+                STR_REG_LSL_IMM5(gd, ed, x14, 0);
            }
            break;

        case 0x8B:
-            grab_tlsdata(dyn, addr, ninst, x12);
            INST_NAME("MOV Gd, GS:Ed");
+            grab_tlsdata(dyn, addr, ninst, x14);
            nextop=F8;
            GETGD;
            if((nextop&0xC0)==0xC0) {   // reg <= reg
                MOV_REG(gd, xEAX+(nextop&7));
            } else {                    // mem <= reg
                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
-                LDR_REG_LSL_IMM5(gd, ed, x12, 0);
+                LDR_REG_LSL_IMM5(gd, ed, x14, 0);
+            }
+            break;
+
+        case 0x8F:
+            INST_NAME("POP GS:Ed");
+            grab_tlsdata(dyn, addr, ninst, x14);
+            nextop = F8;
+            if((nextop&0xC0)==0xC0) {
+                POP1((xEAX+(nextop&7)));
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0);
+                POP1(x2);
+                STR_REG_LSL_IMM5(x2, ed, x14, 0);
            }
            break;

        case 0xA1:
-            grab_tlsdata(dyn, addr, ninst, x1);
            INST_NAME("MOV EAX, GS:Id");
+            grab_tlsdata(dyn, addr, ninst, x1);
            i32 = F32S;
            if(i32>-4096 && i32<4096) {
                LDR_IMM9(xEAX, x1, i32);
@@ -83,8 +216,8 @@ uintptr_t dynarecGS(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
            break;

        case 0xA3:
-            grab_tlsdata(dyn, addr, ninst, x1);
            INST_NAME("MOV GS:Od, EAX");
+            grab_tlsdata(dyn, addr, ninst, x1);
            u32 = F32;
            MOV32(x2, u32);
            ADD_REG_LSL_IMM5(x2, x1, x2, 0);
@@ -92,8 +225,8 @@ uintptr_t dynarecGS(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
            break;

        case 0xC7:
-            grab_tlsdata(dyn, addr, ninst, x12);
            INST_NAME("MOV GS:Ed, Id");
+            grab_tlsdata(dyn, addr, ninst, x14);
            nextop=F8;
            if((nextop&0xC0)==0xC0) {   // reg <= i32
                i32 = F32S;
@@ -103,12 +236,36 @@ uintptr_t dynarecGS(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
                i32 = F32S;
                MOV32(x3, i32);
-                STR_REG_LSL_IMM5(x3, ed, x12, 0);
+                STR_REG_LSL_IMM5(x3, ed, x14, 0);
+            }
+            break;
+
+        case 0xE9:
+        case 0xEB:
+            INST_NAME("(ignored) GS:");
+            --addr;
+            break;
+
+        case 0xFF:
+            nextop = F8;
+            grab_tlsdata(dyn, addr, ninst, x14);
+            switch((nextop>>3)&7) {
+                case 6: // Push Ed
+                    INST_NAME("PUSH GS:Ed");
+                    if((nextop&0xC0)==0xC0) {   // reg
+                        DEFAULT;
+                    } else {                    // mem <= i32
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                        LDR_REG_LSL_IMM5(x3, ed, x14, 0);
+                        PUSH1(x3);
+                    }
+                    break;
+                default:
+                    DEFAULT;
            }
            break;

        default:
-            *ok = 0;
            DEFAULT;
    }
    return addr;
@@ -21,22 +21,117 @@

 #include "dynarec_arm_helper.h"

-
 uintptr_t dynarec67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
 {
-    uint8_t opcode = F8;
-    uint8_t nextop, u8;
+    uint8_t nextop, opcode;
    int8_t  i8;
+    int32_t i32, j32;
    uint32_t u32;
-    int32_t i32;
-    int16_t i16;
-    uint16_t u16;
    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
    int fixedaddress;
-    switch(opcode) {
+
+    MAYUSE(i32);
+    MAYUSE(j32);
+    
+    nextop = F8;
+
+    switch(nextop) {
       

+        case 0x64:
+            // reduced EA size...
+            opcode = F8;
+            switch(opcode) {
+                case 0x89:
+                    INST_NAME("MOV FS:Ew16, Gw");
+                    nextop = F8;
+                    grab_fsdata(dyn, addr, ninst, x14);
+                    GETGD;  // don't need GETGW here
+                    if((nextop&0xC0)==0xC0) {
+                        ed = xEAX+(nextop&7);
+                        if(ed!=gd) {
+                            BFI(ed, gd, 0, 16);
+                        }
+                    } else {
+                        addr = geted16(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                        STRH_REG(gd, x14, ed);
+                    }
+                    break;
+
+                case 0x8B:
+                    INST_NAME("MOV Gd, FS:Ew16");
+                    nextop=F8;
+                    grab_fsdata(dyn, addr, ninst, x14);
+                    GETGD;
+                    if((nextop&0xC0)==0xC0) {   // reg <= reg
+                        ed = xEAX+(nextop&7);
+                        if(ed!=gd) {
+                            BFI(gd, ed, 0, 16);
+                        }
+                    } else {                    // mem <= reg
+                        addr = geted16(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                        LDR_REG_LSL_IMM5(gd, x14, ed, 0);
+                    }
+                    break;
+
+                case 0x8F:
+                    INST_NAME("POP FS:Ew16");
+                    nextop=F8;
+                    grab_fsdata(dyn, addr, ninst, x14);
+                    if((nextop&0xC0)==0xC0) {
+                        POP1(xEAX+(nextop&7));  // 67 ignored
+                    } else {
+                        addr = geted16(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0);
+                        POP1(x2);
+                        STR_REG_LSL_IMM5(x2, x14, ed, 0);
+                    }
+                    break;
+
+                case 0xA1:
+                    INST_NAME("MOV EAX, FS:Ow");
+                    grab_fsdata(dyn, addr, ninst, x1);
+                    u32 = F16;
+                    if(u32) {
+                        MOV32(x2, u32);
+                        ADD_REG_LSL_IMM5(x1, x1, x2, 0);
+                    }
+                    LDR_IMM9(xEAX, x1, 0);
+                    break;
+
+                case 0xA3:
+                    INST_NAME("MOV FS:Ow, EAX");
+                    grab_fsdata(dyn, addr, ninst, x1);
+                    u32 = F16;
+                    if(u32) {
+                        MOV32(x2, u32);
+                        ADD_REG_LSL_IMM5(x1, x1, x2, 0);
+                    }
+                    STR_IMM9(xEAX, x1, 0);
+                    break;
+
+                case 0xFF:
+                    nextop = F8;
+                    grab_fsdata(dyn, addr, ninst, x14);
+                    switch((nextop>>3)&7) {
+                        case 6: // Push Ed
+                            INST_NAME("PUSH FS:Ew");
+                            if((nextop&0xC0)==0xC0) {   // reg
+                                DEFAULT;
+                            } else {                    // mem <= i32
+                                addr = geted16(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0);
+                                LDR_REG_LSL_IMM5(x3, ed, x14, 0);
+                                PUSH1(x3);
+                            }
+                            break;
+                        default:
+                            DEFAULT;
+                    }
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+            
        #define GO(NO, YES)   \
            BARRIER(2); \
            JUMP(addr+i8);\
@@ -54,31 +149,28 @@ uintptr_t dynarec67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
            }
        case 0xE0:
            INST_NAME("LOOPNZ (16bits)");
-            USEFLAG(1);
+            READFLAGS(X_ZF);
            i8 = F8S;
            UXTH(x1, xECX, 0);
            SUBS_IMM8(x1, x1, 1);
            BFI(xECX, x1, 0, 16);
            B_NEXT(cEQ);    // CX is 0, no LOOP
-            LDR_IMM9(x1, xEmu, offsetof(x86emu_t, flags[F_ZF]));
-            TSTS_REG_LSL_IMM8(x1, x1, 0);
+            TSTS_IMM8(xFlags, 1<<F_ZF);
            GO(cNE, cEQ);
            break;
        case 0xE1:
            INST_NAME("LOOPZ (16bits)");
-            USEFLAG(1);
+            READFLAGS(X_ZF);
            i8 = F8S;
            UXTH(x1, xECX, 0);
            SUBS_IMM8(x1, x1, 1);
            BFI(xECX, x1, 0, 16);
            B_NEXT(cEQ);    // CX is 0, no LOOP
-            LDR_IMM9(x1, xEmu, offsetof(x86emu_t, flags[F_ZF]));
-            TSTS_REG_LSL_IMM8(x1, x1, 0);
+            TSTS_IMM8(xFlags, 1<<F_ZF);
            GO(cEQ, cNE);
            break;
        case 0xE2:
            INST_NAME("LOOP (16bits)");
-            USEFLAG(1);
            i8 = F8S;
            UXTH(x1, xECX, 0);
            SUBS_IMM8(x1, x1, 1);
@@ -87,16 +179,14 @@ uintptr_t dynarec67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
            break;
        case 0xE3:
            INST_NAME("JCXZ");
-            USEFLAG(1);
            i8 = F8S;
            UXTH(x1, xECX, 0);
-            TSTS_REG_LSL_IMM8(x1, x1, 0);
+            TSTS_REG_LSL_IMM5(x1, x1, 0);
            GO(cNE, cEQ);
            break;
        #undef GO

        default:
-            *ok = 0;
            DEFAULT;
    }
    return addr;
@@ -26,17 +26,19 @@
 uintptr_t dynarecD8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
 {
    uint8_t nextop = F8;
-    uint8_t u8;
-    uint32_t u32;
-    int32_t i32;
-    int16_t i16;
-    uint16_t u16;
-    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
-    int v1, v2, v3;
-    int s0, s1, s2;
-    int d0, d1;
+    uint8_t ed;
+    uint8_t wback;
+    int v1, v2;
+    int s0;
+    int d1;
    int fixedaddress;
+    int parity;
+
+    MAYUSE(d1);
+    MAYUSE(s0);
+    MAYUSE(v1);
+    MAYUSE(v2);
+    MAYUSE(ed);

    switch(nextop) {
        case 0xC0:
@@ -152,30 +154,48 @@ uintptr_t dynarecD8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                case 0:
                    INST_NAME("FADD ST0, float[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    GETED;
                    s0 = fpu_get_scratch_single(dyn);
                    d1 = fpu_get_scratch_double(dyn);
-                    VMOVtoV(s0, ed);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VLDR_32(s0, ed, fixedaddress);
+                    } else {
+                        GETED;
+                        VMOVtoV(s0, ed);
+                    }
                    VCVT_F64_F32(d1, s0);
                    VADD_F64(v1, v1, d1);
                    break;
                case 1:
                    INST_NAME("FMUL ST0, float[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    GETED;
                    s0 = fpu_get_scratch_single(dyn);
                    d1 = fpu_get_scratch_double(dyn);
-                    VMOVtoV(s0, ed);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VLDR_32(s0, ed, fixedaddress);
+                    } else {
+                        GETED;
+                        VMOVtoV(s0, ed);
+                    }
                    VCVT_F64_F32(d1, s0);
                    VMUL_F64(v1, v1, d1);
                    break;
                case 2:
                    INST_NAME("FCOM ST0, float[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    GETED;
                    s0 = fpu_get_scratch_single(dyn);
                    d1 = fpu_get_scratch_double(dyn);
-                    VMOVtoV(s0, ed);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VLDR_32(s0, ed, fixedaddress);
+                    } else {
+                        GETED;
+                        VMOVtoV(s0, ed);
+                    }
                    VCVT_F64_F32(d1, s0);
                    VCMP_F64(v1, d1);
                    FCOM(x1, x2);
@@ -183,10 +203,16 @@ uintptr_t dynarecD8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                case 3:
                    INST_NAME("FCOMP ST0, float[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    GETED;
                    s0 = fpu_get_scratch_single(dyn);
                    d1 = fpu_get_scratch_double(dyn);
-                    VMOVtoV(s0, ed);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VLDR_32(s0, ed, fixedaddress);
+                    } else {
+                        GETED;
+                        VMOVtoV(s0, ed);
+                    }
                    VCVT_F64_F32(d1, s0);
                    VCMP_F64(v1, d1);
                    FCOM(x1, x2);
@@ -195,45 +221,68 @@ uintptr_t dynarecD8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                case 4:
                    INST_NAME("FSUB ST0, float[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    GETED;
                    s0 = fpu_get_scratch_single(dyn);
                    d1 = fpu_get_scratch_double(dyn);
-                    VMOVtoV(s0, ed);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VLDR_32(s0, ed, fixedaddress);
+                    } else {
+                        GETED;
+                        VMOVtoV(s0, ed);
+                    }
                    VCVT_F64_F32(d1, s0);
                    VSUB_F64(v1, v1, d1);
                    break;
                case 5:
                    INST_NAME("FSUBR ST0, float[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    GETED;
                    s0 = fpu_get_scratch_single(dyn);
                    d1 = fpu_get_scratch_double(dyn);
-                    VMOVtoV(s0, ed);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VLDR_32(s0, ed, fixedaddress);
+                    } else {
+                        GETED;
+                        VMOVtoV(s0, ed);
+                    }
                    VCVT_F64_F32(d1, s0);
                    VSUB_F64(v1, d1, v1);
                    break;
                case 6:
                    INST_NAME("FDIV ST0, float[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    GETED;
                    s0 = fpu_get_scratch_single(dyn);
                    d1 = fpu_get_scratch_double(dyn);
-                    VMOVtoV(s0, ed);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VLDR_32(s0, ed, fixedaddress);
+                    } else {
+                        GETED;
+                        VMOVtoV(s0, ed);
+                    }
                    VCVT_F64_F32(d1, s0);
                    VDIV_F64(v1, v1, d1);
                    break;
                case 7:
                    INST_NAME("FDIVR ST0, float[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    GETED;
                    s0 = fpu_get_scratch_single(dyn);
                    d1 = fpu_get_scratch_double(dyn);
-                    VMOVtoV(s0, ed);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VLDR_32(s0, ed, fixedaddress);
+                    } else {
+                        GETED;
+                        VMOVtoV(s0, ed);
+                    }
                    VCVT_F64_F32(d1, s0);
                    VDIV_F64(v1, d1, v1);
                    break;
                default:
-                    *ok = 0;
                    DEFAULT;
            }
    }
@@ -23,28 +23,29 @@
 #include "dynarec_arm_functions.h"
 #include "dynarec_arm_helper.h"

-static double d_1   = 1.0;
-static double d_l2t = L2T;
-static double d_l2e = L2E;
-static double d_pi  = PI;
-static double d_lg2 = LG2;
-static double d_ln2 = LN2;
-static double d_0   = 0.0;
+static const double d_1   = 1.0;
+static const double d_l2t = L2T;
+static const double d_l2e = L2E;
+static const double d_pi  = PI;
+static const double d_lg2 = LG2;
+static const double d_ln2 = LN2;
+static const double d_0   = 0.0;

 uintptr_t dynarecD9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
 {
    uint8_t nextop = F8;
-    uint8_t u8;
-    uint32_t u32;
-    int32_t i32;
-    int16_t i16;
-    uint16_t u16;
-    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
+    uint8_t ed;
+    uint8_t wback, wb1;
    int fixedaddress;
-    int v1, v2, v3;
-    int s0, s1, s2;
+    int v1, v2;
+    int s0;
    int i1, i2, i3;
+    int parity;
+
+    MAYUSE(s0);
+    MAYUSE(v2);
+    MAYUSE(v1);
+
    switch(nextop) {

        case 0xC0:
@@ -204,6 +205,28 @@ uintptr_t dynarecD9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
            x87_forget(dyn, ninst, x1, x2, 1);
            CALL(arm_fxtract, -1, 0);
            break;
+        case 0xF5:
+            INST_NAME("FPREM1");
+            x87_forget(dyn, ninst, x1, x2, 0);
+            x87_forget(dyn, ninst, x1, x2, 1);
+            CALL(arm_fprem1, -1, 0);
+            break;
+        case 0xF6:
+            INST_NAME("FDECSTP");
+            fpu_purgecache(dyn, ninst, x1, x2, x3);
+            LDR_IMM9(x2, xEmu, offsetof(x86emu_t, top));
+            SUB_IMM8(x2, x2, 1);
+            AND_IMM8(x2, x2, 7);
+            STR_IMM9(x2, xEmu, offsetof(x86emu_t, top));
+            break;
+        case 0xF7:
+            INST_NAME("FINCSTP");
+            fpu_purgecache(dyn, ninst, x1, x2, x3);
+            LDR_IMM9(x2, xEmu, offsetof(x86emu_t, top));
+            ADD_IMM8(x2, x2, 1);
+            AND_IMM8(x2, x2, 7);
+            STR_IMM9(x2, xEmu, offsetof(x86emu_t, top));
+            break;
        case 0xF8:
            INST_NAME("FPREM");
            x87_forget(dyn, ninst, x1, x2, 0);
@@ -259,10 +282,6 @@ uintptr_t dynarecD9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xE6:
        case 0xE7:
        case 0xEF:
-        case 0xF5:
-        case 0xF6:
-        case 0xF7:
-            *ok = 0;
            DEFAULT;
            break;
             
@@ -271,37 +290,59 @@ uintptr_t dynarecD9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                case 0:
                    INST_NAME("FLD ST0, float[ED]");
                    v1 = x87_do_push(dyn, ninst);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095, 0);
                    s0 = fpu_get_scratch_single(dyn);
-                    // to avoid bus error
-                    //VLDR_32(s0, ed, 0);
-                    LDR_IMM9(x2, ed, fixedaddress);
-                    VMOVtoV(s0, x2);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VLDR_32(s0, ed, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095, 0);
+                        LDR_IMM9(x2, ed, fixedaddress);
+                        VMOVtoV(s0, x2);
+                    }
                    VCVT_F64_F32(v1, s0);
                    break;
                case 2:
                    INST_NAME("FST float[ED], ST0");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095, 0);
                    s0 = fpu_get_scratch_single(dyn);
                    VCVT_F32_F64(s0, v1);
-                    // to avoid bus error...
-                    //VSTR_32(s0, ed, 0);
-                    VMOVfrV(x2, s0);
-                    STR_IMM9(x2, ed, fixedaddress);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VSTR_32(s0, ed, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095, 0);
+                        VMOVfrV(x2, s0);
+                        STR_IMM9(x2, ed, fixedaddress);
+                    }
                    break;
                case 3:
                    INST_NAME("FSTP float[ED], ST0");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095, 0);
                    s0 = fpu_get_scratch_single(dyn);
                    VCVT_F32_F64(s0, v1);
-                    // to avoid bus error...
-                    //VSTR_32(s0, ed, 0);
-                    VMOVfrV(x2, s0);
-                    STR_IMM9(x2, ed, fixedaddress);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VSTR_32(s0, ed, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095, 0);
+                        VMOVfrV(x2, s0);
+                        STR_IMM9(x2, ed, fixedaddress);
+                    }
                    x87_do_pop(dyn, ninst);
                    break;
+                case 4:
+                    INST_NAME("FLDENV Ed");
+                    fpu_purgecache(dyn, ninst, x1, x2, x3); // maybe only x87, not SSE?
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0);
+                    if(ed!=x1) {
+                        MOV_REG(x1, ed);
+                    }
+                    MOVW(x2, 0);
+                    CALL(fpu_loadenv, -1, 0);
+                    break;
                case 5:
                    INST_NAME("FLDCW Ew");
                    GETEW(x1);
@@ -309,6 +350,16 @@ uintptr_t dynarecD9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                    UBFX(x1, x1, 10, 2);    // extract round
                    STR_IMM9(x1, xEmu, offsetof(x86emu_t, round));
                    break;
+                case 6:
+                    INST_NAME("FNSTENV Ed");
+                    fpu_purgecache(dyn, ninst, x1, x2, x3); // maybe only x87, not SSE?
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0);
+                    if(ed!=x1) {
+                        MOV_REG(x1, ed);
+                    }
+                    MOVW(x2, 0);
+                    CALL(fpu_savenv, -1, 0);
+                    break;
                case 7:
                    INST_NAME("FNSTCW Ew");
                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 255, 0);
@@ -318,7 +369,6 @@ uintptr_t dynarecD9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                    EWBACK;
                    break;
                default:
-                    *ok = 0;
                    DEFAULT;
            }
    }
@@ -26,17 +26,21 @@
 uintptr_t dynarecDA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
 {
    uint8_t nextop = F8;
-    uint8_t u8;
-    uint32_t u32;
-    int32_t i32;
-    int16_t i16;
-    uint16_t u16;
-    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
+    int32_t j32;
+    uint8_t ed;
+    uint8_t wback;
    int v1, v2;
    int d0;
    int s0;
    int fixedaddress;
+
+    MAYUSE(s0);
+    MAYUSE(d0);
+    MAYUSE(v2);
+    MAYUSE(v1);
+    MAYUSE(ed);
+    MAYUSE(j32);
+
    switch(nextop) {
        case 0xC0:
        case 0xC1:
@@ -47,11 +51,10 @@ uintptr_t dynarecDA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xC6:
        case 0xC7:
            INST_NAME("FCMOVB ST0, STx");
-            USEFLAG(1);
+            READFLAGS(X_CF);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            LDR_IMM9(x1, xEmu, offsetof(x86emu_t, flags[F_CF]));
-            TSTS_REG_LSL_IMM8(x1, x1, 0);
+            TSTS_IMM8(xFlags, 1<<F_CF);
            VMOVcond_64(cNE, v1, v2);   // F_CF==1
            break;
        case 0xC8:
@@ -63,11 +66,10 @@ uintptr_t dynarecDA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xCE:
        case 0xCF:
            INST_NAME("FCMOVE ST0, STx");
-            USEFLAG(1);
+            READFLAGS(X_ZF);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            LDR_IMM9(x1, xEmu, offsetof(x86emu_t, flags[F_ZF]));
-            TSTS_REG_LSL_IMM8(x1, x1, 0);
+            TSTS_IMM8(xFlags, 1<<F_ZF);
            VMOVcond_64(cNE, v1, v2);   // F_ZF==1
            break;
        case 0xD0:
@@ -79,12 +81,10 @@ uintptr_t dynarecDA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xD6:
        case 0xD7:
            INST_NAME("FCMOVBE ST0, STx");
-            USEFLAG(1);
+            READFLAGS(X_CF|X_ZF);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            LDR_IMM9(x1, xEmu, offsetof(x86emu_t, flags[F_ZF]));
-            LDR_IMM9(x2, xEmu, offsetof(x86emu_t, flags[F_CF]));
-            ORRS_REG_LSL_IMM8(x1, x1, x2, 0);
+            TSTS_IMM8(xFlags, (1<<F_CF)|(1<<F_ZF));
            VMOVcond_64(cNE, v1, v2);   // F_CF==1 | F_ZF==1
            break;
        case 0xD8:
@@ -96,17 +96,16 @@ uintptr_t dynarecDA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xDE:
        case 0xDF:
            INST_NAME("FCMOVU ST0, STx");
-            USEFLAG(1);
+            READFLAGS(X_PF);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            LDR_IMM9(x1, xEmu, offsetof(x86emu_t, flags[F_PF]));
-            TSTS_REG_LSL_IMM8(x1, x1, 0);
+            TSTS_IMM8(xFlags, 1<<F_PF);
            VMOVcond_64(cNE, v1, v2);   // F_PF==1
            break;       
        case 0xE9:
-            INST_NAME("FUCOMPP ST0, STx");
+            INST_NAME("FUCOMPP ST0, ST1");
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
+            v2 = x87_get_st(dyn, ninst, x1, x2, 1);
            VCMP_F64(v1, v2);
            FCOM(x1, x2);
            x87_do_pop(dyn, ninst);
@@ -123,7 +122,6 @@ uintptr_t dynarecDA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xF8:
        case 0xF9:
        case 0xFD:
-            *ok = 0;
            DEFAULT;
            break;

@@ -22,22 +22,22 @@
 #include "dynarec_arm_functions.h"
 #include "dynarec_arm_helper.h"

-static double maxint32 = (double)0x7fffffff;
-
 uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
 {
    uint8_t nextop = F8;
    uint8_t u8;
-    uint32_t u32;
-    int32_t i32;
-    int16_t i16;
-    uint16_t u16;
-    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
-    int v1, v2, v3;
-    int s0, s1, s2;
-    int d0;
+    int32_t j32;
+    uint8_t ed;
+    uint8_t wback;
+    int v1, v2;
+    int s0;
    int fixedaddress;
+    int parity;
+
+    MAYUSE(s0);
+    MAYUSE(v1);
+    MAYUSE(v2);
+    MAYUSE(j32);

    switch(nextop) {
        case 0xC0:
@@ -49,11 +49,10 @@ uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xC6:
        case 0xC7:
            INST_NAME("FCMOVNB ST0, STx");
-            USEFLAG(1);
+            READFLAGS(X_CF);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            LDR_IMM9(x1, xEmu, offsetof(x86emu_t, flags[F_CF]));
-            TSTS_REG_LSL_IMM8(x1, x1, 0);
+            TSTS_IMM8(xFlags, 1<<F_CF);
            VMOVcond_64(cEQ, v1, v2);   // F_CF==0
            break;
        case 0xC8:
@@ -65,11 +64,10 @@ uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xCE:
        case 0xCF:
            INST_NAME("FCMOVNE ST0, STx");
-            USEFLAG(1);
+            READFLAGS(X_ZF);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            LDR_IMM9(x1, xEmu, offsetof(x86emu_t, flags[F_ZF]));
-            TSTS_REG_LSL_IMM8(x1, x1, 0);
+            TSTS_IMM8(xFlags, 1<<F_ZF);
            VMOVcond_64(cEQ, v1, v2);   // F_ZF==0
            break;
        case 0xD0:
@@ -81,13 +79,11 @@ uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xD6:
        case 0xD7:
            INST_NAME("FCMOVNBE ST0, STx");
-            USEFLAG(1);
+            READFLAGS(X_CF|X_ZF);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            LDR_IMM9(x1, xEmu, offsetof(x86emu_t, flags[F_ZF]));
-            LDR_IMM9(x2, xEmu, offsetof(x86emu_t, flags[F_CF]));
-            ORRS_REG_LSL_IMM8(x1, x1, x2, 0);
-            VMOVcond_64(cEQ, v1, v2);   // F_CF==0 | F_ZF==0
+            TSTS_IMM8(xFlags, (1<<F_CF)|(1<<F_ZF));
+            VMOVcond_64(cEQ, v1, v2);   // F_CF==0 & F_ZF==0
            break;
        case 0xD8:
        case 0xD9:
@@ -98,17 +94,19 @@ uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xDE:
        case 0xDF:
            INST_NAME("FCMOVNU ST0, STx");
-            USEFLAG(1);
+            READFLAGS(X_PF);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            LDR_IMM9(x1, xEmu, offsetof(x86emu_t, flags[F_PF]));
-            TSTS_REG_LSL_IMM8(x1, x1, 0);
+            TSTS_IMM8(xFlags, 1<<F_PF);
            VMOVcond_64(cEQ, v1, v2);   // F_PF==0
            break;
+        case 0xE1:
+            INST_NAME("FDISI8087_NOP"); // so.. NOP?
+            break;
        case 0xE2:
            INST_NAME("FNCLEX");
-            MOVW(x1, 0);
            LDRH_IMM8(x2, xEmu, offsetof(x86emu_t, sw));
+            MOVW(x1, 0);
            BFI(x2, x1, 0, 8);  // IE .. PE, SF, ES
            BFI(x2, x1, 15, 1); // B
            STRH_IMM8(x2, xEmu, offsetof(x86emu_t, sw));
@@ -127,12 +125,11 @@ uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xEE:
        case 0xEF:
            INST_NAME("FUCOMI ST0, STx");
-            UFLAGS(0);
+            SETFLAGS(X_ALL, SF_SET);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
            VCMP_F64(v1, v2);
            FCOMI(x1, x2);
-            UFLAGS(1);
            break;
        case 0xF0:  
        case 0xF1:
@@ -143,21 +140,18 @@ uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xF6:
        case 0xF7:
            INST_NAME("FCOMI ST0, STx");
-            UFLAGS(0);
+            SETFLAGS(X_ALL, SF_SET);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
            VCMP_F64(v1, v2);
            FCOMI(x1, x2);
-            UFLAGS(1);
            break;

        case 0xE0:
-        case 0xE1:
        case 0xE4:
        case 0xE5:
        case 0xE6:
        case 0xE7:
-            *ok = 0;
            DEFAULT;
            break;

@@ -166,9 +160,15 @@ uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                case 0:
                    INST_NAME("FILD ST0, Ed");
                    v1 = x87_do_push(dyn, ninst);
-                    GETED;
                    s0 = fpu_get_scratch_single(dyn);
-                    VMOVtoV(s0, ed);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 1023, 0);
+                        VLDR_32(s0, ed, fixedaddress);
+                    } else {
+                        GETED;
+                        VMOVtoV(s0, ed);
+                    }
                    VCVT_F64_S32(v1, s0);
                    break;
                case 1:
@@ -183,8 +183,8 @@ uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                    }
                    s0 = fpu_get_scratch_single(dyn);
                    MSR_nzcvq_0();
-                    VMRS(x12);   // Get FPCSR reg to clear exceptions flags
-                    ORR_IMM8(x3, x12, 0b001, 6); // enable exceptions
+                    VMRS(x14);   // Get FPCSR reg to clear exceptions flags
+                    ORR_IMM8(x3, x14, 0b001, 6); // enable exceptions
                    BIC_IMM8(x3, x3, 0b10011111, 0);
                    VMSR(x3);
                    VCVT_S32_F64(s0, v1);
@@ -193,13 +193,13 @@ uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                    TSTS_IMM8_ROR(x3, 0b00000001, 0);
                    MOV_IMM_COND(cNE, ed, 0b10, 1);   // 0x80000000
                    WBACK;
-                    VMSR(x12);  // put back values
+                    VMSR(x14);  // put back values
                    x87_do_pop(dyn, ninst);
                    break;
                case 2:
                    INST_NAME("FIST Ed, ST0");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    u8 = x87_setround(dyn, ninst, x1, x2, x12); // x1 have the modified RPSCR reg
+                    u8 = x87_setround(dyn, ninst, x1, x2, x14); // x1 have the modified RPSCR reg
                    if((nextop&0xC0)==0xC0) {
                        ed = xEAX+(nextop&7);
                        wback = 0;
@@ -224,7 +224,7 @@ uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                case 3:
                    INST_NAME("FISTP Ed, ST0");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    u8 = x87_setround(dyn, ninst, x1, x2, x12); // x1 have the modified RPSCR reg
+                    u8 = x87_setround(dyn, ninst, x1, x2, x14); // x1 have the modified RPSCR reg
                    if((nextop&0xC0)==0xC0) {
                        ed = xEAX+(nextop&7);
                        wback = 0;
@@ -267,7 +267,6 @@ uintptr_t dynarecDB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                    x87_do_pop(dyn, ninst);
                    break;
                default:
-                    *ok = 0;
                    DEFAULT;
            }
    }
@@ -26,17 +26,16 @@
 uintptr_t dynarecDC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
 {
    uint8_t nextop = F8;
-    uint8_t u8;
-    uint32_t u32;
-    int32_t i32;
-    int16_t i16;
-    uint16_t u16;
-    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
-    int v1, v2, v3;
-    int s0, s1;
-    int d0, d1;
+    uint8_t wback;
+    int v1, v2;
+    int d1;
    int fixedaddress;
+    int parity;
+
+    MAYUSE(d1);
+    MAYUSE(v2);
+    MAYUSE(v1);
+
    switch(nextop) {
        case 0xC0:
        case 0xC1:
@@ -150,34 +149,66 @@ uintptr_t dynarecDC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                case 0:
                    INST_NAME("FADD ST0, double[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
                    d1 = fpu_get_scratch_double(dyn);
-                    VLDR_64(d1, wback, fixedaddress);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
+                        VLDR_64(d1, wback, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, 4095-4, 0);
+                        LDR_IMM9(x2, wback, fixedaddress);
+                        LDR_IMM9(x3, wback, fixedaddress+4);
+                        VMOVtoV_D(d1, x2, x3);
+                    }
                    VADD_F64(v1, v1, d1);
                    break;
                case 1:
                    INST_NAME("FMUL ST0, double[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
                    d1 = fpu_get_scratch_double(dyn);
-                    VLDR_64(d1, wback, fixedaddress);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
+                        VLDR_64(d1, wback, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, 4095-4, 0);
+                        LDR_IMM9(x2, wback, fixedaddress);
+                        LDR_IMM9(x3, wback, fixedaddress+4);
+                        VMOVtoV_D(d1, x2, x3);
+                    }
                    VMUL_F64(v1, v1, d1);
                    break;
                case 2:
                    INST_NAME("FCOM ST0, double[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
                    d1 = fpu_get_scratch_double(dyn);
-                    VLDR_64(d1, wback, fixedaddress);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
+                        VLDR_64(d1, wback, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, 4095-4, 0);
+                        LDR_IMM9(x2, wback, fixedaddress);
+                        LDR_IMM9(x3, wback, fixedaddress+4);
+                        VMOVtoV_D(d1, x2, x3);
+                    }
                    VCMP_F64(v1, d1);
                    FCOM(x1, x2);
                    break;
                case 3:
                    INST_NAME("FCOMP ST0, double[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
                    d1 = fpu_get_scratch_double(dyn);
-                    VLDR_64(d1, wback, fixedaddress);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
+                        VLDR_64(d1, wback, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, 4095-4, 0);
+                        LDR_IMM9(x2, wback, fixedaddress);
+                        LDR_IMM9(x3, wback, fixedaddress+4);
+                        VMOVtoV_D(d1, x2, x3);
+                    }
                    VCMP_F64(v1, d1);
                    FCOM(x1, x2);
                    x87_do_pop(dyn, ninst);
@@ -185,33 +216,65 @@ uintptr_t dynarecDC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                case 4:
                    INST_NAME("FSUB ST0, double[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
                    d1 = fpu_get_scratch_double(dyn);
-                    VLDR_64(d1, wback, fixedaddress);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
+                        VLDR_64(d1, wback, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, 4095-4, 0);
+                        LDR_IMM9(x2, wback, fixedaddress);
+                        LDR_IMM9(x3, wback, fixedaddress+4);
+                        VMOVtoV_D(d1, x2, x3);
+                    }
                    VSUB_F64(v1, v1, d1);
                    break;
                case 5:
                    INST_NAME("FSUBR ST0, double[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
                    d1 = fpu_get_scratch_double(dyn);
-                    VLDR_64(d1, wback, fixedaddress);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
+                        VLDR_64(d1, wback, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, 4095-4, 0);
+                        LDR_IMM9(x2, wback, fixedaddress);
+                        LDR_IMM9(x3, wback, fixedaddress+4);
+                        VMOVtoV_D(d1, x2, x3);
+                    }
                    VSUB_F64(v1, d1, v1);
                    break;
                case 6:
                    INST_NAME("FDIV ST0, double[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
                    d1 = fpu_get_scratch_double(dyn);
-                    VLDR_64(d1, wback, fixedaddress);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
+                        VLDR_64(d1, wback, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, 4095-4, 0);
+                        LDR_IMM9(x2, wback, fixedaddress);
+                        LDR_IMM9(x3, wback, fixedaddress+4);
+                        VMOVtoV_D(d1, x2, x3);
+                    }
                    VDIV_F64(v1, v1, d1);
                    break;
                case 7:
                    INST_NAME("FDIVR ST0, double[ED]");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
                    d1 = fpu_get_scratch_double(dyn);
-                    VLDR_64(d1, wback, fixedaddress);
+                    parity = getedparity(dyn, ninst, addr, nextop, 2);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 1023, 3);
+                        VLDR_64(d1, wback, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, 4095-4, 0);
+                        LDR_IMM9(x2, wback, fixedaddress);
+                        LDR_IMM9(x3, wback, fixedaddress+4);
+                        VMOVtoV_D(d1, x2, x3);
+                    }
                    VDIV_F64(v1, d1, v1);
                    break;
            }
@@ -27,15 +27,13 @@
 uintptr_t dynarecDD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
 {
    uint8_t nextop = F8;
-    uint8_t u8;
-    uint32_t u32;
-    int32_t i32;
-    int16_t i16;
-    uint16_t u16;
-    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
    int fixedaddress;
-    int v1, v2, v3;
+    int parity;
+    uint8_t ed;
+    int v1, v2;
+
+    MAYUSE(v2);
+    MAYUSE(v1);

    switch(nextop) {
        case 0xC0:
@@ -133,7 +131,6 @@ uintptr_t dynarecDD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xFD:
        case 0xFE:
        case 0xFF:
-            *ok = 0;
            DEFAULT;
            break;

@@ -147,9 +144,16 @@ uintptr_t dynarecDD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3);
                    VLDR_64(v1, ed, fixedaddress);
                    #else
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 255, 0);
-                    LDRD_IMM8(x2, ed, fixedaddress);
-                    VMOVtoV_D(v1, x2, x3);
+		            parity = getedparity(dyn, ninst, addr, nextop, 3);
+		            if (parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3);
+                        VLDR_64(v1, ed, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095-4, 0);
+                        LDR_IMM9(x2, ed, fixedaddress);
+                        LDR_IMM9(x3, ed, fixedaddress + 4);
+                        VMOVtoV_D(v1, x2, x3);
+        		    }
                    #endif
                    break;
                case 1:
@@ -163,18 +167,58 @@ uintptr_t dynarecDD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                case 2:
                    INST_NAME("FST double");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3);
-                    VSTR_64(v1, ed, fixedaddress); // check alignment?
+                    parity = getedparity(dyn, ninst, addr, nextop, 3);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3);
+                        VSTR_64(v1, ed, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095-4, 0);
+                        VMOVfrV_D(x2, x3, v1);
+                        STR_IMM9(x2, ed, fixedaddress);
+                        STR_IMM9(x3, ed, fixedaddress+4);
+                    }
                    break;
                case 3:
                    INST_NAME("FSTP double");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3);
-                    VSTR_64(v1, ed, fixedaddress); // check alignment?
+                    parity = getedparity(dyn, ninst, addr, nextop, 3);
+                    if(parity) {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3);
+                        VSTR_64(v1, ed, fixedaddress);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095-4, 0);
+                        VMOVfrV_D(x2, x3, v1);
+                        STR_IMM9(x2, ed, fixedaddress);
+                        STR_IMM9(x3, ed, fixedaddress+4);
+                    }
                    x87_do_pop(dyn, ninst);
                    break;
+                case 4: 
+                    INST_NAME("FRSTOR m108byte");
+                    fpu_purgecache(dyn, ninst, x1, x2, x3);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0);
+                    if(ed!=x1) {MOV_REG(x1, ed);}
+                    CALL(arm_frstor, -1, 0);
+                    break;
+                case 6: 
+                    INST_NAME("FSAVE m108byte");
+                    fpu_purgecache(dyn, ninst, x1, x2, x3);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0);
+                    if(ed!=x1) {MOV_REG(x1, ed);}
+                    CALL(arm_fsave, -1, 0);
+                    break;
+                case 7:
+                    INST_NAME("FNSTSW m2byte");
+                    fpu_purgecache(dyn, ninst, x1, x2, x3);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x14, &fixedaddress, 0, 0);
+                    LDR_IMM9(x1, xEmu, offsetof(x86emu_t, top));
+                    MOVW(x2, offsetof(x86emu_t, sw));
+                    ADD_REG_LSL_IMM5(x2, xEmu, x2, 0);
+                    LDRH_IMM8(x3, x2, 0);
+                    BFI(x3, x1, 11, 3); // inject TOP at bit 11 (3 bits)
+                    STRH_IMM8(x3, ed, 0);   // store whole sw flags
+                    break;
                default:
-                    *ok = 0;
                    DEFAULT;
            }
    }
@@ -25,16 +25,10 @@
 uintptr_t dynarecDE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
 {
    uint8_t nextop = F8;
-    uint8_t u8;
-    uint32_t u32;
-    int32_t i32;
-    int16_t i16;
-    uint16_t u16;
-    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
-    int v1, v2, v3;
-    int s0, s1, s2;
-    int fixedaddress;
+    int v1, v2;
+
+    MAYUSE(v2);
+    MAYUSE(v1);

    switch(nextop) {
        case 0xC0:
@@ -65,7 +59,23 @@ uintptr_t dynarecDE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
            VMUL_F64(v2, v2, v1);
            x87_do_pop(dyn, ninst);
            break;
-        case 0xD9:  /* FCOMPP */
+        case 0xD0:
+        case 0xD1:
+        case 0xD2:
+        case 0xD3:
+        case 0xD4:
+        case 0xD5:
+        case 0xD6:
+        case 0xD7:
+            INST_NAME("FCOMP ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
+            VCMP_F64(v1, v2);
+            FCOM(x1, x2);
+            x87_do_pop(dyn, ninst);
+            break;
+
+        case 0xD9: 
            INST_NAME("FCOMPP ST0, ST1");
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, 1);
@@ -131,14 +141,6 @@ uintptr_t dynarecDE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
            x87_do_pop(dyn, ninst);
            break;

-        case 0xD0:
-        case 0xD1:
-        case 0xD2:
-        case 0xD3:
-        case 0xD4:
-        case 0xD5:
-        case 0xD6:
-        case 0xD7:
        case 0xD8:
        case 0xDA:
        case 0xDB:
@@ -146,7 +148,6 @@ uintptr_t dynarecDE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xDD:
        case 0xDE:
        case 0xDF:
-            *ok = 0;
            DEFAULT;
            break;

@@ -154,7 +155,6 @@ uintptr_t dynarecDE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        default:
            switch((nextop>>3)&7) {
                default:
-                    *ok = 0;
                    DEFAULT;
            }
    }
@@ -28,18 +28,32 @@ uintptr_t dynarecDF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
 {
    uint8_t nextop = F8;
    uint8_t u8;
-    uint32_t u32;
-    int32_t i32;
-    int16_t i16;
-    uint16_t u16;
-    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
-    int v1, v2, v3;
-    int s0, s1;
-    int d0;
+    int32_t j32;
+    uint8_t wback;
+    uint8_t ed;
+    int v1, v2;
+    int s0;
    int fixedaddress;

+    MAYUSE(s0);
+    MAYUSE(v2);
+    MAYUSE(v1);
+    MAYUSE(j32);
+
    switch(nextop) {
+        case 0xC0:
+        case 0xC1:
+        case 0xC2:
+        case 0xC3:
+        case 0xC4:
+        case 0xC5:
+        case 0xC6:
+        case 0xC7:
+            INST_NAME("FFREEP STx");
+            // not handling Tag...
+            x87_do_pop(dyn, ninst);
+            break;
+
        case 0xE0:
            INST_NAME("FNSTSW AX");
            LDR_IMM9(x2, xEmu, offsetof(x86emu_t, top));
@@ -57,13 +71,12 @@ uintptr_t dynarecDF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xEE:
        case 0xEF:
            INST_NAME("FUCOMIP ST0, STx");
-            UFLAGS(0);
+            SETFLAGS(X_ALL, SF_SET);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
            VCMP_F64(v1, v2);
            FCOMI(x1, x2);
            x87_do_pop(dyn, ninst);
-            UFLAGS(1);
            break;
        case 0xF0:
        case 0xF1:
@@ -74,23 +87,14 @@ uintptr_t dynarecDF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xF6:
        case 0xF7:
            INST_NAME("FCOMIP ST0, STx");
-            UFLAGS(0);
+            SETFLAGS(X_ALL, SF_SET);
            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
            VCMP_F64(v1, v2);
            FCOMI(x1, x2);
            x87_do_pop(dyn, ninst);
-            UFLAGS(1);
            break;

-        case 0xC0:
-        case 0xC1:
-        case 0xC2:
-        case 0xC3:
-        case 0xC4:
-        case 0xC5:
-        case 0xC6:
-        case 0xC7:
        case 0xC8:
        case 0xC9:
        case 0xCA:
@@ -130,7 +134,6 @@ uintptr_t dynarecDF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        case 0xFD:
        case 0xFE:
        case 0xFF:
-            *ok = 0;
            DEFAULT;
            break;

@@ -148,59 +151,68 @@ uintptr_t dynarecDF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                case 1:
                    INST_NAME("FISTTP Ew, ST0");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    u8 = x87_setround(dyn, ninst, x1, x2, x12);
                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 255, 0);
                    ed = x1;
                    s0 = fpu_get_scratch_single(dyn);
-                    VCVT_S32_F64(s0, v1);
+                    MSR_nzcvq_0();
+                    VMRS(x14);               // get fpscr
+                    // x1 already have FPCSR reg to clear exceptions flags
+                    ORR_IMM8(x3, x14, 0b001, 6); // enable exceptions
+                    BIC_IMM8(x3, x3, 0b10011111, 0);
+                    VMSR(x3);
+                    VCVTR_S32_F64(s0, v1);
+                    VMRS(x3);   // get the FPCSR reg and test FPU execption (invalid operation only)
                    VMOVfrV(ed, s0);
-                    MSR_nzcvq_0();    // reset Q flag (and all other flags too)
-                    SSAT_REG_LSL_IMM5(ed, 16, ed, 0);
-                    MRS_aspr(x3);   // check Q flag
-                    TSTS_IMM8_ROR(x3, 0b10, 3);
-                    B_MARK(cEQ);    // not saturated, continue
-                    MOV32(ed, 0xffff8000);
-                    MARK;
-                    STRH_IMM8(ed, wback, fixedaddress);
+                    TSTS_IMM8_ROR(x3, 0b00000001, 0);
+                    SSAT_REG_LSL_IMM5_COND(cEQ, x3, 16, ed, 0);
+                    CMPS_REG_LSL_IMM5_COND(cEQ, ed, x3, 0);
+                    MOVW_COND(cNE, x3, 0x8000); // saturated
+                    STRH_IMM8(x3, wback, fixedaddress);
                    x87_do_pop(dyn, ninst);
-                    x87_restoreround(dyn, ninst, u8);
+                    VMSR(x14);
                    break;
                case 2:
                    INST_NAME("FIST Ew, ST0");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    u8 = x87_setround(dyn, ninst, x1, x2, x12);
+                    u8 = x87_setround(dyn, ninst, x1, x2, x14);
                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 255, 0);
                    ed = x1;
                    s0 = fpu_get_scratch_single(dyn);
+                    MSR_nzcvq_0();
+                    // x1 already have FPCSR reg to clear exceptions flags
+                    ORR_IMM8(x3, x1, 0b001, 6); // enable exceptions
+                    BIC_IMM8(x3, x3, 0b10011111, 0);
+                    VMSR(x3);
                    VCVTR_S32_F64(s0, v1);
+                    VMRS(x3);   // get the FPCSR reg and test FPU execption (invalid operation only)
                    VMOVfrV(ed, s0);
-                    MSR_nzcvq_0();    // reset Q flag (and all other flags too)
-                    SSAT_REG_LSL_IMM5(ed, 16, ed, 0);
-                    MRS_aspr(x3);   // check Q flag
-                    TSTS_IMM8_ROR(x3, 0b10, 3);
-                    B_MARK(cEQ);    // not saturated, continue
-                    MOV32(ed, 0xffff8000);
-                    MARK;
-                    STRH_IMM8(ed, wback, fixedaddress);
+                    TSTS_IMM8_ROR(x3, 0b00000001, 0);
+                    SSAT_REG_LSL_IMM5_COND(cEQ, x3, 16, ed, 0);
+                    CMPS_REG_LSL_IMM5_COND(cEQ, ed, x3, 0);
+                    MOVW_COND(cNE, x3, 0x8000); // saturated
+                    STRH_IMM8(x3, wback, fixedaddress);
                    x87_restoreround(dyn, ninst, u8);
                    break;
                case 3:
                    INST_NAME("FISTP Ew, ST0");
                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    u8 = x87_setround(dyn, ninst, x1, x2, x12);
+                    u8 = x87_setround(dyn, ninst, x1, x2, x14);
                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 255, 0);
                    ed = x1;
                    s0 = fpu_get_scratch_single(dyn);
+                    MSR_nzcvq_0();
+                    // x1 already have FPCSR reg to clear exceptions flags
+                    ORR_IMM8(x3, x1, 0b001, 6); // enable exceptions
+                    BIC_IMM8(x3, x3, 0b10011111, 0);
+                    VMSR(x3);
                    VCVTR_S32_F64(s0, v1);
+                    VMRS(x3);   // get the FPCSR reg and test FPU execption (invalid operation only)
                    VMOVfrV(ed, s0);
-                    MSR_nzcvq_0();    // reset Q flag (and all other flags too)
-                    SSAT_REG_LSL_IMM5(ed, 16, ed, 0);
-                    MRS_aspr(x3);   // check Q flag
-                    TSTS_IMM8_ROR(x3, 0b10, 3);
-                    B_MARK(cEQ);    // not saturated, continue
-                    MOV32(ed, 0xffff8000);
-                    MARK;
-                    STRH_IMM8(ed, wback, fixedaddress);
+                    TSTS_IMM8_ROR(x3, 0b00000001, 0);
+                    SSAT_REG_LSL_IMM5_COND(cEQ, x3, 16, ed, 0);
+                    CMPS_REG_LSL_IMM5_COND(cEQ, ed, x3, 0);
+                    MOVW_COND(cNE, x3, 0x8000); // saturated
+                    STRH_IMM8(x3, wback, fixedaddress);
                    x87_do_pop(dyn, ninst);
                    x87_restoreround(dyn, ninst, u8);
                    break;
@@ -235,7 +247,6 @@ uintptr_t dynarecDF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
                    x87_do_pop(dyn, ninst);
                    break;
                default:
-                    *ok = 0;
                    DEFAULT;
            }
    }
@@ -0,0 +1,874 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <pthread.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box86context.h"
+#include "dynarec.h"
+#include "emu/x86emu_private.h"
+#include "emu/x86run_private.h"
+#include "x86run.h"
+#include "x86emu.h"
+#include "box86stack.h"
+#include "callback.h"
+#include "emu/x86run_private.h"
+#include "x86trace.h"
+#include "dynarec_arm.h"
+#include "dynarec_arm_private.h"
+#include "arm_printer.h"
+#include "../tools/bridge_private.h"
+
+#include "dynarec_arm_functions.h"
+#include "dynarec_arm_helper.h"
+
+// emit OR32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+void emit_or32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_or32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    IFX(X_ALL) {
+        ORRS_REG_LSL_IMM5(s1, s1, s2, 0);
+    } else {
+        ORR_REG_LSL_IMM5(s1, s1, s2, 0);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit OR32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_or32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOV32(s3, c);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_or32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(c>=0 && c<256) {
+        IFX(X_ALL) {
+            ORRS_IMM8(s1, s1, c, 0);
+        } else {
+            ORR_IMM8(s1, s1, c, 0);
+        }
+    } else {
+        IFX(X_PEND) {} else {MOV32(s3, c);}
+        IFX(X_ALL) {
+            ORRS_REG_LSL_IMM5(s1, s1, s3, 0);
+        } else {
+            ORR_REG_LSL_IMM5(s1, s1, s3, 0);
+        }
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit XOR32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+void emit_xor32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_xor32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    IFX(X_ALL) {
+        XORS_REG_LSL_IMM5(s1, s1, s2, 0);
+    } else {
+        XOR_REG_LSL_IMM5(s1, s1, s2, 0);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit XOR32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_xor32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOV32(s3, c);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_xor32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(c>=0 && c<256) {
+        IFX(X_ALL) {
+            XORS_IMM8(s1, s1, c);
+        } else {
+            XOR_IMM8(s1, s1, c);
+        }
+    } else {
+        IFX(X_PEND) {} else {MOV32(s3, c);}
+        IFX(X_ALL) {
+            XORS_REG_LSL_IMM5(s1, s1, s3, 0);
+        } else {
+            XOR_REG_LSL_IMM5(s1, s1, s3, 0);
+        }
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit AND32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+void emit_and32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_and32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    IFX(X_ALL) {
+        ANDS_REG_LSL_IMM5(s1, s1, s2, 0);
+    } else {
+        AND_REG_LSL_IMM5(s1, s1, s2, 0);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit AND32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_and32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOV32(s3, c);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_and32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(c>=0 && c<256) {
+        IFX(X_ALL) {
+            ANDS_IMM8(s1, s1, c);
+        } else {
+            AND_IMM8(s1, s1, c);
+        }
+    } else {
+        IFX(X_PEND) {} else {MOV32(s3, c);}
+        IFX(X_ALL) {
+            ANDS_REG_LSL_IMM5(s1, s1, s3, 0);
+        } else {
+            AND_REG_LSL_IMM5(s1, s1, s3, 0);
+        }
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit OR8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+void emit_or8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s3, d_or8);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s3);
+    }
+    IFX(X_ALL) {
+        ORRS_REG_LSL_IMM5(s1, s1, s2, 0);
+    } else {
+        ORR_REG_LSL_IMM5(s1, s1, s2, 0);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 7);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        if(save_s4) {PUSH(xSP, 1<<s4);}
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+        if(save_s4) {POP(xSP, 1<<s4);}
+    }
+}
+
+// emit OR8 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOV32(s3, c&0xff);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_or8);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    IFX(X_ALL) {
+        ORRS_IMM8(s1, s1, c, 0);
+    } else {
+        ORR_IMM8(s1, s1, c, 0);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 7);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit XOR8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+void emit_xor8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s3, d_xor8);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s3);
+    }
+    IFX(X_ALL) {
+        XORS_REG_LSL_IMM5(s1, s1, s2, 0);
+    } else {
+        XOR_REG_LSL_IMM5(s1, s1, s2, 0);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 7);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        if(save_s4) {PUSH(xSP, 1<<s4);}
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+        if(save_s4) {POP(xSP, 1<<s4);}
+    }
+}
+
+// emit XOR8 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOV32(s3, c&0xff);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_xor8);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    IFX(X_ALL) {
+        XORS_IMM8(s1, s1, c);
+    } else {
+        XOR_IMM8(s1, s1, c);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 7);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit AND8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+void emit_and8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s3, d_and8);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s3);
+    }
+    IFX(X_ALL) {
+        ANDS_REG_LSL_IMM5(s1, s1, s2, 0);
+    } else {
+        AND_REG_LSL_IMM5(s1, s1, s2, 0);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 7);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        if(save_s4) {PUSH(xSP, 1<<s4);}
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+        if(save_s4) {POP(xSP, 1<<s4);}
+    }
+}
+
+// emit AND8 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOV32(s3, c&0xff);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_and8);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    IFX(X_ALL) {
+        ANDS_IMM8(s1, s1, c);
+    } else {
+        AND_IMM8(s1, s1, c);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 7);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+
+// emit OR16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+void emit_or16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s3, d_or16);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s3);
+    }
+    IFX(X_ALL) {
+        ORRS_REG_LSL_IMM5(s1, s1, s2, 0);
+    } else {
+        ORR_REG_LSL_IMM5(s1, s1, s2, 0);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 15);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        if(save_s4) {PUSH(xSP, 1<<s4);}
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+        if(save_s4) {POP(xSP, 1<<s4);}
+    }
+}
+
+// emit OR16 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_or16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s3, c);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_or16);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(c>=0 && c<256) {
+        IFX(X_ALL) {
+            ORRS_IMM8(s1, s1, c, 0);
+        } else {
+            ORR_IMM8(s1, s1, c, 0);
+        }
+    } else {
+        IFX(X_PEND) {} else {MOVW(s3, c);}
+        IFX(X_ALL) {
+            ORRS_REG_LSL_IMM5(s1, s1, s3, 0);
+        } else {
+            ORR_REG_LSL_IMM5(s1, s1, s3, 0);
+        }
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 15);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit XOR16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+void emit_xor16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s3, d_xor16);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s3);
+    }
+    IFX(X_ALL) {
+        XORS_REG_LSL_IMM5(s1, s1, s2, 0);
+    } else {
+        XOR_REG_LSL_IMM5(s1, s1, s2, 0);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 15);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        if(save_s4) {PUSH(xSP, 1<<s4);}
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+        if(save_s4) {POP(xSP, 1<<s4);}
+    }
+}
+
+// emit XOR16 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_xor16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s3, c);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_xor16);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(c>=0 && c<256) {
+        IFX(X_ALL) {
+            XORS_IMM8(s1, s1, c);
+        } else {
+            XOR_IMM8(s1, s1, c);
+        }
+    } else {
+        IFX(X_PEND) {} else {MOVW(s3, c);}
+        IFX(X_ALL) {
+            XORS_REG_LSL_IMM5(s1, s1, s3, 0);
+        } else {
+            XOR_REG_LSL_IMM5(s1, s1, s3, 0);
+        }
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 15);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit AND16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s3, d_and16);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s3);
+    }
+    IFX(X_ALL) {
+        ANDS_REG_LSL_IMM5(s1, s1, s2, 0);
+    } else {
+        AND_REG_LSL_IMM5(s1, s1, s2, 0);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 15);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        if(save_s4) {PUSH(xSP, 1<<s4);}
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+        if(save_s4) {POP(xSP, 1<<s4);}
+    }
+}
+
+// emit AND16 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_and16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s3, c);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_and16);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(c>=0 && c<256) {
+        IFX(X_ALL) {
+            ANDS_IMM8(s1, s1, c);
+        } else {
+            AND_IMM8(s1, s1, c);
+        }
+    } else {
+        IFX(X_PEND) {} else {MOVW(s3, c);}
+        IFX(X_ALL) {
+            ANDS_REG_LSL_IMM5(s1, s1, s3, 0);
+        } else {
+            AND_REG_LSL_IMM5(s1, s1, s3, 0);
+        }
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 15);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
@@ -0,0 +1,379 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <pthread.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box86context.h"
+#include "dynarec.h"
+#include "emu/x86emu_private.h"
+#include "emu/x86run_private.h"
+#include "x86run.h"
+#include "x86emu.h"
+#include "box86stack.h"
+#include "callback.h"
+#include "emu/x86run_private.h"
+#include "x86trace.h"
+#include "dynarec_arm.h"
+#include "dynarec_arm_private.h"
+#include "arm_printer.h"
+#include "../tools/bridge_private.h"
+
+#include "dynarec_arm_functions.h"
+#include "dynarec_arm_helper.h"
+
+// emit SHL32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_shl32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s3, c);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_shl32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(c==0) {
+        IFX(F_OF) {
+            BIC_IMM8(xFlags, xFlags, 0b10, 0x0b);
+        }
+        IFX(X_PEND) {
+            STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+        }
+        return;
+    }
+    IFX(X_CF) {
+        MOV_REG_LSR_IMM5(s3, s1, 32-c);
+        BFI(xFlags, s3, F_CF, 1);
+    }
+    IFX(X_ZF|X_OF) {
+        MOVS_REG_LSL_IMM5(s1, s1, c);
+    } else {
+        MOV_REG_LSL_IMM5(s1, s1, c);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_OF) {
+        if(c==1) {
+            IFX(X_SF) {} else {MOV_REG_LSR_IMM5(s3, s1, 31);}
+            XOR_IMM8_COND(cCS, s3, s3, 1);
+            BFI(xFlags, s3, F_OF, 1);
+        } else {
+            BFC(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit SHR32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_shr32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s3, c);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_shr32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(!c) {
+        IFX(X_PEND) {
+            STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+        }
+        return;
+    }
+    IFX(X_ZF|X_CF) {
+        MOVS_REG_LSR_IMM5(s1, s1, c);
+    } else {
+        MOV_REG_LSR_IMM5(s1, s1, c);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_CF) {
+        ORR_IMM8_COND(cCS, xFlags, xFlags, 1<<F_CF, 0);
+        BIC_IMM8_COND(cCC, xFlags, xFlags, 1<<F_CF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_OF) {
+        if(c==1) {
+            MOV_REG_LSR_IMM5(s4, s1, 30);
+            XOR_REG_LSR_IMM8(s4, s4, s4, 1);
+            BFI(xFlags, s4, F_OF, 1);
+        }
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit SAR32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_sar32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s3, c);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_sar32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(!c) {
+        IFX(X_PEND) {
+            STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+        }
+        return;
+    }
+    IFX(X_ZF|X_CF) {
+        MOVS_REG_ASR_IMM5(s1, s1, c);
+    } else {
+        MOV_REG_ASR_IMM5(s1, s1, c);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_CF) {
+        ORR_IMM8_COND(cCS, xFlags, xFlags, 1<<F_CF, 0);
+        BIC_IMM8_COND(cCC, xFlags, xFlags, 1<<F_CF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit ROL32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_rol32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s3, c);
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_rol32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(!c) {
+        IFX(X_PEND) {
+            STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+        }
+        return;
+    }
+    MOV_REG_ROR_IMM5(s1, s1, 32-c);
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF) {
+        BFI(xFlags, s1, F_CF, 1);
+    }
+    IFX(X_OF) {
+        if(c==1) {
+            ADD_REG_LSR_IMM5(s3, s1, s1, 31);
+            AND_IMM8(s3, s3, 1);
+            BFI(xFlags, s3, F_OF, 1);
+        }
+    }
+}
+
+// emit ROR32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_ror32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s3, c);
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_ror32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(!c) {
+        IFX(X_PEND) {
+            STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+        }
+        return;
+    }
+    MOV_REG_ROR_IMM5(s1, s1, c);
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_CF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_CF, 1);
+    }
+    IFX(X_OF) {
+        if(c==1) {
+            MOV_REG_LSR_IMM5(s4, s1, 30);
+            XOR_REG_LSR_IMM8(s4, s4, s4, 1);
+            BFI(xFlags, s4, F_OF, 1);
+        }
+    }
+}
+
+// emit SHRD32 instruction, from s1, fill s2 , constant c, store result in s1 using s3 and s4 as scratch
+void emit_shrd32c(dynarec_arm_t* dyn, int ninst, int s1, int s2, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s3, c);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        // same flags calc as shr32
+        SET_DF(s4, d_shr32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(!c) {
+        IFX(X_PEND) {
+            STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+        }
+        return;
+    }
+    IFX(X_CF) {
+        MOVS_REG_LSR_IMM5(s1, s1, c);
+    } else {
+        MOV_REG_LSR_IMM5(s1, s1, c);
+    }
+    IFX(X_CF) {
+        ORR_IMM8_COND(cCS, xFlags, xFlags, 1<<F_CF, 0);
+        BIC_IMM8_COND(cCC, xFlags, xFlags, 1<<F_CF, 0);
+    }
+    IFX(X_ZF) {
+        ORRS_REG_LSL_IMM5(s1, s1, s2, 32-c);
+    } else {
+        ORR_REG_LSL_IMM5(s1, s1, s2, 32-c);
+    }
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_OF) {
+        if(c==1) {
+            MOV_REG_LSR_IMM5(s4, s1, 30);
+            XOR_REG_LSR_IMM8(s4, s4, s4, 1);
+            BFI(xFlags, s4, F_OF, 1);
+        }
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+void emit_shld32c(dynarec_arm_t* dyn, int ninst, int s1, int s2, int32_t c, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s3, c);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        // same flags computation as with shl32
+        SET_DF(s4, d_shl32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(c==0) {
+        IFX(F_OF) {
+            BFC(xFlags, F_OF, 1);
+        }
+        IFX(X_PEND) {
+            STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+        }
+        return;
+    }
+    IFX(X_CF) {
+        MOV_REG_LSR_IMM5(s3, s1, 32-c);
+        BFI(xFlags, s3, F_CF, 1);
+    }
+    IFX(X_OF) {
+        MOVS_REG_LSL_IMM5(s1, s1, c);
+    } else {
+        MOV_REG_LSL_IMM5(s1, s1, c);
+    }
+    IFX(X_OF) {
+        if(c==1) {
+            UBFX(s3, s2, 0, 1);
+            XOR_IMM8_COND(cCS, s3, s3, 1);
+            BFI(xFlags, s3, F_OF, 1);
+        } else {
+            BFC(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_ZF) {
+        ORRS_REG_LSR_IMM5(s1, s1, s2, 32-c);
+    } else {
+        ORR_REG_LSR_IMM5(s1, s1, s2, 32-c);
+    }
+
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s3, s1, 31);
+        BFI(xFlags, s3, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
@@ -0,0 +1,433 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <pthread.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box86context.h"
+#include "dynarec.h"
+#include "emu/x86emu_private.h"
+#include "emu/x86run_private.h"
+#include "x86run.h"
+#include "x86emu.h"
+#include "box86stack.h"
+#include "callback.h"
+#include "emu/x86run_private.h"
+#include "x86trace.h"
+#include "dynarec_arm.h"
+#include "dynarec_arm_private.h"
+#include "arm_printer.h"
+#include "../tools/bridge_private.h"
+
+#include "dynarec_arm_functions.h"
+#include "dynarec_arm_helper.h"
+
+// emit CMP32 instruction, from cmp s1 , s2, using s3 and s4 as scratch
+void emit_cmp32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_cmp32);
+    } else {
+        SET_DFNONE(s4);
+    }
+    SUBS_REG_LSL_IMM5(s3, s1, s2, 0);   // res = s1 - s2
+    IFX(X_PEND) {
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_OF) {
+        ORR_IMM8_COND(cVS, xFlags, xFlags, 0b10, 0x0b);
+        BIC_IMM8_COND(cVC, xFlags, xFlags, 0b10, 0x0b);
+    }
+    IFX(X_CF) {
+        // reversed carry
+        ORR_IMM8_COND(cCC, xFlags, xFlags, 1<<F_CF, 0);
+        BIC_IMM8_COND(cCS, xFlags, xFlags, 1<<F_CF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s4, s3, 31);
+        BFI(xFlags, s4, F_SF, 1);
+    }
+    // and now the tricky ones (and mostly unused), PF and AF
+    IFX(X_AF) {
+        // bc = (res & (~d | s)) | (~d & s)
+        MVN_REG_LSL_IMM5(s4, s1, 0);        // s4 = ~d
+        ORR_REG_LSL_IMM5(s4, s4, s2, 0);    // s4 = ~d | s
+        AND_REG_LSL_IMM5(s4, s4, s3, 0);    // s4 = res & (~d | s)
+        BIC_REG_LSL_IMM5(s3, s2, s1, 0);    // loosing res... s3 = s & ~d
+        ORR_REG_LSL_IMM5(s3, s4, s3, 0);    // s3 = (res & (~d | s)) | (s & ~d)
+        IFX(X_AF) {
+            MOV_REG_LSR_IMM5(s4, s3, 3);
+            BFI(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
+        }
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        IFX(X_CF|X_AF) {
+            SUB_REG_LSL_IMM5(s3, s1, s2, 0);
+        }
+        AND_IMM8(s3, s3, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        SUB_REG_LSL_IMM5(s3, s1, s2, 0);
+        AND_IMM8(s3, s3, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit CMP32 instruction, from cmp s1 , 0, using s3 and s4 as scratch
+void emit_cmp32_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s4, 0);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s4, xEmu, offsetof(x86emu_t, op2));
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+        SET_DF(s4, d_cmp32);
+    } else {
+        SET_DFNONE(s4);
+    }
+    SUBS_IMM8(s3, s1, 0);   // res = s1 - 0
+    // and now the tricky ones (and mostly unused), PF and AF
+    // bc = (res & (~d | s)) | (~d & s) => is 0 here...
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BFC(xFlags, F_OF, 1);
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s4, s3, 31);
+        BFI(xFlags, s4, F_SF, 1);
+    }
+    IFX(X_PF) {
+        // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit CMP16 instruction, from cmp s1 , s2, using s3 and s4 as scratch
+void emit_cmp16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s3, d_cmp16);
+    } else {
+        SET_DFNONE(s3);
+    }
+    SUB_REG_LSL_IMM5(s3, s1, s2, 0);   // res = s1 - s2
+    IFX(X_PEND) {
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_ZF) {
+        MOVW(s4, 0xffff);
+        TSTS_REG_LSL_IMM5(s3, s4, 0);
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s4, s3, 15);
+        BFI(xFlags, s4, F_SF, 1);
+    }
+    // bc = (res & (~d | s)) | (~d & s)
+    IFX(X_CF|X_AF|X_OF) {
+        MVN_REG_LSL_IMM5(s4, s1, 0);        // s4 = ~d
+        ORR_REG_LSL_IMM5(s4, s4, s2, 0);    // s4 = ~d | s
+        AND_REG_LSL_IMM5(s4, s4, s3, 0);    // s4 = res & (~d | s)
+        BIC_REG_LSL_IMM5(s3, s2, s1, 0);    // loosing res... s3 = s & ~d
+        ORR_REG_LSL_IMM5(s3, s4, s3, 0);    // s3 = (res & (~d | s)) | (s & ~d)
+        IFX(X_CF) {
+            MOV_REG_LSR_IMM5(s4, s3, 15);
+            BFI(xFlags, s4, F_CF, 1);    // CF : bc & 0x8000
+        }
+        IFX(X_AF) {
+            MOV_REG_LSR_IMM5(s4, s3, 3);
+            BFI(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
+        }
+        IFX(X_OF) {
+            MOV_REG_LSR_IMM5(s4, s3, 14);
+            XOR_REG_LSR_IMM8(s4, s4, s4, 1);
+            BFI(xFlags, s4, F_OF, 1);    // OF: ((bc >> 14) ^ ((bc>>14)>>1)) & 1
+        }
+    }
+    // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+    IFX(X_PF) {
+        IFX(X_CF|X_AF|X_OF) {
+            SUB_REG_LSL_IMM5(s3, s1, s2, 0);
+        }
+        AND_IMM8(s3, s3, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        SUB_REG_LSL_IMM5(s3, s1, s2, 0);
+        AND_IMM8(s3, s3, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit CMP16 instruction, from cmp s1 , #0, using s3 and s4 as scratch
+void emit_cmp16_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
+{
+    IFX(X_PEND) {
+        MOVW(s3, 0);
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, op2));
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+        SET_DF(s3, d_cmp16);
+    } else {
+        SET_DFNONE(s3);
+    }
+    // bc = (res & (~d | s)) | (~d & s) = 0
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BFC(xFlags, F_OF, 1);
+    }
+    IFX(X_ZF) {
+        MOVW(s4, 0xffff);
+        TSTS_REG_LSL_IMM5(s1, s4, 0);
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s4, s1, 15);
+        BFI(xFlags, s4, F_SF, 1);
+    }
+    // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+    IFX(X_PF) {
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+// emit CMP8 instruction, from cmp s1 , s2, using s3 and s4 as scratch
+void emit_cmp8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        STR_IMM9(s2, xEmu, offsetof(x86emu_t, op2));
+        SET_DF(s4, d_cmp8);
+    } else {
+        SET_DFNONE(s4);
+    }
+    SUB_REG_LSL_IMM5(s3, s1, s2, 0);   // res = s1 - s2
+    IFX(X_PEND) {
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_ZF) {
+        TSTS_IMM8(s3, 0xff);
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s4, s3, 7);
+        BFI(xFlags, s4, F_SF, 1);
+    }
+    // bc = (res & (~d | s)) | (~d & s)
+    IFX(X_CF|X_AF|X_OF) {
+        MVN_REG_LSL_IMM5(s4, s1, 0);        // s4 = ~d
+        ORR_REG_LSL_IMM5(s4, s4, s2, 0);    // s4 = ~d | s
+        AND_REG_LSL_IMM5(s4, s4, s3, 0);    // s4 = res & (~d | s)
+        BIC_REG_LSL_IMM5(s3, s2, s1, 0);    // loosing res... s3 = s & ~d
+        ORR_REG_LSL_IMM5(s3, s4, s3, 0);    // s3 = (res & (~d | s)) | (s & ~d)
+        IFX(X_CF) {
+            MOV_REG_LSR_IMM5(s4, s3, 7);
+            BFI(xFlags, s4, F_CF, 1);    // CF : bc & 0x80
+        }
+        IFX(X_AF) {
+            MOV_REG_LSR_IMM5(s4, s3, 3);
+            BFI(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
+        }
+        IFX(X_OF) {
+            MOV_REG_LSR_IMM5(s4, s3, 6);
+            XOR_REG_LSR_IMM8(s4, s4, s4, 1);
+            BFI(xFlags, s4, F_OF, 1);    // OF: ((bc >> 6) ^ ((bc>>6)>>1)) & 1
+        }
+    }
+    // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+    IFX(X_PF) {
+        IFX(X_CF|X_AF|X_OF) {
+            SUB_REG_LSL_IMM5(s3, s1, s2, 0);
+        }
+        AND_IMM8(s3, s3, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        SUB_REG_LSL_IMM5(s3, s1, s2, 0);
+        AND_IMM8(s3, s3, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+// emit CMP8 instruction, from cmp s1 , 0, using s3 and s4 as scratch
+void emit_cmp8_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
+{
+    IFX(X_PEND) {
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, op1));
+        MOVW(s4, 0);
+        STR_IMM9(s4, xEmu, offsetof(x86emu_t, op2));
+        STR_IMM9(s1, xEmu, offsetof(x86emu_t, res));
+        SET_DF(s3, d_cmp8);
+    } else {
+        SET_DFNONE(s4);
+    }
+    // bc = (res & (~d | s)) | (~d & s) = 0
+    IFX(X_CF | X_AF) {
+        BIC_IMM8(xFlags, xFlags, (1<<F_CF)|(1<<F_AF), 0);
+    }
+    IFX(X_OF) {
+        BFC(xFlags, F_OF, 1);
+    }
+    IFX(X_ZF) {
+        TSTS_IMM8(s1, 0xff);
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s4, s1, 7);
+        BFI(xFlags, s4, F_SF, 1);
+    }
+    // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+    IFX(X_PF) {
+        AND_IMM8(s3, s1, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_IMM8(s3, s1, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit TEST32 instruction, from test s1 , s2, using s3 and s4 as scratch
+void emit_test32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
+{
+    IFX(X_PEND) {
+        SET_DF(s3, d_tst32);
+    } else {
+        SET_DFNONE(s4);
+    }
+    IFX(X_OF) {
+        BFC(xFlags, F_OF, 1);
+    }
+    IFX(X_CF) {
+        BFC(xFlags, F_CF, 1);
+    }
+    ANDS_REG_LSL_IMM5(s3, s1, s2, 0);   // res = s1 & s2
+    IFX(X_PEND) {
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s4, s3, 31);
+        BFI(xFlags, s4, F_SF, 1);
+    }
+    // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+    IFX(X_PF) {
+        AND_IMM8(s3, s3, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_REG_LSL_IMM5(s3, s1, s2, 0);
+        AND_IMM8(s3, s3, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit TEST16 instruction, from test s1 , s2, using s3 and s4 as scratch
+void emit_test16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
+{
+    IFX(X_PEND) {
+        SET_DF(s3, d_tst16);
+    } else {
+        SET_DFNONE(s4);
+    }
+    IFX(X_OF) {
+        BFC(xFlags, F_OF, 1);
+    }
+    IFX(X_CF) {
+        BFC(xFlags, F_CF, 1);
+    }
+    ANDS_REG_LSL_IMM5(s3, s1, s2, 0);   // res = s1 & s2
+    IFX(X_PEND) {
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s4, s3, 15);
+        BFI(xFlags, s4, F_SF, 1);
+    }
+    // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+    IFX(X_PF) {
+        AND_IMM8(s3, s3, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_REG_LSL_IMM5(s3, s1, s2, 0);
+        AND_IMM8(s3, s3, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
+
+// emit TEST8 instruction, from test s1 , s2, using s3 and s4 as scratch
+void emit_test8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
+{
+    IFX(X_PEND) {
+        SET_DF(s3, d_tst8);
+    } else {
+        SET_DFNONE(s4);
+    }
+    IFX(X_OF) {
+        BFC(xFlags, F_OF, 1);
+    }
+    IFX(X_CF) {
+        BFC(xFlags, F_CF, 1);
+    }
+    ANDS_REG_LSL_IMM5(s3, s1, s2, 0);   // res = s1 & s2
+    IFX(X_PEND) {
+        STR_IMM9(s3, xEmu, offsetof(x86emu_t, res));
+    }
+    IFX(X_ZF) {
+        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
+        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
+    }
+    IFX(X_SF) {
+        MOV_REG_LSR_IMM5(s4, s3, 7);
+        BFI(xFlags, s4, F_SF, 1);
+    }
+    // PF: (((emu->x86emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
+    IFX(X_PF) {
+        AND_IMM8(s3, s3, 0xE0); // lsr 5 masking pre-applied
+        LDR_IMM9(s4, xEmu, offsetof(x86emu_t, x86emu_parity_tab));
+        LDR_REG_LSR_IMM5(s4, s4, s3, 5-2);   // x/32 and then *4 because array is integer
+        AND_REG_LSL_IMM5(s3, s1, s2, 0);
+        AND_IMM8(s3, s3, 31);
+        MVN_REG_LSR_REG(s4, s4, s3);
+        BFI(xFlags, s4, F_PF, 1);
+    }
+}
@@ -24,21 +24,477 @@

 uintptr_t dynarecF0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
 {
-    uint8_t nextop = PK(0); // don't increment addr
-    uint8_t u8;
-    uint32_t u32;
-    int32_t i32;
-    int16_t i16;
-    uint16_t u16;
-    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
+    uint8_t nextop, opcode = F8;
+    uint8_t wback, wb1, wb2, gb1, gb2;
+    uint8_t ed, gd, u8;
    int fixedaddress;
-    int locked = 0;
-    switch(nextop) {
-        // generic case
+    int32_t i32, j32;
+    MAYUSE(i32);
+    MAYUSE(j32);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    switch(opcode) {
+        case 0x00:
+            INST_NAME("LOCK ADD Eb, Gb");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGB(x2);
+            if((nextop&0xC0)==0xC0) {
+                wback = (nextop&7);    
+                wb2 = (wback>>2);      
+                wback = xEAX+(wback&3);
+                UXTB(x1, wback, wb2);   
+                emit_add8(dyn, ninst, x1, x2, x14, x3, 0);
+                BFI(wback, ed, wb2*8, 8);
+            } else {                   
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREXB(x1, wback);
+                emit_add8(dyn, ninst, x1, x2, x14, x3, (wback==x3)?1:0);
+                STREXB(x14, x1, wback);
+                CMPS_IMM8(x14, 0);
+                B_MARKLOCK(cNE);    // write failed, try again
+            }
+            break;
+        case 0x01:
+            INST_NAME("LOCK ADD Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGD;
+            if((nextop&0xC0)==0xC0) {
+                ed = xEAX+(nextop&7);
+                emit_add32(dyn, ninst, ed, gd, x3, x14);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREX(x1, wback);
+                emit_add32(dyn, ninst, x1, gd, x3, x14);
+                STREX(x3, x1, wback);
+                CMPS_IMM8(x3, 0);
+                B_MARKLOCK(cNE);
+            }
+            break;
+        case 0x08:
+            INST_NAME("LOCK OR Eb, Gb");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGB(x2);
+            if((nextop&0xC0)==0xC0) {
+                wback = (nextop&7);    
+                wb2 = (wback>>2);      
+                wback = xEAX+(wback&3);
+                UXTB(x1, wback, wb2);   
+                emit_or8(dyn, ninst, x1, x2, x14, x3, 0);
+                BFI(wback, ed, wb2*8, 8);
+            } else {                   
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREXB(x1, wback);
+                emit_or8(dyn, ninst, x1, x2, x14, x3, (wback==x3)?1:0);
+                STREXB(x14, x1, wback);
+                CMPS_IMM8(x14, 0);
+                B_MARKLOCK(cNE);    // write failed, try again
+            }
+            break;
+        case 0x09:
+            INST_NAME("LOCK OR Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGD;
+            if((nextop&0xC0)==0xC0) {
+                ed = xEAX+(nextop&7);
+                emit_or32(dyn, ninst, ed, gd, x3, x14);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREX(x1, wback);
+                emit_or32(dyn, ninst, x1, gd, x3, x14);
+                STREX(x3, x1, wback);
+                CMPS_IMM8(x3, 0);
+                B_MARKLOCK(cNE);
+            }
+            break;
+        case 0x10:
+            INST_NAME("LOCK ADC Eb, Gb");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGB(x2);
+            if((nextop&0xC0)==0xC0) {
+                wback = (nextop&7);    
+                wb2 = (wback>>2);      
+                wback = xEAX+(wback&3);
+                UXTB(x1, wback, wb2);   
+                emit_adc8(dyn, ninst, x1, x2, x14, x3, 0);
+                BFI(wback, ed, wb2*8, 8);
+            } else {                   
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREXB(x1, wback);
+                emit_adc8(dyn, ninst, x1, x2, x14, x3, (wback==x3)?1:0);
+                STREXB(x14, x1, wback);
+                CMPS_IMM8(x14, 0);
+                B_MARKLOCK(cNE);    // write failed, try again
+            }
+            break;
+        case 0x11:
+            INST_NAME("LOCK ADC Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGD;
+            if((nextop&0xC0)==0xC0) {
+                ed = xEAX+(nextop&7);
+                emit_adc32(dyn, ninst, ed, gd, x3, x14);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREX(x1, wback);
+                emit_adc32(dyn, ninst, x1, gd, x3, x14);
+                STREX(x3, x1, wback);
+                CMPS_IMM8(x3, 0);
+                B_MARKLOCK(cNE);
+            }
+            break;
+        case 0x18:
+            INST_NAME("LOCK SBB Eb, Gb");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGB(x2);
+            if((nextop&0xC0)==0xC0) {
+                wback = (nextop&7);    
+                wb2 = (wback>>2);      
+                wback = xEAX+(wback&3);
+                UXTB(x1, wback, wb2);   
+                emit_sbb8(dyn, ninst, x1, x2, x14, x3, 0);
+                BFI(wback, ed, wb2*8, 8);
+            } else {                   
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREXB(x1, wback);
+                emit_sbb8(dyn, ninst, x1, x2, x14, x3, (wback==x3)?1:0);
+                STREXB(x14, x1, wback);
+                CMPS_IMM8(x14, 0);
+                B_MARKLOCK(cNE);    // write failed, try again
+            }
+            break;
+        case 0x19:
+            INST_NAME("LOCK SBB Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGD;
+            if((nextop&0xC0)==0xC0) {
+                ed = xEAX+(nextop&7);
+                emit_sbb32(dyn, ninst, ed, gd, x3, x14);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREX(x1, wback);
+                emit_sbb32(dyn, ninst, x1, gd, x3, x14);
+                STREX(x3, x1, wback);
+                CMPS_IMM8(x3, 0);
+                B_MARKLOCK(cNE);
+            }
+            break;
+        case 0x20:
+            INST_NAME("LOCK AND Eb, Gb");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGB(x2);
+            if((nextop&0xC0)==0xC0) {
+                wback = (nextop&7);    
+                wb2 = (wback>>2);      
+                wback = xEAX+(wback&3);
+                UXTB(x1, wback, wb2);   
+                emit_and8(dyn, ninst, x1, x2, x14, x3, 0);
+                BFI(wback, ed, wb2*8, 8);
+            } else {                   
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREXB(x1, wback);
+                emit_and8(dyn, ninst, x1, x2, x14, x3, (wback==x3)?1:0);
+                STREXB(x14, x1, wback);
+                CMPS_IMM8(x14, 0);
+                B_MARKLOCK(cNE);    // write failed, try again
+            }
+            break;
+        case 0x21:
+            INST_NAME("LOCK AND Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGD;
+            if((nextop&0xC0)==0xC0) {
+                ed = xEAX+(nextop&7);
+                emit_and32(dyn, ninst, ed, gd, x3, x14);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREX(x1, wback);
+                emit_and32(dyn, ninst, x1, gd, x3, x14);
+                STREX(x3, x1, wback);
+                CMPS_IMM8(x3, 0);
+                B_MARKLOCK(cNE);
+            }
+            break;
+        case 0x28:
+            INST_NAME("LOCK SUB Eb, Gb");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGB(x2);
+            if((nextop&0xC0)==0xC0) {
+                wback = (nextop&7);    
+                wb2 = (wback>>2);      
+                wback = xEAX+(wback&3);
+                UXTB(x1, wback, wb2);   
+                emit_sub8(dyn, ninst, x1, x2, x14, x3, 0);
+                BFI(wback, ed, wb2*8, 8);
+            } else {                   
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREXB(x1, wback);
+                emit_sub8(dyn, ninst, x1, x2, x14, x3, (wback==x3)?1:0);
+                STREXB(x14, x1, wback);
+                CMPS_IMM8(x14, 0);
+                B_MARKLOCK(cNE);    // write failed, try again
+            }
+            break;
+        case 0x29:
+            INST_NAME("LOCK SUB Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGD;
+            if((nextop&0xC0)==0xC0) {
+                ed = xEAX+(nextop&7);
+                emit_sub32(dyn, ninst, ed, gd, x3, x14);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREX(x1, wback);
+                emit_sub32(dyn, ninst, x1, gd, x3, x14);
+                STREX(x3, x1, wback);
+                CMPS_IMM8(x3, 0);
+                B_MARKLOCK(cNE);
+            }
+            break;
+        case 0x38:
+            INST_NAME("LOCK XOR Eb, Gb");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGB(x2);
+            if((nextop&0xC0)==0xC0) {
+                wback = (nextop&7);    
+                wb2 = (wback>>2);      
+                wback = xEAX+(wback&3);
+                UXTB(x1, wback, wb2);   
+                emit_xor8(dyn, ninst, x1, x2, x14, x3, 0);
+                BFI(wback, ed, wb2*8, 8);
+            } else {                   
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREXB(x1, wback);
+                emit_xor8(dyn, ninst, x1, x2, x14, x3, (wback==x3)?1:0);
+                STREXB(x14, x1, wback);
+                CMPS_IMM8(x14, 0);
+                B_MARKLOCK(cNE);    // write failed, try again
+            }
+            break;
+        case 0x39:
+            INST_NAME("LOCK XOR Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET);
+            nextop = F8;
+            GETGD;
+            if((nextop&0xC0)==0xC0) {
+                ed = xEAX+(nextop&7);
+                emit_xor32(dyn, ninst, ed, gd, x3, x14);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                MARKLOCK;
+                LDREX(x1, wback);
+                emit_xor32(dyn, ninst, x1, gd, x3, x14);
+                STREX(x3, x1, wback);
+                CMPS_IMM8(x3, 0);
+                B_MARKLOCK(cNE);
+            }
+            break;
+
+        case 0x81:
+        case 0x83:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 0: //ADD
+                    if(opcode==0x81) {
+                        INST_NAME("LOCK ADD Ed, Id");
+                    } else {
+                        INST_NAME("LOCK ADD Ed, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET);
+                    if((nextop&0xC0)==0xC0) {
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        ed = xEAX+(nextop&7);
+                        emit_add32c(dyn, ninst, ed, i32, x3, x14);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        TSTS_IMM8(wback, 0x3);
+                        B_MARK(cNE);
+                        MARKLOCK;
+                        LDREX(x1, wback);
+                        emit_add32c(dyn, ninst, x1, i32, x3, x14);
+                        STREX(x3, x1, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARKLOCK(cNE);
+                        B_NEXT(c__);
+                        MARK;   // unaligned! also, not enough 
+                        LDR_IMM9(x1, wback, 0);
+                        LDREXB(x14, wback);
+                        BFI(x1, x14, 0, 8); // re-inject
+                        emit_add32c(dyn, ninst, x1, i32, x3, x14);
+                        STREXB(x3, x1, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARK(cNE);
+                        STR_IMM9(x1, wback, 0);    // put the whole value
+                    }
+                    break;
+                case 1: //OR
+                    if(opcode==0x81) {INST_NAME("LOCK OR Ed, Id");} else {INST_NAME("LOCK OR Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET);
+                    if((nextop&0xC0)==0xC0) {
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        ed = xEAX+(nextop&7);
+                        emit_or32c(dyn, ninst, ed, i32, x3, x14);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        MARKLOCK;
+                        LDREX(x1, wback);
+                        emit_or32c(dyn, ninst, x1, i32, x3, x14);
+                        STREX(x3, x1, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARKLOCK(cNE);
+                    }
+                    break;
+                case 2: //ADC
+                    if(opcode==0x81) {INST_NAME("LOCK ADC Ed, Id");} else {INST_NAME("LOCK ADC Ed, Ib");}
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET);
+                    if((nextop&0xC0)==0xC0) {
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        ed = xEAX+(nextop&7);
+                        emit_adc32c(dyn, ninst, ed, i32, x3, x14);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        MARKLOCK;
+                        LDREX(x1, wback);
+                        emit_adc32c(dyn, ninst, x1, i32, x3, x14);
+                        STREX(x3, x1, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARKLOCK(cNE);
+                    }
+                    break;
+                case 3: //SBB
+                    if(opcode==0x81) {INST_NAME("LOCK SBB Ed, Id");} else {INST_NAME("LOCK SBB Ed, Ib");}
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET);
+                    if((nextop&0xC0)==0xC0) {
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        ed = xEAX+(nextop&7);
+                        emit_sbb32c(dyn, ninst, ed, i32, x3, x14);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        MARKLOCK;
+                        LDREX(x1, wback);
+                        emit_sbb32c(dyn, ninst, x1, i32, x3, x14);
+                        STREX(x3, x1, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARKLOCK(cNE);
+                    }
+                    break;
+                case 4: //AND
+                    if(opcode==0x81) {INST_NAME("LOCK AND Ed, Id");} else {INST_NAME("LOCK AND Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET);
+                    if((nextop&0xC0)==0xC0) {
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        ed = xEAX+(nextop&7);
+                        emit_and32c(dyn, ninst, ed, i32, x3, x14);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        MARKLOCK;
+                        LDREX(x1, wback);
+                        emit_and32c(dyn, ninst, x1, i32, x3, x14);
+                        STREX(x3, x1, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARKLOCK(cNE);
+                    }
+                    break;
+                case 5: //SUB
+                    if(opcode==0x81) {INST_NAME("LOCK SUB Ed, Id");} else {INST_NAME("LOCK SUB Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET);
+                    if((nextop&0xC0)==0xC0) {
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        ed = xEAX+(nextop&7);
+                        emit_sub32c(dyn, ninst, ed, i32, x3, x14);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        TSTS_IMM8(wback, 0x3);
+                        B_MARK(cNE);
+                        MARKLOCK;
+                        LDREX(x1, wback);
+                        emit_sub32c(dyn, ninst, x1, i32, x3, x14);
+                        STREX(x3, x1, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARKLOCK(cNE);
+                        B_NEXT(c__);
+                        MARK;   // unaligned! also, not enough 
+                        LDR_IMM9(x1, wback, 0);
+                        LDREXB(x14, wback);
+                        BFI(x1, x14, 0, 8); // re-inject
+                        emit_sub32c(dyn, ninst, x1, i32, x3, x14);
+                        STREXB(x3, x1, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARK(cNE);
+                        STR_IMM9(x1, wback, 0);    // put the whole value
+                    }
+                    break;
+                case 6: //XOR
+                    if(opcode==0x81) {INST_NAME("LOCK XOR Ed, Id");} else {INST_NAME("LOCK XOR Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET);
+                    if((nextop&0xC0)==0xC0) {
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        ed = xEAX+(nextop&7);
+                        emit_xor32c(dyn, ninst, ed, i32, x3, x14);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                        if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                        MARKLOCK;
+                        LDREX(x1, wback);
+                        emit_xor32c(dyn, ninst, x1, i32, x3, x14);
+                        STREX(x3, x1, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARKLOCK(cNE);
+                    }
+                    break;
+                case 7: //CMP
+                    if(opcode==0x81) {INST_NAME("(LOCK) CMP Ed, Id");} else {INST_NAME("(LOCK) CMP Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET);
+                    GETEDH(x1);
+                    // No need to LOCK, this is readonly
+                    if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                    if(i32) {
+                        MOV32(x2, i32);
+                        emit_cmp32(dyn, ninst, ed, x2, x3, x14);
+                    } else {
+                        emit_cmp32_0(dyn, ninst, ed, x3, x14);
+                    }
+                    break;
+            }
+            break;
+
+        // generic case, no lock needed, the value is only read (note that on x86 locked read is always followed wy a locked write)
        #define GO(A)   \
-        case A+0x00:    \
-        case A+0x01:    \
        case A+0x02:    \
        case A+0x03:    \
        case A+0x04:    \
@@ -51,62 +507,390 @@ uintptr_t dynarecF0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst,
        GO(0x28);
        GO(0x30);
        #undef GO
-
-        case 0x81:
-        case 0x83:
-            MESSAGE(LOG_DUMP, "LOCK\n");
-            locked = 1;
-            LOCK;
-            addr = dynarec00(dyn, addr, ip, ninst, ok, need_epilog);
-            break;
-
        case 0x86:  // for this two, the lock is already done by the opcode, so just ignoring it
        case 0x87:
-            addr = dynarec00(dyn, addr, ip, ninst, ok, need_epilog);
+            --addr;
            break;
-
+        case 0x90:  // This is xchg reg, reg, so let's ignore the LOCK prefix...
+        case 0x91:
+        case 0x92:
+        case 0x93:
+        case 0x94:
+        case 0x95:
+        case 0x96:
+        case 0x97:
+            --addr;
+            break;
+    
        case 0x0F:
-            nextop = PK(1);
+            nextop = F8;
            switch(nextop) {
                case 0xB0:
+                    INST_NAME("LOCK CMPXCHG Eb, Gb");
+                    SETFLAGS(X_ALL, SF_SET);
+                    nextop = F8;
+                    if((nextop&0xC0)==0xC0) {
+                        wback = (nextop&7);    
+                        wb2 = (wback>>2);      
+                        wback = xEAX+(wback&3);
+                        UXTB(x2, wback, wb2);   
+                        ed = x2;
+                        wb1 = 0;
+                    } else {                   
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0);
+                        MARKLOCK;
+                        LDREXB(x2, wback);
+                        ed = x2;
+                        wb1 = 1;
+                    }
+                    UXTB(x1, xEAX, 0);
+                    CMPS_REG_LSL_IMM5(x1, ed, 0);
+                    B_MARK(cNE);
+                    // AL == Eb
+                    GETGB(x1);
+                    if(wb1) {
+                        STREXB(x14, x1, wback);
+                        CMPS_IMM8(x14, 0);
+                        B_MARKLOCK(cNE);    // write failed, try again
+                        if(!(gb1==xEAX && gb2==0)) {
+                            UXTB(x1, xEAX, 0);  // readback AL if needed
+                        }
+                    } else {
+                        BFI(wback, x1, wb2*8, 8);
+                    }
+                    // done
+                    B_MARK3(c__);
+                    MARK;
+                    // AL != Eb
+                    BFI(xEAX, ed, 0, 8);
+                    MARK3;
+                    // done, do the cmp now
+                    emit_cmp8(dyn, ninst, x1, x2, x3, x14);
+                    break;
                case 0xB1:
+                    INST_NAME("LOCK CMPXCHG Ed, Gd");
+                    SETFLAGS(X_ALL, SF_SET);
+                    nextop = F8;
+                    GETGD;
+                    if((nextop&0xC0)==0xC0) {
+                        ed = xEAX+(nextop&7);
+                        wback = 0;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                        MARKLOCK;
+                        TSTS_IMM8(wback, 3);    // can be unaligned it seems
+                        LDREX_COND(cEQ, x1, wback);
+                        LDR_IMM9_COND(cNE, x1, wback, 0);
+                        LDREXB_COND(cNE, x3, wback); // dummy read, to arm the write...
+                        ed = x1;
+                    }
+                    CMPS_REG_LSL_IMM5(xEAX, ed, 0);
+                    B_MARK(cNE);
+                    // EAX == Ed
+                    if(wback) {
+                        TSTS_IMM8(wback, 3);
+                        STREX_COND(cEQ, x14, gd, wback);
+                        STREXB_COND(cNE, x14, gd, wback);
+                        CMPS_IMM8(x14, 0);
+                        B_MARKLOCK(cNE);
+                        TSTS_IMM8(wback, 3);    // anoying, all those test
+                        STR_IMM9_COND(cNE, gd, wback, 0);
+                        emit_cmp32(dyn, ninst, xEAX, ed, x1, x14);
+                    } else {
+                        emit_cmp32(dyn, ninst, xEAX, ed, x1, x14);
+                        MOV_REG(ed, gd);
+                    }
+                    // done
+                    B_MARK3(c__);   // not next, in case its called with a LOCK prefix
+                    MARK;
+                    // EAX != Ed
+                    emit_cmp32(dyn, ninst, xEAX, ed, x3, x14);
+                    MOV_REG(xEAX, ed);
+                    MARK3
+                    break;
                case 0xB3:
+                    INST_NAME("LOCK BTR Ed, Gd");
+                    SETFLAGS(X_CF, SF_SET);
+                    nextop = F8;
+                    GETGD;
+                    if((nextop&0xC0)==0xC0) {
+                        ed = xEAX+(nextop&7);
+                        wback = 0;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0);
+                        UBFX(x1, gd, 5, 3); // r1 = (gd>>5);
+                        ADD_REG_LSL_IMM5(x3, wback, x1, 2); //(&ed)+=r1*4;
+                        wback = x3;
+                        MARKLOCK;
+                        LDREX(x1, wback);
+                        ed = x1;
+                    }
+                    AND_IMM8(x2, gd, 0x1f);
+                    MOV_REG_LSR_REG(x14, ed, x2);
+                    ANDS_IMM8(x14, x14, 1);
+                    BFI(xFlags, x14, F_CF, 1);
+                    B_MARK3(cEQ); // bit already clear, jump to end of instruction
+                    MOVW(x14, 1);
+                    XOR_REG_LSL_REG(ed, ed, x14, x2);
+                    if(wback) {
+                        STREX(x14, ed, wback);
+                        CMPS_IMM8(x14, 0);
+                        B_MARKLOCK(cNE);
+                    }
+                    MARK3;
+                    break;
+
                case 0xBA:
+                    nextop = F8;
+                    switch((nextop>>3)&7) {
+                        case 4:
+                            INST_NAME("(LOCK) BT Ed, Ib");
+                            SETFLAGS(X_CF, SF_SUBSET);
+                            gd = x2;
+                            if((nextop&0xC0)==0xC0) {
+                                ed = xEAX+(nextop&7);
+                                u8 = F8;
+                            } else {
+                                addr = geted(dyn, addr, ninst, nextop, &ed, x3, &fixedaddress, 4095-32, 0);
+                                u8 = F8;
+                                fixedaddress+=(u8>>5)*4;
+                                LDR_IMM9(x1, ed, fixedaddress);
+                                ed = x1;
+                            }
+                            u8&=0x1f;
+                            if(u8) {
+                                MOV_REG_LSR_IMM5(x1, ed, u8);
+                                ed = x1;
+                            }
+                            BFI(xFlags, ed, F_CF, 1);
+                            break;
+                        case 6:
+                            INST_NAME("LOCK BTR Ed, Ib");
+                            SETFLAGS(X_CF, SF_SUBSET);
+                            gd = x2;
+                            if((nextop&0xC0)==0xC0) {
+                                ed = xEAX+(nextop&7);
+                                u8 = F8;
+                                MOVW(gd, u8);
+                                wback = 0;
+                            } else {
+                                addr = geted(dyn, addr, ninst, nextop, &ed, x3, &fixedaddress, 0, 0);
+                                u8 = F8;
+                                MOVW(gd, u8);
+                                UBFX(x1, gd, 5, 3); // r1 = (gd>>5);
+                                ADD_REG_LSL_IMM5(x3, ed, x1, 2); //(&ed)+=r1*4;
+                                MARKLOCK;
+                                LDREX(x1, x3);
+                                ed = x1;
+                                wback = x3;
+                            }
+                            AND_IMM8(x2, gd, 0x1f);
+                            MOV_REG_LSR_REG(x14, ed, x2);
+                            ANDS_IMM8(x14, x14, 1);
+                            BFI(xFlags, x14, F_CF, 1);
+                            B_MARK3(cEQ); // bit already clear, jump to next instruction
+                            //MOVW(x14, 1); // already 0x01
+                            XOR_REG_LSL_REG(ed, ed, x14, x2);
+                            if(wback) {
+                                STREX(x14, ed, wback);
+                                CMPS_IMM8(x14, 0);
+                                B_MARKLOCK(cNE);
+                            }
+                            MARK3;
+                            break;
+                        default:
+                            DEFAULT;
+                    }
+                    break;
                case 0xBB:
+                    INST_NAME("LOCK BTC Ed, Gd");
+                    SETFLAGS(X_CF, SF_SET);
+                    nextop = F8;
+                    GETGD;
+                    if((nextop&0xC0)==0xC0) {
+                        ed = xEAX+(nextop&7);
+                        wback = 0;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0);
+                        UBFX(x1, gd, 5, 3); // r1 = (gd>>5);
+                        ADD_REG_LSL_IMM5(x3, wback, x1, 2); //(&ed)+=r1*4;
+                        MARKLOCK;
+                        LDREX(x1, x3);
+                        ed = x1;
+                        wback = x3;
+                    }
+                    AND_IMM8(x2, gd, 0x1f);
+                    MOV_REG_LSR_REG(x14, ed, x2);
+                    BFI(xFlags, x14, F_CF, 1);
+                    MOVW(x14, 1);
+                    XOR_REG_LSL_REG(ed, ed, x14, x2);
+                    if(wback) {
+                        STREX(x14, ed, wback);
+                        CMPS_IMM8(x14, 0);
+                        B_MARKLOCK(cNE);
+                    }
+                    break;
+            
                case 0xC0:
+                    INST_NAME("LOCK XADD Gb, Eb");
+                    SETFLAGS(X_ALL, SF_SET);
+                    nextop = F8;
+                    GETGB(x1);
+                    if((nextop&0xC0)==0xC0) {
+                        wback = (nextop&7); 
+                        wb2 = (wback>>2); 
+                        wback = xEAX+(wback&3); 
+                        UXTB(x2, wback, wb2); 
+                        wb1 = 0;
+                        ed = x2;
+                    } else { 
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0); 
+                        MARKLOCK;
+                        LDREXB(x2, wback); 
+                        wb1 = 1;
+                        ed = x2;
+                    }
+                    BFI(gb1, ed, gb2*8, 8); // gb <- eb
+                    emit_add8(dyn, ninst, ed, gd, x14, x3, 1);
+                    if(wb1) {
+                        STREXB(x14, ed, wback);
+                        CMPS_IMM8(x14, 0);
+                        B_MARKLOCK(cNE);
+                    } else {
+                        BFI(wback, ed, wb2*8, 8);
+                    }
+                    break;
                case 0xC1:
+                    INST_NAME("LOCK XADD Gd, Ed");
+                    SETFLAGS(X_ALL, SF_SET);
+                    nextop = F8;
+                    GETGD;
+                    if((nextop&0xC0)==0xC0) {
+                        ed = xEAX+(nextop&7);
+                        if(gd!=ed) {
+                            XOR_REG_LSL_IMM5(gd, gd, ed, 0);    // swap gd, ed
+                            XOR_REG_LSL_IMM5(ed, gd, ed, 0);
+                            XOR_REG_LSL_IMM5(gd, gd, ed, 0);
+                        }
+                        emit_add32(dyn, ninst, ed, gd, x3, x14);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                        TSTS_IMM8(wback, 3);
+                        B_MARK(cNE);    // unaligned
+                        MARKLOCK;
+                        LDREX(x1, wback);
+                        ADD_REG_LSL_IMM5(x14, x1, gd, 0);
+                        STREX(x3, x14, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARKLOCK(cNE);
+                        IFX(X_ALL|X_PEND) {
+                            MOV_REG(x2, x1);
+                            emit_add32(dyn, ninst, x2, gd, x3, x14);
+                        }
+                        MOV_REG(gd, x1);
+                        B_NEXT(c__);
+                        MARK;
+                        LDR_IMM9(x1, wback, 0);
+                        LDREXB(x14, wback);
+                        BFI(x1, x14, 0, 8);
+                        ADD_REG_LSL_IMM5(x14, x1, gd, 0);
+                        STREXB(x3, x14, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARK(cNE);
+                        STR_IMM9(x14, wback, 0);
+                        IFX(X_ALL|X_PEND) {
+                            MOV_REG(x2, x1);
+                            emit_add32(dyn, ninst, x2, gd, x3, x14);
+                        }
+                        MOV_REG(gd, x1);
+                    }
+                    break;
+
                case 0xC7:
-                    MESSAGE(LOG_DUMP, "LOCK\n");
-                    locked = 1;
-                    LOCK;
-                    addr = dynarec0F(dyn, addr+1, ip, ninst, ok, need_epilog);
+                    INST_NAME("LOCK CMPXCHG8B Gq, Eq");
+                    SETFLAGS(X_ZF, SF_SET);
+                    nextop = F8;
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, 0, 0);
+                    MARKLOCK;
+                    TSTS_IMM8(wback, 7);
+                    LDREXD_COND(cEQ, x2, wback);
+                    LDREX_COND(cNE, x2, wback);
+                    LDR_IMM9_COND(cNE, x3, wback, 4);
+                    CMPS_REG_LSL_IMM5(xEAX, x2, 0);
+                    B_MARK(cNE);    // EAX != Ed[0]
+                    CMPS_REG_LSL_IMM5(xEDX, x3, 0);
+                    B_MARK(cNE);    // EDX != Ed[1]
+                    MOV_REG(x2, xEBX);
+                    MOV_REG(x3, xECX);
+                    TSTS_IMM8(wback, 7);
+                    STREXD_COND(cEQ, x14, x2, wback);
+                    STREX_COND(cNE, x14, x2, wback);
+                    CMPS_IMM8(x14, 0);
+                    B_MARKLOCK(cNE);
+                    TSTS_IMM8(wback, 7);
+                    STR_IMM9_COND(cNE, x3, wback, 4);
+                    MOVW(x1, 1);
+                    B_MARK3(c__);
+                    MARK;
+                    MOV_REG(xEAX, x2);
+                    MOV_REG(xEDX, x3);
+                    MOVW(x1, 0);
+                    MARK3;
+                    BFI(xFlags, x1, F_ZF, 1);
                    break;

                default:
-                    addr = dynarec0F(dyn, addr+1, ip, ninst, ok, need_epilog);    // no lock, regular instruction...
+                    // dafault to NO LOCK
+                    addr-=2;
            }
            break;

        case 0xFF:
-            nextop = PK(1);
+            nextop = F8;
            switch((nextop>>3)&7)
            {
-                case 0:
-                case 1:
-                    MESSAGE(LOG_DUMP, "LOCK\n");
-                    locked = 1;
-                    LOCK;
-                    addr = dynarec00(dyn, addr, ip, ninst, ok, need_epilog);
+                case 0: // INC Ed
+                    INST_NAME("INC Ed");
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET);
+                    if((nextop&0xC0)==0xC0) {
+                        ed = xEAX+(nextop&7);
+                        emit_inc32(dyn, ninst, ed, x3, x14);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                        MARKLOCK;
+                        LDREX(x1, wback);
+                        emit_inc32(dyn, ninst, x1, x3, x14);
+                        STREX(x3, x1, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARKLOCK(cNE);
+                    }
+                    break;
+                case 1: //DEC Ed
+                    INST_NAME("DEC Ed");
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET);
+                    if((nextop&0xC0)==0xC0) {
+                        ed = xEAX+(nextop&7);
+                        emit_dec32(dyn, ninst, ed, x3, x14);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0);
+                        MARKLOCK;
+                        LDREX(x1, wback);
+                        emit_dec32(dyn, ninst, x1, x3, x14);
+                        STREX(x3, x1, wback);
+                        CMPS_IMM8(x3, 0);
+                        B_MARKLOCK(cNE);
+                    }
                    break;
                default:
-                addr = dynarec00(dyn, addr, ip, ninst, ok, need_epilog);    // no lock, regular instruction...
+                    // dafault to NO LOCK
+                    addr-=2;
            }
            break;
       
        default:
-            addr = dynarec00(dyn, addr, ip, ninst, ok, need_epilog);    // no lock, regular instruction...
+            // dafault to NO LOCK
+            --addr;
    }
-    if(locked) {UNLOCK;}

    return addr;
 }
@@ -22,43 +22,53 @@
 #include "dynarec_arm_functions.h"
 #include "dynarec_arm_helper.h"

-// Get Ex as a double, not a quad
+// Get Ex as a double, not a quad (warning, x2 and x3 may get used)
 #define GETEX(a) \
    if((nextop&0xC0)==0xC0) { \
        a = sse_get_reg(dyn, ninst, x1, nextop&7); \
    } else {    \
-        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3); \
+        parity = getedparity(dyn, ninst, addr, nextop, 3);  \
        a = fpu_get_scratch_double(dyn);            \
-        VLDR_64(a, ed, fixedaddress);               \
+        if(parity) {                                \
+            addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3); \
+            VLDR_64(a, ed, fixedaddress);           \
+        } else {                                    \
+            addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095-4, 0);\
+            LDR_IMM9(x2, ed, fixedaddress+0);       \
+            LDR_IMM9(x3, ed, fixedaddress+4);       \
+            VMOVtoV_D(a, x2, x3);                   \
+        }                                           \
    }

 uintptr_t dynarecF20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
 {
    uint8_t nextop = F8;
    uint8_t u8;
-    int32_t i32, i32_;
-    int16_t i16;
    uint32_t u32;
-    uint16_t u16;
    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
-    uint8_t eb1, eb2;
+    uint8_t wback;
    int v0, v1;
-    int q0, q1;
    int d0, d1;
-    int s0, s1;
+    int s0;
    int fixedaddress;
+    int parity;
+
+    MAYUSE(s0);
+    MAYUSE(d1);
+    MAYUSE(d0);
+
    switch(nextop) {
-        
+
        case 0x10:
            INST_NAME("MOVSD Gx, Ex");
            nextop = F8;
            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
            if((nextop&0xC0)==0xC0) {
+                v0 = sse_get_reg(dyn, ninst, x1, gd);
                d0 = sse_get_reg(dyn, ninst, x1, nextop&7);
                VMOVD(v0, d0);
            } else {
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095-4, 0);
                LDR_IMM9(x2, ed, fixedaddress+0);
                LDR_IMM9(x3, ed, fixedaddress+4);
@@ -85,18 +95,18 @@ uintptr_t dynarecF20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
            INST_NAME("MOVDDUP Gx, Ex");
            nextop = F8;
            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
            if((nextop&0xC0)==0xC0) {
                d0 = sse_get_reg(dyn, ninst, x1, nextop&7);
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
                VMOVD(v0, d0);
-                VMOVD(v0+1, d0);
            } else {
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095-4, 0);
                LDR_IMM9(x2, ed, fixedaddress+0);
                LDR_IMM9(x3, ed, fixedaddress+4);
                VMOVtoV_D(v0, x2, x3);
-                VMOVD(v0+1, v0);
            }
+            VMOVD(v0+1, v0);
            break;

        case 0x2A:
@@ -127,7 +137,7 @@ uintptr_t dynarecF20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
            break;
        case 0x2D:
            INST_NAME("CVTSD2SI Gd, Ex");
-            u8 = x87_setround(dyn, ninst, x1, x2, x12);
+            u8 = x87_setround(dyn, ninst, x1, x2, x14);
            nextop = F8;
            GETGD;
            s0 = fpu_get_scratch_single(dyn);
@@ -256,6 +266,26 @@ uintptr_t dynarecF20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
            }
            break;

+        case 0x7C:
+            INST_NAME("HADDPS Gx, Ex");
+            nextop = F8;
+            gd = (nextop&0x38)>>3;
+            v0 = sse_get_reg(dyn, ninst, x1, gd);
+            if((nextop&0xC0)==0xC0) {
+                v1 = sse_get_reg(dyn, ninst, x1, nextop&7);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0);
+                v1 = fpu_get_scratch_quad(dyn);
+                VLD1Q_64(v1, ed);
+            }
+            VPADD_F32(v0, v0, v0+1);
+            if(v0==v1) {
+                VMOVD(v0+1, v0);
+            } else {
+                VPADD_F32(v0+1, v1, v1+1);
+            }
+            break;
+
        case 0xC2:
            INST_NAME("CMPSD Gx, Ex");
            nextop = F8;
@@ -267,20 +297,39 @@ uintptr_t dynarecF20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
            MOVW(x2, 0);
            u8 = F8;
            switch(u8&7) {
-                case 0: MVN_COND_REG_LSL_IMM8(cEQ, x2, x2, 0); break;   // Equal
-                case 1: MVN_COND_REG_LSL_IMM8(cCC, x2, x2, 0); break;   // Less than
-                case 2: MVN_COND_REG_LSL_IMM8(cLS, x2, x2, 0); break;   // Less or equal
-                case 3: MVN_COND_REG_LSL_IMM8(cVS, x2, x2, 0); break;   // NaN
-                case 4: MVN_COND_REG_LSL_IMM8(cNE, x2, x2, 0); break;   // Not Equal (or unordered on ARM, not on X86...)
-                case 5: MVN_COND_REG_LSL_IMM8(cPL, x2, x2, 0); break;   // Greater or equal or unordered
-                case 6: MVN_COND_REG_LSL_IMM8(cHI, x2, x2, 0); break;   // Greater or unordered
-                case 7: MVN_COND_REG_LSL_IMM8(cVC, x2, x2, 0); break;   // not NaN
+                case 0: MVN_COND_REG_LSL_IMM5(cEQ, x2, x2, 0); break;   // Equal
+                case 1: MVN_COND_REG_LSL_IMM5(cCC, x2, x2, 0); break;   // Less than
+                case 2: MVN_COND_REG_LSL_IMM5(cLS, x2, x2, 0); break;   // Less or equal
+                case 3: MVN_COND_REG_LSL_IMM5(cVS, x2, x2, 0); break;   // NaN
+                case 4: MVN_COND_REG_LSL_IMM5(cNE, x2, x2, 0); break;   // Not Equal (or unordered on ARM, not on X86...)
+                case 5: MVN_COND_REG_LSL_IMM5(cPL, x2, x2, 0); break;   // Greater or equal or unordered
+                case 6: MVN_COND_REG_LSL_IMM5(cHI, x2, x2, 0); break;   // Greater or unordered
+                case 7: MVN_COND_REG_LSL_IMM5(cVC, x2, x2, 0); break;   // not NaN
            }
            VMOVtoV_D(v0, x2, x2);
            break;

+        case 0xF0:
+            INST_NAME("LDDQ Gx,Ex");
+            nextop = F8;
+            gd = (nextop&0x38)>>3;
+            if((nextop&0xC0)==0xC0) {
+                v1 = sse_get_reg(dyn, ninst, x1, nextop&7);
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                VMOVQ(v0, v1);
+            } else {
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095-12, 0);
+                LDR_IMM9(x2, ed, fixedaddress+0);
+                LDR_IMM9(x3, ed, fixedaddress+4);
+                VMOVtoV_D(v0, x2, x3);
+                LDR_IMM9(x2, ed, fixedaddress+8);
+                LDR_IMM9(x3, ed, fixedaddress+12);
+                VMOVtoV_D(v0+1, x2, x3);
+            }
+            break;
+
        default:
-            *ok = 0;
            DEFAULT;
    }
    return addr;
@@ -34,27 +34,43 @@
        }                                           \
        a *= 2;                                     \
    } else {    \
-        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3); \
-        a = fpu_get_scratch_single(dyn);            \
-        VLDR_32(a, ed, fixedaddress);               \
+        b = fpu_get_scratch_double(dyn);            \
+        a = b*2;                                    \
+        parity = getedparity(dyn, ninst, addr, nextop, 2);  \
+        if(parity) {                                \
+            addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 0); \
+            VLDR_32(a, ed, fixedaddress);           \
+        } else {                                    \
+            GETED;                                  \
+            VMOVtoV(a, ed);                         \
+        }                                           \
    }

+#define GETGX(a) \
+    gd = (nextop&0x38)>>3;                          \
+    a = sse_get_reg(dyn, ninst, x1, gd)
+
+
 uintptr_t dynarecF30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog)
 {
    uint8_t opcode = F8;
    uint8_t nextop, u8;
-    int32_t i32, i32_;
+    int32_t j32;
    uint32_t u32;
-    int16_t i16;
-    uint16_t u16;
    uint8_t gd, ed;
-    uint8_t wback, wb1, wb2;
-    uint8_t eb1, eb2;
+    uint8_t wback;
    int fixedaddress;
    int v0, v1;
-    int s0, s1;
+    int s0, s1, s2;
    int d0, d1;
    int q0, q1;
+    int parity;
+
+    MAYUSE(q1);
+    MAYUSE(s1);
+    MAYUSE(s2);
+    MAYUSE(j32);
+
    switch(opcode) {

        case 0x10:
@@ -117,6 +133,49 @@ uintptr_t dynarecF30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
                STR_IMM9(x2, ed, fixedaddress);
            }
            break;
+        case 0x12:
+            INST_NAME("MOVSLDUP Gx, Ex");
+            nextop = F8;
+            gd = (nextop&0x38)>>3;
+            if((nextop&0xC0)==0xC0) {
+                q1 = sse_get_reg(dyn, ninst, x1, nextop&7);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0);
+                q1 = fpu_get_scratch_quad(dyn);
+                VLD1Q_64(q1, ed);
+            }
+            q0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+            VDUP_32(q0+0, q1+0, 0);
+            VDUP_32(q0+1, q1+1, 0);
+            break;
+        
+        case 0x16:
+            INST_NAME("MOVSHDUP Gx, Ex");
+            nextop = F8;
+            gd = (nextop&0x38)>>3;
+            if((nextop&0xC0)==0xC0) {
+                q1 = sse_get_reg(dyn, ninst, x1, nextop&7);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0);
+                q1 = fpu_get_scratch_quad(dyn);
+                VLD1Q_64(q1, ed);
+            }
+            q0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+            VDUP_32(q0+0, q1+0, 1);
+            VDUP_32(q0+1, q1+1, 1);
+            break;
+
+        
+        case 0x1E:
+            INST_NAME("NOP / ENDBR32 / ENDBR64");
+            nextop = F8;
+            FAKEED;
+            break;
+        case 0x1F:
+            INST_NAME("REP NOP");
+            nextop = F8;
+            FAKEED;
+            break;

        case 0x2A:
            INST_NAME("CVTSI2SS Gx, Ed");
@@ -153,15 +212,22 @@ uintptr_t dynarecF30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
                }
                VMOV_32(s0, d0*2);
            } else {
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3);
-                VLDR_32(s0, ed, fixedaddress);
+                parity = getedparity(dyn, ninst, addr, nextop, 3);
+                if(parity) {
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3);
+                    VLDR_32(s0, ed, fixedaddress);
+                } else {
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095, 0);
+                    LDR_IMM9(x2, ed, fixedaddress);
+                    VMOVtoV(s0, x2);
+                }
            }
            VCVT_S32_F32(s0, s0);
            VMOVfrV(gd, s0);
            break;
        case 0x2D:
            INST_NAME("CVTSS2SI Gd, Ex");
-            u8 = x87_setround(dyn, ninst, x1, x2, x12);
+            u8 = x87_setround(dyn, ninst, x1, x2, x14);
            nextop = F8;
            GETGD;
            s0 = fpu_get_scratch_single(dyn);
@@ -175,8 +241,15 @@ uintptr_t dynarecF30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
                }
                VMOV_32(s0, d0*2);
            } else {
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3);
-                VLDR_32(s0, ed, fixedaddress);
+                parity = getedparity(dyn, ninst, addr, nextop, 3);
+                if(parity) {
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3);
+                    VLDR_32(s0, ed, fixedaddress);
+                } else {
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095, 0);
+                    LDR_IMM9(x2, ed, fixedaddress);
+                    VMOVtoV(s0, x2);
+                }
            }
            VCVTR_S32_F32(s0, s0);
            VMOVfrV(gd, s0);
@@ -186,104 +259,118 @@ uintptr_t dynarecF30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
        case 0x51:
            INST_NAME("SQRTSS Gx, Ex");
            nextop = F8;
-            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(s0, d0);
-            if(v0<16)
-                d1 = v0;
-            else {
-                d1 = fpu_get_scratch_double(dyn);
-                VMOV_64(d1, v0);
-            }
-            VSQRT_F32(d1*2, s0);
-            if(v0!=d1) {
-                VMOV_64(v0, d1);
+            GETGX(v0);
+            GETEX(s1, v1);
+            if(v0==v1)
+                d0 = s1/2;
+            else
+                if(v0<16)
+                    d0 = v0;
+                else {
+                    d0 = fpu_get_scratch_double(dyn);
+                    VMOV_64(d0, v0);
+                }
+            s0 = d0*2;
+            VSQRT_F32(s0, s1);
+            if(v0!=d0) {
+                VMOV_64(v0, d0);
            }
            break;
        case 0x52:
            INST_NAME("RSQRTSS Gx, Ex");
            nextop = F8;
-            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(s0, d0);
-            if(v0<16)
-                d1 = v0;
-            else {
-                d1 = fpu_get_scratch_double(dyn);
-                VMOV_64(d1, v0);
-            }
-            s1 = fpu_get_scratch_single(dyn);
+            GETGX(v0);
+            GETEX(s1, v1);
+            if(v0==v1)
+                d0 = s1/2;
+            else
+                if(v0<16)
+                    d0 = v0;
+                else {
+                    d0 = fpu_get_scratch_double(dyn);
+                    VMOV_64(d0, v0);
+                }
+            s0 = d0*2;
+            s2 = fpu_get_scratch_single(dyn);
            // so here: F32: Imm8 = abcd efgh that gives => aBbbbbbc defgh000 00000000 00000000
            // and want 1.0f = 0x3f800000
            // so 00111111 10000000 00000000 00000000
            // a = 0, b = 1, c = 1, d = 1, efgh=0
            // 0b01110000
-            VMOV_i_32(s1, 0b01110000);
-            VDIV_F32(s0, s1, s0);
-            VSQRT_F32(d1*2, s0);
-            if(v0!=d1) {
-                VMOV_64(v0, d1);
+            VMOV_i_32(s2, 0b01110000);
+            VSQRT_F32(s0, s1);
+            VDIV_F32(s0, s2, s0);
+            if(v0!=d0) {
+                VMOV_64(v0, d0);
            }
            break;
        case 0x53:
            INST_NAME("RCPSS Gx, Ex");
            nextop = F8;
-            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(s0, d0);
-            if(v0<16)
-                d1 = v0;
-            else {
-                d1 = fpu_get_scratch_double(dyn);
-                VMOV_64(d1, v0);
-            }
-            s1 = fpu_get_scratch_single(dyn);
-            VMOV_i_32(s1, 0b01110000);
-            VDIV_F32(d1*2, s1, s0);
-            if(v0!=d1) {
-                VMOV_64(v0, d1);
+            GETGX(v0);
+            GETEX(s1, v1);
+            if(v0==v1)
+                d0 = s1/2;
+            else
+                if(v0<16)
+                    d0 = v0;
+                else {
+                    d0 = fpu_get_scratch_double(dyn);
+                    VMOV_64(d0, v0);
+                }
+            s0 = d0*2;
+            s2 = fpu_get_scratch_single(dyn);
+            VMOV_i_32(s2, 0b01110000);
+            VDIV_F32(s0, s2, s1);
+            if(v0!=d0) {
+                VMOV_64(v0, d0);
            }
            break;

        case 0x58:
            INST_NAME("ADDSS Gx, Ex");
            nextop = F8;
-            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(s0, d0);
-            if(v0<16)
-                d1 = v0;
-            else {
-                d1 = fpu_get_scratch_double(dyn);
-                VMOV_64(d1, v0);
-            }
-            VADD_F32(d1*2, d1*2, s0);
-            if(v0!=d1) {
-                VMOV_64(v0, d1);
+            GETGX(v0);
+            GETEX(s1, v1);
+            if(v0==v1)
+                d0 = s1/2;
+            else
+                if(v0<16)
+                    d0 = v0;
+                else {
+                    d0 = fpu_get_scratch_double(dyn);
+                    VMOV_64(d0, v0);
+                }
+            s0 = d0*2;
+            VADD_F32(s0, s0, s1);
+            if(v0!=d0) {
+                VMOV_64(v0, d0);
            }
            break;
        case 0x59:
            INST_NAME("MULSS Gx, Ex");
            nextop = F8;
-            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(s0, d0);
-            if(v0<16)
-                d1 = v0;
-            else {
-                d1 = fpu_get_scratch_double(dyn);
-                VMOV_64(d1, v0);
-            }
-            VMUL_F32(d1*2, d1*2, s0);
-            if(v0!=d1) {
-                VMOV_64(v0, d1);
+            GETGX(v0);
+            GETEX(s1, v1);
+            if(v0==v1)
+                d0 = s1/2;
+            else
+                if(v0<16)
+                    d0 = v0;
+                else {
+                    d0 = fpu_get_scratch_double(dyn);
+                    VMOV_64(d0, v0);
+                }
+            s0 = d0*2;
+            VMUL_F32(s0, s0, s1);
+            if(v0!=d0) {
+                VMOV_64(v0, d0);
            }
            break;
        case 0x5A:
            INST_NAME("CVTSS2SD Gx, Ex");
            nextop = F8;
-            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
+            GETGX(v0);
            GETEX(s0, d0);
            VCVT_F64_F32(v0, s0);
            break;
@@ -304,75 +391,87 @@ uintptr_t dynarecF30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
        case 0x5C:
            INST_NAME("SUBSS Gx, Ex");
            nextop = F8;
-            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(s0, d0);
-            if(v0<16)
-                d1 = v0;
-            else {
-                d1 = fpu_get_scratch_double(dyn);
-                VMOV_64(d1, v0);
-            }
-            VSUB_F32(d1*2, d1*2, s0);
-            if(v0!=d1) {
-                VMOV_64(v0, d1);
+            GETGX(v0);
+            GETEX(s1, v1);
+            if(v0==v1)
+                d0 = s1/2;
+            else
+                if(v0<16)
+                    d0 = v0;
+                else {
+                    d0 = fpu_get_scratch_double(dyn);
+                    VMOV_64(d0, v0);
+                }
+            s0 = d0*2;
+            VSUB_F32(s0, s0, s1);
+            if(v0!=d0) {
+                VMOV_64(v0, d0);
            }
            break;
        case 0x5D:
            INST_NAME("MINSS Gx, Ex");
            nextop = F8;
-            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(s0, d0);
-            if(v0<16)
-                d1 = v0;
-            else {
-                d1 = fpu_get_scratch_double(dyn);
-                VMOV_64(d1, v0);
-            }
+            GETGX(v0);
+            GETEX(s1, v1);
+            if(v0==v1)
+                d0 = s1/2;
+            else
+                if(v0<16)
+                    d0 = v0;
+                else {
+                    d0 = fpu_get_scratch_double(dyn);
+                    VMOV_64(d0, v0);
+                }
+            s0 = d0*2;
            // MINSS: if any input is NaN, or Ex[0]<Gx[0], copy Ex[0] -> Gx[0]
-            VCMP_F32(d1*2, s0);
+            VCMP_F32(s0, s1);
            VMRS_APSR();
-            VMOVcond_32(cPL, d1*2, s0);
-            if(v0!=d1) {
-                VMOV_64(v0, d1);
+            VMOVcond_32(cPL, s0, s1);
+            if(v0!=d0) {
+                VMOV_64(v0, d0);
            }
            break;
        case 0x5E:
            INST_NAME("DIVSS Gx, Ex");
            nextop = F8;
-            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(s0, d0);
-            if(v0<16)
-                d1 = v0;
-            else {
-                d1 = fpu_get_scratch_double(dyn);
-                VMOV_64(d1, v0);
-            }
-            VDIV_F32(d1*2, d1*2, s0);
-            if(v0!=d1) {
-                VMOV_64(v0, d1);
+            GETGX(v0);
+            GETEX(s1, v1);
+            if(v0==v1)
+                d0 = s1/2;
+            else
+                if(v0<16)
+                    d0 = v0;
+                else {
+                    d0 = fpu_get_scratch_double(dyn);
+                    VMOV_64(d0, v0);
+                }
+            s0 = d0*2;
+            VDIV_F32(s0, s0, s1);
+            if(v0!=d0) {
+                VMOV_64(v0, d0);
            }
            break;
        case 0x5F:
            INST_NAME("MAXSS Gx, Ex");
            nextop = F8;
-            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(s0, d0);
-            if(v0<16)
-                d1 = v0;
-            else {
-                d1 = fpu_get_scratch_double(dyn);
-                VMOV_64(d1, v0);
-            }
+            GETGX(v0);
+            GETEX(s1, v1);
+            if(v0==v1)
+                d0 = s1/2;
+            else
+                if(v0<16)
+                    d0 = v0;
+                else {
+                    d0 = fpu_get_scratch_double(dyn);
+                    VMOV_64(d0, v0);
+                }
+            s0 = d0*2;
            // MAXSS: if any input is NaN, or Ex[0]>Gx[0], copy Ex[0] -> Gx[0]
-            VCMP_F32(s0, d1*2);
+            VCMP_F32(s1, s0);
            VMRS_APSR();
-            VMOVcond_32(cPL, d1*2, s0);
-            if(v0!=d1) {
-                VMOV_64(v0, d1);
+            VMOVcond_32(cPL, s0, s1);
+            if(v0!=d0) {
+                VMOV_64(v0, d0);
            }
            break;

@@ -408,7 +507,7 @@ uintptr_t dynarecF30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
                VLD1Q_64(v1, ed);
            }
            u8 = F8;
-            // only high part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits
+            // only high part need to be shuffled. VTBL only handle 8bits value, so the 16bits shuffles need to be changed in 8bits
            u32 = 0;
            for (int i=0; i<2; ++i) {
                u32 |= (((u8>>(i*2))&3)*2+0)<<(i*16+0);
@@ -450,8 +549,8 @@ uintptr_t dynarecF30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
            nextop = F8;
            gd = (nextop&0x38)>>3;
            if((nextop&0xC0)==0xC0) {
-                v1 = sse_get_reg_empty(dyn, ninst, x1, nextop&7);
                v0 = sse_get_reg(dyn, ninst, x1, gd);
+                v1 = sse_get_reg_empty(dyn, ninst, x1, nextop&7);
                VMOVQ(v1, v0);
            } else {
                v0 = sse_get_reg(dyn, ninst, x1, gd);
@@ -465,37 +564,87 @@ uintptr_t dynarecF30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
            }
            break;

+        case 0xBC:
+            INST_NAME("TZCNT Gd, Ed");
+            SETFLAGS(X_CF|X_ZF, SF_SET);
+            nextop = F8;
+            GETED;
+            GETGD;
+            TSTS_REG_LSL_IMM5(ed, ed, 0);
+            RBIT(x1, ed);   // reverse
+            CLZ(gd, x1);    // x2 gets leading 0 == TZCNT
+            MOVW_COND(cEQ, x1, 1);
+            MOVW_COND(cNE, x1, 0);
+            BFI(xFlags, x1, F_CF, 1);
+            RSB_IMM8(x1, x1, 1);
+            BFI(xFlags, x1, F_ZF, 1);
+            SET_DFNONE(x1);
+            break;
+
        case 0xC2:
            INST_NAME("CMPSS Gx, Ex");
            nextop = F8;
-            gd = (nextop&0x38)>>3;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(s0, d0);
-            if(v0<16)
-                d1 = v0;
-            else {
-                d1 = fpu_get_scratch_double(dyn);
-                VMOV_64(d1, v0);
-            }
-            VCMP_F32(d1*2, s0);
+            GETGX(v0);
+            GETEX(s1, v1);
+            if(v0==v1)
+                d0 = s1/2;
+            else
+                if(v0<16)
+                    d0 = v0;
+                else {
+                    d0 = fpu_get_scratch_double(dyn);
+                    VMOV_64(d0, v0);
+                }
+            s0 = d0*2;
+            VCMP_F32(s0, s1);
            VMRS_APSR();
            MOVW(x2, 0);
            u8 = F8;
            switch(u8&7) {
-                case 0: MVN_COND_REG_LSL_IMM8(cEQ, x2, x2, 0); break;   // Equal
-                case 1: MVN_COND_REG_LSL_IMM8(cCC, x2, x2, 0); break;   // Less than
-                case 2: MVN_COND_REG_LSL_IMM8(cLS, x2, x2, 0); break;   // Less or equal
-                case 3: MVN_COND_REG_LSL_IMM8(cVS, x2, x2, 0); break;   // NaN
-                case 4: MVN_COND_REG_LSL_IMM8(cNE, x2, x2, 0); break;   // Not Equal (or unordered on ARM, not on X86...)
-                case 5: MVN_COND_REG_LSL_IMM8(cPL, x2, x2, 0); break;   // Greater or equal or unordered
-                case 6: MVN_COND_REG_LSL_IMM8(cHI, x2, x2, 0); break;   // Greater or unordered
-                case 7: MVN_COND_REG_LSL_IMM8(cVC, x2, x2, 0); break;   // not NaN
+                case 0: MVN_COND_REG_LSL_IMM5(cEQ, x2, x2, 0); break;   // Equal
+                case 1: MVN_COND_REG_LSL_IMM5(cCC, x2, x2, 0); break;   // Less than
+                case 2: MVN_COND_REG_LSL_IMM5(cLS, x2, x2, 0); break;   // Less or equal
+                case 3: MVN_COND_REG_LSL_IMM5(cVS, x2, x2, 0); break;   // NaN
+                case 4: MVN_COND_REG_LSL_IMM5(cNE, x2, x2, 0); break;   // Not Equal (or unordered on ARM, not on X86...)
+                case 5: MVN_COND_REG_LSL_IMM5(cPL, x2, x2, 0); break;   // Greater or equal or unordered
+                case 6: MVN_COND_REG_LSL_IMM5(cHI, x2, x2, 0); break;   // Greater or unordered
+                case 7: MVN_COND_REG_LSL_IMM5(cVC, x2, x2, 0); break;   // not NaN
            }
            VMOVtoDx_32(v0, 0, x2);
            break;
+        
+        case 0xE6:
+            INST_NAME("CVTDQ2PD Gx, Ex");
+            nextop = F8;
+            if((nextop&0xC0)==0xC0) {
+                v1 = sse_get_reg(dyn, ninst, x1, nextop&7);
+                if(v1<16)
+                    v0 = v1;
+                else {
+                    v0 = fpu_get_scratch_double(dyn);
+                    VMOV_64(v0, v1);    // vfpu opcode here
+                }
+            } else {
+                v0 = fpu_get_scratch_double(dyn);
+                parity = getedparity(dyn, ninst, addr, nextop, 3);
+                if(parity) {
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 1023, 3);
+                    VLDR_64(v0, ed, fixedaddress);    // vfpu opcode here
+                } else {
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 4095-8, 0);
+                    LDR_IMM9(x2, ed, fixedaddress);
+                    LDR_IMM9(x3, ed, fixedaddress+4);
+                    VMOVtoV_D(v0, x2, x3);
+                }
+            }
+            gd = (nextop&0x38)>>3;
+            q0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+            //v0 is a low reg now
+            VCVT_F64_S32(q0+1, v0*2+1);
+            VCVT_F64_S32(q0+0, v0*2+0);
+            break;

        default:
-            *ok = 0;
            DEFAULT;
    }
    return addr;
@@ -5,6 +5,9 @@
 #include <errno.h>
 #include <string.h>
 #include <math.h>
+#include <signal.h>
+#include <sys/types.h>
+#include <unistd.h>

 #include "debug.h"
 #include "box86context.h"
@@ -22,13 +25,6 @@
 #include "dynarec_arm_private.h"
 #include "dynarec_arm_functions.h"

-void arm_popf(x86emu_t* emu, uint32_t f)
-{
-    emu->packed_eflags.x32 = (f & 0x3F7FD7) | 0x2; // mask off res2 and res3 and on res1
-    UnpackFlags(emu);
-    RESET_FLAGS(emu);
-}
-
 void arm_fstp(x86emu_t* emu, void* p)
 {
    if(ST0.ll!=STld(0).ref)
@@ -106,8 +102,10 @@ void arm_fbld(x86emu_t* emu, uint8_t* ed)

 void arm_fild64(x86emu_t* emu, int64_t* ed)
 {
-    ST0.d = *ed;
-    STll(0).ll = *ed;
+    int64_t tmp;
+    memcpy(&tmp, ed, sizeof(tmp));
+    ST0.d = tmp;
+    STll(0).ll = tmp;
    STll(0).ref = ST0.ll;
 }

@@ -118,13 +116,16 @@ void arm_fbstp(x86emu_t* emu, uint8_t* ed)

 void arm_fistp64(x86emu_t* emu, int64_t* ed)
 {
+    // used of memcpy to avoid aligments issues
    if(STll(0).ref==ST(0).ll) {
-        *ed = STll(0).ll;
+        memcpy(ed, &STll(0).ll, sizeof(int64_t));
    } else {
-        if(isgreater(ST0.d, (double)(int64_t)0x7fffffffffffffffLL) || isless(ST0.d, (double)(int64_t)0x8000000000000000LL))
-            *ed = 0x8000000000000000LL;
+        int64_t tmp;
+        if(isgreater(ST0.d, (double)(int64_t)0x7fffffffffffffffLL) || isless(ST0.d, (double)(int64_t)0x8000000000000000LL) || !isfinite(ST0.d))
+            tmp = 0x8000000000000000LL;
        else
-            *ed = (int64_t)ST0.d;
+            tmp = fpu_round(emu, ST0.d);
+        memcpy(ed, &tmp, sizeof(tmp));
    }
 }

@@ -135,97 +136,47 @@ void arm_fld(x86emu_t* emu, uint8_t* ed)
    STld(0).ref = ST0.ll;
 }

-void arm_cpuid(x86emu_t* emu, uint32_t tmp32u)
+void arm_ud(x86emu_t* emu)
 {
-    switch(tmp32u) {
-        case 0x0:
-            // emulate a P4
-            R_EAX = 0x80000004;
-            // return GenuineIntel
-            R_EBX = 0x756E6547;
-            R_EDX = 0x49656E69;
-            R_ECX = 0x6C65746E;
-            break;
-        case 0x1:
-            R_EAX = 0x00000101; // familly and all
-            R_EBX = 0;          // Brand indexe, CLFlush, Max APIC ID, Local APIC ID
-            R_EDX =   1         // fpu 
-                    | 1<<8      // cmpxchg8
-                    | 1<<11     // sep (sysenter & sysexit)
-                    | 1<<15     // cmov
-                    | 1<<19     // clflush (seems to be with SSE2)
-                    | 1<<23     // mmx
-                    //| 1<<24     // fxsr (fxsave, fxrestore)
-                    | 1<<25     // SSE
-                    | 1<<26     // SSE2
-                    ;
-            R_ECX =   1<<12     // fma
-                    | 1<<13     // cx16 (cmpxchg16)
-                    ;           // also 1<<0 is SSE3 and 1<<9 is SSSE3
-            break;
-        case 0x2:   // TLB and Cache info. Sending 1st gen P4 info...
-            R_EAX = 0x665B5001;
-            R_EBX = 0x00000000;
-            R_ECX = 0x00000000;
-            R_EDX = 0x007A7000;
-            break;
-        
-        case 0x4:   // Cache info
-            switch (R_ECX) {
-                case 0: // L1 data cache
-                    R_EAX = (1 | (1<<5) | (1<<8));   //type
-                    R_EBX = (63 | (7<<22)); // size
-                    R_ECX = 63;
-                    R_EDX = 1;
-                    break;
-                case 1: // L1 inst cache
-                    R_EAX = (2 | (1<<5) | (1<<8)); //type
-                    R_EBX = (63 | (7<<22)); // size
-                    R_ECX = 63;
-                    R_EDX = 1;
-                    break;
-                case 2: // L2 cache
-                    R_EAX = (3 | (2<<5) | (1<<8)); //type
-                    R_EBX = (63 | (15<<22));    // size
-                    R_ECX = 4095;
-                    R_EDX = 1;
-                    break;
-
-                default:
-                    R_EAX = 0x00000000;
-                    R_EBX = 0x00000000;
-                    R_ECX = 0x00000000;
-                    R_EDX = 0x00000000;
-                    break;
-            }
-            break;
-        case 0x5:   //mwait info
-            R_EAX = 0;
-            R_EBX = 0;
-            R_ECX = 1 | 2;
-            R_EDX = 0;
-            break;
-        case 0x6:   // thermal
-        case 0x9:   // direct cache access
-        case 0xA:   // Architecture performance monitor
-            R_EAX = 0;
-            R_EBX = 0;
-            R_ECX = 0;
-            R_EDX = 0;
-            break;
-        case 0x7:   // extended bits...
-            /*if(R_ECX==0)    R_EAX = 0;
-            else*/ R_EAX = R_ECX = R_EBX = R_EDX = 0;
-            break;
-
-        case 0x80000000:        // max extended
-            break;              // no extended, so return same value as beeing the max value!
-        default:
-            printf_log(LOG_INFO, "Warning, CPUID command %X unsupported (ECX=%08x)\n", tmp32u, R_ECX);
-            R_EAX = 0;
-    }   
+    kill(getpid(), SIGILL);
 }

+void arm_fsave(x86emu_t* emu, uint8_t* ed)
+{
+    fpu_savenv(emu, (char*)ed, 0);
+
+    uint8_t* p = ed;
+    p += 28;
+    for (int i=0; i<8; ++i) {
+        LD2D(p, &ST(i).d);
+        p+=10;
+    }
+}
+void arm_frstor(x86emu_t* emu, uint8_t* ed)
+{
+    fpu_loadenv(emu, (char*)ed, 0);
+
+    uint8_t* p = ed;
+    p += 28;
+    for (int i=0; i<8; ++i) {
+        D2LD(&ST(i).d, p);
+        p+=10;
+    }
+
+}
+
+void arm_fprem1(x86emu_t* emu)
+{
+    // simplified version
+    int32_t tmp32s = round(ST0.d / ST1.d);
+    ST0.d -= ST1.d*tmp32s;
+    emu->sw.f.F87_C2 = 0;
+    emu->sw.f.F87_C0 = (tmp32s&1);
+    emu->sw.f.F87_C3 = ((tmp32s>>1)&1);
+    emu->sw.f.F87_C1 = ((tmp32s>>2)&1);
+}
+
+
 // Get a FPU single scratch reg
 int fpu_get_scratch_single(dynarec_arm_t* dyn)
 {
@@ -241,14 +192,25 @@ int fpu_get_scratch_double(dynarec_arm_t* dyn)
 // Get a FPU quad scratch reg
 int fpu_get_scratch_quad(dynarec_arm_t* dyn)
 {
+    if(dyn->fpu_scratch>4) {
+        if(dyn->fpu_extra_qscratch) {
+            dynarec_log(LOG_NONE, "Warning, Extra QScratch slot taken and need another one!\n");
+        } else
+            dyn->fpu_extra_qscratch = fpu_get_reg_quad(dyn);
+        return dyn->fpu_extra_qscratch;
+    }
    int i = (dyn->fpu_scratch+3)&(~3);
    dyn->fpu_scratch = i+4;
    return i/2; // Return a Dx, not a Qx
 }
 // Reset scratch regs counter
-int fpu_reset_scratch(dynarec_arm_t* dyn)
+void fpu_reset_scratch(dynarec_arm_t* dyn)
 {
    dyn->fpu_scratch = 0;
+    if(dyn->fpu_extra_qscratch) {
+        fpu_free_reg_quad(dyn, dyn->fpu_extra_qscratch);
+        dyn->fpu_extra_qscratch = 0;
+    }
 }
 #define FPUFIRST    8
 // Get a FPU double reg
@@ -282,9 +244,103 @@ void fpu_free_reg_quad(dynarec_arm_t* dyn, int reg)
    dyn->fpuused[i] = dyn->fpuused[i+1] = 0;
 }
 // Reset fpu regs counter
-int fpu_reset_reg(dynarec_arm_t* dyn)
+void fpu_reset_reg(dynarec_arm_t* dyn)
 {
    dyn->fpu_reg = 0;
    for (int i=0; i<24; ++i)
        dyn->fpuused[i]=0;
 }
+
+#define F8      *(uint8_t*)(addr++)
+#define F32     *(uint32_t*)(addr+=4, addr-4)
+// Get if ED will have the correct parity. Not emiting anything. Parity is 2 for DWORD or 3 for QWORD
+int getedparity(dynarec_arm_t* dyn, int ninst, uintptr_t addr, uint8_t nextop, int parity)
+{
+
+    uint32_t tested = (1<<parity)-1;
+    if((nextop&0xC0)==0xC0)
+        return 0;   // direct register, no parity...
+    if(!(nextop&0xC0)) {
+        if((nextop&7)==4) {
+            uint8_t sib = F8;
+            int sib_reg = (sib>>3)&7;
+            if((sib&0x7)==5) {
+                uint32_t tmp = F32;
+                if (sib_reg!=4) {
+                    // if XXXXXX+reg<<N then check parity of XXXXX and N should be enough
+                    return ((tmp&tested)==0 && (sib>>6)>=parity)?1:0;
+                } else {
+                    // just a constant...
+                    return (tmp&tested)?0:1;
+                }
+            } else {
+                if(sib_reg==4 && parity<3)
+                    return 0;   // simple [reg]
+                // don't try [reg1 + reg2<<N], unless reg1 is ESP
+                return ((sib&0x7)==4 && (sib>>6)>=parity)?1:0;
+            }
+        } else if((nextop&7)==5) {
+            uint32_t tmp = F32;
+            return (tmp&tested)?0:1;
+        } else {
+            return 0;
+        }
+    } else {
+        return 0; //Form [reg1 + reg2<<N + XXXXXX]
+    }
+}
+
+// Do the GETED, but don't emit anything...
+uintptr_t fakeed(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop) 
+{
+    if((nextop&0xC0)==0xC0)
+        return addr;
+    if(!(nextop&0xC0)) {
+        if((nextop&7)==4) {
+            uint8_t sib = F8;
+            if((sib&0x7)==5) {
+                addr+=4;
+            }
+        } else if((nextop&7)==5) {
+            addr+=4;
+        }
+    } else {
+        if((nextop&7)==4) {
+            ++addr;
+        }
+        if(nextop&0x80) {
+            addr+=4;
+        } else {
+            ++addr;
+        }
+    }
+    return addr;
+}
+#undef F8
+#undef F32
+
+int isNativeCall(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t* calladdress, int* retn)
+{
+#define PK(a)       *(uint8_t*)(addr+a)
+#define PK32(a)     *(uint32_t*)(addr+a)
+
+    if(!addr)
+        return 0;
+    if(PK(0)==0xff && PK(1)==0x25) {  // absolute jump, maybe the GOT
+        uintptr_t a1 = (PK32(2));   // need to add a check to see if the address is from the GOT !
+        addr = *(uint32_t*)a1; 
+    }
+    if(addr<0x10000)    // too low, that is suspicious
+        return 0;
+    onebridge_t *b = (onebridge_t*)(addr);
+    if(b->CC==0xCC && b->S=='S' && b->C=='C' && b->w!=(wrapper_t)0 && b->f!=(uintptr_t)PltResolver) {
+        // found !
+        if(retn) *retn = (b->C3==0xC2)?b->N:0;
+        if(calladdress) *calladdress = addr+1;
+        return 1;
+    }
+    return 0;
+#undef PK32
+#undef PK
+}
+
@@ -3,7 +3,6 @@

 typedef struct x86emu_s x86emu_t;

-void arm_popf(x86emu_t* emu, uint32_t f);
 void arm_fstp(x86emu_t* emu, void* p);

 void arm_print_armreg(x86emu_t* emu, uintptr_t reg, uintptr_t n);
@@ -25,8 +24,11 @@ void arm_fild64(x86emu_t* emu, int64_t* ed);
 void arm_fbstp(x86emu_t* emu, uint8_t* ed);
 void arm_fistp64(x86emu_t* emu, int64_t* ed);
 void arm_fld(x86emu_t* emu, uint8_t* ed);
+void arm_fsave(x86emu_t* emu, uint8_t* ed);
+void arm_frstor(x86emu_t* emu, uint8_t* ed);
+void arm_fprem1(x86emu_t* emu);

-void arm_cpuid(x86emu_t* emu, uint32_t tmp32u);
+void arm_ud(x86emu_t* emu);

 // Get an FPU single scratch reg
 int fpu_get_scratch_single(dynarec_arm_t* dyn);
@@ -35,7 +37,7 @@ int fpu_get_scratch_double(dynarec_arm_t* dyn);
 // Get an FPU quad scratch reg
 int fpu_get_scratch_quad(dynarec_arm_t* dyn);
 // Reset scratch regs counter
-int fpu_reset_scratch(dynarec_arm_t* dyn);
+void fpu_reset_scratch(dynarec_arm_t* dyn);
 // Get an FPU double reg
 int fpu_get_reg_double(dynarec_arm_t* dyn);
 // Free a FPU double reg
@@ -45,6 +47,14 @@ int fpu_get_reg_quad(dynarec_arm_t* dyn);
 // Free a FPU quad reg
 void fpu_free_reg_quad(dynarec_arm_t* dyn, int reg);
 // Reset fpu regs counter
-int fpu_reset_reg(dynarec_arm_t* dyn);
+void fpu_reset_reg(dynarec_arm_t* dyn);
+
+// Get if ED will have the correct parity. Not emiting anything. Parity is 2 for DWORD or 3 for QWORD
+int getedparity(dynarec_arm_t* dyn, int ninst, uintptr_t addr, uint8_t nextop, int parity);
+// Do the GETED, but don't emit anything...
+uintptr_t fakeed(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop);
+
+// Is what pointed at addr a native call? And if yes, to what function?
+int isNativeCall(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t* calladdress, int* retn);

 #endif //__DYNAREC_ARM_FUNCTIONS_H__
@@ -132,6 +132,21 @@
                    wb1 = 1;                \
                    ed = i;                 \
                }
+//GETEBO will use i for ed, i is also Offset, and can use r3 for wback.
+#define GETEBO(i) if((nextop&0xC0)==0xC0) {  \
+                    wback = (nextop&7);     \
+                    wb2 = (wback>>2);       \
+                    wback = xEAX+(wback&3); \
+                    UXTB(i, wback, wb2);    \
+                    wb1 = 0;                \
+                    ed = i;                 \
+                } else {                    \
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0); \
+                    ADD_REG_LSL_IMM5(wback, wback, i, 0);   \
+                    LDRB_IMM9(i, wback, fixedaddress);      \
+                    wb1 = 1;                \
+                    ed = i;                 \
+                }
 //GETSEB sign extend EB, will use i for ed, and can use r3 for wback.
 #define GETSEB(i) if((nextop&0xC0)==0xC0) { \
                    wback = (nextop&7);     \
@@ -164,16 +179,22 @@
 #define GBBACK   BFI(gb1, gd, gb2*8, 8);

 // Get Direction with size Z and based of F_DF flag, on register r ready for LDR/STR fetching
+// F_DF is 1<<10, so 1 ROR 11*2 (so F_OF)
 #define GETDIR(r, A)    \
-    LDR_IMM9(r, xEmu, offsetof(x86emu_t, flags[F_DF]));     \
-    CMPS_IMM8(r, 1);                                        \
-    MOVW(r, A);                                             \
-    RSB_COND_IMM8(cEQ, r, r, 0)
+    TSTS_IMM8_ROR(xFlags, 1, 0x0b);         \
+    MOVW(r, A);                             \
+    RSB_COND_IMM8(cNE, r, r, 0)

-// CALL will use x12 for the call address. Return value can be put in ret (unless ret is -1)
-#define CALL(F, ret, M) call_c(dyn, ninst, F, x12, ret, M)
+// CALL will use x14 for the call address. Return value can be put in ret (unless ret is -1)
+// R0 will not be pushed/popd if ret is -2
+#define CALL(F, ret, M) call_c(dyn, ninst, F, x14, ret, M, 1)
 // CALL_ will use x3 for the call address. Return value can be put in ret (unless ret is -1)
-#define CALL_(F, ret, M) call_c(dyn, ninst, F, x3, ret, M)
+// R0 will not be pushed/popd if ret is -2
+#define CALL_(F, ret, M) call_c(dyn, ninst, F, x3, ret, M, 1)
+// CALL_S will use x3 for the call address. Return value can be put in ret (unless ret is -1)
+// R0 will not be pushed/popd if ret is -2. Flags are not save/restored
+#define CALL_S(F, ret, M) call_c(dyn, ninst, F, x3, ret, M, 0)
+
 #define MARK    if(dyn->insts) {dyn->insts[ninst].mark = (uintptr_t)dyn->arm_size;}
 #define GETMARK ((dyn->insts)?dyn->insts[ninst].mark:(dyn->arm_size+4))
 #define MARK2   if(dyn->insts) {dyn->insts[ninst].mark2 = (uintptr_t)dyn->arm_size;}
@@ -182,94 +203,136 @@
 #define GETMARK3 ((dyn->insts)?dyn->insts[ninst].mark3:(dyn->arm_size+4))
 #define MARKF   if(dyn->insts) {dyn->insts[ninst].markf = (uintptr_t)dyn->arm_size;}
 #define GETMARKF ((dyn->insts)?dyn->insts[ninst].markf:(dyn->arm_size+4))
+#define MARKSEG if(dyn->insts) {dyn->insts[ninst].markseg = (uintptr_t)dyn->arm_size;}
+#define GETMARKSEG ((dyn->insts)?dyn->insts[ninst].markseg:(dyn->arm_size+4))
+#define MARKLOCK if(dyn->insts) {dyn->insts[ninst].marklock = (uintptr_t)dyn->arm_size;}
+#define GETMARKLOCK ((dyn->insts)?dyn->insts[ninst].marklock:(dyn->arm_size+4))

-// Branch to MARK if cond (use i32)
+// Branch to MARK if cond (use j32)
 #define B_MARK(cond)    \
-    i32 = GETMARK-(dyn->arm_size+8);    \
-    Bcond(cond, i32)
-// Branch to MARK2 if cond (use i32)
+    j32 = GETMARK-(dyn->arm_size+8);    \
+    Bcond(cond, j32)
+// Branch to MARK2 if cond (use j32)
 #define B_MARK2(cond)    \
-    i32 = GETMARK2-(dyn->arm_size+8);   \
-    Bcond(cond, i32)
-// Branch to MARK3 if cond (use i32)
+    j32 = GETMARK2-(dyn->arm_size+8);   \
+    Bcond(cond, j32)
+// Branch to MARK3 if cond (use j32)
 #define B_MARK3(cond)    \
-    i32 = GETMARK3-(dyn->arm_size+8);   \
-    Bcond(cond, i32)
-// Branch to next instruction if cond (use i32)
+    j32 = GETMARK3-(dyn->arm_size+8);   \
+    Bcond(cond, j32)
+// Branch to next instruction if cond (use j32)
 #define B_NEXT(cond)     \
-    i32 = (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->arm_size+8)):0; \
-    Bcond(cond, i32)
+    j32 = (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->arm_size+8)):0; \
+    Bcond(cond, j32)
+// Branch to MARKSEG if cond (use j32)
+#define B_MARKSEG(cond)    \
+    j32 = GETMARKSEG-(dyn->arm_size+8);   \
+    Bcond(cond, j32)
+// Branch to MARKLOCK if cond (use j32)
+#define B_MARKLOCK(cond)    \
+    j32 = GETMARKLOCK-(dyn->arm_size+8);   \
+    Bcond(cond, j32)
+
+#define IFX(A)  if(dyn->insts && (dyn->insts[ninst].x86.need_flags&(A)))
+#define IFXX(A) if(dyn->insts && (dyn->insts[ninst].x86.need_flags==(A)))
+#define IFX2X(A, B) if(dyn->insts && (dyn->insts[ninst].x86.need_flags==(A) || dyn->insts[ninst].x86.need_flags==(B) || dyn->insts[ninst].x86.need_flags==((A)|(B))))
+#define IFXN(A, B)  if(dyn->insts && (dyn->insts[ninst].x86.need_flags&(A) && !(dyn->insts[ninst].x86.need_flags&(B))))

 // Generate FCOM with s1 and s2 scratch regs (the VCMP is already done)
 #define FCOM(s1, s2)    \
    VMRS_APSR();    /* 0b0100011100000000 */                                    \
    LDRH_IMM8(s2, xEmu, offsetof(x86emu_t, sw));   /*offset is 8bits right?*/   \
    MOVW(s1, 0b0100011100000000);                                               \
-    BIC_REG_LSL_IMM8(s2, s2, s1, 0);                                            \
+    BIC_REG_LSL_IMM5(s2, s2, s1, 0);                                            \
    MOVW_COND(cVS, s1, 0b0100010100000000); /* unordered */                     \
    MOVW_COND(cEQ, s1, 0b0100000000000000); /* zero */                          \
    MOVW_COND(cGT, s1, 0b0000000000000000); /* greater than */                  \
    MOVW_COND(cLO, s1, 0b0000000100000000); /* less than */                     \
-    ORR_REG_LSL_IMM8(s2, s2, s1, 0);                                            \
+    ORR_REG_LSL_IMM5(s2, s2, s1, 0);                                            \
    STRH_IMM8(s2, xEmu, offsetof(x86emu_t, sw))

 // Generate FCOMI with s1 and s2 scratch regs (the VCMP is already done)
 #define FCOMI(s1, s2)    \
    VMRS_APSR();    /* 0b111 */                             \
-    XOR_REG_LSL_IMM8(s2, s2, s2, 0);                        \
-    MOVW_COND(cVS, s1, 0b111); /* unordered */              \
-    MOVW_COND(cEQ, s1, 0b100); /* zero */                   \
-    MOVW_COND(cGT, s1, 0b000); /* greater than */           \
-    MOVW_COND(cLO, s1, 0b001); /* less than */              \
-    UBFX(s2, s1, 0, 1);                                     \
-    STR_IMM9(s2, xEmu, offsetof(x86emu_t, flags[F_CF]));    \
-    UBFX(s2, s1, 1, 1);                                     \
-    STR_IMM9(s2, xEmu, offsetof(x86emu_t, flags[F_PF]));    \
-    UBFX(s2, s1, 2, 1);                                     \
-    STR_IMM9(s2, xEmu, offsetof(x86emu_t, flags[F_ZF]));    \
-    MOVW(s2, d_none);                                       \
-    STR_IMM9(s2, xEmu, offsetof(x86emu_t, df));
+    MOVW_COND(cVS, s1, 0b1000101); /* unordered */          \
+    MOVW_COND(cEQ, s1, 0b1000000); /* zero */               \
+    MOVW_COND(cGT, s1, 0b0000000); /* greater than */       \
+    MOVW_COND(cLO, s1, 0b0000001); /* less than */          \
+    IFX(X_CF|X_PF|X_ZF|X_PEND) {                            \
+        BIC_IMM8(xFlags, xFlags, 0b1000101, 0);             \
+        ORR_REG_LSL_IMM5(xFlags, xFlags, s1, 0);            \
+    }                                                       \
+    SET_DFNONE(s1);                                         \
+    IFX(X_OF|X_PEND) {                                      \
+        BFC(xFlags, F_OF, 1);                               \
+    }                                                       \
+    IFX(X_AF|X_PEND) {                                      \
+        BFC(xFlags, F_AF, 1);                               \
+    }                                                       \
+    IFX(X_SF|X_PEND) {                                      \
+        BFC(xFlags, F_SF, 1);                               \
+    }                                                       \


-#ifndef UFLAGS
-#define UFLAGS(A)  dyn->cleanflags=A
-#endif
-#ifndef USEFLAG
-// USEFLAG will check status of defered flags the call update flags if needed. x3 will be used
-#define USEFLAG(A)   \
-    if(!dyn->cleanflags) {  \
-        if(A) {             \
+#define SET_DFNONE(S)    if(!dyn->dfnone) {MOVW(S, d_none); STR_IMM9(S, xEmu, offsetof(x86emu_t, df)); dyn->dfnone=1;}
+#define SET_DF(S, N)     if(N) {MOVW(S, N); STR_IMM9(S, xEmu, offsetof(x86emu_t, df)); dyn->dfnone=0;} else SET_DFNONE(S)
+#define SET_NODF()          dyn->dfnone = 0
+#define SET_DFOK()          dyn->dfnone = 1
+
+#ifndef READFLAGS
+#define READFLAGS(A) \
+    if(((A)!=X_PEND) && dyn->state_flags!=SF_SET) {     \
+        if(dyn->state_flags!=SF_PENDING) {              \
            LDR_IMM9(x3, xEmu, offsetof(x86emu_t, df)); \
-            TSTS_REG_LSL_IMM8(x3, x3, 0);               \
-            i32 = (GETMARKF)-(dyn->arm_size+8);         \
-            Bcond(cEQ, i32);                            \
-            CALL_(UpdateFlags, -1, 0);                  \
-            MARKF;                                      \
-            dyn->cleanflags=1;                          \
-        }                   \
+            TSTS_REG_LSL_IMM5(x3, x3, 0);               \
+            j32 = (GETMARKF)-(dyn->arm_size+8);         \
+            Bcond(cEQ, j32);                            \
+        }                                               \
+        CALL_(UpdateFlags, -1, 0);                      \
+        MARKF;                                          \
+        dyn->state_flags = SF_SET;                      \
+        SET_DFOK();                                     \
    }
 #endif
+#ifndef SETFLAGS
+#define SETFLAGS(A, B)  \
+    if(dyn->state_flags!=SF_SET && B==SF_SUBSET && (dyn->insts[ninst].x86.need_flags&(~((A)|X_PEND)))) \
+        READFLAGS(dyn->insts[ninst].x86.need_flags&(~(A)));    \
+    dyn->state_flags = (B==SF_SUBSET)?SF_SET:B
+#endif
 #ifndef JUMP
 #define JUMP(A) 
 #endif
-#define BARRIER(A) if (dyn->insts && !dyn->insts[ninst].x86.barrier) dyn->insts[ninst].x86.barrier = A
-#define UFLAG_OP1(A) if(dyn->insts && dyn->insts[ninst].x86.flags) {STR_IMM9(A, 0, offsetof(x86emu_t, op1));}
-#define UFLAG_OP2(A) if(dyn->insts && dyn->insts[ninst].x86.flags) {STR_IMM9(A, 0, offsetof(x86emu_t, op2));}
-#define UFLAG_OP12(A1, A2) if(dyn->insts && dyn->insts[ninst].x86.flags) {STR_IMM9(A1, 0, offsetof(x86emu_t, op1));STR_IMM9(A2, 0, offsetof(x86emu_t, op2));}
-#define UFLAG_RES(A) if(dyn->insts && dyn->insts[ninst].x86.flags) {STR_IMM9(A, 0, offsetof(x86emu_t, res));}
-#define UFLAG_DF(r, A) if(dyn->insts && dyn->insts[ninst].x86.flags) {MOVW(r, A); STR_IMM9(r, 0, offsetof(x86emu_t, df));}
-#define UFLAG_IF if(dyn->insts && dyn->insts[ninst].x86.flags)
+#ifndef BARRIER
+#define BARRIER(A) 
+#endif
+#ifndef BARRIER_NEXT
+#define BARRIER_NEXT(A)
+#endif
+#define UFLAG_OP1(A) if(dyn->insts && dyn->insts[ninst].x86.need_flags) {STR_IMM9(A, xEmu, offsetof(x86emu_t, op1));}
+#define UFLAG_OP2(A) if(dyn->insts && dyn->insts[ninst].x86.need_flags) {STR_IMM9(A, xEmu, offsetof(x86emu_t, op2));}
+#define UFLAG_OP12(A1, A2) if(dyn->insts && dyn->insts[ninst].x86.need_flags) {STR_IMM9(A1, xEmu, offsetof(x86emu_t, op1));STR_IMM9(A2, 0, offsetof(x86emu_t, op2));}
+#define UFLAG_RES(A) if(dyn->insts && dyn->insts[ninst].x86.need_flags) {STR_IMM9(A, xEmu, offsetof(x86emu_t, res));}
+#define UFLAG_DF(r, A) if(dyn->insts && dyn->insts[ninst].x86.need_flags) {SET_DF(r, A)}
+#define UFLAG_IF if(dyn->insts && dyn->insts[ninst].x86.need_flags)
 #ifndef DEFAULT
-#define DEFAULT      BARRIER(2)
+#define DEFAULT      *ok = -1; BARRIER(2)
+#endif
+#ifndef NEW_BARRIER_INST
+#define NEW_BARRIER_INST
 #endif
-// Emit the LOCK mutex (x1, x2 and x3 are lost)
-#define LOCK        emit_lock(dyn, addr, ninst)
-// Emit the UNLOCK mutex (x1, x2 and x3 are lost)
-#define UNLOCK      emit_unlock(dyn, addr, ninst)

+#if STEP < 2
+#define PASS2IF(A, B) if(A)
+#elif STEP == 2
+#define PASS2IF(A, B) if(A) dyn->insts[ninst].pass2choice = B; if(dyn->insts[ninst].pass2choice == B)
+#else
+#define PASS2IF(A, B) if(dyn->insts[ninst].pass2choice == B)
+#endif

 void arm_epilog();
 void* arm_linker(x86emu_t* emu, void** table, uintptr_t addr);
+void* arm_next(x86emu_t* emu, uintptr_t addr);

 #ifndef STEPNAME
 #define STEPNAME3(N,M) N##M
@@ -281,6 +344,7 @@ void* arm_linker(x86emu_t* emu, void** table, uintptr_t addr);

 #define dynarec00       STEPNAME(dynarec00)
 #define dynarec0F       STEPNAME(dynarec0F)
+#define dynarecFS       STEPNAME(dynarecFS)
 #define dynarecGS       STEPNAME(dynarecGS)
 #define dynarec66       STEPNAME(dynarec66)
 #define dynarec67       STEPNAME(dynarec67)
@@ -298,25 +362,83 @@ void* arm_linker(x86emu_t* emu, void** table, uintptr_t addr);
 #define dynarecF30F     STEPNAME(dynarecF30F)

 #define geted           STEPNAME(geted_)
-#define fakeed          STEPNAME(fakeed_)
+#define geted16         STEPNAME(geted16_)
 #define jump_to_epilog  STEPNAME(jump_to_epilog_)
 #define jump_to_linker  STEPNAME(jump_to_linker_)
+#define jump_to_next    STEPNAME(jump_to_next_)
 #define ret_to_epilog   STEPNAME(ret_to_epilog_)
 #define retn_to_epilog  STEPNAME(retn_to_epilog_)
+#define iret_to_epilog  STEPNAME(iret_to_epilog_)
 #define call_c          STEPNAME(call_c_)
+#define grab_fsdata     STEPNAME(grab_fsdata_)
 #define grab_tlsdata    STEPNAME(grab_tlsdata_)
-#define isNativeCall    STEPNAME(isNativeCall_)
-#define emit_lock       STEPNAME(emit_lock)
-#define emit_unlock     STEPNAME(emit_unlock)
 #define emit_cmp8       STEPNAME(emit_cmp8)
 #define emit_cmp16      STEPNAME(emit_cmp16)
 #define emit_cmp32      STEPNAME(emit_cmp32)
 #define emit_cmp8_0     STEPNAME(emit_cmp8_0)
 #define emit_cmp16_0    STEPNAME(emit_cmp16_0)
 #define emit_cmp32_0    STEPNAME(emit_cmp32_0)
-#define emit_test8     STEPNAME(emit_test8)
+#define emit_test8      STEPNAME(emit_test8)
 #define emit_test16     STEPNAME(emit_test16)
 #define emit_test32     STEPNAME(emit_test32)
+#define emit_add32      STEPNAME(emit_add32)
+#define emit_add32c     STEPNAME(emit_add32c)
+#define emit_add8       STEPNAME(emit_add8)
+#define emit_add8c      STEPNAME(emit_add8c)
+#define emit_sub32      STEPNAME(emit_sub32)
+#define emit_sub32c     STEPNAME(emit_sub32c)
+#define emit_sub8       STEPNAME(emit_sub8)
+#define emit_sub8c      STEPNAME(emit_sub8c)
+#define emit_or32       STEPNAME(emit_or32)
+#define emit_or32c      STEPNAME(emit_or32c)
+#define emit_xor32      STEPNAME(emit_xor32)
+#define emit_xor32c     STEPNAME(emit_xor32c)
+#define emit_and32      STEPNAME(emit_and32)
+#define emit_and32c     STEPNAME(emit_and32c)
+#define emit_or8        STEPNAME(emit_or8)
+#define emit_or8c       STEPNAME(emit_or8c)
+#define emit_xor8       STEPNAME(emit_xor8)
+#define emit_xor8c      STEPNAME(emit_xor8c)
+#define emit_and8       STEPNAME(emit_and8)
+#define emit_and8c      STEPNAME(emit_and8c)
+#define emit_add16      STEPNAME(emit_add16)
+#define emit_add16c     STEPNAME(emit_add16c)
+#define emit_sub16      STEPNAME(emit_sub16)
+#define emit_sub16c     STEPNAME(emit_sub16c)
+#define emit_or16       STEPNAME(emit_or16)
+#define emit_or16c      STEPNAME(emit_or16c)
+#define emit_xor16      STEPNAME(emit_xor16)
+#define emit_xor16c     STEPNAME(emit_xor16c)
+#define emit_and16      STEPNAME(emit_and16)
+#define emit_and16c     STEPNAME(emit_and16c)
+#define emit_inc32      STEPNAME(emit_inc32)
+#define emit_inc16      STEPNAME(emit_inc16)
+#define emit_inc8       STEPNAME(emit_inc8)
+#define emit_dec32      STEPNAME(emit_dec32)
+#define emit_dec16      STEPNAME(emit_dec16)
+#define emit_dec8       STEPNAME(emit_dec8)
+#define emit_adc32      STEPNAME(emit_adc32)
+#define emit_adc32c     STEPNAME(emit_adc32c)
+#define emit_adc8       STEPNAME(emit_adc8)
+#define emit_adc8c      STEPNAME(emit_adc8c)
+#define emit_adc16      STEPNAME(emit_adc16)
+#define emit_adc16c     STEPNAME(emit_adc16c)
+#define emit_sbb32      STEPNAME(emit_sbb32)
+#define emit_sbb32c     STEPNAME(emit_sbb32c)
+#define emit_sbb8       STEPNAME(emit_sbb8)
+#define emit_sbb8c      STEPNAME(emit_sbb8c)
+#define emit_sbb16      STEPNAME(emit_sbb16)
+#define emit_sbb16c     STEPNAME(emit_sbb16c)
+#define emit_neg32      STEPNAME(emit_neg32)
+#define emit_neg16      STEPNAME(emit_neg16)
+#define emit_neg8       STEPNAME(emit_neg8)
+#define emit_shl32c     STEPNAME(emit_shl32c)
+#define emit_shr32c     STEPNAME(emit_shr32c)
+#define emit_sar32c     STEPNAME(emit_sar32c)
+#define emit_rol32c     STEPNAME(emit_rol32c)
+#define emit_ror32c     STEPNAME(emit_ror32c)
+#define emit_shrd32c    STEPNAME(emit_shrd32c)
+#define emit_shld32c    STEPNAME(emit_shld32c)

 #define x87_do_push     STEPNAME(x87_do_push)
 #define x87_do_push_empty STEPNAME(x87_do_push_empty)
@@ -341,6 +463,9 @@ void* arm_linker(x86emu_t* emu, void** table, uintptr_t addr);
 #ifdef HAVE_TRACE
 #define fpu_reflectcache STEPNAME(fpu_reflectcache)
 #endif
+#define cstack_push     STEPNAME(cstack_push)
+#define cstack_pop      STEPNAME(cstack_pop)
+

 // get the single reg that from the double "reg" (so Dx[idx])
 #define fpu_get_single_reg      STEPNAME(fpu_get_single_reg)
@@ -350,17 +475,20 @@ void* arm_linker(x86emu_t* emu, void** table, uintptr_t addr);
 /* setup r2 to address pointed by */
 uintptr_t geted(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop, uint8_t* ed, uint8_t hint, int* fixedaddress, uint32_t absmax, uint32_t mask);

-// Do the GETED, but don't emit anything...
-uintptr_t fakeed(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop);
+/* setup r2 to address pointed by */
+uintptr_t geted16(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop, uint8_t* ed, uint8_t hint, int* fixedaddress, uint32_t absmax, uint32_t mask);
+

 // generic x86 helper
 void jump_to_epilog(dynarec_arm_t* dyn, uintptr_t ip, int reg, int ninst);
 void jump_to_linker(dynarec_arm_t* dyn, uintptr_t ip, int reg, int ninst);
+void jump_to_next(dynarec_arm_t* dyn, uintptr_t ip, int reg, int ninst);
 void ret_to_epilog(dynarec_arm_t* dyn, int ninst);
 void retn_to_epilog(dynarec_arm_t* dyn, int ninst, int n);
-void call_c(dynarec_arm_t* dyn, int ninst, void* fnc, int reg, int ret, uint32_t mask);
+void iret_to_epilog(dynarec_arm_t* dyn, int ninst);
+void call_c(dynarec_arm_t* dyn, int ninst, void* fnc, int reg, int ret, uint32_t mask, int saveflags);
+void grab_fsdata(dynarec_arm_t* dyn, uintptr_t addr, int ninst, int reg);
 void grab_tlsdata(dynarec_arm_t* dyn, uintptr_t addr, int ninst, int reg);
-int isNativeCall(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t* calladdress, int* retn);
 void emit_lock(dynarec_arm_t* dyn, uintptr_t addr, int ninst);
 void emit_unlock(dynarec_arm_t* dyn, uintptr_t addr, int ninst);
 void emit_cmp8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
@@ -372,6 +500,64 @@ void emit_cmp32_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
 void emit_test8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
 void emit_test16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
 void emit_test32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
+void emit_add32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
+void emit_add32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_add8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_add8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_sub32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
+void emit_sub32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_sub8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_sub8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_or32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
+void emit_or32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_xor32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
+void emit_xor32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_and32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
+void emit_and32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_or8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_xor8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_and8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_add16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_sub16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_or16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_or16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_xor16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_xor16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_and16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_inc32(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
+void emit_inc16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
+void emit_inc8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
+void emit_dec32(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
+void emit_dec16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
+void emit_dec8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
+void emit_adc32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
+void emit_adc32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_adc8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_adc8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_adc16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_sbb32(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4);
+void emit_sbb32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_sbb8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_sbb8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_sbb16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int save_s4);
+void emit_sbb16c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_neg32(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
+void emit_neg16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
+void emit_neg8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
+void emit_shl32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_shr32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_sar32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_rol32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_ror32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4);
+void emit_shrd32c(dynarec_arm_t* dyn, int ninst, int s1, int s2, int32_t c, int s3, int s4);
+void emit_shld32c(dynarec_arm_t* dyn, int ninst, int s1, int s2, int32_t c, int s3, int s4);

 // x87 helper
 // cache of the local stack counter, to avoid upadte at every call
@@ -425,9 +611,9 @@ int fpu_get_single_reg(dynarec_arm_t* dyn, int ninst, int reg, int idx);
 // put back (if needed) the single reg in place
 void fpu_putback_single_reg(dynarec_arm_t* dyn, int ninst, int reg, int idx, int s);

-
 uintptr_t dynarec00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog);
 uintptr_t dynarec0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog);
+uintptr_t dynarecFS(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog);
 uintptr_t dynarecGS(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog);
 uintptr_t dynarec66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog);
 uintptr_t dynarec67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog);
@@ -444,4 +630,27 @@ uintptr_t dynarec660F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nins
 uintptr_t dynarecF20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog);
 uintptr_t dynarecF30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, int* ok, int* need_epilog);

+// PUSH a x86/native couple of address in cstack, using s1, s2, s2+1
+void cstack_push(dynarec_arm_t* dyn, int ninst, uintptr_t x86ip, uintptr_t armip, int s1, int s2);
+// POP a x86/native couple of address from cstack, and generate the jump is x86 address is s0, use s1, s2 and s2+1 as scratch
+void cstack_pop(dynarec_arm_t* dyn, int ninst, int s0, int s1, int s2);
+
+#if STEP < 2
+#define PASS2(A)
+#else
+#define PASS2(A)   A
+#endif
+
+#if STEP < 3
+#define PASS3(A)
+#else
+#define PASS3(A)   A
+#endif
+
+#if STEP < 3
+#define MAYUSE(A)   (void)A
+#else
+#define MAYUSE(A)   
+#endif
+
 #endif //__DYNAREC_ARM_HELPER_H__
@@ -24,45 +24,38 @@
 #error No STEP defined
 #endif

-#include "dynarec_arm_helper.h"
-
 void arm_pass(dynarec_arm_t* dyn, uintptr_t addr)
 {
-    uint8_t nextop, opcode;
    int ok = 1;
    int ninst = 0;
    uintptr_t ip = addr;
-    uintptr_t natcall;
-    int retn;
-    uint8_t gd, ed;
-    int8_t i8;
-    int32_t i32, tmp;
-    uint8_t u8;
-    uint8_t gb1, gb2, eb1, eb2;
-    uint32_t u32;
    int need_epilog = 1;
-    uint8_t wback, wb1, wb2;
-    int fixedaddress;
    dyn->tablei = 0;
+    dyn->sons_size = 0;
    // Clean up (because there are multiple passes)
-    dyn->cleanflags = 0;
+    dyn->state_flags = 0;
+    dyn->dfnone = 0;
    fpu_reset(dyn, ninst);
    // ok, go now
    INIT;
    while(ok) {
+        if(dyn->insts && (ninst>dyn->size)) {dynarec_log(LOG_NONE, "Warning, too many inst treated (%d / %d)\n",ninst, dyn->size);}
        ip = addr;
+        if(dyn->insts && (dyn->insts[ninst].x86.barrier==1)) {
+            NEW_BARRIER_INST;
+        }
        NEW_INST;
        fpu_reset_scratch(dyn);
 #ifdef HAVE_TRACE
-        if(dyn->emu->dec && box86_dynarec_trace) {
-        if((dyn->emu->trace_end == 0) 
-            || ((ip >= dyn->emu->trace_start) && (ip <= dyn->emu->trace_end)))  {
+        if(my_context->dec && box86_dynarec_trace) {
+        if((trace_end == 0) 
+            || ((ip >= trace_start) && (ip < trace_end)))  {
                MESSAGE(LOG_DUMP, "TRACE ----\n");
                fpu_reflectcache(dyn, ninst, x1, x2, x3);
-                MOV32(1, ip);
-                STM(0, (1<<4)|(1<<5)|(1<<6)|(1<<7)|(1<<8)|(1<<9)|(1<<10)|(1<<11));
-                STR_IMM9(1, 0, offsetof(x86emu_t, ip));
-                MOV32(2, 1);
+                MOV32(x1, ip);
+                STM(xEmu, (1<<xEAX)|(1<<xEBX)|(1<<xECX)|(1<<xEDX)|(1<<xESI)|(1<<xEDI)|(1<<xESP)|(1<<xEBP));
+                STR_IMM9(x1, xEmu, offsetof(x86emu_t, ip));
+                MOVW(x2, 1);
                CALL(PrintTrace, -1, 0);
                MESSAGE(LOG_DUMP, "----------\n");
            }
@@ -75,9 +68,27 @@ void arm_pass(dynarec_arm_t* dyn, uintptr_t addr)

        if(dyn->insts && dyn->insts[ninst+1].x86.barrier) {
            fpu_purgecache(dyn, ninst, x1, x2, x3);
-            if(dyn->insts[ninst+1].x86.barrier!=2)
-                dyn->cleanflags = 0;
+            if(dyn->insts[ninst+1].x86.barrier!=2) {
+                dyn->state_flags = 0;
+                dyn->dfnone = 0;
+            }
        }
+        if(!ok && !need_epilog && dyn->insts && (addr < (dyn->start+dyn->isize))) {
+            ok = 1;
+        }
+        if(!ok && !need_epilog && !dyn->insts) {   // check if need to continue
+            uintptr_t next = get_closest_next(dyn, addr);
+            if(next && (
+                  (((next-addr)<15) && is_nops(dyn, addr, next-addr)) 
+                ||(((next-addr)<30) && is_instructions(dyn, addr, next-addr)) ))
+            {
+                dynarec_log(LOG_DEBUG, "Extend block %p, %p -> %p (ninst=%d)\n", dyn, (void*)addr, (void*)next, ninst);
+                ok = 1;
+            } else if(next && (next-addr)<30) {
+                dynarec_log(LOG_DEBUG, "Cannot extend block %p -> %p (%02X %02X %02X %02X %02X %02X %02X %02x)\n", (void*)addr, (void*)next, PK(0), PK(1), PK(2), PK(3), PK(4), PK(5), PK(6), PK(7));
+            }
+        }
+        if(ok<0)  {ok = 0; need_epilog=1;}
        ++ninst;
    }
    if(need_epilog) {
@@ -85,4 +96,5 @@ void arm_pass(dynarec_arm_t* dyn, uintptr_t addr)
        jump_to_epilog(dyn, ip, 0, ninst);  // no linker here, it's an unknow instruction
    }
    FINI;
+    MESSAGE(LOG_DUMP, "---- END OF BLOCK ---- (%d, %d sons)\n", dyn->size, dyn->sons_size);
 }
@@ -2,15 +2,24 @@
 #define INIT    uintptr_t sav_addr=addr
 #define FINI    dyn->isize = addr-sav_addr
 #define MESSAGE(A, ...)  
+#define SETFLAGS(A, B)  
+#define READFLAGS(A)    
 #define EMIT(A)     
-#define UFLAGS(A)          {}
-#define USEFLAGS(A)        {}
+#define JUMP(A)         add_next(dyn, (uintptr_t)A)
 #define NEW_INST        ++dyn->size
 #define INST_EPILOG         
 #define INST_NAME(name) 
-#define DEFAULT         \
-        --dyn->size;    \
-        dynarec_log(LOG_INFO, "%p: Dynarec stopped because of Opcode %02X %02X %02X %02X %02X %02X %02X\n", \
-        ip, PKip(0),                   \
-        PKip(1), PKip(2), PKip(3),     \
-        PKip(4), PKip(5), PKip(6))
+#define DEFAULT                         \
+        --dyn->size;                    \
+        *ok = -1;                       \
+        if(box86_dynarec_log>=LOG_INFO) {\
+        dynarec_log(LOG_NONE, "%p: Dynarec stopped because of Opcode %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X", \
+        (void*)ip, PKip(0),             \
+        PKip(1), PKip(2), PKip(3),      \
+        PKip(4), PKip(5), PKip(6),      \
+        PKip(7), PKip(8), PKip(9),      \
+        PKip(10),PKip(11),PKip(12),     \
+        PKip(13),PKip(14));             \
+        printFunctionAddr(ip, " => ");  \
+        dynarec_log(LOG_NONE, "\n");    \
+        }
@@ -1,15 +1,17 @@
 #define INIT    
 #define FINI     \
    dyn->insts[ninst].x86.addr = addr; \
-    dyn->insts[ninst].x86.flags = X86_FLAGS_USE; \
    if(ninst) dyn->insts[ninst-1].x86.size = dyn->insts[ninst].x86.addr - dyn->insts[ninst-1].x86.addr;
 #define MESSAGE(A, ...)  
 #define EMIT(A)     
-#define UFLAGS(A)   dyn->insts[ninst+(A?1:0)].x86.flags = X86_FLAGS_CHANGE
-#define USEFLAG(A)  dyn->insts[ninst].x86.flags = X86_FLAGS_USE
-#define JUMP(A)     dyn->insts[ninst].x86.jmp = A
+#define READFLAGS(A)    dyn->insts[ninst].x86.use_flags = A
+#define SETFLAGS(A,B)   {dyn->insts[ninst].x86.set_flags = A; dyn->insts[ninst].x86.state_flags = B;}
+#define JUMP(A)         dyn->insts[ninst].x86.jmp = A
+#define BARRIER(A)      dyn->insts[ninst].x86.barrier = A
+#define BARRIER_NEXT(A) if(ninst<dyn->size) dyn->insts[ninst+1].x86.barrier = A
+
 #define NEW_INST \
    dyn->insts[ninst].x86.addr = ip; \
    if(ninst) dyn->insts[ninst-1].x86.size = dyn->insts[ninst].x86.addr - dyn->insts[ninst-1].x86.addr;
 #define INST_EPILOG 
-#define INST_NAME(name) 
+#define INST_NAME(name)  
@@ -6,3 +6,4 @@
 #define NEW_INST    if(ninst) {dyn->insts[ninst].address = (dyn->insts[ninst-1].address+dyn->insts[ninst-1].size);}
 #define INST_EPILOG dyn->insts[ninst].epilog = dyn->arm_size; 
 #define INST_NAME(name) 
+#define NEW_BARRIER_INST    if(ninst) ++dyn->sons_size
@@ -1,12 +1,34 @@
 #define INIT    
 #define FINI
 #define EMIT(A)     \
-    if(box86_dynarec_log>=LOG_DUMP) {dynarec_log(LOG_NONE, "\t%08x\t%s\n", (A), arm_print(A));} \
-    *(uint32_t*)(dyn->block) = A;   \
-    dyn->block += 4; dyn->arm_size += 4
+    if(box86_dynarec_dump) {dynarec_log(LOG_NONE, "\t%08x\t%s\n", (A), arm_print(A));} \
+    *(uint32_t*)(dyn->block) = A;       \
+    dyn->block += 4; dyn->arm_size += 4;\
+    dyn->insts[ninst].size2 += 4

-#define MESSAGE(A, ...)  dynarec_log(A, __VA_ARGS__);
+#define MESSAGE(A, ...)  if(box86_dynarec_dump) dynarec_log(LOG_NONE, __VA_ARGS__)
 #define NEW_INST        
 #define INST_EPILOG     
-#define INST_NAME(name) if(box86_dynarec_log>=LOG_DUMP) printf_x86_instruction(dyn->emu->dec, &dyn->insts[ninst].x86, name)
+#define INST_NAME(name) \
+    if(box86_dynarec_dump) {\
+        printf_x86_instruction(my_context->dec, &dyn->insts[ninst].x86, name); \
+        dynarec_log(LOG_NONE, "%s%p: %d emited opcodes, state=%d/%d, set=%X, use=%X, need=%X%s\n", \
+            (box86_dynarec_dump>1)?"\e[32m":"", \
+            (void*)(dyn->arm_start+dyn->insts[ninst].address),  \
+            dyn->insts[ninst].size/4,           \
+            dyn->insts[ninst].x86.state_flags,  \
+            dyn->state_flags,                   \
+            dyn->insts[ninst].x86.set_flags,    \
+            dyn->insts[ninst].x86.use_flags,    \
+            dyn->insts[ninst].x86.need_flags,   \
+            (box86_dynarec_dump>1)?"\e[m":"");  \
+    }
+
+#define NEW_BARRIER_INST                            \
+    if(ninst) {                                     \
+    dyn->sons_x86[dyn->sons_size] = (uintptr_t)ip;  \
+    dyn->sons_arm[dyn->sons_size] = dyn->block;     \
+    MESSAGE(LOG_DUMP, "----> potential Son here\n");\
+    ++dyn->sons_size;                               \
+    }

@@ -10,8 +10,14 @@ typedef struct instruction_arm_s {
    uintptr_t           address;    // (start) address of the arm emited instruction
    uintptr_t           epilog;     // epilog of current instruction (can be start of next, of barrier stuff)
    int                 size;       // size of the arm emited instruction
+    int                 size2;      // size of the arm emited instrucion after pass2
    uintptr_t           mark, mark2, mark3;
    uintptr_t           markf;
+    uintptr_t           markseg;
+    uintptr_t           marklock;
+    int                 pass2choice;// value for choices that are fixed on pass2 for pass3
+    uintptr_t           natcall;
+    int                 retn;
 } instruction_arm_t;

 typedef struct dynarec_arm_s {
@@ -21,12 +27,12 @@ typedef struct dynarec_arm_s {
    uintptr_t           start;      // start of the block
    uint32_t            isize;      // size in byte of x86 instructions included
    void*               block;      // memory pointer where next instruction is emited
+    uintptr_t           arm_start;  // start of the arm code
    int                 arm_size;   // size of emitted arm code
-    x86emu_t*           emu;
    uintptr_t*          table;      // jump table
    int                 tablesz;    // size of the jump table
    int                 tablei;     // index
-    int                 cleanflags; // flags are clean (CMP or TST have been just executed)
+    int                 state_flags;// actual state for on-demand flags
    int                 x87cache[8];// cache status for the 8 x87 register behind the fpu stack
    int                 x87reg[8];  // reg used for x87cache entry
    int                 mmxcache[8];// cache status for the 8 MMX registers
@@ -34,8 +40,21 @@ typedef struct dynarec_arm_s {
    int                 fpuused[24];// all 8..31 double reg from fpu, used by x87, sse and mmx
    int                 x87stack;   // cache stack counter
    int                 fpu_scratch;// scratch counter
+    int                 fpu_extra_qscratch; // some opcode need an extra quad scratch register
    int                 fpu_reg;    // x87/sse/mmx reg counter
+    int                 nolinker;   // disable use of (smart) linker in the block
+    int                 dfnone;     // if defered flags is already set to df_none
+    uintptr_t*          next;       // variable array of "next" jump address
+    int                 next_sz;
+    int                 next_cap;
+    uintptr_t*          sons_x86;   // the x86 address of potential dynablock sons
+    void**              sons_arm;   // the arm address of potential dynablock sons
+    int                 sons_size;  // number of potential dynablock sons
 } dynarec_arm_t;

+void add_next(dynarec_arm_t *dyn, uintptr_t addr);
+uintptr_t get_closest_next(dynarec_arm_t *dyn, uintptr_t addr);
+int is_nops(dynarec_arm_t *dyn, uintptr_t addr, int n);
+int is_instructions(dynarec_arm_t *dyn, uintptr_t addr, int n);

 #endif //__DYNAREC_ARM_PRIVATE_H_
@@ -1,19 +1,37 @@
 #ifndef __DYNAREC_PRIVATE_H_
 #define __DYNAREC_PRIVATE_H_

-#define X86_FLAGS_NONE      0
-#define X86_FLAGS_CHANGE    1
-#define X86_FLAGS_USE       2
+// all flags for the use_flags field
+#define X_CF    (1<<0)
+#define X_PF    (1<<1)
+#define X_AF    (1<<2)
+#define X_ZF    (1<<3)
+#define X_SF    (1<<4)
+#define X_OF    (1<<5)
+#define X_ALL   ((1<<6)-1)
+#define X_PEND  (0x1000)
+
+// all state flags
+#define SF_UNKNOWN  0
+#define SF_SET      1
+#define SF_PENDING  2
+#define SF_MAYSET   3
+#define SF_SUBSET   4

 typedef struct instruction_x86_s {
    uintptr_t   addr;   //address of the instruction
    int32_t     size;   // size of the instruction
-    int         flags;  // flags for this instruction (see X86_FLAGS_XXXX)
    int         barrier; // next instruction is a jump point, so no optim allowed
    uintptr_t   jmp;    // offset to jump to, even if conditionnal (0 if not), no relative offset here
    int         jmp_insts;  // instuction to jump to (-1 if out of the block)
+    uint32_t    use_flags;  // 0 or combination of X_?F
+    uint32_t    set_flags;  // 0 or combination of X_?F
+    uint32_t    need_flags; // calculated
+    int         state_flags; // One of SF_XXX state
 } instruction_x86_t;

 void printf_x86_instruction(zydis_dec_t* dec, instruction_x86_t* inst, const char* name);
+void tableupdate(void* jumpto, uintptr_t ref, void** table);
+void resettable(void** table);

-#endif //__DYNAREC_PRIVATE_H_
+#endif //__DYNAREC_PRIVATE_H_
@@ -0,0 +1,475 @@
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 op 0 N Q M 0 Vm VH\(op ? "SUB" : "ADD")\<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 0 0 N Q M 1 Vm VQADD<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 0 1 N Q M 0 Vm VRHADD<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 0 0 Vn Vd 0 0 0 1 N Q M 1 Vm VAND<c> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 0 1 Vn Vd 0 0 0 1 N Q M 1 Vm VBIC<c> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 1 0 Vn Vd 0 0 0 1 N Q M 1 Vm @ m=n const char* op op,"MOV","ORR"@ m=n char lastop[6] !@ %@ lastop[0] = '\0'@ sprintf(lastop, ", %s", vecname[(q << 5) + 0x20 + n])@ @ V\op\<c> <Qd>, <Qm>\lastop\
+NEON 1 1 1 1 0 0 1 0 0 D 1 1 Vn Vd 0 0 0 1 N Q M 1 Vm VORN<c> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D @<2> Vn Vd 0 0 0 1 N Q M 1 Vm @ param=0b00=0b01=0b10 const char* op op,"EOR","BSL","BIT","BIF"@ @ V\op\<c> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 1 0 N Q M 1 Vm VQSUB<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 0 1 1 N Q M op Vm @ op=0 const char* strict strict,"T","E"@ @ VCG\strict\<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 0 0 N Q M 0 Vm VSHL<c>.<dt> <Qd>, <Qm>, <Qn>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 0 0 N Q M 1 Vm VQSHL<c>.<dt> <Qd>, <Qm>, <Qn>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 0 1 N Q M 0 Vm VRSHL<c>.<dt> <Qd>, <Qm>, <Qn>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 0 1 N Q M 1 Vm VQRSHL<c>.<dt> <Qd>, <Qm>, <Qn>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 1 0 N Q M op Vm @ op=0 const char* opname opname,"MAX","MIN"@ @ V\opname\<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 1 1 N Q M 0 Vm VABD<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 0 1 1 1 N Q M 1 Vm VABA<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 op 0 D size Vn Vd 1 0 0 0 N Q M 0 Vm @ op=0 const char* opname opname,"ADD","SUB"@ @ V\opname\<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D size Vn Vd 1 0 0 0 N Q M 1 Vm VTST<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D size Vn Vd 1 0 0 0 N Q M 1 Vm VCEQ<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 1 0 0 1 N Q M 0 Vm @ set size = 8 << size@ @ VML\(u ? "S" : "A")\<c>.I\%dsize\ <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 1 0 0 1 N Q M 1 Vm VMUL<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 0 D size Vn Vd 1 0 1 0 N Q M op Vm @ op=0 const char* opname opname,"MAX","MIN"@ @ VP\opname\<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D size Vn Vd 1 0 1 1 N Q M 0 Vm VQDMULH<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D size Vn Vd 1 0 1 1 N Q M 0 Vm VQRDMULH<c>.<dt> <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D size Vn Vd 1 0 1 1 N Q/=0 M 1 Vm VPADD<c>.<dt> <Dd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 0 0 D U sz/=0 Vn Vd 1 1 0 0 N Q M 1 Vm @ u=0 const char* y y,"A","S"@ @ VFM\y\<c>.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D U sz/=0 Vn Vd 1 1 0 1 N Q M 0 Vm @ u=0 const char* op op,"ADD","SUB"@ @ V\op\<c>.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D 0 sz/=0 Vn Vd 1 1 0 1 N Q/=0 M 0 Vm VPADD.F32 <Dd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 1 0 D 1 sz/=0 Vn Vd 1 1 0 1 N Q M 0 Vm VABD.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D op sz/=0 Vn Vd 1 1 0 1 N Q M 1 Vm VML\(op ? "S" : "A")\<c>.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D 0 sz/=0 Vn Vd 1 1 0 1 N Q M 1 Vm VMUL.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 0 sz/=0 Vn Vd 1 1 1 0 N Q M 0 Vm VCEQ.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D op sz/=0 Vn Vd 1 1 1 0 N Q M 0 Vm @ op=1 const char* strict strict,"T","E"@ @ VCG\strict\.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D op sz/=0 Vn Vd 1 1 1 0 N Q M 1 Vm @ op=1 const char* strict strict,"T","E"@ @ VACG\strict\.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D op sz/=0 Vn Vd 1 1 1 1 N Q M 0 Vm @ op=0 const char* opname opname,"MAX","MIN"@ @ V\opname\.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 0 D op sz/=0 Vn Vd 1 1 1 1 N Q M 0 Vm @ op=0 const char* opname opname,"MAX","MIN"@ @ VP\opname\.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 0 sz/=0 Vn Vd 1 1 1 1 N Q M 1 Vm VRECPS.F32 <Qd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 0 0 D 1 sz/=0 Vn Vd 1 1 1 1 N Q M 1 Vm VRSQRTS.F32 <Qd>, <Qn>, <Qm>
+INVALIDATE 1 1 1 1 0 0 1 <1> 0 <23>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=0xx0 0 Q op/=0 1 imm4 VMOV<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=0xx1 0 Q op/=0 1 imm4 VORR<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=10x0 0 Q op/=0 1 imm4 VMOV<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=10x1 0 Q op/=0 1 imm4 VORR<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=11xx 0 Q op/=0 1 imm4 VMOV<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=0xx0 0 Q op/=1 1 imm4 VMVN<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=0xx1 0 Q op/=1 1 imm4 VBIC<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=10x0 0 Q op/=1 1 imm4 VMVN<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=10x1 0 Q op/=1 1 imm4 BIC<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=110x 0 Q op/=1 1 imm4 VMVN<c>.<dt> <Qd>, #<imm>
+NEON 1 1 1 1 0 0 1 i 1 D 0 0 0 imm3 Vd cmode/=1110 0 Q op/=1 1 imm4 VMOV<c>.<dt> <Qd>, #<imm>
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <1> 0 0 0 <11> 0 <2> 1 <4>
+NEON 1 1 1 1 0 0 1 0 1 D 0 0 1 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.S8 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D 0 1 0 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.S16 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D 1 0 0 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.S32 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 1 1 D 0 0 1 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.U8 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 1 1 D 0 1 0 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.U16 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 0 0 0 0 0 Vd 1 0 1 0 0 0 M 1 Vm VMOVL<c>.U32 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 0 0 0 0 L Q M 1 Vm VSHR<c>.<dt> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 0 0 0 1 L Q M 1 Vm VSRA<c>.<dt> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 0 0 1 0 L Q M 1 Vm VRSHR<c>.<dt> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 0 0 1 1 L Q M 1 Vm VRSRA<c>.<dt> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 1 1 D imm6 Vd 0 1 0 0 L Q M 1 Vm VSRI<c>.<size> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 0 1 D Imm6 Vd 0 1 0 1 L Q M 1 Vm VSHL<c>.I<size> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 1 1 D Imm6 Vd 0 1 0 1 L Q M 1 Vm VSLI<c>.<size> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D Imm6 Vd 0 1 1 op L Q M 1 Vm VQSHL\((u & op) ? "U" : "")\<c>.<dt> <Qd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 0 1 D imm6 Vd 1 0 0 0 0 0 M 1 Vm @ set ++size@ @ VSHRN<c>.I<size> <Dd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 0 1 D imm6 Vd 1 0 0 0 0 1 M 1 Vm VRSHRN<c>.I<size> <Dd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 1 0 0 op 0 0 M 1 Vm VQSHR\((u & op) ? "U" : "")\N<c>.<dt> <Dd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 U 1 D imm6 Vd 1 0 0 op 0 1 M 1 Vm VQRSHR\((u & op) ? "U" : "")\N<c>.<dt> <Dd>, <Qm>, #<imm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 1 1 0 0 M 1 Vm VSHLL<c>.<dt> <Qd>, <Dm>, #\%d8 &l&l size\
+NEON 1 1 1 1 0 0 1 U 1 D Imm6 Vd 1 0 1 0 0 0 M 1 Vm VSHLL<c>.<dt> <Qd>, <Dm>, #<imm>
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <1> 0 <9> 1 1 1 <1> 0 <2> 1 <4>
+NEON 1 1 1 1 0 0 1 0 1 D IMM6 Vd 1 1 1 0 0 Q M 1 Vm VCVT<c>.F32.S32 <Qd>, <Qm>, #<fbits>
+NEON 1 1 1 1 0 0 1 0 1 D IMM6 Vd 1 1 1 1 0 Q M 1 Vm VCVT<c>.S32.F32 <Qd>, <Qm>, #<fbits>
+NEON 1 1 1 1 0 0 1 1 1 D IMM6 Vd 1 1 1 0 0 Q M 1 Vm VCVT<c>.F32.U32 <Qd>, <Qm>, #<fbits>
+NEON 1 1 1 1 0 0 1 1 1 D IMM6 Vd 1 1 1 1 0 Q M 1 Vm VCVT<c>.U32.F32 <Qd>, <Qm>, #<fbits>
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <18> 1 <4>
+NEON 1 1 1 1 0 0 1 0 1 D 1 1 Vn Vd IMM4 N Q M 0 Vm VEXT<c>.8 <Qd>, <Qn>, <Qm>, #<imm>
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <2>/=11 0 0 <4> 0 0 0 <2> <2> 0 <4>
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <2>/=10 0 0 <4> 0 0 0 <2>/11 <2> 0 <4>
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <2>/=10 0 0 <4> 0 0 0 <2>/01 <2> 0 <4>
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <2>/=01 0 0 <4> 0 0 0 <2>/11 <2> 0 <4>
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <2>/=00 0 0 <4> 0 0 0 <2>/=11 <2> 0 <4>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 0 0 @<2> Q M 0 Vm VREV\%d16 &l&l param\<c>.\%d8 &l&l size\ <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 0 1 0 U Q M 0 Vm VPADDL<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 0 0 0 Q M 0 Vm VCLS<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 0 0 1 Q M 0 Vm VCLZ<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=00 0 0 Vd 0 1 0 1 0 Q M 0 Vm VCNT<c>.8 <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=00 0 0 Vd 0 1 0 1 1 Q M 0 Vm VMVN<c> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 1 0 U Q M 0 Vm VPADAL<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 1 1 0 Q M 0 Vm VQABS<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 1 1 1 Q M 0 Vm VQNEG<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 0 0 0 Q M 0 Vm VCGT<c>.<dt> <Qd>, <Qm>, #0
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 0 0 1 Q M 0 Vm VCGE<c>.<dt> <Qd>, <Qm>, #0
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 0 1 0 Q M 0 Vm VCEQ<c>.<dt> <Qd>, <Qm>, #0
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 0 1 1 Q M 0 Vm VCLE<c>.<dt> <Qd>, <Qm>, #0
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 1 0 0 Q M 0 Vm VCLT<c>.<dt> <Qd>, <Qm>, #0
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 1 1 0 Q M 0 Vm VABS<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 0 1 Vd 0 F 1 1 1 Q M 0 Vm VNEG<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=00 1 0 Vd 0 0 0 0 0 Q M 0 Vm VSWP<c> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 0 0 1 Q M 0 Vm VTRN<c>.\%d8 &l&l size\ <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 0 1 0 Q M 0 Vm VUZP<c>.\%d8 &l&l size\ <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 0 1 1 Q M 0 Vm VZIP<c>.\%d8 &l&l size\ <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 1 0 0 0 M 0 Vm VMOVN<c>.<dt> <Dd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 1 0 0 1 M 0 Vm VQMOVUN<c>.S\%d16 &l&l size\ <Dd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 1 0 1 U M 0 Vm @ set ++size@ @ VQMOVN<c>.<dt> <Dd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 0 Vd 0 0 1 1 0 0 M 0 Vm VSHLL<c>.I\%d8 &l&l size\ <Qd>, <Dm>, #\%d8 &l&l size\
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=01 1 0 Vd 0 1 1 0 0 0 M 0 Vm VCVT<c>.F16.F32 <Dd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=01 1 0 Vd 0 1 1 1 0 0 M 0 Vm VCVT<c>.F32.F16 <Qd>, <Dm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 1 Vd 0 1 0 F 0 Q M 0 Vm VRECPE<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size 1 1 Vd 0 1 0 F 1 Q M 0 Vm VRSQRTE<c>.<dt> <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=10 1 1 Vd 0 1 1 0 0 Q M 0 Vm VCVT<c>.F32.S32 <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=10 1 1 Vd 0 1 1 0 1 Q M 0 Vm VCVT<c>.S32.F32 <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=10 1 1 Vd 0 1 1 1 0 Q M 0 Vm VCVT<c>.F32.U32 <Qd>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 size/=10 1 1 Vd 0 1 1 1 1 Q M 0 Vm VCVT<c>.U32.F32 <Qd>, <Qm>
+INVALIDATE 1 1 1 1 0 0 1 1 1 <1> 1 1 <8> 0 <6> 0 <4>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 Vn Vd 1 0 @<2> N op M 0 Vm @ param=0b00 char list[10] !@ sprintf(list, %)@ "{%s}", vecname[0x20 + n]@ "{%s-%s}", vecname[0x20 + n], vecname[0x20 + n + param]@ @ VTB\(op ? "X" : "L")\<c>.8 <Dd>, \list\, <Dm>
+NEON 1 1 1 1 0 0 1 1 1 D 1 1 imm4 Vd 1 1 0 0 0 Q M 0 Vm VDUP<c>.\%dsize\ <Qd>, <Dm[x]>
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <1> 1 1 <13> 0 <1> 0 <4>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 0 0 0 Q N 0 M 0 Vm VADD\(q ? "W" : "L")\<c>.<dt> <qd>, <Qn>, <Dm>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 0 0 1 Q N 0 M 0 Vm VSUB\(q ? "W" : "L")\<c>.<dt> <qd>, <Qn>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 0 1 0 0 N 0 M 0 Vm @ set size = 16 << size@ @ VADDHN<c>.I\%dsize\ <Dd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D size Vn Vd 0 1 0 0 N 0 M 0 Vm VRADDHN<c>.<dt> <Dd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 0 1 0 1 N 0 M 0 Vm VABAL<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 0 1 1 0 N 0 M 0 Vm VSUBHN<c>.<dt> <Dd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 1 1 D size Vn Vd 0 1 1 0 N 0 M 0 Vm VRSUBHN<c>.<dt> <Dd>, <Qn>, <Qm>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 0 1 1 1 N 0 M 0 Vm VABDL<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 1 0 op 0 N 0 M 0 Vm VML\(op ? "S" : "A")\L<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 1 0 op 1 N 0 M 0 Vm VQDML\(op ? "S" : "A")\L<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 1 1 0 0 N 0 M 0 Vm VMULL<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 1 1 0 1 N 0 M 0 Vm VQDMULL<c>.<dt> <Qd>, <Dn>, <Dm>
+NEON 1 1 1 1 0 0 1 U/=0 1 D size/=00 Vn Vd 1 1 1 0 N 0 M 0 Vm @ set uint8_t size = 0@ @ VMULL<c>.<dt> <Qd>, <Dn>, <Dm>
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <16> 0 <1> 0 <4>
+NEON 1 1 1 1 0 0 1 Q 1 D size Vn Vd 0 op 0 F N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VML\(op ? "S" : "A")\<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 0 op 1 0 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VML\(op ? "S" : "A")\L<c>.<dt> <Qd>, <Dn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 0 op 1 1 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VQDML\(op ? "S" : "A")\L<c>.<dt> <Qd>, <Dn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 Q 1 D size Vn Vd 1 0 0 F N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VMUL<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 U 1 D size Vn Vd 1 0 1 0 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VMULL<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 0 1 D size Vn Vd 1 0 1 1 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VQDMULL<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 Q 1 D size Vn Vd 1 1 0 0 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VQDMULH<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+NEON 1 1 1 1 0 0 1 Q 1 D size Vn Vd 1 1 0 1 N 1 M 0 Vm @ size=0b01=0b10 unsigned int decodedImm !@ decodedImm = m >> %; m %@ 3@ &= 0x7@ 4@ &= 0xF@ 5@ = 0x21@ @ VQRDMULH<c>.<dt> <Qd>, <Qn>, <Dm[x]>
+INVALIDATE 1 1 1 1 0 0 1 <1> 1 <16> 0 <1> 0 <4>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 0 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 0 1 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 0 size @<2> Rm @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 0 1 size @<2> Rm @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 0 1 1 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 0 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 0 0 Rn Vd 1 0 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\], <Rm>
+INVALIDATE 1 1 1 1 0 1 0 0 1 <1> 0 0 <8> 1 1 <10>
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 0 @<4> 1 1 1 1 @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 0 @<4> 1 1 0 1 @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 0 @<4> Rm @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VST1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> Rm @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>]
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>]!
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> Rm @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VST3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 0 0 Rn Vd size 0 1 @<4> Rm @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VST4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\, \vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 0 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\, \vecname[0x26 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 0 1 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x23 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 0 size @<2> Rm @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 0 1 size @<2> Rm @ param=0b00 char align[4] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 63 + param)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\, \vecname[0x24 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\-\vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 0 1 1 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 1 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 1 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 0 1 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x22 + d]\}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 1 0 size @<2> 1 1 1 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 1 0 size @<2> 1 1 0 1 @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 0 D 1 0 Rn Vd 1 0 1 0 size @<2> Rm @ param=0b00 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 32 << param)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\, \vecname[0x21 + d]\}, [<Rn>\align\], <Rm>
+INVALIDATE 1 1 1 1 0 1 0 0 1 <1> 1 0 <8> 1 1 <10>
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 0 @<4> 1 1 1 1 @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 0 @<4> 1 1 0 1 @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 0 @<4> Rm @ set uint8_t temp = (2 << size) - 1@ set uint8_t temp2 = param & temp@ temp2=0=param>>1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 8 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ @ VLD1<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\]}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> Rm @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0=1 char align[5] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", 16 << size)@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD2<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\]}, [<Rn>\align\], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>]
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>]!
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> Rm @ set uint8_t temp = param & (1 << size)@ temp=0 uint8_t spacing spacing,0,1@ set uint8_t x = param >> (size + 1)@ @ VLD3<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\]}, [<Rn>], <Rm>
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 1 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\]
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> 1 1 0 1 @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\]!
+NEON 1 1 1 1 0 1 0 0 1 D 1 0 Rn Vd size 0 1 @<4> Rm @ size=0b00=0b01 uint8_t temp temp,1,1,3@ set uint8_t temp2 = param & temp@ temp2=0b0=0b1=0b10 char align[6] !@ %@ align[0] = '\0'@ sprintf(align, ":%d", (size ? 64 : 32))@ sprintf(align, ":128")@ sprintf(align, "???")@ set uint8_t x = param >> (size + 1)@ set int spacing = size ? ((param >> size) & 1) : 0@ @ VLD4<c>.\%d8 &l&l size\ {\vecname[0x20 + d]\[\%dx\], \vecname[0x21 + d + spacing]\[\%dx\], \vecname[0x22 + d + 2*spacing]\[\%dx\], \vecname[0x23 + d + 3*spacing]\[\%dx\]}, [<Rn>\align\], <Rm>
+INVALIDATE 1 1 1 1 0 1 0 0 <3> 0 <20>
+INVALIDATE 1 1 1 1 <28>
+ARMS cond 0 0 0 0 0 0 0 S Rn Rd imm5 type 0 Rm AND{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 0 0 0 S Rd (0) (0) (0) (0) Rm 1 0 0 1 Rn MUL{S}<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 0 0 0 U 0 0 0 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm STRH<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 0 0 Rn Rt (0) (0) (0) (0) 1 1 0 1 Rm LDRD<c> <Rt>, <Rt2>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 0 0 Rn Rt (0) (0) (0) (0) 1 1 1 1 Rm STRD<c> <Rt>, <Rt2>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 0 1 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm LDRH<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 0 1 Rn Rt (0) (0) (0) (0) 1 1 0 1 Rm LDRSB<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 0 1 Rn Rt (0) (0) (0) (0) 1 1 1 1 Rm LDRSH<c> <Rt>, [<Rn>], +/-<Rm>
+ARMS cond 0 0 0 0 0 0 1 S Rn Rd imm5 type 0 Rm EOR{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 0 0 1 S Rd Ra Rm 1 0 0 1 Rn MLA{S}<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 0 U 0 1 0 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm STRHT<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 1 1 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm LDRHT<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 1 1 Rn Rt (0) (0) (0) (0) 1 1 0 1 Rm LDRSBT<c> <Rt>, [<Rn>], +/-<Rm>
+ARM_ cond 0 0 0 0 U 0 1 1 Rn Rt (0) (0) (0) (0) 1 1 1 1 Rm LDRSHT<c> <Rt>, [<Rn>], +/-<Rm>
+ARMS cond 0 0 0 0 0 1 0 S Rn Rd imm5 type 0 Rm SUB{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 0 1 0 0 RdHi RdLo Rm 1 0 0 1 Rn UMAAL<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+ARM_ cond 0 0 0 0 U 1 0 0 Rn Rt imm4H 1 0 1 1 imm4L STRH<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 0 0 Rn Rt imm4H 1 1 0 1 imm4L LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 0 0 Rn Rt imm4H 1 1 1 1 imm4L STRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 0 1 Rn Rt imm4H 1 0 1 1 imm4L LDRH<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 0 1 Rn Rt imm4H 1 1 0 1 imm4L LDRSB<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 0 1 Rn Rt imm4H 1 1 1 1 imm4L LDRSH<c> <Rt>, [<Rn>], #+/-<imm8>
+ARMS cond 0 0 0 0 0 1 1 S Rn Rd imm5 type 0 Rm RSB{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 0 1 1 0 Rd Ra Rm 1 0 0 1 Rn MLS<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 0 U 1 1 0 Rn Rt imm4H 1 0 1 1 imm4L STRHT<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 1 1 Rn Rt imm4H 1 0 1 1 imm4L LDRHT<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 1 1 Rn Rt imm4H 1 1 0 1 imm4L LDRSBT<c> <Rt>, [<Rn>], #+/-<imm8>
+ARM_ cond 0 0 0 0 U 1 1 1 Rn Rt imm4H 1 1 1 1 imm4L LDRSHT<c> <Rt>, [<Rn>], #+/-<imm8>
+ARMS cond 0 0 0 0 1 0 0 S Rn Rd imm5 type 0 Rm ADD{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 1 0 0 S RdHi RdLo Rm 1 0 0 1 Rn UMULL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+ARMS cond 0 0 0 0 1 0 1 S Rn Rd imm5 type 0 Rm ADC{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 1 0 1 S RdHi RdLo Rm 1 0 0 1 Rn UMLAL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+ARMS cond 0 0 0 0 1 1 0 S Rn Rd imm5 type 0 Rm SBC{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 1 1 0 S RdHi RdLo Rm 1 0 0 1 Rn SMULL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+ARMS cond 0 0 0 0 1 1 1 S Rn Rd imm5 type 0 Rm RSC{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 0 1 1 1 S RdHi RdLo Rm 1 0 0 1 Rn SMLAL{S}<c> <RdLo>, <RdHi>, <Rn>, <Rm>
+ARM_ cond 0 0 0 1 0 0 0 0 Rd Ra Rm 1 0 0 0 Rn SMLABB<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 1 0 0 0 0 Rd Ra Rm 1 0 1 0 Rn SMLATB<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 1 0 0 0 0 Rd Ra Rm 1 1 0 0 Rn SMLABT<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 1 0 0 0 0 Rd Ra Rm 1 1 1 0 Rn SMLATT<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 0 0 1 0 0 0 0 Rn Rt (0) (0) (0) (0) 1 0 0 1 Rm SWP<c> <Rt>, <Rm>, [<Rn>]
+ARM_ cond 0 0 0 1 U 0 W 0 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm STRH<c> <Rt>, [<Rn>, +/-<Rm>]{!}
+ARM_ cond 0 0 0 1 U 0 W 0 Rn Rt (0) (0) (0) (0) 1 1 0 1 Rm LDRD<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}
+ARM_ cond 0 0 0 1 U 0 W 0 Rn Rt (0) (0) (0) (0) 1 1 1 1 Rm STRD<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}
+ARMS cond 0 0 0 1 0 0 0 1 Rn (0) (0) (0) (0) imm5 type 0 Rm TST<c> <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 U 0 W 1 Rn Rt (0) (0) (0) (0) 1 0 1 1 Rm LDRH<c> <Rt>, [<Rn>, +/-<Rm>]{!}
+ARM_ cond 0 0 0 1 U 0 W 1 Rn Rt (0) (0) (0) (0) 1 1 0 1 Rm LDRSB<c> <Rt>, [<Rn>, +/-<Rm>]{!}
+ARM_ cond 0 0 0 1 U 0 W 1 Rn Rt (0) (0) (0) (0) 1 1 1 1 Rm LDRSH<c> <Rt>, [<Rn>, +/-<Rm>]{!}
+ARM_ cond 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 0 1 Rm BX<c> <Rm>
+ARM_ cond 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 0 Rm BXJ<c> <Rm>
+ARM_ cond 0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 1 Rm BLX<c> <Rm>
+ARM_ cond/=1110 0 0 0 1 0 0 1 0 imm12 0 1 1 1 imm4 BKPT #<imm16>
+ARMS cond 0 0 0 1 0 0 1 1 Rn (0) (0) (0) (0) imm5 type 0 Rm TEQ<c> <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 0 1 0 0 Rn Rt (0) (0) (0) (0) 1 0 0 1 Rm SWPB<c> <Rt>, <Rm>, [<Rn>]
+ARM_ cond 0 0 0 1 U 1 W 0 Rn Rt imm4H 1 0 1 1 imm4L STRH<c> <Rt>, [<Rn>, #+/-<imm8>]{!}
+ARM_ cond 0 0 0 1 U 1 W 0 Rn Rt imm4H 1 1 0 1 imm4L LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm8>]{!}
+ARM_ cond 0 0 0 1 U 1 W 0 Rn Rt imm4H 1 1 1 1 imm4L STRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm8>]{!}
+ARMS cond 0 0 0 1 0 1 0 1 Rn (0) (0) (0) (0) imm5 type 0 Rm CMP<c> <Rn>, <Rm>{, <shift>}
+ARMS cond 0 0 0 1 0 1 1 1 Rn (0) (0) (0) (0) imm5 type 0 Rm CMN<c> <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 U 1 W 1 Rn Rt imm4H 1 0 1 1 imm4L LDRH<c> <Rt>, [<Rn>, #+/-<imm8>]{!}
+ARM_ cond 0 0 0 1 U 1 W 1 Rn Rt imm4H 1 1 0 1 imm4L LDRSB<c> <Rt>, [<Rn>, #+/-<imm8>]{!}
+ARM_ cond 0 0 0 1 U 1 W 1 Rn Rt imm4H 1 1 1 1 imm4L LDRSH<c> <Rt>, [<Rn>, #+/-<imm8>]{!}
+ARMS cond 0 0 0 1 1 0 0 S Rn Rd imm5 type 0 Rm ORR{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 1 0 0 0 Rn Rd (1) (1) (1) (1) 1 0 0 1 Rt STREX<c> <Rd>, <Rt>, [<Rn>]
+ARM_ cond 0 0 0 1 1 0 0 1 Rn Rt (1) (1) (1) (1) 1 0 0 1 (1) (1) (1) (1) LDREX<c> <Rt>, [<Rn>]
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd 0 0 0 0 0 0 0 0 Rm MOV{S}<c> <Rd>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd imm5 0 0 0 Rm LSL{S}<c> <Rd>, <Rm>, #<imm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd Rm 0 0 0 1 Rn LSL{S}<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd imm5 0 1 0 Rm LSR{S}<c> <Rd>, <Rm>, #<imm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd Rm 0 0 1 1 Rn LSR{S}<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd imm5 1 0 0 Rm ASR{S}<c> <Rd>, <Rm>, #<imm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd Rm 0 1 0 1 Rn ASR{S}<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd 0 0 0 0 0 1 1 0 Rm RRX{S}<c> <Rd>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd imm5 1 1 0 Rm ROR{S}<c> <Rd>, <Rm>, #<imm>
+ARM_ cond 0 0 0 1 1 0 1 S (0) (0) (0) (0) Rd Rm 0 1 1 1 Rn ROR{S}<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 0 0 1 1 0 1 0 Rn Rd (1) (1) (1) (1) 1 0 0 1 Rt STREXD<c> <Rd>, <Rt>, <Rt2>, [<Rn>]
+ARM_ cond 0 0 0 1 1 0 1 1 Rn Rt (1) (1) (1) (1) 1 0 0 1 (1) (1) (1) (1) LDREXD<c> <Rt>, <Rt2>, [<Rn>]
+ARMS cond 0 0 0 1 1 1 0 S Rn Rd imm5 type 0 Rm BIC{S}<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 1 1 0 0 Rn Rd (1) (1) (1) (1) 1 0 0 1 Rt STREXB<c> <Rd>, <Rt>, [<Rn>]
+ARM_ cond 0 0 0 1 1 1 0 1 Rn Rt (1) (1) (1) (1) 1 0 0 1 (1) (1) (1) (1) LDREXB<c> <Rt>, [<Rn>]
+ARMS cond 0 0 0 1 1 1 1 S (0) (0) (0) (0) Rd imm5 type 0 Rm MVN{S}<c> <Rd>, <Rm>{, <shift>}
+ARM_ cond 0 0 0 1 1 1 1 0 Rn Rd (1) (1) (1) (1) 1 0 0 1 Rt STREXH<c> <Rd>, <Rt>, [<Rn>]
+ARM_ cond 0 0 0 1 1 1 1 1 Rn Rt (1) (1) (1) (1) 1 0 0 1 (1) (1) (1) (1) LDREXH<c> <Rt>, [<Rn>]
+ARM_ cond 0 0 1 0 0 0 0 S Rn Rd imm12 AND{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 0 0 1 S Rn Rd imm12 EOR{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 0 1 0 S Rn Rd imm12 SUB{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 0 1 1 S Rn Rd imm12 RSB{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 1 0 0 S Rn Rd imm12 ADD{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 1 0 1 S Rn Rd imm12 ADC{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 1 1 0 S Rn Rd imm12 SBC{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 0 1 1 1 S Rn Rd imm12 RSC{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 1 0 0 0 0 imm4 Rd imm12 MOVW<c> <Rd>, #<imm16>
+ARM_ cond 0 0 1 1 0 0 0 1 Rn (0) (0) (0) (0) imm12 TST<c> <Rn>, #<const>
+ARM_ cond 0 0 1 1 0 0 1 0 0 0 0 0 (1) (1) (1) (1) (0) (0) (0) (0) 0 0 0 0 0 0 0 0 NOP<c>
+ARM_ cond 0 0 1 1 0 0 1 1 Rn (0) (0) (0) (0) imm12 TEQ<c> <Rn>, #<const>
+ARM_ cond 0 0 1 1 0 1 0 0 imm4 Rd imm12 MOVT<c> <Rd>, #<imm16>
+ARM_ cond 0 0 1 1 0 1 0 1 Rn (0) (0) (0) (0) imm12 CMP<c> <Rn>, #<const>
+ARM_ cond 0 0 1 1 0 1 1 1 Rn (0) (0) (0) (0) imm12 CMN<c> <Rn>, #<const>
+ARM_ cond 0 0 1 1 1 0 0 S Rn Rd imm12 ORR{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 1 1 0 1 S (0) (0) (0) (0) Rd imm12 MOV{S}<c> <Rd>, #<const>
+ARM_ cond 0 0 1 1 1 1 0 S Rn Rd imm12 BIC{S}<c> <Rd>, <Rn>, #<const>
+ARM_ cond 0 0 1 1 1 1 1 S (0) (0) (0) (0) Rd imm12 MVN{S}<c> <Rd>, #<const>
+ARM_ cond 0 1 0 0 1 0 0 1 1 1 0 1 Rt 0 0 0 0 0 0 0 0 0 1 0 0 POP<c> {<Rt>}
+ARM_ cond 0 1 0 0 U 0 0 0 Rn Rt imm12 STR<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 0 0 1 Rn Rt imm12 LDR<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 0 1 0 Rn Rt imm12 STRT<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 0 1 1 Rn Rt imm12 LDRT<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 1 0 0 Rn Rt imm12 STRB<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 1 0 1 Rn Rt imm12 LDRB<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 1 1 0 Rn Rt imm12 STRBT<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 0 U 1 1 1 Rn Rt imm12 LDRBT<c> <Rt>, [<Rn>], #+/-<imm12>
+ARM_ cond 0 1 0 1 0 0 1 0 1 1 0 1 Rt 0 0 0 0 0 0 0 0 0 1 0 0 PUSH<c> {<Rt>}
+ARM_ cond 0 1 0 1 U 0 W 0 Rn Rt imm12 STR<c> <Rt>, [<Rn>, #+/-<imm12>]{!}
+ARM_ cond 0 1 0 1 U 0 W 1 Rn Rt imm12 LDR<c> <Rt>, [<Rn>, #+/-<imm12>]{!}
+ARM_ cond 0 1 0 1 U 1 W 0 Rn Rt imm12 STRB<c> <Rt>, [<Rn>, #+/-<imm12>]{!}
+ARM_ cond 0 1 0 1 U 1 W 1 Rn Rt imm12 LDRB<c> <Rt>, [<Rn>, #+/-<imm12>]{!}
+ARM_ cond 0 1 1 0 0 0 0 1 Rn Rd (1) (1) (1) (1) 0 1 0 1 Rm SSAX<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 0 0 0 0 1 Rn Rd (1) (1) (1) (1) 0 1 1 1 Rm SSUB16<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 0 0 0 0 1 Rn Rd (1) (1) (1) (1) 1 1 1 1 Rm SSUB8<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 0 0 1 0 1 Rn Rd (1) (1) (1) (1) 0 1 0 1 Rm USAX<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 0 0 1 0 1 Rn Rd (1) (1) (1) (1) 0 1 1 1 Rm USUB16<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 0 0 1 0 1 Rn Rd (1) (1) (1) (1) 1 1 1 1 Rm USUB8<c> <Rd>, <Rn>, <Rm>
+ARMs cond 0 1 1 0 1 0 0 0 Rn Rd imm5 0 0 1 Rm PKHBT<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARMs cond 0 1 1 0 1 0 0 0 Rn Rd imm5 1 0 1 Rm PKHTB<c> <Rd>, <Rn>, <Rm>{, <shift>}
+ARM_ cond 0 1 1 0 1 0 0 0 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm SXTB16<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 0 0 0 Rn Rd rotate (0) (0) 0 1 1 1 Rm SXTAB16<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARMs cond 0 1 1 0 1 0 1 sat_imm Rd imm5 sh 0 1 Rn SSAT<c> <Rd>, #<imm>, <Rn>{, <shift>}
+ARM_ cond 0 1 1 0 1 0 1 0 sat_imm Rd (1) (1) (1) (1) 0 0 1 1 Rn SSAT16<c> <Rd>, #<imm>, <Rn>
+ARM_ cond 0 1 1 0 1 0 1 0 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm SXTB<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 0 1 0 Rn Rd rotate (0) (0) 0 1 1 1 Rm SXTAB<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 0 1 1 (1) (1) (1) (1) Rd (1) (1) (1) (1) 0 0 1 1 Rm REV<c> <Rd>, <Rm>
+ARM_ cond 0 1 1 0 1 0 1 1 (1) (1) (1) (1) Rd (1) (1) (1) (1) 1 0 1 1 Rm REV16<c> <Rd>, <Rm>
+ARM_ cond 0 1 1 0 1 0 1 1 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm SXTH<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 0 1 1 Rn Rd rotate (0) (0) 0 1 1 1 Rm SXTAH<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 1 0 0 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm UXTB16<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 1 0 0 Rn Rd rotate (0) (0) 0 1 1 1 Rm UXTAB16<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARMs cond 0 1 1 0 1 1 1 sat_imm Rd imm5 sh 0 1 Rn USAT<c> <Rd>, #<imm>, <Rn>{, <shift>}
+ARM_ cond 0 1 1 0 1 1 1 0 sat_imm Rd (1) (1) (1) (1) 0 0 1 1 Rn USAT16<c> <Rd>, #<imm>, <Rn>
+ARM_ cond 0 1 1 0 1 1 1 0 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm UXTB<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 1 1 0 Rn Rd rotate (0) (0) 0 1 1 1 Rm UXTAB<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 1 1 1 1 1 1 1 Rd rotate (0) (0) 0 1 1 1 Rm UXTH<c> <Rd>, <Rm>{, <rotation>}
+ARM_ cond 0 1 1 0 1 1 1 1 (1) (1) (1) (1) Rd (1) (1) (1) (1) 1 0 1 1 Rm REVSH<c> <Rd>, <Rm>
+ARM_ cond 0 1 1 0 1 1 1 1 Rn Rd rotate (0) (0) 0 1 1 1 Rm UXTAH<c> <Rd>, <Rn>, <Rm>{, <rotation>}
+ARMs cond 0 1 1 0 U 0 0 0 Rn Rt imm5 type 0 Rm STR<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 0 0 1 Rn Rt imm5 type 0 Rm LDR<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 0 1 0 Rn Rt imm5 type 0 Rm STRT<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 0 1 1 Rn Rt imm5 type 0 Rm LDRT<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 1 0 0 Rn Rt imm5 type 0 Rm STRB<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 1 0 1 Rn Rt imm5 type 0 Rm LDRB<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 1 1 0 Rn Rt imm5 type 0 Rm STRBT<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 0 U 1 1 1 Rn Rt imm5 type 0 Rm LDRBT<c> <Rt>, [<Rn>], +/-<Rm>{, <shift>}
+ARMs cond 0 1 1 1 U 0 W 0 Rn Rt imm5 type 0 Rm STR<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
+ARMs cond 0 1 1 1 U 0 W 1 Rn Rt imm5 type 0 Rm LDR<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
+ARMs cond 0 1 1 1 U 1 W 0 Rn Rt imm5 type 0 Rm STRB<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
+ARMs cond 0 1 1 1 U 1 W 1 Rn Rt imm5 type 0 Rm LDRB<c> <Rt>, [<Rn>, +/-<Rm>{, <shift>}]{!}
+ARM_ cond 0 1 1 1 1 0 0 0 Rd 1 1 1 1 Rm 0 0 0 1 Rn USAD8<c> <Rd>, <Rn>, <Rm>
+ARM_ cond 0 1 1 1 1 0 0 0 Rd Ra Rm 0 0 0 1 Rn USADA8<c> <Rd>, <Rn>, <Rm>, <Ra>
+ARM_ cond 0 1 1 1 1 1 0 msb Rd lsb 0 0 1 1 1 1 1 BFC<c> <Rd>, #<lsb>, #<width>
+ARM_ cond 0 1 1 1 1 1 0 msb Rd lsb 0 0 1 Rn BFI<c> <Rd>, <Rn>, #<lsb>, #<width>
+ARM_ cond 0 1 1 1 1 1 1 widthm1 Rd lsb 1 0 1 Rn UBFX<c> <Rd>, <Rn>, #<lsb>, #<width>
+ARM_ cond 1 0 0 0 0 0 W 0 Rn/=1101 register_list STMED<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 0 0 W 0 Rn register_list STMDA<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 0 0 W 1 Rn/=1101 register_list LDMED<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 0 0 W 1 Rn register_list LDMDA<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 1 0 W 0 Rn/=1101 register_list STMEA<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 1 0 W 0 Rn register_list STM<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 0 1 0 0 1 Rn/=1101 register_list LDMEA<c> <Rn>, <registers>
+ARM_ cond 1 0 0 0 1 0 1 1 1 1 0 1 register_list @ = const char* op @@ (reglist != 0) && ((reglist & (reglist - 1)) == 0)@ op,"POP","LDMEA"@ @ \op\<c> <registers>
+ARM_ cond 1 0 0 0 1 0 W 1 Rn register_list LDM<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 0 0 0 0 Rn/=1101 register_list STMFD<c> <Rn>, <registers>
+ARM_ cond 1 0 0 1 0 0 1 0 1 1 0 1 register_list @ = const char* op @@ (reglist != 0) && ((reglist & (reglist - 1)) == 0)@ op,"PUSH","STMFD"@ @ \op\<c> <registers>
+ARM_ cond 1 0 0 1 0 0 W 0 Rn register_list STMDB<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 0 0 W 1 Rn/=1101 register_list LDMFD<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 0 0 W 1 Rn register_list LDMDB<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 1 0 W 0 Rn/=1101 register_list STMFA<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 1 0 W 0 Rn register_list STMIB<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 1 0 W 1 Rn/=1101 register_list LDMFA<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 0 1 1 0 W 1 Rn register_list LDMIB<c> <Rn>{!}, <registers>
+ARM_ cond 1 0 1 0 imm24 B<c> <label>
+ARM_ cond 1 0 1 1 imm24 BL<c> <label>
+VFPU cond 1 1 0 0 0 1 0 0 Rn Rt 1 0 1 0 0 0 M 1 Vm VMOV<c> <Sm>, <Sm1>, <Rt>, <Rn>
+VFPU cond 1 1 0 0 0 1 0 1 Rn Rt 1 0 1 0 0 0 M 1 Vm VMOV<c> <Rt>, <Rn>, <Sm>, <Sm1>
+VFPU cond 1 1 0 0 0 1 0 0 Rn Rt 1 0 1 1 0 0 M 1 Vm VMOV<c> <Dm>, <Rt>, <Rn>
+VFPU cond 1 1 0 0 0 1 0 1 Rn Rt 1 0 1 1 0 0 M 1 Vm VMOV<c> <Rt>, <Rn>, <Dm>
+INVALIDATE <4> 1 1 0 0 0 <11> 1 0 1 <9>
+INVALIDATE <4> 1 1 0 0 0 <11> 1 0 1 <9>
+INVALIDATE <4> 1 1 0 1 1 <1> 1 <9> 1 0 1 <9>
+INVALIDATE <4> 1 1 0 1 1 <1> 1 <9> 1 0 1 <9>
+VFPU cond 1 1 0 1 0 D 1 0 1 1 0 1 Vd 1 0 1 1 imm8/01 @ set --imm8@ @ FSTMX<c> <LIst>
+VFPU cond 1 1 0 1 0 D 1 0 1 1 0 1 Vd 1 0 1 sz imm8 VPUSH<c> <list>
+VFPU cond 1 1 0 1 U D 0 0 Rn Vd 1 0 1 sz imm8 VSTR<c> <Dd>, [<Rn>{, #+/-<imm>}]
+VFPU cond 1 1 0 @<2> D W 0 Rn Vd 1 0 1 1 imm8/01 @ set --imm8@ @ FSTM\(param == 0b01 ? "IA" : "DB")\X<c> <Rn>{!}, <LIst>
+VFPU cond 1 1 0 @<2> D W 0 Rn Vd 1 0 1 sz imm8 VSTM\(param == 0b01 ? "IA" : "DB")\<c> <Rn>{!}, <list>
+VFPU cond 1 1 0 0 1 D 1 1 1 1 0 1 Vd 1 0 1 1 imm8/01 @ set --imm8@ @ FLDMX<c> <LIst>
+VFPU cond 1 1 0 0 1 D 1 1 1 1 0 1 Vd 1 0 1 sz imm8 VPOP<c> <list>
+VFPU cond 1 1 0 1 0 D 0 1 1 1 1 1 Vd 1 0 1 sz 0 0 0 0 0 0 0 0 VLDR<c> <Dd>, [PC, #-0]
+VFPU cond 1 1 0 1 U D 0 1 1 1 1 1 Vd 1 0 1 sz imm8 VLDR<c> <Dd>, <label>
+VFPU cond 1 1 0 1 U D 0 1 Rn Vd 1 0 1 sz imm8 VLDR<c> <Dd>, [<Rn>{, #+/-<imm>}]
+VFPU cond 1 1 0 @<2> D W 1 Rn Vd 1 0 1 1 imm8/01 @ set --imm8@ @ FLDM\(param == 0b01 ? "IA" : "DB")\X<c> <Rn>{!}, <LIst>
+VFPU cond 1 1 0 @<2> D W 1 Rn Vd 1 0 1 sz imm8 VLDM\(param == 0b01 ? "IA" : "DB")\<c> <Rn>{!}, <list>
+INVALIDATE <4> 1 1 0 <25>
+INVALIDATE <4> 1 1 1 0 0 0 <1> 0 <8> 1 0 1 1 <1> 1 0 1 (0) (0) (0) (0)
+VFPU cond 1 1 1 0 0 0 0 0 Vn Rt 1 0 1 0 N (0) (0) 1 (0) (0) (0) (0) VMOV<c> <Sn>, <Rt>
+VFPU cond 1 1 1 0 1 1 1 0 0 0 0 1 Rt 1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0) VMSR<c> FPSCR, <Rt>
+VFPU cond 1 1 1 0 0 @<2> 0 Vd Rt 1 0 1 1 D @<2> 1 (0) (0) (0) (0) @ set uint8_t opc = (param1_2 << 2) + param2_2@ = uint8_t shift @@ (opc & 0b1000) == 0b1000@ @@ (opc & 0b1001) == 0b0001@ @@ (opc & 0b1011) == 0b0000@ shift,0,1,2,0xFF@ set uint8_t decodedImm = (opc & 0x7) >> shift@ @ VMOV<c>.\%d8 &l&l shift\ <Dd[x]>, <Rt>
+VFPU cond 1 1 1 0 1 0 Q 0 Vd Rt 1 0 1 1 D 0 0 1 (0) (0) (0) (0) VDUP<c>.32 <Qd>, <Rt>
+VFPU cond 1 1 1 0 1 0 Q 0 Vd Rt 1 0 1 1 D 0 1 1 (0) (0) (0) (0) VDUP<c>.16 <Qd>, <Rt>
+VFPU cond 1 1 1 0 1 1 Q 0 Vd Rt 1 0 1 1 D 0 0 1 (0) (0) (0) (0) VDUP<c>.8 <Qd>, <Rt>
+VFPU cond 1 1 1 0 0 0 0 1 Vn Rt 1 0 1 0 N (0) (0) 1 (0) (0) (0) (0) VMOV<c> <Rt>, <Sn>
+VFPU cond 1 1 1 0 1 1 1 1 0 0 0 1 Rt 1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0) VMRS<c> <Rt>, FPSCR
+VFPU cond 1 1 1 0 U @<2> 1 Vn Rt 1 0 1 1 N @<2> 1 (0) (0) (0) (0) @ set uint8_t opc = (u << 4) + (param1_2 << 2) + param2_2@ = uint8_t shift, size @@ (opc & 0b01000) == 0b01000@ @@ (opc & 0b01001) == 0b00001@ @@ (opc & 0b11011) == 0b00000@ shift,0,1,2,0xFF;size,0,1,2,4@ set uint8_t decodedImm = (opc & 0x7) >> shift@ @ VMOV<c>.<dt> <Rt>, <Dn[x]>
+INVALIDATE <4> 1 1 1 0 <12> 1 0 1 <4> 1 <4>
+VFPU cond 1 1 1 0 0 D 0 0 Vn Vd 1 0 1 sz N op M 0 Vm VML\(op ? "S" : "A")\<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 0 D 0 1 Vn Vd 1 0 1 sz N op M 0 Vm VNML\(op ? "S" : "A")\<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 0 D 1 0 Vn Vd 1 0 1 sz N 0 M 0 Vm VMUL<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 0 D 1 0 Vn Vd 1 0 1 sz N 1 M 0 Vm VNMUL<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 0 D 1 1 Vn Vd 1 0 1 sz N 0 M 0 Vm VADD<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 0 D 1 1 Vn Vd 1 0 1 sz N 1 M 0 Vm VSUB<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 1 D 0 0 Vn Vd 1 0 1 sz N 0 M 0 Vm VDIV<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 1 D 0 1 Vn Vd 1 0 1 sz N op M 0 Vm VFNM\(op ? "A" : "S")\<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 0 Vn Vd 1 0 1 sz N op M 0 Vm VFM\(op ? "S" : "A")\<c>.F\(size ? "64" : "32")\ <Dd>, <Dn>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 @<4> Vd 1 0 1 0 (0) 0 (0) 0 @<4> @ set int8_t sign = (param1_4 >> 3) ? -1 : 1@ set uint8_t exp = ((param1_4 & 0b111) ^ 0b100)@ set float mantissa = 16 + param2_4@ set float imm = sign * (1 << exp) * mantissa / 128.@ @ VMOV<c>.F32 <Sd>, #\%fimm\
+VFPU cond 1 1 1 0 1 D 1 1 @<4> Vd 1 0 1 1 (0) 0 (0) 0 @<4> @ set int8_t sign = (param1_4 >> 3) ? -1 : 1@ set uint8_t exp = ((param1_4 & 0b111) ^ 0b100)@ set double mantissa = 16 + param2_4@ set double imm = sign * (1 << exp) * mantissa / 128.@ @ VMOV<c>.F64 <Dd>, #\%fimm\
+VFPU cond 1 1 1 0 1 D 1 1 0 0 0 0 Vd 1 0 1 sz 0 1 M 0 Vm VMOV<c>.F\(size ? "64" : "32")\ <Dd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 0 0 0 0 Vd 1 0 1 sz 1 1 M 0 Vm VABS<c>.F\(size ? "64" : "32")\ <Dd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 0 0 0 1 Vd 1 0 1 sz 0 1 M 0 Vm VNEG<c>.F\(size ? "64" : "32")\ <Dd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 0 0 0 1 Vd 1 0 1 sz 1 1 M 0 Vm VSQRT<c>.F\(size ? "64" : "32")\ <Dd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 0 0 1 0 Vd 1 0 1 (0) @<1> 1 M 0 Vm VCVT\(param ? "T" : "B")\<c>.F32.F16 <Sd>, <Sm>
+VFPU cond 1 1 1 0 1 D 1 1 0 0 1 1 Vd 1 0 1 (0) @<1> 1 M 0 Vm VCVT\(param ? "T" : "B")\<c>.F16.F32 <Sd>, <Sm>
+VFPU cond 1 1 1 0 1 D 1 1 0 1 0 0 Vd 1 0 1 sz op 1 M 0 Vm VCMP\(op ? "E" : "")\<c>.F\(size ? "64" : "32")\ <Dd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 0 1 0 1 Vd 1 0 1 sz op 1 (0) 0 (0) (0) (0) (0) VCMP\(op ? "E" : "")\<c>.F\(size ? "64" : "32")\ <Dd>, #0.0
+VFPU cond 1 1 1 0 1 D 1 1 0 1 1 1 Vd 1 0 1 0 1 1 M 0 Vm VCVT<c>.F64.F32 <Dd>, <Sm>
+VFPU cond 1 1 1 0 1 D 1 1 0 1 1 1 Vd 1 0 1 1 1 1 M 0 Vm VCVT<c>.F32.F64 <Sd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 1 0 0 0 Vd 1 0 1 sz op 1 M 0 Vm VCVT<c>.F\(size ? "64" : "32")\.\(op ? "S" : "U")\32 <Dd>, <Sm>
+VFPU cond 1 1 1 0 1 D 1 1 1 0 1 U Vd 1 0 1 sz op 1 i 0 imm4 @ set uint8_t td = (u << 2) + op + 1@ td=0b001=0b010=0b101 const char* Td Td,"S16","U16","S32","U32"@ set imm5 = (16 << op) - (imm5 >> 4) - ((imm5 & 0xF) << 1)@ @ VCVT<c>.F\(size ? "64" : "32")\.\Td\ <Dd>, <Dd>, #<imm>
+VFPU cond 1 1 1 0 1 D 1 1 1 1 0 U Vd 1 0 1 sz op 1 M 0 Vm VCVT\(op ? "" : "R")\<c>.\(u ? "U" : "S")\32.F\(size ? "64" : "32")\ <Sd>, <Dm>
+VFPU cond 1 1 1 0 1 D 1 1 1 1 1 U Vd 1 0 1 sz op 1 i 0 imm4 @ set uint8_t td = (u << 2) + op + 1@ td=0b001=0b010=0b101 const char* Td Td,"S16","U16","S32","U32"@ set imm5 = (16 << op) - (imm5 >> 4) - ((imm5 & 0xF) << 1)@ @ VCVT<c>.\Td\.F\(size ? "64" : "32")\ <Dd>, <Dd>, #<imm>
+INVALIDATE <32>
@@ -40,6 +40,7 @@ const char* DumpSection(Elf32_Shdr *s, char* SST) {
        GO(SHT_HIPROC);
        GO(SHT_LOUSER);
        GO(SHT_HIUSER);
+        #ifdef SHT_GNU_versym
        GO(SHT_GNU_versym);
        GO(SHT_GNU_ATTRIBUTES);
        GO(SHT_GNU_HASH);
@@ -51,6 +52,7 @@ const char* DumpSection(Elf32_Shdr *s, char* SST) {
        GO(SHT_SUNW_syminfo);
        GO(SHT_GNU_verdef);
        GO(SHT_GNU_verneed);
+        #endif
        #undef GO
        default:
            sprintf(buff, "0x%X unknown type", s->sh_type);
@@ -98,6 +100,7 @@ const char* DumpDynamic(Elf32_Dyn *s) {
            GO(DT_RUNPATH, 0);
            GO(DT_FLAGS, 0);
            GO(DT_ENCODING, 0);
+            #ifdef DT_NUM
            GO(DT_NUM, 0);
            GO(DT_VALRNGLO, 0);
            GO(DT_GNU_PRELINKED, 0);
@@ -133,6 +136,7 @@ const char* DumpDynamic(Elf32_Dyn *s) {
            GO(DT_VERNEEDNUM, 0);
            GO(DT_AUXILIARY, 0);
            GO(DT_FILTER, 0);
+            #endif
        #undef GO
        default:
            sprintf(buff, "0x%X unknown type", s->d_tag);
@@ -154,11 +158,13 @@ const char* DumpPHEntry(Elf32_Phdr *e)
        GO(PT_SHLIB);
        GO(PT_PHDR);
        GO(PT_TLS);
+        #ifdef PT_NUM
        GO(PT_NUM);
        GO(PT_LOOS);
        GO(PT_GNU_EH_FRAME);
        GO(PT_GNU_STACK);
        GO(PT_GNU_RELRO);
+        #endif
        #undef GO
        default: sprintf(buff, "type: %x, Off=%x vaddr=%p paddr=%p filesz=%u memsz=%u flags=%x align=%u", e->p_type, e->p_offset, (void*)e->p_vaddr, (void*)e->p_paddr, e->p_filesz, e->p_memsz, e->p_flags, e->p_align); break;
    }
@@ -284,6 +290,22 @@ void DumpDynamicNeeded(elfheader_t *h)
    }
 }

+void DumpDynamicRPath(elfheader_t *h)
+{
+    if(box86_log>=LOG_DUMP && h->DynStrTab) {
+        printf_log(LOG_DUMP, "ELF Dump DT_RPATH/DT_RUNPATH=====\n");
+        for (int i=0; i<h->numDynamic; ++i) {
+            if(h->Dynamic[i].d_tag==DT_RPATH) {
+                printf_log(LOG_DUMP, "   RPATH : %s\n", h->DynStrTab+h->Dynamic[i].d_un.d_val + h->delta);
+            }
+            if(h->Dynamic[i].d_tag==DT_RUNPATH) {
+                printf_log(LOG_DUMP, " RUNPATH : %s\n", h->DynStrTab+h->Dynamic[i].d_un.d_val + h->delta);
+            }
+        }
+        printf_log(LOG_DUMP, "=====ELF Dump DT_RPATH/DT_RUNPATH\n");
+    }
+}
+
 void DumpRelTable(elfheader_t *h, int cnt, Elf32_Rel *rel, const char* name)
 {
    if(box86_log>=LOG_DUMP) {
@@ -5,10 +5,14 @@
 typedef struct dynablocklist_s dynablocklist_t;
 #endif

+typedef struct library_s library_t;
+typedef struct needed_libs_s needed_libs_t;
+
 #include <pthread.h>

 struct elfheader_s {
    char*       name;
+    char*       path;   // Resolved path to file
    int         numPHEntries;
    Elf32_Phdr  *PHEntries;
    int         numSHEntries;
@@ -48,7 +52,12 @@ struct elfheader_s {
    int         pltent;
    uint32_t    pltrel;
    uintptr_t   gotplt;
+    uintptr_t   gotplt_end;
+    uintptr_t   pltgot;
    uintptr_t   got;
+    uintptr_t   got_end;
+    uintptr_t   plt;
+    uintptr_t   plt_end;
    uintptr_t   text;
    int         textsz;

@@ -67,9 +76,13 @@ struct elfheader_s {
    int         fini_done;

    char*       memory; // char* and not void* to allow math on memory pointer
-#ifdef DYNAREC
-    dynablocklist_t *blocks;
-#endif
+    void**      multiblock;
+    uintptr_t*  multiblock_offs;
+    uint32_t*   multiblock_size;
+    int         multiblock_n;
+
+    library_t   *lib;
+    needed_libs_t *neededlibs;
 };

 #define R_386_NONE	0
@@ -1,3 +1,4 @@
+#define _GNU_SOURCE
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
@@ -23,7 +24,7 @@ int LoadSH(FILE *f, Elf32_Shdr *s, void** SH, const char* name, uint32_t type)
        printf_log(LOG_INFO, "Section Header \"%s\" (off=%d, size=%d) has size (not multiple of %d)\n", name, s->sh_offset, s->sh_size, sizeof(Elf32_Sym));
    }
    *SH = calloc(1, s->sh_size);
-    fseek(f, s->sh_offset ,SEEK_SET);
+    fseeko64(f, s->sh_offset ,SEEK_SET);
    if(fread(*SH, s->sh_size, 1, f)!=1) {
            printf_log(LOG_INFO, "Cannot read Section Header \"%s\" (off=%d, size=%d)\n", name, s->sh_offset, s->sh_size);
            return -1;
@@ -60,8 +61,9 @@ void LoadNamedSection(FILE *f, Elf32_Shdr *s, int size, char* SHStrTab, const ch
 elfheader_t* ParseElfHeader(FILE* f, const char* name, int exec)
 {
    Elf32_Ehdr header;
+    int level = (exec)?LOG_INFO:LOG_DEBUG;
    if(fread(&header, sizeof(Elf32_Ehdr), 1, f)!=1) {
-        printf_log(LOG_INFO, "Cannot read ELF Header\n");
+        printf_log(level, "Cannot read ELF Header\n");
        return NULL;
    }
    if(memcmp(header.e_ident, ELFMAG, SELFMAG)!=0) {
@@ -69,11 +71,15 @@ elfheader_t* ParseElfHeader(FILE* f, const char* name, int exec)
        return NULL;
    }
    if(header.e_ident[EI_CLASS]!=ELFCLASS32) {
-        printf_log(LOG_INFO, "Not an 32bits ELF (%d)\n", header.e_ident[EI_CLASS]);
+        if(header.e_ident[EI_CLASS]==ELFCLASS64) {
+            printf_log(LOG_INFO, "This is a 64bits ELF! box86 can only run 32bits ELF!\n");
+        } else {
+            printf_log(LOG_INFO, "Not a 32bits ELF (%d)\n", header.e_ident[EI_CLASS]);
+        }
        return NULL;
    }
    if(header.e_ident[EI_DATA]!=ELFDATA2LSB) {
-        printf_log(LOG_INFO, "Not an LittleEndian ELF (%d)\n", header.e_ident[EI_DATA]);
+        printf_log(LOG_INFO, "Not a LittleEndian ELF (%d)\n", header.e_ident[EI_DATA]);
        return NULL;
    }
    if(header.e_ident[EI_VERSION]!=EV_CURRENT) {
@@ -91,7 +97,7 @@ elfheader_t* ParseElfHeader(FILE* f, const char* name, int exec)
    }

    if(header.e_machine != EM_386) {
-        printf_log(LOG_INFO, "Not an i386 ELF (%d)\n", header.e_machine);
+        printf_log(level, "Not an i386 ELF (%d)\n", header.e_machine);
        return NULL;
    }

@@ -114,12 +120,12 @@ elfheader_t* ParseElfHeader(FILE* f, const char* name, int exec)
    h->numPHEntries = header.e_phnum;
    h->numSHEntries = header.e_shnum;
    h->SHIdx = header.e_shstrndx;
-    if(header.e_shentsize!=0) {
+    if(header.e_shentsize && header.e_shnum) {
        // special cases for nums
        if(h->numSHEntries == 0) {
            printf_log(LOG_DEBUG, "Read number of Sections in 1st Section\n");
            // read 1st section header and grab actual number from here
-            fseek(f, header.e_shoff, SEEK_SET);
+            fseeko64(f, header.e_shoff, SEEK_SET);
            Elf32_Shdr section;
            if(fread(&section, sizeof(Elf32_Shdr), 1, f)!=1) {
                free(h);
@@ -131,7 +137,7 @@ elfheader_t* ParseElfHeader(FILE* f, const char* name, int exec)
        // now read all section headers
        printf_log(LOG_DEBUG, "Read %d Section header\n", h->numSHEntries);
        h->SHEntries = (Elf32_Shdr*)calloc(h->numSHEntries, sizeof(Elf32_Shdr));
-        fseek(f, header.e_shoff ,SEEK_SET);
+        fseeko64(f, header.e_shoff ,SEEK_SET);
        if(fread(h->SHEntries, sizeof(Elf32_Shdr), h->numSHEntries, f)!=h->numSHEntries) {
                FreeElfHeader(&h);
                printf_log(LOG_INFO, "Cannot read all Section Header\n");
@@ -147,14 +153,14 @@ elfheader_t* ParseElfHeader(FILE* f, const char* name, int exec)

    printf_log(LOG_DEBUG, "Read %d Program header\n", h->numPHEntries);
    h->PHEntries = (Elf32_Phdr*)calloc(h->numPHEntries, sizeof(Elf32_Phdr));
-    fseek(f, header.e_phoff ,SEEK_SET);
+    fseeko64(f, header.e_phoff ,SEEK_SET);
    if(fread(h->PHEntries, sizeof(Elf32_Phdr), h->numPHEntries, f)!=h->numPHEntries) {
            FreeElfHeader(&h);
            printf_log(LOG_INFO, "Cannot read all Program Header\n");
            return NULL;
    }

-    if(header.e_shentsize!=0) {
+    if(header.e_shentsize && header.e_shnum) {
        if(h->SHIdx == SHN_XINDEX) {
            printf_log(LOG_DEBUG, "Read number of String Table in 1st Section\n");
            h->SHIdx = h->SHEntries[0].sh_link;
@@ -194,6 +200,8 @@ elfheader_t* ParseElfHeader(FILE* f, const char* name, int exec)
                    h->relasz = h->Dynamic[i].d_un.d_val;
                else if(h->Dynamic[i].d_tag == DT_RELAENT)
                    h->relaent = h->Dynamic[i].d_un.d_val;
+                else if(h->Dynamic[i].d_tag == DT_PLTGOT)
+                    h->pltgot = h->Dynamic[i].d_un.d_val;
                else if(h->Dynamic[i].d_tag == DT_PLTREL)
                    h->pltrel = h->Dynamic[i].d_un.d_val;
                else if(h->Dynamic[i].d_tag == DT_PLTRELSZ)
@@ -246,12 +254,20 @@ elfheader_t* ParseElfHeader(FILE* f, const char* name, int exec)
        int ii = FindSection(h->SHEntries, h->numSHEntries, h->SHStrTab, ".got.plt");
        if(ii) {
            h->gotplt = h->SHEntries[ii].sh_addr;
+            h->gotplt_end = h->gotplt + h->SHEntries[ii].sh_size;
            printf_log(LOG_DEBUG, "The GOT.PLT Table is at address %p\n", (void*)h->gotplt);
        }
        ii = FindSection(h->SHEntries, h->numSHEntries, h->SHStrTab, ".got");
        if(ii) {
            h->got = h->SHEntries[ii].sh_addr;
-            printf_log(LOG_DEBUG, "The GOT Table is at address %p\n", (void*)h->got);
+            h->got_end = h->got + h->SHEntries[ii].sh_size;
+            printf_log(LOG_DEBUG, "The GOT Table is at address %p..%p\n", (void*)h->got, (void*)h->got_end);
+        }
+        ii = FindSection(h->SHEntries, h->numSHEntries, h->SHStrTab, ".plt");
+        if(ii) {
+            h->plt = h->SHEntries[ii].sh_addr;
+            h->plt_end = h->plt + h->SHEntries[ii].sh_size;
+            printf_log(LOG_DEBUG, "The PLT Table is at address %p..%p\n", (void*)h->plt, (void*)h->plt_end);
        }
        // look for .init entry point
        ii = FindSection(h->SHEntries, h->numSHEntries, h->SHStrTab, ".init");
@@ -47,10 +47,60 @@
        base+=(nextop&0x80)?(F32S):(F8S); \
        A = (T*)(base+O); \
    }
+
+#define  getecommon16(A, T)                     \
+    {                                           \
+        uint32_t m = nextop&0xC7;               \
+        uint32_t base = 0;                      \
+        switch(m&7) {                           \
+            case 0: base = R_BX+R_SI; break;    \
+            case 1: base = R_BX+R_DI; break;    \
+            case 2: base = R_BP+R_SI; break;    \
+            case 3: base = R_BP+R_DI; break;    \
+            case 4: base =      R_SI; break;    \
+            case 5: base =      R_DI; break;    \
+            case 6: base =      R_BP; break;    \
+            case 7: base =      R_BX; break;    \
+        }                                       \
+        switch((m>>6)&3) {                      \
+            case 0: if(m==6) base = F16; break; \
+            case 1: base += F8S; break;         \
+            case 2: base += F16S; break;        \
+        }                                       \
+        A =  (T*)base;                          \
+    }
+
+#define  getecommon16o(A, T, O)                 \
+    {                                           \
+        uint32_t m = nextop&0xC7;               \
+        uint32_t base = 0;                      \
+        switch(m&7) {                           \
+            case 0: base = R_BX+R_SI; break;    \
+            case 1: base = R_BX+R_DI; break;    \
+            case 2: base = R_BP+R_SI; break;    \
+            case 3: base = R_BP+R_DI; break;    \
+            case 4: base =      R_SI; break;    \
+            case 5: base =      R_DI; break;    \
+            case 6: base =      R_BP; break;    \
+            case 7: base =      R_BX; break;    \
+        }                                       \
+        switch((m>>6)&3) {                      \
+            case 0: if(m==6) base = F16; break; \
+            case 1: base += F8S; break;         \
+            case 2: base += F16S; break;        \
+        }                                       \
+        A =  (T*)(base+O);                      \
+    }
+
+
 #define geteb(A) \
    if((nextop&0xC0)==0xC0) { \
        A = (reg32_t*)&emu->regs[(nextop&3)].byte[((nextop&0x4)>>2)]; \
    } else getecommon(A, reg32_t)
+#define getebo(A, O)          \
+    if((nextop&0xC0)==0xC0) { \
+        A = (reg32_t*)&emu->regs[(nextop&3)].byte[((nextop&0x4)>>2)]; \
+    } else getecommono(A, reg32_t, O)
 #define geted(A) \
    if((nextop&0xC0)==0xC0) { \
        A = &emu->regs[(nextop&7)]; \
@@ -67,12 +117,24 @@
    if((nextop&0xC0)==0xC0) { \
        A = &emu->xmm[(nextop&7)]; \
    } else getecommon(A, sse_regs_t)
+#define getew16(A)  \
+    if((nextop&0xC0)==0xC0) { \
+        A = &emu->regs[(nextop&7)]; \
+    } else getecommon16(A, reg32_t)
+#define getew16o(A, O)              \
+    if((nextop&0xC0)==0xC0) {       \
+        A = &emu->regs[(nextop&7)]; \
+    } else getecommon16o(A, reg32_t, O)
+
 // Macros for ModR/M gets
 #define GET_EB      geteb(oped)
 #define GET_ED      geted(oped)
 #define GET_ED_OFFS(o) getedo(oped, o)
+#define GET_EB_OFFS(o) getebo(oped, o)
 #define GET_EM      getem(opem)
 #define GET_EX      getex(opex)
+#define GET_EW16    getew16(oped)
+#define GET_EW16_OFFS(o)    getew16o(oped, o)
 #define EB          oped
 #define ED          oped
 #define EM          opem
@@ -84,5 +146,6 @@

 // Alias
 #define GET_EW      GET_ED
+#define GET_EW_OFFS GET_ED_OFFS
 #define EW          ED
 #define GW          GD
@@ -1,5 +1,33 @@
    opcode = F8;
    goto *opcodes0f[opcode];
+        _0f_0x00:                       /* VERx Ed */
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 4: //VERR
+                case 5: //VERW
+                    GET_EW;
+                    if(!EW->word[0])
+                        CLEAR_FLAG(F_ZF);
+                    else
+                        SET_FLAG(F_ZF); // should test if selector is ok
+                    break;
+                default:
+                    goto _default;
+            }
+            NEXT;
+        _0f_0x01:                      
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 4:                 /* SMSW Ew */
+                    GET_ED;
+                    // dummy for now... Do I need to track CR0 state?
+                    ED->word[0] = (1<<0) | (1<<4); // only PE and ET set...
+                    break;
+                default:
+                    goto _default;
+            }
+            NEXT;
+
        _0f_0x0B:                      /* UD2 */
            kill(getpid(), SIGILL);              // this is undefined instruction
            NEXT;
@@ -54,7 +82,27 @@
        _0f_0x18:                       /* PREFETCHh Ed */
            nextop = F8;
            GET_ED;
-            __builtin_prefetch((void*)ED->dword[0], 0, 0); // inoring wich level of cache (roughly (nextop>>3)&7)
+            if((nextop&0xC0)==0xC0) {
+            } else
+            switch((nextop>>3)&7) {
+                case 0: //PREFETCHnta
+                case 1: //PREFETCH1
+                case 2: //PREFETCH2
+                case 3: //PREFETCH3
+                    __builtin_prefetch((void*)ED, 0, 0); // ignoring wich level of cache
+                    break;
+                default:    //NOP
+                    break;
+            }
+            NEXT;
+
+        _0f_0x1A:                      /* NOP (multi-byte) / ignored BNDLDX */
+            nextop = F8;
+            GET_ED;
+            NEXT;
+        _0f_0x1B:                      /* NOP (multi-byte) / ignored BNDSTX */
+            nextop = F8;
+            GET_ED;
            NEXT;

        _0f_0x1F:                      /* NOP (multi-byte) */
@@ -139,6 +187,64 @@
            R_EAX = tmp64u&0xFFFFFFFF;
            NEXT;
        
+        _0f_0x38:  // these are some SSE3 opcodes
+            opcode = F8;
+            switch(opcode) {
+                case 0x00:  /* PSHUFB */
+                    nextop = F8;
+                    GET_EM;
+                    eam1 = GM;
+                    for (int i=0; i<8; ++i) {
+                        if(EM->ub[i]&128)
+                            GM.ub[i] = 0;
+                        else
+                            GM.ub[i] = eax1.ub[EM->ub[i]&7];
+                    }
+                    break;
+                case 0x04:  /* PMADDUBSW Gm,Em */
+                    nextop = F8;
+                    GET_EM;
+                    for (int i=0; i<4; ++i) {
+                        tmp32s = (int32_t)(GM.ub[i*2+0])*EM->sb[i*2+0] + (int32_t)(GM.ub[i*2+1])*EM->sb[i*2+1];
+                        GM.sw[i] = (tmp32s>32767)?32767:((tmp32s<-32768)?-32768:tmp32s);
+                    }
+                    break;
+                case 0x0B:  /* PMULHRSW Gm, Em */
+                    nextop = F8;
+                    GET_EM;
+                    for (int i=0; i<4; ++i) {
+                        tmp32s = ((((int32_t)(GM.sw[i])*(int32_t)(EM->sw[i]))>>14) + 1)>>1;
+                        GM.uw[i] = tmp32s&0xffff;
+                    }
+                    break;
+
+                case 0x1C:  /* PABSB Gm, Em */
+                    nextop = F8;
+                    GET_EM;
+                    for (int i=0; i<8; ++i) {
+                        GM.sb[i] = abs(EM->sb[i]);
+                    }
+                    break;
+                case 0x1D:  /* PABSW Gm, Em */
+                    nextop = F8;
+                    GET_EM;
+                    for (int i=0; i<4; ++i) {
+                        GM.sw[i] = abs(EM->sw[i]);
+                    }
+                    break;
+                case 0x1E:  /* PABSD Gm, Em */
+                    nextop = F8;
+                    GET_EM;
+                    for (int i=0; i<2; ++i) {
+                        GM.sd[i] = abs(EM->sd[i]);
+                    }
+                    break;
+
+                default:
+                    goto _default;
+            }
+            NEXT;
+            
        #define GOCOND(BASE, PREFIX, CONDITIONAL) \
        _0f_##BASE##_0:                          \
            PREFIX                              \
@@ -571,95 +677,16 @@
            EM->q = GM.q;
            NEXT;

+        _0f_0xA0:                      /* PUSH FS */
+            Push(emu, emu->segs[_FS]);    // even if a segment is a 16bits, a 32bits push/pop is done
+            NEXT;
+        _0f_0xA1:                      /* POP FS */
+            emu->segs[_FS] = Pop(emu);    // no check, no use....
+            emu->segs_serial[_FS] = 0;
+            NEXT;
        _0f_0xA2:                      /* CPUID */
            tmp32u = R_EAX;
-            switch(tmp32u) {
-                case 0x0:
-                    // emulate a P4
-                    R_EAX = 0x80000004;
-                    // return GenuineIntel
-                    R_EBX = 0x756E6547;
-                    R_EDX = 0x49656E69;
-                    R_ECX = 0x6C65746E;
-                    break;
-                case 0x1:
-                    R_EAX = 0x00000101; // familly and all
-                    R_EBX = 0;          // Brand indexe, CLFlush, Max APIC ID, Local APIC ID
-                    R_EDX =   1         // fpu 
-                            | 1<<8      // cmpxchg8
-                            | 1<<11     // sep (sysenter & sysexit)
-                            | 1<<15     // cmov
-                            | 1<<19     // clflush (seems to be with SSE2)
-                            | 1<<23     // mmx
-                            //| 1<<24     // fxsr (fxsave, fxrestore)
-                            | 1<<25     // SSE
-                            | 1<<26     // SSE2
-                            ;
-                    R_ECX =   1<<12     // fma
-                            | 1<<13     // cx16 (cmpxchg16)
-                            ;           // also 1<<0 is SSE3 and 1<<9 is SSSE3
-                    break;
-                case 0x2:   // TLB and Cache info. Sending 1st gen P4 info...
-                    R_EAX = 0x665B5001;
-                    R_EBX = 0x00000000;
-                    R_ECX = 0x00000000;
-                    R_EDX = 0x007A7000;
-                    break;
-                
-                case 0x4:   // Cache info
-                    switch (R_ECX) {
-                        case 0: // L1 data cache
-                            R_EAX = (1 | (1<<5) | (1<<8));   //type
-                            R_EBX = (63 | (7<<22)); // size
-                            R_ECX = 63;
-                            R_EDX = 1;
-                            break;
-                        case 1: // L1 inst cache
-                            R_EAX = (2 | (1<<5) | (1<<8)); //type
-                            R_EBX = (63 | (7<<22)); // size
-                            R_ECX = 63;
-                            R_EDX = 1;
-                            break;
-                        case 2: // L2 cache
-                            R_EAX = (3 | (2<<5) | (1<<8)); //type
-                            R_EBX = (63 | (15<<22));    // size
-                            R_ECX = 4095;
-                            R_EDX = 1;
-                            break;
-
-                        default:
-                            R_EAX = 0x00000000;
-                            R_EBX = 0x00000000;
-                            R_ECX = 0x00000000;
-                            R_EDX = 0x00000000;
-                            break;
-                    }
-                    break;
-                case 0x5:   //mwait info
-                    R_EAX = 0;
-                    R_EBX = 0;
-                    R_ECX = 1 | 2;
-                    R_EDX = 0;
-                    break;
-                case 0x6:   // thermal
-                case 0x9:   // direct cache access
-                case 0xA:   // Architecture performance monitor
-                    R_EAX = 0;
-                    R_EBX = 0;
-                    R_ECX = 0;
-                    R_EDX = 0;
-                    break;
-                case 0x7:   // extended bits...
-                    /*if(R_ECX==0)    R_EAX = 0;
-                    else*/ R_EAX = R_ECX = R_EBX = R_EDX = 0;
-                    break;
-
-                case 0x80000000:        // max extended
-                    break;              // no extended, so return same value as beeing the max value!
-                default:
-                    printf_log(LOG_INFO, "Warning, CPUID command %X unsupported (ECX=%08x)\n", tmp32u, R_ECX);
-                    R_EAX = 0;
-            }
+            my_cpuid(emu, tmp32u);
            NEXT;
        _0f_0xA3:                      /* BT Ed,Gd */
            CHECK_FLAGS(emu);
@@ -684,6 +711,15 @@
            ED->dword[0] = shld32(emu, ED->dword[0], GD.dword[0], tmp8u);
            NEXT;

+        _0f_0xA8:                      /* PUSH GS */
+            Push(emu, emu->segs[_GS]);    // even if a segment is a 16bits, a 32bits push/pop is done
+            NEXT;
+        _0f_0xA9:                      /* POP GS */
+            emu->segs[_GS] = Pop(emu);
+            emu->segs_serial[_GS] = 0;
+            NEXT;
+
+
        _0f_0xAB:                      /* BTS Ed,Gd */
            CHECK_FLAGS(emu);
            nextop = F8;
@@ -725,16 +761,23 @@
                case 0:                 /* FXSAVE m512byte */
                    // should save flags & all
                    // copy MMX regs...
-                    memcpy(ED->dword+32/4, &emu->mmx[0], sizeof(emu->mmx));
+                    for(int i=0; i<8; ++i)
+                        memcpy(((void*)(ED))+32+i*16, &emu->mmx[0], sizeof(emu->mmx[0]));
                    // copy SSE regs
-                    memcpy(ED->dword+160/4, &emu->xmm[0], sizeof(emu->xmm));
+                    memcpy(((void*)(ED))+160, &emu->xmm[0], sizeof(emu->xmm));
+                    // put also FPU regs in a reserved area...
+                    for(int i=0; i<8; ++i)
+                        memcpy(((void*)(ED))+416+i*8, &emu->fpu[0], sizeof(emu->fpu[0]));
                    break;
                case 1:                 /* FXRSTOR m512byte */
                    // should restore flags & all
-                    // copy MMX regs...
-                    memcpy(&emu->mmx[0], ED->dword+32/4, sizeof(emu->mmx));
+                    // copy back MMX regs...
+                    for(int i=0; i<8; ++i)
+                        memcpy(&emu->mmx[i], ((void*)(ED))+32+i*16, sizeof(emu->mmx[0]));
                    // copy SSE regs
-                    memcpy(&emu->xmm[0], ED->dword+160/4, sizeof(emu->xmm));
+                    memcpy(&emu->xmm[0], ((void*)(ED))+160/4, sizeof(emu->xmm));
+                    for(int i=0; i<8; ++i)
+                        memcpy(&emu->fpu[0], ((void*)(ED))+416+i*8, sizeof(emu->fpu[0]));
                    break;
                case 2:                 /* LDMXCSR Md */
                    emu->mxcsr = ED->dword[0];
@@ -818,6 +861,22 @@
                    else
                        CLEAR_FLAG(F_CF);
                    break;
+                case 5:             /* BTS Ed, Ib */
+                    CHECK_FLAGS(emu);
+                    GET_ED;
+                    tmp8u = F8;
+                    if((nextop&0xC0)!=0xC0)
+                    {
+                        ED=(reg32_t*)(((uint32_t*)(ED))+(tmp8u>>5));
+                    }
+                    tmp8u&=31;
+                    if(ED->dword[0] & (1<<tmp8u)) {
+                        SET_FLAG(F_CF);
+                    } else {
+                        ED->dword[0] ^= (1<<tmp8u);
+                        CLEAR_FLAG(F_CF);
+                    }
+                    break;
                case 6:             /* BTR Ed, Ib */
                    CHECK_FLAGS(emu);
                    GET_ED;
@@ -833,6 +892,21 @@
                    } else
                        CLEAR_FLAG(F_CF);
                    break;
+                case 7:             /* BTC Ed, Ib */
+                    CHECK_FLAGS(emu);
+                    GET_ED;
+                    tmp8u = F8;
+                    if((nextop&0xC0)!=0xC0)
+                    {
+                        ED=(reg32_t*)(((uint32_t*)(ED))+(tmp8u>>5));
+                    }
+                    tmp8u&=31;
+                    if(ED->dword[0] & (1<<tmp8u))
+                        SET_FLAG(F_CF);
+                    else
+                        CLEAR_FLAG(F_CF);
+                    ED->dword[0] ^= (1<<tmp8u);
+                    break;

                default:
                    goto _default;
@@ -926,7 +1000,11 @@
                GX.ud[i]=(tmp8s)?0xffffffff:0;
            }
            NEXT;
-
+        _0f_0xC3:                       /* MOVNTI Ed,Gd */
+            nextop = F8;
+            GET_ED;
+            ED->dword[0] = GD.dword[0];
+            NEXT;
        _0f_0xC4:                       /* PINSRW Gm,Ew,Ib */
            nextop = F8;
            GET_ED;
@@ -1021,6 +1099,17 @@
            }
            NEXT;

+        _0f_0xD7:                   /* PMOVMSKB Gd,Em */
+            nextop = F8;
+            if((nextop&0xC0)==0xC0) {
+                GET_EM;
+                GD.dword[0] = 0;
+                for (int i=0; i<8; ++i)
+                    if(EM->ub[i]&0x80)
+                        GD.dword[0] |= (1<<i);
+                NEXT;
+            } else
+                goto _default;
        _0f_0xD8:                   /* PSUBUSB Gm,Em */
            nextop = F8;
            GET_EM;
@@ -1037,7 +1126,12 @@
                GM.uw[i] = (tmp32s < 0) ? 0 : tmp32s;
            }
            NEXT;
-
+        _0f_0xDA:                   /* PMINUB Gm,Em */
+            nextop = F8;
+            GET_EM;
+            for (int i=0; i<8; ++i)
+                GM.ub[i] = (GM.ub[i]<EM->ub[i])?GM.ub[i]:EM->ub[i];
+            NEXT;
        _0f_0xDB:                   /* PAND Gm,Em */
            nextop = F8;
            GET_EM;
@@ -1059,7 +1153,12 @@
                GM.uw[i] = (tmp32u>65535) ? 65535 : tmp32u;
            }
            NEXT;
-
+        _0f_0xDE:                   /* PMAXUB Gm,Em */
+            nextop = F8;
+            GET_EM;
+            for (int i=0; i<8; ++i)
+                GM.ub[i] = (GM.ub[i]>EM->ub[i])?GM.ub[i]:EM->ub[i];
+            NEXT;
        _0f_0xDF:                   /* PANDN Gm,Em */
            nextop = F8;
            GET_EM;
@@ -1119,6 +1218,13 @@
            }
            NEXT;

+        _0f_0xE7:                   /* MOVNTQ Em,Gm */
+            nextop = F8;
+            if((nextop&0xC0)==0xC0)
+                goto _default;
+            GET_EM;
+            EM->q = GM.q;
+            NEXT;
        _0f_0xE8:                   /* PSUBSB Gm,Em */
            nextop = F8;
            GET_EM;
@@ -1135,7 +1241,12 @@
                GM.sw[i] = (tmp32s>32767)?32767:((tmp32s<-32768)?-32768:tmp32s);
            }
            NEXT;
-
+        _0f_0xEA:                   /* PMINSW Gm,Em */
+            nextop = F8;
+            GET_EM;
+            for (int i=0; i<4; ++i)
+                GM.sw[i] = (GM.sw[i]<EM->sw[i])?GM.sw[i]:EM->sw[i];
+            NEXT;
        _0f_0xEB:                   /* POR Gm, Em */
            nextop = F8;
            GET_EM;
@@ -1157,7 +1268,12 @@
                GM.sw[i] = (tmp32s>32767)?32767:((tmp32s<-32768)?-32768:tmp32s);
            }
            NEXT;
-
+        _0f_0xEE:                   /* PMAXSW Gm,Em */
+            nextop = F8;
+            GET_EM;
+            for (int i=0; i<4; ++i)
+                GM.sw[i] = (GM.sw[i]>EM->sw[i])?GM.sw[i]:EM->sw[i];
+            NEXT;
        _0f_0xEF:                   /* PXOR Gm, Em */
            nextop = F8;
            GET_EM;
@@ -1215,7 +1331,15 @@
                tmp32u += (GM.ub[i]>EM->ub[i])?(GM.ub[i] - EM->ub[i]):(EM->ub[i] - GM.ub[i]);
            GM.q = tmp32u;
            NEXT;
-
+        _0f_0xF7:                   /* MASKMOVQ Gm, Em */
+            nextop = F8;
+            if((nextop&0xC0)==0xC0) {
+                GET_EM;
+                for (int i=0; i<8; ++i)
+                    if(EM->ub[i]&0x80) ((uint8_t*)(R_EDI))[i] = GM.ub[i];
+            } else
+                goto _default;
+            NEXT;
        _0f_0xF8:                   /* PSUBB Gm,Em */
            nextop = F8;
            GET_EM;
@@ -2,16 +2,29 @@
    goto *opcodes66[opcode];

    #define GO(B, OP)                       \
+    _66_##B##_0: \
+        nextop = F8;               \
+        GET_EB;             \
+        EB->byte[0] = OP##8(emu, EB->byte[0], GB);  \
+        NEXT;                              \
    _66_##B##_1:                               \
        nextop = F8;                \
        GET_EW;                   \
        EW->word[0] = OP##16(emu, EW->word[0], GW.word[0]); \
        NEXT;                              \
+    _66_##B##_2: \
+        nextop = F8;               \
+        GET_EB;                   \
+        GB = OP##8(emu, GB, EB->byte[0]); \
+        NEXT;                              \
    _66_##B##_3:                               \
        nextop = F8;                \
        GET_EW;                   \
        GW.word[0] = OP##16(emu, GW.word[0], EW->word[0]); \
        NEXT;                              \
+    _66_##B##_4: \
+        R_AL = OP##8(emu, R_AL, F8); \
+        NEXT;                              \
    _66_##B##_5:                               \
        R_AX = OP##16(emu, R_AX, F16); \
        NEXT;
@@ -30,17 +43,36 @@
        NEXT;
    _66_0x07:                      /* POP ES */
        emu->segs[_ES] = Pop16(emu);    // no check, no use....
+        emu->segs_serial[_ES] = 0;
        NEXT;

    _66_0x0F:                      /* 66 0f prefix */
-        #include "run660f.h"
+        emu->old_ip = R_EIP;
+        R_EIP = ip-2;   // don't count 66 0F yet
+        Run660F(emu); // implemented in Run660f.c
+        ip = R_EIP;
+        if(emu->quit) goto fini;
+        STEP
+        NEXT;
+
+    _66_0x1F:                      /* POP DS */
+        emu->segs[_DS] = Pop16(emu);    // no check, no use....
+        emu->segs_serial[_DS] = 0;
+        NEXT;
        
    _66_0x26:                      /* ES: */
        // ignored
-        NEXT;
+        opcode = F8;
+        goto *opcodes66[opcode];
    _66_0x2E:                      /* CS: */
        // ignored
-        NEXT;
+        opcode = F8;
+        goto *opcodes66[opcode];
+    _66_0x36:                      /* SS: */
+        // ignored
+        opcode = F8;
+        goto *opcodes66[opcode];
+
    _66_0x39:
        nextop = F8;
        GET_EW;
@@ -99,6 +131,27 @@
        tmp8u = opcode&7;
        emu->regs[tmp8u].word[0] = Pop16(emu);
        NEXT;
+    _66_0x60:                              /* PUSHA */
+        tmp16u = R_SP;
+        Push16(emu, R_AX);
+        Push16(emu, R_CX);
+        Push16(emu, R_DX);
+        Push16(emu, R_BX);
+        Push16(emu, tmp16u);
+        Push16(emu, R_BP);
+        Push16(emu, R_SI);
+        Push16(emu, R_DI);
+        NEXT;
+    _66_0x61:                              /* POPA */
+        R_DI = Pop16(emu);
+        R_SI = Pop16(emu);
+        R_BP = Pop16(emu);
+        R_ESP+=2;   // POP ESP
+        R_BX = Pop16(emu);
+        R_DX = Pop16(emu);
+        R_CX = Pop16(emu);
+        R_AX = Pop16(emu);
+        NEXT;

    _66_0x66:
        goto _0x66; // 0x66 0x66 => can remove one 0x66
@@ -174,13 +227,14 @@
    _66_0x8C:                              /* MOV Ew,Seg */
        nextop = F8;
        GET_EW;
-        EW->word[0] = emu->segs[(nextop&38)>>3];
+        EW->word[0] = emu->segs[(nextop&0x38)>>3];
        NEXT;
    
    _66_0x8E:                               /* MOV Seg,Ew */
        nextop = F8;
        GET_EW;
        emu->segs[((nextop&0x38)>>3)] = EW->word[0];
+        emu->segs_serial[((nextop&0x38)>>3)] = 0;
        NEXT;
    _66_0x8F:                              /* POP Ew */
        nextop = F8;
@@ -190,10 +244,16 @@
    _66_0x90:                              /* NOP */
        NEXT;

-    _66_0x92:                              /* XCHG DX,AX */
+    _66_0x91:
+    _66_0x92:
+    _66_0x93:
+    _66_0x94:
+    _66_0x95:
+    _66_0x96:
+    _66_0x97:                      /* XCHG reg,EAX */
        tmp16u = R_AX;
-        R_AX = R_DX;
-        R_DX = tmp16u;
+        R_AX = emu->regs[opcode&7].word[0];
+        emu->regs[opcode&7].word[0] = tmp16u;
        NEXT;

    _66_0x98:                               /* CBW */
@@ -205,8 +265,12 @@

    _66_0x9C:                              /* PUSHFW */
        CHECK_FLAGS(emu);
-        PackFlags(emu);
-        Push16(emu, (uint16_t)emu->packed_eflags.x32);
+        Push16(emu, (uint16_t)emu->eflags.x32);
+        NEXT;
+    _66_0x9D:                              /* POPFW */
+        CHECK_FLAGS(emu);
+        emu->eflags.x32 &=0xffff0000;
+        emu->eflags.x32 |= (Pop16(emu) & 0x3F7FD7) | 0x2;
        NEXT;

    _66_0xA1:                              /* MOV AX,Ow */
@@ -284,6 +348,22 @@
        EW->word[0] = F16;
        NEXT;

+    _66_0xCB:                               /* FAR RET */
+        ip = Pop(emu);
+        emu->segs[_CS] = Pop(emu);    // no check, no use....
+        emu->segs_serial[_CS] = 0;
+        // need to check status of CS register!
+        STEP
+        NEXT;
+    _66_0xCC:                              /* INT3 */
+        emu->old_ip = R_EIP;
+        R_EIP = ip-1;
+        if(my_context->signals[SIGTRAP])
+            raise(SIGTRAP);
+        ip = R_EIP;
+        if(emu->quit) goto fini;
+        STEP
+        NEXT;
    _66_0xD1:                              /* GRP2 Ew,1  */
    _66_0xD3:                              /* GRP2 Ew,CL */
        nextop = F8;
@@ -302,21 +382,31 @@
        NEXT;
    
    _66_0xD9:
-        emu->old_ip = old_ip;
+        emu->old_ip = R_EIP;
        R_EIP = ip;
        Run66D9(emu);
        ip = R_EIP;
        if(emu->quit) goto fini;
+        STEP
        NEXT;

    _66_0xDD:
-        emu->old_ip = old_ip;
+        emu->old_ip = R_EIP;
        R_EIP = ip;
        Run66DD(emu);
        ip = R_EIP;
        if(emu->quit) goto fini;
+        STEP
        NEXT;

+    _66_0xF0:                      /* LOCK prefix */
+        emu->old_ip = R_EIP;
+        R_EIP = ip;
+        RunLock66(emu);
+        ip = R_EIP;
+        if(emu->quit) goto fini;
+        STEP
+        NEXT;

    _66_0xF2:                      /* REPNZ prefix */
    _66_0xF3:                      /* REPZ prefix */
@@ -324,6 +414,14 @@
        tmp8s = ACCESS_FLAG(F_DF)?-2:+2;
        tmp32u = R_ECX;
        switch(nextop) {
+            case 0xA4:              /* REP MOVSB */
+                while(tmp32u) {
+                    --tmp32u;
+                    *(uint8_t*)R_EDI = *(uint8_t*)R_ESI;
+                    R_EDI += tmp8s;
+                    R_ESI += tmp8s;
+                }
+                break;
            case 0xA5:              /* REP MOVSW */
                while(tmp32u) {
                    --tmp32u;
@@ -405,6 +503,14 @@
                break;
        }
        NEXT;
+    _66_0xF8:                       /* CLC */
+        CHECK_FLAGS(emu);
+        CLEAR_FLAG(F_CF);
+        NEXT;
+    _66_0xF9:                       /* STC */
+        CHECK_FLAGS(emu);
+        SET_FLAG(F_CF);
+        NEXT;

    _66_0xFF:                      /* GRP 5 Ew */
        nextop = F8;
@@ -416,8 +522,11 @@
            case 1:                 /* DEC Ed */
                EW->word[0] = dec16(emu, EW->word[0]);
                break;
+            case 6:
+                Push16(emu, EW->word[0]);
+                break;
            default:
-                emu->old_ip = old_ip;
+                emu->old_ip = R_EIP;
                R_EIP = ip;
                printf_log(LOG_NONE, "Illegal Opcode 66 %02X %02X\n", opcode, nextop);
                emu->quit=1;
@@ -10,11 +10,7 @@
        case 0xC5:
        case 0xC6:
        case 0xC7:  /* FADD */
-            #ifdef USE_FLOAT
-            ST0.f += ST(nextop&7).f;
-            #else
            ST0.d += ST(nextop&7).d;
-            #endif
            break;
        case 0xC8:
        case 0xC9:
@@ -24,11 +20,7 @@
        case 0xCD:
        case 0xCE:
        case 0xCF:  /* FMUL */
-            #ifdef USE_FLOAT
-            ST0.f *= ST(nextop&7).f;
-            #else
            ST0.d *= ST(nextop&7).d;
-            #endif
            break;
        case 0xD0:
        case 0xD1:
@@ -38,11 +30,7 @@
        case 0xD5:
        case 0xD6:
        case 0xD7:  /* FCOM */
-            #ifdef USE_FLOAT
-            fpu_fcom(emu, ST(nextop&7).f);
-            #else
            fpu_fcom(emu, ST(nextop&7).d);
-            #endif
            break;
        case 0xD8:
        case 0xD9:
@@ -52,11 +40,7 @@
        case 0xDD:
        case 0xDE:
        case 0xDF:  /* FCOMP */
-            #ifdef USE_FLOAT
-            fpu_fcom(emu, ST(nextop&7).f);
-            #else
            fpu_fcom(emu, ST(nextop&7).d);
-            #endif
            fpu_do_pop(emu);
            break;
        case 0xE0:
@@ -67,11 +51,7 @@
        case 0xE5:
        case 0xE6:
        case 0xE7:  /* FSUB */
-            #ifdef USE_FLOAT
-            ST0.f -= ST(nextop&7).f;
-            #else
            ST0.d -= ST(nextop&7).d;
-            #endif
            break;
        case 0xE8:
        case 0xE9:
@@ -81,11 +61,7 @@
        case 0xED:
        case 0xEE:
        case 0xEF:  /* FSUBR */
-            #ifdef USE_FLOAT
-            ST0.f = ST(nextop&7).f - ST0.f;
-            #else
            ST0.d = ST(nextop&7).d - ST0.d;
-            #endif
            break;
        case 0xF0:
        case 0xF1:
@@ -95,11 +71,7 @@
        case 0xF5:
        case 0xF6:
        case 0xF7:  /* FDIV */
-            #ifdef USE_FLOAT
-            ST0.f /= ST(nextop&7).f;
-            #else
            ST0.d /= ST(nextop&7).d;
-            #endif
            break;
        case 0xF8:
        case 0xF9:
@@ -109,46 +81,26 @@
        case 0xFD:
        case 0xFE:
        case 0xFF:  /* FDIVR */
-            #ifdef USE_FLOAT
-            ST0.f = ST(nextop&7).f / ST0.f;
-            #else
            ST0.d = ST(nextop&7).d / ST0.d;
-            #endif
            break;
        default:
        switch((nextop>>3)&7) {
            case 0:         /* FADD ST0, float */
                GET_ED;
                if(!(((uintptr_t)ED)&3))
-                    #ifdef USE_FLOAT
-                    ST0.f += *(float*)ED;
-                    #else
                    ST0.d += *(float*)ED;
-                    #endif
                else {
-                    *(uint32_t*)&f = ED->dword[0];
-                    #ifdef USE_FLOAT
-                    ST0.f += f;
-                    #else
+                    memcpy(&f, ED, sizeof(float));
                    ST0.d += f;
-                    #endif
                }
                break;
            case 1:         /* FMUL ST0, float */
                GET_ED;
                if(!(((uintptr_t)ED)&3))
-                    #ifdef USE_FLOAT
-                    ST0.f *= *(float*)ED;
-                    #else
                    ST0.d *= *(float*)ED;
-                    #endif
                else {
-                    *(uint32_t*)&f = ED->dword[0];
-                    #ifdef USE_FLOAT
-                    ST0.f *= f;
-                    #else
+                    memcpy(&f, ED, sizeof(float));
                    ST0.d *= f;
-                    #endif
                }
                break;
            case 2:      /* FCOM ST0, float */
@@ -156,7 +108,7 @@
                if(!(((uintptr_t)ED)&3))
                    fpu_fcom(emu, *(float*)ED);
                else {
-                    *(uint32_t*)&f = ED->dword[0];
+                    memcpy(&f, ED, sizeof(float));
                    fpu_fcom(emu, f);
                }
                break;
@@ -165,7 +117,7 @@
                if(!(((uintptr_t)ED)&3))
                    fpu_fcom(emu, *(float*)ED);
                else {
-                    *(uint32_t*)&f = ED->dword[0];
+                    memcpy(&f, ED, sizeof(float));
                    fpu_fcom(emu, f);
                }
                fpu_do_pop(emu);
@@ -173,69 +125,37 @@
            case 4:         /* FSUB ST0, float */
                GET_ED;
                if(!(((uintptr_t)ED)&3))
-                    #ifdef USE_FLOAT
-                    ST0.f -= *(float*)ED;
-                    #else
                    ST0.d -= *(float*)ED;
-                    #endif
                else {
-                    *(uint32_t*)&f = ED->dword[0];
-                    #ifdef USE_FLOAT
-                    ST0.f -= f;
-                    #else
+                    memcpy(&f, ED, sizeof(float));
                    ST0.d -= f;
-                    #endif
                }
                break;
            case 5:         /* FSUBR ST0, float */
                GET_ED;
                if(!(((uintptr_t)ED)&3))
-                    #ifdef USE_FLOAT
-                    ST0.f = *(float*)ED - ST0.f;
-                    #else
                    ST0.d = *(float*)ED - ST0.d;
-                    #endif
                else {
-                    *(uint32_t*)&f = ED->dword[0];
-                    #ifdef USE_FLOAT
-                    ST0.f = f - ST0.f;
-                    #else
+                    memcpy(&f, ED, sizeof(float));
                    ST0.d = f - ST0.d;
-                    #endif
                }
                break;
            case 6:         /* FDIV ST0, float */
                GET_ED;
                if(!(((uintptr_t)ED)&3))
-                    #ifdef USE_FLOAT
-                    ST0.f /= *(float*)ED;
-                    #else
                    ST0.d /= *(float*)ED;
-                    #endif
                else {
-                    *(uint32_t*)&f = ED->dword[0];
-                    #ifdef USE_FLOAT
-                    ST0.f /= f;
-                    #else
+                    memcpy(&f, ED, sizeof(float));
                    ST0.d /= f;
-                    #endif
                }
                break;
            case 7:         /* FDIVR ST0, float */
                GET_ED;
                if(!(((uintptr_t)ED)&3))
-                    #ifdef USE_FLOAT
-                    ST0.f = *(float*)ED / ST0.f;
-                    #else
                    ST0.d = *(float*)ED / ST0.d;
-                    #endif
                else {
-                    *(uint32_t*)&f = ED->dword[0];
-                    #ifdef USE_FLOAT
-                    ST0.f = f / ST0.f;
-                    #else
+                    memcpy(&f, ED, sizeof(float));
                    ST0.d = f / ST0.d;
-                    #endif
                }
                break;
            default:
@@ -1,5 +1,3 @@
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstrict-aliasing"
    nextop = F8;
    switch (nextop) {
        case 0xC0:
@@ -31,18 +29,10 @@
            break;

        case 0xE0:  /* FCHS */
-            #ifdef USE_FLOAT
-            ST0.f = -ST0.f;
-            #else
            ST0.d = -ST0.d;
-            #endif
            break;
        case 0xE1:  /* FABS */
-            #ifdef USE_FLOAT
-            ST0.f = fabsf(ST0.f);
-            #else
            ST0.d = fabs(ST0.d);
-            #endif
            break;
        
        case 0xE4:  /* FTST */
@@ -54,175 +44,128 @@

        case 0xE8:  /* FLD1 */
            fpu_do_push(emu);
-            #ifdef USE_FLOAT
-            ST0.f = 1.0f;
-            #else
            ST0.d = 1.0;
-            #endif
            break;
        case 0xE9:  /* FLDL2T */
            fpu_do_push(emu);
-            #ifdef USE_FLOAT
-            ST0.f = L2T;
-            #else
            ST0.d = L2T;
-            #endif
            break;
        case 0xEA:  /* FLDL2E */
            fpu_do_push(emu);
-            #ifdef USE_FLOAT
-            ST0.f = L2E;
-            #else
            ST0.d = L2E;
-            #endif
            break;
        case 0xEB:  /* FLDPI */
            fpu_do_push(emu);
-            #ifdef USE_FLOAT
-            ST0.f = PI;
-            #else
            ST0.d = PI;
-            #endif
            break;
        case 0xEC:  /* FLDLG2 */
            fpu_do_push(emu);
-            #ifdef USE_FLOAT
-            ST0.f = LG2;
-            #else
            ST0.d = LG2;
-            #endif
            break;
        case 0xED:  /* FLDLN2 */
            fpu_do_push(emu);
-            #ifdef USE_FLOAT
-            ST0.f = LN2;
-            #else
            ST0.d = LN2;
-            #endif
            break;
        case 0xEE:  /* FLDZ */
            fpu_do_push(emu);
-            #ifdef USE_FLOAT
-            ST0.f = 0.0f;
-            #else
            ST0.d = 0.0;
-            #endif
            break;

        case 0xF0:  /* F2XM1 */
-            #ifdef USE_FLOAT
-            ST0.f = exp2f(ST0.f) - 1.0f;
-            #else
            ST0.d = exp2(ST0.d) - 1.0;
-            #endif
            break;
        case 0xF1:  /* FYL2X */
-            #ifdef USE_FLOAT
-            ST(1).f = log2f(ST0.f)*ST(1).f;
-            #else
-            ST(1).d = log2(ST0.d)*ST(1).d;
-            #endif
+            ST(1).d *= log2(ST0.d);
            fpu_do_pop(emu);
            break;
-        case 0xF2:  /* FTAN */
-            #ifdef USE_FLOAT
-            ST0.f = tanf(ST0.f);
-            fpu_do_push(emu);
-            ST0.f = 1.0f;
-            #else
+        case 0xF2:  /* FPTAN */
            ST0.d = tan(ST0.d);
            fpu_do_push(emu);
            ST0.d = 1.0;
-            #endif
+            emu->sw.f.F87_C2 = 0;
            break;
        case 0xF3:  /* FPATAN */
-            #ifdef USE_FLOAT
-            ST1.f = atan2f(ST1.f, ST0.f);
-            #else
            ST1.d = atan2(ST1.d, ST0.d);
-            #endif
            fpu_do_pop(emu);
            break;
        case 0xF4:  /* FXTRACT */
-            #ifdef USE_FLOAT
-            tmp32s = (ST0.ll&0x7f700000)>>23;
-            tmp32s -= 127;
-            ST0.f /= exp2f(tmp32s);
-            fpu_do_push(emu);
-            ST0.f = tmp32s;
-            #else
-            tmp32s = (ST0.ll&0x7ff0000000000000LL)>>52;
-            tmp32s -= 1023;
-            ST0.d /= exp2(tmp32s);
+            ST0.d = frexp(ST0.d, &tmp32s);
            fpu_do_push(emu);
            ST0.d = tmp32s;
-            #endif
            break;

        case 0xF8:  /* FPREM */
-            #ifdef USE_FLOAT
-            tmp32s = ST0.f / ST1.f;
-            ST0.f -= ST1.f * tmp32s;
-            #else
-            tmp32s = ST0.d / ST1.d;
-            ST0.d -= ST1.d * tmp32s;
-            #endif
-            emu->sw.f.F87_C2 = 0;
-            emu->sw.f.F87_C0 = (tmp32s&1);
-            emu->sw.f.F87_C3 = ((tmp32s>>1)&1);
-            emu->sw.f.F87_C1 = ((tmp32s>>2)&1);
+            {
+                int e0, e1;
+                frexp(ST0.d, &e0);
+                frexp(ST1.d, &e1);
+                tmp32s = e0 - e1;
+            }
+            if(tmp32s<64)
+            {
+                ll = (int64_t)floor(ST0.d/ST1.d);
+                ST0.d = ST0.d - (ST1.d*ll);
+                emu->sw.f.F87_C2 = 0;
+                emu->sw.f.F87_C1 = (ll&1)?1:0;
+                emu->sw.f.F87_C3 = (ll&2)?1:0;
+                emu->sw.f.F87_C0 = (ll&4)?1:0;
+            } else {
+                ll = (int64_t)(floor((ST0.d/ST1.d))/exp2(tmp32s - 32));
+                ST0.d = ST0.d - ST1.d*ll*exp2(tmp32s - 32);
+                emu->sw.f.F87_C2 = 1;
+            }
+            break;
+        case 0xF5:  /* FPREM1 */
+            // get exponant(ST(0))-exponant(ST(1)) in temp32s
+            {
+                int e0, e1;
+                frexp(ST0.d, &e0);
+                frexp(ST1.d, &e1);
+                tmp32s = e0 - e1;
+            }
+            if(tmp32s<64)
+            {
+                ll = (int64_t)round(ST0.d/ST1.d);
+                ST0.d = ST0.d - (ST1.d*ll);
+                emu->sw.f.F87_C2 = 0;
+                emu->sw.f.F87_C1 = (ll&1)?1:0;
+                emu->sw.f.F87_C3 = (ll&2)?1:0;
+                emu->sw.f.F87_C0 = (ll&4)?1:0;
+            } else {
+                ll = (int64_t)(trunc((ST0.d/ST1.d))/exp2(tmp32s - 32));
+                ST0.d = ST0.d - ST1.d*ll*exp2(tmp32s - 32);
+                emu->sw.f.F87_C2 = 1;
+            }
+            break;
+        case 0xF6:  /* FDECSTP */
+            emu->top=(emu->top-1)&7;    // this will probably break a few things
+            break;
+        case 0xF7:  /* FINCSTP */
+            emu->top=(emu->top+1)&7;    // this will probably break a few things
            break;
        case 0xF9:  /* FYL2XP1 */
-            #ifdef USE_FLOAT
-            ST(1).f = log2f(ST0.f + 1.0f)*ST(1).f;
-            #else
-            ST(1).d = log2(ST0.d + 1.0)*ST(1).d;
-            #endif
+            ST(1).d *= log2(ST0.d + 1.0);
            fpu_do_pop(emu);
            break;
        case 0xFA:  /* FSQRT */
-            #ifdef USE_FLOAT
-            ST0.f = sqrtf(ST0.f);
-            #else
            ST0.d = sqrt(ST0.d);
-            #endif
            break;
        case 0xFB:  /* FSINCOS */
            fpu_do_push(emu);
-            #ifdef USE_FLOAT
-            sincosf(ST1.f, &ST1.f, &ST0.f);
-            #else
            sincos(ST1.d, &ST1.d, &ST0.d);
-            #endif
            break;
        case 0xFC:  /* FRNDINT */
-            #ifdef USE_FLOAT
-            ST0.f = fpu_round(emu, ST0.f);
-            #else
            ST0.d = fpu_round(emu, ST0.d);
-            #endif
            break;
        case 0xFD:  /* FSCALE */
            // this could probably be done by just altering the exponant part of the float...
-            #ifdef USE_FLOAT
-            ST0.f *= exp2f(truncf(ST1.f));
-            #else
            ST0.d *= exp2(trunc(ST1.d));
-            #endif
            break;
        case 0xFE:  /* FSIN */
-            #ifdef USE_FLOAT
-            ST0.f = sinf(ST0.f);
-            #else
            ST0.d = sin(ST0.d);
-            #endif
            break;
        case 0xFF:  /* FCOS */
-            #ifdef USE_FLOAT
-            ST0.f = cosf(ST0.f);
-            #else
            ST0.d = cos(ST0.d);
-            #endif
            break;


@@ -244,51 +187,36 @@
        case 0xE6:
        case 0xE7:
        case 0xEF:
-        case 0xF5:
-        case 0xF6:
-        case 0xF7:
            goto _default;
        default:
        switch((nextop>>3)&7) {
            case 0:     /* FLD ST0, Ed float */
                GET_ED;
                fpu_do_push(emu);
-                #ifdef USE_FLOAT
-                ST0.ll = ED->dword[0];
-                #else
                if(!(((uintptr_t)ED)&3))
                    ST0.d = *(float*)ED;
                else {
-                    memcpy(&f, ED->dword, sizeof(float));
+                    memcpy(&f, ED, sizeof(float));
                    ST0.d = f;
                }
-                #endif
                break;
            case 2:     /* FST Ed, ST0 */
                GET_ED;
-                #ifdef USE_FLOAT
-                *(float*)ED = ST0.f;
-                #else
                if(!(((uintptr_t)ED)&3))
                    *(float*)ED = ST0.d;
                else {
                    f = ST0.d;
-                    memcpy(ED->dword, &f, sizeof(float));
+                    memcpy(ED, &f, sizeof(float));
                }
-                #endif
                break;
            case 3:     /* FSTP Ed, ST0 */
                GET_ED;
-                #ifdef USE_FLOAT
-                ED->dword[0] = ST0.ll;
-                #else
                if(!(((uintptr_t)ED)&3))
                    *(float*)ED = ST0.d;
                else {
                    f = ST0.d;
-                    memcpy(ED->dword, &f, sizeof(float));
+                    memcpy(ED, &f, sizeof(float));
                }
-                #endif
                fpu_do_pop(emu);
                break;
            case 4:     /* FLDENV m */
@@ -306,9 +234,6 @@
                // warning, incomplete
                GET_ED;
                fpu_savenv(emu, (char*)ED, 0);
-                ED->dword[0] = emu->cw;
-                ED->dword[1] = emu->sw.x16;
-                // tagword: 2bits*8
                // intruction pointer: 48bits
                // data (operand) pointer: 48bits
                // last opcode: 11bits save: 16bits restaured (1st and 2nd opcode only)
@@ -321,4 +246,3 @@
                goto _default;
        }
    }
-#pragma GCC diagnostic pop
@@ -51,11 +51,7 @@
        break;
    
    case 0xE9:      /* FUCOMPP */
-        #ifdef USE_FLOAT
-        fpu_fcom(emu, ST1.f);
-        #else
        fpu_fcom(emu, ST1.d);   // bad, should handle QNaN and IA interrupt
-        #endif
        fpu_do_pop(emu);
        fpu_do_pop(emu);
        break;
@@ -76,19 +72,11 @@
        switch((nextop>>3)&7) {
            case 0:     /* FIADD ST0, Ed int */
                GET_ED;
-                #ifdef USE_FLOAT
-                ST0.f += ED->sdword[0];
-                #else
                ST0.d += ED->sdword[0];
-                #endif
                break;
            case 1:     /* FIMUL ST0, Ed int */
                GET_ED;
-                #ifdef USE_FLOAT
-                ST0.f *= ED->sdword[0];
-                #else
                ST0.d *= ED->sdword[0];
-                #endif
                break;
            case 2:     /* FICOM ST0, Ed int */
                GET_ED;
@@ -101,35 +89,19 @@
                break;
            case 4:     /* FISUB ST0, Ed int */
                GET_ED;
-                #ifdef USE_FLOAT
-                ST0.f -= ED->sdword[0];
-                #else
                ST0.d -= ED->sdword[0];
-                #endif
                break;
            case 5:     /* FISUBR ST0, Ed int */
                GET_ED;
-                #ifdef USE_FLOAT
-                ST0.f = ED->sdword[0] - ST0.f;
-                #else
-                ST0.d = ED->sdword[0] - ST0.d;
-                #endif
+                ST0.d = (double)ED->sdword[0] - ST0.d;
                break;
            case 6:     /* FIDIV ST0, Ed int */
                GET_ED;
-                #ifdef USE_FLOAT
-                ST0.f /= ED->sdword[0];
-                #else
                ST0.d /= ED->sdword[0];
-                #endif
                break;
            case 7:     /* FIDIVR ST0, Ed int */
                GET_ED;
-                #ifdef USE_FLOAT
-                ST0.f = ED->sdword[0] / ST0.f;
-                #else
-                ST0.d = ED->sdword[0] / ST0.d;
-                #endif
+                ST0.d = (double)ED->sdword[0] / ST0.d;
                break;
        }
    }
@@ -49,6 +49,8 @@
            ST0.ll = ST(nextop&7).ll;
        break;

+    case 0xE1:      /* FDISI8087_NOP */
+        break;
    case 0xE2:      /* FNCLEX */
        //Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), 
        // the exception summary status flag (ES), the stack fault flag (SF), and the busy flag (B) in the FPU status word
@@ -73,11 +75,7 @@
    case 0xED:
    case 0xEE:
    case 0xEF:
-        #ifdef USE_FLOAT
-        fpu_fcomi(emu, ST(nextop&7).f);
-        #else
        fpu_fcomi(emu, ST(nextop&7).d);   // bad, should handle QNaN and IA interrupt
-        #endif
        break;

    case 0xF0:  /* FCOMI ST0, STx */
@@ -88,14 +86,9 @@
    case 0xF5:
    case 0xF6:
    case 0xF7:
-        #ifdef USE_FLOAT
-        fpu_fcomi(emu, ST(nextop&7).f);
-        #else
        fpu_fcomi(emu, ST(nextop&7).d);
-        #endif
        break;
    case 0xE0:
-    case 0xE1:
    case 0xE4:
    case 0xE5:
    case 0xE6:
@@ -103,134 +96,49 @@
        goto _default;
    default:
        switch((nextop>>3)&7) {
-            case 0: /* FILD ST0, Gd */
+            case 0: /* FILD ST0, Ed */
                GET_ED;
                fpu_do_push(emu);
-                #ifdef USE_FLOAT
-                ST0.f = ED->sdword[0];
-                #else
                ST0.d = ED->sdword[0];
-                #endif
                break;
            case 1: /* FISTTP Ed, ST0 */
                GET_ED;
-                #ifdef USE_FLOAT
-                tmp32s = ST0.f; // TODO: Handling of FPU Exception
-                if(tmp32s==0x7fffffff && isgreater(ST0.f, (float)(int32_t)0x7fffffff))
-                    tmp32s = 0x80000000;
-                #else
                tmp32s = ST0.d; // TODO: Handling of FPU Exception
                if(tmp32s==0x7fffffff && isgreater(ST0.d, (double)(int32_t)0x7fffffff))
                    tmp32s = 0x80000000;
-                #endif
                fpu_do_pop(emu);
                ED->sdword[0] = tmp32s;
                break;
            case 2: /* FIST Ed, ST0 */
                GET_ED;
-                #ifdef USE_FLOAT
-                if(isgreater(ST0.f, (float)(int32_t)0x7fffffff) || isless(ST0.f, -(float)(int32_t)0x7fffffff))
+                if(isgreater(ST0.d, (double)(int32_t)0x7fffffff) || isless(ST0.d, -(double)(int32_t)0x7fffffff) || !isfinite(ST0.d))
                    ED->sdword[0] = 0x80000000;
                else {
-                    switch(emu->round) {
-                        case ROUND_Nearest:
-                            ED->sdword[0] = floorf(ST0.f+0.5);
-                            break;
-                        case ROUND_Down:
-                            ED->sdword[0] = floorf(ST0.f);
-                            break;
-                        case ROUND_Up:
-                            ED->sdword[0] = ceilf(ST0.f);
-                            break;
-                        case ROUND_Chop:
-                            ED->sdword[0] = ST0.f;
-                            break;
-                    }
+                    volatile int32_t tmp = fpu_round(emu, ST0.d);    // tmp to avoid BUS ERROR
+                    ED->sdword[0] = tmp;
                }
-                #else
-                if(isgreater(ST0.d, (double)(int32_t)0x7fffffff) || isless(ST0.d, -(double)(int32_t)0x7fffffff))
-                    ED->sdword[0] = 0x80000000;
-                else {
-                    switch(emu->round) {
-                        case ROUND_Nearest:
-                            ED->sdword[0] = floor(ST0.d+0.5);
-                            break;
-                        case ROUND_Down:
-                            ED->sdword[0] = floor(ST0.d);
-                            break;
-                        case ROUND_Up:
-                            ED->sdword[0] = ceil(ST0.d);
-                            break;
-                        case ROUND_Chop:
-                            ED->sdword[0] = ST0.d;
-                            break;
-                    }
-                }
-                #endif
                break;
            case 3: /* FISTP Ed, ST0 */
                GET_ED;
-                #ifdef USE_FLOAT
-                if(isgreater(ST0.f, (float)(int32_t)0x7fffffff) || isless(ST0.f, -(float)(int32_t)0x7fffffff))
+                if(isgreater(ST0.d, (double)(int32_t)0x7fffffff) || isless(ST0.d, -(double)(int32_t)0x7fffffff) || !isfinite(ST0.d))
                    ED->sdword[0] = 0x80000000;
                else {
-                    switch(emu->round) {
-                        case ROUND_Nearest:
-                            ED->sdword[0] = floorf(ST0.f+0.5);
-                            break;
-                        case ROUND_Down:
-                            ED->sdword[0] = floorf(ST0.f);
-                            break;
-                        case ROUND_Up:
-                            ED->sdword[0] = ceilf(ST0.f);
-                            break;
-                        case ROUND_Chop:
-                            ED->sdword[0] = ST0.f;
-                            break;
-                    }
+                    volatile int32_t tmp = fpu_round(emu, ST0.d);    // tmp to avoid BUS ERROR
+                    ED->sdword[0] = tmp;
                }
-                #else
-                if(isgreater(ST0.d, (double)(int32_t)0x7fffffff) || isless(ST0.d, -(double)(int32_t)0x7fffffff))
-                    ED->sdword[0] = 0x80000000;
-                else {
-                    switch(emu->round) {
-                        case ROUND_Nearest:
-                            ED->sdword[0] = floor(ST0.d+0.5);
-                            break;
-                        case ROUND_Down:
-                            ED->sdword[0] = floor(ST0.d);
-                            break;
-                        case ROUND_Up:
-                            ED->sdword[0] = ceil(ST0.d);
-                            break;
-                        case ROUND_Chop:
-                            ED->sdword[0] = ST0.d;
-                            break;
-                    }
-                }
-                #endif
                fpu_do_pop(emu);
                break;
-            case 5: /* FLD ST0, Gt */
+            case 5: /* FLD ST0, Et */
                GET_ED;
                fpu_do_push(emu);
                memcpy(&STld(0).ld, ED, 10);
-                #ifdef USE_FLOAT
-                LD2D(&STld(0), &d);
-                ST0.f = d;
-                #else
                LD2D(&STld(0), &ST(0).d);
-                #endif
                STld(0).ref = ST0.ll;
                break;
            case 7: /* FSTP tbyte */
                GET_ED;
                if(ST0.ll!=STld(0).ref)
-                    #ifdef USE_FLOAT
-                    {d = ST0.f; D2LD(&d, ED);}
-                    #else
                    D2LD(&ST0.d, ED);
-                    #endif
                else
                    memcpy(ED, &STld(0).ld, 10);
                fpu_do_pop(emu);
@@ -1,5 +1,3 @@
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstrict-aliasing"
    nextop = F8;
    switch(nextop) {
        case 0xC0:
@@ -10,11 +8,7 @@
        case 0xC5:
        case 0xC6:
        case 0xC7:  /* FADD */
-            #ifdef USE_FLOAT
-            ST(nextop&7).f += ST0.f;
-            #else
            ST(nextop&7).d += ST0.d;
-            #endif
            break;
        case 0xC8:
        case 0xC9:
@@ -24,11 +18,7 @@
        case 0xCD:
        case 0xCE:
        case 0xCF:  /* FMUL */
-            #ifdef USE_FLOAT
-            ST(nextop&7).f *= ST0.f;
-            #else
            ST(nextop&7).d *= ST0.d;
-            #endif
            break;
        case 0xD0:
        case 0xD1:
@@ -38,11 +28,7 @@
        case 0xD5:
        case 0xD6:
        case 0xD7:  /* FCOM */
-            #ifdef USE_FLOAT
-            fpu_fcom(emu, ST(nextop&7).f);
-            #else
            fpu_fcom(emu, ST(nextop&7).d);
-            #endif
            break;
        case 0xD8:
        case 0xD9:
@@ -52,11 +38,7 @@
        case 0xDD:
        case 0xDE:
        case 0xDF:  /* FCOMP */
-            #ifdef USE_FLOAT
-            fpu_fcom(emu, ST(nextop&7).f);
-            #else
            fpu_fcom(emu, ST(nextop&7).d);  // TODO: is this ok?
-            #endif
            fpu_do_pop(emu);
            break;
        case 0xE0:
@@ -67,11 +49,7 @@
        case 0xE5:
        case 0xE6:
        case 0xE7:  /* FSUBR */
-            #ifdef USE_FLOAT
-            ST(nextop&7).f = ST0.f -ST(nextop&7).f;
-            #else
            ST(nextop&7).d = ST0.d -ST(nextop&7).d;
-            #endif
            break;
        case 0xE8:
        case 0xE9:
@@ -81,11 +59,7 @@
        case 0xED:
        case 0xEE:
        case 0xEF:  /* FSUB */
-            #ifdef USE_FLOAT
-            ST(nextop&7).f -= ST0.f;
-            #else
            ST(nextop&7).d -= ST0.d;
-            #endif
            break;
        case 0xF0:
        case 0xF1:
@@ -95,11 +69,7 @@
        case 0xF5:
        case 0xF6:
        case 0xF7:  /* FDIVR */
-            #ifdef USE_FLOAT
-            ST(nextop&7).f = ST0.f / ST(nextop&7).f;
-            #else
            ST(nextop&7).d = ST0.d / ST(nextop&7).d;
-            #endif
            break;
        case 0xF8:
        case 0xF9:
@@ -109,54 +79,32 @@
        case 0xFD:
        case 0xFE:
        case 0xFF:  /* FDIV */
-            #ifdef USE_FLOAT
-            ST(nextop&7).f /=  ST0.f;
-            #else
            ST(nextop&7).d /=  ST0.d;
-            #endif
            break;
        default:
            GET_ED;
            switch((nextop>>3)&7) {
            case 0:         /* FADD ST0, double */
-                #ifdef USE_FLOAT
-                if(!(((uintptr_t)ED)&7))
-                    ST0.f += *(double*)ED;
-                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
-                    ST0.f += d;
-                }
-                #else
                if(!(((uintptr_t)ED)&7))
                    ST0.d += *(double*)ED;
                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
+                    memcpy(&d, ED, sizeof(double));
                    ST0.d += d;
                }
-                #endif
                break;
            case 1:         /* FMUL ST0, double */
-                #ifdef USE_FLOAT
-                if(!(((uintptr_t)ED)&7))
-                    ST0.f *= *(double*)ED;
-                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
-                    ST0.f *= d;
-                }
-                #else
                if(!(((uintptr_t)ED)&7))
                    ST0.d *= *(double*)ED;
                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
+                    memcpy(&d, ED, sizeof(double));
                    ST0.d *= d;
                }
-                #endif
                break;
            case 2:      /* FCOM ST0, double */
                if(!(((uintptr_t)ED)&7))
                    fpu_fcom(emu, *(double*)ED);
                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
+                    memcpy(&d, ED, sizeof(double));
                    fpu_fcom(emu, d);
                }
                break;
@@ -164,78 +112,42 @@
                if(!(((uintptr_t)ED)&7))
                    fpu_fcom(emu, *(double*)ED);
                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
+                    memcpy(&d, ED, sizeof(double));
                    fpu_fcom(emu, d);
                }
                fpu_do_pop(emu);
                break;
            case 4:         /* FSUB ST0, double */
-                #ifdef USE_FLOAT
-                if(!(((uintptr_t)ED)&7))
-                    ST0.f -= *(double*)ED;
-                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
-                    ST0.f -= d;
-                }
-                #else
                if(!(((uintptr_t)ED)&7))
                    ST0.d -= *(double*)ED;
                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
+                    memcpy(&d, ED, sizeof(double));
                    ST0.d -= d;
                }
-                #endif
                break;
            case 5:         /* FSUBR ST0, double */
-                #ifdef USE_FLOAT
-                if(!(((uintptr_t)ED)&7))
-                    ST0.f = *(double*)ED - ST0.f;
-                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
-                    ST0.f = d - ST0.f;
-                }
-                #else
                if(!(((uintptr_t)ED)&7))
                    ST0.d = *(double*)ED - ST0.d;
                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
+                    memcpy(&d, ED, sizeof(double));
                    ST0.d = d - ST0.d;
                }
-                #endif
                break;
            case 6:         /* FDIV ST0, double */
-                #ifdef USE_FLOAT
-                if(!(((uintptr_t)ED)&7))
-                    ST0.f /= *(double*)ED;
-                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
-                    ST0.f /= d;
-                }
-                #else
                if(!(((uintptr_t)ED)&7))
                    ST0.d /= *(double*)ED;
                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
+                    memcpy(&d, ED, sizeof(double));
                    ST0.d /= d;
                }
-                #endif
                break;
            case 7:         /* FDIVR ST0, double */
-                #ifdef USE_FLOAT
-                if(!(((uintptr_t)ED)&7))
-                    ST0.f = *(double*)ED / ST0.f;
-                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
-                    ST0.f = d / ST0.f;
-                }
-                #else
                if(!(((uintptr_t)ED)&7))
                    ST0.d = *(double*)ED / ST0.d;
                else {
-                    *(uint64_t*)&d = *(uint64_t*)ED;
+                    memcpy(&d, ED, sizeof(double));
                    ST0.d = d / ST0.d;
                }
-                #endif
                break;
            default:
                goto _default;
@@ -9,7 +9,8 @@
    case 0xC5:
    case 0xC6:
    case 0xC7:
-        break;  // not handling Tag...
+        fpu_do_free(emu, nextop-0xC0);
+        break;

    case 0xD0:  /* FST ST0, STx */
    case 0xD1:
@@ -40,11 +41,7 @@
    case 0xE5:
    case 0xE6:
    case 0xE7:
-        #ifdef USE_FLOAT
-        fpu_fcom(emu, ST(nextop&7).f);
-        #else
        fpu_fcom(emu, ST(nextop&7).d);   // bad, should handle QNaN and IA interrupt
-        #endif
        break;
    case 0xE8:  /* FUCOMP ST0, STx */
    case 0xE9:
@@ -54,11 +51,7 @@
    case 0xED:
    case 0xEE:
    case 0xEF:
-        #ifdef USE_FLOAT
-        fpu_fcom(emu, ST(nextop&7).f);
-        #else
        fpu_fcom(emu, ST(nextop&7).d);   // bad, should handle QNaN and IA interrupt
-        #endif
        fpu_do_pop(emu);
        break;

@@ -93,39 +86,37 @@
            case 0: /* FLD double */
                GET_ED;
                fpu_do_push(emu);
-                #ifdef USE_FLOAT
-                *(uint64_t*)&d = *(int64_t*)ED;
-                ST0.f = d;
-                #else
-                ST0.ll = *(int64_t*)ED;
-                #endif
+                if(!(((uintptr_t)ED)&7))
+                    ST0.d = *(double*)ED;
+                else {
+                    memcpy(&ST0.d, ED, sizeof(double));
+                }
                break;
            case 1: /* FISTTP ED qword */
                GET_ED;
-                #ifdef USE_FLOAT
-                *(int64_t*)ED = ST0.f;
-                #else
-                *(int64_t*)ED = ST0.d;
-                #endif
+                if(!(((uintptr_t)ED)&7))
+                    *(int64_t*)ED = ST0.d;
+                else {
+                    int64_t i64 = ST0.d;
+                    memcpy(ED, &i64, sizeof(int64_t));
+                }
                fpu_do_pop(emu);
                break;
            case 2: /* FST double */
                GET_ED;
-                #ifdef USE_FLOAT
-                d = ST0.f;
-                *(int64_t*)ED = *(uint64_t*)&d;
-                #else
-                *(int64_t*)ED = ST0.ll;
-                #endif
+                if(!(((uintptr_t)ED)&7))
+                    *(double*)ED = ST0.d;
+                else {
+                    memcpy(ED, &ST0.d, sizeof(double));
+                }
                break;
            case 3: /* FSTP double */
                GET_ED;
-                #ifdef USE_FLOAT
-                d = ST0.f;
-                *(int64_t*)ED = *(uint64_t*)&d;
-                #else
-                *(int64_t*)ED = ST0.ll;
-                #endif
+                if(!(((uintptr_t)ED)&7))
+                    *(double*)ED = ST0.d;
+                else {
+                    memcpy(ED, &ST0.d, sizeof(double));
+                }
                fpu_do_pop(emu);
                break;
            case 4: /* FRSTOR m108byte */
@@ -136,12 +127,7 @@
                    char* p =(char*)ED;
                    p += 28;
                    for (int i=0; i<8; ++i) {
-                        #ifdef USE_FLOAT
-                        d = ST(i).f;
-                        LD2D(p, &d);
-                        #else
                        LD2D(p, &ST(i).d);
-                        #endif
                        p+=10;
                    }
                }
@@ -156,12 +142,7 @@
                    char* p =(char*)ED;
                    p += 28;
                    for (int i=0; i<8; ++i) {
-                        #ifdef USE_FLOAT
-                        D2LD(&d, p);
-                        ST(i).f = d;
-                        #else
                        D2LD(&ST(i).d, p);
-                        #endif
                        p+=10;
                    }
                }
@@ -1,55 +1,41 @@
    nextop = F8;
    switch (nextop) {
-    case 0xC1:  /* FADDP ST1, ST0 */
-        #ifdef USE_FLOAT
-        ST(1).f += ST0.f;
-        #else
-        ST(1).d += ST0.d;
-        #endif
-        fpu_do_pop(emu);
-        break;
    case 0xC0:  /* FADDP STx, ST0 */
+    case 0xC1:  /* FADDP ST1, ST0 */
    case 0xC2:
    case 0xC3:
    case 0xC4:
    case 0xC5:
    case 0xC6:
    case 0xC7:
-        #ifdef USE_FLOAT
-        ST(nextop&7).f += ST0.f;
-        #else
        ST(nextop&7).d += ST0.d;
-        #endif
-        fpu_do_pop(emu);
-        break;
-    case 0xC9:  /* FMULP ST1, ST0 */
-        #ifdef USE_FLOAT
-        ST1.f *= ST0.f;
-        #else
-        ST1.d *= ST0.d;
-        #endif
        fpu_do_pop(emu);
        break;
    case 0xC8:  /* FMULP STx, ST0 */
+    case 0xC9:  /* FMULP ST1, ST0 */
    case 0xCA:
    case 0xCB:
    case 0xCC:
    case 0xCD:
    case 0xCE:
    case 0xCF:
-        #ifdef USE_FLOAT
-        ST(nextop&7).f *= ST0.f;
-        #else
        ST(nextop&7).d *= ST0.d;
-        #endif
        fpu_do_pop(emu);
        break;
+    case 0xD0:
+    case 0xD1:
+    case 0xD2:
+    case 0xD3:
+    case 0xD4:
+    case 0xD5:
+    case 0xD6:
+    case 0xD7:  /* FCOMP */
+        fpu_fcom(emu, ST(nextop&7).d);
+        fpu_do_pop(emu);
+        break;
+
    case 0xD9:  /* FCOMPP */
-        #ifdef USE_FLOAT
-        fpu_fcom(emu, ST1.f);
-        #else
        fpu_fcom(emu, ST1.d);
-        #endif
        fpu_do_pop(emu);
        fpu_do_pop(emu);
        break;
@@ -65,33 +51,18 @@
    case 0xE5:
    case 0xE6:
    case 0xE7:
-        #ifdef USE_FLOAT
-        ST(nextop&7).f = ST0.f - ST(nextop&7).f;
-        #else
        ST(nextop&7).d = ST0.d - ST(nextop&7).d;
-        #endif
-        fpu_do_pop(emu);
-        break;
-   case 0xE9:  /* FSUBP ST1, ST0 */
-        #ifdef USE_FLOAT
-        ST1.f -= ST0.f;
-        #else
-        ST1.d -= ST0.d;
-        #endif
        fpu_do_pop(emu);
        break;
    case 0xE8:  /* FSUBP STx, ST0 */
+    case 0xE9:  /* FSUBP ST1, ST0 */
    case 0xEA:
    case 0xEB:
    case 0xEC:
    case 0xED:
    case 0xEE:
    case 0xEF:
-        #ifdef USE_FLOAT
-        ST(nextop&7).f -= ST0.f;
-        #else
        ST(nextop&7).d -= ST0.d;
-        #endif
        fpu_do_pop(emu);
        break;
    case 0xF0:  /* FDIVRP STx, ST0 */
@@ -102,11 +73,7 @@
    case 0xF5:
    case 0xF6:
    case 0xF7:
-        #ifdef USE_FLOAT
-        ST(nextop&7).f = ST0.f / ST(nextop&7).f;
-        #else
        ST(nextop&7).d = ST0.d / ST(nextop&7).d;
-        #endif
        fpu_do_pop(emu);
        break;
    case 0xF8:  /* FDIVP STx, ST0 */
@@ -117,23 +84,11 @@
    case 0xFD:
    case 0xFE:
    case 0xFF:
-        #ifdef USE_FLOAT
-        ST(nextop&7).f /= ST0.f;
-        #else
        ST(nextop&7).d /= ST0.d;
-        #endif
        fpu_do_pop(emu);
        break;

-    case 0xD0:
-    case 0xD1:
-    case 0xD2:
-    case 0xD3:
-    case 0xD4:
-    case 0xD5:
-    case 0xD6:
-    case 0xD7:
-    case 0xD8:
+    case 0xD8:  
    case 0xDA:
    case 0xDB:
    case 0xDC:
@@ -146,51 +101,27 @@
        switch((nextop>>3)&7) {
            case 0:     /* FIADD ST0, Ew int */
                GET_EW;
-                #ifdef USE_FLOAT
-                ST0.f += EW->sword[0];
-                #else
                ST0.d += EW->sword[0];
-                #endif
                break;
            case 1:     /* FIMUL ST0, Ew int */
                GET_EW;
-                #ifdef USE_FLOAT
-                ST0.f *= EW->sword[0];
-                #else
                ST0.d *= EW->sword[0];
-                #endif
                break;
            case 4:     /* FISUB ST0, Ew int */
                GET_EW;
-                #ifdef USE_FLOAT
-                ST0.f -= EW->sword[0];
-                #else
                ST0.d -= EW->sword[0];
-                #endif
                break;
            case 5:     /* FISUBR ST0, Ew int */
                GET_EW;
-                #ifdef USE_FLOAT
-                ST0.f = EW->sword[0] - ST0.f;
-                #else
-                ST0.d = EW->sword[0] - ST0.d;
-                #endif
+                ST0.d = (double)EW->sword[0] - ST0.d;
                break;
            case 6:     /* FIDIV ST0, Ew int */
                GET_EW;
-                #ifdef USE_FLOAT
-                ST0.f /= EW->sword[0];
-                #else
                ST0.d /= EW->sword[0];
-                #endif
                break;
            case 7:     /* FIDIVR ST0, Ew int */
                GET_EW;
-                #ifdef USE_FLOAT
-                ST0.f = EW->sword[0] / ST0.f;
-                #else
-                ST0.d = EW->sword[0] / ST0.d;
-                #endif
+                ST0.d = (double)EW->sword[0] / ST0.d;
                break;
        default:
            goto _default;
@@ -1,5 +1,17 @@
    nextop = F8;
    switch (nextop) {
+    case 0xC0:  /* FFREEP STx */
+    case 0xC1:
+    case 0xC2:
+    case 0xC3:
+    case 0xC4:
+    case 0xC5:
+    case 0xC6:
+    case 0xC7:
+        fpu_do_free(emu, nextop-0xC0);
+        fpu_do_pop(emu);
+        break;
+
    case 0xE0:  /* FNSTSW AX */
        emu->sw.f.F87_TOP = emu->top&7;
        R_AX = emu->sw.x16;
@@ -13,11 +25,7 @@
    case 0xED:
    case 0xEE:
    case 0xEF:
-        #ifdef USE_FLOAT
-        fpu_fcomi(emu, ST(nextop&7).f);
-        #else
        fpu_fcomi(emu, ST(nextop&7).d);   // bad, should handle QNaN and IA interrupt
-        #endif
        fpu_do_pop(emu);
        break;

@@ -29,22 +37,10 @@
    case 0xF5:
    case 0xF6:
    case 0xF7:
-        #ifdef USE_FLOAT
-        fpu_fcomi(emu, ST(nextop&7).f);
-        #else
        fpu_fcomi(emu, ST(nextop&7).d);
-        #endif
        fpu_do_pop(emu);
        break;

-    case 0xC0:
-    case 0xC1:
-    case 0xC2:
-    case 0xC3:
-    case 0xC4:
-    case 0xC5:
-    case 0xC6:
-    case 0xC7:
    case 0xC8:
    case 0xC9:
    case 0xCA:
@@ -92,105 +88,27 @@
            GET_EW;
            tmp16s = EW->sword[0];
            fpu_do_push(emu);
-            #ifdef USE_FLOAT
-            ST0.f = tmp16s;
-            #else
            ST0.d = tmp16s;
-            #endif
            break;
        case 1: /* FISTTP Ew, ST0 */
            GET_EW;
-            #ifdef USE_FLOAT
-            tmp16s = ST0.f;
-            #else
            tmp16s = ST0.d;
-            #endif
            EW->sword[0] = tmp16s;
            fpu_do_pop(emu);
            break;
        case 2: /* FIST Ew, ST0 */
            GET_EW;
-            #ifdef USE_FLOAT
-            if(isgreater(ST0.f, (float)(int32_t)0x7fff) || isless(ST0.f, -(float)(int32_t)0x7fff))
+            if(isgreater(ST0.d, (double)(int32_t)0x7fff) || isless(ST0.d, -(double)(int32_t)0x7fff) || !isfinite(ST0.d))
                EW->sword[0] = 0x8000;
-            else {
-                switch(emu->round) {
-                    case ROUND_Nearest:
-                        EW->sword[0] = floorf(ST0.f+0.5);
-                        break;
-                    case ROUND_Down:
-                        EW->sword[0] = floorf(ST0.f);
-                        break;
-                    case ROUND_Up:
-                        EW->sword[0] = ceilf(ST0.f);
-                        break;
-                    case ROUND_Chop:
-                        EW->sword[0] = ST0.f;
-                        break;
-                }
-            }
-            #else
-            if(isgreater(ST0.d, (double)(int32_t)0x7fff) || isless(ST0.d, -(double)(int32_t)0x7fff))
-                EW->sword[0] = 0x8000;
-            else {
-                switch(emu->round) {
-                    case ROUND_Nearest:
-                        EW->sword[0] = floor(ST0.d+0.5);
-                        break;
-                    case ROUND_Down:
-                        EW->sword[0] = floor(ST0.d);
-                        break;
-                    case ROUND_Up:
-                        EW->sword[0] = ceil(ST0.d);
-                        break;
-                    case ROUND_Chop:
-                        EW->sword[0] = ST0.d;
-                        break;
-                }
-            }
-            #endif
+            else
+                EW->sword[0] = fpu_round(emu, ST0.d);
            break;
        case 3: /* FISTP Ew, ST0 */
            GET_EW;
-            #ifdef USE_FLOAT
-            if(isgreater(ST0.f, (float)(int32_t)0x7fff) || isless(ST0.f, -(float)(int32_t)0x7fff))
+            if(isgreater(ST0.d, (double)(int32_t)0x7fff) || isless(ST0.d, -(double)(int32_t)0x7fff) || !isfinite(ST0.d))
                EW->sword[0] = 0x8000;
-            else {
-                switch(emu->round) {
-                    case ROUND_Nearest:
-                        EW->sword[0] = floorf(ST0.f+0.5);
-                        break;
-                    case ROUND_Down:
-                        EW->sword[0] = floorf(ST0.f);
-                        break;
-                    case ROUND_Up:
-                        EW->sword[0] = ceilf(ST0.f);
-                        break;
-                    case ROUND_Chop:
-                        EW->sword[0] = ST0.f;
-                        break;
-                }
-            }
-            #else
-            if(isgreater(ST0.d, (double)(int32_t)0x7fff) || isless(ST0.d, -(double)(int32_t)0x7fff))
-                EW->sword[0] = 0x8000;
-            else {
-                switch(emu->round) {
-                    case ROUND_Nearest:
-                        EW->sword[0] = floor(ST0.d+0.5);
-                        break;
-                    case ROUND_Down:
-                        EW->sword[0] = floor(ST0.d);
-                        break;
-                    case ROUND_Up:
-                        EW->sword[0] = ceil(ST0.d);
-                        break;
-                    case ROUND_Chop:
-                        EW->sword[0] = ST0.d;
-                        break;
-                }
-            }
-            #endif
+            else
+                EW->sword[0] = fpu_round(emu, ST0.d);
            fpu_do_pop(emu);
            break;
        case 4: /* FBLD ST0, tbytes */
@@ -202,11 +120,7 @@
            GET_ED;
            tmp64s = *(int64_t*)ED;
            fpu_do_push(emu);
-            #ifdef USE_FLOAT
-            ST0.f = tmp64s;
-            #else
            ST0.d = tmp64s;
-            #endif
            STll(0).ll = tmp64s;
            STll(0).ref = ST0.ll;
            break;
@@ -217,20 +131,27 @@
            break;
        case 7: /* FISTP i64 */
            GET_ED;
-            if(STll(0).ref==ST(0).ll) {
-                *(int64_t*)ED = STll(0).ll;
+            if((uintptr_t)ED & 0x7) {
+                // un-aligned!
+                if(STll(0).ref==ST(0).ll)
+                    memcpy(ED, &STll(0).ll, sizeof(int64_t));
+                else {
+                    int64_t i64;
+                    if(isgreater(ST0.d, (double)(int64_t)0x7fffffffffffffffLL) || isless(ST0.d, -(double)(int64_t)0x7fffffffffffffffLL) || !isfinite(ST0.d))
+                        i64 = 0x8000000000000000LL;
+                    else
+                        i64 = fpu_round(emu, ST0.d);
+                    memcpy(ED, &i64, sizeof(int64_t));
+                }
            } else {
-                #ifdef USE_FLOAT
-                if(isgreater(ST0.f, (float)(int64_t)0x7fffffffffffffffLL) || isless(ST0.f, (float)(int64_t)0x8000000000000000LL))
-                    *(int64_t*)ED = 0x8000000000000000LL;
-                else
-                    *(int64_t*)ED = (int64_t)ST0.f;
-                #else
-                if(isgreater(ST0.d, (double)(int64_t)0x7fffffffffffffffLL) || isless(ST0.d, (double)(int64_t)0x8000000000000000LL))
-                    *(int64_t*)ED = 0x8000000000000000LL;
-                else
-                    *(int64_t*)ED = (int64_t)ST0.d;
-                #endif
+                if(STll(0).ref==ST(0).ll)
+                    *(int64_t*)ED = STll(0).ll;
+                else {
+                    if(isgreater(ST0.d, (double)(int64_t)0x7fffffffffffffffLL) || isless(ST0.d, -(double)(int64_t)0x7fffffffffffffffLL) || !isfinite(ST0.d))
+                        *(int64_t*)ED = 0x8000000000000000LL;
+                    else
+                        *(int64_t*)ED = fpu_round(emu, ST0.d);
+                }
            }
            fpu_do_pop(emu);
            break;
@@ -111,6 +111,107 @@
        }
        break;

+    case 0x7C:  /* HADDPS Gx, Ex */
+        nextop = F8;
+        GET_EX;
+        GX.f[0] += GX.f[1];
+        GX.f[1] = GX.f[2] + GX.f[3];
+        if(EX==&GX) {
+            GX.f[2] = GX.f[0];
+            GX.f[3] = GX.f[1];
+        } else {
+            GX.f[2] = EX->f[0] + EX->f[1];
+            GX.f[3] = EX->f[2] + EX->f[3];
+        }
+        break;
+
+    #define GOCOND(BASE, PREFIX, CONDITIONAL)   \
+    case BASE+0:                                \
+        PREFIX                                  \
+        if(ACCESS_FLAG(F_OF))                   \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+1:                                \
+        PREFIX                                  \
+        if(!ACCESS_FLAG(F_OF))                  \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+2:                                \
+        PREFIX                                  \
+        if(ACCESS_FLAG(F_CF))                   \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+3:                                \
+        PREFIX                                  \
+        if(!ACCESS_FLAG(F_CF))                  \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+4:                                \
+        PREFIX                                  \
+        if(ACCESS_FLAG(F_ZF))                   \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+5:                                \
+        PREFIX                                  \
+        if(!ACCESS_FLAG(F_ZF))                  \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+6:                                \
+        PREFIX                                  \
+        if((ACCESS_FLAG(F_ZF) || ACCESS_FLAG(F_CF)))  \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+7:                                \
+        PREFIX                                  \
+        if(!(ACCESS_FLAG(F_ZF) || ACCESS_FLAG(F_CF))) \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+8:                                \
+        PREFIX                                  \
+        if(ACCESS_FLAG(F_SF))                   \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+9:                                \
+        PREFIX                                  \
+        if(!ACCESS_FLAG(F_SF))                  \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+0xA:                              \
+        PREFIX                                  \
+        if(ACCESS_FLAG(F_PF))                   \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+0xB:                              \
+        PREFIX                                  \
+        if(!ACCESS_FLAG(F_PF))                  \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+0xC:                              \
+        PREFIX                                  \
+        if(ACCESS_FLAG(F_SF) != ACCESS_FLAG(F_OF))  \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+0xD:                              \
+        PREFIX                                  \
+        if(ACCESS_FLAG(F_SF) == ACCESS_FLAG(F_OF)) \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+0xE:                              \
+        PREFIX                                  \
+        if(ACCESS_FLAG(F_ZF) || (ACCESS_FLAG(F_SF) != ACCESS_FLAG(F_OF))) \
+            CONDITIONAL                         \
+        break;                                  \
+    case BASE+0xF:                              \
+        PREFIX                                  \
+        if(!ACCESS_FLAG(F_ZF) && (ACCESS_FLAG(F_SF) == ACCESS_FLAG(F_OF))) \
+            CONDITIONAL                         \
+        break;
+        
+    GOCOND(0x80
+        , tmp32s = F32S; CHECK_FLAGS(emu);
+        , ip += tmp32s;
+    )                               /* 0x80 -> 0x8F Jxx */
+        
    case 0xC2:  /* CMPSD Gx, Ex, Ib */
        nextop = F8;
        GET_EX;
@@ -129,6 +230,15 @@
        GX.q[0]=(tmp8s)?0xffffffffffffffffLL:0LL;
        break;

+    case 0xD0:  /* ADDSUBPS Gx, Ex */
+        nextop = F8;
+        GET_EX;
+        GX.f[0] -= EX->f[0];
+        GX.f[1] += EX->f[1];
+        GX.f[2] -= EX->f[2];
+        GX.f[3] += EX->f[3];
+        break;
+
    case 0xD6:  /* MOVDQ2Q Gm, Ex */
        nextop = F8;
        GET_EX;
@@ -143,6 +253,12 @@
        GX.q[1] = 0;
        break;

+    case 0xF0:  /* LDDQU Gx, Ex */
+        nextop = F8;
+        GET_EX;
+        memcpy(&GX, EX, 16);
+        break;
+
    default:
        goto _default;
    }
@@ -15,6 +15,28 @@
        GET_EX;
        EX->ud[0] = GX.ud[0];
        break;
+    case 0x12:  /* MOVSLDUP Gx, Ex */
+        nextop = F8;
+        GET_EX;
+        GX.ud[1] = GX.ud[0] = EX->ud[0];
+        GX.ud[3] = GX.ud[2] = EX->ud[2];
+        break;
+    
+    case 0x16:  /* MOVSHDUP Gx, Ex */
+        nextop = F8;
+        GET_EX;
+        GX.ud[1] = GX.ud[0] = EX->ud[1];
+        GX.ud[3] = GX.ud[2] = EX->ud[3];
+        break;
+    
+    case 0x1E:  /* NOP / ENDBR32 / ENDBR64 */
+        nextop = F8;
+        GET_ED;
+        break;
+    case 0x1F:  /* REP NOP */
+        nextop = F8;
+        GET_ED;
+        break;

    case 0x2A:  /* CVTSI2SS Gx, Ed */
        nextop = F8;
@@ -141,7 +163,7 @@
        memcpy(EX, &GX, 16);    // unaligned...
        break;

-    case 0xBC:  /* TZCNT Ew,Gw */
+    case 0xBC:  /* TZCNT Ed,Gd */
        CHECK_FLAGS(emu);
        nextop = F8;
        GET_ED;
@@ -151,7 +173,7 @@
            tmp8u = 0;
            while(!(tmp32u&(1<<tmp8u))) ++tmp8u;
            GD.dword[0] = tmp8u;
-            CONDITIONAL_SET_FLAG(tmp8u, F_ZF);
+            CONDITIONAL_SET_FLAG(tmp8u==0, F_ZF);
            CLEAR_FLAG(F_CF);
        } else {
            CLEAR_FLAG(F_ZF);
@@ -12,9 +12,12 @@
 #include "x86emu_private.h"
 #include "x87emu_private.h"
 #include "box86context.h"
-#include "x86trace.h"
 #include "x86run.h"
 #include "x86run_private.h"
+#include "callback.h"
+#ifdef DYNAREC
+#include "custommem.h"
+#endif

 typedef struct cleanup_s {
    void*       f;
@@ -35,6 +38,13 @@ static uint32_t x86emu_parity_tab[8] =
 };

 static uint8_t EndEmuMarker[] = {0xcc, 'S', 'C', 0, 0, 0, 0};
+#ifdef DYNAREC
+void DynablockEmuMarker(box86context_t* context)
+{
+    dynarec_log(LOG_DUMP, "Create bridge memory map for PushExit\n");
+    addDBFromAddressRange((uintptr_t)&EndEmuMarker[0], sizeof(EndEmuMarker), 0);
+}
+#endif
 void PushExit(x86emu_t* emu)
 {
    Push(emu, (uint32_t)&EndEmuMarker);
@@ -53,11 +63,9 @@ static void internalX86Setup(x86emu_t* emu, box86context_t *context, uintptr_t s
        emu->sbiidx[i] = &emu->regs[i];
    emu->sbiidx[4] = &emu->zero;
    emu->x86emu_parity_tab = x86emu_parity_tab;
-    emu->packed_eflags.x32 = 0x202; // default flags?
-    UnpackFlags(emu);
+    emu->eflags.x32 = 0x202; // default flags?
    // own stack?
-    if(ownstack)
-        emu->stack = (void*)stack;
+    emu->stack2free = (ownstack)?(void*)stack:NULL;
    emu->init_stack = (void*)stack;
    emu->size_stack = stacksize;
    // set default value
@@ -66,18 +74,13 @@ static void internalX86Setup(x86emu_t* emu, box86context_t *context, uintptr_t s
    // fake init of segments...
    emu->segs[_CS] = 0x73;
    emu->segs[_DS] = emu->segs[_ES] = emu->segs[_SS] = 0x7b;
-    emu->segs[_FS] = 0;
+    emu->segs[_FS] = default_fs;
    emu->segs[_GS] = 0x33;
    // setup fpu regs
    reset_fpu(emu);
-    // if trace is activated
-    if(context->x86trace) {
-        emu->dec = InitX86TraceDecoder(context);
-        if(!emu->dec)
-            printf_log(LOG_INFO, "Failed to initialize Zydis decoder and formater, no trace activated\n");
-    }
 }

+EXPORTDYN
 x86emu_t *NewX86Emu(box86context_t *context, uintptr_t start, uintptr_t stack, int stacksize, int ownstack)
 {
    printf_log(LOG_DEBUG, "Allocate a new X86 Emu, with EIP=%p and Stack=%p/0x%X\n", (void*)start, (void*)stack, stacksize);
@@ -98,101 +101,85 @@ x86emu_t *NewX86EmuFromStack(x86emu_t* emu, box86context_t *context, uintptr_t s
    return emu;
 }

+EXPORTDYN
 void SetupX86Emu(x86emu_t *emu)
 {
    printf_log(LOG_DEBUG, "Setup X86 Emu\n");
 }

-void SetTraceEmu(x86emu_t *emu, uintptr_t trace_start, uintptr_t trace_end)
+void SetTraceEmu(uintptr_t start, uintptr_t end)
 {
-    if(emu->dec) {
-        if (trace_end == 0) {
+    if(my_context->zydis) {
+        if (end == 0) {
            printf_log(LOG_INFO, "Setting trace\n");
        } else {
-            if(trace_end!=1) {  // 0-1 is basically no trace, so don't printf it...
-                printf_log(LOG_INFO, "Setting trace only between %p and %p\n", (void*)trace_start, (void*)trace_end);
+            if(end!=1) {  // 0-1 is basically no trace, so don't printf it...
+                printf_log(LOG_INFO, "Setting trace only between %p and %p\n", (void*)start, (void*)end);
            }
        }
    }
-    emu->trace_start = trace_start;
-    emu->trace_end = trace_end;
+    trace_start = start;
+    trace_end = end;
 }

 void AddCleanup(x86emu_t *emu, void *p)
 {
-    if(emu->clean_sz == emu->clean_cap) {
-        emu->clean_cap += 4;
-        emu->cleanups = (cleanup_t*)realloc(emu->cleanups, sizeof(cleanup_t)*emu->clean_cap);
+    if(my_context->clean_sz == my_context->clean_cap) {
+        my_context->clean_cap += 4;
+        my_context->cleanups = (cleanup_t*)realloc(my_context->cleanups, sizeof(cleanup_t)*my_context->clean_cap);
    }
-    emu->cleanups[emu->clean_sz].arg = 0;
-    emu->cleanups[emu->clean_sz++].f = p;
+    my_context->cleanups[my_context->clean_sz].arg = 0;
+    my_context->cleanups[my_context->clean_sz].a = NULL;
+    my_context->cleanups[my_context->clean_sz++].f = p;
 }

 void AddCleanup1Arg(x86emu_t *emu, void *p, void* a)
 {
-    if(emu->clean_sz == emu->clean_cap) {
-        emu->clean_cap += 4;
-        emu->cleanups = (cleanup_t*)realloc(emu->cleanups, sizeof(cleanup_t)*emu->clean_cap);
+    if(my_context->clean_sz == my_context->clean_cap) {
+        my_context->clean_cap += 4;
+        my_context->cleanups = (cleanup_t*)realloc(my_context->cleanups, sizeof(cleanup_t)*my_context->clean_cap);
    }
-    emu->cleanups[emu->clean_sz].arg = 1;
-    emu->cleanups[emu->clean_sz].a = a;
-    emu->cleanups[emu->clean_sz++].f = p;
+    my_context->cleanups[my_context->clean_sz].arg = 1;
+    my_context->cleanups[my_context->clean_sz].a = a;
+    my_context->cleanups[my_context->clean_sz++].f = p;
 }

 void CallCleanup(x86emu_t *emu, void* p)
 {
-    for(int i=emu->clean_sz-1; i>=0; --i) {
-        if(p==emu->cleanups[i].f) {
+    printf_log(LOG_DEBUG, "Calling atexit registered functions for %p mask\n", p);
+    for(int i=my_context->clean_sz-1; i>=0; --i) {
+        if(p==my_context->cleanups[i].f) {
            printf_log(LOG_DEBUG, "Call cleanup #%d\n", i);
-            if(emu->cleanups[i].arg)
-                Push(emu, (uintptr_t)emu->cleanups[i].a);
-            PushExit(emu);
-            emu->ip.dword[0] = (uintptr_t)(emu->cleanups[i].f);
-            Run(emu, 0);
-            emu->quit = 0;
+            RunFunctionWithEmu(emu, 0, (uintptr_t)(my_context->cleanups[i].f), my_context->cleanups[i].arg, my_context->cleanups[i].a );
            // now remove the cleanup
-            if(i!=emu->clean_sz-1)
-                memmove(emu->cleanups+i, emu->cleanups+i+1, (emu->clean_sz-i-1)*sizeof(cleanup_t));
-            --emu->clean_sz;
-            return;
+            if(i!=my_context->clean_sz-1)
+                memmove(my_context->cleanups+i, my_context->cleanups+i+1, (my_context->clean_sz-i-1)*sizeof(cleanup_t));
+            --my_context->clean_sz;
        }
    }
 }

 void CallAllCleanup(x86emu_t *emu)
 {
-    /* disabling for now...
-    for(int i=emu->clean_sz-1; i>=0; --i) {
+    printf_log(LOG_DEBUG, "Calling atexit registered functions\n");
+    for(int i=my_context->clean_sz-1; i>=0; --i) {
        printf_log(LOG_DEBUG, "Call cleanup #%d\n", i);
-        if(emu->cleanups[i].arg)
-            Push(emu, (uintptr_t)emu->cleanups[i].a);
-        PushExit(emu);
-        emu->ip.dword[0] = (uintptr_t)(emu->cleanups[i].f);
-        Run(emu);
-        emu->quit = 0;
+        RunFunctionWithEmu(emu, 0, (uintptr_t)(my_context->cleanups[i].f), my_context->cleanups[i].arg, my_context->cleanups[i].a );
    }
-    */
-    emu->clean_sz = 0;
+    my_context->clean_sz = 0;
 }

 static void internalFreeX86(x86emu_t* emu)
 {
-    // stop trace now
-    if(emu->dec)
-        DeleteX86TraceDecoder(&emu->dec);
-    emu->dec = NULL;
-    // call atexit and fini first!
-    CallAllCleanup(emu);
-    free(emu->cleanups);
-
-    free(emu->stack);
+    free(emu->stack2free);
 }

+EXPORTDYN
 void FreeX86Emu(x86emu_t **emu)
 {
    if(!emu)
        return;
-    printf_log(LOG_DEBUG, "Free a X86 Emu (%p)\n", *emu);
+    printf_log(LOG_DEBUG, "%04d|Free a X86 Emu (%p)\n", GetTID(), *emu);

    internalFreeX86(*emu);

@@ -204,21 +191,19 @@ void FreeX86EmuFromStack(x86emu_t **emu)
 {
    if(!emu)
        return;
-    printf_log(LOG_DEBUG, "Free a X86 Emu from stack (%p)\n", *emu);
+    printf_log(LOG_DEBUG, "%04d|Free a X86 Emu from stack (%p)\n", GetTID(), *emu);

    internalFreeX86(*emu);
-
-    *emu = NULL;
 }

 void CloneEmu(x86emu_t *newemu, const x86emu_t* emu)
 {
 	memcpy(newemu->regs, emu->regs, sizeof(emu->regs));
    memcpy(&newemu->ip, &emu->ip, sizeof(emu->ip));
-	memcpy(&newemu->packed_eflags, &emu->packed_eflags, sizeof(emu->packed_eflags));
-    memcpy(&newemu->flags, &emu->flags, sizeof(emu->flags));
+	memcpy(&newemu->eflags, &emu->eflags, sizeof(emu->eflags));
    newemu->old_ip = emu->old_ip;
    memcpy(newemu->segs, emu->segs, sizeof(emu->segs));
+    memset(newemu->segs_serial, 0, sizeof(newemu->segs_serial));
 	memcpy(newemu->fpu, emu->fpu, sizeof(emu->fpu));
    memcpy(newemu->fpu_ld, emu->fpu_ld, sizeof(emu->fpu_ld));
    memcpy(newemu->fpu_ll, emu->fpu_ll, sizeof(emu->fpu_ll));
@@ -234,10 +219,9 @@ void CloneEmu(x86emu_t *newemu, const x86emu_t* emu)
    newemu->mxcsr = emu->mxcsr;
    newemu->quit = emu->quit;
    newemu->error = emu->error;
-    SetTraceEmu(newemu, emu->trace_start, emu->trace_end);
-    // addapt R_ESP to new stack frame
-    uintptr_t oldst = (uintptr_t)((emu->stack)?emu->stack:emu->context->stack);
-    uintptr_t newst = (uintptr_t)((newemu->stack)?newemu->stack:newemu->context->stack);
+    // adapt R_ESP to new stack frame
+    uintptr_t oldst = (uintptr_t)((emu->init_stack)?emu->init_stack:emu->context->stack);
+    uintptr_t newst = (uintptr_t)((newemu->init_stack)?newemu->init_stack:newemu->context->stack);
    newemu->regs[_SP].dword[0] = emu->regs[_SP].dword[0] + (intptr_t)(newst - oldst);
 }

@@ -294,6 +278,14 @@ uint32_t GetESP(x86emu_t *emu)
 {
    return R_ESP;
 }
+void SetFS(x86emu_t *emu, uint16_t v)
+{
+    emu->segs[_FS] = v;
+}
+uint16_t GetFS(x86emu_t *emu)
+{
+    return emu->segs[_FS];
+}


 void ResetFlags(x86emu_t *emu)
@@ -326,11 +318,7 @@ const char* DumpCPURegs(x86emu_t* emu, uintptr_t ip)
    // start with FPU regs...
    if(emu->fpu_stack) {
        for (int i=0; i<emu->fpu_stack; i++) {
-            #ifdef USE_FLOAT
-            sprintf(tmp, "ST%d=%f", i, emu->fpu[(emu->top+i)&7].f);
-            #else
            sprintf(tmp, "ST%d=%f", i, emu->fpu[(emu->top+i)&7].d);
-            #endif
            strcat(buff, tmp);
            int c = 10-strlen(tmp);
            if(c<1) c=1;
@@ -480,3 +468,10 @@ uint64_t ReadTSC(x86emu_t* emu)
  return (uint64_t)(tv.tv_sec) * 1000000 + tv.tv_usec;
 #endif
 }
+
+void ResetSegmentsCache(x86emu_t *emu)
+{
+    if(!emu)
+        return;
+    memset(emu->segs_serial, 0, sizeof(emu->segs_serial));
+}
@@ -3,7 +3,6 @@

 #include "regs.h"

-typedef struct zydis_dec_s zydis_dec_t;
 typedef struct box86context_s box86context_t;
 typedef struct i386_ucontext_s i386_ucontext_t;

@@ -11,7 +10,10 @@ typedef struct i386_ucontext_s i386_ucontext_t;
 #define ERR_DIVBY0  2
 #define ERR_ILLEGAL 4

-typedef struct cleanup_s cleanup_t;
+#ifdef DYNAREC
+#define CSTACK      32
+#define CSTACKMASK  31
+#endif

 typedef struct forkpty_s {
    void*    amaster;
@@ -23,9 +25,9 @@ typedef struct forkpty_s {

 typedef struct x86emu_s {
    // cpu
-	reg32_t     regs[8],ip;
-    int         flags[F_LAST];
-	x86flags_t  packed_eflags;
+	reg32_t     regs[8];
+	x86flags_t  eflags;
+    reg32_t     ip;
    uintptr_t   old_ip;
    // fpu
 	fpu_reg_t   fpu[9];
@@ -52,7 +54,9 @@ typedef struct x86emu_s {
    uintptr_t   prev2_ip, prev_ip;
    #endif
    // segments
-    uint32_t    segs[6];    // only 32bits value?
+    uint32_t    segs[6];        // only 32bits value?
+    uintptr_t   segs_offs[6];   // computed offset associate with segment
+    uint32_t    segs_serial[6];  // are seg offset clean (not 0) or does they need to be re-computed (0)? For GS, serial need to be the same as context->sel_serial
    // emu control
    int         quit;
    int         error;
@@ -61,29 +65,33 @@ typedef struct x86emu_s {
    int         exit;
    int         quitonlongjmp;  // quit if longjmp is called
    int         longjmp;        // if quit because of longjmp
-    // trace
-    zydis_dec_t *dec;
-    uintptr_t   trace_start, trace_end;
    // parent context
    box86context_t *context;
+    #ifdef DYNAREC
+    // virtual return stack
+    int         cstacki;            // current index
+    uint64_t    cstack[CSTACK+1];   // pair of x86 address / native address for call/ret, using uint64_t for alignement, +1 for allignment
+    #endif
    // cpu helpers
    reg32_t     zero;
    reg32_t     *sbiidx[8];
-    // atexit and fini functions
-    cleanup_t   *cleanups;
-    int         clean_sz;
-    int         clean_cap;
    // scratch stack, used for alignement of double and 64bits ints on arm. 200 elements should be enough
    uint32_t    scratch[200];
    // local stack, do be deleted when emu is freed
-    void*       stack;
+    void*       stack2free; // this is the stack to free (can be NULL)
    void*       init_stack; // initial stack (owned or not)
    uint32_t    size_stack; // stack size (owned or not)

    i386_ucontext_t *uc_link; // to handle setcontext

+    int         type;       // EMUTYPE_xxx define
+
 } x86emu_t;

+#define EMUTYPE_NONE    0
+#define EMUTYPE_MAIN    1
+#define EMUTYPE_SIGNAL  2
+
 //#define INTR_RAISE_DIV0(emu) {emu->error |= ERR_DIVBY0; emu->quit=1;}
 #define INTR_RAISE_DIV0(emu) {emu->error |= ERR_DIVBY0;} // should rise a SIGFPE and not quit

@@ -1,3 +1,5 @@
+#define _GNU_SOURCE         /* See feature_test_macros(7) */
+#include <dlfcn.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -7,6 +9,7 @@
 #include <sys/syscall.h>
 #include <sys/types.h>
 #include <pthread.h>
+#include <signal.h>

 #include "debug.h"
 #include "box86stack.h"
@@ -21,13 +24,19 @@
 #include "box86context.h"
 #include "librarian.h"

+#include <elf.h>
+#include "elfloader.h"
+#include "elfs/elfloader_private.h"
+
 typedef int32_t (*iFpppp_t)(void*, void*, void*, void*);

 x86emu_t* x86emu_fork(x86emu_t* emu, int forktype)
 {
    // execute atforks prepare functions, in reverse order
-    for (int i=emu->context->atfork_sz-1; i>=0; --i)
-        EmuCall(emu, emu->context->atforks[i].prepare);
+    for (int i=my_context->atfork_sz-1; i>=0; --i)
+        if(my_context->atforks[i].prepare)
+            EmuCall(emu, my_context->atforks[i].prepare);
+    int type = emu->type;
    int v;
    if(forktype==2) {
        iFpppp_t forkpty = (iFpppp_t)emu->forkpty_info->f;
@@ -35,17 +44,21 @@ x86emu_t* x86emu_fork(x86emu_t* emu, int forktype)
        emu->forkpty_info = NULL;
    } else
        v = fork();
+    if(type == EMUTYPE_MAIN)
+        thread_set_emu(emu);
    if(v==EAGAIN || v==ENOMEM) {
        // error...
    } else if(v!=0) {  
        // execute atforks parent functions
-        for (int i=0; i<emu->context->atfork_sz; --i)
-            EmuCall(emu, emu->context->atforks[i].parent);
+        for (int i=0; i<my_context->atfork_sz; --i)
+            if(my_context->atforks[i].parent)
+                EmuCall(emu, my_context->atforks[i].parent);

    } else if(v==0) {
        // execute atforks child functions
-        for (int i=0; i<emu->context->atfork_sz; --i)
-            EmuCall(emu, emu->context->atforks[i].child);
+        for (int i=0; i<my_context->atfork_sz; --i)
+            if(my_context->atforks[i].child)
+                EmuCall(emu, my_context->atforks[i].child);
    }
    R_EAX = v;
    return emu;
@@ -57,6 +70,9 @@ void x86Int3(x86emu_t* emu)
    if(Peek(emu, 0)=='S' && Peek(emu, 1)=='C') // Signature for "Out of x86 door"
    {
        R_EIP += 2;
+        #ifdef RK3399
+        volatile    // to avoid addr to be put in an VFPU register
+        #endif
        uint32_t addr = Fetch32(emu);
        if(addr==0) {
            //printf_log(LOG_INFO, "%p:Exit x86 emu (emu=%p)\n", *(void**)(R_ESP), emu);
@@ -65,9 +81,13 @@ void x86Int3(x86emu_t* emu)
            RESET_FLAGS(emu);
            wrapper_t w = (wrapper_t)addr;
            addr = Fetch32(emu);
-            if(box86_log>=LOG_DEBUG /*&& emu->trace_end==0 && !emu->context->x86trace*/) {
+            /* This party can be used to trace only 1 specific lib (but it is quite slow)
+            elfheader_t *h = FindElfAddress(my_context, *(uintptr_t*)(R_ESP));
+            int have_trace = 0;
+            if(h && strstr(ElfName(h), "libMiles")) have_trace = 1;*/
+            if(box86_log>=LOG_DEBUG /*|| have_trace*/) {
                pthread_mutex_lock(&emu->context->mutex_trace);
-                int tid = syscall(SYS_gettid);
+                int tid = GetTID();
                char buff[256] = "\0";
                char buff2[64] = "\0";
                char buff3[64] = "\0";
@@ -75,107 +95,169 @@ void x86Int3(x86emu_t* emu)
                int post = 0;
                int perr = 0;
                uint32_t *pu32 = NULL;
-                const char *s = GetNativeName(emu, (void*)addr);
+                const char *s = NULL;
+                {
+                    Dl_info info;
+                    if(dladdr((void*)addr, &info))
+                        s = info.dli_sname;
+                }
+                if(!s) s = GetNativeName((void*)addr);
                if(addr==(uintptr_t)PltResolver) {
                    snprintf(buff, 256, "%s", " ... ");
                } else
                if(strstr(s, "SDL_RWFromFile")==s || strstr(s, "SDL_RWFromFile")==s) {
                    snprintf(buff, 255, "%04d|%p: Calling %s(%s, %s)", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(char**)(R_ESP+8));
                } else  if(strstr(s, "glColor4f")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f, %f, %f)", tid, *(void**)(R_ESP), "glColor4f", *(float*)(R_ESP+4), *(float*)(R_ESP+8), *(float*)(R_ESP+12), *(float*)(R_ESP+16));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f, %f, %f)", tid, *(void**)(R_ESP), s, *(float*)(R_ESP+4), *(float*)(R_ESP+8), *(float*)(R_ESP+12), *(float*)(R_ESP+16));
                } else  if(strstr(s, "glTexCoord2f")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f)", tid, *(void**)(R_ESP), "glTexCoord2f", *(float*)(R_ESP+4), *(float*)(R_ESP+8));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f)", tid, *(void**)(R_ESP), s, *(float*)(R_ESP+4), *(float*)(R_ESP+8));
                } else  if(strstr(s, "glVertex2f")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f)", tid, *(void**)(R_ESP), "glVertex2f", *(float*)(R_ESP+4), *(float*)(R_ESP+8));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f)", tid, *(void**)(R_ESP), s, *(float*)(R_ESP+4), *(float*)(R_ESP+8));
                } else  if(strstr(s, "glVertex3f")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f, %f)", tid, *(void**)(R_ESP), "glVertex3f", *(float*)(R_ESP+4), *(float*)(R_ESP+8), *(float*)(R_ESP+12));
-                } else  if(strstr(s, "__open64")==s || strstr(s, "open64")==s || strstr(s, "open64")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", %d, %d)", tid, *(void**)(R_ESP), "open64", *(char**)(R_ESP+4), *(int*)(R_ESP+8), *(int*)(R_ESP+12));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f, %f)", tid, *(void**)(R_ESP), s, *(float*)(R_ESP+4), *(float*)(R_ESP+8), *(float*)(R_ESP+12));
+                } else  if(strstr(s, "__open64")==s || strcmp(s, "open64")==0) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", %d, %d)", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(int*)(R_ESP+8), *(int*)(R_ESP+12));
                    perr = 1;
-                } else  if(strstr(s, "__open")==s || strstr(s, "open")==s || strstr(s, "open")==s) {
+                } else  if(!strcmp(s, "opendir")) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\")", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4));
+                    perr = 1;
+                } else  if(strstr(s, "__open")==s || strcmp(s, "open")==0) {
+                    tmp = *(char**)(R_ESP+4);
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", %d (,%d))", tid, *(void**)(R_ESP), s, (tmp)?tmp:"(nil)", *(int*)(R_ESP+8), *(int*)(R_ESP+12));
+                    perr = 1;
+                } else  if(strcmp(s, "mkdir")==0) {
                    tmp = *(char**)(R_ESP+4);
                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", %d)", tid, *(void**)(R_ESP), s, (tmp)?tmp:"(nil)", *(int*)(R_ESP+8));
                    perr = 1;
-                } else  if(strstr(s, "fopen")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\")", tid, *(void**)(R_ESP), "fopen", *(char**)(R_ESP+4), *(char**)(R_ESP+8));
+                } else  if(!strcmp(s, "fopen")) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\")", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(char**)(R_ESP+8));
                    perr = 1;
-                } else  if(strstr(s, "chdir")==s) {
+                } else  if(!strcmp(s, "freopen")) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\", %p)", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(char**)(R_ESP+8), *(void**)(R_ESP+12));
+                    perr = 1;
+                } else  if(!strcmp(s, "fopen64")) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\")", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(char**)(R_ESP+8));
+                    perr = 2;
+                } else  if(!strcmp(s, "chdir")) {
                    pu32=*(uint32_t**)(R_ESP+4);
-                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\")", tid, *(void**)(R_ESP), "chdir", pu32?((pu32==(uint32_t*)1)?"/1/":(char*)pu32):"/0/");
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\")", tid, *(void**)(R_ESP), s, pu32?((pu32==(uint32_t*)1)?"/1/":(char*)pu32):"/0/");
                } else  if(strstr(s, "getenv")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\")", tid, *(void**)(R_ESP), "getenv", *(char**)(R_ESP+4));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\")", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4));
                    post = 2;
                } else  if(strstr(s, "pread")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p, %u, %i)", tid, *(void**)(R_ESP), "pread", *(int32_t*)(R_ESP+4), *(void**)(R_ESP+8), *(uint32_t*)(R_ESP+12), *(int32_t*)(R_ESP+16));
-                } else  if(strstr(s, "statvfs64")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%p(\"%s\"), %p)", tid, *(void**)(R_ESP), "statvfs64", *(void**)(R_ESP+4), *(char**)(R_ESP+4), *(void**)(R_ESP+8));
-                } else  if(strstr(s, "index")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%p(\"%s\"), %i(%c))", tid, *(void**)(R_ESP), "index", *(char**)(R_ESP+4), *(char**)(R_ESP+4), *(int32_t*)(R_ESP+8), *(int32_t*)(R_ESP+8));
-                } else  if(strstr(s, "rindex")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%p(\"%s\"), %i(%c))", tid, *(void**)(R_ESP), "rindex", *(char**)(R_ESP+4), *(char**)(R_ESP+4), *(int32_t*)(R_ESP+8), *(int32_t*)(R_ESP+8));
-                } else  if(strstr(s, "__xstat64")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p(\"%s\"), %p)", tid, *(void**)(R_ESP), "__xstat64", *(int32_t*)(R_ESP+4), *(char**)(R_ESP+8), *(char**)(R_ESP+8), *(void**)(R_ESP+12));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p, %u, %d)", tid, *(void**)(R_ESP), s, *(int32_t*)(R_ESP+4), *(void**)(R_ESP+8), *(uint32_t*)(R_ESP+12), *(int32_t*)(R_ESP+16));
                    perr = 1;
-                } else  if(strstr(s, "__lxstat64")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p(\"%s\"), %p)", tid, *(void**)(R_ESP), "__lxstat64", *(int32_t*)(R_ESP+4), *(char**)(R_ESP+8), *(char**)(R_ESP+8), *(void**)(R_ESP+12));
+                } else  if(strstr(s, "ioctl")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, 0x%x, %p)", tid, *(void**)(R_ESP), s, *(int32_t*)(R_ESP+4), *(int32_t*)(R_ESP+8), *(void**)(R_ESP+12));
+                    perr = 1;
+                } else  if(strstr(s, "statvfs64")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p(\"%s\"), %p)", tid, *(void**)(R_ESP), s, *(void**)(R_ESP+4), *(char**)(R_ESP+4), *(void**)(R_ESP+8));
+                } else  if(strstr(s, "index")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p(\"%s\"), %i(%c))", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(char**)(R_ESP+4), *(int32_t*)(R_ESP+8), *(int32_t*)(R_ESP+8));
+                } else  if(strstr(s, "rindex")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p(\"%s\"), %i(%c))", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(char**)(R_ESP+4), *(int32_t*)(R_ESP+8), *(int32_t*)(R_ESP+8));
+                } else  if(strstr(s, "my___xstat64")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p(\"%s\"), %p)", tid, *(void**)(R_ESP), s, *(int32_t*)(R_ESP+4), *(char**)(R_ESP+8), *(char**)(R_ESP+8), *(void**)(R_ESP+12));
+                    perr = 1;
+                } else  if(strcmp(s, "my___xstat")==0) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p(\"%s\"), %p)", tid, *(void**)(R_ESP), s, *(int32_t*)(R_ESP+4), *(char**)(R_ESP+8), *(char**)(R_ESP+8), *(void**)(R_ESP+12));
+                    perr = 1;
+                } else  if(strstr(s, "my___lxstat64")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p(\"%s\"), %p)", tid, *(void**)(R_ESP), s, *(int32_t*)(R_ESP+4), *(char**)(R_ESP+8), *(char**)(R_ESP+8), *(void**)(R_ESP+12));
                    perr = 1;
                } else  if(strstr(s, "sem_timedwait")==s) {
                    pu32 = *(uint32_t**)(R_ESP+8);
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, %p[%d sec %d ns])", tid, *(void**)(R_ESP), "sem_timedwait", *(void**)(R_ESP+4), *(void**)(R_ESP+8), pu32?pu32[0]:-1, pu32?pu32[1]:-1);
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, %p[%d sec %d ns])", tid, *(void**)(R_ESP), s, *(void**)(R_ESP+4), *(void**)(R_ESP+8), pu32?pu32[0]:-1, pu32?pu32[1]:-1);
+                    perr = 1;
+                } else  if(strstr(s, "waitpid")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p, 0x%x)", tid, *(void**)(R_ESP), s, *(int32_t*)(R_ESP+4), *(void**)(R_ESP+8), *(uint32_t*)(R_ESP+12));
                    perr = 1;
                } else  if(strstr(s, "clock_gettime")==s || strstr(s, "__clock_gettime")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p)", tid, *(void**)(R_ESP), "clock_gettime", *(uint32_t*)(R_ESP+4), *(void**)(R_ESP+8));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p)", tid, *(void**)(R_ESP), s, *(uint32_t*)(R_ESP+4), *(void**)(R_ESP+8));
                    post = 1;
                    pu32 = *(uint32_t**)(R_ESP+8);
+                } else  if(strstr(s, "semop")==s) {
+                    int16_t* p16 = *(int16_t**)(R_ESP+8);
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p[%u/%d/%d], %d)", tid, *(void**)(R_ESP), s, *(int*)(R_ESP+4), p16, p16[0], p16[1], p16[2], *(int*)(R_ESP+12));
+                    perr = 1;
+                } else  if(!strcmp(s, "my_mmap64")) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, 0x%x, %d, 0x%x, %d, %lld)", tid, *(void**)(R_ESP), s, *(void**)(R_ESP+4), *(size_t*)(R_ESP+8), *(int*)(R_ESP+12), *(int*)(R_ESP+16), *(int*)(R_ESP+20), *(int64_t*)(R_ESP+24));
+                    perr = 1;
+                } else  if(!strcmp(s, "my_mmap")) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, 0x%x, %d, 0x%x, %d, %d)", tid, *(void**)(R_ESP), s, *(void**)(R_ESP+4), *(size_t*)(R_ESP+8), *(int*)(R_ESP+12), *(int*)(R_ESP+16), *(int*)(R_ESP+20), *(int*)(R_ESP+24));
+                    perr = 1;
                } else  if(strstr(s, "strcasecmp")==s || strstr(s, "__strcasecmp")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\")", tid, *(void**)(R_ESP), "strcasecmp", *(char**)(R_ESP+4), *(char**)(R_ESP+8));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\")", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(char**)(R_ESP+8));
                } else  if(strstr(s, "gtk_signal_connect_full")) {
                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, \"%s\", %p, %p, %p, %p, %d, %d)", tid, *(void**)(R_ESP), "gtk_signal_connect_full", *(void**)(R_ESP+4), *(char**)(R_ESP+8), *(void**)(R_ESP+12), *(void**)(R_ESP+16), *(void**)(R_ESP+20), *(void**)(R_ESP+24), *(int32_t*)(R_ESP+28), *(int32_t*)(R_ESP+32));
-                } else  if(strstr(s, "strncasecmp")==s || strstr(s, "__strncasecmp")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\", %u)", tid, *(void**)(R_ESP), "strcasecmp", *(char**)(R_ESP+4), *(char**)(R_ESP+8), *(uint32_t*)(R_ESP+12));
                } else  if(strstr(s, "strcmp")==s || strstr(s, "__strcmp")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\")", tid, *(void**)(R_ESP), "strcmp", *(char**)(R_ESP+4), *(char**)(R_ESP+8));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\")", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(char**)(R_ESP+8));
                } else  if(strstr(s, "strstr")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\")", tid, *(void**)(R_ESP), "strstr", *(char**)(R_ESP+4), *(char**)(R_ESP+8));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%.127s\", \"%.127s\")", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(char**)(R_ESP+8));
                } else  if(strstr(s, "strlen")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%p(\"%s\"))", tid, *(void**)(R_ESP), "strlen", *(char**)(R_ESP+4), ((R_ESP+4))?(*(char**)(R_ESP+4)):"nil");
-                } else  if(strstr(s, "vsnprintf")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%08X, %u, %08X...)", tid, *(void**)(R_ESP), "vsnprintf", *(uint32_t*)(R_ESP+4), *(uint32_t*)(R_ESP+8), *(uint32_t*)(R_ESP+12));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p(\"%s\"))", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), ((R_ESP+4))?(*(char**)(R_ESP+4)):"nil");
+                } else  if(strstr(s, "my_vsnprintf")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%08X, %u, %08X...)", tid, *(void**)(R_ESP), s, *(uint32_t*)(R_ESP+4), *(uint32_t*)(R_ESP+8), *(uint32_t*)(R_ESP+12));
                    pu32 = *(uint32_t**)(R_ESP+4);
                    post = 3;
-                } else  if(strstr(s, "vsprintf")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%08X, \"%s\"...)", tid, *(void**)(R_ESP), "vsprintf", *(uint32_t*)(R_ESP+4), *(char**)(R_ESP+8));
+                } else  if(strstr(s, "my_vsprintf")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%08X, \"%s\"...)", tid, *(void**)(R_ESP), s, *(uint32_t*)(R_ESP+4), *(char**)(R_ESP+8));
                    pu32 = *(uint32_t**)(R_ESP+4);
                    post = 3;
-                } else  if(strstr(s, "snprintf")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%08X, %u, %08X...)", tid, *(void**)(R_ESP), "snprintf", *(uint32_t*)(R_ESP+4), *(uint32_t*)(R_ESP+8), *(uint32_t*)(R_ESP+12));
+                } else  if(strstr(s, "my_snprintf")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%08X, %u, %08X...)", tid, *(void**)(R_ESP), s, *(uint32_t*)(R_ESP+4), *(uint32_t*)(R_ESP+8), *(uint32_t*)(R_ESP+12));
                    pu32 = *(uint32_t**)(R_ESP+4);
                    post = 3;
-                } else  if(strstr(s, "sprintf")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%08X, %08X...)", tid, *(void**)(R_ESP), "sprintf", *(uint32_t*)(R_ESP+4), *(uint32_t*)(R_ESP+8));
+                } else  if(strstr(s, "my_sprintf")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%08X, %08X...)", tid, *(void**)(R_ESP), s, *(uint32_t*)(R_ESP+4), *(uint32_t*)(R_ESP+8));
                    pu32 = *(uint32_t**)(R_ESP+4);
                    post = 3;
-                } else  if(strstr(s, "fprintf")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%08X, \"%s\", ...)", tid, *(void**)(R_ESP), "fprintf", *(uint32_t*)(R_ESP+4), *(char**)(R_ESP+8));
+                } else  if(strstr(s, "my_printf")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\"...)", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4));
+                } else  if(strstr(s, "puts")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\"...)", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4));
+                } else  if(strstr(s, "fputs")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", %p...)", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(void**)(R_ESP+8));
+                } else  if(strstr(s, "my_fprintf")==s) {
+                    pu32 = *(uint32_t**)(R_ESP+8);
+                    if(((uintptr_t)pu32)<0x5) // probably a __fprint_chk
+                        pu32 = *(uint32_t**)(R_ESP+12);
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%08X, \"%s\", ...)", tid, *(void**)(R_ESP), s, *(uint32_t*)(R_ESP+4), pu32?((char*)(pu32)):"nil");
+                } else  if(strstr(s, "my_vfprintf")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%08X, \"%s\", ...)", tid, *(void**)(R_ESP), s, *(uint32_t*)(R_ESP+4), *(char**)(R_ESP+8));
+                } else  if(strstr(s, "vkGetInstanceProcAddr")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, \"%s\")", tid, *(void**)(R_ESP), s, *(void**)(R_ESP+4), *(char**)(R_ESP+8));
+                } else  if(strstr(s, "vkGetDeviceProcAddr")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, \"%s\")", tid, *(void**)(R_ESP), s, *(void**)(R_ESP+4), *(char**)(R_ESP+8));
+                } else  if(strstr(s, "my_sscanf")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\", ...)", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(char**)(R_ESP+8));
+                } else  if(strstr(s, "vsscanf")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(\"%s\", \"%s\", ...)", tid, *(void**)(R_ESP), s, *(char**)(R_ESP+4), *(char**)(R_ESP+8));
                } else if(strstr(s, "XCreateWindow")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, %p, %d, %d, %u, %u, %u, %d, %u, %p, %u, %p)", tid, *(void**)(R_ESP), "XCreateWindow", *(void**)(R_ESP+4), *(void**)(R_ESP+8), *(int*)(R_ESP+12), *(int*)(R_ESP+16), *(uint32_t*)(R_ESP+20), *(uint32_t*)(R_ESP+24), *(uint32_t*)(R_ESP+28), *(int32_t*)(R_ESP+32), *(uint32_t*)(R_ESP+36), *(void**)(R_ESP+40), *(uint32_t*)(R_ESP+44), *(void**)(R_ESP+48));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, %p, %d, %d, %u, %u, %u, %d, %u, %p, %u, %p)", tid, *(void**)(R_ESP), s, *(void**)(R_ESP+4), *(void**)(R_ESP+8), *(int*)(R_ESP+12), *(int*)(R_ESP+16), *(uint32_t*)(R_ESP+20), *(uint32_t*)(R_ESP+24), *(uint32_t*)(R_ESP+28), *(int32_t*)(R_ESP+32), *(uint32_t*)(R_ESP+36), *(void**)(R_ESP+40), *(uint32_t*)(R_ESP+44), *(void**)(R_ESP+48));
                } else if(strstr(s, "XLoadQueryFont")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, \"%s\")", tid, *(void**)(R_ESP), "XLoadQueryFont", *(void**)(R_ESP+4), *(char**)(R_ESP+8));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, \"%s\")", tid, *(void**)(R_ESP), s, *(void**)(R_ESP+4), *(char**)(R_ESP+8));
                } else if(strstr(s, "pthread_mutex_lock")==s) {
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%p)", tid, *(void**)(R_ESP), "pthread_mutex_lock", *(void**)(R_ESP+4));
-                } else if(strstr(s, "fmodf")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p)", tid, *(void**)(R_ESP), s, *(void**)(R_ESP+4));
+                } else if(!strcmp(s, "fmodf")) {
                    post = 4;
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f)", tid, *(void**)(R_ESP), "fmodf", *(float*)(R_ESP+4), *(float*)(R_ESP+8));
-                } else if(strstr(s, "fmod")==s) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f)", tid, *(void**)(R_ESP), s, *(float*)(R_ESP+4), *(float*)(R_ESP+8));
+                } else if(!strcmp(s, "fmod")) {
                    post = 4;
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f)", tid, *(void**)(R_ESP), "fmod", *(double*)(R_ESP+4), *(double*)(R_ESP+12));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%f, %f)", tid, *(void**)(R_ESP), s, *(double*)(R_ESP+4), *(double*)(R_ESP+12));
                } else if(strstr(s, "SDL_GetWindowSurface")==s) {
                    post = 5;
-                    snprintf(buff, 255, "%04d|%p: Calling %s(%p)", tid, *(void**)(R_ESP), "SDL_GetWindowSurface", *(void**)(R_ESP+4));
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p)", tid, *(void**)(R_ESP), s, *(void**)(R_ESP+4));
+                } else if(strstr(s, "udev_monitor_new_from_netlink")==s) {
+                    post = 5;
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%p, \"%s\")", tid, *(void**)(R_ESP), s, *(void**)(R_ESP+4), *(char**)(R_ESP+8));
+                } else  if(!strcmp(s, "my_syscall")) {
+                    snprintf(buff, 255, "%04d|%p: Calling %s(%d, %p, %p, %p...)", tid, *(void**)(R_ESP), s, *(int32_t*)(R_ESP+4), *(void**)(R_ESP+8), *(void**)(R_ESP+12), *(void**)(R_ESP+16));
+                    perr = 1;
                } else {
                    snprintf(buff, 255, "%04d|%p: Calling %s (%08X, %08X, %08X...)", tid, *(void**)(R_ESP), s, *(uint32_t*)(R_ESP+4), *(uint32_t*)(R_ESP+8), *(uint32_t*)(R_ESP+12));
                }
-                printf_log(LOG_DEBUG, "%s =>", buff);
+                printf_log(LOG_NONE, "%s =>", buff);
                pthread_mutex_unlock(&emu->context->mutex_trace);
                w(emu, addr);   // some function never come back, so unlock the mutex first!
                pthread_mutex_lock(&emu->context->mutex_trace);
@@ -187,11 +269,7 @@ void x86Int3(x86emu_t* emu)
                            break;
                    case 3: snprintf(buff2, 63, "(%s)", pu32?((char*)pu32):"nil");
                            break;
-                    #ifdef USE_FLOAT
-                    case 4: snprintf(buff2, 63, " (%f)", ST0.f);
-                    #else
                    case 4: snprintf(buff2, 63, " (%f)", ST0.d);
-                    #endif
                            break;
                    case 5: {
                            uint32_t* p = (uint32_t*)R_EAX;
@@ -202,15 +280,25 @@ void x86Int3(x86emu_t* emu)
                            }
                            break;
                }
-                if(perr && ((int)R_EAX)<0)
-                    snprintf(buff3, 63, " (errno=%d)", errno);
-                printf_log(LOG_DEBUG, " return 0x%08X%s%s\n", R_EAX, buff2, buff3);
+                if(perr==1 && ((int)R_EAX)<0)
+                    snprintf(buff3, 63, " (errno=%d:\"%s\")", errno, strerror(errno));
+                else if(perr==2 && R_EAX==0)
+                    snprintf(buff3, 63, " (errno=%d:\"%s\")", errno, strerror(errno));
+                printf_log(LOG_NONE, " return 0x%08X%s%s\n", R_EAX, buff2, buff3);
                pthread_mutex_unlock(&emu->context->mutex_trace);
            } else
                w(emu, addr);
        }
        return;
    }
-    printf_log(LOG_INFO, "Warning, ignoring unsupported Int 3 call\n");
+    if(my_context->signals[SIGTRAP])
+        raise(SIGTRAP);
+    else
+        printf_log(LOG_INFO, "Warning, ignoring unsupported Int 3 call\n");
    //emu->quit = 1;
 }
+
+int GetTID()
+{
+    return syscall(SYS_gettid);
+}
@@ -714,7 +714,7 @@ uint8_t rol8(x86emu_t *emu, uint8_t d, uint8_t s)
 	if((cnt = s % 8) != 0) {
 	d = (d << cnt) + ((d >> (8 - cnt)) & ((1 << cnt) - 1));
 	}
-	CHECK_FLAGS(emu);
+	RESET_FLAGS(emu);

 	/* OF flag is set if s == 1; OF = CF _XOR_ MSB of result */
 	if(s == 1) {
@@ -741,7 +741,7 @@ uint16_t rol16(x86emu_t *emu, uint16_t d, uint8_t s)
 	if((cnt = s % 16) != 0) {
 	d = (d << cnt) + ((d >> (16 - cnt)) & ((1 << cnt) - 1));
 	}
-	CHECK_FLAGS(emu);
+	RESET_FLAGS(emu);

 	/* OF flag is set if s == 1; OF = CF _XOR_ MSB of result */
 	if(s == 1) {
@@ -768,7 +768,7 @@ uint32_t rol32(x86emu_t *emu, uint32_t d, uint8_t s)
 	if((cnt = s % 32) != 0) {
 	d = (d << cnt) + ((d >> (32 - cnt)) & ((1 << cnt) - 1));
 	}
-	CHECK_FLAGS(emu);
+	RESET_FLAGS(emu);

 	/* OF flag is set if s == 1; OF = CF _XOR_ MSB of result */
 	if(s == 1) {
@@ -795,7 +795,7 @@ uint8_t ror8(x86emu_t *emu, uint8_t d, uint8_t s)
 	if((cnt = s % 8) != 0) {
 	d = (d << (8 - cnt)) + ((d >> (cnt)) & ((1 << (8 - cnt)) - 1));
 	}
-	CHECK_FLAGS(emu);
+	RESET_FLAGS(emu);

 	/* OF flag is set if s == 1; OF = MSB _XOR_ (M-1)SB of result */
 	if(s == 1) {
@@ -822,7 +822,7 @@ uint16_t ror16(x86emu_t *emu, uint16_t d, uint8_t s)
 	if((cnt = s % 16) != 0) {
 	d = (d << (16 - cnt)) + ((d >> (cnt)) & ((1 << (16 - cnt)) - 1));
 	}
-	CHECK_FLAGS(emu);
+	RESET_FLAGS(emu);

 	/* OF flag is set if s == 1; OF = MSB _XOR_ (M-1)SB of result */
 	if(s == 1) {
@@ -849,7 +849,7 @@ uint32_t ror32(x86emu_t *emu, uint32_t d, uint8_t s)
 	if((cnt = s % 32) != 0) {
 	d = (d << (32 - cnt)) + ((d >> (cnt)) & ((1 << (32 - cnt)) - 1));
 	}
-	CHECK_FLAGS(emu);
+	RESET_FLAGS(emu);

 	/* OF flag is set if s == 1; OF = MSB _XOR_ (M-1)SB of result */
 	if(s == 1) {
@@ -891,7 +891,7 @@ uint16_t shld16 (x86emu_t *emu, uint16_t d, uint16_t fill, uint8_t s)
 			CLEAR_FLAG(F_OF);
 		}
 	} else {
-		res = (fill << (cnt)) | (fill >> (16 - cnt));
+		res = (fill << (cnt)) | (d >> (16 - cnt));
 		if(s==16)
 			cf = d & 1;
 		else
@@ -965,7 +965,7 @@ uint16_t shrd16 (x86emu_t *emu, uint16_t d, uint16_t fill, uint8_t s)
        }
 	} else {
 		cf = fill & (1 << (cnt - 1));
-		res = (fill >> cnt) | (fill << (16 - cnt));
+		res = (fill >> cnt) | (d << (16 - cnt));
 		CONDITIONAL_SET_FLAG(cf, F_CF);
 		CONDITIONAL_SET_FLAG((res & 0xffff) == 0, F_ZF);
 		CONDITIONAL_SET_FLAG(res & 0x8000, F_SF);
@@ -1153,7 +1153,7 @@ Implements the IDIV instruction and side effects.
 ****************************************************************************/
 void idiv8(x86emu_t *emu, uint8_t s)
 {
-    int32_t dvd, div, mod;
+    int32_t dvd, quot, mod;
 	RESET_FLAGS(emu);

 	dvd = (int16_t)R_AX;
@@ -1161,13 +1161,14 @@ void idiv8(x86emu_t *emu, uint8_t s)
 		INTR_RAISE_DIV0(emu);
        return;
 	}
-	div = dvd / (int8_t)s;
-	mod = dvd % (int8_t)s;
-	if (abs(div) > 0x7f) {
+	div_t p = div(dvd, (int8_t)s);
+	quot = p.quot;
+	mod = p.rem;
+	if (abs(quot) > 0x7f) {
 		INTR_RAISE_DIV0(emu);
 		return;
 	}
-	R_AL = (int8_t) div;
+	R_AL = (int8_t) quot;
 	R_AH = (int8_t) mod;
 }

@@ -1177,25 +1178,26 @@ Implements the IDIV instruction and side effects.
 ****************************************************************************/
 void idiv16(x86emu_t *emu, uint16_t s)
 {
-	int32_t dvd, div, mod;
+	int32_t dvd, quot, mod;

 	dvd = (((int32_t)R_DX) << 16) | R_AX;
 	if (s == 0) {
 		INTR_RAISE_DIV0(emu);
 		return;
 	}
-	div = dvd / (int16_t)s;
-	mod = dvd % (int16_t)s;
-	if (abs(div) > 0x7fff) {
+	div_t p = div(dvd, (int16_t)s);
+	quot = p.quot;
+	mod = p.rem;
+	if (abs(quot) > 0x7fff) {
 		INTR_RAISE_DIV0(emu);
 		return;
 	}
 	CLEAR_FLAG(F_CF);
 	CLEAR_FLAG(F_SF);
-	CONDITIONAL_SET_FLAG(div == 0, F_ZF);
+	CONDITIONAL_SET_FLAG(quot == 0, F_ZF);
 	CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF);

-	R_AX = (uint16_t)div;
+	R_AX = (uint16_t)quot;
 	R_DX = (uint16_t)mod;
 }

@@ -1205,7 +1207,7 @@ Implements the IDIV instruction and side effects.
 ****************************************************************************/
 void idiv32(x86emu_t *emu, uint32_t s)
 {
-	int64_t dvd, div, mod;
+	int64_t dvd, quot, mod;
 	RESET_FLAGS(emu);

 	dvd = (((int64_t)R_EDX) << 32) | R_EAX;
@@ -1213,9 +1215,10 @@ void idiv32(x86emu_t *emu, uint32_t s)
 		INTR_RAISE_DIV0(emu);
 		return;
 	}
-	div = dvd / (int32_t)s;
-	mod = dvd % (int32_t)s;
-	if (llabs(div) > 0x7fffffff) {
+	lldiv_t p = lldiv(dvd, (int32_t)s);
+	quot = p.quot;
+	mod = p.rem;
+	if (llabs(quot) > 0x7fffffff) {
 		INTR_RAISE_DIV0(emu);
 		return;
 	}
@@ -1225,7 +1228,7 @@ void idiv32(x86emu_t *emu, uint32_t s)
 	SET_FLAG(F_ZF);
 	CONDITIONAL_SET_FLAG(PARITY(mod & 0xff), F_PF);

-	R_EAX = (uint32_t)div;
+	R_EAX = (uint32_t)quot;
 	R_EDX = (uint32_t)mod;
 }

@@ -81,8 +81,6 @@ Implements the AND instruction and side effects.
 ****************************************************************************/
 static inline uint32_t and32(x86emu_t *emu, uint32_t d, uint32_t s)
 {
-	register uint32_t res;   /* all operands in native machine order */
-
 	emu->res = d & s;
 	emu->df = d_and32;

@@ -161,6 +159,14 @@ Implements the INC instruction and side effects.
 ****************************************************************************/
 static inline uint32_t inc32(x86emu_t *emu, uint32_t d)
 {
+	if(emu->df == d_shr32) {
+		// workaround for some wine trickery
+		uint32_t cnt = emu->op2;
+        if (cnt > 0) {
+            uint32_t cc = emu->op1 & (1 << (cnt - 1));
+			CONDITIONAL_SET_FLAG(cc, F_CF);
+		}
+	}
 	emu->res = d + 1;
 	emu->op1 = d;
 	emu->df = d_inc32;
@@ -507,7 +513,7 @@ static inline uint32_t xor32(x86emu_t *emu, uint32_t d, uint32_t s)
 REMARKS:
 Implements the IMUL instruction and side effects.
 ****************************************************************************/
-static void imul8(x86emu_t *emu, uint8_t s)
+static inline void imul8(x86emu_t *emu, uint8_t s)
 {
 	emu->df = d_imul8;
 	R_AX = emu->res = (int16_t)(int8_t)R_AL * (int8_t)s;
@@ -516,7 +522,7 @@ static void imul8(x86emu_t *emu, uint8_t s)
 REMARKS:
 Implements the IMUL instruction and side effects.
 ****************************************************************************/
-static void imul16_eax(x86emu_t *emu, uint16_t s)
+static inline void imul16_eax(x86emu_t *emu, uint16_t s)
 {
 	emu->df = d_imul16;
 	emu->res = (int32_t)(int16_t)R_AX * (int16_t)s;
@@ -527,7 +533,7 @@ static void imul16_eax(x86emu_t *emu, uint16_t s)
 REMARKS:
 Implements the IMUL instruction and side effects.
 ****************************************************************************/
-static uint16_t imul16(x86emu_t *emu, uint16_t op1, uint16_t op2)
+static inline uint16_t imul16(x86emu_t *emu, uint16_t op1, uint16_t op2)
 {
 	emu->df = d_imul16;
 	emu->res = (int32_t)(int16_t)op1 * (int16_t)op2;
@@ -537,7 +543,7 @@ static uint16_t imul16(x86emu_t *emu, uint16_t op1, uint16_t op2)
 REMARKS:
 Implements the IMUL instruction and side effects.
 ****************************************************************************/
-static void imul32_direct(uint32_t *res_lo, uint32_t* res_hi,uint32_t d, uint32_t s)
+static inline void imul32_direct(uint32_t *res_lo, uint32_t* res_hi,uint32_t d, uint32_t s)
 {
 	int64_t res = (int64_t)(int32_t)d * (int32_t)s;

@@ -548,7 +554,7 @@ static void imul32_direct(uint32_t *res_lo, uint32_t* res_hi,uint32_t d, uint32_
 REMARKS:
 Implements the IMUL instruction and side effects.
 ****************************************************************************/
-static uint32_t imul32(x86emu_t *emu, uint32_t op1, uint32_t op2)
+static inline uint32_t imul32(x86emu_t *emu, uint32_t op1, uint32_t op2)
 {
 	emu->df = d_imul32;
 	imul32_direct(&emu->res,&emu->op1,op1,op2);
@@ -558,7 +564,7 @@ static uint32_t imul32(x86emu_t *emu, uint32_t op1, uint32_t op2)
 REMARKS:
 Implements the IMUL instruction and side effects.
 ****************************************************************************/
-static void imul32_eax(x86emu_t *emu, uint32_t s)
+static inline void imul32_eax(x86emu_t *emu, uint32_t s)
 {
 	emu->df = d_imul32;
 	imul32_direct(&R_EAX,&R_EDX,R_EAX,s);
@@ -569,7 +575,7 @@ static void imul32_eax(x86emu_t *emu, uint32_t s)
 REMARKS:
 Implements the MUL instruction and side effects.
 ****************************************************************************/
-static void mul8(x86emu_t *emu, uint8_t s)
+static inline void mul8(x86emu_t *emu, uint8_t s)
 {
 	emu->df = d_mul8;
 	R_AX = emu->res = (uint16_t)(R_AL) * s;
@@ -578,7 +584,7 @@ static void mul8(x86emu_t *emu, uint8_t s)
 REMARKS:
 Implements the MUL instruction and side effects.
 ****************************************************************************/
-static void mul16(x86emu_t *emu, uint16_t s)
+static inline void mul16(x86emu_t *emu, uint16_t s)
 {
 	emu->df = d_mul16;
 	emu->res = (uint32_t)R_AX * s;
@@ -589,7 +595,7 @@ static void mul16(x86emu_t *emu, uint16_t s)
 REMARKS:
 Implements the MUL instruction and side effects.
 ****************************************************************************/
-static void mul32_eax(x86emu_t *emu, uint32_t s)
+static inline void mul32_eax(x86emu_t *emu, uint32_t s)
 {
 	emu->df = d_mul32;
 	uint64_t res = (uint64_t)R_EAX * s;
@@ -18,6 +18,11 @@
 #include "x86trace.h"
 #include "x87emu_private.h"
 #include "box86context.h"
+#include "my_cpuid.h"
+#include "bridge.h"
+#ifdef DYNAREC
+#include "../dynarec/arm_lock_helper.h"
+#endif

 int my_setcontext(x86emu_t* emu, void* ucp);

@@ -26,7 +31,6 @@ int Run(x86emu_t *emu, int step)
    uint8_t opcode;
    uint8_t nextop;
    reg32_t *oped;
-    reg32_t ea1;
    uint8_t tmp8u, tmp8u2;
    int8_t tmp8s;
    uint16_t tmp16u, tmp16u2;
@@ -35,18 +39,16 @@ int Run(x86emu_t *emu, int step)
    int32_t tmp32s, tmp32s2;
    uint64_t tmp64u;
    int64_t tmp64s;
-    uintptr_t ip, old_ip;
+    uintptr_t ip;
    double d;
    float f;
    int64_t ll;
-    sse_regs_t *opex, eax1, *opx2;
+    sse_regs_t *opex, eax1;
    mmx_regs_t *opem, eam1;

    if(emu->quit)
        return 0;

-    old_ip = 0;
-
    //ref opcode: http://ref.x86asm.net/geek32.html#xA1
    printf_log(LOG_DEBUG, "Run X86 (%p), EIP=%p, Stack=%p\n", emu, (void*)R_EIP, emu->context->stack);
 #define F8      *(uint8_t*)(ip++)
@@ -63,48 +65,48 @@ int Run(x86emu_t *emu, int step)

    static const void* baseopcodes[256] ={
    &&_0x00_0,  &&_0x00_1,  &&_0x00_2,  &&_0x00_3,  &&_0x00_4,  &&_0x00_5,  &&_0x06,    &&_0x07,      //0x00-0x07
-    &&_0x08_0,  &&_0x08_1,  &&_0x08_2,  &&_0x08_3,  &&_0x08_4,  &&_0x08_5,  &&_default, &&_0x0F,      //0x08-0x0F
-    &&_0x10_0,  &&_0x10_1,  &&_0x10_2,  &&_0x10_3,  &&_0x10_4,  &&_0x10_5,  &&_default, &&_default,   //0x10-0x17
+    &&_0x08_0,  &&_0x08_1,  &&_0x08_2,  &&_0x08_3,  &&_0x08_4,  &&_0x08_5,  &&_0x0E,    &&_0x0F,      //0x08-0x0F
+    &&_0x10_0,  &&_0x10_1,  &&_0x10_2,  &&_0x10_3,  &&_0x10_4,  &&_0x10_5,  &&_0x16,    &&_0x17,      //0x10-0x17
    &&_0x18_0,  &&_0x18_1,  &&_0x18_2,  &&_0x18_3,  &&_0x18_4,  &&_0x18_5,  &&_0x1E,    &&_0x1F,      //0x18-0x1F
    &&_0x20_0,  &&_0x20_1,  &&_0x20_2,  &&_0x20_3,  &&_0x20_4,  &&_0x20_5,  &&_0x26,    &&_0x27,      //0x20-0x27
    &&_0x28_0,  &&_0x28_1,  &&_0x28_2,  &&_0x28_3,  &&_0x28_4,  &&_0x28_5,  &&_0x2E,    &&_0x2F,      //0x28-0x2F
-    &&_0x30_0,  &&_0x30_1,  &&_0x30_2,  &&_0x30_3,  &&_0x30_4,  &&_0x30_5,  &&_default, &&_0x37,      //0x30-0x37
-    &&_0x38,    &&_0x39,    &&_0x3A,    &&_0x3B,    &&_0x3C,    &&_0x3D,    &&_default, &&_0x3F,      //0x38-0x3F
+    &&_0x30_0,  &&_0x30_1,  &&_0x30_2,  &&_0x30_3,  &&_0x30_4,  &&_0x30_5,  &&_0x36,    &&_0x37,      //0x30-0x37
+    &&_0x38,    &&_0x39,    &&_0x3A,    &&_0x3B,    &&_0x3C,    &&_0x3D,    &&_0x3E,    &&_0x3F,      //0x38-0x3F
    &&_0x40,    &&_0x41,    &&_0x42,    &&_0x43,    &&_0x44,    &&_0x45,    &&_0x46,    &&_0x47, 
    &&_0x48,    &&_0x49,    &&_0x4A,    &&_0x4B,    &&_0x4C,    &&_0x4D,    &&_0x4E,    &&_0x4F,     
    &&_0x50,    &&_0x51,    &&_0x52,    &&_0x53,    &&_0x54,    &&_0x55,    &&_0x56,    &&_0x57, 
    &&_0x58,    &&_0x59,    &&_0x5A,    &&_0x5B,    &&_0x5C,    &&_0x5D,    &&_0x5E,    &&_0x5F, 
-    &&_0x60,    &&_0x61,    &&_default, &&_default, &&_0x64, &&_0x65,    &&_0x66,    &&_0x67,
-    &&_0x68,    &&_0x69,    &&_0x6A,    &&_0x6B,    &&_0x6C,    &&_0x6D,    &&_default, &&_default,   //0x68-0x6F
+    &&_0x60,    &&_0x61,    &&_0x62,    &&_0x63,    &&_0x64,    &&_0x65,    &&_0x66,    &&_0x67,
+    &&_0x68,    &&_0x69,    &&_0x6A,    &&_0x6B,    &&_0x6C,    &&_0x6D,    &&_0x6E,    &&_0x6F,      //0x68-0x6F
    &&_0x70_0,  &&_0x70_1,  &&_0x70_2,  &&_0x70_3,  &&_0x70_4,  &&_0x70_5,  &&_0x70_6,  &&_0x70_7,    //0x70-0x77
    &&_0x70_8,  &&_0x70_9,  &&_0x70_A,  &&_0x70_B,  &&_0x70_C,  &&_0x70_D,  &&_0x70_E,  &&_0x70_F,    //0x78-0x7F
-    &&_0x80,    &&_0x81,    &&_default, &&_0x83,    &&_0x84,    &&_0x85,    &&_0x86,    &&_0x87,     
-    &&_0x88,    &&_0x89,    &&_0x8A,    &&_0x8B,    &&_default, &&_0x8D,    &&_0x8E,    &&_0x8F,     
+    &&_0x80,    &&_0x81,    &&_0x82,    &&_0x83,    &&_0x84,    &&_0x85,    &&_0x86,    &&_0x87,     
+    &&_0x88,    &&_0x89,    &&_0x8A,    &&_0x8B,    &&_0x8C,    &&_0x8D,    &&_0x8E,    &&_0x8F,     
    &&_0x90,    &&_0x91,    &&_0x92,    &&_0x93,    &&_0x94,    &&_0x95,    &&_0x96,    &&_0x97, 
    &&_0x98,    &&_0x99,    &&_default, &&_0x9B,    &&_0x9C,    &&_0x9D,    &&_0x9E,    &&_0x9F,
    &&_0xA0,    &&_0xA1,    &&_0xA2,    &&_0xA3,    &&_0xA4,    &&_0xA5,    &&_0xA6,    &&_0xA7, 
    &&_0xA8,    &&_0xA9,    &&_0xAA,    &&_0xAB,    &&_0xAC,    &&_0xAD,    &&_0xAE,    &&_0xAF,     
    &&_0xB0,    &&_0xB1,    &&_0xB2,    &&_0xB3,    &&_0xB4,    &&_0xB5,    &&_0xB6,    &&_0xB7, 
    &&_0xB8,    &&_0xB9,    &&_0xBA,    &&_0xBB,    &&_0xBC,    &&_0xBD,    &&_0xBE,    &&_0xBF, 
-    &&_0xC0,    &&_0xC1,    &&_0xC2,    &&_0xC3,    &&_default, &&_default, &&_0xC6,    &&_0xC7, 
-    &&_0xC8,    &&_0xC9,    &&_default, &&_default, &&_0xCC,    &&_0xCD,    &&_default, &&_default,  //0xC8-0xCF
-    &&_0xD0,    &&_0xD1,    &&_0xD2,    &&_0xD3,    &&_0xD4,    &&_0xD5,    &&_default, &&_0xD7, 
+    &&_0xC0,    &&_0xC1,    &&_0xC2,    &&_0xC3,    &&_0xC4,    &&_0xC5,    &&_0xC6,    &&_0xC7, 
+    &&_0xC8,    &&_0xC9,    &&_default, &&_0xCB,    &&_0xCC,    &&_0xCD,    &&_default, &&_0xCF,      //0xC8-0xCF
+    &&_0xD0,    &&_0xD1,    &&_0xD2,    &&_0xD3,    &&_0xD4,    &&_0xD5,    &&_0xD6,    &&_0xD7, 
    &&_0xD8,    &&_0xD9,    &&_0xDA,    &&_0xDB,    &&_0xDC,    &&_0xDD,    &&_0xDE,    &&_0xDF, 
-    &&_0xE0,    &&_0xE1,    &&_0xE2,    &&_0xE3,    &&_default, &&_0xE5,    &&_default, &&_default,
-    &&_0xE8,    &&_0xE9,    &&_default, &&_0xEB,    &&_default, &&_default, &&_default, &&_default,
-    &&_0xF0,    &&_default, &&_0xF2,    &&_0xF3,    &&_default, &&_0xF5,    &&_0xF6,    &&_0xF7, 
-    &&_0xF8,    &&_0xF9,    &&_default, &&_default, &&_0xFC,    &&_0xFD,    &&_0xFE,    &&_0xFF
+    &&_0xE0,    &&_0xE1,    &&_0xE2,    &&_0xE3,    &&_0xE4,    &&_0xE5,    &&_0xE6,    &&_0xE7,
+    &&_0xE8,    &&_0xE9,    &&_default, &&_0xEB,    &&_0xEC,    &&_0xED,    &&_default, &&_default,
+    &&_0xF0,    &&_0xF1,    &&_0xF2,    &&_0xF3,    &&_default, &&_0xF5,    &&_0xF6,    &&_0xF7, 
+    &&_0xF8,    &&_0xF9,    &&_0xFA,    &&_0xFB,    &&_0xFC,    &&_0xFD,    &&_0xFE,    &&_0xFF
    };

    static const void* opcodes0f[256] = {
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x00-0x07
+    &&_0f_0x00, &&_0f_0x01, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x00-0x07
    &&_default, &&_default, &&_default, &&_0f_0x0B, &&_default ,&&_default, &&_default, &&_default, //0x08-0x0F
    &&_0f_0x10, &&_0f_0x11, &&_0f_0x12, &&_0f_0x13, &&_0f_0x14, &&_0f_0x15, &&_0f_0x16, &&_0f_0x17, //0x10-0x17 
-    &&_0f_0x18, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_0f_0x1F, //0x18-0x1F
+    &&_0f_0x18, &&_default, &&_0f_0x1A, &&_0f_0x1B, &&_default ,&&_default, &&_default, &&_0f_0x1F, //0x18-0x1F
    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x20-0x27
    &&_0f_0x28, &&_0f_0x29, &&_0f_0x2A, &&_0f_0x2B, &&_0f_0x2C, &&_0f_0x2D, &&_0f_0x2E, &&_0f_0x2F, 
    &&_default, &&_0f_0x31, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x30-0x37
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x38-0x3F
+    &&_0f_0x38, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x38-0x3F
    &&_0f_0x40_0, &&_0f_0x40_1, &&_0f_0x40_2, &&_0f_0x40_3, &&_0f_0x40_4, &&_0f_0x40_5, &&_0f_0x40_6, &&_0f_0x40_7,
    &&_0f_0x40_8, &&_0f_0x40_9, &&_0f_0x40_A, &&_0f_0x40_B, &&_0f_0x40_C, &&_0f_0x40_D, &&_0f_0x40_E, &&_0f_0x40_F,
    &&_0f_0x50, &&_0f_0x51, &&_0f_0x52, &&_0f_0x53, &&_0f_0x54, &&_0f_0x55, &&_0f_0x56, &&_0f_0x57, //0x50-0x57
@@ -117,106 +119,71 @@ int Run(x86emu_t *emu, int step)
    &&_0f_0x80_8, &&_0f_0x80_9, &&_0f_0x80_A, &&_0f_0x80_B, &&_0f_0x80_C, &&_0f_0x80_D, &&_0f_0x80_E, &&_0f_0x80_F,
    &&_0f_0x90_0, &&_0f_0x90_1, &&_0f_0x90_2, &&_0f_0x90_3, &&_0f_0x90_4, &&_0f_0x90_5, &&_0f_0x90_6, &&_0f_0x90_7,
    &&_0f_0x90_8, &&_0f_0x90_9, &&_0f_0x90_A, &&_0f_0x90_B, &&_0f_0x90_C, &&_0f_0x90_D, &&_0f_0x90_E, &&_0f_0x90_F,
-    &&_default, &&_default, &&_0f_0xA2, &&_0f_0xA3, &&_0f_0xA4, &&_0f_0xA5, &&_default, &&_default, //0xA0-0xA7
-    &&_default, &&_default, &&_default, &&_0f_0xAB, &&_0f_0xAC, &&_0f_0xAD, &&_0f_0xAE, &&_0f_0xAF, 
+    &&_0f_0xA0, &&_0f_0xA1, &&_0f_0xA2, &&_0f_0xA3, &&_0f_0xA4, &&_0f_0xA5, &&_default, &&_default, //0xA0-0xA7
+    &&_0f_0xA8, &&_0f_0xA9, &&_default, &&_0f_0xAB, &&_0f_0xAC, &&_0f_0xAD, &&_0f_0xAE, &&_0f_0xAF, 
    &&_0f_0xB0, &&_0f_0xB1, &&_default, &&_0f_0xB3, &&_default, &&_default, &&_0f_0xB6, &&_0f_0xB7, 
    &&_default, &&_default, &&_0f_0xBA, &&_0f_0xBB, &&_0f_0xBC, &&_0f_0xBD, &&_0f_0xBE, &&_0f_0xBF, 
-    &&_0f_0xC0, &&_0f_0xC1, &&_0f_0xC2, &&_default, &&_0f_0xC4, &&_0f_0xC5, &&_0f_0xC6, &&_0f_0xC7, 
+    &&_0f_0xC0, &&_0f_0xC1, &&_0f_0xC2, &&_0f_0xC3, &&_0f_0xC4, &&_0f_0xC5, &&_0f_0xC6, &&_0f_0xC7, 
    &&_0f_0xC8, &&_0f_0xC9, &&_0f_0xCA, &&_0f_0xCB, &&_0f_0xCC, &&_0f_0xCD, &&_0f_0xCE, &&_0f_0xCF, //0xC8-0xCF
-    &&_default, &&_0f_0xD1, &&_0f_0xD2, &&_0f_0xD3, &&_0f_0xD4 ,&&_0f_0xD5, &&_default, &&_default, //0xD0-0xD7
-    &&_0f_0xD8, &&_0f_0xD9, &&_default, &&_0f_0xDB, &&_0f_0xDC ,&&_0f_0xDD, &&_default, &&_0f_0xDF, //0xD8-0xDF
-    &&_0f_0xE0, &&_0f_0xE1, &&_0f_0xE2, &&_0f_0xE3, &&_0f_0xE4 ,&&_0f_0xE5, &&_default, &&_default, //0xE0-0xE7
-    &&_0f_0xE8, &&_0f_0xE9, &&_default, &&_0f_0xEB, &&_0f_0xEC ,&&_0f_0xED, &&_default, &&_0f_0xEF, //0xE8-0xEF
-    &&_default, &&_0f_0xF1, &&_0f_0xF2, &&_0f_0xF3, &&_0f_0xF4 ,&&_0f_0xF5, &&_0f_0xF6, &&_default, //0xF0-0xF7
+    &&_default, &&_0f_0xD1, &&_0f_0xD2, &&_0f_0xD3, &&_0f_0xD4 ,&&_0f_0xD5, &&_default, &&_0f_0xD7, //0xD0-0xD7
+    &&_0f_0xD8, &&_0f_0xD9, &&_0f_0xDA, &&_0f_0xDB, &&_0f_0xDC ,&&_0f_0xDD, &&_0f_0xDE, &&_0f_0xDF, //0xD8-0xDF
+    &&_0f_0xE0, &&_0f_0xE1, &&_0f_0xE2, &&_0f_0xE3, &&_0f_0xE4 ,&&_0f_0xE5, &&_default, &&_0f_0xE7, //0xE0-0xE7
+    &&_0f_0xE8, &&_0f_0xE9, &&_0f_0xEA, &&_0f_0xEB, &&_0f_0xEC ,&&_0f_0xED, &&_0f_0xEE, &&_0f_0xEF, //0xE8-0xEF
+    &&_default, &&_0f_0xF1, &&_0f_0xF2, &&_0f_0xF3, &&_0f_0xF4 ,&&_0f_0xF5, &&_0f_0xF6, &&_0f_0xF7, //0xF0-0xF7
    &&_0f_0xF8, &&_0f_0xF9, &&_0f_0xFA, &&_default, &&_0f_0xFC ,&&_0f_0xFD, &&_0f_0xFE, &&_default  //0xF8-0xFF
    };

    static const void* opcodes66[256] = {
-    &&_default, &&_66_0x00_1, &&_default, &&_66_0x00_3, &&_default ,&&_66_0x00_5, &&_66_0x06, &&_66_0x07, //0x00-0x07
-    &&_default, &&_66_0x08_1, &&_default, &&_66_0x08_3, &&_default ,&&_66_0x08_5, &&_default, &&_66_0x0F, //0x08-0x0F
-    &&_default, &&_66_0x10_1, &&_default, &&_66_0x10_3, &&_default ,&&_66_0x10_5, &&_default, &&_default, //0x10-0x17
-    &&_default, &&_66_0x18_1, &&_default, &&_66_0x18_3, &&_default ,&&_66_0x18_5, &&_default, &&_default, //0x18-0x1F
-    &&_default, &&_66_0x20_1, &&_default, &&_66_0x20_3, &&_default ,&&_66_0x20_5, &&_66_0x26, &&_default, //0x20-0x27
-    &&_default, &&_66_0x28_1, &&_default, &&_66_0x28_3, &&_default ,&&_66_0x28_5, &&_66_0x2E, &&_default, //0x28-0x2F
-    &&_default, &&_66_0x30_1, &&_default, &&_66_0x30_3, &&_default ,&&_66_0x30_5, &&_default, &&_default, //0x30-0x37
+    &&_66_0x00_0, &&_66_0x00_1, &&_66_0x00_2, &&_66_0x00_3, &&_66_0x00_4 ,&&_66_0x00_5, &&_66_0x06, &&_66_0x07, //0x00-0x07
+    &&_66_0x08_0, &&_66_0x08_1, &&_66_0x08_2, &&_66_0x08_3, &&_66_0x08_4 ,&&_66_0x08_5, &&_default, &&_66_0x0F, //0x08-0x0F
+    &&_66_0x10_0, &&_66_0x10_1, &&_66_0x10_2, &&_66_0x10_3, &&_66_0x10_4 ,&&_66_0x10_5, &&_default, &&_default, //0x10-0x17
+    &&_66_0x18_0, &&_66_0x18_1, &&_66_0x18_2, &&_66_0x18_3, &&_66_0x18_4 ,&&_66_0x18_5, &&_default, &&_66_0x1F, //0x18-0x1F
+    &&_66_0x20_0, &&_66_0x20_1, &&_66_0x20_2, &&_66_0x20_3, &&_66_0x20_4 ,&&_66_0x20_5, &&_66_0x26, &&_default, //0x20-0x27
+    &&_66_0x28_0, &&_66_0x28_1, &&_66_0x28_2, &&_66_0x28_3, &&_66_0x28_4 ,&&_66_0x28_5, &&_66_0x2E, &&_default, //0x28-0x2F
+    &&_66_0x30_0, &&_66_0x30_1, &&_66_0x30_2, &&_66_0x30_3, &&_66_0x30_4 ,&&_66_0x30_5, &&_66_0x36, &&_default, //0x30-0x37
    &&_default, &&_66_0x39, &&_default, &&_66_0x3B, &&_default, &&_66_0x3D, &&_default, &&_default, //0x38-0x3F
    &&_66_0x40, &&_66_0x41, &&_66_0x42, &&_66_0x43, &&_66_0x44, &&_66_0x45, &&_66_0x46, &&_66_0x47, 
    &&_66_0x48, &&_66_0x49, &&_66_0x4A, &&_66_0x4B, &&_66_0x4C, &&_66_0x4D, &&_66_0x4E, &&_66_0x4F, 
    &&_66_0x50, &&_66_0x51, &&_66_0x52, &&_66_0x53, &&_66_0x54, &&_66_0x55, &&_66_0x56, &&_66_0x57, //0x50-0x57
    &&_66_0x58, &&_66_0x59, &&_66_0x5A, &&_66_0x5B, &&_66_0x5C, &&_66_0x5D, &&_66_0x5E, &&_66_0x5F, //0x58-0x5F
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_66_0x66, &&_default, //0x60-0x67
+    &&_66_0x60, &&_66_0x61, &&_default, &&_default, &&_default ,&&_default, &&_66_0x66, &&_default, //0x60-0x67
    &&_66_0x68, &&_66_0x69, &&_66_0x6A, &&_66_0x6B, &&_default, &&_default, &&_default, &&_default, //0x68-0x6F
    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x70-0x77
    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x78-0x7F
    &&_default, &&_66_0x81, &&_default, &&_66_0x83, &&_default, &&_66_0x85, &&_default, &&_66_0x87, 
    &&_default, &&_66_0x89, &&_default, &&_66_0x8B, &&_66_0x8C, &&_default, &&_66_0x8E, &&_66_0x8F, 
-    &&_66_0x90, &&_default, &&_66_0x92, &&_default, &&_default, &&_default, &&_default, &&_default, 
-    &&_66_0x98, &&_66_0x99, &&_default, &&_default, &&_66_0x9C, &&_default, &&_default, &&_default, //0x98-0x9F
+    &&_66_0x90, &&_66_0x91, &&_66_0x92, &&_66_0x93, &&_66_0x94, &&_66_0x95, &&_66_0x96, &&_66_0x97, 
+    &&_66_0x98, &&_66_0x99, &&_default, &&_default, &&_66_0x9C, &&_66_0x9D, &&_default, &&_default, //0x98-0x9F
    &&_default, &&_66_0xA1, &&_default, &&_66_0xA3, &&_default, &&_66_0xA5, &&_default, &&_66_0xA7, 
    &&_default, &&_66_0xA9, &&_default, &&_66_0xAB, &&_default, &&_66_0xAD, &&_default, &&_66_0xAF, //0xA8-0xAF
    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0xB0-0xB7
    &&_66_0xB8, &&_66_0xB9, &&_66_0xBA, &&_66_0xBB, &&_66_0xBC, &&_66_0xBD, &&_66_0xBE, &&_66_0xBF, 
    &&_default, &&_66_0xC1, &&_default, &&_default, &&_default, &&_default, &&_default, &&_66_0xC7, 
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0xC8-0xCF
+    &&_default, &&_default, &&_default, &&_66_0xCB, &&_66_0xCC ,&&_default, &&_default, &&_default, //0xC8-0xCF
    &&_default, &&_66_0xD1, &&_default, &&_66_0xD3, &&_default, &&_default, &&_default, &&_default, //0xD0-0xD7
    &&_default, &&_66_0xD9, &&_default, &&_default, &&_default ,&&_66_0xDD, &&_default, &&_default, //0xD8-0xDF
    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0xE0-0xE7
    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0xE8-0xEF
-    &&_default, &&_default, &&_66_0xF2, &&_66_0xF3, &&_default, &&_default, &&_default, &&_66_0xF7, 
-    &&_default, &&_default, &&_default, &&_default, &&_default, &&_default, &&_default, &&_66_0xFF
-    };
-
-    static const void* opcodes660f[256] = {
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x00-0x07
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x08-0x0F
-    &&_6f_0x10, &&_6f_0x11, &&_6f_0x12, &&_6f_0x13, &&_6f_0x14, &&_6f_0x15, &&_6f_0x16, &&_6f_0x17, 
-    &&_default, &&_default, &&_default, &&_default, &&_default, &&_default, &&_default, &&_6f_0x1F, 
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x20-0x27
-    &&_6f_0x28, &&_6f_0x29, &&_6f_0x2A, &&_default, &&_6f_0x2C, &&_6f_0x2D, &&_6f_0x2E, &&_6f_0x2F, 
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x30-0x37
-    &&_6f_0x38, &&_default, &&_6f_0x3A, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x38-0x3F
-    &&_6f_0x40_0, &&_6f_0x40_1, &&_6f_0x40_2, &&_6f_0x40_3, &&_6f_0x40_4, &&_6f_0x40_5, &&_6f_0x40_6, &&_6f_0x40_7, 
-    &&_6f_0x40_8, &&_6f_0x40_9, &&_6f_0x40_A, &&_6f_0x40_B, &&_6f_0x40_C, &&_6f_0x40_D, &&_6f_0x40_E, &&_6f_0x40_F, 
-    &&_6f_0x50, &&_6f_0x51, &&_default, &&_default, &&_6f_0x54, &&_6f_0x55, &&_6f_0x56, &&_6f_0x57, 
-    &&_6f_0x58, &&_6f_0x59, &&_6f_0x5A, &&_6f_0x5B, &&_6f_0x5C, &&_6f_0x5D, &&_6f_0x5E, &&_6f_0x5F, 
-    &&_6f_0x60, &&_6f_0x61, &&_6f_0x62, &&_6f_0x63, &&_6f_0x64, &&_6f_0x65, &&_6f_0x66, &&_6f_0x67, 
-    &&_6f_0x68, &&_6f_0x69, &&_6f_0x6A, &&_6f_0x6B, &&_6f_0x6C, &&_6f_0x6D, &&_6f_0x6E, &&_6f_0x6F,     
-    &&_6f_0x70, &&_6f_0x71, &&_6f_0x72, &&_6f_0x73, &&_6f_0x74, &&_6f_0x75, &&_6f_0x76, &&_default, 
-    &&_default, &&_default, &&_default, &&_default, &&_default, &&_default, &&_6f_0x7E, &&_6f_0x7F, //0x78-0x7F
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x80-0x87
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x88-0x8F
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x90-0x97
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x98-0x9F
-    &&_default, &&_default, &&_default, &&_6f_0xA3, &&_6f_0xA4, &&_6f_0xA5, &&_default, &&_default, 
-    &&_default, &&_default, &&_default, &&_6f_0xAB, &&_6f_0xAC, &&_6f_0xAD, &&_default, &&_6f_0xAF, 
-    &&_default, &&_6f_0xB1, &&_default, &&_6f_0xB3, &&_default, &&_default, &&_6f_0xB6, &&_default, 
-    &&_default, &&_default, &&_default, &&_6f_0xBB, &&_6f_0xBC, &&_6f_0xBD, &&_6f_0xBE, &&_default, //0xB8-0xBF
-    &&_default, &&_6f_0xC1, &&_6f_0xC2, &&_default, &&_6f_0xC4, &&_6f_0xC5, &&_6f_0xC6, &&_default, 
-    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0xC8-0xCF
-    &&_default, &&_6f_0xD1, &&_6f_0xD2, &&_6f_0xD3, &&_6f_0xD4, &&_6f_0xD5, &&_6f_0xD6, &&_6f_0xD7, 
-    &&_6f_0xD8, &&_6f_0xD9, &&_default, &&_6f_0xDB, &&_6f_0xDC, &&_default, &&_6f_0xDE, &&_6f_0xDF, 
-    &&_default, &&_6f_0xE1, &&_6f_0xE2, &&_default, &&_default, &&_6f_0xE5, &&_6f_0xE6, &&_6f_0xE7, 
-    &&_6f_0xE8, &&_6f_0xE9, &&_6f_0xEA, &&_6f_0xEB, &&_6f_0xEC, &&_6f_0xED, &&_6f_0xEE, &&_6f_0xEF, 
-    &&_default, &&_6f_0xF1, &&_6f_0xF2, &&_6f_0xF3, &&_6f_0xF4, &&_6f_0xF5, &&_6f_0xF6, &&_6f_0xF7, 
-    &&_default, &&_6f_0xF9, &&_6f_0xFA, &&_6f_0xFB, &&_6f_0xFC, &&_6f_0xFD, &&_6f_0xFE, &&_default
+    &&_66_0xF0, &&_default, &&_66_0xF2, &&_66_0xF3, &&_default, &&_default, &&_default, &&_66_0xF7, 
+    &&_66_0xF8, &&_66_0xF9, &&_default, &&_default, &&_default, &&_default, &&_default, &&_66_0xFF
    };

 x86emurun:
    ip = R_EIP;
-//    UnpackFlags(emu);
 #ifdef HAVE_TRACE
 _trace:
+    __builtin_prefetch((void*)ip, 0, 0); 
    emu->prev2_ip = emu->prev_ip;
-    emu->prev_ip = old_ip;
-    old_ip = ip;
-    if(emu->dec && (
-        (emu->trace_end == 0) 
-        || ((ip >= emu->trace_start) && (ip < emu->trace_end))) )
+    emu->prev_ip = R_EIP;
+    R_EIP=ip;
+    if(my_context->dec && (
+        (trace_end == 0) 
+        || ((ip >= trace_start) && (ip < trace_end))) )
            PrintTrace(emu, ip, 0);

-    #define NEXT    __builtin_prefetch((void*)ip, 0, 0); goto _trace;
+    #define NEXT    goto _trace
 #else
-    #define NEXT    old_ip = ip; __builtin_prefetch((void*)ip, 0, 0); goto *baseopcodes[(opcode=F8)];
+    #define NEXT    goto *baseopcodes[(R_EIP=ip, opcode=F8)]
 #endif

 #include "modrm.h"
@@ -295,17 +262,30 @@ _trace:
            NEXT;
        _0x07:                      /* POP ES */
            emu->segs[_ES] = Pop(emu);    // no check, no use....
+            emu->segs_serial[_ES] = 0;
            NEXT;

+        _0x0E:                      /* PUSH CS */
+            Push(emu, emu->segs[_CS]);
+            NEXT;
        _0x0F:                      /* More instructions */
            #include "run0f.h"
            NEXT;

+        _0x16:                      /* PUSH SS */
+            Push(emu, emu->segs[_SS]);    // even if a segment is a 16bits, a 32bits push/pop is done
+            NEXT;
+        _0x17:                      /* POP SS */
+            emu->segs[_SS] = Pop(emu);    // no check, no use....
+            emu->segs_serial[_SS] = 0;
+            NEXT;
+
        _0x1E:                      /* PUSH DS */
            Push(emu, emu->segs[_DS]);  // even if a segment is a 16bits, a 32bits push/pop is done
            NEXT;
        _0x1F:                      /* POP DS */
            emu->segs[_DS] = Pop(emu);    // no check, no use....
+            emu->segs_serial[_DS] = 0;
            NEXT;

        _0x26:                      /* ES: */
@@ -315,18 +295,24 @@ _trace:
            NEXT;

        _0x2E:                      /* CS: */
+            // Can also happens before a condition branch: Branch Not Taken Hint
            NEXT;  //ignored...
        _0x2F:                      /* DAS */
            R_AL = das8(emu, R_AL);
            NEXT;
+
+        _0x36:                      /* SS: */
+            NEXT;
        _0x37:                      /* AAA */
            R_AX = aaa16(emu, R_AX);
            NEXT;
+
+        _0x3E:                      /* DS: */
+            // Can also happens before a condition branch: Branch Taken Hint
+            NEXT;
        _0x3F:                      /* AAS */
            R_AX = aas16(emu, R_AX);
            NEXT;
-
-
        _0x40:
        _0x41:
        _0x42:
@@ -395,41 +381,43 @@ _trace:
            R_ECX = Pop(emu);
            R_EAX = Pop(emu);
            NEXT;
+        _0x62:                      /* BOUND Gd, Ed */
+            nextop = F8;
+            GET_ED;
+            // ignoring the test for now
+            NEXT;
+        _0x63:                      /* ARPL Ew, Gw */
+            nextop = F8;
+            GET_EW;
+            // faking to always happy...
+            SET_FLAG(F_ZF);
+            NEXT;
        _0x64:                      /* FS: */
-
-            switch(F8)
-            {
-            case 0xA1:
-                tmp32s = F32S;
-                R_EAX = *(uint32_t*)((emu->segs[_FS]) + tmp32s);
-                break;
-            case 0x89:
-                nextop = F8;
-                GET_ED_OFFS(emu->segs[_FS]);
-                ED->dword[0] = GD.dword[0];
-                break;
-            default:
-                UnimpOpcode(emu);
-            }
-
+            emu->old_ip = R_EIP;
+            R_EIP = ip-1;
+            RunFS(emu); // implemented in Run66.c
+            ip = R_EIP;
            if(emu->quit) goto fini;
+            STEP
            NEXT;
        _0x65:                      /* GS: */
-            emu->old_ip = old_ip;
-            R_EIP = ip;
+            emu->old_ip = R_EIP;
+            R_EIP = ip-1;
            RunGS(emu); // implemented in Run66.c
            ip = R_EIP;
            if(emu->quit) goto fini;
+            STEP
            NEXT;

        _0x66:                      /* Prefix to change width of intructions, so here, down to 16bits */
            #include "run66.h"
        _0x67:                      /* Prefix to change width of registers */
-            emu->old_ip = old_ip;
-            R_EIP = ip;
+            emu->old_ip = R_EIP;
+            R_EIP = ip-1;   // don't count 0x67 yet
            Run67(emu); // implemented in Run66.c
            ip = R_EIP;
            if(emu->quit) goto fini;
+            STEP
            NEXT;

        _0x68:                      /* Push Id */
@@ -452,19 +440,33 @@ _trace:
            GD.dword[0] = imul32(emu, ED->dword[0], (uint32_t)tmp32s);
            NEXT;
        _0x6C:                      /* INSB */
-            *(int8_t*)R_EDI = 0;   // faking port read
+            *(int8_t*)(R_EDI+GetESBaseEmu(emu)) = 0;   // faking port read, using explicit ES segment
            if(ACCESS_FLAG(F_DF))
                R_EDI-=1;
            else
                R_EDI+=1;
            NEXT;
        _0x6D:                      /* INSD */
-            *(int32_t*)R_EDI = 0;   // faking port read
+            *(int32_t*)(R_EDI+GetESBaseEmu(emu)) = 0;   // faking port read, using explicit ES segment
            if(ACCESS_FLAG(F_DF))
                R_EDI-=4;
            else
                R_EDI+=4;
            NEXT;
+        _0x6E:                      /* OUTSB */
+            // faking port write, using explicit ES segment
+            if(ACCESS_FLAG(F_DF))
+                R_ESI-=1;
+            else
+                R_ESI+=1;
+            NEXT;
+        _0x6F:                      /* OUTSD */
+            // faking port write, using explicit ES segment
+            if(ACCESS_FLAG(F_DF))
+                R_ESI-=4;
+            else
+                R_ESI+=4;
+            NEXT;

        #define GOCOND(BASE, PREFIX, CONDITIONAL) \
        _##BASE##_0:                            \
@@ -555,6 +557,7 @@ _trace:

        
        _0x80:                      /* GRP Eb,Ib */
+        _0x82:                      // 0x82 and 0x80 are the same opcodes it seems?
            nextop = F8;
            GET_EB;
            tmp8u = F8;
@@ -603,6 +606,20 @@ _trace:
            NEXT;
        _0x86:                      /* XCHG Eb,Gb */
            nextop = F8;
+#ifdef DYNAREC
+            GET_EB;
+            if((nextop&0xC0)==0xC0) { // reg / reg: no lock
+                tmp8u = GB;
+                GB = EB->byte[0];
+                EB->byte[0] = tmp8u;
+            } else {
+                do {
+                    tmp8u = arm_lock_read_b(EB);
+                } while(arm_lock_write_b(EB, GB));
+                GB = tmp8u;
+            }
+            // dynarec use need it's own mecanism
+#else
            GET_EB;
            if((nextop&0xC0)!=0xC0)
                pthread_mutex_lock(&emu->context->mutex_lock); // XCHG always LOCK (but when accessing memory only)
@@ -611,9 +628,29 @@ _trace:
            EB->byte[0] = tmp8u;
            if((nextop&0xC0)!=0xC0)
                pthread_mutex_unlock(&emu->context->mutex_lock);
+#endif                
            NEXT;
        _0x87:                      /* XCHG Ed,Gd */
            nextop = F8;
+#ifdef DYNAREC
+            GET_ED;
+            if((nextop&0xC0)==0xC0) {
+                tmp32u = GD.dword[0];
+                GD.dword[0] = ED->dword[0];
+                ED->dword[0] = tmp32u;
+            } else {
+                if(((uintptr_t)ED)&3)
+                {
+                    // not aligned, dont't try to "LOCK"
+                    tmp32u = ED->dword[0];
+                    ED->dword[0] = GD.dword[0];
+                    GD.dword[0] = tmp32u;
+                } else {
+                    // XCHG is supposed to automaticaly LOCK memory bus
+                    GD.dword[0] = arm_lock_xchg(ED, GD.dword[0]);
+                }
+            }
+#else
            GET_ED;
            if((nextop&0xC0)!=0xC0)
                pthread_mutex_lock(&emu->context->mutex_lock); // XCHG always LOCK (but when accessing memory only)
@@ -622,6 +659,7 @@ _trace:
            ED->dword[0] = tmp32u;
            if((nextop&0xC0)!=0xC0)
                pthread_mutex_unlock(&emu->context->mutex_lock);
+#endif
            NEXT;
        _0x88:                      /* MOV Eb,Gb */
            nextop = F8;
@@ -643,7 +681,11 @@ _trace:
            GET_ED;
            GD.dword[0] = ED->dword[0];
            NEXT;
-
+        _0x8C:                      /* MOV Ed, Seg */
+            nextop = F8;
+            GET_ED;
+            ED->dword[0] = emu->segs[((nextop&0x38)>>3)];
+            NEXT;
        _0x8D:                      /* LEA Gd,M */
            nextop = F8;
            GET_ED;
@@ -653,11 +695,21 @@ _trace:
            nextop = F8;
            GET_EW;
            emu->segs[((nextop&0x38)>>3)] = EW->word[0];
+            emu->segs_serial[((nextop&0x38)>>3)] = 0;
+            if(((nextop&0x38)>>3)==_FS)
+                default_fs = EW->word[0];
            NEXT;
        _0x8F:                      /* POP Ed */
            nextop = F8;
-            GET_ED;
-            ED->dword[0] = Pop(emu);
+            if((nextop&0xC0)==0xC0) {
+                emu->regs[(nextop&7)].dword[0] = Pop(emu);
+            } else {
+                tmp32u = Pop(emu);  // this order allows handling POP [ESP] and variant
+                GET_ED;
+                R_ESP -= 4; // to prevent issue with SEGFAULT
+                ED->dword[0] = tmp32u;
+                R_ESP += 4;
+            }
            NEXT;
        _0x90:                      /* NOP */
            NEXT;
@@ -684,12 +736,10 @@ _trace:
            NEXT;
        _0x9C:                      /* PUSHF */
            CHECK_FLAGS(emu);
-            PackFlags(emu);
-            Push(emu, emu->packed_eflags.x32);
+            Push(emu, emu->eflags.x32);
            NEXT;
        _0x9D:                      /* POPF */
-            emu->packed_eflags.x32 = ((Pop(emu) & 0x3F7FD7)/* & (0xffff-40)*/ ) | 0x2; // mask off res2 and res3 and on res1
-            UnpackFlags(emu);
+            emu->eflags.x32 = ((Pop(emu) & 0x3F7FD7)/* & (0xffff-40)*/ ) | 0x2; // mask off res2 and res3 and on res1
            RESET_FLAGS(emu);
            NEXT;
        _0x9E:                      /* SAHF */
@@ -703,8 +753,7 @@ _trace:
            NEXT;
        _0x9F:                      /* LAHF */
            CHECK_FLAGS(emu);
-            PackFlags(emu);
-            R_AH = (uint8_t)emu->packed_eflags.x32;
+            R_AH = (uint8_t)emu->eflags.x32;
            NEXT;

        _0xA0:                      /* MOV AL,Ob */
@@ -847,7 +896,20 @@ _trace:
            ip = Pop(emu);
            STEP
            NEXT;
-
+        _0xC4:                      /* LES Gd,Ed */
+            nextop = F8;
+            GET_ED;
+            emu->segs[_ES] = ED->word[0];
+            emu->segs_serial[_ES] = 0;
+            GD.dword[0] = *(uint32_t*)(((void*)ED)+2);
+            NEXT;
+        _0xC5:                      /* LDS Gd,Ed */
+            nextop = F8;
+            GET_ED;
+            emu->segs[_DS] = ED->word[0];
+            emu->segs_serial[_DS] = 0;
+            GD.dword[0] = *(uint32_t*)(((void*)ED)+2);
+            NEXT;
        _0xC6:                      /* MOV Eb,Ib */
            nextop = F8;
            GET_EB;
@@ -880,8 +942,15 @@ _trace:
            R_EBP = Pop(emu);
            NEXT;

+        _0xCB:                      /* FAR RET */
+            ip = Pop(emu);
+            emu->segs[_CS] = Pop(emu);    // no check, no use....
+            emu->segs_serial[_CS] = 0;
+            // need to check status of CS register!
+            STEP
+            NEXT;
        _0xCC:                      /* INT 3 */
-            emu->old_ip = old_ip;
+            emu->old_ip = R_EIP;
            R_EIP = ip;
            x86Int3(emu);
            ip = R_EIP;
@@ -890,14 +959,15 @@ _trace:
        _0xCD:                      /* INT Ib */
            nextop = F8;
            if(nextop == 0x80) {
-                emu->old_ip = old_ip;
+                emu->old_ip = R_EIP;
                R_EIP = ip;
                x86Syscall(emu);
                ip = R_EIP;
                if(emu->quit) goto fini;
            } else {
-                printf_log(LOG_NONE, "Unsupported Int %02Xh\n", nextop);
-                emu->old_ip = old_ip;
+                int tid = GetTID();
+                printf_log(LOG_NONE, "%04d|%p: Ignoring Unsupported Int %02Xh\n", tid, (void*)ip, nextop);
+                emu->old_ip = R_EIP;
                R_EIP = ip;
                emu->quit = 1;
                emu->error |= ERR_UNIMPL;
@@ -905,6 +975,13 @@ _trace:
            }
            NEXT;

+        _0xCF:                      /* IRET */
+            ip = Pop(emu);
+            emu->segs[_CS] = Pop(emu);
+            emu->segs_serial[_CS] = 0;
+            emu->eflags.x32 = ((Pop(emu) & 0x3F7FD7)/* & (0xffff-40)*/ ) | 0x2; // mask off res2 and res3 and on res1
+            RESET_FLAGS(emu);
+            NEXT;
        _0xD0:                      /* GRP2 Eb,1 */
        _0xD2:                      /* GRP2 Eb,CL */
            nextop = F8;
@@ -943,7 +1020,10 @@ _trace:
        _0xD5:                      /* AAD Ib */
            R_AX = aad16(emu, R_AX, F8);
            NEXT;
-        
+        _0xD6:
+            CHECK_FLAGS(emu);
+            R_AL = ACCESS_FLAG(F_CF)?0xFF:0x00;
+            NEXT;
        _0xD7:                      /* XLAT */
            R_AL = *(uint8_t*)(R_EBX + R_AL);
            NEXT;
@@ -979,6 +1059,7 @@ _trace:
            --R_ECX; // don't update flags
            if(R_ECX && !ACCESS_FLAG(F_ZF))
                ip += tmp8s;
+            STEP
            NEXT;
        _0xE1:                      /* LOOPZ */
            CHECK_FLAGS(emu);
@@ -986,26 +1067,37 @@ _trace:
            --R_ECX; // don't update flags
            if(R_ECX && ACCESS_FLAG(F_ZF))
                ip += tmp8s;
+            STEP
            NEXT;
        _0xE2:                      /* LOOP */
            tmp8s = F8S;
            --R_ECX; // don't update flags
            if(R_ECX)
                ip += tmp8s;
+            STEP
            NEXT;
        _0xE3:                      /* JECXZ */
            tmp8s = F8S;
-            if(!R_ECX) {
+            if(!R_ECX)
                ip += tmp8s;
-                STEP
-            }
+            STEP
+            NEXT;
+        _0xE4:                      /* IN AL, Ib */
+            tmp32s = F8;   // port address
+            R_AL = 0;  // nothing... should do a warning maybe?
            NEXT;
-
        _0xE5:                      /* IN EAX, Ib */
            tmp32s = F8;   // port address
            R_EAX = 0;  // nothing... should do a warning maybe?
            NEXT;
-
+        _0xE6:                      /* OUT Ib, AL */
+            tmp32s = F8;    // port address
+            //nothing goes out...
+            NEXT;
+        _0xE7:                      /* OUT Ib, EAX */
+            tmp32s = F8;    // port address
+            //nothing goes out...
+            NEXT;
        _0xE8:                      /* CALL Id */
            tmp32s = F32S; // call is relative
            Push(emu, ip);
@@ -1023,15 +1115,23 @@ _trace:
            ip += tmp32s;
            STEP
            NEXT;
+        _0xEC:                      /* IN AL, DX */
+            R_AL = 0;  // nothing... should do a warning maybe?
+            NEXT;
+        _0xED:                      /* IN EAX, DX */
+            R_EAX = 0;  // nothing... should do a warning maybe?
+            NEXT;

        _0xF0:                      /* LOCK */
-            emu->old_ip = old_ip;
-            R_EIP = ip;
+            emu->old_ip = R_EIP;
+            R_EIP = ip-1;   // dont't count F0 yet
            RunLock(emu); // implemented in Run66.c
            ip = R_EIP;
            if(emu->quit) goto fini;
            NEXT;
-
+        _0xF1:                      /* INT1 */
+            // does nothing for now
+            NEXT;
        _0xF2:                      /* REPNZ prefix */
        _0xF3:                      /* REPZ prefix */
            nextop = F8;
@@ -1041,6 +1141,7 @@ _trace:
                } else {
                    #include "runf20f.h"
                }
+                STEP
                NEXT;
            } else if(nextop==0x66) {
                nextop = F8;
@@ -1064,6 +1165,55 @@ _trace:
                            R_EDI += tmp8s;
                        }
                        break;
+                    case 0xA7:              /* REP(N)Z CMPSW */
+                        tmp16u = 0;
+                        tmp16u2 = 0;
+                        tmp8s *= 2;
+                        if(opcode==0xF2) {
+                            while(tmp32u) {
+                                --tmp32u;
+                                tmp16u2 = *(uint16_t*)R_EDI;
+                                tmp16u  = *(uint16_t*)R_ESI;
+                                R_EDI += tmp8s;
+                                R_ESI += tmp8s;
+                                if(tmp16u2==tmp16u)
+                                    break;
+                            }
+                        } else {
+                            while(tmp32u) {
+                                --tmp32u;
+                                tmp16u2 = *(uint16_t*)R_EDI;
+                                tmp16u  = *(uint16_t*)R_ESI;
+                                R_EDI += tmp8s;
+                                R_ESI += tmp8s;
+                                if(tmp16u2!=tmp16u)
+                                    break;
+                            }
+                        }
+                        if(R_ECX) cmp16(emu, tmp16u, tmp16u2);
+                        break;
+                    case 0xAF:              /* REP(N)Z SCASW */
+                        tmp16u = 0;
+                        tmp8s *= 2;
+                        if(opcode==0xF2) {
+                            while(tmp32u) {
+                                --tmp32u;
+                                tmp16u = *(uint16_t*)R_EDI;
+                                R_EDI += tmp8s;
+                                if(R_AX==tmp16u)
+                                    break;
+                            }
+                        } else {
+                            while(tmp32u) {
+                                --tmp32u;
+                                tmp16u = *(uint16_t*)R_EDI;
+                                R_EDI += tmp8s;
+                                if(R_AX!=tmp16u)
+                                    break;
+                            }
+                        }
+                        if(R_ECX) cmp16(emu, R_AX, tmp16u);
+                        break;
                    default:
                        goto _default;
                }
@@ -1072,10 +1222,58 @@ _trace:
                tmp8s = ACCESS_FLAG(F_DF)?-1:+1;
                tmp32u = R_ECX;
                switch(nextop) {
-                    case 0x90:              /* PAUSE */
+                    case 0x18:
+                    case 0x19:
+                    case 0x1A:
+                    case 0x1B:
+                    case 0x1C:
+                    case 0x1D:
+                    case 0x25:
+                    case 0x40:
+                    case 0x41:
+                    case 0x42:
+                    case 0x43:
+                    case 0x44:
+                    case 0x45:
+                    case 0x46:
+                    case 0x47:
+                    case 0x48:
+                    case 0x49:
+                    case 0x4A:
+                    case 0x4B:
+                    case 0x4C:
+                    case 0x4D:
+                    case 0x4E:
+                    case 0x4F:
+                    case 0x70:
+                    case 0x71:
+                    case 0x72:
+                    case 0x73:
+                    case 0x74:
+                    case 0x75:
+                    case 0x76:
+                    case 0x77:
+                    case 0x78:
+                    case 0x79:
+                    case 0x7A:
+                    case 0x7B:
+                    case 0x7C:
+                    case 0x7D:
+                    case 0x7E:
+                    case 0x7F:              /* BND / NOP */
+                    case 0x86:              /* XACQUIRE/XRELEASE XCHG */
+                    case 0x87:              /* XACQUIRE/XRELEASE XCHG */
+                    case 0x88:              /* XRELEASE MOV... */
+                    case 0x89:              /* XRELEASE MOV... ignoring acquire thingy */
+                    case 0x9C:
+                    case 0xC3:              /* yup, repz ret is valid */
+                    case 0xE8:
+                    case 0xE9:
+                    case 0xEB:
+                    case 0xF0:              /* XACQUIRE/XRELEASE LOCK ... ignoring acquire thingy */
+                        --ip;
                        NEXT;
-                    case 0xC3:              /* REPZ RET... yup */
-                        ip = Pop(emu);
+                    case 0x90:              /* PAUSE */
                        NEXT;
                    case 0xA4:              /* REP MOVSB */
                        while(tmp32u) {
@@ -1238,7 +1436,8 @@ _trace:
            switch((nextop>>3)&7) {
                case 0: 
                case 1:                 /* TEST Eb,Ib */
-                    test8(emu, EB->byte[0], F8);
+                    tmp8u = F8;
+                    test8(emu, EB->byte[0], tmp8u);
                    break;
                case 2:                 /* NOT Eb */
                    EB->byte[0] = not8(emu, EB->byte[0]);
@@ -1266,7 +1465,8 @@ _trace:
            switch((nextop>>3)&7) {
                case 0: 
                case 1:                 /* TEST Ed,Id */
-                    test32(emu, ED->dword[0], F32);
+                    tmp32u = F32;
+                    test32(emu, ED->dword[0], tmp32u);
                    break;
                case 2:                 /* NOT Ed */
                    ED->dword[0] = not32(emu, ED->dword[0]);
@@ -1297,7 +1497,12 @@ _trace:
            CHECK_FLAGS(emu);
            SET_FLAG(F_CF);
            NEXT;
-
+        _0xFA:                      /* CLI */
+            CLEAR_FLAG(F_IF);   //not really handled...
+            NEXT;
+        _0xFB:                      /* STI */
+            SET_FLAG(F_IF);
+            NEXT;
        _0xFC:                      /* CLD */
            CLEAR_FLAG(F_DF);
            NEXT;
@@ -1306,6 +1511,7 @@ _trace:
            NEXT;
        _0xFE:                      /* GRP 5 Eb */
            nextop = F8;
+            tmp32u2 = ip;
            GET_EB;
            switch((nextop>>3)&7) {
                case 0:                 /* INC Eb */
@@ -1315,9 +1521,9 @@ _trace:
                    EB->byte[0] = dec8(emu, EB->byte[0]);
                    break;
                default:
-                    emu->old_ip = old_ip;
-                    R_EIP = ip;
-                    printf_log(LOG_NONE, "Illegal Opcode %02X %02X\n", opcode, nextop);
+                    emu->old_ip = R_EIP;
+                    R_EIP = ip = tmp32u2;
+                    printf_log(LOG_NONE, "Illegal Opcode %p: %02X %02X %02X %02X\n", (void*)ip, opcode, nextop, PK(2), PK(3));
                    emu->quit=1;
                    emu->error |= ERR_ILLEGAL;
                    goto fini;
@@ -1325,6 +1531,7 @@ _trace:
            NEXT;
        _0xFF:                      /* GRP 5 Ed */
            nextop = F8;
+            tmp32u2 = ip;
            GET_ED;
            switch((nextop>>3)&7) {
                case 0:                 /* INC Ed */
@@ -1334,15 +1541,16 @@ _trace:
                    ED->dword[0] = dec32(emu, ED->dword[0]);
                    break;
                case 2:                 /* CALL NEAR Ed */
+                    tmp32u = (uintptr_t)getAlternate((void*)ED->dword[0]);
                    Push(emu, ip);
-                    ip = ED->dword[0];  // should get value in temp var. in case ED use ESP?
+                    ip = tmp32u;
                    STEP
                    break;
                case 3:                 /* CALL FAR Ed */
                    if(nextop>0xc0) {
-                        emu->old_ip = old_ip;
-                        R_EIP = ip;
-                        printf_log(LOG_NONE, "Illegal Opcode %02X %02X\n", opcode, nextop);
+                        emu->old_ip = R_EIP;
+                        R_EIP = ip = tmp32u2;
+                        printf_log(LOG_NONE, "Illegal Opcode %p: %02X %02X %02X %02X\n", (void*)ip, opcode, nextop, PK(2), PK(3));
                        emu->quit=1;
                        emu->error |= ERR_ILLEGAL;
                        goto fini;
@@ -1355,14 +1563,14 @@ _trace:
                    }
                    break;
                case 4:                 /* JMP NEAR Ed */
-                    ip = ED->dword[0];
+                    ip = (uintptr_t)getAlternate((void*)ED->dword[0]);
                    STEP
                    break;
                case 5:                 /* JMP FAR Ed */
                    if(nextop>0xc0) {
-                        emu->old_ip = old_ip;
-                        R_EIP = ip;
-                        printf_log(LOG_NONE, "Illegal Opcode 0x%02X 0x%02X\n", opcode, nextop);
+                        emu->old_ip = R_EIP;
+                        R_EIP = ip = tmp32u2;
+                        printf_log(LOG_NONE, "Illegal Opcode %p: 0x%02X 0x%02X %02X %02X\n", (void*)ip, opcode, nextop, PK(2), PK(3));
                        emu->quit=1;
                        emu->error |= ERR_ILLEGAL;
                        goto fini;
@@ -1373,12 +1581,13 @@ _trace:
                    }
                    break;
                case 6:                 /* Push Ed */
-                    Push(emu, ED->dword[0]);
+                    tmp32u = ED->dword[0];
+                    Push(emu, tmp32u);  // avoid potential issue with push [esp+...]
                    break;
                default:
-                    emu->old_ip = old_ip;
-                    R_EIP = ip;
-                    printf_log(LOG_NONE, "Illegal Opcode 0x%02X 0x%02X\n", opcode, nextop);
+                    emu->old_ip = R_EIP;
+                    R_EIP = ip = tmp32u2;
+                    printf_log(LOG_NONE, "Illegal Opcode %p: %02X %02X %02X %02X %02X %02X\n",(void*)ip, opcode, nextop, PK(2), PK(3), PK(4), PK(5));
                    emu->quit=1;
                    emu->error |= ERR_ILLEGAL;
                    goto fini;
@@ -1386,13 +1595,13 @@ _trace:
            NEXT;

        _default:
-            emu->old_ip = old_ip;
+            emu->old_ip = R_EIP;
            R_EIP = ip;
            UnimpOpcode(emu);
            goto fini;
 #ifdef DYNAREC
 stepout:
-    emu->old_ip = old_ip;
+    emu->old_ip = R_EIP;
    R_EIP = ip;
    return 0;
 #endif
@@ -1,6 +1,90 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <math.h>
+#include <string.h>
+
+#include "debug.h"
+#include "box86stack.h"
+#include "x86emu.h"
+#include "x86run.h"
+#include "x86emu_private.h"
+#include "x86run_private.h"
+#include "x86primop.h"
+#include "x86trace.h"
+#include "box86context.h"
+
+#define F8      *(uint8_t*)(ip++)
+#define F8S     *(int8_t*)(ip++)
+#define F16     *(uint16_t*)(ip+=2, ip-2)
+#define F16S    *(int16_t*)(ip+=2, ip-2)
+#define F32     *(uint32_t*)(ip+=4, ip-4)
+#define F32S    *(int32_t*)(ip+=4, ip-4)
+#define PK(a)   *(uint8_t*)(ip+a)
+
+#include "modrm.h"
+
+void Run660F(x86emu_t *emu)
+{
+    uintptr_t ip = R_EIP+2; //skip 66 0F
+    uint8_t opcode;
+    uint8_t nextop;
+    reg32_t *oped;
+    uint8_t tmp8u;
+    int8_t tmp8s;
+    uint16_t tmp16u;
+    int16_t tmp16s;
+    uint32_t tmp32u;
+    int32_t tmp32s;
+    sse_regs_t *opex, eax1, *opx2;
+    mmx_regs_t *opem;
+
+    static const void* opcodes660f[256] = {
+    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x00-0x07
+    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x08-0x0F
+    &&_6f_0x10, &&_6f_0x11, &&_6f_0x12, &&_6f_0x13, &&_6f_0x14, &&_6f_0x15, &&_6f_0x16, &&_6f_0x17, 
+    &&_default, &&_default, &&_default, &&_default, &&_default, &&_default, &&_default, &&_6f_0x1F, 
+    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x20-0x27
+    &&_6f_0x28, &&_6f_0x29, &&_6f_0x2A, &&_default, &&_6f_0x2C, &&_6f_0x2D, &&_6f_0x2E, &&_6f_0x2F, 
+    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x30-0x37
+    &&_6f_0x38, &&_default, &&_6f_0x3A, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x38-0x3F
+    &&_6f_0x40_0, &&_6f_0x40_1, &&_6f_0x40_2, &&_6f_0x40_3, &&_6f_0x40_4, &&_6f_0x40_5, &&_6f_0x40_6, &&_6f_0x40_7, 
+    &&_6f_0x40_8, &&_6f_0x40_9, &&_6f_0x40_A, &&_6f_0x40_B, &&_6f_0x40_C, &&_6f_0x40_D, &&_6f_0x40_E, &&_6f_0x40_F, 
+    &&_6f_0x50, &&_6f_0x51, &&_default, &&_default, &&_6f_0x54, &&_6f_0x55, &&_6f_0x56, &&_6f_0x57, 
+    &&_6f_0x58, &&_6f_0x59, &&_6f_0x5A, &&_6f_0x5B, &&_6f_0x5C, &&_6f_0x5D, &&_6f_0x5E, &&_6f_0x5F, 
+    &&_6f_0x60, &&_6f_0x61, &&_6f_0x62, &&_6f_0x63, &&_6f_0x64, &&_6f_0x65, &&_6f_0x66, &&_6f_0x67, 
+    &&_6f_0x68, &&_6f_0x69, &&_6f_0x6A, &&_6f_0x6B, &&_6f_0x6C, &&_6f_0x6D, &&_6f_0x6E, &&_6f_0x6F,     
+    &&_6f_0x70, &&_6f_0x71, &&_6f_0x72, &&_6f_0x73, &&_6f_0x74, &&_6f_0x75, &&_6f_0x76, &&_default, 
+    &&_default, &&_default, &&_default, &&_default, &&_6f_0x7C, &&_default, &&_6f_0x7E, &&_6f_0x7F, //0x78-0x7F
+    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x80-0x87
+    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x88-0x8F
+    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x90-0x97
+    &&_default, &&_default, &&_default, &&_default, &&_default ,&&_default, &&_default, &&_default, //0x98-0x9F
+    &&_default, &&_default, &&_default, &&_6f_0xA3, &&_6f_0xA4, &&_6f_0xA5, &&_default, &&_default, 
+    &&_default, &&_default, &&_default, &&_6f_0xAB, &&_6f_0xAC, &&_6f_0xAD, &&_default, &&_6f_0xAF, 
+    &&_default, &&_6f_0xB1, &&_default, &&_6f_0xB3, &&_default, &&_default, &&_6f_0xB6, &&_6f_0xB7, 
+    &&_default, &&_default, &&_6f_0xBA, &&_6f_0xBB, &&_6f_0xBC, &&_6f_0xBD, &&_6f_0xBE, &&_default, //0xB8-0xBF
+    &&_default, &&_6f_0xC1, &&_6f_0xC2, &&_default, &&_6f_0xC4, &&_6f_0xC5, &&_6f_0xC6, &&_default, 
+    &&_6f_0xC8, &&_6f_0xC9, &&_6f_0xCA, &&_6f_0xCB, &&_6f_0xCC ,&&_6f_0xCD, &&_6f_0xCE, &&_6f_0xCF, //0xC8-0xCF
+    &&_6f_0xD0, &&_6f_0xD1, &&_6f_0xD2, &&_6f_0xD3, &&_6f_0xD4, &&_6f_0xD5, &&_6f_0xD6, &&_6f_0xD7, 
+    &&_6f_0xD8, &&_6f_0xD9, &&_6f_0xDA, &&_6f_0xDB, &&_6f_0xDC, &&_6f_0xDD, &&_6f_0xDE, &&_6f_0xDF, 
+    &&_6f_0xE0, &&_6f_0xE1, &&_6f_0xE2, &&_6f_0xE3, &&_6f_0xE4, &&_6f_0xE5, &&_6f_0xE6, &&_6f_0xE7, 
+    &&_6f_0xE8, &&_6f_0xE9, &&_6f_0xEA, &&_6f_0xEB, &&_6f_0xEC, &&_6f_0xED, &&_6f_0xEE, &&_6f_0xEF, 
+    &&_default, &&_6f_0xF1, &&_6f_0xF2, &&_6f_0xF3, &&_6f_0xF4, &&_6f_0xF5, &&_6f_0xF6, &&_6f_0xF7, 
+    &&_6f_0xF8, &&_6f_0xF9, &&_6f_0xFA, &&_6f_0xFB, &&_6f_0xFC, &&_6f_0xFD, &&_6f_0xFE, &&_default
+    };
+
+    #define NEXT    goto _fini
+
    opcode = F8;
    goto *opcodes660f[opcode];

+    _default:
+        emu->old_ip = R_EIP;
+        R_EIP = ip;
+        UnimpOpcode(emu);
+        goto _fini;
+
    #define GOCOND(BASE, PREFIX, CONDITIONAL) \
    _6f_##BASE##_0:                          \
        PREFIX                              \
@@ -104,12 +188,18 @@
    _6f_0x12:                      /* MOVLPD Gx, Eq */
        nextop = F8;
        GET_ED;
-        GX.q[0] = *(uint64_t*)ED;
+        if((uintptr_t)ED & 7)
+            memcpy(&GX.q[0], ED, 8);
+        else
+            GX.q[0] = *(uint64_t*)ED;
        NEXT;
    _6f_0x13:                      /* MOVLPD Eq, Gx */
        nextop = F8;
        GET_ED;
-        *(uint64_t*)ED = GX.q[0];
+        if((uintptr_t)ED & 7)
+            memcpy(ED, &GX.q[0], 8);
+        else
+            *(uint64_t*)ED = GX.q[0];
        NEXT;
    _6f_0x14:                      /* UNPCKLPD Gx, Ex */
        nextop = F8;
@@ -207,17 +297,127 @@
    _6f_0x38:  // these are some SSE3 opcodes
        opcode = F8;
        switch(opcode) {
-            case 0x00:  // PSHUFB
+            case 0x00:  /* PSHUFB */
                nextop = F8;
                GET_EX;
                eax1 = GX;
-                for (int i=0; i<15; ++i) {
+                for (int i=0; i<16; ++i) {
                    if(EX->ub[i]&128)
                        GX.ub[i] = 0;
                    else
                        GX.ub[i] = eax1.ub[EX->ub[i]&15];
                }
                break;
+            case 0x01:  /* PHADDW Gx, Ex */
+                nextop = F8;
+                GET_EX;
+                for (int i=0; i<4; ++i)
+                    GX.sw[i] = GX.sw[i*2+0]+GX.sw[i*2+1];
+                if(&GX == EX) {
+                    GX.q[1] = GX.q[0];
+                } else {
+                    for (int i=0; i<4; ++i)
+                        GX.sw[4+i] = EX->sw[i*2+0] + EX->sw[i*2+1];
+                }
+                break;
+            case 0x02:  /* PHADDD Gx, Ex */
+                nextop = F8;
+                GET_EX;
+                GX.sd[0] += GX.sd[1];
+                GX.sd[1] = GX.sd[2] + GX.sd[3];
+                if(&GX == EX) {
+                    GX.q[1] = GX.q[0];
+                } else {
+                    GX.sd[2] = EX->sd[0] + EX->sd[1];
+                    GX.sd[3] = EX->sd[2] + EX->sd[3];
+                }
+                break;
+            case 0x03:  /* PHADDSW Gx, Ex */
+                nextop = F8;
+                GET_EX;
+                for (int i=0; i<4; ++i) {
+                    tmp32s = GX.sw[i*2+0]+GX.sw[i*2+1];
+                    GX.sw[i] = (tmp32s<-32768)?-32768:((tmp32s>32767)?32767:tmp32s);
+                }
+                if(&GX == EX) {
+                    GX.q[1] = GX.q[0];
+                } else {
+                    for (int i=0; i<4; ++i) {
+                        tmp32s = EX->sw[i*2+0] + EX->sw[i*2+1];
+                        GX.sw[4+i] = (tmp32s<-32768)?-32768:((tmp32s>32767)?32767:tmp32s);
+                    }
+                }
+                break;
+            case 0x04:  /* PMADDUBSW Gx,Ex */
+                nextop = F8;
+                GET_EX;
+                for (int i=0; i<8; ++i) {
+                    tmp32s = (int32_t)(GX.ub[i*2+0])*EX->sb[i*2+0] + (int32_t)(GX.ub[i*2+1])*EX->sb[i*2+1];
+                    GX.sw[i] = (tmp32s>32767)?32767:((tmp32s<-32768)?-32768:tmp32s);
+                }
+                break;
+            case 0x05:  /* PHSUBW Gx, Ex */
+                nextop = F8;
+                GET_EX;
+                for (int i=0; i<4; ++i)
+                    GX.sw[i] = GX.sw[i*2+0] - GX.sw[i*2+1];
+                if(&GX == EX) {
+                    GX.q[1] = GX.q[0];
+                } else {
+                    for (int i=0; i<4; ++i)
+                        GX.sw[4+i] = EX->sw[i*2+0] - EX->sw[i*2+1];
+                }
+                break;
+                
+            case 0x08:  /* PSIGNB Gx, Ex */
+                nextop = F8;
+                GET_EX;
+                for (int i=0; i<16; ++i)
+                    GX.sb[i] *= (EX->sb[i]<0)?-1:((EX->sb[i]>0)?1:0);
+            break;
+            case 0x09:  /* PSIGNW Gx, Ex */
+                nextop = F8;
+                GET_EX;
+                for (int i=0; i<8; ++i)
+                    GX.sw[i] *= (EX->sw[i]<0)?-1:((EX->sw[i]>0)?1:0);
+            break;
+            case 0x0A:  /* PSIGND Gx, Ex */
+                nextop = F8;
+                GET_EX;
+                for (int i=0; i<4; ++i)
+                    GX.sd[i] *= (EX->sd[i]<0)?-1:((EX->sd[i]>0)?1:0);
+            break;
+            case 0x0B:  /* PMULHRSW Gx, Ex */
+                nextop = F8;
+                GET_EX;
+                for (int i=0; i<8; ++i) {
+                    tmp32s = ((((int32_t)(GX.sw[i])*(int32_t)(EX->sw[i]))>>14) + 1)>>1;
+                    GX.uw[i] = tmp32s&0xffff;
+                }
+            break;
+
+            case 0x1C:  /* PABSB Gx, Ex */
+                nextop = F8;
+                GET_EX;
+                for (int i=0; i<16; ++i) {
+                    GX.sb[i] = abs(EX->sb[i]);
+                }
+                break;
+            case 0x1D:  /* PABSW Gx, Ex */
+                nextop = F8;
+                GET_EX;
+                for (int i=0; i<8; ++i) {
+                    GX.sw[i] = abs(EX->sw[i]);
+                }
+                break;
+            case 0x1E:  /* PABSD Gx, Ex */
+                nextop = F8;
+                GET_EX;
+                for (int i=0; i<4; ++i) {
+                    GX.sd[i] = abs(EX->sd[i]);
+                }
+                break;
+
            default:
                goto _default;
        }
@@ -226,31 +426,42 @@
    _6f_0x3A:  // these are some SSE3 opcodes
        opcode = F8;
        switch(opcode) {
-            case 0x0F:          // PALIGNR
+            case 0x0F:          // PALIGNR GX, EX, u8
                nextop = F8;
                GET_EX;
                tmp8u = F8;
                if(tmp8u>31)
-                    {EX->q[0] = EX->q[1] = 0;}
-                else if(tmp8u>15) {
+                    {GX.q[0] = GX.q[1] = 0;}
+                else
+                #if 0
+                    if(tmp8u>15) {
                    tmp8u=(tmp8u-16)*8;
                    if (tmp8u < 64) {
-                        GX.q[0] = (EX->q[0] >> tmp8u) | (EX->q[1] << (64 - tmp8u));
-                        GX.q[1] = (EX->q[1] >> tmp8u);
+                        GX.q[0] = (GX.q[0] >> tmp8u) | (GX.q[1] << (64 - tmp8u));
+                        GX.q[1] = (GX.q[1] >> tmp8u);
                    } else {
-                        GX.q[0] = EX->q[1] >> (tmp8u - 64);
+                        GX.q[0] = GX.q[1] >> (tmp8u - 64);
                        GX.q[1] = 0;
                    }                    
                } else {
                    tmp8u*=8;
                    if (tmp8u < 64) {
-                        GX.q[0] = (GX.q[0] >> tmp8u) | (GX.q[1] << (64 - tmp8u));
-                        GX.q[1] = (GX.q[1] >> tmp8u) | (EX->q[0] << (64-tmp8u));
+                        GX.q[0] = (EX->q[0] >> tmp8u) | (EX->q[1] << (64 - tmp8u));
+                        GX.q[1] = (EX->q[1] >> tmp8u) | (GX.q[0] << (64-tmp8u));
                    } else {
-                        GX.q[0] = GX.q[1] >> (tmp8u - 64) | (EX->q[0] << (tmp8u));
-                        GX.q[1] = (EX->q[0] << (64-tmp8u)) | (EX->q[1] >> (tmp8u - 64));
+                        tmp8u -= 64;
+                        GX.q[0] = (EX->q[1] >> tmp8u) | (GX.q[0] << (64 - tmp8u));
+                        GX.q[1] = (GX.q[0] >> tmp8u) | (GX.q[1] >> (64 - tmp8u));
                    }                    
                }
+                #else
+                {
+                    for (int i=0; i<16; ++i, ++tmp8u)
+                        eax1.ub[i] = (tmp8u>15)?((tmp8u>31)?0:GX.ub[tmp8u-16]):EX->ub[tmp8u];
+                    GX.q[0] = eax1.q[0];
+                    GX.q[1] = eax1.q[1];
+                }
+                #endif
                break;
            default:
                goto _default;
@@ -354,18 +565,26 @@
    _6f_0x60:  /* PUNPCKLBW Gx,Ex */
        nextop = F8;
        GET_EX;
-        for(int i=7; i>0; --i)
+        for(int i=7; i>0; --i)  // 0 is untouched
            GX.ub[2 * i] = GX.ub[i];
-        for(int i=0; i<8; ++i)
-            GX.ub[2 * i + 1] = EX->ub[i];
+        if(&GX==EX)
+            for(int i=0; i<8; ++i)
+                GX.ub[2 * i + 1] = GX.ub[2 * i];
+        else 
+            for(int i=0; i<8; ++i)
+                GX.ub[2 * i + 1] = EX->ub[i];
        NEXT;
    _6f_0x61:  /* PUNPCKLWD Gx,Ex */
        nextop = F8;
        GET_EX;
        for(int i=3; i>0; --i)
            GX.uw[2 * i] = GX.uw[i];
-        for(int i=0; i<4; ++i)
-            GX.uw[2 * i + 1] = EX->uw[i];
+        if(&GX==EX)
+            for(int i=0; i<4; ++i)
+                GX.uw[2 * i + 1] = GX.uw[2 * i];
+        else
+            for(int i=0; i<4; ++i)
+                GX.uw[2 * i + 1] = EX->uw[i];
        NEXT;
    _6f_0x62:  /* PUNPCKLDQ Gx,Ex */
        nextop = F8;
@@ -377,10 +596,16 @@
    _6f_0x63:  /* PACKSSWB Gx,Ex */
        nextop = F8;
        GET_EX;
-        for(int i=0; i<8; ++i)
-            GX.sb[i] = (GX.sw[i]<-128)?-128:((GX.sw[i]>127)?127:GX.sw[i]);
-        for(int i=0; i<8; ++i)
-            GX.sb[8+i] = (EX->sw[i]<-128)?-128:((EX->sw[i]>127)?127:EX->sw[i]);
+        if(&GX==EX) {
+            for(int i=0; i<8; ++i)
+                GX.sb[i] = (EX->sw[i]<-128)?-128:((EX->sw[i]>127)?127:EX->sw[i]);
+            GX.q[1] = GX.q[0];
+        } else {
+            for(int i=0; i<8; ++i)
+                GX.sb[i] = (GX.sw[i]<-128)?-128:((GX.sw[i]>127)?127:GX.sw[i]);
+            for(int i=0; i<8; ++i)
+                GX.sb[8+i] = (EX->sw[i]<-128)?-128:((EX->sw[i]>127)?127:EX->sw[i]);
+        }
        NEXT;
    _6f_0x64:  /* PCMPGTB Gx,Ex */
        nextop = F8;
@@ -400,13 +625,19 @@
        for(int i=0; i<4; ++i)
            GX.ud[i] = (GX.sd[i]>EX->sd[i])?0xFFFFFFFF:0x00000000;
        NEXT;
-    _6f_0x67:  /* PACKUSWB */
+    _6f_0x67:  /* PACKUSWB Gx,Ex */
        nextop = F8;
        GET_EX;
-        for(int i=0; i<8; ++i)
-            GX.ub[i] = (GX.sw[i]<0)?0:((GX.sw[i]>0xff)?0xff:GX.sw[i]);
-        for(int i=0; i<8; ++i)
-            GX.ub[8+i] = (EX->sw[i]<0)?0:((EX->sw[i]>0xff)?0xff:EX->sw[i]);
+        if(&GX==EX) {
+            for(int i=0; i<8; ++i)
+                GX.ub[i] = (EX->sw[i]<0)?0:((EX->sw[i]>0xff)?0xff:EX->sw[i]);
+            GX.q[1] = GX.q[0];
+        } else {
+            for(int i=0; i<8; ++i)
+                GX.ub[i] = (GX.sw[i]<0)?0:((GX.sw[i]>0xff)?0xff:GX.sw[i]);
+            for(int i=0; i<8; ++i)
+                GX.ub[8+i] = (EX->sw[i]<0)?0:((EX->sw[i]>0xff)?0xff:EX->sw[i]);
+        }
        NEXT;
    _6f_0x68:  /* PUNPCKHBW Gx,Ex */
        nextop = F8;
@@ -429,20 +660,25 @@
    _6f_0x6A:  /* PUNPCKHDQ Gx,Ex */
        nextop = F8;
        GET_EX;
-        if(EX==&GX) {eax1 = GX; EX = &eax1;}   // copy is needed
+        // no copy needed if &GX==EX
        GX.ud[0] = GX.ud[2];
-        GX.ud[2] = GX.ud[3];
        GX.ud[1] = EX->ud[2];
+        GX.ud[2] = GX.ud[3];
        GX.ud[3] = EX->ud[3];
        NEXT;
    _6f_0x6B:  /* PACKSSDW Gx,Ex */
        nextop = F8;
        GET_EX;
-        if(EX==&GX) {eax1 = GX; EX = &eax1;}   // copy is needed
-        for(int i=0; i<4; ++i)
-            GX.sw[i] = (GX.sd[i]<-32768)?-32768:((GX.sd[i]>32767)?32767:GX.sd[i]);
-        for(int i=0; i<4; ++i)
-            GX.sw[4+i] = (EX->sd[i]<-32768)?-32768:((EX->sd[i]>32767)?32767:EX->sd[i]);
+        if(&GX==EX) {
+            for(int i=0; i<4; ++i)
+                GX.sw[i] = (EX->sd[i]<-32768)?-32768:((EX->sd[i]>32767)?32767:EX->sd[i]);
+            GX.q[1] = GX.q[0];
+        } else {
+            for(int i=0; i<4; ++i)
+                GX.sw[i] = (GX.sd[i]<-32768)?-32768:((GX.sd[i]>32767)?32767:GX.sd[i]);
+            for(int i=0; i<4; ++i)
+                GX.sw[4+i] = (EX->sd[i]<-32768)?-32768:((EX->sd[i]>32767)?32767:EX->sd[i]);
+        }
        NEXT;
    _6f_0x6C:  /* PUNPCKLQDQ Gx,Ex */
        nextop = F8;
@@ -598,6 +834,17 @@
            GX.ud[i] = (GX.ud[i]==EX->ud[i])?0xffffffff:0;
        NEXT;

+    _6f_0x7C:  /* HADDPD Gx, Ex */
+        nextop = F8;
+        GET_EX;
+        GX.d[0] += GX.d[1];
+        if(EX==&GX) {
+            GX.d[1] = GX.d[0];
+        } else {
+            GX.d[1] = EX->d[0] + EX->d[1];
+        }
+        NEXT;
+
    _6f_0x7E:  /* MOVD Ed, Gx */
        nextop = F8;
        GET_ED;
@@ -623,7 +870,10 @@
    _6f_0xA5:                      /* SHLD Ew,Gw,CL */
        nextop = F8;
        GET_EW;
-        tmp8u = (opcode==0xA4)?(F8):R_CL;
+        if(opcode==0xA4)
+            tmp8u = F8;
+        else
+            tmp8u = R_CL;
        EW->word[0] = shld16(emu, EW->word[0], GW.word[0], tmp8u);
        NEXT;

@@ -642,7 +892,10 @@
    _6f_0xAD:                      /* SHRD Ew,Gw,CL */
        nextop = F8;
        GET_EW;
-        tmp8u = (opcode==0xAC)?(F8):R_CL;
+        if(opcode==0xAC)
+            tmp8u = F8;
+        else
+            tmp8u = R_CL;
        EW->word[0] = shrd16(emu, EW->word[0], GW.word[0], tmp8u);
        NEXT;

@@ -679,7 +932,79 @@
        GET_EB;
        GW.word[0] = EB->byte[0];
        NEXT;
+    _6f_0xB7:                      /* MOVZX Gw,Ew */
+        nextop = F8;
+        GET_EW;
+        GW.word[0] = EW->word[0];   // yeah, the ZX is useless here
+        NEXT;

+    _6f_0xBA:                      
+        nextop = F8;
+        switch((nextop>>3)&7) {
+            case 4:                 /* BT Ew,Ib */
+                CHECK_FLAGS(emu);
+                GET_EW;
+                tmp8u = F8;
+                if((nextop&0xC0)!=0xC0)
+                {
+                    EW=(reg32_t*)(((uint16_t*)(EW))+(tmp8u>>4));
+                }
+                tmp8u&=15;
+                if(EW->word[0] & (1<<tmp8u))
+                    SET_FLAG(F_CF);
+                else
+                    CLEAR_FLAG(F_CF);
+                break;
+            case 5:             /* BTS Ew, Ib */
+                CHECK_FLAGS(emu);
+                GET_EW;
+                tmp8u = F8;
+                if((nextop&0xC0)!=0xC0)
+                {
+                    EW=(reg32_t*)(((uint16_t*)(EW))+(tmp8u>>4));
+                }
+                tmp8u&=15;
+                if(EW->word[0] & (1<<tmp8u)) {
+                    SET_FLAG(F_CF);
+                } else
+                    EW->word[0] ^= (1<<tmp8u);
+                    CLEAR_FLAG(F_CF);
+                break;
+            case 6:             /* BTR Ew, Ib */
+                CHECK_FLAGS(emu);
+                GET_EW;
+                tmp8u = F8;
+                if((nextop&0xC0)!=0xC0)
+                {
+                    EW=(reg32_t*)(((uint16_t*)(ED))+(tmp8u>>4));
+                }
+                tmp8u&=15;
+                if(EW->word[0] & (1<<tmp8u)) {
+                    SET_FLAG(F_CF);
+                    EW->word[0] ^= (1<<tmp8u);
+                } else
+                    CLEAR_FLAG(F_CF);
+                break;
+            case 7:             /* BTC Ew, Ib */
+                CHECK_FLAGS(emu);
+                GET_EW;
+                tmp8u = F8;
+                if((nextop&0xC0)!=0xC0)
+                {
+                    EW=(reg32_t*)(((uint16_t*)(EW))+(tmp8u>>4));
+                }
+                tmp8u&=15;
+                if(EW->word[0] & (1<<tmp8u))
+                    SET_FLAG(F_CF);
+                else
+                    CLEAR_FLAG(F_CF);
+                EW->word[0] ^= (1<<tmp8u);
+                break;
+
+            default:
+                goto _default;
+        }
+        NEXT;
    _6f_0xBB:                      /* BTC Ew,Gw */
        CHECK_FLAGS(emu);
        nextop = F8;
@@ -773,6 +1098,23 @@
        GX.q[1] = eax1.q[1];
        NEXT;

+    _6f_0xC8:
+    _6f_0xC9:
+    _6f_0xCA:
+    _6f_0xCB:
+    _6f_0xCC:
+    _6f_0xCD:
+    _6f_0xCE:
+    _6f_0xCF:                  /* BSWAP reg16 */
+        tmp8s = opcode&7;
+        emu->regs[tmp8s].word[0] = __builtin_bswap16(emu->regs[tmp8s].word[0]);
+        NEXT;
+    _6f_0xD0:  /* ADDSUBPD Gx, Ex */
+        nextop = F8;
+        GET_EX;
+        GX.d[0] -= EX->d[0];
+        GX.d[1] += EX->d[1];
+        NEXT;
    _6f_0xD1:  /* PSRLW Gx, Ex */
        nextop = F8;
        GET_EX;
@@ -808,7 +1150,7 @@
        GET_EX;
        for(int i=0; i<8; ++i) {
            tmp32s = (int32_t)GX.sw[i] * EX->sw[i];
-            GX.sw[i] = tmp32s;
+            GX.sw[i] = tmp32s&0xffff;
        }
        NEXT;
    _6f_0xD6:  /* MOVQ Ex,Gx */
@@ -820,18 +1162,21 @@
        NEXT;
    _6f_0xD7:  /* PMOVMSKB Gd,Ex */
        nextop = F8;
-        GET_EX;
-        GD.dword[0] = 0;
-        for (int i=0; i<16; ++i)
-            if(EX->ub[i]&0x80)
-                GD.dword[0] |= (1<<i);
-        NEXT;
+        if((nextop&0xC0)==0xC0) {
+            GET_EX;
+            GD.dword[0] = 0;
+            for (int i=0; i<16; ++i)
+                if(EX->ub[i]&0x80)
+                    GD.dword[0] |= (1<<i);
+            NEXT;
+        } else
+            goto _default;
    _6f_0xD8:  /* PSUBUSB Gx,Ex */
        nextop = F8;
        GET_EX;
        for(int i=0; i<16; ++i) {
            tmp16s = (int16_t)GX.ub[i] - EX->ub[i];
-            GX.ub[i] = (tmp16s<0)?0:((tmp16s>255)?255:tmp16s);
+            GX.ub[i] = (tmp16s<0)?0:tmp16s;
        }
        NEXT;
    _6f_0xD9:  /* PSUBUSW Gx,Ex */
@@ -839,10 +1184,15 @@
        GET_EX;
        for(int i=0; i<8; ++i) {
            tmp32s = (int32_t)GX.uw[i] - EX->uw[i];
-            GX.uw[i] = (tmp32s<0)?0:((tmp32s>0xffff)?0xffff:tmp32s);
+            GX.uw[i] = (tmp32s<0)?0:tmp32s;
        }
        NEXT;
-
+    _6f_0xDA:  /* PMINUB Gx, Ex */
+        nextop = F8;
+        GET_EX;
+        for (int i=0; i<16; ++i)
+            if(EX->ub[i]<GX.ub[i]) GX.ub[i] = EX->ub[i];
+        NEXT;
    _6f_0xDB:  /* PAND Gx,Ex */
        nextop = F8;
        GET_EX;
@@ -857,7 +1207,14 @@
            GX.ub[i] = (tmp16s>255)?255:tmp16s;
        }
        NEXT;
-
+    _6f_0xDD:  /* PADDUSW Gx,Ex */
+        nextop = F8;
+        GET_EX;
+        for(int i=0; i<8; ++i) {
+            tmp32s = (int32_t)GX.uw[i] + EX->uw[i];
+            GX.uw[i] = (tmp32s>65535)?65535:tmp32s;
+        }
+        NEXT;
    _6f_0xDE:  /* PMAXUB Gx, Ex */
        nextop = F8;
        GET_EX;
@@ -867,23 +1224,43 @@
    _6f_0xDF:  /* PANDN Gx,Ex */
        nextop = F8;
        GET_EX;
-        GX.q[0] = (~GX.q[0]) & EX->q[0];
-        GX.q[1] = (~GX.q[1]) & EX->q[1];
+        GX.q[0] = (~(GX.q[0])) & EX->q[0];
+        GX.q[1] = (~(GX.q[1])) & EX->q[1];
+        NEXT;
+    _6f_0xE0:  /* PAVGB Gx, Ex */
+        nextop = F8;
+        GET_EX;
+        for (int i=0; i<16; ++i)
+            GX.ub[i] = ((uint16_t)GX.ub[i] + EX->ub[i] + 1)>>1;
        NEXT;
-
    _6f_0xE1:  /* PSRAW Gx, Ex */
        nextop = F8;
        GET_EX;
        tmp8u=(EX->q[0]>15)?16:EX->ub[0];
-        for (int i=0; i<8; ++i) GX.sw[i] >>= tmp8u;
+        for (int i=0; i<8; ++i) 
+            GX.sw[i] >>= tmp8u;
        NEXT;
    _6f_0xE2:  /* PSRAD Gx, Ex */
        nextop = F8;
        GET_EX;
        tmp8u=(EX->q[0]>31)?32:EX->ub[0];
-        for (int i=0; i<4; ++i) GX.sd[i] >>= tmp8u;
+        for (int i=0; i<4; ++i)
+            GX.sd[i] >>= tmp8u;
+        NEXT;
+    _6f_0xE3:  /* PAVGW Gx, Ex */
+        nextop = F8;
+        GET_EX;
+        for (int i=0; i<8; ++i)
+            GX.uw[i] = ((uint32_t)GX.uw[i] + EX->uw[i] + 1)>>1;
+        NEXT;
+    _6f_0xE4:  /* PMULHUW Gx, Ex */
+        nextop = F8;
+        GET_EX;
+        for(int i=0; i<8; ++i) {
+            tmp32u = (uint32_t)GX.uw[i] * EX->uw[i];
+            GX.uw[i] = (tmp32u>>16)&0xffff;
+        }
        NEXT;
-
    _6f_0xE5:  /* PMULHW Gx, Ex */
        nextop = F8;
        GET_EX;
@@ -899,7 +1276,7 @@
        GX.sd[1] = EX->d[1];
        GX.q[1] = 0;
        NEXT;
-    _6f_0xE7:                      /* MOVNTDQ Ex, Gx */
+    _6f_0xE7:   /* MOVNTDQ Ex, Gx */
        nextop = F8;
        GET_EX;
        EX->q[0] = GX.q[0];
@@ -910,7 +1287,7 @@
        GET_EX;
        for(int i=0; i<16; ++i) {
            tmp16s = (int16_t)GX.sb[i] - EX->sb[i];
-            GX.ub[i] = (tmp16s<-128)?-128:((tmp16s>127)?127:tmp16s);
+            GX.sb[i] = (tmp16s<-128)?-128:((tmp16s>127)?127:tmp16s);
        }
        NEXT;
    _6f_0xE9:  /* PSUBSW Gx,Ex */
@@ -1023,12 +1400,17 @@
                opx2->ub[i] = GX.ub[i];
        }
        NEXT;
-
+    _6f_0xF8:  /* PSUBB Gx,Ex */
+        nextop = F8;
+        GET_EX;
+        for(int i=0; i<16; ++i)
+            GX.sb[i] -= EX->sb[i];
+        NEXT;
    _6f_0xF9:  /* PSUBW Gx,Ex */
        nextop = F8;
        GET_EX;
        for(int i=0; i<8; ++i)
-            GX.uw[i] -= EX->uw[i];
+            GX.sw[i] -= EX->sw[i];
        NEXT;
    _6f_0xFA:  /* PSUBD Gx,Ex */
        nextop = F8;
@@ -1064,5 +1446,8 @@
        GX.sd[2] += EX->sd[2];
        GX.sd[3] += EX->sd[3];
        NEXT;
-
-
+ 
+    _fini:
+        R_EIP = ip;
+        return;
+}
@@ -22,6 +22,7 @@
 #ifdef HAVE_TRACE
 #include "x86trace.h"
 #endif
+#include "x86tls.h"

 #define PARITY(x)   (((emu->x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0)
 #define XOR2(x) 	(((x) ^ ((x)>>1)) & 0x1)
@@ -31,9 +32,9 @@ int32_t EXPORT my___libc_start_main(x86emu_t* emu, int *(main) (int, char * *, c
    //TODO: register rtld_fini
    //TODO: register fini
    // let's cheat and set all args...
-    Push(emu, (uint32_t)emu->context->envv);
-    Push(emu, (uint32_t)emu->context->argv);
-    Push(emu, (uint32_t)emu->context->argc);
+    Push(emu, (uint32_t)my_context->envv);
+    Push(emu, (uint32_t)my_context->argv);
+    Push(emu, (uint32_t)my_context->argc);
    if(init) {
        PushExit(emu);
        R_EIP=(uint32_t)*init;
@@ -43,7 +44,7 @@ int32_t EXPORT my___libc_start_main(x86emu_t* emu, int *(main) (int, char * *, c
            return 0;
        emu->quit = 0;
    }
-    printf_log(LOG_DEBUG, "Transfert to main(%d, %p, %p)=>%p from __libc_start_main\n", emu->context->argc, emu->context->argv, emu->context->envv, main);
+    printf_log(LOG_DEBUG, "Transfert to main(%d, %p, %p)=>%p from __libc_start_main\n", my_context->argc, my_context->argv, my_context->envv, main);
    // call main and finish
    PushExit(emu);
    R_EIP=(uint32_t)main;
@@ -53,36 +54,30 @@ int32_t EXPORT my___libc_start_main(x86emu_t* emu, int *(main) (int, char * *, c
    return 0;
 }

-const char* GetNativeName(x86emu_t* emu, void* p)
+const char* GetNativeName(void* p)
 {
-    static char unknown[10] = "???";
-    const char *ret = GetNameOffset(emu->context->maplib, p);
-    if(ret)
-        return ret;
-
    static char buff[500] = {0};
    Dl_info info;
-    if(dladdr(p, &info)==0)
-        return unknown;
-    else {
+    if(dladdr(p, &info)==0) {
+        const char *ret = GetNameOffset(my_context->maplib, p);
+        if(ret)
+            return ret;
+        sprintf(buff, "%s(%p)", "???", p);
+        return buff;
+    } else {
        if(info.dli_sname) {
            strcpy(buff, info.dli_sname);
            if(info.dli_fname) {
                strcat(buff, " ("); strcat(buff, info.dli_fname); strcat(buff, ")");
            }
-        } else
-            return unknown;
+        } else {
+            sprintf(buff, "%s(%s/%p)", "???", info.dli_fname, p);
+            return buff;
+        }
    }
    return buff;
 }

-uintptr_t pltResolver = ~0;
-void PltResolver(x86emu_t* emu, uint32_t id, uintptr_t ofs)
-{
-    printf_log(LOG_INFO, "PltResolver: Ofs=%p, Id=%d (IP=%p, ESP+4=%p)", (void*)ofs, id, *(void**)(R_ESP), *(void**)(R_ESP+4));
-    emu->quit=1;
-}
-
 void UpdateFlags(x86emu_t *emu)
 {
    uint32_t cc;
@@ -537,6 +532,152 @@ void UpdateFlags(x86emu_t *emu)
            CLEAR_FLAG(F_CF);
            CLEAR_FLAG(F_AF);
            break;
+        case d_cmp8:
+            CLEAR_FLAG(F_CF);
+            CONDITIONAL_SET_FLAG(emu->res & 0x80, F_SF);
+            CONDITIONAL_SET_FLAG((emu->res & 0xff) == 0, F_ZF);
+            CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+            bc = (emu->res & (~emu->op1 | emu->op2)) | (~emu->op1 & emu->op2);
+            CONDITIONAL_SET_FLAG(bc & 0x80, F_CF);
+            CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF);
+            CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+            break;
+        case d_cmp16:
+            CONDITIONAL_SET_FLAG(emu->res & 0x8000, F_SF);
+            CONDITIONAL_SET_FLAG((emu->res & 0xffff) == 0, F_ZF);
+            CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+            bc = (emu->res & (~emu->op1 | emu->op2)) | (~emu->op1 & emu->op2);
+            CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF);
+            CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF);
+            CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+            break;
+        case d_cmp32:
+        	CONDITIONAL_SET_FLAG(emu->res & 0x80000000, F_SF);
+        	CONDITIONAL_SET_FLAG(!emu->res, F_ZF);
+        	CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+        	bc = (emu->res & (~emu->op1 | emu->op2)) | (~emu->op1 & emu->op2);
+        	CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF);
+        	CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF);
+        	CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+            break;
+        case d_tst8:
+        	CLEAR_FLAG(F_OF);
+        	CONDITIONAL_SET_FLAG(emu->res & 0x80, F_SF);
+        	CONDITIONAL_SET_FLAG(emu->res == 0, F_ZF);
+        	CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+        	CLEAR_FLAG(F_CF);
+            break;
+        case d_tst16:
+            CLEAR_FLAG(F_OF);
+            CONDITIONAL_SET_FLAG(emu->res & 0x8000, F_SF);
+            CONDITIONAL_SET_FLAG(emu->res == 0, F_ZF);
+            CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+            CLEAR_FLAG(F_CF);
+            break;
+        case d_tst32:
+        	CLEAR_FLAG(F_OF);
+        	CONDITIONAL_SET_FLAG(emu->res & 0x80000000, F_SF);
+        	CONDITIONAL_SET_FLAG(emu->res == 0, F_ZF);
+        	CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+        	CLEAR_FLAG(F_CF);
+            break;
+        case d_adc8:
+            CONDITIONAL_SET_FLAG(emu->res & 0x100, F_CF);
+            CONDITIONAL_SET_FLAG((emu->res & 0xff) == 0, F_ZF);
+            CONDITIONAL_SET_FLAG(emu->res & 0x80, F_SF);
+            CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+            cc = (emu->op1 & emu->op2) | ((~emu->res) & (emu->op1 | emu->op2));
+            CONDITIONAL_SET_FLAG(XOR2(cc >> 6), F_OF);
+            CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+            break;
+        case d_adc16:
+            CONDITIONAL_SET_FLAG(emu->res & 0x10000, F_CF);
+            CONDITIONAL_SET_FLAG((emu->res & 0xffff) == 0, F_ZF);
+            CONDITIONAL_SET_FLAG(emu->res & 0x8000, F_SF);
+            CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+            cc = (emu->op1 & emu->op2) | ((~emu->res) & (emu->op1 | emu->op2));
+            CONDITIONAL_SET_FLAG(XOR2(cc >> 14), F_OF);
+            CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+            break;
+        case d_adc32:
+            if(emu->res == (emu->op1+emu->op2)) {
+                lo = (emu->op1 & 0xFFFF) + (emu->op2 & 0xFFFF);
+            } else {
+                lo = 1 + (emu->op1 & 0xFFFF) + (emu->op2 & 0xFFFF);
+            }
+            hi = (lo >> 16) + (emu->op1 >> 16) + (emu->op2 >> 16);
+            CONDITIONAL_SET_FLAG(hi & 0x10000, F_CF);
+            CONDITIONAL_SET_FLAG(!emu->res, F_ZF);
+            CONDITIONAL_SET_FLAG(emu->res & 0x80000000, F_SF);
+            CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+            cc = (emu->op2 & emu->op1) | ((~emu->res) & (emu->op2 | emu->op1));
+            CONDITIONAL_SET_FLAG(XOR2(cc >> 30), F_OF);
+            CONDITIONAL_SET_FLAG(cc & 0x8, F_AF);
+            break;
+        case d_sbb8:
+            CONDITIONAL_SET_FLAG(emu->res & 0x80, F_SF);
+            CONDITIONAL_SET_FLAG((emu->res & 0xff) == 0, F_ZF);
+            CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+            bc = (emu->res & (~emu->op1 | emu->op2)) | (~emu->op1 & emu->op2);
+            CONDITIONAL_SET_FLAG(bc & 0x80, F_CF);
+            CONDITIONAL_SET_FLAG(XOR2(bc >> 6), F_OF);
+            CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+            break;
+        case d_sbb16:
+            CONDITIONAL_SET_FLAG(emu->res & 0x8000, F_SF);
+            CONDITIONAL_SET_FLAG((emu->res & 0xffff) == 0, F_ZF);
+            CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+            bc = (emu->res & (~emu->op1 | emu->op2)) | (~emu->op1 & emu->op2);
+            CONDITIONAL_SET_FLAG(bc & 0x8000, F_CF);
+            CONDITIONAL_SET_FLAG(XOR2(bc >> 14), F_OF);
+            CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+            break;
+        case d_sbb32:
+            CONDITIONAL_SET_FLAG(emu->res & 0x80000000, F_SF);
+            CONDITIONAL_SET_FLAG(!emu->res, F_ZF);
+            CONDITIONAL_SET_FLAG(PARITY(emu->res & 0xff), F_PF);
+            bc = (emu->res & (~emu->op1 | emu->op2)) | (~emu->op1 & emu->op2);
+            CONDITIONAL_SET_FLAG(bc & 0x80000000, F_CF);
+            CONDITIONAL_SET_FLAG(XOR2(bc >> 30), F_OF);
+            CONDITIONAL_SET_FLAG(bc & 0x8, F_AF);
+            break;
+        case d_rol8:
+            if(emu->op2 == 1) {
+                CONDITIONAL_SET_FLAG((emu->res + (emu->res >> 7)) & 1, F_OF);
+            }
+        	CONDITIONAL_SET_FLAG(emu->res & 0x1, F_CF);
+            break;
+        case d_rol16:
+            if(emu->op2 == 1) {
+                CONDITIONAL_SET_FLAG((emu->res + (emu->res >> 15)) & 1, F_OF);
+            }
+        	CONDITIONAL_SET_FLAG(emu->res & 0x1, F_CF);
+            break;
+        case d_rol32:
+            if(emu->op2 == 1) {
+                CONDITIONAL_SET_FLAG((emu->res + (emu->res >> 31)) & 1, F_OF);
+            }
+        	CONDITIONAL_SET_FLAG(emu->res & 0x1, F_CF);
+            break;
+        case d_ror8:
+            if(emu->op2 == 1) {
+                CONDITIONAL_SET_FLAG(XOR2(emu->res >> 6), F_OF);
+            }
+            CONDITIONAL_SET_FLAG(emu->res & (1 << 7), F_CF);
+            break;
+        case d_ror16:
+            if(emu->op2 == 1) {
+                CONDITIONAL_SET_FLAG(XOR2(emu->res >> 14), F_OF);
+            }
+            CONDITIONAL_SET_FLAG(emu->res & (1 << 15), F_CF);
+            break;
+        case d_ror32:
+            if(emu->op2 == 1) {
+                CONDITIONAL_SET_FLAG(XOR2(emu->res >> 30), F_OF);
+            }
+            CONDITIONAL_SET_FLAG(emu->res & (1 << 31), F_CF);
+            break;
+
        case d_unknown:
            printf_log(LOG_NONE, "Box86: %p trying to evaluate Unknown defered Flags\n", (void*)R_EIP);
            break;
@@ -544,132 +685,99 @@ void UpdateFlags(x86emu_t *emu)
    RESET_FLAGS(emu);
 }

-
-void PackFlags(x86emu_t* emu)
+uintptr_t GetSegmentBaseEmu(x86emu_t* emu, int seg)
 {
-    #define GO(A) emu->packed_eflags.f.F__##A = emu->flags[F_##A];
-    GO(CF);
-    GO(res1);
-    GO(PF);
-    GO(res2);
-    GO(AF);
-    GO(res3);
-    GO(ZF);
-    GO(SF);
-    GO(TF);
-    GO(IF);
-    GO(DF);
-    GO(OF);
-    GO(IOPL);
-    GO(NT);
-    GO(dummy);
-    GO(RF);
-    GO(VM);
-    GO(AC);
-    GO(VIF);
-    GO(VIP);
-    GO(ID);
-    #undef GO
-}
-void UnpackFlags(x86emu_t* emu)
-{
-    #define GO(A) emu->flags[F_##A] = emu->packed_eflags.f.F__##A;
-    GO(CF);
-    GO(res1);
-    GO(PF);
-    GO(res2);
-    GO(AF);
-    GO(res3);
-    GO(ZF);
-    GO(SF);
-    GO(TF);
-    GO(IF);
-    GO(DF);
-    GO(OF);
-    GO(IOPL);
-    GO(NT);
-    GO(dummy);
-    GO(RF);
-    GO(VM);
-    GO(AC);
-    GO(VIF);
-    GO(VIP);
-    GO(ID);
-    #undef GO
+    if(emu->segs_serial[seg] != emu->context->sel_serial) {
+        emu->segs_offs[seg] = (uintptr_t)GetSegmentBase(emu->segs[seg]);
+        emu->segs_serial[seg] = emu->context->sel_serial;
+    }
+    return emu->segs_offs[seg];
 }

-uintptr_t GetGSBaseEmu(x86emu_t* emu)
+
+const char* getAddrFunctionName(uintptr_t addr)
 {
-    return (uintptr_t)GetGSBase(emu->context);
+    static char ret[1000];
+    uint32_t sz = 0;
+    uintptr_t start = 0;
+    const char* symbname = FindNearestSymbolName(FindElfAddress(my_context, addr), (void*)addr, &start, &sz);
+    if(symbname && addr>=start && (addr<(start+sz) || !sz)) {
+        if(addr==start)
+            sprintf(ret, "%s/%s", ElfName(FindElfAddress(my_context, addr)), symbname);
+        else
+            sprintf(ret, "%s/%s + %d", ElfName(FindElfAddress(my_context, addr)), symbname, addr - start);
+    } else
+        sprintf(ret, "???");
+    return ret;
+}
+
+void printFunctionAddr(uintptr_t nextaddr, const char* text)
+{
+    uint32_t sz = 0;
+    uintptr_t start = 0;
+    const char* symbname = FindNearestSymbolName(FindElfAddress(my_context, nextaddr), (void*)nextaddr, &start, &sz);
+    if(symbname && nextaddr>=start && (nextaddr<(start+sz) || !sz)) {
+        if(nextaddr==start)
+            printf_log(LOG_NONE, " (%s%s/%s)", text, ElfName(FindElfAddress(my_context, nextaddr)), symbname);
+        else
+            printf_log(LOG_NONE, " (%s%s/%s + %d)", text, ElfName(FindElfAddress(my_context, nextaddr)), symbname, nextaddr - start);
+    }
 }

 #ifdef HAVE_TRACE
 extern uint64_t start_cnt;
-#define PK(a)   *(uint8_t*)(ip+a)
-#define PK32(a)   *(uint32_t*)(uint8_t*)(ip+a)
-
-static void printFunctionAddr(x86emu_t* emu, uintptr_t nextaddr, const char* text)
-{
-    uint32_t sz = 0;
-    uintptr_t start = 0;
-    const char* symbname = FindNearestSymbolName(FindElfAddress(emu->context, nextaddr), (void*)nextaddr, &start, &sz);
-    if(symbname && nextaddr>=start && nextaddr<(start+sz)) {
-        if(nextaddr==start)
-            printf_log(LOG_NONE, " (%s%s)", text, symbname);
-        else
-            printf_log(LOG_NONE, " (%s%s + 0x%x)", text, symbname, nextaddr - start);
-    }
-}
+#define PK(a)   (*(uint8_t*)(ip+a))
+#define PK32(a)   (*(int32_t*)((uint8_t*)(ip+a)))

 void PrintTrace(x86emu_t* emu, uintptr_t ip, int dynarec)
 {
    if(start_cnt) --start_cnt;
-    if(!start_cnt && emu->dec && (
-            (emu->trace_end == 0) 
-            || ((ip >= emu->trace_start) && (ip < emu->trace_end))) ) {
-        pthread_mutex_lock(&emu->context->mutex_trace);
+    if(!start_cnt && my_context->dec && (
+            (trace_end == 0) 
+            || ((ip >= trace_start) && (ip < trace_end))) ) {
        int tid = syscall(SYS_gettid);
+        pthread_mutex_lock(&my_context->mutex_trace);
 #ifdef DYNAREC
-        if((emu->context->trace_tid != tid) || (emu->context->trace_dynarec!=dynarec)) {
+        if((my_context->trace_tid != tid) || (my_context->trace_dynarec!=dynarec)) {
            printf_log(LOG_NONE, "Thread %04d| (%s) |\n", tid, dynarec?"dyn":"int");
-            emu->context->trace_tid = tid;
-            emu->context->trace_dynarec = dynarec;
+            my_context->trace_tid = tid;
+            my_context->trace_dynarec = dynarec;
        }
 #else
-        if(emu->context->trace_tid != tid) {
+        if(my_context->trace_tid != tid) {
            printf_log(LOG_NONE, "Thread %04d|\n", tid);
-            emu->context->trace_tid = tid;
+            my_context->trace_tid = tid;
        }
 #endif
        printf_log(LOG_NONE, "%s", DumpCPURegs(emu, ip));
        if(PK(0)==0xcc && PK(1)=='S' && PK(2)=='C') {
            uint32_t a = *(uint32_t*)(ip+3);
            if(a==0) {
-                printf_log(LOG_NONE, "0x%p: Exit x86emu\n", (void*)ip);
+                printf_log(LOG_NONE, "%p: Exit x86emu\n", (void*)ip);
            } else {
-                printf_log(LOG_NONE, "0x%p: Native call to %p => %s\n", (void*)ip, (void*)a, GetNativeName(emu, *(void**)(ip+7)));
+                printf_log(LOG_NONE, "%p: Native call to %p => %s\n", (void*)ip, (void*)a, GetNativeName(*(void**)(ip+7)));
            }
        } else {
-            printf_log(LOG_NONE, "%s", DecodeX86Trace(emu->dec, ip));
+            printf_log(LOG_NONE, "%s", DecodeX86Trace(my_context->dec, ip));
            uint8_t peek = PK(0);
            if(peek==0xC3 || peek==0xC2) {
                printf_log(LOG_NONE, " => %p", *(void**)(R_ESP));
-                printFunctionAddr(emu, *(uintptr_t*)(R_ESP), "=> ");
+                printFunctionAddr(*(uintptr_t*)(R_ESP), "=> ");
            } else if(peek==0x55) {
                printf_log(LOG_NONE, " => STACK_TOP: %p", *(void**)(R_ESP));
-                printFunctionAddr(emu, ip, "here: ");
+                printFunctionAddr(ip, "here: ");
            } else if(peek==0xE8) { // Call
-                uintptr_t nextaddr = ip + PK32(1);
-                printFunctionAddr(emu, nextaddr, "=> ");
+                uintptr_t nextaddr = ip + 5 + PK32(1);
+                printFunctionAddr(nextaddr, "=> ");
            } else if(peek==0xFF) {
                if(PK(1)==0x25) {
-                    uintptr_t nextaddr = ip + PK32(2);
-                    printFunctionAddr(emu, nextaddr, "=> ");
+                    uintptr_t nextaddr = ip + 6 + PK32(2);
+                    printFunctionAddr(nextaddr, "=> ");
                }
            }
            printf_log(LOG_NONE, "\n");
        }
-        pthread_mutex_unlock(&emu->context->mutex_trace);
+        pthread_mutex_unlock(&my_context->mutex_trace);
    }
 }

@@ -122,6 +122,33 @@ static inline reg32_t* GetEw16(x86emu_t *emu, uint32_t v)
    }
 }

+static inline reg32_t* GetEw16off(x86emu_t *emu, uint32_t v, uintptr_t offset)
+{
+    uint32_t m = v&0xC7;    // filter Ed
+    if(m>=0xC0) {
+         return &emu->regs[(m&0x07)];
+    } else {
+        uint32_t base = 0;
+        switch(m&7) {
+            case 0: base = R_BX+R_SI; break;
+            case 1: base = R_BX+R_DI; break;
+            case 2: base = R_BP+R_SI; break;
+            case 3: base = R_BP+R_DI; break;
+            case 4: base =      R_SI; break;
+            case 5: base =      R_DI; break;
+            case 6: base =      R_BP; break;
+            case 7: base =      R_BX; break;
+        }
+        switch((m>>6)&3) {
+            case 0: if(m==6) base = Fetch16(emu); break;
+            case 1: base += Fetch8s(emu); break;
+            case 2: base += Fetch16s(emu); break;
+            // case 3 is C0..C7, already dealt with
+        }
+        return (reg32_t*)(base+offset);
+    }
+}
+
 static inline mmx_regs_t* GetEm(x86emu_t *emu, uint32_t v)
 {
    uint32_t m = v&0xC7;    // filter Ed
@@ -173,18 +200,20 @@ void Run660F(x86emu_t *emu);
 void Run66D9(x86emu_t *emu);    // x87
 void Run6766(x86emu_t *emu);
 void RunGS(x86emu_t *emu);
+void RunFS(x86emu_t *emu);
 void RunLock(x86emu_t *emu);
+void RunLock66(x86emu_t *emu);

 void x86Syscall(x86emu_t *emu);
 void x86Int3(x86emu_t* emu);
 x86emu_t* x86emu_fork(x86emu_t* e, int forktype);

-void PackFlags(x86emu_t* emu);
-void UnpackFlags(x86emu_t* emu);
+uintptr_t GetSegmentBaseEmu(x86emu_t* emu, int seg);
+#define GetGSBaseEmu(emu)    GetSegmentBaseEmu(emu, _GS)
+#define GetFSBaseEmu(emu)    GetSegmentBaseEmu(emu, _FS)
+#define GetESBaseEmu(emu)    GetSegmentBaseEmu(emu, _ES)

-uintptr_t GetGSBaseEmu(x86emu_t* emu);
-
-const char* GetNativeName(x86emu_t* emu, void* p);
+const char* GetNativeName(void* p);

 #ifdef HAVE_TRACE
 void PrintTrace(x86emu_t* emu, uintptr_t ip, int dynarec);