Merge pull request #1367 from ucgJhe/dev

update return register accordingly for all arch

qiling/cc/arm.py

@@ -20,8 +20,7 @@ class QlArmBaseCC(QlCommonBaseCC):
         return 1
 
     def setReturnAddress(self, addr: int) -> None:
-        # TODO: do we need to update LR?
-        self.arch.stack_push(addr)
+        self.arch.regs.lr = addr
 
     def unwind(self, nslots: int) -> int:
         # TODO: cleanup?

qiling/cc/mips.py

@@ -12,6 +12,9 @@ class mipso32(QlCommonBaseCC):
     _shadow = 4
     _retaddr_on_stack = False
 
+    def setReturnAddress(self, addr: int):
+        self.arch.regs.ra = addr
+
     @staticmethod
     def getNumSlots(argbits: int):
         return 1

qiling/cc/ppc.py

@@ -21,3 +21,6 @@ class ppc(QlCommonBaseCC):
     @staticmethod
     def getNumSlots(argbits: int):
         return 1
+
+    def setReturnAddress(self, addr: int):
+        self.arch.regs.lr = addr

qiling/cc/riscv.py

@@ -19,4 +19,7 @@ class riscv(QlCommonBaseCC):
 
     @staticmethod
     def getNumSlots(argbits: int):
-        return 1
+        return 1
+
+    def setReturnAddress(self, addr: int):
+        self.arch.regs.ra = addr