Fix the debug output of UART

This commit is contained in:
dataisland
2021-10-21 18:21:30 +08:00
parent 9ddceea833
commit 6e54620d87
2 changed files with 21 additions and 11 deletions
+1 -10
View File
@@ -13,17 +13,8 @@ def stm32f411_freertos():
ql.hw.create('rcc')
ql.hw.create('gpioa')
count = 0
def counter():
nonlocal count
count += 1
ql.hw.gpioa.hook_set(5, counter)
ql.hw.systick.set_ratio(100)
ql.run(count=200000)
print(count >= 5)
print(ql.hw.usart2.recv())
if __name__ == "__main__":
stm32f411_freertos()
+20 -1
View File
@@ -74,17 +74,36 @@ class STM32F4xxUsart(QlPeripheral):
self.usart.SR &= value | USART_SR.CTS | USART_SR.LBD | USART_SR.TC | USART_SR.RXNE
elif offset == self.struct.DR.offset:
self.send_buf.append(value & 0xff)
self.transfer(value & 0xff)
self.usart.SR |= USART_SR.TC
else:
data = (value).to_bytes(size, byteorder='little')
ctypes.memmove(ctypes.addressof(self.usart) + offset, data, size)
def transfer(self, value: int):
""" transfer data to buffer
Args:
value (int): transfer data
"""
self.send_buf.append(value)
self.ql.log.debug(f'[{self.label}] Send {repr(chr(value))}')
def send(self, data: bytes):
""" send user data into USART.
Args:
data (bytes): Input Data
"""
self.recv_buf += data
def recv(self) -> bytes:
""" receive data from USART.
Returns:
bytes: USART send buffer data
"""
data = bytes(self.send_buf)
self.send_buf.clear()
return data