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Merge pull request #1574 from elicn/fix-qdb-cortexm
Fix qdb support for ARM Cortex-M
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@@ -3,12 +3,14 @@
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# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
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#
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from typing import Dict, Optional
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from typing import ClassVar, Dict, Optional
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from .arch import Arch
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class ArchARM(Arch):
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_flags_reg: ClassVar[str] = 'cpsr'
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def __init__(self) -> None:
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regs = (
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'r0', 'r1', 'r2', 'r3',
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@@ -134,6 +136,8 @@ class ArchARM(Arch):
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class ArchCORTEX_M(ArchARM):
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_flags_reg: ClassVar[str] = 'xpsr'
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def __init__(self):
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super().__init__()
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@@ -27,11 +27,11 @@ class BranchPredictorARM(BranchPredictor, ArchARM):
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stop = 'udf'
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def get_cpsr(self) -> Tuple[bool, bool, bool, bool]:
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"""Get flags map of CPSR.
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def get_cond_flags(self) -> Tuple[bool, bool, bool, bool]:
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"""Get condition status flags from CPSR / xPSR.
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"""
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cpsr = self.read_reg('cpsr')
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cpsr = self.read_reg(self._flags_reg)
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return (
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(cpsr & (0b1 << 28)) != 0, # V, overflow flag
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@@ -122,9 +122,9 @@ class BranchPredictorARM(BranchPredictor, ArchARM):
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def __is_taken(cc: int) -> Tuple[bool, Tuple[bool, ...]]:
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pred = predicate[cc]
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cpsr = self.get_cpsr()
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flags = self.get_cond_flags()
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return pred(*cpsr), cpsr
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return pred(*flags), flags
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# conditions predicate selector
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predicate: Dict[int, Callable[..., bool]] = {
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@@ -215,13 +215,13 @@ class BranchPredictorARM(BranchPredictor, ArchARM):
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where = __parse_op(operands[1], **msize[suffix])
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elif iname in binop:
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going, cpsr = __is_taken(insn.cc)
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going, flags = __is_taken(insn.cc)
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if going:
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operator = binop[iname]
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op1 = __parse_op(operands[1])
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op2 = __parse_op(operands[2])
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carry = int(cpsr[1])
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carry = int(flags[1])
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where = (op1 and op2) and operator(op1, op2, carry)
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@@ -3,7 +3,7 @@
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# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
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#
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from typing import Iterator, Optional
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from typing import Iterator
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from .render import Render, ContextRender
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from ..arch import ArchARM, ArchCORTEX_M
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@@ -15,7 +15,7 @@ class ContextRenderARM(ContextRender, ArchARM):
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"""
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def print_mode_info(self) -> None:
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cpsr = self.read_reg('cpsr')
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cpsr = self.read_reg(self._flags_reg)
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flags = ArchARM.get_flags(cpsr)
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mode = ArchARM.get_mode(cpsr)
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