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Merge pull request #1148 from elicn/gdb-improv

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New and improved gdbserver
This commit is contained in:
Eli
2022-05-11 02:36:57 +03:00
committed by GitHub
parent 561f3a80d3 fc8c22a5a4
commit 7c1580e82d
37 changed files with 1879 additions and 1380 deletions
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qiling/arch/arm64.py
+7 -1
View File
@@ -26,7 +26,13 @@ class QlArchARM64(QlArch):
def regs(self) -> QlRegisterManager:
regs_map = dict(
**arm64_const.reg_map,
**arm64_const.reg_map_w
**arm64_const.reg_map_b,
**arm64_const.reg_map_d,
**arm64_const.reg_map_h,
**arm64_const.reg_map_q,
**arm64_const.reg_map_s,
**arm64_const.reg_map_w,
**arm64_const.reg_map_v
)
pc_reg = 'pc'
qiling/arch/arm64_const.py
+279 -69
View File
@@ -1,79 +1,289 @@
#!/usr/bin/env python3
#
#
# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
#
from unicorn.arm64_const import *
reg_map = {
"x0": UC_ARM64_REG_X0,
"x1": UC_ARM64_REG_X1,
"x2": UC_ARM64_REG_X2,
"x3": UC_ARM64_REG_X3,
"x4": UC_ARM64_REG_X4,
"x5": UC_ARM64_REG_X5,
"x6": UC_ARM64_REG_X6,
"x7": UC_ARM64_REG_X7,
"x8": UC_ARM64_REG_X8,
"x9": UC_ARM64_REG_X9,
"x10": UC_ARM64_REG_X10,
"x11": UC_ARM64_REG_X11,
"x12": UC_ARM64_REG_X12,
"x13": UC_ARM64_REG_X13,
"x14": UC_ARM64_REG_X14,
"x15": UC_ARM64_REG_X15,
"x16": UC_ARM64_REG_X16,
"x17": UC_ARM64_REG_X17,
"x18": UC_ARM64_REG_X18,
"x19": UC_ARM64_REG_X19,
"x20": UC_ARM64_REG_X20,
"x21": UC_ARM64_REG_X21,
"x22": UC_ARM64_REG_X22,
"x23": UC_ARM64_REG_X23,
"x24": UC_ARM64_REG_X24,
"x25": UC_ARM64_REG_X25,
"x26": UC_ARM64_REG_X26,
"x27": UC_ARM64_REG_X27,
"x28": UC_ARM64_REG_X28,
"x29": UC_ARM64_REG_X29,
"x30": UC_ARM64_REG_X30,
"sp": UC_ARM64_REG_SP,
"pc": UC_ARM64_REG_PC,
"lr": UC_ARM64_REG_LR,
"cpacr_el1": UC_ARM64_REG_CPACR_EL1,
"tpidr_el0": UC_ARM64_REG_TPIDR_EL0,
"x0": UC_ARM64_REG_X0,
"x1": UC_ARM64_REG_X1,
"x2": UC_ARM64_REG_X2,
"x3": UC_ARM64_REG_X3,
"x4": UC_ARM64_REG_X4,
"x5": UC_ARM64_REG_X5,
"x6": UC_ARM64_REG_X6,
"x7": UC_ARM64_REG_X7,
"x8": UC_ARM64_REG_X8,
"x9": UC_ARM64_REG_X9,
"x10": UC_ARM64_REG_X10,
"x11": UC_ARM64_REG_X11,
"x12": UC_ARM64_REG_X12,
"x13": UC_ARM64_REG_X13,
"x14": UC_ARM64_REG_X14,
"x15": UC_ARM64_REG_X15,
"x16": UC_ARM64_REG_X16,
"x17": UC_ARM64_REG_X17,
"x18": UC_ARM64_REG_X18,
"x19": UC_ARM64_REG_X19,
"x20": UC_ARM64_REG_X20,
"x21": UC_ARM64_REG_X21,
"x22": UC_ARM64_REG_X22,
"x23": UC_ARM64_REG_X23,
"x24": UC_ARM64_REG_X24,
"x25": UC_ARM64_REG_X25,
"x26": UC_ARM64_REG_X26,
"x27": UC_ARM64_REG_X27,
"x28": UC_ARM64_REG_X28,
"x29": UC_ARM64_REG_X29,
"x30": UC_ARM64_REG_X30,
"sp": UC_ARM64_REG_SP,
"pc": UC_ARM64_REG_PC,
"lr": UC_ARM64_REG_LR,
"cpacr_el1": UC_ARM64_REG_CPACR_EL1,
"tpidr_el0": UC_ARM64_REG_TPIDR_EL0
}
reg_map_b = {
"b0" : UC_ARM64_REG_B0,
"b1" : UC_ARM64_REG_B1,
"b2" : UC_ARM64_REG_B2,
"b3" : UC_ARM64_REG_B3,
"b4" : UC_ARM64_REG_B4,
"b5" : UC_ARM64_REG_B5,
"b6" : UC_ARM64_REG_B6,
"b7" : UC_ARM64_REG_B7,
"b8" : UC_ARM64_REG_B8,
"b9" : UC_ARM64_REG_B9,
"b10" : UC_ARM64_REG_B10,
"b11" : UC_ARM64_REG_B11,
"b12" : UC_ARM64_REG_B12,
"b13" : UC_ARM64_REG_B13,
"b14" : UC_ARM64_REG_B14,
"b15" : UC_ARM64_REG_B15,
"b16" : UC_ARM64_REG_B16,
"b17" : UC_ARM64_REG_B17,
"b18" : UC_ARM64_REG_B18,
"b19" : UC_ARM64_REG_B19,
"b20" : UC_ARM64_REG_B20,
"b21" : UC_ARM64_REG_B21,
"b22" : UC_ARM64_REG_B22,
"b23" : UC_ARM64_REG_B23,
"b24" : UC_ARM64_REG_B24,
"b25" : UC_ARM64_REG_B25,
"b26" : UC_ARM64_REG_B26,
"b27" : UC_ARM64_REG_B27,
"b28" : UC_ARM64_REG_B28,
"b29" : UC_ARM64_REG_B29,
"b30" : UC_ARM64_REG_B30,
"b31" : UC_ARM64_REG_B31
}
reg_map_d = {
"d0" : UC_ARM64_REG_D0,
"d1" : UC_ARM64_REG_D1,
"d2" : UC_ARM64_REG_D2,
"d3" : UC_ARM64_REG_D3,
"d4" : UC_ARM64_REG_D4,
"d5" : UC_ARM64_REG_D5,
"d6" : UC_ARM64_REG_D6,
"d7" : UC_ARM64_REG_D7,
"d8" : UC_ARM64_REG_D8,
"d9" : UC_ARM64_REG_D9,
"d10" : UC_ARM64_REG_D10,
"d11" : UC_ARM64_REG_D11,
"d12" : UC_ARM64_REG_D12,
"d13" : UC_ARM64_REG_D13,
"d14" : UC_ARM64_REG_D14,
"d15" : UC_ARM64_REG_D15,
"d16" : UC_ARM64_REG_D16,
"d17" : UC_ARM64_REG_D17,
"d18" : UC_ARM64_REG_D18,
"d19" : UC_ARM64_REG_D19,
"d20" : UC_ARM64_REG_D20,
"d21" : UC_ARM64_REG_D21,
"d22" : UC_ARM64_REG_D22,
"d23" : UC_ARM64_REG_D23,
"d24" : UC_ARM64_REG_D24,
"d25" : UC_ARM64_REG_D25,
"d26" : UC_ARM64_REG_D26,
"d27" : UC_ARM64_REG_D27,
"d28" : UC_ARM64_REG_D28,
"d29" : UC_ARM64_REG_D29,
"d30" : UC_ARM64_REG_D30,
"d31" : UC_ARM64_REG_D31
}
reg_map_h = {
"h0" : UC_ARM64_REG_H0,
"h1" : UC_ARM64_REG_H1,
"h2" : UC_ARM64_REG_H2,
"h3" : UC_ARM64_REG_H3,
"h4" : UC_ARM64_REG_H4,
"h5" : UC_ARM64_REG_H5,
"h6" : UC_ARM64_REG_H6,
"h7" : UC_ARM64_REG_H7,
"h8" : UC_ARM64_REG_H8,
"h9" : UC_ARM64_REG_H9,
"h10" : UC_ARM64_REG_H10,
"h11" : UC_ARM64_REG_H11,
"h12" : UC_ARM64_REG_H12,
"h13" : UC_ARM64_REG_H13,
"h14" : UC_ARM64_REG_H14,
"h15" : UC_ARM64_REG_H15,
"h16" : UC_ARM64_REG_H16,
"h17" : UC_ARM64_REG_H17,
"h18" : UC_ARM64_REG_H18,
"h19" : UC_ARM64_REG_H19,
"h20" : UC_ARM64_REG_H20,
"h21" : UC_ARM64_REG_H21,
"h22" : UC_ARM64_REG_H22,
"h23" : UC_ARM64_REG_H23,
"h24" : UC_ARM64_REG_H24,
"h25" : UC_ARM64_REG_H25,
"h26" : UC_ARM64_REG_H26,
"h27" : UC_ARM64_REG_H27,
"h28" : UC_ARM64_REG_H28,
"h29" : UC_ARM64_REG_H29,
"h30" : UC_ARM64_REG_H30,
"h31" : UC_ARM64_REG_H31
}
reg_map_q = {
"q0" : UC_ARM64_REG_Q0,
"q1" : UC_ARM64_REG_Q1,
"q2" : UC_ARM64_REG_Q2,
"q3" : UC_ARM64_REG_Q3,
"q4" : UC_ARM64_REG_Q4,
"q5" : UC_ARM64_REG_Q5,
"q6" : UC_ARM64_REG_Q6,
"q7" : UC_ARM64_REG_Q7,
"q8" : UC_ARM64_REG_Q8,
"q9" : UC_ARM64_REG_Q9,
"q10" : UC_ARM64_REG_Q10,
"q11" : UC_ARM64_REG_Q11,
"q12" : UC_ARM64_REG_Q12,
"q13" : UC_ARM64_REG_Q13,
"q14" : UC_ARM64_REG_Q14,
"q15" : UC_ARM64_REG_Q15,
"q16" : UC_ARM64_REG_Q16,
"q17" : UC_ARM64_REG_Q17,
"q18" : UC_ARM64_REG_Q18,
"q19" : UC_ARM64_REG_Q19,
"q20" : UC_ARM64_REG_Q20,
"q21" : UC_ARM64_REG_Q21,
"q22" : UC_ARM64_REG_Q22,
"q23" : UC_ARM64_REG_Q23,
"q24" : UC_ARM64_REG_Q24,
"q25" : UC_ARM64_REG_Q25,
"q26" : UC_ARM64_REG_Q26,
"q27" : UC_ARM64_REG_Q27,
"q28" : UC_ARM64_REG_Q28,
"q29" : UC_ARM64_REG_Q29,
"q30" : UC_ARM64_REG_Q30,
"q31" : UC_ARM64_REG_Q31
}
reg_map_s = {
"s0" : UC_ARM64_REG_S0,
"s1" : UC_ARM64_REG_S1,
"s2" : UC_ARM64_REG_S2,
"s3" : UC_ARM64_REG_S3,
"s4" : UC_ARM64_REG_S4,
"s5" : UC_ARM64_REG_S5,
"s6" : UC_ARM64_REG_S6,
"s7" : UC_ARM64_REG_S7,
"s8" : UC_ARM64_REG_S8,
"s9" : UC_ARM64_REG_S9,
"s10" : UC_ARM64_REG_S10,
"s11" : UC_ARM64_REG_S11,
"s12" : UC_ARM64_REG_S12,
"s13" : UC_ARM64_REG_S13,
"s14" : UC_ARM64_REG_S14,
"s15" : UC_ARM64_REG_S15,
"s16" : UC_ARM64_REG_S16,
"s17" : UC_ARM64_REG_S17,
"s18" : UC_ARM64_REG_S18,
"s19" : UC_ARM64_REG_S19,
"s20" : UC_ARM64_REG_S20,
"s21" : UC_ARM64_REG_S21,
"s22" : UC_ARM64_REG_S22,
"s23" : UC_ARM64_REG_S23,
"s24" : UC_ARM64_REG_S24,
"s25" : UC_ARM64_REG_S25,
"s26" : UC_ARM64_REG_S26,
"s27" : UC_ARM64_REG_S27,
"s28" : UC_ARM64_REG_S28,
"s29" : UC_ARM64_REG_S29,
"s30" : UC_ARM64_REG_S30,
"s31" : UC_ARM64_REG_S31
}
reg_map_w = {
"w0" : UC_ARM64_REG_W0,
"w1" : UC_ARM64_REG_W1,
"w2" : UC_ARM64_REG_W2,
"w3" : UC_ARM64_REG_W3,
"w4" : UC_ARM64_REG_W4,
"w5" : UC_ARM64_REG_W5,
"w6" : UC_ARM64_REG_W6,
"w7" : UC_ARM64_REG_W7,
"w8" : UC_ARM64_REG_W8,
"w9" : UC_ARM64_REG_W9,
"w10" : UC_ARM64_REG_W10,
"w11" : UC_ARM64_REG_W11,
"w12" : UC_ARM64_REG_W12,
"w13" : UC_ARM64_REG_W13,
"w14" : UC_ARM64_REG_W14,
"w15" : UC_ARM64_REG_W15,
"w16" : UC_ARM64_REG_W16,
"w17" : UC_ARM64_REG_W17,
"w18" : UC_ARM64_REG_W18,
"w19" : UC_ARM64_REG_W19,
"w20" : UC_ARM64_REG_W20,
"w21" : UC_ARM64_REG_W21,
"w22" : UC_ARM64_REG_W22,
"w23" : UC_ARM64_REG_W23,
"w24" : UC_ARM64_REG_W24,
"w25" : UC_ARM64_REG_W25,
"w26" : UC_ARM64_REG_W26,
"w27" : UC_ARM64_REG_W27,
"w28" : UC_ARM64_REG_W28,
"w29" : UC_ARM64_REG_W29,
"w30" : UC_ARM64_REG_W30,
}
"w0" : UC_ARM64_REG_W0,
"w1" : UC_ARM64_REG_W1,
"w2" : UC_ARM64_REG_W2,
"w3" : UC_ARM64_REG_W3,
"w4" : UC_ARM64_REG_W4,
"w5" : UC_ARM64_REG_W5,
"w6" : UC_ARM64_REG_W6,
"w7" : UC_ARM64_REG_W7,
"w8" : UC_ARM64_REG_W8,
"w9" : UC_ARM64_REG_W9,
"w10" : UC_ARM64_REG_W10,
"w11" : UC_ARM64_REG_W11,
"w12" : UC_ARM64_REG_W12,
"w13" : UC_ARM64_REG_W13,
"w14" : UC_ARM64_REG_W14,
"w15" : UC_ARM64_REG_W15,
"w16" : UC_ARM64_REG_W16,
"w17" : UC_ARM64_REG_W17,
"w18" : UC_ARM64_REG_W18,
"w19" : UC_ARM64_REG_W19,
"w20" : UC_ARM64_REG_W20,
"w21" : UC_ARM64_REG_W21,
"w22" : UC_ARM64_REG_W22,
"w23" : UC_ARM64_REG_W23,
"w24" : UC_ARM64_REG_W24,
"w25" : UC_ARM64_REG_W25,
"w26" : UC_ARM64_REG_W26,
"w27" : UC_ARM64_REG_W27,
"w28" : UC_ARM64_REG_W28,
"w29" : UC_ARM64_REG_W29,
"w30" : UC_ARM64_REG_W30
}
reg_map_v = {
"v0" : UC_ARM64_REG_V0,
"v1" : UC_ARM64_REG_V1,
"v2" : UC_ARM64_REG_V2,
"v3" : UC_ARM64_REG_V3,
"v4" : UC_ARM64_REG_V4,
"v5" : UC_ARM64_REG_V5,
"v6" : UC_ARM64_REG_V6,
"v7" : UC_ARM64_REG_V7,
"v8" : UC_ARM64_REG_V8,
"v9" : UC_ARM64_REG_V9,
"v10" : UC_ARM64_REG_V10,
"v11" : UC_ARM64_REG_V11,
"v12" : UC_ARM64_REG_V12,
"v13" : UC_ARM64_REG_V13,
"v14" : UC_ARM64_REG_V14,
"v15" : UC_ARM64_REG_V15,
"v16" : UC_ARM64_REG_V16,
"v17" : UC_ARM64_REG_V17,
"v18" : UC_ARM64_REG_V18,
"v19" : UC_ARM64_REG_V19,
"v20" : UC_ARM64_REG_V20,
"v21" : UC_ARM64_REG_V21,
"v22" : UC_ARM64_REG_V22,
"v23" : UC_ARM64_REG_V23,
"v24" : UC_ARM64_REG_V24,
"v25" : UC_ARM64_REG_V25,
"v26" : UC_ARM64_REG_V26,
"v27" : UC_ARM64_REG_V27,
"v28" : UC_ARM64_REG_V28,
"v29" : UC_ARM64_REG_V29,
"v30" : UC_ARM64_REG_V30,
"v31" : UC_ARM64_REG_V31
}
qiling/arch/arm_const.py
+57 -33
View File
@@ -4,39 +4,63 @@
#
from unicorn.arm_const import *
from enum import IntEnum
reg_map = {
"r0": UC_ARM_REG_R0,
"r1": UC_ARM_REG_R1,
"r2": UC_ARM_REG_R2,
"r3": UC_ARM_REG_R3,
"r4": UC_ARM_REG_R4,
"r5": UC_ARM_REG_R5,
"r6": UC_ARM_REG_R6,
"r7": UC_ARM_REG_R7,
"r8": UC_ARM_REG_R8,
"r9": UC_ARM_REG_R9,
"r10": UC_ARM_REG_R10,
"r11": UC_ARM_REG_R11,
"r12": UC_ARM_REG_R12,
"sp": UC_ARM_REG_SP,
"lr": UC_ARM_REG_LR,
"pc": UC_ARM_REG_PC,
# CPSR needs to be at offset 25 for GDB, see https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=gdb/arch/arm.h;h=fa589fd0582c0add627a068e6f4947a909c45e86;hb=HEAD#l34
# The fp registers inbetween have become obsolete
"f0": UC_ARM_REG_INVALID,
"f1": UC_ARM_REG_INVALID,
"f2": UC_ARM_REG_INVALID,
"f3": UC_ARM_REG_INVALID,
"f4": UC_ARM_REG_INVALID,
"f5": UC_ARM_REG_INVALID,
"f6": UC_ARM_REG_INVALID,
"f7": UC_ARM_REG_INVALID,
"fps": UC_ARM_REG_INVALID,
"cpsr": UC_ARM_REG_CPSR,
"c1_c0_2": UC_ARM_REG_C1_C0_2,
"c13_c0_3": UC_ARM_REG_C13_C0_3,
"fpexc": UC_ARM_REG_FPEXC,
"r0": UC_ARM_REG_R0,
"r1": UC_ARM_REG_R1,
"r2": UC_ARM_REG_R2,
"r3": UC_ARM_REG_R3,
"r4": UC_ARM_REG_R4,
"r5": UC_ARM_REG_R5,
"r6": UC_ARM_REG_R6,
"r7": UC_ARM_REG_R7,
"r8": UC_ARM_REG_R8,
"r9": UC_ARM_REG_R9,
"r10": UC_ARM_REG_R10,
"r11": UC_ARM_REG_R11,
"r12": UC_ARM_REG_R12,
"sp": UC_ARM_REG_SP,
"lr": UC_ARM_REG_LR,
"pc": UC_ARM_REG_PC,
"cpsr": UC_ARM_REG_CPSR,
"c1_c0_2": UC_ARM_REG_C1_C0_2,
"c13_c0_3": UC_ARM_REG_C13_C0_3,
"fpexc": UC_ARM_REG_FPEXC
}
reg_vfp = {
"d0" : UC_ARM_REG_D0,
"d1" : UC_ARM_REG_D1,
"d2" : UC_ARM_REG_D2,
"d3" : UC_ARM_REG_D3,
"d4" : UC_ARM_REG_D4,
"d5" : UC_ARM_REG_D5,
"d6" : UC_ARM_REG_D6,
"d7" : UC_ARM_REG_D7,
"d8" : UC_ARM_REG_D8,
"d9" : UC_ARM_REG_D9,
"d10" : UC_ARM_REG_D10,
"d11" : UC_ARM_REG_D11,
"d12" : UC_ARM_REG_D12,
"d13" : UC_ARM_REG_D13,
"d14" : UC_ARM_REG_D14,
"d15" : UC_ARM_REG_D15,
"d16" : UC_ARM_REG_D16,
"d17" : UC_ARM_REG_D17,
"d18" : UC_ARM_REG_D18,
"d19" : UC_ARM_REG_D19,
"d20" : UC_ARM_REG_D20,
"d21" : UC_ARM_REG_D21,
"d22" : UC_ARM_REG_D22,
"d23" : UC_ARM_REG_D23,
"d24" : UC_ARM_REG_D24,
"d25" : UC_ARM_REG_D25,
"d26" : UC_ARM_REG_D26,
"d27" : UC_ARM_REG_D27,
"d28" : UC_ARM_REG_D28,
"d29" : UC_ARM_REG_D29,
"d30" : UC_ARM_REG_D30,
"d31" : UC_ARM_REG_D31,
"fpscr" : UC_ARM_REG_FPSCR
}
qiling/arch/mips.py
+2 -1
View File
@@ -37,7 +37,8 @@ class QlArchMIPS(QlArch):
def regs(self) -> QlRegisterManager:
regs_map = dict(
**mips_const.reg_map,
**mips_const.reg_map_afpr128
**mips_const.reg_map_afpr128,
**mips_const.reg_map_fpu
)
pc_reg = 'pc'
qiling/arch/mips_const.py
+69 -1
View File
@@ -6,6 +6,39 @@
from unicorn.mips_const import *
reg_map = {
"r0" : UC_MIPS_REG_0,
"r1" : UC_MIPS_REG_1,
"r2" : UC_MIPS_REG_2,
"r3" : UC_MIPS_REG_3,
"r4" : UC_MIPS_REG_4,
"r5" : UC_MIPS_REG_5,
"r6" : UC_MIPS_REG_6,
"r7" : UC_MIPS_REG_7,
"r8" : UC_MIPS_REG_8,
"r9" : UC_MIPS_REG_9,
"r10" : UC_MIPS_REG_10,
"r11" : UC_MIPS_REG_11,
"r12" : UC_MIPS_REG_12,
"r13" : UC_MIPS_REG_13,
"r14" : UC_MIPS_REG_14,
"r15" : UC_MIPS_REG_15,
"r16" : UC_MIPS_REG_16,
"r17" : UC_MIPS_REG_17,
"r18" : UC_MIPS_REG_18,
"r19" : UC_MIPS_REG_19,
"r20" : UC_MIPS_REG_20,
"r21" : UC_MIPS_REG_21,
"r22" : UC_MIPS_REG_22,
"r23" : UC_MIPS_REG_23,
"r24" : UC_MIPS_REG_24,
"r25" : UC_MIPS_REG_25,
"r26" : UC_MIPS_REG_26,
"r27" : UC_MIPS_REG_27,
"r28" : UC_MIPS_REG_28,
"r29" : UC_MIPS_REG_29,
"r30" : UC_MIPS_REG_30,
"r31" : UC_MIPS_REG_31,
"zero": UC_MIPS_REG_ZERO,
"at": UC_MIPS_REG_AT,
"v0": UC_MIPS_REG_V0,
@@ -49,4 +82,39 @@ reg_map = {
reg_map_afpr128 = {
"cp0_config3" : UC_MIPS_REG_CP0_CONFIG3,
"cp0_userlocal": UC_MIPS_REG_CP0_USERLOCAL,
}
}
reg_map_fpu = {
"f0" : UC_MIPS_REG_F0,
"f1" : UC_MIPS_REG_F1,
"f2" : UC_MIPS_REG_F2,
"f3" : UC_MIPS_REG_F3,
"f4" : UC_MIPS_REG_F4,
"f5" : UC_MIPS_REG_F5,
"f6" : UC_MIPS_REG_F6,
"f7" : UC_MIPS_REG_F7,
"f8" : UC_MIPS_REG_F8,
"f9" : UC_MIPS_REG_F9,
"f10" : UC_MIPS_REG_F10,
"f11" : UC_MIPS_REG_F11,
"f12" : UC_MIPS_REG_F12,
"f13" : UC_MIPS_REG_F13,
"f14" : UC_MIPS_REG_F14,
"f15" : UC_MIPS_REG_F15,
"f16" : UC_MIPS_REG_F16,
"f17" : UC_MIPS_REG_F17,
"f18" : UC_MIPS_REG_F18,
"f19" : UC_MIPS_REG_F19,
"f20" : UC_MIPS_REG_F20,
"f21" : UC_MIPS_REG_F21,
"f22" : UC_MIPS_REG_F22,
"f23" : UC_MIPS_REG_F23,
"f24" : UC_MIPS_REG_F24,
"f25" : UC_MIPS_REG_F25,
"f26" : UC_MIPS_REG_F26,
"f27" : UC_MIPS_REG_F27,
"f28" : UC_MIPS_REG_F28,
"f29" : UC_MIPS_REG_F29,
"f30" : UC_MIPS_REG_F30,
"f31" : UC_MIPS_REG_F31
}
qiling/arch/register.py
-6
View File
@@ -102,12 +102,6 @@ class QlRegisterManager:
return self.uc.reg_write(self.uc_pc, value)
@property
def arch_pc_name(self) -> str:
"""Get the architectural program counter register name.
"""
return next(k for k, v in self.register_mapping.items() if v == self.uc_pc)
@property
def arch_sp(self) -> int:
qiling/arch/x86.py
-33
View File
@@ -4,14 +4,11 @@
#
from functools import cached_property
from typing import Union
from unicorn import Uc, UC_ARCH_X86, UC_MODE_16, UC_MODE_32, UC_MODE_64
from capstone import Cs, CS_ARCH_X86, CS_MODE_16, CS_MODE_32, CS_MODE_64
from keystone import Ks, KS_ARCH_X86, KS_MODE_16, KS_MODE_32, KS_MODE_64
from unicorn.x86_const import UC_X86_REG_EFLAGS
from qiling.arch.arch import QlArch
from qiling.arch.msr import QlMsrManager
from qiling.arch.register import QlRegisterManager
@@ -126,33 +123,3 @@ class QlArchX8664(QlArchIntel):
@cached_property
def assembler(self) -> Ks:
return Ks(KS_ARCH_X86, KS_MODE_64)
# TODO: generalize this
def __reg_bits(self, register: int) -> int:
# all regs in reg_map_misc are 16 bits except of eflags
if register == UC_X86_REG_EFLAGS:
return 32
regmaps = (
(x86_const.reg_map_8, 8),
(x86_const.reg_map_16, 16),
(x86_const.reg_map_32, 32),
(x86_const.reg_map_64, 64),
(x86_const.reg_map_misc, 16),
(x86_const.reg_map_cr, 64), # 32 bits for x86
(x86_const.reg_map_st, 32),
(x86_const.reg_map_seg_base, 64), # 32 bits for x86
)
return next((rsize for rmap, rsize in regmaps if register in rmap.values()), 0)
# note: this method was not generalized for all archs since it requires a bookkeeping
# of all registers, while it is used only by gdb and only for x86-64
def reg_bits(self, reg: Union[str, int]) -> int:
"""Get register size in bits.
"""
if type(reg) is str:
reg = self.regs.register_mapping[reg]
return self.__reg_bits(reg)
qiling/arch/x86_const.py
+1 -1
View File
@@ -177,7 +177,7 @@ reg_map_st = {
}
reg_map_misc = {
"ef": UC_X86_REG_EFLAGS,
"eflags": UC_X86_REG_EFLAGS,
"cs": UC_X86_REG_CS,
"ss": UC_X86_REG_SS,
"ds": UC_X86_REG_DS,
qiling/const.py
+7 -3
View File
@@ -60,9 +60,8 @@ class QL_STOP(Flag):
QL_ARCH_INTERPRETER = (QL_ARCH.EVM,)
QL_OS_NONPID = (QL_OS.DOS, QL_OS.UEFI)
QL_OS_POSIX = (QL_OS.LINUX, QL_OS.FREEBSD, QL_OS.MACOS, QL_OS.QNX)
QL_OS_BAREMETAL = (QL_OS.MCU,)
QL_OS_POSIX = (QL_OS.LINUX, QL_OS.FREEBSD, QL_OS.MACOS, QL_OS.QNX)
QL_OS_BAREMETAL = (QL_OS.MCU,)
QL_HOOK_BLOCK = 0b0001
QL_CALL_BLOCK = 0b0010
@@ -83,3 +82,8 @@ arch_os_map = {
QL_ARCH.EVM : QL_OS.EVM,
QL_ARCH.CORTEX_M : QL_OS.MCU
}
__all__ = [
'QL_ENDIAN', 'QL_ARCH', 'QL_OS', 'QL_VERBOSE', 'QL_DEBUGGER', 'QL_INTERCEPT', 'QL_STOP',
'QL_ARCH_INTERPRETER', 'QL_OS_POSIX', 'QL_OS_BAREMETAL', 'QL_HOOK_BLOCK', 'QL_CALL_BLOCK'
]
qiling/debugger/gdb/gdb.py
+913 -752
View File
File diff suppressed because it is too large Load Diff
qiling/debugger/gdb/utils.py
+37 -78
View File
@@ -3,117 +3,76 @@
# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
#
from typing import Optional
from qiling import Qiling
from qiling.const import QL_ARCH
# this code is partially based on uDbg
# @see: https://github.com/iGio90/uDdbg
PROMPT = r'gdb>'
class QlGdbUtils:
def __init__(self):
self.ql: Qiling
self.current_address = 0x0
self.current_address_size = 0x0
self.last_bp = 0x0
self.entry_point = None
self.exit_point = None
self.soft_bp = False
self.has_soft_bp = False
self.bp_list = []
# self.mapping = []
self.breakpoint_count = 0x0
self.skip_bp_count = 0x0
def initialize(self, ql: Qiling, hook_address: int, exit_point: int, mappings=[]):
def __init__(self, ql: Qiling, entry_point: int, exit_point: int):
self.ql = ql
if ql.baremetal:
self.current_address = self.entry_point
else:
self.current_address = self.entry_point = ql.os.entry_point
self.exit_point = exit_point
# self.mapping = mappings
self.bp_list = []
self.last_bp = None
def __entry_point_hook(ql: Qiling):
ql.hook_del(ep_hret)
ql.hook_code(self.dbg_hook)
ql.log.info(f'{PROMPT} stopped at entry point: {ql.arch.regs.arch_pc:#x}')
ql.stop()
ql.log.info(f'{PROMPT} Stop at entry point: {ql.arch.regs.arch_pc:#x}')
ep_hret = ql.hook_address(__entry_point_hook, hook_address)
# set a one-time hook to be dispatched upon reaching program entry point.
# that hook will be used to set up the breakpoint handling hook
ep_hret = ql.hook_address(__entry_point_hook, entry_point)
def dbg_hook(self, ql: Qiling, address: int, size: int):
"""Modified this function for qiling.gdbserver by kabeor from https://github.com/iGio90/uDdbg
"""
if ql.arch.type == QL_ARCH.ARM and ql.arch.is_thumb:
address += 1
try:
if ql.arch.type == QL_ARCH.ARM:
if ql.arch.is_thumb:
address += 1
# resuming emulation after hitting a breakpoint will re-enter this hook.
# avoid an endless hooking loop by detecting and skipping this case
if address == self.last_bp:
self.last_bp = None
# self.mapping.append([(hex(address))])
self.current_address = address
hit_soft_bp = False
elif address in self.bp_list:
self.last_bp = address
if self.soft_bp == True:
self.soft_bp = False
hit_soft_bp = True
# Breakpoints are always added without the LSB, even in Thumb, so they should be checked like this as well
if ((address & ~1) in self.bp_list and (address & ~1) != self.last_bp) or self.has_soft_bp == True:
if self.skip_bp_count > 0:
self.skip_bp_count -= 1
else:
self.breakpoint_count += 1
ql.stop()
self.last_bp = address
ql.log.info(f'{PROMPT} Breakpoint found, stop at address: {address:#x}')
elif address == self.last_bp:
self.last_bp = 0x0
self.has_soft_bp = hit_soft_bp
if self.current_address + size == self.exit_point:
ql.log.debug(f'{PROMPT} emulation entrypoint at {self.entry_point:#x}')
ql.log.debug(f'{PROMPT} emulation exitpoint at {self.exit_point:#x}')
except KeyboardInterrupt:
ql.log.info(f'{PROMPT} Paused at {address:#x}, instruction size = {size:d}')
ql.log.info(f'{PROMPT} breakpoint hit, stopped at {address:#x}')
ql.stop()
except:
raise
# # TODO: not sure what this is about
# if address + size == self.exit_point:
# ql.log.debug(f'{PROMPT} emulation entrypoint at {self.entry_point:#x}')
# ql.log.debug(f'{PROMPT} emulation exitpoint at {self.exit_point:#x}')
def bp_insert(self, addr: int):
if addr not in self.bp_list:
self.bp_list.append(addr)
self.ql.log.info(f'{PROMPT} Breakpoint added at: {addr:#x}')
self.ql.log.info(f'{PROMPT} breakpoint added at {addr:#x}')
def bp_remove(self, addr: int, type = None, len = None):
def bp_remove(self, addr: int):
self.bp_list.remove(addr)
self.ql.log.info(f'{PROMPT} Breakpoint removed at: {addr:#x}')
self.ql.log.info(f'{PROMPT} breakpoint removed from {addr:#x}')
def resume_emu(self, address: int = None, skip_bp: int = 0):
"""Modified this function for qiling.gdbserver by kabeor from https://github.com/iGio90/uDdbg
"""
def resume_emu(self, address: Optional[int] = None, steps: int = 0):
if address is None:
address = self.ql.arch.regs.arch_pc
if address is not None:
if self.ql.arch.type == QL_ARCH.ARM:
if self.ql.arch.is_thumb:
address += 1
if self.ql.arch.type == QL_ARCH.ARM and self.ql.arch.is_thumb:
address += 1
self.current_address = address
op = f'stepping {steps} instructions' if steps else 'resuming'
self.ql.log.info(f'{PROMPT} {op} from {address:#x}')
self.skip_bp_count = skip_bp
if self.exit_point is not None:
self.ql.log.info(f'{PROMPT} Resume at: {self.current_address:#x}')
self.ql.emu_start(self.current_address, self.exit_point)
self.ql.emu_start(address, self.exit_point, count=steps)
qiling/debugger/gdb/xml/a8086/target.xml
+6 -1
View File
@@ -1 +1,6 @@
<?xml version="1.0"?><!DOCTYPE target SYSTEM "gdb-target.dtd"><target><architecture>i8086</architecture><xi:include href="i386-32bit.xml"/></target>
<?xml version="1.0"?>
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target xmlns:xi="http://www.w3.org/2001/XInclude">
<architecture>i8086</architecture>
<xi:include href="i386-32bit.xml"/>
</target>
qiling/debugger/gdb/xml/arm/arm-core.xml
+24 -24
View File
@@ -1,31 +1,31 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2007-2016 Free Software Foundation, Inc.
<!-- Copyright (C) 2007-2020 Free Software Foundation, Inc.
*!Copying and distribution of this file, with or without modification,
*!are permitted in any medium without royalty provided the copyright
*!notice and this notice are preserved. -->
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.arm.core">
<reg name="r0" bitsize="32" type="uint32"/>
<reg name="r1" bitsize="32" type="uint32"/>
<reg name="r2" bitsize="32" type="uint32"/>
<reg name="r3" bitsize="32" type="uint32"/>
<reg name="r4" bitsize="32" type="uint32"/>
<reg name="r5" bitsize="32" type="uint32"/>
<reg name="r6" bitsize="32" type="uint32"/>
<reg name="r7" bitsize="32" type="uint32"/>
<reg name="r8" bitsize="32" type="uint32"/>
<reg name="r9" bitsize="32" type="uint32"/>
<reg name="r10" bitsize="32" type="uint32"/>
<reg name="r11" bitsize="32" type="uint32"/>
<reg name="r12" bitsize="32" type="uint32"/>
<reg name="sp" bitsize="32" type="data_ptr"/>
<reg name="lr" bitsize="32"/>
<reg name="pc" bitsize="32" type="code_ptr"/>
<reg name="r0" bitsize="32" type="uint32"/>
<reg name="r1" bitsize="32" type="uint32"/>
<reg name="r2" bitsize="32" type="uint32"/>
<reg name="r3" bitsize="32" type="uint32"/>
<reg name="r4" bitsize="32" type="uint32"/>
<reg name="r5" bitsize="32" type="uint32"/>
<reg name="r6" bitsize="32" type="uint32"/>
<reg name="r7" bitsize="32" type="uint32"/>
<reg name="r8" bitsize="32" type="uint32"/>
<reg name="r9" bitsize="32" type="uint32"/>
<reg name="r10" bitsize="32" type="uint32"/>
<reg name="r11" bitsize="32" type="uint32"/>
<reg name="r12" bitsize="32" type="uint32"/>
<reg name="sp" bitsize="32" type="data_ptr"/>
<reg name="lr" bitsize="32"/>
<reg name="pc" bitsize="32" type="code_ptr"/>
<!-- The CPSR is register 25, rather than register 16, because
*" the FPA registers historically were placed between the PC
*" and the CPSR in the "g" packet. -->
<reg name="cpsr" bitsize="32" regnum="25"/>
<!-- The CPSR is register 25, rather than register 16, because
the FPA registers historically were placed between the PC
and the CPSR in the "g" packet. -->
<reg name="cpsr" bitsize="32" regnum="25"/>
</feature>
qiling/debugger/gdb/xml/arm/arm-m-profile-with-fpa.xml
-39
View File
@@ -1,39 +0,0 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2019-2020 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.arm.m-profile">
<reg name="r0" bitsize="32"/>
<reg name="r1" bitsize="32"/>
<reg name="r2" bitsize="32"/>
<reg name="r3" bitsize="32"/>
<reg name="r4" bitsize="32"/>
<reg name="r5" bitsize="32"/>
<reg name="r6" bitsize="32"/>
<reg name="r7" bitsize="32"/>
<reg name="r8" bitsize="32"/>
<reg name="r9" bitsize="32"/>
<reg name="r10" bitsize="32"/>
<reg name="r11" bitsize="32"/>
<reg name="r12" bitsize="32"/>
<reg name="sp" bitsize="32" type="data_ptr"/>
<reg name="lr" bitsize="32"/>
<reg name="pc" bitsize="32" type="code_ptr"/>
<!-- Slack for unused FPA registers (f0-f7 + fps). -->
<reg name="" bitsize="96" type="arm_fpa_ext" regnum="16"/>
<reg name="" bitsize="96" type="arm_fpa_ext"/>
<reg name="" bitsize="96" type="arm_fpa_ext"/>
<reg name="" bitsize="96" type="arm_fpa_ext"/>
<reg name="" bitsize="96" type="arm_fpa_ext"/>
<reg name="" bitsize="96" type="arm_fpa_ext"/>
<reg name="" bitsize="96" type="arm_fpa_ext"/>
<reg name="" bitsize="96" type="arm_fpa_ext"/>
<reg name="" bitsize="32"/>
<reg name="xpsr" bitsize="32" regnum="25"/>
</feature>
qiling/debugger/gdb/xml/arm/arm-m-profile.xml
+2 -1
View File
@@ -7,7 +7,7 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.arm.m-profile">
<reg name="r0" bitsize="32"/>
<reg name="r0" bitsize="32" regnum="0"/>
<reg name="r1" bitsize="32"/>
<reg name="r2" bitsize="32"/>
<reg name="r3" bitsize="32"/>
@@ -23,5 +23,6 @@
<reg name="sp" bitsize="32" type="data_ptr"/>
<reg name="lr" bitsize="32"/>
<reg name="pc" bitsize="32" type="code_ptr"/>
<reg name="xpsr" bitsize="32" regnum="25"/>
</feature>
qiling/debugger/gdb/xml/arm/target.xml
+6 -6
View File
@@ -6,9 +6,9 @@
*!notice and this notice are preserved. -->
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target>
<architecture>arm</architecture>
<xi:include href="arm-core.xml"/>
<xi:include href="arm-vfpv3.xml"/>
<feature name="org.gnu.gdb.arm.neon"/>
</target>
<target xmlns:xi="http://www.w3.org/2001/XInclude">
<architecture>arm</architecture>
<xi:include href="arm-core.xml"/>
<xi:include href="arm-vfpv3.xml"/>
<feature name="org.gnu.gdb.arm.neon"/>
</target>
qiling/debugger/gdb/xml/arm64/aarch64-core.xml
+55 -55
View File
@@ -1,67 +1,67 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2009-2016 Free Software Foundation, Inc.
*!Contributed by ARM Ltd.
Contributed by ARM Ltd.
*!Copying and distribution of this file, with or without modification,
*!are permitted in any medium without royalty provided the copyright
*!notice and this notice are preserved. -->
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.aarch64.core">
<reg name="x0" bitsize="64"/>
<reg name="x1" bitsize="64"/>
<reg name="x2" bitsize="64"/>
<reg name="x3" bitsize="64"/>
<reg name="x4" bitsize="64"/>
<reg name="x5" bitsize="64"/>
<reg name="x6" bitsize="64"/>
<reg name="x7" bitsize="64"/>
<reg name="x8" bitsize="64"/>
<reg name="x9" bitsize="64"/>
<reg name="x10" bitsize="64"/>
<reg name="x11" bitsize="64"/>
<reg name="x12" bitsize="64"/>
<reg name="x13" bitsize="64"/>
<reg name="x14" bitsize="64"/>
<reg name="x15" bitsize="64"/>
<reg name="x16" bitsize="64"/>
<reg name="x17" bitsize="64"/>
<reg name="x18" bitsize="64"/>
<reg name="x19" bitsize="64"/>
<reg name="x20" bitsize="64"/>
<reg name="x21" bitsize="64"/>
<reg name="x22" bitsize="64"/>
<reg name="x23" bitsize="64"/>
<reg name="x24" bitsize="64"/>
<reg name="x25" bitsize="64"/>
<reg name="x26" bitsize="64"/>
<reg name="x27" bitsize="64"/>
<reg name="x28" bitsize="64"/>
<reg name="x29" bitsize="64"/>
<reg name="x30" bitsize="64"/>
<reg name="sp" bitsize="64" type="data_ptr"/>
<reg name="x0" bitsize="64"/>
<reg name="x1" bitsize="64"/>
<reg name="x2" bitsize="64"/>
<reg name="x3" bitsize="64"/>
<reg name="x4" bitsize="64"/>
<reg name="x5" bitsize="64"/>
<reg name="x6" bitsize="64"/>
<reg name="x7" bitsize="64"/>
<reg name="x8" bitsize="64"/>
<reg name="x9" bitsize="64"/>
<reg name="x10" bitsize="64"/>
<reg name="x11" bitsize="64"/>
<reg name="x12" bitsize="64"/>
<reg name="x13" bitsize="64"/>
<reg name="x14" bitsize="64"/>
<reg name="x15" bitsize="64"/>
<reg name="x16" bitsize="64"/>
<reg name="x17" bitsize="64"/>
<reg name="x18" bitsize="64"/>
<reg name="x19" bitsize="64"/>
<reg name="x20" bitsize="64"/>
<reg name="x21" bitsize="64"/>
<reg name="x22" bitsize="64"/>
<reg name="x23" bitsize="64"/>
<reg name="x24" bitsize="64"/>
<reg name="x25" bitsize="64"/>
<reg name="x26" bitsize="64"/>
<reg name="x27" bitsize="64"/>
<reg name="x28" bitsize="64"/>
<reg name="x29" bitsize="64"/>
<reg name="x30" bitsize="64"/>
<reg name="sp" bitsize="64" type="data_ptr"/>
<reg name="pc" bitsize="64" type="code_ptr"/>
<reg name="pc" bitsize="64" type="code_ptr"/>
<flags id="cpsr_flags" size="4">
* <field name="SP" start="0" end="0"/>
* <field name="" start="1" end="1"/>
* <field name="EL" start="2" end="3"/>
* <field name="nRW" start="4" end="4"/>
* <field name="" start="5" end="5"/>
* <field name="F" start="6" end="6"/>
* <field name="I" start="7" end="7"/>
* <field name="A" start="8" end="8"/>
* <field name="D" start="9" end="9"/>
<flags id="cpsr_flags" size="4">
<field name="SP" start="0" end="0"/>
<field name="" start="1" end="1"/>
<field name="EL" start="2" end="3"/>
<field name="nRW" start="4" end="4"/>
<field name="" start="5" end="5"/>
<field name="F" start="6" end="6"/>
<field name="I" start="7" end="7"/>
<field name="A" start="8" end="8"/>
<field name="D" start="9" end="9"/>
* <field name="IL" start="20" end="20"/>
* <field name="SS" start="21" end="21"/>
<field name="IL" start="20" end="20"/>
<field name="SS" start="21" end="21"/>
* <field name="V" start="28" end="28"/>
* <field name="C" start="29" end="29"/>
* <field name="Z" start="30" end="30"/>
* <field name="N" start="31" end="31"/>
</flags>
<reg name="cpsr" bitsize="32" type="cpsr_flags"/>
<field name="V" start="28" end="28"/>
<field name="C" start="29" end="29"/>
<field name="Z" start="30" end="30"/>
<field name="N" start="31" end="31"/>
</flags>
<reg name="cpsr" bitsize="32" type="cpsr_flags"/>
</feature>
qiling/debugger/gdb/xml/arm64/aarch64-fpu.xml
+86 -79
View File
@@ -1,86 +1,93 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2009-2016 Free Software Foundation, Inc.
*!Contributed by ARM Ltd.
Contributed by ARM Ltd.
*!Copying and distribution of this file, with or without modification,
*!are permitted in any medium without royalty provided the copyright
*!notice and this notice are preserved. -->
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.aarch64.fpu">
<vector id="v2d" type="ieee_double" count="2"/>
<vector id="v2u" type="uint64" count="2"/>
<vector id="v2i" type="int64" count="2"/>
<vector id="v4f" type="ieee_single" count="4"/>
<vector id="v4u" type="uint32" count="4"/>
<vector id="v4i" type="int32" count="4"/>
<vector id="v8u" type="uint16" count="8"/>
<vector id="v8i" type="int16" count="8"/>
<vector id="v16u" type="uint8" count="16"/>
<vector id="v16i" type="int8" count="16"/>
<vector id="v1u" type="uint128" count="1"/>
<vector id="v1i" type="int128" count="1"/>
<union id="vnd">
* <field name="f" type="v2d"/>
* <field name="u" type="v2u"/>
* <field name="s" type="v2i"/>
</union>
<union id="vns">
* <field name="f" type="v4f"/>
* <field name="u" type="v4u"/>
* <field name="s" type="v4i"/>
</union>
<union id="vnh">
* <field name="u" type="v8u"/>
* <field name="s" type="v8i"/>
</union>
<union id="vnb">
* <field name="u" type="v16u"/>
* <field name="s" type="v16i"/>
</union>
<union id="vnq">
* <field name="u" type="v1u"/>
* <field name="s" type="v1i"/>
</union>
<union id="aarch64v">
* <field name="d" type="vnd"/>
* <field name="s" type="vns"/>
* <field name="h" type="vnh"/>
* <field name="b" type="vnb"/>
* <field name="q" type="vnq"/>
</union>
<reg name="v0" bitsize="128" type="aarch64v" regnum="34"/>
<reg name="v1" bitsize="128" type="aarch64v" />
<reg name="v2" bitsize="128" type="aarch64v" />
<reg name="v3" bitsize="128" type="aarch64v" />
<reg name="v4" bitsize="128" type="aarch64v" />
<reg name="v5" bitsize="128" type="aarch64v" />
<reg name="v6" bitsize="128" type="aarch64v" />
<reg name="v7" bitsize="128" type="aarch64v" />
<reg name="v8" bitsize="128" type="aarch64v" />
<reg name="v9" bitsize="128" type="aarch64v" />
<reg name="v10" bitsize="128" type="aarch64v"/>
<reg name="v11" bitsize="128" type="aarch64v"/>
<reg name="v12" bitsize="128" type="aarch64v"/>
<reg name="v13" bitsize="128" type="aarch64v"/>
<reg name="v14" bitsize="128" type="aarch64v"/>
<reg name="v15" bitsize="128" type="aarch64v"/>
<reg name="v16" bitsize="128" type="aarch64v"/>
<reg name="v17" bitsize="128" type="aarch64v"/>
<reg name="v18" bitsize="128" type="aarch64v"/>
<reg name="v19" bitsize="128" type="aarch64v"/>
<reg name="v20" bitsize="128" type="aarch64v"/>
<reg name="v21" bitsize="128" type="aarch64v"/>
<reg name="v22" bitsize="128" type="aarch64v"/>
<reg name="v23" bitsize="128" type="aarch64v"/>
<reg name="v24" bitsize="128" type="aarch64v"/>
<reg name="v25" bitsize="128" type="aarch64v"/>
<reg name="v26" bitsize="128" type="aarch64v"/>
<reg name="v27" bitsize="128" type="aarch64v"/>
<reg name="v28" bitsize="128" type="aarch64v"/>
<reg name="v29" bitsize="128" type="aarch64v"/>
<reg name="v30" bitsize="128" type="aarch64v"/>
<reg name="v31" bitsize="128" type="aarch64v"/>
<reg name="fpsr" bitsize="32"/>
<reg name="fpcr" bitsize="32"/>
<vector id="v2d" type="ieee_double" count="2"/>
<vector id="v2u" type="uint64" count="2"/>
<vector id="v2i" type="int64" count="2"/>
<vector id="v4f" type="ieee_single" count="4"/>
<vector id="v4u" type="uint32" count="4"/>
<vector id="v4i" type="int32" count="4"/>
<vector id="v8u" type="uint16" count="8"/>
<vector id="v8i" type="int16" count="8"/>
<vector id="v16u" type="uint8" count="16"/>
<vector id="v16i" type="int8" count="16"/>
<vector id="v1u" type="uint128" count="1"/>
<vector id="v1i" type="int128" count="1"/>
<union id="vnd">
<field name="f" type="v2d"/>
<field name="u" type="v2u"/>
<field name="s" type="v2i"/>
</union>
<union id="vns">
<field name="f" type="v4f"/>
<field name="u" type="v4u"/>
<field name="s" type="v4i"/>
</union>
<union id="vnh">
<field name="u" type="v8u"/>
<field name="s" type="v8i"/>
</union>
<union id="vnb">
<field name="u" type="v16u"/>
<field name="s" type="v16i"/>
</union>
<union id="vnq">
<field name="u" type="v1u"/>
<field name="s" type="v1i"/>
</union>
<union id="aarch64v">
<field name="d" type="vnd"/>
<field name="s" type="vns"/>
<field name="h" type="vnh"/>
<field name="b" type="vnb"/>
<field name="q" type="vnq"/>
</union>
<reg name="v0" bitsize="128" type="aarch64v" regnum="34"/>
<reg name="v1" bitsize="128" type="aarch64v" />
<reg name="v2" bitsize="128" type="aarch64v" />
<reg name="v3" bitsize="128" type="aarch64v" />
<reg name="v4" bitsize="128" type="aarch64v" />
<reg name="v5" bitsize="128" type="aarch64v" />
<reg name="v6" bitsize="128" type="aarch64v" />
<reg name="v7" bitsize="128" type="aarch64v" />
<reg name="v8" bitsize="128" type="aarch64v" />
<reg name="v9" bitsize="128" type="aarch64v" />
<reg name="v10" bitsize="128" type="aarch64v"/>
<reg name="v11" bitsize="128" type="aarch64v"/>
<reg name="v12" bitsize="128" type="aarch64v"/>
<reg name="v13" bitsize="128" type="aarch64v"/>
<reg name="v14" bitsize="128" type="aarch64v"/>
<reg name="v15" bitsize="128" type="aarch64v"/>
<reg name="v16" bitsize="128" type="aarch64v"/>
<reg name="v17" bitsize="128" type="aarch64v"/>
<reg name="v18" bitsize="128" type="aarch64v"/>
<reg name="v19" bitsize="128" type="aarch64v"/>
<reg name="v20" bitsize="128" type="aarch64v"/>
<reg name="v21" bitsize="128" type="aarch64v"/>
<reg name="v22" bitsize="128" type="aarch64v"/>
<reg name="v23" bitsize="128" type="aarch64v"/>
<reg name="v24" bitsize="128" type="aarch64v"/>
<reg name="v25" bitsize="128" type="aarch64v"/>
<reg name="v26" bitsize="128" type="aarch64v"/>
<reg name="v27" bitsize="128" type="aarch64v"/>
<reg name="v28" bitsize="128" type="aarch64v"/>
<reg name="v29" bitsize="128" type="aarch64v"/>
<reg name="v30" bitsize="128" type="aarch64v"/>
<reg name="v31" bitsize="128" type="aarch64v"/>
<reg name="fpsr" bitsize="32"/>
<reg name="fpcr" bitsize="32"/>
</feature>
qiling/debugger/gdb/xml/arm64/target.xml
+9 -8
View File
@@ -1,14 +1,15 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2009-2016 Free Software Foundation, Inc.
*!Contributed by ARM Ltd.
Contributed by ARM Ltd.
*!Copying and distribution of this file, with or without modification,
*!are permitted in any medium without royalty provided the copyright
*!notice and this notice are preserved. -->
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target>
<architecture>aarch64</architecture>
<xi:include href="aarch64-core.xml"/>
<xi:include href="aarch64-fpu.xml"/>
<target xmlns:xi="http://www.w3.org/2001/XInclude">
<architecture>aarch64</architecture>
<xi:include href="aarch64-core.xml"/>
<xi:include href="aarch64-fpu.xml"/>
</target>
qiling/debugger/gdb/xml/mips/target.xml
+10 -9
View File
@@ -6,14 +6,15 @@
*!notice and this notice are preserved. -->
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target>
<architecture>mips</architecture>
<osabi>GNU/Linux</osabi>
<xi:include href="mips-cpu.xml"/>
<xi:include href="mips-cp0.xml"/>
<xi:include href="mips-fpu.xml"/>
<target xmlns:xi="http://www.w3.org/2001/XInclude">
<architecture>mips</architecture>
<osabi>GNU/Linux</osabi>
<feature name="org.gnu.gdb.mips.linux">
* <reg name="restart" bitsize="32" group="system"/>
</feature>
<xi:include href="mips-cpu.xml"/>
<xi:include href="mips-cp0.xml"/>
<xi:include href="mips-fpu.xml"/>
<feature name="org.gnu.gdb.mips.linux">
<reg name="restart" bitsize="32" group="system"/>
</feature>
</target>
qiling/debugger/gdb/xml/x86/32bit-core.xml
+52 -52
View File
@@ -7,59 +7,59 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.i386.core">
<flags id="i386_eflags" size="4">
<field name="CF" start="0" end="0"/>
<field name="" start="1" end="1"/>
<field name="PF" start="2" end="2"/>
<field name="AF" start="4" end="4"/>
<field name="ZF" start="6" end="6"/>
<field name="SF" start="7" end="7"/>
<field name="TF" start="8" end="8"/>
<field name="IF" start="9" end="9"/>
<field name="DF" start="10" end="10"/>
<field name="OF" start="11" end="11"/>
<field name="NT" start="14" end="14"/>
<field name="RF" start="16" end="16"/>
<field name="VM" start="17" end="17"/>
<field name="AC" start="18" end="18"/>
<field name="VIF" start="19" end="19"/>
<field name="VIP" start="20" end="20"/>
<field name="ID" start="21" end="21"/>
</flags>
<flags id="i386_eflags" size="4">
<field name="CF" start="0" end="0"/>
<field name="" start="1" end="1"/>
<field name="PF" start="2" end="2"/>
<field name="AF" start="4" end="4"/>
<field name="ZF" start="6" end="6"/>
<field name="SF" start="7" end="7"/>
<field name="TF" start="8" end="8"/>
<field name="IF" start="9" end="9"/>
<field name="DF" start="10" end="10"/>
<field name="OF" start="11" end="11"/>
<field name="NT" start="14" end="14"/>
<field name="RF" start="16" end="16"/>
<field name="VM" start="17" end="17"/>
<field name="AC" start="18" end="18"/>
<field name="VIF" start="19" end="19"/>
<field name="VIP" start="20" end="20"/>
<field name="ID" start="21" end="21"/>
</flags>
<reg name="eax" bitsize="32" type="int32"/>
<reg name="ecx" bitsize="32" type="int32"/>
<reg name="edx" bitsize="32" type="int32"/>
<reg name="ebx" bitsize="32" type="int32"/>
<reg name="esp" bitsize="32" type="data_ptr"/>
<reg name="ebp" bitsize="32" type="data_ptr"/>
<reg name="esi" bitsize="32" type="int32"/>
<reg name="edi" bitsize="32" type="int32"/>
<reg name="eax" bitsize="32" type="int32"/>
<reg name="ecx" bitsize="32" type="int32"/>
<reg name="edx" bitsize="32" type="int32"/>
<reg name="ebx" bitsize="32" type="int32"/>
<reg name="esp" bitsize="32" type="data_ptr"/>
<reg name="ebp" bitsize="32" type="data_ptr"/>
<reg name="esi" bitsize="32" type="int32"/>
<reg name="edi" bitsize="32" type="int32"/>
<reg name="eip" bitsize="32" type="code_ptr"/>
<reg name="eflags" bitsize="32" type="i386_eflags"/>
<reg name="cs" bitsize="32" type="int32"/>
<reg name="ss" bitsize="32" type="int32"/>
<reg name="ds" bitsize="32" type="int32"/>
<reg name="es" bitsize="32" type="int32"/>
<reg name="fs" bitsize="32" type="int32"/>
<reg name="gs" bitsize="32" type="int32"/>
<reg name="eip" bitsize="32" type="code_ptr"/>
<reg name="eflags" bitsize="32" type="i386_eflags"/>
<reg name="cs" bitsize="32" type="int32"/>
<reg name="ss" bitsize="32" type="int32"/>
<reg name="ds" bitsize="32" type="int32"/>
<reg name="es" bitsize="32" type="int32"/>
<reg name="fs" bitsize="32" type="int32"/>
<reg name="gs" bitsize="32" type="int32"/>
<reg name="st0" bitsize="80" type="i387_ext"/>
<reg name="st1" bitsize="80" type="i387_ext"/>
<reg name="st2" bitsize="80" type="i387_ext"/>
<reg name="st3" bitsize="80" type="i387_ext"/>
<reg name="st4" bitsize="80" type="i387_ext"/>
<reg name="st5" bitsize="80" type="i387_ext"/>
<reg name="st6" bitsize="80" type="i387_ext"/>
<reg name="st7" bitsize="80" type="i387_ext"/>
<reg name="st0" bitsize="80" type="i387_ext"/>
<reg name="st1" bitsize="80" type="i387_ext"/>
<reg name="st2" bitsize="80" type="i387_ext"/>
<reg name="st3" bitsize="80" type="i387_ext"/>
<reg name="st4" bitsize="80" type="i387_ext"/>
<reg name="st5" bitsize="80" type="i387_ext"/>
<reg name="st6" bitsize="80" type="i387_ext"/>
<reg name="st7" bitsize="80" type="i387_ext"/>
<reg name="fctrl" bitsize="32" type="int" group="float"/>
<reg name="fstat" bitsize="32" type="int" group="float"/>
<reg name="ftag" bitsize="32" type="int" group="float"/>
<reg name="fiseg" bitsize="32" type="int" group="float"/>
<reg name="fioff" bitsize="32" type="int" group="float"/>
<reg name="foseg" bitsize="32" type="int" group="float"/>
<reg name="fooff" bitsize="32" type="int" group="float"/>
<reg name="fop" bitsize="32" type="int" group="float"/>
</feature>
<reg name="fctrl" bitsize="32" type="int" group="float"/>
<reg name="fstat" bitsize="32" type="int" group="float"/>
<reg name="ftag" bitsize="32" type="int" group="float"/>
<reg name="fiseg" bitsize="32" type="int" group="float"/>
<reg name="fioff" bitsize="32" type="int" group="float"/>
<reg name="foseg" bitsize="32" type="int" group="float"/>
<reg name="fooff" bitsize="32" type="int" group="float"/>
<reg name="fop" bitsize="32" type="int" group="float"/>
</feature>
qiling/debugger/gdb/xml/x86/32bit-mpx.xml
+33 -31
View File
@@ -7,39 +7,41 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.i386.mpx">
<struct id="br128">
<field name="lbound" type="uint64"/>
<field name="ubound_raw" type="uint64"/>
</struct>
<struct id="br128">
<field name="lbound" type="uint64"/>
<field name="ubound_raw" type="uint64"/>
</struct>
<struct id="_bndstatus" size="8">
<field name="bde" start="2" end="31"/>
<field name="error" start="0" end="1"/>
</struct>
<struct id="_bndstatus" size="8">
<field name="bde" start="2" end="31"/>
<field name="error" start="0" end="1"/>
</struct>
<union id="status">
<field name="raw" type="data_ptr"/>
<field name="status" type="_bndstatus"/>
</union>
<union id="status">
<field name="raw" type="data_ptr"/>
<field name="status" type="_bndstatus"/>
</union>
<struct id="_bndcfgu" size="8">
<field name="base" start="12" end="31" />
<field name="reserved" start="2" end="11"/>
<!-- Explicitly set the type here, otherwise it defaults to bool.
Perhaps this should be uint32, but the container type has size 8. -->
<field name="preserved" start="1" end="1" type="uint64"/>
<field name="enabled" start="0" end="0" type="uint64"/>
</struct>
<struct id="_bndcfgu" size="8">
<field name="base" start="12" end="31" />
<field name="reserved" start="2" end="11"/>
<!--
Explicitly set the type here, otherwise it defaults to bool.
Perhaps this should be uint32, but the container type has size 8.
-->
<field name="preserved" start="1" end="1" type="uint64"/>
<field name="enabled" start="0" end="0" type="uint64"/>
</struct>
<union id="cfgu">
<field name="raw" type="data_ptr"/>
<field name="config" type="_bndcfgu"/>
</union>
<union id="cfgu">
<field name="raw" type="data_ptr"/>
<field name="config" type="_bndcfgu"/>
</union>
<reg name="bnd0raw" bitsize="128" type="br128"/>
<reg name="bnd1raw" bitsize="128" type="br128"/>
<reg name="bnd2raw" bitsize="128" type="br128"/>
<reg name="bnd3raw" bitsize="128" type="br128"/>
<reg name="bndcfgu" bitsize="64" type="cfgu"/>
<reg name="bndstatus" bitsize="64" type="status"/>
</feature>
<reg name="bnd0raw" bitsize="128" type="br128"/>
<reg name="bnd1raw" bitsize="128" type="br128"/>
<reg name="bnd2raw" bitsize="128" type="br128"/>
<reg name="bnd3raw" bitsize="128" type="br128"/>
<reg name="bndcfgu" bitsize="64" type="cfgu"/>
<reg name="bndstatus" bitsize="64" type="status"/>
</feature>
qiling/debugger/gdb/xml/x86/32bit-pkeys.xml
+2 -4
View File
@@ -7,7 +7,5 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.i386.pkeys">
<reg name="pkru" bitsize="32" type="uint32"/>
</feature>
<reg name="pkru" bitsize="32" type="uint32"/>
</feature>
qiling/debugger/gdb/xml/x86/32bit-sse.xml
+43 -41
View File
@@ -7,46 +7,48 @@
<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.i386.sse">
<vector id="v4f" type="ieee_single" count="4"/>
<vector id="v2d" type="ieee_double" count="2"/>
<vector id="v16i8" type="int8" count="16"/>
<vector id="v8i16" type="int16" count="8"/>
<vector id="v4i32" type="int32" count="4"/>
<vector id="v2i64" type="int64" count="2"/>
<union id="vec128">
<field name="v4_float" type="v4f"/>
<field name="v2_double" type="v2d"/>
<field name="v16_int8" type="v16i8"/>
<field name="v8_int16" type="v8i16"/>
<field name="v4_int32" type="v4i32"/>
<field name="v2_int64" type="v2i64"/>
<field name="uint128" type="uint128"/>
</union>
<flags id="i386_mxcsr" size="4">
<field name="IE" start="0" end="0"/>
<field name="DE" start="1" end="1"/>
<field name="ZE" start="2" end="2"/>
<field name="OE" start="3" end="3"/>
<field name="UE" start="4" end="4"/>
<field name="PE" start="5" end="5"/>
<field name="DAZ" start="6" end="6"/>
<field name="IM" start="7" end="7"/>
<field name="DM" start="8" end="8"/>
<field name="ZM" start="9" end="9"/>
<field name="OM" start="10" end="10"/>
<field name="UM" start="11" end="11"/>
<field name="PM" start="12" end="12"/>
<field name="FZ" start="15" end="15"/>
</flags>
<vector id="v4f" type="ieee_single" count="4"/>
<vector id="v2d" type="ieee_double" count="2"/>
<vector id="v16i8" type="int8" count="16"/>
<vector id="v8i16" type="int16" count="8"/>
<vector id="v4i32" type="int32" count="4"/>
<vector id="v2i64" type="int64" count="2"/>
<reg name="xmm0" bitsize="128" type="vec128" regnum="32"/>
<reg name="xmm1" bitsize="128" type="vec128"/>
<reg name="xmm2" bitsize="128" type="vec128"/>
<reg name="xmm3" bitsize="128" type="vec128"/>
<reg name="xmm4" bitsize="128" type="vec128"/>
<reg name="xmm5" bitsize="128" type="vec128"/>
<reg name="xmm6" bitsize="128" type="vec128"/>
<reg name="xmm7" bitsize="128" type="vec128"/>
<union id="vec128">
<field name="v4_float" type="v4f"/>
<field name="v2_double" type="v2d"/>
<field name="v16_int8" type="v16i8"/>
<field name="v8_int16" type="v8i16"/>
<field name="v4_int32" type="v4i32"/>
<field name="v2_int64" type="v2i64"/>
<field name="uint128" type="uint128"/>
</union>
<reg name="mxcsr" bitsize="32" type="i386_mxcsr" group="vector"/>
</feature>
<flags id="i386_mxcsr" size="4">
<field name="IE" start="0" end="0"/>
<field name="DE" start="1" end="1"/>
<field name="ZE" start="2" end="2"/>
<field name="OE" start="3" end="3"/>
<field name="UE" start="4" end="4"/>
<field name="PE" start="5" end="5"/>
<field name="DAZ" start="6" end="6"/>
<field name="IM" start="7" end="7"/>
<field name="DM" start="8" end="8"/>
<field name="ZM" start="9" end="9"/>
<field name="OM" start="10" end="10"/>
<field name="UM" start="11" end="11"/>
<field name="PM" start="12" end="12"/>
<field name="FZ" start="15" end="15"/>
</flags>
<reg name="xmm0" bitsize="128" type="vec128" regnum="32"/>
<reg name="xmm1" bitsize="128" type="vec128"/>
<reg name="xmm2" bitsize="128" type="vec128"/>
<reg name="xmm3" bitsize="128" type="vec128"/>
<reg name="xmm4" bitsize="128" type="vec128"/>
<reg name="xmm5" bitsize="128" type="vec128"/>
<reg name="xmm6" bitsize="128" type="vec128"/>
<reg name="xmm7" bitsize="128" type="vec128"/>
<reg name="mxcsr" bitsize="32" type="i386_mxcsr" group="vector"/>
</feature>
qiling/debugger/gdb/xml/x86/target.xml
+9 -9
View File
@@ -1,11 +1,11 @@
<?xml version="1.0"?>
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target><architecture>i386</architecture>
<osabi>GNU/Linux</osabi>
<xi:include href="32bit-core.xml"/>
<xi:include href="32bit-sse.xml"/>
<xi:include href="32bit-linux.xml"/>
<xi:include href="32bit-segments.xml"/>
<xi:include href="32bit-avx.xml"/>
<xi:include href="32bit-mpx.xml"/>
</target>
<target xmlns:xi="http://www.w3.org/2001/XInclude">
<architecture>i386</architecture>
<osabi>GNU/Linux</osabi>
<xi:include href="32bit-core.xml"/>
<xi:include href="32bit-sse.xml"/>
<xi:include href="32bit-linux.xml"/>
<xi:include href="32bit-avx.xml"/>
</target>
qiling/debugger/gdb/xml/x8664/target.xml
+13 -1
View File
@@ -1 +1,13 @@
<?xml version="1.0"?><!DOCTYPE target SYSTEM "gdb-target.dtd"><target><architecture>i386:x86-64</architecture><osabi>GNU/Linux</osabi><xi:include href="64bit-core.xml"/><xi:include href="64bit-sse.xml"/><xi:include href="64bit-linux.xml"/><xi:include href="64bit-segments.xml"/><xi:include href="64bit-avx.xml"/><xi:include href="64bit-mpx.xml"/></target>
<?xml version="1.0"?>
<!DOCTYPE target SYSTEM "gdb-target.dtd">
<target xmlns:xi="http://www.w3.org/2001/XInclude">
<architecture>i386:x86-64</architecture>
<osabi>GNU/Linux</osabi>
<xi:include href="64bit-core.xml"/>
<xi:include href="64bit-sse.xml"/>
<xi:include href="64bit-linux.xml"/>
<xi:include href="64bit-segments.xml"/>
<xi:include href="64bit-avx.xml"/>
<xi:include href="64bit-mpx.xml"/>
</target>
qiling/debugger/gdb/xmlregs.py
+112
View File
@@ -0,0 +1,112 @@
#!/usr/bin/env python3
#
# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
#
from typing import Iterator, Mapping, Optional, Sequence, Tuple
from pathlib import PurePath
from qiling.arch.arm_const import reg_map as arm_regs
from qiling.arch.arm_const import reg_vfp as arm_regs_vfp
from qiling.arch.arm64_const import reg_map as arm64_regs
from qiling.arch.arm64_const import reg_map_v as arm64_regs_v
from qiling.arch.mips_const import reg_map as mips_regs_gpr
from qiling.arch.mips_const import reg_map_fpu as mips_regs_fpu
from qiling.arch.x86_const import reg_map_16 as x86_regs_16
from qiling.arch.x86_const import reg_map_32 as x86_regs_32
from qiling.arch.x86_const import reg_map_64 as x86_regs_64
from qiling.arch.x86_const import reg_map_misc as x86_regs_misc
from qiling.arch.x86_const import reg_map_cr as x86_regs_cr
from qiling.arch.x86_const import reg_map_st as x86_regs_st
from qiling.arch.x86_const import reg_map_xmm as x86_regs_xmm
from qiling.arch.x86_const import reg_map_ymm as x86_regs_ymm
from qiling.const import QL_ARCH
RegEntry = Tuple[Optional[int], int, int]
# define a local dummy function to let us reference this module
__anchor__ = lambda x: x
def __get_xml_path(archtype: QL_ARCH) -> Tuple[str, PurePath]:
import inspect
p = PurePath(inspect.getfile(__anchor__))
basedir = p.parent / 'xml' / archtype.name.lower()
filename = basedir / 'target.xml'
return str(filename), basedir
def __walk_xml_regs(filename: str, base_url: PurePath) -> Iterator[Tuple[int, str, int]]:
from xml.etree import ElementTree, ElementInclude
tree = ElementTree.parse(filename)
root = tree.getroot()
# NOTE: this is needed to load xinclude hrefs relative to the main xml file. starting
# from python 3.9 ElementInclude.include has an argument for that called 'base_url'.
# this is a workaround for earlier python versions such as 3.8
def my_loader(base: PurePath):
def __wrapped(href: str, parse, encoding=None):
abshref = base / href
return ElementInclude.default_loader(str(abshref), parse, encoding)
return __wrapped
ElementInclude.include(root, loader=my_loader(base_url))
regnum = -1
for reg in root.iter('reg'):
# if regnum is not specified, assume it follows the previous one
regnum = int(reg.get('regnum', regnum + 1))
name = reg.attrib['name']
bitsize = reg.attrib['bitsize']
yield regnum, name, int(bitsize)
def load_regsmap(archtype: QL_ARCH) -> Sequence[RegEntry]:
"""Initialize registers map using available target XML files.
Args:
archtype: target architecture type
Returns: a list representing registers data
"""
# retreive the relevant set of registers; their order of appearance is not
# important as it is determined by the info read from the xml files
ucregs: Mapping[str, int] = {
QL_ARCH.A8086 : dict(**x86_regs_32, **x86_regs_misc, **x86_regs_cr, **x86_regs_st),
QL_ARCH.X86 : dict(**x86_regs_32, **x86_regs_misc, **x86_regs_cr, **x86_regs_st, **x86_regs_xmm),
QL_ARCH.X8664 : dict(**x86_regs_64, **x86_regs_misc, **x86_regs_cr, **x86_regs_st, **x86_regs_xmm, **x86_regs_ymm),
QL_ARCH.ARM : dict(**arm_regs, **arm_regs_vfp),
QL_ARCH.CORTEX_M : arm_regs,
QL_ARCH.ARM64 : dict(**arm64_regs, **arm64_regs_v),
QL_ARCH.MIPS : dict(**mips_regs_gpr, **mips_regs_fpu)
}[archtype]
xmlpath = __get_xml_path(archtype)
regsinfo = sorted(__walk_xml_regs(*xmlpath))
# pre-allocate regmap and occupy it with null entries
last_regnum = regsinfo[-1][0]
regmap: Sequence[RegEntry] = [(None, 0, 0)] * (last_regnum + 1)
pos = 0
for regnum, name, bitsize in sorted(regsinfo):
# reg value size in nibbles
nibbles = bitsize // 4
regmap[regnum] = (ucregs.get(name), pos, nibbles)
# value position of next reg
pos += nibbles
return regmap
__all__ = ['RegEntry', 'load_regsmap']
qiling/debugger/qdb/arch/arch_x86.py
+2 -2
View File
@@ -21,7 +21,7 @@ class ArchX86(Arch):
"eax", "ebx", "ecx", "edx",
"esp", "ebp", "esi", "edi",
"eip", "ss", "cs", "ds", "es",
"fs", "gs", "ef",
"fs", "gs", "eflags",
)
def read_insn(self, address: int) -> bytes:
@@ -34,7 +34,7 @@ class ArchX86(Arch):
@staticmethod
def get_flags(bits: int) -> Mapping[str, bool]:
"""
get flags from ql.reg.ef
get flags from ql.reg.eflags
"""
return {
qiling/debugger/qdb/branch_predictor/branch_predictor_x86.py
+1 -1
View File
@@ -91,7 +91,7 @@ class BranchPredictorX86(BranchPredictor, ArchX86):
}
if line.mnemonic in jump_table:
eflags = self.get_flags(self.ql.arch.regs.ef).values()
eflags = self.get_flags(self.ql.arch.regs.eflags).values()
prophecy.going = jump_table.get(line.mnemonic)(*eflags)
elif line.mnemonic in jump_reg_table:
qiling/debugger/qdb/frontend.py
+2 -2
View File
@@ -389,7 +389,7 @@ class CtxManager_X86(CtxManager):
"eax", "ebx", "ecx", "edx",
"esp", "ebp", "esi", "edi",
"eip", "ss", "cs", "ds", "es",
"fs", "gs", "ef",
"fs", "gs", "eflags",
)
@context_printer("[ REGISTERS ]")
def context_reg(self, saved_reg_dump):
@@ -416,7 +416,7 @@ class CtxManager_X86(CtxManager):
lines += line
print(lines.format(*cur_regs.values()))
print(color.GREEN, "EFLAGS: [CF: {flags[CF]}, PF: {flags[PF]}, AF: {flags[AF]}, ZF: {flags[ZF]}, SF: {flags[SF]}, OF: {flags[OF]}]".format(flags=get_x86_eflags(self.ql.arch.regs.ef)), color.END, sep="")
print(color.GREEN, "EFLAGS: [CF: {flags[CF]}, PF: {flags[PF]}, AF: {flags[AF]}, ZF: {flags[ZF]}, SF: {flags[SF]}, OF: {flags[OF]}]".format(flags=get_x86_eflags(self.ql.arch.regs.eflags)), color.END, sep="")
@context_printer("[ DISASM ]", footer=True)
def context_asm(self):
qiling/debugger/qdb/render/render_x86.py
+1 -1
View File
@@ -22,7 +22,7 @@ class ContextRenderX86(ContextRender, ArchX86):
cur_regs = self.dump_regs()
diff_reg = self.reg_diff(cur_regs, saved_reg_dump)
self.render_regs_dump(cur_regs, diff_reg=diff_reg)
print(color.GREEN, "EFLAGS: [CF: {flags[CF]}, PF: {flags[PF]}, AF: {flags[AF]}, ZF: {flags[ZF]}, SF: {flags[SF]}, OF: {flags[OF]}]".format(flags=self.get_flags(self.ql.arch.regs.ef)), color.END, sep="")
print(color.GREEN, "EFLAGS: [CF: {flags[CF]}, PF: {flags[PF]}, AF: {flags[AF]}, ZF: {flags[ZF]}, SF: {flags[SF]}, OF: {flags[OF]}]".format(flags=self.get_flags(self.ql.arch.regs.eflags)), color.END, sep="")
@Render.divider_printer("[ DISASM ]")
def context_asm(self):
qiling/extensions/report/report.py
+2 -2
View File
@@ -12,8 +12,8 @@ class Report:
def __init__(self, ql):
self.filename = ql.argv
self.rootfs = ql.rootfs
self.arch = list(arch_map.keys())[list(arch_map.values()).index(ql.arch.type)]
self.os = list(os_map.keys())[list(os_map.values()).index(ql.os.type)]
self.arch = ql.arch.type.name
self.os = ql.os.type.name
self.env = ql.env
self.strings = set()
for string in ql.os.stats.strings:
qiling/loader/elf.py
+28 -25
View File
@@ -29,7 +29,7 @@ from qiling.os.linux.kernel_api.kernel_api import hook_sys_open, hook_sys_read,
# auxiliary vector types
# see: https://man7.org/linux/man-pages/man3/getauxval.3.html
class AUX(IntEnum):
class AUXV(IntEnum):
AT_NULL = 0
AT_IGNORE = 1
AT_EXECFD = 2
@@ -317,36 +317,39 @@ class QlLoaderELF(QlLoader):
elf_hwcap = 0xd7b81f
# setup aux vector
aux_entries = (
(AUX.AT_PHDR, elf_phdr),
(AUX.AT_PHENT, elf_phent),
(AUX.AT_PHNUM, elf_phnum),
(AUX.AT_PAGESZ, self.ql.mem.pagesize),
(AUX.AT_BASE, interp_address),
(AUX.AT_FLAGS, 0),
(AUX.AT_ENTRY, self.elf_entry),
(AUX.AT_UID, self.ql.os.uid),
(AUX.AT_EUID, self.ql.os.euid),
(AUX.AT_GID, self.ql.os.gid),
(AUX.AT_EGID, self.ql.os.egid),
(AUX.AT_HWCAP, elf_hwcap),
(AUX.AT_CLKTCK, 100),
(AUX.AT_RANDOM, randstraddr),
(AUX.AT_HWCAP2, 0),
(AUX.AT_EXECFN, execfn),
(AUX.AT_PLATFORM, cpustraddr),
(AUX.AT_SECURE, 0),
(AUX.AT_NULL, 0)
auxv_entries = (
(AUXV.AT_HWCAP, elf_hwcap),
(AUXV.AT_PAGESZ, self.ql.mem.pagesize),
(AUXV.AT_CLKTCK, 100),
(AUXV.AT_PHDR, elf_phdr),
(AUXV.AT_PHENT, elf_phent),
(AUXV.AT_PHNUM, elf_phnum),
(AUXV.AT_BASE, interp_address),
(AUXV.AT_FLAGS, 0),
(AUXV.AT_ENTRY, self.elf_entry),
(AUXV.AT_UID, self.ql.os.uid),
(AUXV.AT_EUID, self.ql.os.euid),
(AUXV.AT_GID, self.ql.os.gid),
(AUXV.AT_EGID, self.ql.os.egid),
(AUXV.AT_SECURE, 0),
(AUXV.AT_RANDOM, randstraddr),
(AUXV.AT_HWCAP2, 0),
(AUXV.AT_EXECFN, execfn),
(AUXV.AT_PLATFORM, cpustraddr),
(AUXV.AT_NULL, 0)
)
# add all aux entries
for key, val in aux_entries:
elf_table.extend(self.ql.pack(key) + self.ql.pack(val))
bytes_before_auxv = len(elf_table)
# add all auxv entries
for key, val in auxv_entries:
elf_table.extend(self.ql.pack(key))
elf_table.extend(self.ql.pack(val))
new_stack = self.ql.mem.align(new_stack - len(elf_table), 0x10)
self.ql.mem.write(new_stack, bytes(elf_table))
self.aux_vec = dict(aux_entries)
self.auxv = new_stack + bytes_before_auxv
self.stack_address = new_stack
self.load_address = load_address
qiling/os/dos/dos.py
+2 -2
View File
@@ -58,10 +58,10 @@ class QlOsDos(QlOs):
curses.endwin()
def set_flag_value(self, fl: Flags, val: int) -> None:
self.ql.arch.regs.ef = self.ql.arch.regs.ef & (~fl) | (fl * val)
self.ql.arch.regs.eflags = self.ql.arch.regs.eflags & (~fl) | (fl * val)
def test_flags(self, fl):
return self.ql.arch.regs.ef & fl == fl
return self.ql.arch.regs.eflags & fl == fl
def set_cf(self):
self.set_flag_value(Flags.CF, 0b1)
qiling/os/macos/utils.py
+2 -2
View File
@@ -188,5 +188,5 @@ def page_align_end(addr, page_size):
def set_eflags_cf(ql, target_cf):
ql.arch.regs.ef = ( ql.arch.regs.ef & 0xfffffffe ) | target_cf
return ql.arch.regs.ef
ql.arch.regs.eflags = ( ql.arch.regs.eflags & 0xfffffffe ) | target_cf
return ql.arch.regs.eflags
qiling/os/memory.py
+1 -2
View File
@@ -4,12 +4,11 @@
#
import os, re
from typing import Any, Callable, List, MutableSequence, Optional, Sequence, Tuple
from typing import Any, Callable, List, Mapping, MutableSequence, Optional, Sequence, Tuple
from unicorn import UC_PROT_NONE, UC_PROT_READ, UC_PROT_WRITE, UC_PROT_EXEC, UC_PROT_ALL
from qiling import Qiling
from qiling.const import *
from qiling.exception import *
# tuple: range start, range end, permissions mask, range label, is mmio?
qiling/os/posix/const_mapping.py
+4 -3
View File
@@ -3,11 +3,12 @@
# Cross Platform and Multi Architecture Advanced Binary Emulation Framework
#
from typing import MutableSequence
from .const import *
from typing import Mapping, MutableSequence
from qiling import Qiling
from qiling.const import *
from qiling.const import QL_ARCH, QL_OS
from .const import *
def _invert_dict(d: Mapping) -> Mapping:
return { v:k for k, v in d.items()}