Save and restore ARM coprocessor register as part of Qiling save and restore

qiling/arch/cpr.py

@@ -80,5 +80,18 @@ class QlCprManager:
 
         self.uc.cpr_write(coproc, opc1, crn, crm, opc2, el, is_64, value)
 
+    def save(self) -> Dict[str, int]:
+        """Save registers.
+        """
+
+        return dict((name, self.read(*reg)) for name, reg in self.register_mapping.items())
+
+    def restore(self, context: Mapping[str, int]) -> None:
+        """Restore registers.
+        """
+
+        for name, val in context.items():
+            self.write(*self.register_mapping[name], val)
+
 
 __all__ = ['QlCprManager']

qiling/arch/cpr64.py

@@ -76,5 +76,18 @@ class QlCpr64Manager:
 
         self.uc.cpr_write(op0, op1, crn, crm, op2, value)
 
+    def save(self) -> Dict[str, int]:
+        """Save registers.
+        """
+
+        return dict((name, self.read(*reg)) for name, reg in self.register_mapping.items())
+
+    def restore(self, context: Mapping[str, int]) -> None:
+        """Restore registers.
+        """
+
+        for name, val in context.items():
+            self.write(*self.register_mapping[name], val)
+
 
 __all__ = ['QlCpr64Manager']

qiling/core.py

@@ -628,6 +628,9 @@ class Qiling(QlCoreHooks, QlCoreStructs):
         if reg:
             saved_states["reg"] = self.arch.regs.save()
 
+            if self.arch.type in (QL_ARCH.ARM, QL_ARCH.ARM64):
+                saved_states["cpr"] = self.arch.cpr.save()
+
         if mem:
             saved_states["mem"] = self.mem.save()
 
@@ -679,6 +682,9 @@ class Qiling(QlCoreHooks, QlCoreStructs):
         if "reg" in saved_states:
             self.arch.regs.restore(saved_states["reg"])
 
+            if self.arch.type in (QL_ARCH.ARM, QL_ARCH.ARM64):
+                self.arch.cpr.restore(saved_states["cpr"])
+
         if "hw" in saved_states:
             self.hw.restore(saved_states['hw'])