Remove create_reverse_mapping

This commit is contained in:
elicn
2021-09-17 00:58:32 +03:00
parent 513d595c33
commit e53290d091
5 changed files with 1 additions and 12 deletions
-1
View File
@@ -24,7 +24,6 @@ class QlArchARM(QlArch):
for reg_maper in reg_maps:
self.ql.reg.expand_mapping(reg_maper)
self.ql.reg.create_reverse_mapping()
self.ql.reg.register_sp(reg_map["sp"])
self.ql.reg.register_pc(reg_map["pc"])
-1
View File
@@ -23,7 +23,6 @@ class QlArchARM64(QlArch):
for reg_maper in reg_maps:
self.ql.reg.expand_mapping(reg_maper)
self.ql.reg.create_reverse_mapping()
self.ql.reg.register_sp(reg_map["sp"])
self.ql.reg.register_pc(reg_map["pc"])
-1
View File
@@ -24,7 +24,6 @@ class QlArchMIPS(QlArch):
for reg_maper in reg_maps:
self.ql.reg.expand_mapping(reg_maper)
self.ql.reg.create_reverse_mapping()
self.ql.reg.register_sp(reg_map["sp"])
self.ql.reg.register_pc(reg_map["pc"])
+1 -6
View File
@@ -17,7 +17,6 @@ class QlRegisterManager:
def __init__(self, ql: Qiling):
self.register_mapping: MutableMapping[str, int] = {}
self.reverse_mapping: Mapping[int, str] = {}
self.ql = ql
self.uc_pc = 0
self.uc_sp = 0
@@ -137,7 +136,7 @@ class QlRegisterManager:
@property
def arch_pc_name(self) -> str:
return self.reverse_mapping[self.uc_pc]
return next(k for k, v in self.register_mapping.items() if v == self.uc_pc)
@property
def arch_sp(self) -> int:
@@ -147,7 +146,3 @@ class QlRegisterManager:
@arch_sp.setter
def arch_sp(self, value: int) -> None:
return self.ql.uc.reg_write(self.uc_sp, value)
def create_reverse_mapping(self):
self.reverse_mapping = {v:k for k, v in self.register_mapping.items()}
-3
View File
@@ -48,7 +48,6 @@ class QlArchA8086(QlArchIntel):
for reg_maper in reg_maps:
self.ql.reg.expand_mapping(reg_maper)
self.ql.reg.create_reverse_mapping()
self.ql.reg.register_pc(reg_map_16["sp"])
self.ql.reg.register_sp(reg_map_16["ip"])
@@ -83,7 +82,6 @@ class QlArchX86(QlArchIntel):
for reg_maper in reg_maps:
self.ql.reg.expand_mapping(reg_maper)
self.ql.reg.create_reverse_mapping()
self.ql.reg.register_sp(reg_map_32["esp"])
self.ql.reg.register_pc(reg_map_32["eip"])
@@ -123,7 +121,6 @@ class QlArchX8664(QlArchIntel):
for reg_maper in reg_maps:
self.ql.reg.expand_mapping(reg_maper)
self.ql.reg.create_reverse_mapping()
self.ql.reg.register_sp(reg_map_64["rsp"])
self.ql.reg.register_pc(reg_map_64["rip"])