Fix compiler warnings and silence ghidra-native ones in meson builds

.github/workflows/ci.yml

@@ -168,7 +168,7 @@ jobs:
     - name: Installing System's Meson Ninja
       run: sudo pip install ninja meson && sudo ninja --version && sudo meson --version
     - name: Building r2ghidra with meson
-      run: ./preconfigure && meson b && ninja -C b && sudo ninja -C b install
+      run: ./preconfigure && meson setup b && ninja -C b && sudo ninja -C b install
     - name: Cannot test meson builds, because those cant be installed yet
       run: echo nada
 #    - name: Testing r2ghidra oneliner

meson.build

@@ -87,9 +87,9 @@ add_global_arguments('-DNDEBUG', language: ['c', 'cpp'])
 
 r2ghidra_incdirs = include_directories(incdirs)
 
-ghidra = subproject('ghidra-native', version: '>=0.7.2', default_options: ['default_library=static', 'werror=false'])
+ghidra = subproject('ghidra-native', version: '>=0.7.2', default_options: ['default_library=static', 'werror=false', 'warning_level=0'])
 
-r2ghidra_deps = [r_core, ghidra.get_variable('ghidra_dep')]
+r2ghidra_deps = [r_core, ghidra.get_variable('ghidra_dep').as_system()]
 r2ghidra_cpp_args = []
 
 r2ghidra_core_sources = [
@@ -112,7 +112,7 @@ r2ghidra_core_plugin = shared_library('core_r2ghidra',
 
 pcode_xml_test = executable('pcode-xml-test',
   'test/pcode_xml.cpp',
-  dependencies: ghidra.get_variable('ghidra_dep'),
+  dependencies: ghidra.get_variable('ghidra_dep').as_system(),
   include_directories: r2ghidra_incdirs,
   install: false
 )

src/R2LoadImage.cpp

@@ -39,7 +39,6 @@ static bool isptr(const ut8 *p, size_t remain) {
 }
 
 static void addRangesWithPointers(RCoreLock &core, RangeList &list, AddrSpace *space) {
-	RIOMapRef *mapref;
 	RIO *io = core->io;
 	RIOBank *bank = r_io_bank_get (io, io->bank);
 	r_list_foreach_cpp<RIOMapRef>(bank->maprefs, [&](RIOMapRef *mapref) {
@@ -133,8 +132,6 @@ void R2LoadImage::getReadonly(RangeList &list) const {
 			break;
 		case 3:
 			{
-				RIOMapRef *mapref;
-				RListIter *iter;
 				RIO *io = core->io;
 				RIOBank *bank = r_io_bank_get (io, io->bank);
 				r_list_foreach_cpp<RIOMapRef>(bank->maprefs, [&](RIOMapRef *mapref) {

src/R2Scope.cpp

@@ -398,7 +398,7 @@ struct FunctionVars {
 				typelock ? "true" : "false", var->isarg ? "0" : "-1", index,
 				var->isarg && var->kind == R_ANAL_VAR_KIND_REG, childRegRange);
 			if (var->isarg) {
-				if (argsByIndex.size () < index + 1) {
+				if (argsByIndex.size () < (size_t)index + 1) {
 					argsByIndex.resize (index + 1, nullptr);
 				}
 				argsByIndex[index] = symbolElement;
@@ -763,17 +763,13 @@ FunctionSymbol *R2Scope::registerFunction(RAnalFunction *fcn) const {
 	});
 
 	Address returnAddr(arch->getSpaceByName("register"), 0);
-	bool returnFound = false;
 	if (proto) {
 		for (auto it = proto->effectBegin (); it != proto->effectEnd(); it++) {
 			if (it->getType() == EffectRecord::return_address) {
 				returnAddr = it->getAddress();
-				returnFound = true;
 				break;
 			}
 		}
-		//if (!returnFound)
-		//	arch->addWarning("Failed to find return address in ProtoModel");
 	}
 	// TODO: should we try to get the return address from r2's cc?
 

src/SleighAsm.cpp

@@ -642,10 +642,10 @@ void SleighAsm::check(ut64 offset, const ut8 *buf, int len) { // To refresh cach
 	if (ctx->getParserState () > ParserContext::uninitialized) {
 		ut8 *cached = ctx->getBuffer ();
 		size_t i = 0;
-		for (; i < len && cached[i] == buf[i]; i++) {
+		for (; i < (size_t)len && cached[i] == buf[i]; i++) {
 			// just loop in here
 		}
-		if (i != len) {
+		if (i != (size_t)len) {
 			ctx->setParserState (ParserContext::uninitialized);
 		}
 	}

src/SleighAsm.h

@@ -51,9 +51,9 @@ public:
 };
 
 struct PcodeOperand {
-	PcodeOperand(uintb offset, uint4 size): type(RAM), offset(offset), size(size) {}
-	PcodeOperand(uintb number): type(CONSTANT), number(number), size(0) {}
-	PcodeOperand(const std::string &name, uint4 size): type(REGISTER), name(name), size(size) {}
+	PcodeOperand(uintb offset, uint4 size): offset(offset), size(size), type(RAM) {}
+	PcodeOperand(uintb number): number(number), size(0), type(CONSTANT) {}
+	PcodeOperand(const std::string &name, uint4 size): name(name), size(size), type(REGISTER) {}
 	virtual ~PcodeOperand() {
 		if (type == REGISTER) {
 			name.~string();
@@ -136,7 +136,7 @@ struct Pcodeop {
 	/* input2 for STORE will use output to save memory space */
 
 	Pcodeop(PcodeOpType opc, PcodeOperand *in0, PcodeOperand *in1, PcodeOperand *out):
-	    type(opc), input0(in0), input1(in1), output(out) {
+	    type(opc), output(out), input0(in0), input1(in1) {
 	}
 
 	void fini() {

src/SleighInstruction.cpp

@@ -214,7 +214,7 @@ FlowType SleighInstructionPrototype::convertFlowFlags(FlowFlags flags) {
 	flags = FlowFlags(flags & (~(FLOW_CROSSBUILD | FLOW_LABEL)));
 	// NOTE: If prototype has cross-build, flow must be determined dynamically
 	// Convert flags to a standard flowtype
-	switch (flags) {
+	switch ((int)flags) {
 	case 0:
 	case FLOW_BRANCH_TO_END: return FlowType::FALL_THROUGH;
 	case FLOW_CALL: return FlowType::UNCONDITIONAL_CALL;
@@ -414,7 +414,7 @@ SleighInstructionPrototype::FlowFlags SleighInstructionPrototype::gatherFlags(Fl
 	std::vector<FlowRecord *> curlist;
 	if (secnum < 0) {
 		curlist = flowStateList;
-	} else if ((!flowStateListNamed.empty()) && (secnum < flowStateListNamed.size())) {
+	} else if ((!flowStateListNamed.empty()) && ((size_t)secnum < flowStateListNamed.size())) {
 		curlist = flowStateListNamed[secnum];
 	}
 	if (curlist.empty()) {
@@ -451,7 +451,7 @@ void SleighInstructionPrototype::gatherFlows(std::vector<Address> &res, SleighIn
 	std::vector<FlowRecord *> curlist;
 	if (secnum < 0) {
 		curlist = flowStateList;
-	} else if ((!flowStateListNamed.empty()) && (secnum < flowStateListNamed.size())) {
+	} else if ((!flowStateListNamed.empty()) && ((size_t)secnum < flowStateListNamed.size())) {
 		curlist = flowStateListNamed[secnum];
 	}
 	if (curlist.empty()) {

src/SleighInstruction.h

@@ -95,7 +95,7 @@ enum FlowType {
 	CALLOTHER_OVERRIDE_JUMP,
 };
 
-static bool flowTypeHasFallthrough(FlowType t) {
+static inline bool flowTypeHasFallthrough(FlowType t) {
 	switch (t) {
 	case FlowType::INVALID:
 	case FlowType::FLOW:
@@ -286,7 +286,7 @@ private:
 	void generatePointer(const VarnodeTpl *vntpl, VarnodeData &vn, ParserWalker &walker);
 
 public:
-	R2Sleigh(LoadImage *ld, ContextDatabase *c_db): R2loader(ld), Sleigh(ld, c_db) {}
+	R2Sleigh(LoadImage *ld, ContextDatabase *c_db): Sleigh(ld, c_db), R2loader(ld) {}
 	~R2Sleigh() { clearCache(); }
 	
 	void reconstructContext(ParserContext &protoContext);

src/anal_ghidra.cpp

@@ -568,7 +568,6 @@ static ut32 anal_type_NOT(RAnal *anal, RAnalOp *anal_op, const std::vector<Pcode
 	SleighAnalValue in0, out;
 	in0.invalid(); out.invalid();
 	std::vector<SleighAnalValue> outs;
-	uintb unique_off = 0;
 
 	for (auto iter = raw_ops.cbegin(); iter != raw_ops.cend(); iter++) {
 		if (iter->type == key_pcode) {
@@ -1011,6 +1010,7 @@ static void sleigh_esil(RAnal *a, RAnalOp *anal_op, ut64 addr, const ut8 *data,
 					case CPUI_FLOAT_SUB: ss << "F-"; break;
 					case CPUI_FLOAT_MULT: ss << "F*"; break;
 					case CPUI_FLOAT_DIV: ss << "F/"; break;
+					default: break;
 				}
 
 				if (iter->output->size != 1 && iter->output->size != 8) 
@@ -1052,6 +1052,7 @@ static void sleigh_esil(RAnal *a, RAnalOp *anal_op, ut64 addr, const ut8 *data,
 					case CPUI_INT_LESSEQUAL: ss << "<="; break;
 					case CPUI_INT_NOTEQUAL: ss << "-,!,!"; break;
 					case CPUI_INT_EQUAL: ss << "-,!"; break;
+					default: break;
 				}
 				if (iter->output->is_unique()) {
 					push_stack(iter->output);
@@ -1115,6 +1116,7 @@ static void sleigh_esil(RAnal *a, RAnalOp *anal_op, ut64 addr, const ut8 *data,
 					case CPUI_INT_SRIGHT:
 						ss << "SWAP," << iter->input0->size * 8 << ",~,SWAP,>>>>";
 						break;
+					default: break;
 				}
 				ss << ",1," << iter->output->size * 8 << ",<<,1,-,&";
 
@@ -1291,6 +1293,7 @@ static void sleigh_esil(RAnal *a, RAnalOp *anal_op, ut64 addr, const ut8 *data,
 			case CPUI_FLOAT_ABS: ss << ",0,I2D,F<=,!,?{,-F,}"; break;
 			case CPUI_FLOAT_NEG: ss << ",-F"; break;
 			case CPUI_FLOAT_FLOAT2FLOAT: /* same as below */ break;
+			default: break;
 			}
 			if (iter->output->size != 8) {
 				switch (iter->type) {
@@ -1303,6 +1306,7 @@ static void sleigh_esil(RAnal *a, RAnalOp *anal_op, ut64 addr, const ut8 *data,
 				case CPUI_FLOAT_FLOAT2FLOAT:
 					ss << "," << iter->output->size << ",SWAP,D2F";
 					break;
+				default: break;
 				}
 			}
 			if (iter->output->is_unique()) {
@@ -1311,6 +1315,7 @@ static void sleigh_esil(RAnal *a, RAnalOp *anal_op, ut64 addr, const ut8 *data,
 				ss << "," << *iter->output << ",=";
 			}
 			break;
+		default: break;
 		}
 	}
 
@@ -1609,43 +1614,6 @@ static const char *r_reg_string_arr[] = {
 	"vec256", "vec64", "fpu", "fpu", "drx", "vec256", nullptr
 };
 
-static int get_reg_type(const std::string &name) {
-	auto p = sanal->reg_mapping.cbegin();
-	for (; p != sanal->reg_mapping.cend() && p->second != name; p++) {
-	}
-	if (p == sanal->reg_mapping.cend()) {
-		throw LowlevelError("get_reg_type: reg doesn't exist.");
-	}
-	const std::string &group = sanal->reg_group[p->first];
-
-	if (group. empty()) {
-		return R_REG_TYPE_GPR;
-	}
-	for (size_t i = 0; r_reg_type_arr[i]; i++) {
-		if (group == r_reg_type_arr[i]) {
-			const char *curr = r_reg_string_arr[i];
-			switch (curr[0] | curr[1] << 8) {
-			case 'g' | 'p' << 8: return R_REG_TYPE_GPR;
-			case 'd' | 'r' << 8: return R_REG_TYPE_DRX;
-			case 'f' | 'p' << 8: return R_REG_TYPE_FPU;
-			case 'v' | 'e' << 8:
-				switch (curr[3]) {
-				case '6':
-					return R_REG_TYPE_VEC64;
-				case '1':
-					return R_REG_TYPE_VEC128;
-				case '2':
-					return R_REG_TYPE_VEC256;
-				}
-				break;
-			case 'f' | 'l' << 8: return R_REG_TYPE_FLG;
-			case 's' | 'e' << 8: return R_REG_TYPE_SEG;
-			}
-		}
-	}
-	return -1;
-}
-
 static void append_hardcoded_regs(std::stringstream &buf, const std::string &arch, bool little, int bits) {
 	if (arch.size() < 3) {
 		throw LowlevelError("append_hardcoded_regs: Unexpected arch name.");
@@ -1750,22 +1718,22 @@ static void append_hardcoded_regs(std::stringstream &buf, const std::string &arc
 
 static const char *regtype_name(const char *cpu, const std::string &regname, ut64 bits) {
 	if (!r_str_ncasecmp (cpu, "x86", 3)) {
-		if (regname.find ("cr") != -1) {
+		if (regname.find ("cr") != std::string::npos) {
 			return "drx";
 		}
-		if (regname.find ("ia32") != -1) {
+		if (regname.find ("ia32") != std::string::npos) {
 			return "drx";
 		}
 		if (regname.find ("bnd") == 0) {
 			return "fpu";
 		}
-		if (regname.find ("_offset") != -1) {
+		if (regname.find ("_offset") != std::string::npos) {
 			return "seg";
 		}
-		if (regname.find ("tr_addr") != -1) {
+		if (regname.find ("tr_addr") != std::string::npos) {
 			return "drx";
 		}
-		if (regname.find ("mm") != -1) {
+		if (regname.find ("mm") != std::string::npos) {
 			// r2 has no "mmx" type, and the narrower views must share one arena to alias
 			switch (bits) {
 			case 512: return "vec512";
@@ -1847,18 +1815,6 @@ extern "C" char *r2ghidra_regs(RArchSession *as) {
 	return strdup (res.c_str ());
 }
 
-static constexpr int ESIL_PARM_FLOAT = 127; // Avoid conflict
-
-static bool esil_pushnum_float(REsil *esil, long double num) {
-	char str[64];
-	snprintf (str, sizeof (str) - 1, "%.*LeF", DECIMAL_DIG, num);
-#if R2_ABIVERSION >= 87
-	return r_esil_push (esil, r_strs_from (str));
-#else
-	return r_esil_push (esil, str);
-#endif
-}
-
 static bool sleigh_esil_consts_pick(REsil *esil) {
 	if (!esil || !esil->stack) {
 		return false;