mirror of
https://github.com/radareorg/radare2-extras.git
synced 2026-11-08 09:10:01 -10:00
[WIP] Apollo Guidance Computer disassembly (#54)
* Implemented basic structure for AGC plugin. Implemented integration into build system and layout, as well as some barebones setup code. Now onto the actual logic :3 * Added basic structure of AGC disassembler The core disassembly logic has been ported over from https://github.com/alfonsokim/apollo-guidance-computer/blob/master/yaAGC/agc_disassembler.c . However, since the disassembler is inherently stateful, we still need to implement either state or port over the whole lib / rewrite it. Or I get to find a different solution for this. * Done some research and gathered some information It seems clear how to get the current address etc. from the data passed to the plugin without resorting to internal state. That way a lot of complexity should be avoidable and implementation gets a lot easier. * Cleaned up logic * Integrated things * Finished integration of disasm plugin. * Worked through the AGC instruction set Gathered info needed for the anal plugin and commented the disassembler components. * Fixed compiler error * Added some constants and fixed errors * Added help file
This commit is contained in:
ibabushkin authored and radare committed
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@@ -0,0 +1,82 @@
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VERSION=0.10.4
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HAVE_LIB_YARA=0
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PREFIX=/usr
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DESTDIR?=
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TAR=tar -cvf
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CZ=xz -f
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DIRS=
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ifeq ($(HAVE_LIB_YARA),1)
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DIRS+=yara/yara2
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DIRS+=yara/yara3
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DIRS+=libr/asm/p
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DIRS+=libr/anal/p
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endif
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help:
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@echo "Usage make [target] .. Targets:"
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@echo " all - build everything"
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@echo " baleful - build baleful r2 plugin"
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@echo " asm - build armthumb, ppc, psosvm, x86bea, m68k plugins"
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@echo " anal - build analysis plugins (RAnal)"
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@echo " debug - build debugger plugins (RDebug)"
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@echo " dlang - support DLang demangler (RBin)"
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@echo " yara{2,3} - build yara2 or yara3 r2 plugin"
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||||
@echo " (target)-install - install given plugin"
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@echo " (target)-clean - clean given plugin"
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@echo " install-yara{2,3} - install Yara 2 or 3 from Git"
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baleful:
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$(MAKE) -C baleful
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debug unicorn:
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$(MAKE) -C libr/debug/p
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anal:
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$(MAKE) -C libr/anal/p
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asm:
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$(MAKE) -C libr/asm/p
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asm-install:
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$(MAKE) -C libr/asm/p install DESTDIR=$(DESTDIR)
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asm-clean:
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$(MAKE) -C libr/asm/p clean
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dlang:
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$(MAKE) -C libr/bin/p
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dlang-install:
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$(MAKE) -C libr/bin/p install DESTDIR=$(DESTDIR)
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yara2 yara3:
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cd yara/$@ ; ./configure --prefix=$(PREFIX)
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$(MAKE) -C yara/$@
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yara2-clean:
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$(MAKE) -C yara/yara2 clean
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yara3-clean:
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$(MAKE) -C yara/yara3 clean
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baleful-install:
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$(MAKE) -C baleful install DESTDIR=$(DESTDIR)
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debug-install unicorn-install:
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$(MAKE) -C libr/debug/p install DESTDIR=$(DESTDIR)
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debug-uninstall unicorn-uninstall:
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$(MAKE) -C libr/debug/p uninstall DESTDIR=$(DESTDIR)
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yara2-install:
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$(MAKE) -C yara/yara2 install DESTDIR=$(DESTDIR)
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yara3-install:
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$(MAKE) -C yara/yara3 install DESTDIR=$(DESTDIR)
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all:
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for a in $(DIRS) ; do \
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( cd $$a ; ./configure --prefix=$(PREFIX) ; $(MAKE) ) ; \
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done
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clean mrproper install symstall uninstall deinstall:
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for a in $(DIRS) ; do ( cd $$a ; $(MAKE) $@ ) ; done
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dist:
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DIR=`basename $$PWD` ; \
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FILES=`git ls-files | sed -e s,^,radare2-extras-${VERSION}/,` ; \
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cd .. && mv $${DIR} radare2-extras-${VERSION} && \
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${TAR} radare2-extras-${VERSION}.tar $${FILES} ; \
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${CZ} radare2-extras-${VERSION}.tar ; \
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mv radare2-extras-${VERSION} $${DIR}
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w32dist:
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@echo TODO: w32dist
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.PHONY: dist all
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@@ -1,5 +1,6 @@
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ARCHS=
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ARCHS+=agc.mk
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ARCHS+=x86_bea.mk
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#ARCHS+=x86_im.mk
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ARCHS+=x86_simple.mk
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@@ -0,0 +1,10 @@
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OBJ_AGC=anal_agc.o
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STATIC_OBJ+=${OBJ_AGC}
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TARGET_AGC=anal_agc.${LIBEXT}
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ALL_TARGETS+=${TARGET_AGC}
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${TARGET_AGC}: ${OBJ_AGC}
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${CC} $(call libname,anal_agc) ${LDFLAGS} \
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${CFLAGS} -o anal_agc.${LIBEXT} ${OBJ_AGC}
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@@ -0,0 +1,36 @@
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#include <r_types.h>
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#include <r_lib.h>
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#include <r_util.h>
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#include <r_anal.h>
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static int agc_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len) {
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// TODO: get rid of this, we have that in our disassembler already
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static bool extra_opcode_bit = false;
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if (!data || len != 2) return -1;
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op->size = 2;
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op->type = R_ANAL_OP_TYPE_UNK;
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if (!extra_opcode_bit) {
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} else {
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}
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return op->size;
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}
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RAnalPlugin r_anal_plugin_agc = {
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.name = "agc",
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.desc = "AGC code analysis plugin",
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.license = "LGPL3",
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.arch = "agc",
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.bits = 16,
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.op = &agc_op,
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};
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#ifndef CORELIB
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RLibStruct radare_plugin = {
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.type = R_LIB_TYPE_ANAL,
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.data = &r_anal_plugin_agc,
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.version = R2_VERSION
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};
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#endif
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@@ -0,0 +1,350 @@
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/*
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Copyright 2003-2006 Ronald S. Burkey <[email protected]>,
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2008 Onno Hommes
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2016 Inokentiy Babushkin
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This file is based on the implmentation found in yaAGC, but modified for new
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purposes.
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This file is part of yaAGC / radare2-extras.
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yaAGC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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yaAGC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with yaAGC; if not, write to the Free Software
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||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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Filename: agc_disassembler.h
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Purpose: Source file for AGC Disassembler.
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Contact: Onno Hommes
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Reference: http://www.ibiblio.org/apollo
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Mods: 08/31/08 OH. Began.
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07/12/16 IB. Began refactoring to include in radare2-extras.
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*/
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#include <stdbool.h>
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#include <stdio.h>
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#include "asm_agc.h"
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/*
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* We need to find out what the logic behind the modifications done by
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* ShowAddressContents() is. Since that function performs some lookup
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* on the internal state of the AGC *simulator*, it is very well possible
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* we can simplify things a fair bit. This would also mean that we might be
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* able to reduce the decoding work to interpreting the EXTEND instruction
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* as a prefix, since that's it's only function as far as we know so far.
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*
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* However, if the assembling/disassembling doesn't yield the desired
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* results, we will be in deep trouble already.
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*
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* So far, the best thing to do is to document the functionality of the
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* different static variables employes:
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* * sCurrentZ: the current address to be disassembled.
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* It appears that they are handled differently depending on their value.
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* For instance, the bank gets computed using them (duh).
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* * sBank: the memory bank the address maps to.
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* Memory bank addressing was used because of storage shortage for
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* adresses, which led to this workaround. Banks have different sizes
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* (1K or 256 bytes), thus they get used differently in the code.
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* * sValue: the memory value at the location denoted by the address.
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* * sErasable: whether the data we access is in erasable memory.
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* * sFixed: whether we are reading from ROM.
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*
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* But why are we using two variables to denote mutually exclusive flags?
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*
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* We can get the current address from the RAsm structure pointer passed
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* to disassemble(). Thus, we can compute erasable and fixed.
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*
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* NOP's seem to be encoded in a position-depend way, but that's all we
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* need to handle specially.
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*/
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#define SWITCH_MASK 070000
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#define LOWER_WIDE 07777
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#define LOWER 01777
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#define HIGHER 06000
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void disasm_instruction(unsigned int address, int value, char *buf, int len) {
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static bool extra_opcode_bit = false;
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// distinguish between RW and RO memory
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bool erasable = false;
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if (address < 02000)
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erasable = true;
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// instruction encoding is pretty convoluted, since it doesn't work well with
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// byte boundaries. Thus, every decoding operation below is about to get proper
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// documentation to allow for better understanding (to write the ESIL and ANAL
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// bits still needed).
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// also see http://www.ibiblio.org/apollo/assembly_language_manual.html
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if (!extra_opcode_bit) {
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// simple instructions below - encoded as follows: x iii ooo ooo ooo
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// where x is the odd-parity bit, which is used only by the hardware itself
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// to determine error conditions. However, yaYUL doesn't emulate it, so things
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// are shifted one bit to the left. TODO: maybe we should change this?
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// first, special cases that have their own mnemonics
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if (value == 040000) // i = 100, o = 0
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// complement the A register (address 0)
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snprintf(buf, len, "com");
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else if (value == 020001) // i = 010, o = 0, 1
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// add the A, L register pair to itself (addresses 0 and 1)
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snprintf(buf, len, "ddoubl");
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else if (value == 060000) // i = 110, o = 0
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// add the A register to itself (address 0o)
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snprintf(buf, len, "double");
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else if (value == 052006)
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// change adressing, see manual
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snprintf(buf, len, "dtcb");
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else if (value == 052005)
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// change adressing, see manual
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snprintf(buf, len, "dtcf");
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else if (value == 6) {
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// set extracode flag for next instruction, and the instruction after that,
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// if it is an index.
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snprintf(buf, len, "extend");
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extra_opcode_bit = true;
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} else if (value == 4)
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// disable interrupts
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snprintf(buf, len, "inhint");
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else if (!erasable && value == address + 1 && value != 10000)
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// NOOP's are special:
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// they are encoded as 10000 + current adress in fixed memory...
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// (which is a jump to the next instruction)
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snprintf(buf, len, "noop");
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else if (erasable && value == 030000)
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// ...and as a constant value in erasable memory, because the jump method
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// isn't applicable. Note that this way of encoding it means loading the
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// accumulator (A) with itself.
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snprintf(buf, len, "noop");
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else if (value == 054000)
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// skip the next instruction if A is overflown
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snprintf(buf, len, "ovsk");
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else if (value == 3)
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// enable interrupts after an inhint
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snprintf(buf, len, "relint");
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else if (value == 050017)
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// resume program from an ISR
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snprintf(buf, len, "resume");
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else if (value == 2)
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// return from subroutine, which is to say, move the Q register
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// into the Z register.
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snprintf(buf, len, "return");
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else if (value == 054005) // essentially a `TS Z`
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// jump to the address stored in the A register
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snprintf(buf, len, "tcaa");
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else if (value == 1) // essentially a `TC L`
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// convoluted control flow primitive from hell, see manual:
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// load an instruction in the `A` register, and a return instruction into
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// the `L` register, call `XLQ` and you will execute the contents of `A`
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// and return.
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||||
snprintf(buf, len, "xlq");
|
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else if (value == 0) // essentially `TC A`
|
||||
// similar to the above, but with extracode:
|
||||
// load an `EXTEND` instruction into the `A` register, an extracode
|
||||
// instruction into the `L` register, a return instruction into the `Q`
|
||||
// register and call `XXALQ`. This results in the execution of the given
|
||||
// extracode instruction.
|
||||
snprintf(buf, len, "xxalq");
|
||||
else if (value == 022007) // essentially `LXCH 7`
|
||||
// zero the `L` register, by exchanging it's content with the 7th register,
|
||||
// which is hardwired to zero.
|
||||
snprintf(buf, len, "zl");
|
||||
else switch (value & SWITCH_MASK) {
|
||||
// from now on, we have instructions with operands, so switch based on
|
||||
// the first three bits.
|
||||
case 000000: // i = 000, o = address of subroutine
|
||||
// call a subroutine (this can't be nested, because it stores the
|
||||
// current contents of the `Z` register in the `Q` register).
|
||||
snprintf(buf, len, "tc\t%04o", value & LOWER_WIDE);
|
||||
break;
|
||||
case 010000: // i = 001
|
||||
if (!(value & 06000)) // one of the many space-saving tricks employed
|
||||
// weird compare and jump (10 bit address in erasable memory)
|
||||
snprintf(buf, len, "ccs\t%04o",value & LOWER);
|
||||
else
|
||||
// jump to a memory location (12 bit address in fixed memory)
|
||||
snprintf(buf, len, "tcf\t%04o", value & LOWER_WIDE);
|
||||
break;
|
||||
case 020000: // i = 010
|
||||
switch (value & 06000) { // lower bits...
|
||||
case 00000:
|
||||
// add the `A`, `L` register pair to a memory location
|
||||
snprintf(buf, len, "das\t%04o", (value - 1) & LOWER);
|
||||
break;
|
||||
case 02000:
|
||||
// exchange the L register and a memory location
|
||||
snprintf(buf, len, "lxch\t%04o", value & LOWER);
|
||||
break;
|
||||
case 04000:
|
||||
// increment a memory location
|
||||
snprintf(buf, len, "incr\t%04o", value & LOWER);
|
||||
break;
|
||||
case 06000:
|
||||
// add the `A` register to a memory location
|
||||
snprintf(buf, len, "ads\t%04o", value & LOWER);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 030000: // i = 011
|
||||
// move a memory location's contents into the `A` register
|
||||
snprintf(buf, len, "ca\t%04o", value & LOWER_WIDE);
|
||||
break;
|
||||
case 040000: // i = 100
|
||||
// move a memory location's complement into the `A` register
|
||||
snprintf(buf, len, "cs\t%04o", value & LOWER_WIDE);
|
||||
break;
|
||||
case 050000: // i = 101
|
||||
switch (value & HIGHER) { // lower bits again...
|
||||
case 00000:
|
||||
// adds the contents of a memory location to the next
|
||||
// instruction before it is executed, without altering memory
|
||||
snprintf(buf, len, "index\t%04o", value & LOWER);
|
||||
break;
|
||||
case 02000:
|
||||
// exchange double precision int with `A`, `L` register pair
|
||||
snprintf(buf, len, "dxch\t%04o", (value - 1) & LOWER);
|
||||
break;
|
||||
case 04000:
|
||||
// copy the contents of the `A` register to memory, with extra
|
||||
// magic when overflow occured.
|
||||
snprintf(buf, len, "ts\t%04o", value & LOWER);
|
||||
break;
|
||||
case 06000:
|
||||
// exchange an erasable memory location with the `A` register
|
||||
snprintf(buf, len, "xch\t%04o", value & LOWER);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 060000: // i = 110
|
||||
// add a memory location to the `A` register
|
||||
snprintf(buf, len, "ad\t%04o", value & LOWER_WIDE);
|
||||
break;
|
||||
case 070000: // i = 111
|
||||
// logical and between the `A` register and a memory location
|
||||
snprintf(buf, len, "mask\t%04o", value & LOWER_WIDE);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
// the previous instruction was an `EXTEND`. This means we will interpret
|
||||
// not three, but four leading bits of our intruction as an opcode. This
|
||||
// was added to the second-generation AGC, after it became clear that three
|
||||
// bits for an opcode are not enough.
|
||||
extra_opcode_bit = false;
|
||||
if (value == 040001) // basically a `DCS A`
|
||||
// bitwise complement of the register pair `A`, `L`
|
||||
snprintf(buf, len, "dcom");
|
||||
else if (value == 050017) //
|
||||
// resume program from an ISR
|
||||
snprintf(buf, len, "resume"); // FIXME: wtf is this here? see manual...
|
||||
else if (value == 070000) // essentially `MP A`
|
||||
// square the contents of register `A`
|
||||
snprintf(buf, len, "square");
|
||||
else if (value == 022007) // essentially `QXCH 7`
|
||||
// zero the `Q` register, by exchanging it's content with the 7th register,
|
||||
// which is hardwired to zero.
|
||||
snprintf(buf, len, "zq");
|
||||
else switch (value & SWITCH_MASK) {
|
||||
case 000000: // i = 000
|
||||
switch (value & 07000) { // lower bits
|
||||
case 00000:
|
||||
// read a 9 bit IO channel into register `A`
|
||||
snprintf(buf, len, "read\t%03o", value & 0777);
|
||||
break;
|
||||
case 01000:
|
||||
// write register `A` into a 9 bit IO channel
|
||||
snprintf(buf, len, "write\t%03o", value & 0777);
|
||||
break;
|
||||
case 02000:
|
||||
// read and bitwise and
|
||||
snprintf(buf, len, "rand\t%03o", value & 0777);
|
||||
break;
|
||||
case 03000:
|
||||
// read and bitwise and with writeback
|
||||
snprintf(buf, len, "wand\t%03o", value & 0777);
|
||||
break;
|
||||
case 04000:
|
||||
// read and bitwise or
|
||||
snprintf(buf, len, "ror\t%03o", value & 0777);
|
||||
break;
|
||||
case 05000:
|
||||
// read and bitwise or with writeback
|
||||
snprintf(buf, len, "wor\t%03o", value & 0777);
|
||||
break;
|
||||
case 06000:
|
||||
// read and xor
|
||||
snprintf(buf, len, "rxor\t%03o", value & 0777);
|
||||
break;
|
||||
case 07000:
|
||||
// noone knows o__O
|
||||
snprintf(buf, len, "edrupt\t%03o", value & 0777);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 010000: // i = 001
|
||||
if (!(value & HIGHER))
|
||||
// divide register pair `A`, `L` by a memory location,
|
||||
// putting the quotient/remainder in `A`, `L`, respectively
|
||||
snprintf(buf, len, "dv\t%04o", value & LOWER);
|
||||
else
|
||||
// branch to a fixed memory location if `A` equals 0
|
||||
snprintf(buf, len, "bzf\t%04o", value & LOWER_WIDE);
|
||||
break;
|
||||
case 020000: // i = 010
|
||||
switch (value & HIGHER) {
|
||||
case 00000:
|
||||
// 1's complement difference between two 2's complement values
|
||||
// of which the first is the register `A`
|
||||
snprintf(buf, len, "msu\t%04o", value & LOWER);
|
||||
break;
|
||||
case 02000:
|
||||
// exchange `Q` register with memory location
|
||||
snprintf(buf, len, "qxch\t%04o", value & LOWER);
|
||||
break;
|
||||
case 04000:
|
||||
// increment positive and decrement negative values at a
|
||||
// memory location, using 1's complement
|
||||
snprintf(buf, len, "aug\t%04o", value & LOWER);
|
||||
break;
|
||||
case 06000:
|
||||
// other way 'round
|
||||
snprintf(buf, len, "dim\t%04o", value & LOWER);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 030000: // i = 011
|
||||
// move a pair of registers into `A` and `L`
|
||||
snprintf(buf, len, "dca\t%04o", (value - 1) & LOWER_WIDE);
|
||||
break;
|
||||
case 040000: // i = 100
|
||||
// move the complement of a pair of registers into `A` and `L`
|
||||
snprintf(buf, len, "dcs\t%04o", (value - 1) & LOWER_WIDE);
|
||||
break;
|
||||
case 050000: // i = 101
|
||||
// see above
|
||||
snprintf(buf, len, "index\t%04o", value & LOWER_WIDE);
|
||||
// reset bit
|
||||
extra_op_code_bit = true;
|
||||
break;
|
||||
case 060000: // i = 110
|
||||
if (!(value & HIGHER))
|
||||
// subtract a memory location from the `A` register
|
||||
snprintf(buf, len, "su\t%04o", value & LOWER);
|
||||
else
|
||||
// branch to a fixed memory location if `A` is equal or less than 0
|
||||
snprintf(buf, len, "bzmf\t%04o", value & LOWER_WIDE);
|
||||
break;
|
||||
case 070000: // i = 111
|
||||
// multiply two single precision values to form a double precision
|
||||
// value, of which one is the accumulator.
|
||||
snprintf(buf, len, "mp\t%04o", value & LOWER_WIDE);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,6 @@
|
||||
#ifndef INCLUDED_AGC_H
|
||||
#define INCLUDED_AGC_H
|
||||
|
||||
void disasm_instruction(unsigned int address, int value, char *buf, int len);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,54 @@
|
||||
com=complement the `A` register (address 0)
|
||||
ddoubl=add the A, `L` register pair to itself (addresses 0 and 1)
|
||||
double=add the `A` register to itself (address 0o)
|
||||
dtcb=change adressing, see manual
|
||||
dtcf=change adressing, see manual
|
||||
extend=set extracode flag for next instruction, and the instruction after that, if it is an index.
|
||||
inhint=disable interrupts
|
||||
noop=no operation, but note that this is encoded in a context-sensitive fashion
|
||||
ovsk=skip the next instruction if `A` is overflown
|
||||
relint=enable interrupts after an inhint
|
||||
resume=resume program from an ISR
|
||||
return=return from subroutine, which is to say, move the `Q` register into the `Z` register
|
||||
tcaa=jump to the address stored in the `A` register
|
||||
xlq=execute the content of the `A` register, assuming there is a `return` instruction in `L`
|
||||
xxalq=execute the content of the `L` register as an extracode instruction, assuming there is an `extend` instruction in the `A` register and a `return` instruction in `Q`
|
||||
zl=zero the `L` register
|
||||
tc=call a subroutine, can't be nested
|
||||
ccs=weird compare and jump (10 bit address in erasable memory)
|
||||
tcf=jump to a memory location (12 bit address in fixed memory)
|
||||
das=add the `A`, `L` register pair to a memory location
|
||||
lxch=exchange the `L` register and a memory location
|
||||
incr=increment a memory location
|
||||
ads=add the `A` register to a memory location
|
||||
ca=move a memory location's contents into the `A` register
|
||||
cs=move a memory location's complement into the `A` register
|
||||
index=add a memory location to the next instruction before it is executed, without altering memory
|
||||
dxch=exchange double precision int with `A`, `L` register pair
|
||||
ts=copy the contents of the `A` register to memory, with extra magic when overflow occured.
|
||||
xch=exchange an erasable memory location with the `A` register
|
||||
ad=add a memory location to the `A` register
|
||||
mask=logical and between the `A` register and a memory location
|
||||
dcom=bitwise complement of the register pair `A`, `L`
|
||||
resume=resume program from an ISR
|
||||
square=square the contents of register `A`
|
||||
zq=zero the `Q` register
|
||||
read=read a 9 bit IO channel into register `A`
|
||||
write=write register `A` into a 9 bit IO channel
|
||||
rand=read and bitwise and
|
||||
wand=read and bitwise and with writeback
|
||||
ror=read and bitwise or
|
||||
wor=read and bitwise or with writeback
|
||||
rxor=read and xor
|
||||
edrupt=noone knows o__O
|
||||
dv=divide register pair `A`, `L` by a memory location (double precision), putting the quotient/remainder in `A`, `L`, respectively
|
||||
bzf=branch to a fixed memory location if `A` equals 0
|
||||
msu=1's complement difference between two 2's complement values, of which the first is the register `A`
|
||||
qxch=exchange `Q` register with memory location
|
||||
aug=increment positive and decrement negative values at a memory location, using 1's complement
|
||||
dim=other way 'round compared to `aug`
|
||||
dca=move a pair of registers into `A` and `L`
|
||||
dcs=move the complement of a pair of registers into `A` and `L`
|
||||
su=subtract a memory location from the `A` register
|
||||
bzmf=branch to a fixed memory location if `A` is equal or less than 0
|
||||
mp=multiply two single precision values to form a double precision value, of which one is the accumulator.
|
||||
@@ -1,5 +1,6 @@
|
||||
ARCHS=
|
||||
|
||||
ARCHS+=agc.mk
|
||||
ARCHS+=armthumb.mk
|
||||
ARCHS+=ppc_disasm.mk
|
||||
ARCHS+=psosvm.mk
|
||||
|
||||
@@ -0,0 +1,11 @@
|
||||
OBJ_AGC=asm_agc.o
|
||||
OBJ_AGC+=../arch/agc/asm_agc.o
|
||||
|
||||
STATIC_OBJ+=${OBJ_AGC}
|
||||
TARGET_AGC=asm_agc.${LIBEXT}
|
||||
|
||||
ALL_TARGETS+=${TARGET_AGC}
|
||||
|
||||
${TARGET_AGC}: ${OBJ_AGC}
|
||||
${CC} $(call libname,asm_armthumb) ${LDFLAGS} \
|
||||
${CFLAGS} -o ${TARGET_AGC} ${OBJ_AGC}
|
||||
@@ -0,0 +1,36 @@
|
||||
#include <r_lib.h>
|
||||
#include <r_asm.h>
|
||||
#include "../arch/agc/asm_agc.h"
|
||||
|
||||
static int disassemble(RAsm *a, RAsmOp *op, const ut8 *buf, int len) {
|
||||
op->buf_asm[0] = 0;
|
||||
disasm_instruction(a->pc,
|
||||
((const ut16 *)buf)[0], op->buf_asm, R_ASM_BUFSIZE);
|
||||
op->size = 2;
|
||||
return op->size;
|
||||
}
|
||||
|
||||
static int assemble(RAsm *a, RAsmOp *op, const char *buf) {
|
||||
// TODO
|
||||
return 0;
|
||||
}
|
||||
|
||||
RAsmPlugin r_asm_plugin_agc = {
|
||||
.name = "agc",
|
||||
.arch = "agc",
|
||||
.bits = 16,
|
||||
.license = "GPL3",
|
||||
.desc = "AGC (Apollo Guidance Computer) disassembly plugin",
|
||||
.init = NULL,
|
||||
.fini = NULL,
|
||||
.disassemble = &disassemble,
|
||||
.assemble = &assemble
|
||||
};
|
||||
|
||||
#ifndef CORELIB
|
||||
struct r_lib_struct_t radare_plugin = {
|
||||
.type = R_LIB_TYPE_ASM,
|
||||
.data = &r_asm_plugin_agc,
|
||||
.version = R2_VERSION
|
||||
};
|
||||
#endif
|
||||
+33
@@ -0,0 +1,33 @@
|
||||
# TEST
|
||||
CC=gcc
|
||||
PREFIX=/usr
|
||||
HOST_OS=linux
|
||||
VERSION=0.10.4
|
||||
LIBDIR=/usr/lib
|
||||
INSTALL_LIB=/usr/bin/install -m 755 -c
|
||||
USEROSTYPE=auto
|
||||
|
||||
HAVE_PKGCFG_UNICORN=0
|
||||
UC_CFLAGS=
|
||||
UC_LDFLAGS=
|
||||
|
||||
R2_CFLAGS=-I/usr/include/libr
|
||||
R2_LDFLAGS=-lr_core -lr_config -lr_cons -lr_io -lr_util -lr_flags -lr_asm -lr_debug -lr_hash -lr_bin -lr_lang -lr_io -lr_anal -lr_parse -lr_bp -lr_egg -lr_reg -lr_search -lr_syscall -lr_socket -lr_fs -lr_magic
|
||||
|
||||
HAVE_LIB_EWF=0
|
||||
EWF_CFLAGS=
|
||||
EWF_LDFLAGS=
|
||||
|
||||
#CFLAGS+=$(R2_CFLAGS)
|
||||
#LDFLAGS+=$(R2_LDFLAGS)
|
||||
|
||||
ifeq ($(HOST_OS),darwin)
|
||||
LIBEXT?=dylib
|
||||
else
|
||||
ifeq ($(HOST_OS),windows)
|
||||
LIBEXT?=dll
|
||||
else
|
||||
LIBEXT?=so
|
||||
endif
|
||||
endif
|
||||
|
||||
Reference in new issue
Block a user