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Fix the broken Doxygen documentation blocks

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This commit is contained in:
Anton Kochkov
2026-09-06 10:23:06 +08:00
committed by NOT XVilka
parent ca2f24aebb
commit 98df84934a
70 changed files with 232 additions and 145 deletions
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librz/README.md
+4 -4
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@@ -9,13 +9,13 @@ to navigate the codebase.
- [RzUtil](util/README.md)
- [RzIO](io/README.md)
- [RzBin](bin/README.md)
- [RzAnalysis](analysis/README.md)
- [RzAsm](asm/README.md)
- RzAnalysis
- RzAsm
- [RzCons](cons/README.md)
- [RzDebug](debug/README.md)
- [RzFlag](flag/README.md)
- [RzCore](core/README.md)
- [RzBp](bp/README.md)
- RzBp
- [RzConfig](config/README.md)
- [RzCrypto](crypto/README.md)
- [RzDemangler](demangler/README.md)
@@ -26,7 +26,7 @@ to navigate the codebase.
- [RzLang](lang/README.md)
- [RzMagic](magic/README.md)
- [RzMain](main/README.md)
- [RzParse](parse/README.md)
- RzParse
- [RzReg](reg/README.md)
- [RzSearch](search/README.md)
- [RzSign](sign/README.md)
librz/arch/il_trace.c
+5 -5
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@@ -95,7 +95,7 @@ RZ_API bool rz_analysis_il_trace_add_mem(RzILTraceInstruction *trace, RzILTraceM
/**
* add register change to an instruction trace
* \param trace RzILTraceInstruction *, trace of instruction which triggers a register change
* \param mem RzILTraceRegOp *, info of register change
* \param reg info of register change
* \return true if succeed
*/
RZ_API bool rz_analysis_il_trace_add_reg(RzILTraceInstruction *trace, RzILTraceRegOp *reg) {
@@ -128,7 +128,7 @@ RZ_API bool rz_analysis_il_trace_add_reg(RzILTraceInstruction *trace, RzILTraceR
* Find the memory change in an instruction by given address
* \param trace RzILTraceInstruction *, instruction trace
* \param addr ut64, memory address
* \param is_write bool, true if you want to find a write operation to address, else find a read operation
* \param op_type kind of memory operation to look for
* \return RzILTraceMemOp *, info of memory change
*/
RZ_API RzILTraceMemOp *rz_analysis_il_get_mem_op_trace(RzILTraceInstruction *trace, ut64 addr, RzILTraceOpType op_type) {
@@ -165,7 +165,7 @@ RZ_API RzILTraceMemOp *rz_analysis_il_get_mem_op_trace(RzILTraceInstruction *tra
* Find the register change in an instruction by register name
* \param trace RzILTraceInstruction *, instruction trace
* \param regname const char *, name of register
* \param is_write bool, true if you want to find a write operation to register, else find a read operation
* \param op_type kind of register operation to look for
* \return RzILTraceRegOp *, info of register change
*/
RZ_API RzILTraceRegOp *rz_analysis_il_get_reg_op_trace(RzILTraceInstruction *trace, const char *regname, RzILTraceOpType op_type) {
@@ -202,7 +202,7 @@ RZ_API RzILTraceRegOp *rz_analysis_il_get_reg_op_trace(RzILTraceInstruction *tra
* Check if instruction contains a read/write to given address
* \param trace RzILTraceInstruction *, instruction trace
* \param addr ut64, Address of memory
* \param is_write bool, set true to find if it contains a write to address, else read
* \param op_type kind of memory operation to look for
* \return bool, true if contains, else return a false
*/
RZ_API bool rz_analysis_il_mem_trace_contains(RzILTraceInstruction *trace, ut64 addr, RzILTraceOpType op_type) {
@@ -213,7 +213,7 @@ RZ_API bool rz_analysis_il_mem_trace_contains(RzILTraceInstruction *trace, ut64
* Check if instruction contains a read/write to given register
* \param trace RzILTraceInstruction *, instruction trace
* \param regname const char *, name of register
* \param is_write bool, set true to find if it contains a write to the register, else read
* \param op_type kind of register operation to look for
* \return bool, true if contains, else return a false
*/
RZ_API bool rz_analysis_il_reg_trace_contains(RzILTraceInstruction *trace, const char *regname, RzILTraceOpType op_type) {
librz/arch/isa/luac/v54/arch_54.h
+2 -2
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@@ -146,7 +146,7 @@ typedef enum {
OP_UNM, ///< A B R[A] := -R[B]
OP_BNOT, ///< A B R[A] := ~R[B]
OP_NOT, ///< A B R[A] := not R[B]
OP_LEN, ///< A B R[A] := #R[B] (length operator)
OP_LEN, ///< A B `R[A] := #R[B]` (length operator)
OP_CONCAT, ///< A B R[A] := R[A].. ... ..R[A + B - 1]
@@ -175,7 +175,7 @@ typedef enum {
OP_RETURN1, ///< A return R[A]
OP_FORLOOP, ///< A Bx update counters; if loop continues then pc-=Bx;
OP_FORPREP, ///< A Bx <check values and prepare counters>; if not to run then pc+=Bx+1;
OP_FORPREP, ///< A Bx `<check values and prepare counters>`; if not to run then pc+=Bx+1;
OP_TFORPREP, ///< A Bx create upvalue for R[A + 3]; pc+=Bx
OP_TFORCALL, ///< A C R[A+4], ... ,R[A+3+C] := R[A](R[A+1], R[A+2]);
librz/arch/isa/luac/v55/arch_55.h
+2 -2
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@@ -151,7 +151,7 @@ typedef enum {
OP_UNM, ///< A B R[A] := -R[B]
OP_BNOT, ///< A B R[A] := ~R[B]
OP_NOT, ///< A B R[A] := not R[B]
OP_LEN, ///< A B R[A] := #R[B] (length operator)
OP_LEN, ///< A B `R[A] := #R[B]` (length operator)
OP_CONCAT, ///< A B R[A] := R[A].. ... ..R[A + B - 1]
@@ -180,7 +180,7 @@ typedef enum {
OP_RETURN1, ///< A return R[A]
OP_FORLOOP, ///< A Bx update counters; if loop continues then pc-=Bx;
OP_FORPREP, ///< A Bx <check values and prepare counters>; if not to run then pc+=Bx+1;
OP_FORPREP, ///< A Bx `<check values and prepare counters>`; if not to run then pc+=Bx+1;
OP_TFORPREP, ///< A Bx create upvalue for R[A + 3]; pc+=Bx
OP_TFORCALL, ///< A C R[A+4], ... ,R[A+3+C] := R[A](R[A+1], R[A+2]);
librz/arch/isa/milstd1750/milstd1750_disas.c
+2 -1
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@@ -2,7 +2,8 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file Disassembler for the MIL-STD-1750A instruction set architecture.
* \file
* Disassembler for the MIL-STD-1750A instruction set architecture.
*
* MIL-STD-1750A is a 16-bit military standard ISA originally developed by
* the US Department of Defense for airborne embedded computers. It features
librz/arch/isa/or1k/or1k_disas.h
+2 -2
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@@ -107,14 +107,14 @@ typedef struct {
char *name;
int type;
int opcode_mask;
int insn_type; /**< One of \link _RzAnalysisOpType \endlink */
int insn_type; /**< One of the RzAnalysisOpType values */
} insn_extra_t;
typedef struct {
ut32 opcode;
char *name;
int type;
int insn_type; /**< One of \link _RzAnalysisOpType \endlink */
int insn_type; /**< One of the RzAnalysisOpType values */
insn_extra_t *extra;
} insn_t;
librz/arch/isa/pic/pic_baseline.c
+2 -1
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@@ -5,7 +5,8 @@
#include "pic_midrange.h"
/**
* \file PIC Baseline (some but not all of 10Fxxx, 12Fxxx, and 16Fxxx) instruction set
* \file
* PIC Baseline (some but not all of 10Fxxx, 12Fxxx, and 16Fxxx) instruction set
* Because baseline instructions are a subset of midrange, but the encoding is
* different, only decoding is implemented specifically for baseline, but for analysis,
* il, etc., the decoded instructions are lifted to midrange and its code is reused.
librz/arch/isa/pic/pic_highend.c
+2 -1
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@@ -7,7 +7,8 @@
#include "pic_highend.h"
/**
* \file High-end (e.g. PIC18CXXX) instruction set
* \file
* High-end (e.g. PIC18CXXX) instruction set
*/
// instruction classification according to the argument types
librz/arch/isa/tms320/c2x/c2x_il.c
+1 -1
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@@ -57,7 +57,7 @@ static RzILOpPure *c2x_addr(const C55Operand *m) {
* \return Pure expression yielding the *word* address
*
* Word (not byte) addresses are the analysis/CFG convention for this arch;
* \ref c2x_byte scales the result where a byte address is needed.
* c2x_byte() scales the result where a byte address is needed.
*/
RZ_IPI RzILOpPure *c2x_ea(RZ_UNUSED const C55ArchDesc *a, const C55Operand *m) {
if (m->amode != C55_AM_DIRECT) {
librz/arch/isa/tms320/c55_ir.c
+1 -1
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@@ -6,7 +6,7 @@
* Shared, arch-independent layer of the TMS320 decode IR (see c55_ir.h):
* - c55_decode(): the table-walking decode engine
* - c55_x_*(): the operand extractors the per-arch tables reference
* - c55_generic_ea() etc: RzIL primitives consumed by each arch's ::lift
* - c55_generic_ea() etc: RzIL primitives consumed by each arch's `lift`
* - c55_format / c55_fill_analysis / c55_lift: the three pure consumers
*
* Per-arch specifics (encoding tables, register set, mnemonic/op-type/lift
librz/arch/isa/tms320/c55_ir.h
+32 -32
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@@ -98,19 +98,19 @@ typedef enum {
C55_AM_POSTDEC, ///< *arN-
C55_AM_PREINC, ///< *+arN
C55_AM_PREDEC, ///< *-arN
C55_AM_INDEXED, ///< *arN(short(#K)) / *sp(#K)
C55_AM_INDEXED, ///< `*arN(short(#K))` / `*sp(#K)`
C55_AM_IDXREG, ///< *arN(tM)
C55_AM_POSTADD, ///< *(arN+tM)
C55_AM_POSTSUB, ///< *(arN-tM)
C55_AM_IDXSCALE, ///< *arN(tM<<#1)
C55_AM_ABSOLUTE, ///< *(#k) absolute address
C55_AM_CONST_IDX, ///< *arN(#K16) long const-index (2-byte extension, ARn unmodified)
C55_AM_CONST_IDX_PRE, ///< *+arN(#K16) long const-index with pre-modify (2-byte extension, ARn += K16)
C55_AM_ABS16, ///< abs16(#k16) data-page absolute: DPH:k16 (2-byte extension, k16 unsigned)
C55_AM_ABSOLUTE, ///< `*(#k)` absolute address
C55_AM_CONST_IDX, ///< `*arN(#K16)` long const-index (2-byte extension, ARn unmodified)
C55_AM_CONST_IDX_PRE, ///< `*+arN(#K16)` long const-index with pre-modify (2-byte extension, ARn += K16)
C55_AM_ABS16, ///< `abs16(#k16)` data-page absolute: DPH:k16 (2-byte extension, k16 unsigned)
// arch-specific: C55ArchDesc::ea()
C55_AM_BITREV, ///< *(arN+t0b) reverse-carry (C54x *arN+0B)
C55_AM_XAR15, ///< *arN(xar15)
C55_AM_DIRECT, ///< C54x DP/SP-relative direct (@addr / addr)
C55_AM_DIRECT, ///< C54x DP/SP-relative direct (`@addr` / `addr`)
C55_AM_MMR, ///< C54x memory-mapped register
C55_AM_CIRCULAR, ///< explicit circular via BK/ARP
C55_AM_BITREV_SUB, ///< *(arN-t0b) reverse-carry (the decrement bit-reverse form)
@@ -130,7 +130,7 @@ typedef enum {
C55_OP_REG, ///< register (optional sub-field, optional shift wrapper)
C55_OP_IMM, ///< immediate (width + signedness, optional shift wrapper)
C55_OP_MEM, ///< data-memory operand (base + amode + index + disp + access)
C55_OP_COND, ///< condition: reg <relop> 0|imm|reg (bcc/xcc/cmp/btst)
C55_OP_COND, ///< condition: `reg <relop> 0|imm|reg` (bcc/xcc/cmp/btst)
C55_OP_INVALID, ///< operand the decoder cannot represent yet; forces legacy fallback
} C55OpKind;
@@ -187,10 +187,10 @@ typedef struct {
C55Relop relop; ///< COND: relational operator
bool cmp_to_reg; ///< COND: compare to \ref index register rather than \ref imm
bool cond_is_flag; ///< COND: a status-bit flag expression rather than reg <relop> 0
bool cond_is_flag; ///< COND: a status-bit flag expression rather than `reg <relop> 0`
ut8 cond_flag; ///< COND: status-flag id (when \ref cond_is_flag)
bool cmp_imm; ///< COND: compare to an explicit immediate (#0x..) vs literal #0
bool cmp_mem; ///< COND: the left-hand side is a memory operand (cmp Smem <rel> #k)
bool cmp_mem; ///< COND: the left-hand side is a memory operand (`cmp Smem <rel> #k`)
bool elide_if_eq_prev; ///< REG: omit this operand (and its separator) when it equals the immediately preceding operand (mpyk/mack ACy defaulting to ACx)
bool circular; ///< MEM: C54x circular-addressing variant (the '%' suffix: *arN+%, *arN+0%, ...)
bool is_shift; ///< IMM: this operand is a standalone C54x shift count applied to the preceding value (\ref shamt / \ref sh_left carry the amount/direction)
@@ -229,27 +229,27 @@ typedef enum {
C55_LOP_ADDV, ///< dst = dst + |src(32-16)| (addition with absolute value)
C55_LOP_SFTL, ///< dst = sftl(src, Tx): logical shift, right by -Tx when Tx<0 else left by Tx
C55_LOP_SFTS, ///< dst = sfts(src, Tx): arithmetic right shift (sign-fill) / logical left
C55_LOP_ANDSHL, ///< dst = dst & (src << #SHIFTW)
C55_LOP_ORSHL, ///< dst = dst | (src << #SHIFTW)
C55_LOP_XORSHL, ///< dst = dst ^ (src << #SHIFTW)
C55_LOP_ADDSHL, ///< dst = dst + (src << #SHIFTW)
C55_LOP_SUBSHL, ///< dst = dst - (src << #SHIFTW)
C55_LOP_MOVSHL, ///< dst = (src << #SHIFTW): load a shifted immediate (mov #k16 << #sh)
C55_LOP_ANDSHL, ///< dst = dst & `(src << #SHIFTW)`
C55_LOP_ORSHL, ///< dst = dst | `(src << #SHIFTW)`
C55_LOP_XORSHL, ///< dst = dst ^ `(src << #SHIFTW)`
C55_LOP_ADDSHL, ///< dst = dst + `(src << #SHIFTW)`
C55_LOP_SUBSHL, ///< dst = dst - `(src << #SHIFTW)`
C55_LOP_MOVSHL, ///< dst = `(src << #SHIFTW)`: load a shifted immediate (`mov #k16 << #sh`)
C55_LOP_ANDMEM, ///< ACy = ACx & sx(Smem)
C55_LOP_ORMEM, ///< ACy = ACx | sx(Smem)
C55_LOP_XORMEM, ///< ACy = ACx ^ sx(Smem)
C55_LOP_BITCLR, ///< STx = STx & ~(1 << #k4): clear a status-register bit (bclr); also the register bit ops with an is_bit operand
C55_LOP_BITSET, ///< STx = STx | (1 << #k4): set a status-register bit (bset)
C55_LOP_BITCLR, ///< STx = STx & ~`(1 << #k4)`: clear a status-register bit (bclr); also the register bit ops with an is_bit operand
C55_LOP_BITSET, ///< STx = STx | `(1 << #k4)`: set a status-register bit (bset)
C55_LOP_BITNOT, ///< dst = dst ^ (1 << k): toggle a register bit (bnot)
C55_LOP_STBITCLR, ///< st0_55 = ite(0, st0_55 | (1<<bit), st0_55 & ~(1<<bit)): clear an st0_55 named bit
C55_LOP_STBITSET, ///< st0_55 = ite(1, st0_55 | (1<<bit), st0_55 & ~(1<<bit)): set an st0_55 named bit
C55_LOP_AMOV, ///< dst = zero-extend(#k16): load a 16-bit constant/address (amov)
C55_LOP_CMP, ///< TCz = (SRC <relop> DST): register compare writing a status TC bit
C55_LOP_CMPAND, ///< TCz = (SRC <relop> DST) && TCx
C55_LOP_CMPOR, ///< TCz = (SRC <relop> DST) || TCx
C55_LOP_AMOV, ///< dst = `zero-extend(#k16)`: load a 16-bit constant/address (amov)
C55_LOP_CMP, ///< TCz = `(SRC <relop> DST)`: register compare writing a status TC bit
C55_LOP_CMPAND, ///< TCz = `(SRC <relop> DST)` && TCx
C55_LOP_CMPOR, ///< TCz = `(SRC <relop> DST)` || TCx
C55_LOP_AREG_MOV, ///< dst = cast(dst, src): register move with width conversion (amov ACx,ACy)
C55_LOP_AREG_SUB, ///< dst = dst - cast(dst, src): register address subtract (asub ACx,ACy)
C55_LOP_AREG_ADD, ///< dst = dst + cast(dst, src): register/immediate address add (aadd #k,reg)
C55_LOP_AREG_ADD, ///< dst = dst + cast(dst, src): register/immediate address add (`aadd #k,reg`)
C55_LOP_AREG_AND, ///< dst = dst & cast(dst, src): A-unit register and (and src, dst)
C55_LOP_AREG_OR, ///< dst = dst | cast(dst, src): A-unit register or (or src, dst)
C55_LOP_AREG_XOR, ///< dst = dst ^ cast(dst, src): A-unit register xor (xor src, dst)
@@ -260,13 +260,13 @@ typedef enum {
C55_LOP_OPAQUE, ///< decode + analyse only; data effect not modelled (no IL)
C55_LOP_ROL, ///< ACy = rotate-left(ACx) by one through a status bit (carry/tc2)
C55_LOP_ROR, ///< ACy = rotate-right(ACx) by one through a status bit (carry/tc2)
C55_LOP_MPYK, ///< ACy = #k * ACx: multiply accumulator low word by a signed constant (mpyk/mpykr)
C55_LOP_MACK, ///< ACy = ACx + #k * Tx: multiply-accumulate a signed constant by a Tx coefficient (mack/mackr)
C55_LOP_ADDK, ///< dst = ACx + zero-extend(#k16): immediate add (opcode 0x7b)
C55_LOP_SUBK, ///< dst = ACx - zero-extend(#k16): immediate subtract (opcode 0x7c)
C55_LOP_ANDK, ///< dst = ACx & zero-extend(#k16): immediate and (opcode 0x7d)
C55_LOP_ORK, ///< dst = ACx | zero-extend(#k16): immediate or (opcode 0x7e)
C55_LOP_XORK, ///< dst = ACx ^ zero-extend(#k16): immediate xor (opcode 0x7f)
C55_LOP_MPYK, ///< `ACy = #k * ACx`: multiply accumulator low word by a signed constant (mpyk/mpykr)
C55_LOP_MACK, ///< `ACy = ACx + #k * Tx`: multiply-accumulate a signed constant by a Tx coefficient (mack/mackr)
C55_LOP_ADDK, ///< dst = ACx + `zero-extend(#k16)`: immediate add (opcode 0x7b)
C55_LOP_SUBK, ///< dst = ACx - `zero-extend(#k16)`: immediate subtract (opcode 0x7c)
C55_LOP_ANDK, ///< dst = ACx & `zero-extend(#k16)`: immediate and (opcode 0x7d)
C55_LOP_ORK, ///< dst = ACx | `zero-extend(#k16)`: immediate or (opcode 0x7e)
C55_LOP_XORK, ///< dst = ACx ^ `zero-extend(#k16)`: immediate xor (opcode 0x7f)
C55_LOP_RPTADD, ///< CSR = CSR + src: single-repeat-counter add (rptadd CSR, src). The repeat loop itself (the next instruction running CSR+1 times) is a control-flow effect that one-instruction RzIL cannot express; only the named CSR write is modelled.
C55_LOP_RPTSUB, ///< CSR = CSR - src: single-repeat-counter subtract (rptsub CSR, src). As with RPTADD, only the CSR write is modelled, not the repeat loop.
} C55LiftOp;
@@ -327,7 +327,7 @@ struct c55_op_desc_t;
*/
typedef void (*C55Extract)(const struct c55_arch_desc_t *a, ut64 bits, const struct c55_op_desc_t *d, C55Operand *out);
/** One operand slot in a \ref C55InsnDef: which bits feed which extractor. */
/** One operand slot in a \ref C55InsnDef, mapping bits to an extractor. */
typedef struct c55_op_desc_t {
ut8 lo; ///< bitfield start (LSB index within the packed instruction word)
ut8 width; ///< bitfield width
@@ -370,7 +370,7 @@ typedef struct {
/**
* The arch extension point. Adding C54x = providing one of these; C55x/C55x+
* each provide one but share id/register/mnemonic tables. The decode fields
* (\ref table .. \ref insn_len) are optional: an arch may instead fill
* (`table` .. `insn_len`) are optional: an arch may instead fill
* \ref C55Insn from its own front-end (e.g. capstone for a future C64x lifter)
* and still use the consumers and primitives.
*/
@@ -379,7 +379,7 @@ typedef struct c55_arch_desc_t {
const char *cpu_name; ///< "c54x" / "c55x" / "c55x+"
const C55InsnDef *table; ///< instruction table (NULL if decoded externally)
size_t table_len; ///< number of rows in \ref table
size_t table_len; ///< number of rows in `table`
ut8 (*insn_len)(const ut8 *buf, int len); ///< variable-length decode helper
const C55RegInfo *(*reg_info)(C55RegClass cls, ut8 num, C55SubReg sub); ///< register resolver
librz/arch/isa/tms320/c5x/c5x.c
+2 -2
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@@ -22,7 +22,7 @@
*
* Only the C5x-only ids and the shared ids whose canonical C5x spelling
* differs from the C2x one are handled here; the rest delegate to
* \ref c2x_mnemonic.
* c2x_mnemonic().
*/
RZ_IPI const char *c5x_mnemonic(ut16 id) {
switch (id) {
@@ -110,7 +110,7 @@ RZ_IPI const char *c5x_mnemonic(ut16 id) {
* \param id C5X_INS_* id, or a shared C2X_INS_* id
* \return RZ_ANALYSIS_OP_TYPE_* value for \p id
*
* Shared ids delegate to \ref c2x_op_type.
* Shared ids delegate to c2x_op_type().
*/
RZ_IPI ut32 c5x_op_type(ut16 id) {
switch (id) {
librz/arch/isa/tms320/c5x/c5x.h
+2 -2
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@@ -88,8 +88,8 @@ enum {
C5X_INS_BD, ///< delayed branch
C5X_INS_CALLD, ///< delayed call
C5X_INS_BANZD, ///< delayed branch on AR not zero
C5X_INS_LST, ///< load status register STn (C5x #n, mem form)
C5X_INS_SST, ///< store status register STn (C5x #n, mem form)
C5X_INS_LST, ///< load status register STn (C5x `#n`, mem form)
C5X_INS_SST, ///< store status register STn (C5x `#n`, mem form)
};
RZ_IPI int c5x_decode(const ut8 *buf, int len, C55Insn *out);
librz/arch/isa/tricore/README.md
+2
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@@ -1,3 +1,5 @@
# TriCore architecture
Tricore ISA 1.3: https://www.infineon.com/dgdl/tc_v131_corearchitecture_v__138.pdf?fileId=db3a304412b407950112b409c4500359
Tricore ISA 1.6: https://www.infineon.com/dgdl/tc1_6__architecture_vol1.pdf?fileId=db3a3043372d5cc801373b0f374d5d67
librz/arch/similarity.c
+1 -1
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@@ -350,7 +350,7 @@ fail:
/**
* \brief Frees a valid pointer to a RzAnalysisMatchResult struct
*
* \param[in] RzAnalysisMatchResult The analysis match result to be freed
* \param[in] result The analysis match result to be freed
*/
RZ_API void rz_analysis_match_result_free(RZ_NULLABLE RzAnalysisMatchResult *result) {
if (!result) {
librz/bin/README.md
+1
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@@ -0,0 +1 @@
# RzBin
librz/bin/format/elf/elf64_parser.c
+2 -1
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@@ -3,7 +3,8 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file The functions in this file are an API for binary modules which need
* \file
* The functions in this file are an API for binary modules which need
* ELF parsing capabilities.
* Most of the ELF plugin was not build as library and can't be used without
* code duplication.
librz/bin/format/elf/elf_parser.c
+2 -1
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@@ -3,7 +3,8 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file The functions in this file are an API for binary modules which need
* \file
* The functions in this file are an API for binary modules which need
* ELF parsing capabilities.
* Most of the ELF plugin was not build as library and can't be used without
* code duplication.
librz/bin/format/gns1/gns1.c
+2 -1
View File
@@ -2,7 +2,8 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file Implementation of Apple C4000 baseband firmware (GNS1.bin) parser.
* \file
* Implementation of Apple C4000 baseband firmware (GNS1.bin) parser.
*
* Detection heuristic:
* - Dword at offset 0xC (first chunk offset) must be >= 0x64
librz/bin/format/mach0/mach0_chained_fixups.c
+2
View File
@@ -101,7 +101,9 @@ RZ_API size_t MACH0_(chained_imports_count)(struct MACH0_(obj_t) * obj) {
/**
* Copy contents of a dyld_chained_import* of the binary into \p dst
* \param obj Mach-O object to read the import from
* \param ordinal index of the import, given by chained pointers
* \param dst where the import is copied to
* \return true if an import with the given ordinal was found and read successfully
*/
RZ_API bool MACH0_(get_chained_import)(struct MACH0_(obj_t) * obj, ut32 ordinal, struct MACH0_(chained_import_t) * dst) {
librz/bin/format/mbn/mbn.c
+2 -1
View File
@@ -3,7 +3,8 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file The MBN file format is not publicly documented currently.
* \file
* The MBN file format is not publicly documented currently.
* It is used in Qualcomm firmware images to verify the firmware binaries against the root of trust.
* There are more than one version of the MBN file format.
* This implementation only handles the signature bundle for the Qualcomm secure boot mechanism.
librz/bin/format/mdt/mdt.h
+2 -1
View File
@@ -2,7 +2,8 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file Loader for the Qualcomm peripheral firmware images.
* \file
* Loader for the Qualcomm peripheral firmware images.
*
* Reference: https://github.com/torvalds/linux/blob/master/drivers/soc/qcom/mdt_loader.c
*/
librz/bin/format/mtk/md1img.c
+2 -1
View File
@@ -2,7 +2,8 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file Parser for MediaTek md1img container format.
* \file
* Parser for MediaTek md1img container format.
*
* The md1img format is a simple section-based container used by MediaTek
* to package modem firmware components: md1rom (GFH firmware image),
librz/bin/format/mtk/md1img.h
+2 -1
View File
@@ -2,7 +2,8 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file Header for MediaTek md1img container format parser.
* \file
* Header for MediaTek md1img container format parser.
*
* The md1img format packages modem firmware components: md1rom (GFH image),
* debug info (CATI format), DSP images, certificates, etc.
librz/bin/format/mtk/mtk.c
+2 -1
View File
@@ -2,7 +2,8 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file Implementation of MediaTek GFH firmware image parser (md1rom).
* \file
* Implementation of MediaTek GFH firmware image parser (md1rom).
*
* The GFH (Generic File Header) format is used by MediaTek for bootloader
* and modem firmware images. The file starts with a chain of GFH headers
librz/bin/format/omf/omf.h
+4 -3
View File
@@ -220,7 +220,7 @@ typedef enum omf_ityp_t {
*/
ITYP_COMMANDFILE = 0x03, ///< Commandfile descriptor.
/**
* Used when @file was given in the invocation line.
* Used when \@file was given in the invocation line.
*/
ITYP_OBJECT_INPUTFILE = 0x04, ///< Object-Inputfile descriptor.
/**
@@ -547,7 +547,8 @@ typedef struct {
* +------+-------+-----+
* | E8 | R16 | N |
* +------+-------+-----+
* *
* ```
*
* ```
* **************************************************************
* * 0x94 | RecLen | AddressBase | LinNum16 | Offset16 | ChkSum *
@@ -692,7 +693,7 @@ typedef struct {
ut8 n; ///< struct/union-tag name length
char tagname[MAX_NAME_LEN]; ///< struct/union-tag name in OMF166 name format
ut32 size; ///< sizeof struct or union
ut16 member_ti; ///< reference to component list or <void>
ut16 member_ti; ///< reference to component list or `<void>`
} struct_union;
struct {
ut16 ti; ///< base scalar type of the field [uchar, uint, long ]
librz/bin/golang.c
+1 -1
View File
@@ -267,7 +267,7 @@ static void find_go_build_info(RzBinFile *bf, GoBuildInfo *go_info, RzBinSection
/**
* \brief Returns the golang compiler info if buildinfo struct is found.
*
* \param RzBinFile The RzBinFile to use for the search
* \param bf The RzBinFile to use for the search
*
* \return Returns a string on success, otherwise NULL
*/
librz/config/README.md
+1
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@@ -0,0 +1 @@
# RzConfig
librz/cons/README.md
+1
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@@ -0,0 +1 @@
# RzCons
librz/core/README.md
+1
View File
@@ -0,0 +1 @@
# RzCore
librz/core/basefind.c
+2 -1
View File
@@ -3,7 +3,8 @@
// SPDX-License-Identifier: MIT
/**
* \file Calculates a list of possible base addresses candidates using the strings position
* \file
* Calculates a list of possible base addresses candidates using the strings position
* Original code from 2013 Michael Coppola
* https://github.com/mncoppola/ws30/blob/master/basefind.py
*/
librz/core/cmd/cmd_search_gadget.c
+1
View File
@@ -402,6 +402,7 @@ compound:
/**
* \brief Create a new RzGadgetSearchContext object.
* \param core RZ_NONNULL Pointer to the RzCore structure containing configuration settings.
* \param gadget_type Kind of gadget to search for.
* \param greparg RZ_NULLABLE Pointer to a string containing the grep argument.
* \param regexp Flag specifying whether regular expressions should be used.
* \param mask Gadget request mask specifying the Gadget request parameters.
librz/core/cmeta.c
+1 -1
View File
@@ -482,4 +482,4 @@ RZ_API bool rz_core_meta_pascal_string_add(RzCore *core, ut64 addr, RzStrEnc enc
return true;
}
/**@{*/
/**@}*/
librz/core/cmp.c
+2 -1
View File
@@ -394,7 +394,8 @@ RZ_API bool rz_core_cmpwatch_del(RzCore *core, ut64 addr) {
* \param core Current RzCore instance
* \param addr Address of the memory watcher to be printed (if UT64_MAX, then all memory watchers will be printed)
* \param mode Output mode
* \return void Print nothing if no memory watcher found at \p addr
*
* Prints nothing if no memory watcher is found at \p addr.
*/
RZ_API void rz_core_cmpwatch_show(RzCore *core, ut64 addr, RzOutputMode mode) {
rz_return_if_fail(core);
librz/core/gadget.c
-1
View File
@@ -448,7 +448,6 @@ RZ_API RZ_BORROW RzGadgetRegInfo *rz_core_gadget_info_get_modified_register(cons
* \brief Update a register info in the RzGadgetInfo object.
* \param gadget_info Pointer to the RzGadgetInfo object.
* \param new_reg_info Pointer to the new RzGadgetRegInfo object.
* \return void
*
* Updates the register info in the RzGadgetInfo object with the values from the new register info.
* If the register is not already in the modified registers list, it is added.
librz/core/p/core_plugin_example.c
+1 -1
View File
@@ -17,7 +17,7 @@
* - rizin =
* This init was called!
* - [0x00000000]> example?
* Usage: example <number> # example summary that contains some description
* Usage: example `<number>` # example summary that contains some description
* - [0x00000000]> example 1777
* WARNING: the parsed number is 1777
* - [0x00000000]> example -777
librz/crypto/README.md
+1
View File
@@ -0,0 +1 @@
# RzCrypto
librz/debug/README.md
+1
View File
@@ -0,0 +1 @@
# RzDebug
librz/debug/p/native/unsupported.c
+3 -2
View File
@@ -3,8 +3,9 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file This is a file with dummy debugger functions for when
* the native debugger is unsupported.
* \file
* This is a file with dummy debugger functions for when
* the native debugger is unsupported.
*/
#include <rz_debug.h>
librz/demangler/README.md
+1
View File
@@ -0,0 +1 @@
# RzDemangler
librz/diff/README.md
+1
View File
@@ -0,0 +1 @@
# RzDiff
librz/egg/README.md
+1
View File
@@ -0,0 +1 @@
# RzEgg
librz/egg/egg_c_compile.c
+1 -1
View File
@@ -4,7 +4,7 @@
#include <rz_egg.h>
typedef struct egg_c_config {
const char *triplet; ///< <os>-<arch>-<bits>
const char *triplet; ///< `<os>-<arch>-<bits>`
const char *exe_compiler; ///< special compiler to override the normal one.
const char *add_cflags; ///< CFLAGS to append
const char *add_ldflags; ///< LDFLAGS to append
librz/flag/README.md
+1
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@@ -0,0 +1 @@
# RzFlag
librz/hash/algorithms/murmur3/murmur3.c
+2 -1
View File
@@ -2,7 +2,8 @@
// SPDX-License-Identifier: MIT
/**
* \file MurmurHash3.cpp
* \file
* MurmurHash3.cpp
* High performance non cryptographic hashing algorithm.
* Implementation of the MurmurHash3 algorithm.
* 3 variants of this algo are provided to hash 32,64 and 128 bit data
librz/il/README.md
+1
View File
@@ -0,0 +1 @@
# RzIL
librz/il/definitions/float.c
+2 -1
View File
@@ -2,7 +2,8 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file this file contains some float function used in rzil fbasic theory
* \file
* this file contains some float function used in rzil fbasic theory
* To avoid conflict during developing, I put some float operation here at first
* Some of them should be moved to rz_util/float in the future and resolve conflict to merge
*/
librz/il/il_events.c
+10 -11
View File
@@ -31,7 +31,7 @@ RZ_API const char *rz_il_event_exception_msg(const RzILEventException id) {
/**
* Frees an RzILEvent struct
* \param evt, RzILEvent, pointer to the RzILEvent to free
* \param evt Pointer to the RzILEvent to free
*/
RZ_API void rz_il_event_free(RZ_NULLABLE RzILEvent *evt) {
if (!evt) {
@@ -72,7 +72,6 @@ RZ_API void rz_il_event_free(RZ_NULLABLE RzILEvent *evt) {
/**
* Creates an RzILEvent of type RZ_IL_EVENT_EXCEPTION
* \param id The exception identifier.
* \param msg Pointer to the exception message
*/
RZ_API RZ_OWN RzILEvent *rz_il_event_exception_new(RzILEventException id) {
rz_return_val_if_fail(id != RZ_IL_EVENT_EXC_NONE, NULL);
@@ -90,8 +89,8 @@ RZ_API RZ_OWN RzILEvent *rz_il_event_exception_new(RzILEventException id) {
/**
* Creates an RzILEvent of type RZ_IL_EVENT_PC_WRITE
* \param old_pc, RzBitVector, old program counter value before the change
* \param new_pc, RzBitVector, new program counter value after the change
* \param old_pc Old program counter value before the change
* \param new_pc New program counter value after the change
*/
RZ_API RZ_OWN RzILEvent *rz_il_event_pc_write_new(RZ_NONNULL const RzBitVector *old_pc, RZ_NONNULL const RzBitVector *new_pc) {
rz_return_val_if_fail(old_pc && new_pc, NULL);
@@ -114,9 +113,9 @@ RZ_API RZ_OWN RzILEvent *rz_il_event_pc_write_new(RZ_NONNULL const RzBitVector *
/**
* Creates an RzILEvent of type RZ_IL_EVENT_MEM_READ
* \param index, RzILMemIndex, index of the memory to read
* \param addr, RzBitVector, address of the memory where the read op has occurred
* \param value, RzBitVector, value read from the variable
* \param index Index of the memory to read
* \param address Address of the memory where the read op has occurred
* \param value Value read from the variable
*/
RZ_API RZ_OWN RzILEvent *rz_il_event_mem_read_new(RzILMemIndex index, RZ_NONNULL const RzBitVector *address, RZ_NULLABLE const RzBitVector *value) {
rz_return_val_if_fail(address && value, NULL);
@@ -140,10 +139,10 @@ RZ_API RZ_OWN RzILEvent *rz_il_event_mem_read_new(RzILMemIndex index, RZ_NONNULL
/**
* Creates an RzILEvent of type RZ_IL_EVENT_MEM_WRITE
* \param index, RzILMemIndex, index of the memory to store data
* \param addr, RzBitVector, address of the memory that has changed
* \param old_v, RzBitVector, old value before the change
* \param new_v, RzBitVector, new value after the change
* \param index Index of the memory to store data
* \param addr Address of the memory that has changed
* \param old_v Old value before the change
* \param new_v New value after the change
*/
RZ_API RZ_OWN RzILEvent *rz_il_event_mem_write_new(RzILMemIndex index, RZ_NONNULL const RzBitVector *addr, RZ_NONNULL const RzBitVector *old_v, RZ_NONNULL const RzBitVector *new_v) {
rz_return_val_if_fail(addr && old_v && new_v, NULL);
librz/il/il_graph.c
+2
View File
@@ -813,6 +813,7 @@ static void il_op_effect_graph_resolve(RzILOpEffect *op, RzGraph /*<RzGraphNodeI
/**
* \brief Generates the graph representation of the IL pure statement
* \param op IL pure statement
* \param name Name of the root node, "pure" when NULL
* \return On success returns a valid pointer, otherwise NULL.
*/
RZ_API RZ_OWN RzGraph /*<RzGraphNodeInfo *, NULL *>*/ *rz_il_op_pure_graph(RZ_NONNULL RzILOpPure *op, RZ_NULLABLE const char *name) {
@@ -830,6 +831,7 @@ RZ_API RZ_OWN RzGraph /*<RzGraphNodeInfo *, NULL *>*/ *rz_il_op_pure_graph(RZ_NO
/**
* \brief Generates the graph representation of the IL effect statement
* \param op IL effect statement
* \param name Name of the root node, "effect" when NULL
* \return On success returns a valid pointer, otherwise NULL.
*/
RZ_API RZ_OWN RzGraph /*<RzGraphNodeInfo *, NULL *>*/ *rz_il_op_effect_graph(RZ_NONNULL RzILOpEffect *op, RZ_NULLABLE const char *name) {
librz/il/il_routines.c
+2 -1
View File
@@ -2,7 +2,8 @@
// SPDX-License-Identifier: LGPL-3.0-only
/**
* \file Implements common bit operation perfomed on values.
* \file
* Implements common bit operation perfomed on values.
*/
#include <rz_util/rz_assert.h>
librz/il/il_vm.c
+13 -9
View File
@@ -15,9 +15,10 @@ extern RZ_IPI RzILOpEffectHandler rz_il_op_handler_effect_table_default[RZ_IL_OP
/**
* initiate an empty VM
* \param vm RzILVM, pointer to an empty VM
* \param start_addr ut64, initiation pc address
* \param addr_size ut32, size of the address in VM
* \param vm Pointer to an empty VM
* \param start_addr Initial pc address
* \param addr_size Size of the address in the VM
* \param big_endian True if the VM memory is big endian
* \param halt_exc The exceptions the VM should halt for if encountered.
*/
RZ_API bool rz_il_vm_init(RzILVM *vm, ut64 start_addr, ut32 addr_size, bool big_endian, RzILEventException halt_exc) {
@@ -101,9 +102,9 @@ RZ_API void rz_il_vm_fini(RzILVM *vm) {
/**
* Create a new empty VM
* \param vm RzILVM, pointer to an empty VM
* \param start_addr ut64, initiation pc address
* \param addr_size ut32, size of the address in VM
* \param start_addr Initial pc address
* \param addr_size Size of the address in the VM
* \param big_endian True if the VM memory is big endian
* \param halt_exc The exceptions the VM should halt for if encountered.
*/
RZ_API RzILVM *rz_il_vm_new(ut64 start_addr, ut32 addr_size, bool big_endian, RzILEventException halt_exc) {
@@ -210,6 +211,8 @@ RZ_API RzILLocalPurePrev rz_il_vm_push_local_pure_var(RZ_NONNULL RzILVM *vm, RZ_
/**
* \brief Remove a local let binding and restore the state for the outer context.
* \param vm Pointer to the VM
* \param name Name of the local variable to unbind
* \param prev pass here the return value of rz_il_vm_push_local_pure_var()
*/
RZ_API void rz_il_vm_pop_local_pure_var(RZ_NONNULL RzILVM *vm, RZ_NONNULL const char *name, RzILLocalPurePrev prev) {
@@ -317,9 +320,10 @@ RZ_API RZ_BORROW RzILEffectLabel *rz_il_vm_create_label_lazy(RZ_NONNULL RzILVM *
/**
* Update the address info of a label
* \param vm RzILVM, pointer to VM
* \param name string, name of this label
* \return lbl RzILEffectLabel, pointer to label instance
* \param vm Pointer to the VM
* \param name Name of this label
* \param addr New address of the label
* \return Pointer to the label instance
*/
RZ_API RZ_BORROW RzILEffectLabel *rz_il_vm_update_label(RZ_NONNULL RzILVM *vm, RZ_NONNULL char *name, RZ_NONNULL RZ_BORROW RzBitVector *addr) {
rz_return_val_if_fail(vm && name && addr, NULL);
librz/il/il_vm_eval.c
+21 -17
View File
@@ -192,9 +192,10 @@ RZ_IPI RzILOpEffectHandler rz_il_op_handler_effect_table_default[RZ_IL_OP_EFFECT
/**
* Load data from memory by given key and generates an RZ_IL_EVENT_MEM_READ event
* \param vm RzILVM, pointer to VM
* \param key RzBitVector, aka address, a key to load data from memory
* \return val Bitvector, data at the address, has `vm->min_unit_size` length
* \param vm Pointer to the VM
* \param index Index of the memory to read
* \param key Address to load the data from
* \return Data at the address, `vm->min_unit_size` wide
*/
RZ_API RzBitVector *rz_il_vm_mem_load(RzILVM *vm, RzILMemIndex index, RzBitVector *key) {
rz_return_val_if_fail(vm && key, NULL);
@@ -212,9 +213,10 @@ RZ_API RzBitVector *rz_il_vm_mem_load(RzILVM *vm, RzILMemIndex index, RzBitVecto
* Store data to memory by key, will create a key-value pair
* or update the key-value pair if key existed; also generates
* an RZ_IL_EVENT_MEM_WRITE event
* \param vm RzILVM* pointer to VM
* \param key RzBitVector, aka address, a key to store data from memory
* \param value RzBitVector, aka value to store in memory
* \param vm Pointer to the VM
* \param index Index of the memory to store data into
* \param key Address to store the data at
* \param value Value to store in memory
*/
RZ_API void rz_il_vm_mem_store(RzILVM *vm, RzILMemIndex index, RzBitVector *key, RzBitVector *value) {
rz_return_if_fail(vm && key && value);
@@ -231,9 +233,11 @@ RZ_API void rz_il_vm_mem_store(RzILVM *vm, RzILMemIndex index, RzBitVector *key,
/**
* Load data from memory by given key and generates an RZ_IL_EVENT_MEM_READ event
* \param vm RzILVM, pointer to VM
* \param key RzBitVector, aka address, a key to load data from memory
* \return val Bitvector, data at the address, has `vm->min_unit_size` length
* \param vm Pointer to the VM
* \param index Index of the memory to read
* \param key Address to load the data from
* \param n_bits Amount of bits to load
* \return Data at the address, \p n_bits wide
*/
RZ_API RzBitVector *rz_il_vm_mem_loadw(RzILVM *vm, RzILMemIndex index, RzBitVector *key, ut32 n_bits) {
rz_return_val_if_fail(vm && key, NULL);
@@ -251,10 +255,10 @@ RZ_API RzBitVector *rz_il_vm_mem_loadw(RzILVM *vm, RzILMemIndex index, RzBitVect
* Store data to memory by key, will create a key-value pair
* or update the key-value pair if key existed; also generates
* an RZ_IL_EVENT_MEM_WRITE event
* \param index RzILMemIndex, index of the memory to store data
* \param vm RzILVM* pointer to VM
* \param key RzBitVector, aka address, a key to store data from memory
* \param value RzBitVector, aka value to store in memory
* \param vm Pointer to the VM
* \param index Index of the memory to store data into
* \param key Address to store the data at
* \param value Value to store in memory
*/
RZ_API void rz_il_vm_mem_storew(RzILVM *vm, RzILMemIndex index, RzBitVector *key, RzBitVector *value) {
rz_return_if_fail(vm && key && value);
@@ -275,8 +279,8 @@ end:
/**
* Adds to the VM a new event into the VM event list
* \param vm, RzILVM, pointer to the VM
* \param evt, RzILEvent, pointer to the event
* \param vm Pointer to the VM
* \param evt Pointer to the event
*/
RZ_API void rz_il_vm_event_add(RzILVM *vm, RzILEvent *evt) {
rz_return_if_fail(vm && vm->events && evt);
@@ -299,8 +303,8 @@ RZ_API void rz_il_vm_clear_events(RzILVM *vm) {
/**
* Execute the opcodes uplifted from raw instructions.A list may contain multiple opcode trees
* \param vm pointer to VM
* \param op_list, a list of op roots.
* \param vm Pointer to the VM
* \param op Root of the op tree to evaluate
* \param fallthrough_addr initial address to set PC to. Thus also the address to "step to" if no explicit jump occurs.
*/
RZ_API bool rz_il_vm_step(RzILVM *vm, RzILOpEffect *op, ut64 fallthrough_addr) {
librz/include/rz_cmd.h
+1 -1
View File
@@ -175,7 +175,7 @@ typedef struct rz_cmd_alias_t {
* a command, variables, etc.).
*
* Displayed as:
* | <text><arg_str> # <comment>
* | `<text><arg_str> # <comment>`
*/
typedef struct rz_cmd_desc_detail_entry_t {
/**
librz/include/rz_util/rz_annotated_code.h
+1 -1
View File
@@ -78,7 +78,7 @@ typedef struct rz_code_annotation_t {
*/
typedef struct rz_annotated_code_t {
char *code; /**< Decompiled code. RzAnnotatedCode owns this string and it must free it. */
RzVector /*<RzCodeAnnotation>*/ annotations; /**< @ref RzVector <RzCodeAnnotation> contains the list of annotations for the decompiled code. */
RzVector /*<RzCodeAnnotation>*/ annotations; /**< Contains the list of annotations for the decompiled code. */
} RzAnnotatedCode;
/**
librz/include/rz_util/rz_str.h
+2 -2
View File
@@ -54,8 +54,8 @@ typedef struct {
bool show_asciidot; ///< When true, dots `.` are placed instead of unprintable ASCII characters.
bool esc_bslash; ///< When true, backslashes `\` are quoted with `\\`
bool esc_double_quotes; ///< When true, double quotes `"` are quoted with `\"`
bool dot_nl; ///< When true, \n is converted into the graphiz-compatible newline \l
bool keep_printable; ///< Keep all printable characters (excludes \n, \t etc.).
bool dot_nl; ///< When true, `\n` is converted into the graphiz-compatible newline `\l`
bool keep_printable; ///< Keep all printable characters (excludes `\n`, `\t` etc.).
} RzStrEscOptions;
/**
librz/lang/README.md
+1
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@@ -0,0 +1 @@
# RzLang
librz/magic/README.md
+1
View File
@@ -0,0 +1 @@
# RzMagic
librz/main/README.md
+1
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@@ -0,0 +1 @@
# RzMain
librz/reg/README.md
+1
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@@ -0,0 +1 @@
# RzReg
librz/socket/README.md
+1
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@@ -0,0 +1 @@
# RzSocket
librz/type/README.md
+1 -1
View File
@@ -1,4 +1,4 @@
# Type database and `pf` format engine
# Type database and pf format engine
This library owns Rizin's representation of C-style types (structs, unions,
enums, typedefs, callables) and the `pf` print-format language for decoding
librz/type/format.c
+5 -5
View File
@@ -234,7 +234,7 @@ static void base_type_to_format_unfold(const RzTypeDB *typedb, RZ_NONNULL RzBase
/**
* \brief Represents the RzBaseType as a `pf` format string
*
* Produces the pair of of <format> <fields>. If the type
* Produces the pair of of `<format> <fields>`. If the type
* is atomic it searches if the type database has predefined
* format assigned to it and uses it.
*
@@ -258,7 +258,7 @@ RZ_API RZ_OWN char *rz_base_type_as_format(const RzTypeDB *typedb, RZ_NONNULL Rz
/**
* \brief Represents the RzBaseType as a `pf` format string
*
* Produces the pair of of <format> <fields>. If the type
* Produces the pair of of `<format> <fields>`. If the type
* is atomic it searches if the type database has predefined
* format assigned to it and uses it.
*
@@ -554,8 +554,8 @@ static void type_to_format(const RzTypeDB *typedb, RzStrBuf *buf, RzType *type)
* \brief Represents the RzType as a `pf` format string
*
* Different from the similar function for the RzBaseType,
* since the latter shows the pair of <format> <fields>,
* while this implementation produces only the <format> part.
* since the latter shows the pair of `<format> <fields>`,
* while this implementation produces only the `<format>` part.
*
* \param typedb Types Database instance
* \param type RzType type
@@ -636,7 +636,7 @@ static bool type_to_format_pair(const RzTypeDB *typedb, RzStrBuf *format, RzStrB
*
* Different from the similar `rz_type_as_format` and similar
* to the `rz_base_type_as_format` since the latter shows
* the pair of <format> <fields>.
* the pair of `<format> <fields>`.
*
* \param typedb Types Database instance
* \param type RzType type
librz/type/pf/pf_parser_time.c
+3
View File
@@ -172,6 +172,9 @@ static bool dos_to_tm(ut32 dosval, struct tm *out) {
* formats, v_f64 for OLE/Cocoa. The reader (rz_pf_timestamp_read) takes
* care of placing the bytes in the right slot.
*
* \param fmt Timestamp format the raw scalar holds
* \param raw Raw scalar holding the timestamp value
* \param out_tm Broken-down UTC time to fill in
* \param out_subsec_ns Optional out-param for sub-second precision; set
* to 0 for second-resolution formats.
* \return true on success, false on unknown format or out-of-range DOS
librz/util/base64.c
+1 -1
View File
@@ -360,7 +360,7 @@ RZ_API st64 rz_base64_decode(RZ_OUT RZ_NULLABLE ut8 *dest, RZ_NULLABLE const cha
/**
* \brief Decode a Base64-encoded message.
* \param[in] src The encoded message to decode.
* \param n The length of the encoded message.
* \param len The length of the encoded message.
* \return The dynamically-allocated decoded binary-data.
*
* This function dynamically allocates a buffer in which to store the
librz/util/float/float.c
+43 -7
View File
@@ -50,8 +50,9 @@ RZ_API bool rz_float_ext80_set_rounding_precision(RzFloatRPrecision precision) {
}
/**
* \defgroup Generate Nan and infinite for float/double/long double
* @ {
* \defgroup rz_float_special_group Special values
* generates NaN and infinity for float/double/long double
* \{
*/
#define define_types_gen_nan(fname, ftype) \
RZ_API ftype rz_types_gen_##fname##_nan() { \
@@ -80,10 +81,12 @@ define_types_gen_nan(f128, long double);
define_types_gen_inf(f32, float);
define_types_gen_inf(f64, double);
define_types_gen_inf(f128, long double);
/**@}*/
/** \} */ // end rz_float_special_group
/** \defgroup Helper utilities to inter-operate with SoftFloat.
* @ {
/**
* \defgroup rz_float_softfloat_group SoftFloat helpers
* utilities to inter-operate with SoftFloat
* \{
*/
static inline float16_t to_float16(RzFloat *f16) {
rz_warn_if_fail(f16->r == RZ_FLOAT_IEEE754_BIN_16);
@@ -260,7 +263,7 @@ static inline bool f128_is_zero(float128_t value) {
static inline bool ext_f80_is_special(extFloat80_t value) {
return (value.signExp & 0x7fff) == 0x7fff;
}
/**@}*/
/** \} */ // end rz_float_softfloat_group
/**
* \brief return the bitvector string of a float
@@ -490,6 +493,7 @@ RZ_API void rz_float_free(RZ_NULLABLE RzFloat *f) {
/**
* Init the bitvector inside float
* \param f float
* \param format format of the float
* \return return true if init success else return false
*/
RZ_API bool rz_float_init(RZ_NONNULL RzFloat *f, RzFloatFormat format) {
@@ -1300,6 +1304,8 @@ RZ_API RZ_OWN RzFloat *rz_float_new_snan(RzFloatFormat format) {
/**
* calculate \p left + \p right and round the result after, return the result
* \param left left operand
* \param right right operand
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -1330,6 +1336,8 @@ RZ_API RZ_OWN RzFloat *rz_float_add_ieee_bin(RZ_NONNULL RzFloat *left, RZ_NONNUL
/**
* calculate \p left - \p right and round the result after, return the result
* \param left left operand
* \param right right operand
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -1360,6 +1368,8 @@ RZ_API RZ_OWN RzFloat *rz_float_sub_ieee_bin(RZ_NONNULL RzFloat *left, RZ_NONNUL
/**
* calculate \p left * \p right and round the result after, return the result
* \param left left operand
* \param right right operand
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -1396,6 +1406,8 @@ RZ_API RZ_OWN RzFloat *rz_float_mul_ieee_bin(RZ_NONNULL RzFloat *left, RZ_NONNUL
* Inf / Inf -> invalid
* 0 / 0 -> invalid
* 0 / not 0 -> 0
* \param left left operand
* \param right right operand
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -1431,6 +1443,8 @@ RZ_API RZ_OWN RzFloat *rz_float_div_ieee_bin(RZ_NONNULL RzFloat *left, RZ_NONNUL
* Inf % Any => NaN, invalid
* Any % Inf -> Any
* 0 % Any -> 0
* \param left left operand
* \param right right operand
* \param mode rounding mode used for calculating the quotient
* \return result of arithmetic operation
*
@@ -1468,6 +1482,8 @@ RZ_API RZ_OWN RzFloat *rz_float_rem_ieee_bin(RZ_NONNULL RzFloat *left, RZ_NONNUL
* Inf % Any => NaN, invalid
* Any % Inf -> Any
* 0 % Any -> 0
* \param left left operand
* \param right right operand
* \param mode rounding mode used for calculating the quotient
* \return result of arithmetic operation
*
@@ -1508,6 +1524,9 @@ RZ_API RZ_OWN RzFloat *rz_float_mod_ieee_bin(RZ_NONNULL RzFloat *left, RZ_NONNUL
/**
* calculate \p a * \p b + \p c, and round the result after, return the result
* \param a first factor
* \param b second factor
* \param c addend
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -1611,6 +1630,7 @@ RZ_API RZ_OWN RzFloat *rz_float_fma_ieee_bin(RZ_NONNULL RzFloat *a, RZ_NONNULL R
/**
* calculate the root of \p n, and round the result after, return the result
* \param n the operand to take the root of
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -1688,7 +1708,7 @@ RZ_API RZ_OWN RzFloat *rz_float_trunc(RZ_NONNULL RzFloat *f) {
/**
* \brief round float to an integral valued float with the same format
* \detail [fround m x] is the floating-point number closest to [x]
* \details [fround m x] is the floating-point number closest to [x]
* rounded to an integral, using the rounding mode [m].
* \param f float
* \param mode round mode
@@ -2009,6 +2029,8 @@ RZ_API RZ_OWN RzFloat *rz_float_convert(RZ_NONNULL RzFloat *f, RzFloatFormat for
/**
* calculate \p left + \p right and round the result after, return the result
* \param x left operand
* \param y right operand
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -2018,6 +2040,8 @@ RZ_API RZ_OWN RzFloat *rz_float_add(RZ_NONNULL RzFloat *x, RZ_NONNULL RzFloat *y
/**
* calculate \p left - \p right and round the result after, return the result
* \param x left operand
* \param y right operand
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -2027,6 +2051,8 @@ RZ_API RZ_OWN RzFloat *rz_float_sub(RZ_NONNULL RzFloat *x, RZ_NONNULL RzFloat *y
/**
* calculate \p left * \p right and round the result after, return the result
* \param x left operand
* \param y right operand
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -2042,6 +2068,8 @@ RZ_API RZ_OWN RzFloat *rz_float_mul(RZ_NONNULL RzFloat *x, RZ_NONNULL RzFloat *y
* Inf / Inf -> invalid
* 0 / 0 -> invalid
* 0 / not 0 -> 0
* \param x left operand
* \param y right operand
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -2056,6 +2084,8 @@ RZ_API RZ_OWN RzFloat *rz_float_div(RZ_NONNULL RzFloat *x, RZ_NONNULL RzFloat *y
* Inf % Any => NaN, invalid
* Any % Inf -> Any
* 0 % Any -> 0
* \param x left operand
* \param y right operand
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -2070,6 +2100,8 @@ RZ_API RZ_OWN RzFloat *rz_float_rem(RZ_NONNULL RzFloat *x, RZ_NONNULL RzFloat *y
* Inf % Any => NaN, invalid
* Any % Inf -> Any
* 0 % Any -> 0
* \param x left operand
* \param y right operand
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -2079,6 +2111,9 @@ RZ_API RZ_OWN RzFloat *rz_float_mod(RZ_NONNULL RzFloat *x, RZ_NONNULL RzFloat *y
/**
* calculate \p a * \p b + \p c, and round the result after, return the result
* \param a first factor
* \param b second factor
* \param c addend
* \param mode rounding mode
* \return result of arithmetic operation
*/
@@ -2088,6 +2123,7 @@ RZ_API RZ_OWN RzFloat *rz_float_fma(RZ_NONNULL RzFloat *a, RZ_NONNULL RzFloat *b
/**
* calculate the root of \p n, and round the result after, return the result
* \param n the operand to take the root of
* \param mode rounding mode
* \return result of arithmetic operation
*/
librz/util/float/float_internal.c
+2 -2
View File
@@ -4,8 +4,8 @@
#include <rz_util.h>
/**
* \file : Internal function for float
* \brief : Should be included directly in float.c
* \file
* \brief Internal functions for float, included directly in float.c
*/
static inline ut32 rz_float_info_bin16(RzFloatInfo which_info) {
switch (which_info) {
librz/util/ht/ht_inc.c
+2 -2
View File
@@ -18,8 +18,8 @@
* \brief "SwissTable" hash table implementation.
*
* References:
* - https://abseil.io/about/design/swisstables
* - https://en.wikipedia.org/wiki/Open_addressing
* - https://abseil.io/about/design/swisstables
* - https://en.wikipedia.org/wiki/Open_addressing
*/
// Load factor thershold of 87.5% (after that the table grows)
librz/util/num/value_print.c
+2 -2
View File
@@ -226,7 +226,7 @@ static void print_bitvector(const RzNumValue *v, RzStrBuf *sb, bool utf8) {
* BIG decimal + hex (lossless)
* BITVECTOR bit-width / hex / binary
*
* On a value with v->err != RZ_NUM_ERR_OK, a single 'error <category>'
* On a value with v->err != RZ_NUM_ERR_OK, a single `error <category>`
* line is appended instead.
*
* \param v The value to format.
@@ -250,7 +250,7 @@ static void print_bigdecimal(const RzNumValue *v, RzStrBuf *sb) {
*
* With opts->utf8 set, a bit-vector additionally renders a compact
* Unicode form (hex value with the bit-width as a subscript, e.g.
* 0x2c\u2088), mirroring how RzIL renders bit-vectors in its Unicode
* `0x2c\u2088`), mirroring how RzIL renders bit-vectors in its Unicode
* export. Other kinds are unaffected for now.
*
* \param v The value to format. Must be a valid RzNumValue.
librz/util/structured_data.c
+3 -3
View File
@@ -549,7 +549,7 @@ RZ_API bool rz_structured_data_array_add_signed(RZ_NONNULL RzStructuredData *par
* \brief Adds double type child to an array type parent
*
* \param parent Where to add the child RzStructuredData
* \param n The value to assign to the child
* \param d The value to assign to the child
*
* \return On success returns true, otherwise false.
*/
@@ -561,10 +561,10 @@ RZ_API bool rz_structured_data_array_add_double(RZ_NONNULL RzStructuredData *par
}
/**
* \brief Adds signed type child to an array type parent
* \brief Adds boolean type child to an array type parent
*
* \param parent Where to add the child RzStructuredData
* \param n The value to assign to the child
* \param b The value to assign to the child
*
* \return On success returns true, otherwise false.
*/
librz/util/thread_ring_buf.c
+2 -1
View File
@@ -7,7 +7,8 @@
#include <rz_util/rz_sys.h>
/**
* \file A ring buffer implementation.
* \file
* A ring buffer implementation.
*
* Functionally it is equivalent to a fixed size queue, except that it
* copies the data into the buffer.