12638 Commits
Author SHA1 Message Date
Daniel Nylander cd024df237 Update Swedish Qt translation preview 2026-10-11 02:47:54 +10:00
Stenzek 387c35ffe0 Settings: Use constants for section names 2026-10-10 21:47:56 +10:00
Stenzek 5e3b269274 Settings: Fix inconsistent default values 2026-10-10 21:47:44 +10:00
Stenzek 5df57d1a3b System: Don't use exact sleep on core thread
Only need an exact sleep for pre-frame sleep, since the frame is scheduled
to finish just in time.

Otherwise waking slightly late is harmless, the video thread handles the
presentation timing.

In the worst case, input would get polled up to 0.5ms later than originally
expected which isn't going to hurt anything. If you have that little frame
budget, disable optimal frame pacing.
2026-10-10 21:47:44 +10:00
Stenzek 875f0e07f1 Settings: Shorten fastmem mode description 2026-10-10 21:47:44 +10:00
Stenzek 252c1cbec6 InputManager: Return proper error from GetGenericBindingMapping() 2026-10-10 21:47:44 +10:00
Stenzek e04aa86a42 ZipHelpers: Fix incorrect error message 2026-10-10 21:47:44 +10:00
Stenzek dcb230b15c System: Avoid unnecessary mutex unlock->relock 2026-10-10 21:47:44 +10:00
Stenzek 88af218295 System: Add optional callback to screenshot save 2026-10-10 21:47:44 +10:00
Stenzek 371115a5b8 CPU: Don't stall for GTE with a single cycle remaining
Fixes timing of 5 and 8 cycle commands in psxtest_gte.
2026-10-10 21:47:44 +10:00
Stenzek 44bb56d651 CMake: Improve reproducibility
Relative build RPATH, rcc mtime pinning.
2026-10-10 21:47:44 +10:00
Stenzek 29fe750fc9 MSBuild: Improve reproducibility
Pin mtime of rcc timestamps.
2026-10-10 21:47:44 +10:00
Stenzek 73d4e3c75a CDROM: Vectorize XA resampling 2026-10-10 21:47:43 +10:00
Stenzek bbf5cc9142 GTE: Use branchless saturation for light matrix multiply
With lm set, every normal facing away from a light gets clamped to zero,
so unlike elsewhere, the saturation branches are frequently mispredicted
here. Clamp unconditionally and derive the flag from the comparison.
2026-10-10 21:47:43 +10:00
Stenzek 077c034020 GTE: Mark saturation branches as unlikely
With the helpers inlined, FLAG is kept in a register, which led to the
compiler turning the IR/colour saturation checks into conditional moves.
That is slower than a predicted branch when saturation is rare, and made
DPCS slower than it was before inlining.
2026-10-10 21:47:43 +10:00
Stenzek 86c84f9d5f GTE: Simplify FLAG error bit update
The error bit is always clear when it is computed, since FLAG is either
reset at the start of the instruction, or masked when the guest writes
it. So it can be ORed in, instead of being cleared and reinserted.
2026-10-10 21:47:43 +10:00
Stenzek 50225103a1 GTE: Use shift for IRGB/ORGB conversion
Dividing rounds towards zero, which needs a fixup for negative values.
Those are clamped to zero regardless, so an arithmetic shift is the same.
2026-10-10 21:47:43 +10:00
Stenzek 7547f640c5 GTE: Factorize NCLIP to use three multiplies
The cross product can be computed with half as many multiplies. None of
the intermediates can overflow, and only the sum was being range checked,
so MAC0 and the flags are unchanged.
2026-10-10 21:47:43 +10:00
Stenzek ef5bffc8d7 GTE: Specialize instruction handlers on sf/lm
The recompilers resolve the handler once per instruction, so return a
variant with the sf/lm bits baked in. Shift amounts and IR saturation
limits become constants, rather than being decoded for each execution.
2026-10-10 21:47:43 +10:00
Stenzek 811585c42c GTE: Force inline matrix/lighting/projection helpers
The triple variants were making up to nine calls per instruction, with
FLAG and IR1-3 going through memory between each of them. PGXP's part of
RTPS is moved out of line instead, so the integer path stays compact.
2026-10-10 21:47:43 +10:00
Stenzek 78f91b6d34 GTE: Only sign extend MAC results on overflow
Sign extending to 44 bits is a no-op unless the value is out of range,
so move it to the overflow path, and test both bounds with a single
comparison. Shortens the dependency chain of each matrix row.
2026-10-10 21:47:43 +10:00
Stenzek cc9be54402 GTE: Add regression tests
Covers IR/colour saturation, 44-bit MAC overflow wrapping, NCLIP and ORGB
against reference formulas, and hashes the register state after random
instructions through both the interpreter and recompiler entry points.
2026-10-10 21:47:43 +10:00
Stenzek 276b8adb2d SPU: Extract reverb-master-enable out of loop 2026-10-10 21:47:42 +10:00
Stenzek aad9c4ebec SPU: Pack reverb FIR coefficients into 16-bit lanes
Use three packed multiply-adds for the 20-tap upsampling FIR and widen
the shared coefficients for downsampling. Preserve the final shift and clamp.
The absolute coefficient sum is 31142, keeping every s32 sum within range.

Validated output, persistent state, and RAM against the original across
8,192 frames using both SSE4.1 and SSE2; compiled with clang-cl /O2.
2026-10-10 21:47:42 +10:00
Stenzek e7098b5156 SPU: Skip reverb output filtering at zero volume
Bypass the read-only upsampling FIR for channels with zero output volume.
Keep updating feedback and resampling history so re-enabling output is exact.

Validated output and persistent state against the original implementation
across 8,192 frames with independent output-volume and enable transitions.
2026-10-10 21:47:42 +10:00
Stenzek 69f643c195 SPU: Fast-path ADPCM blocks without predictors
Decode shifted nibbles directly when both predictor coefficients are zero,
preserving interpolation history, predictor history, and block flags.

Validated against the original decoder across 262,144 blocks and all
header filters/shifts; compiled with clang-cl /O2.
2026-10-10 21:47:42 +10:00
Stenzek 9deb896297 CPU/Recompiler: Handle large ARM64 backpatch cycle counts
Materialize cycle counts in a scratch register when they do not fit an ADD/SUB immediate, avoiding assertions for long blocks.
2026-10-10 21:47:42 +10:00
Stenzek 470ef0656f CPU/Recompiler: Use 32-bit ARM64 fastmem LUT indices
Shift the guest address into a W register in load and store paths, matching operand widths and avoiding VIXL_DEBUG assertions.
2026-10-10 21:47:42 +10:00
Stenzek a5d6e76ef1 CPU/Recompiler: Align ARM32 backpatch thunk calls
Pad odd register save lists with the reserved state register to preserve the required eight-byte stack alignment when calling memory helpers.
2026-10-10 21:47:42 +10:00
Stenzek beb75d1dec CPU/Recompiler: Decode ARM32 load exceptions from r0
Negate the low half of the checked-read error return so address and bus errors retain their correct exception codes.
2026-10-10 21:47:42 +10:00
Stenzek 6db5f053d9 CPU/Recompiler: Truncate ARM64 multiplication results in LO
Clear the upper product bits after extracting HI so an MFLO register rename cannot carry them into a guest fastmem address.
2026-10-10 21:47:42 +10:00
Stenzek 885d5bbdde CPU/Recompiler: Mask constant variable shift counts on ARM
Mask shift counts to five bits before checking for zero, avoiding invalid ARM64 instructions and ARM32 assembler failures for counts such as 32.
2026-10-10 21:47:42 +10:00
Stenzek 22cc43186c CPU/Recompiler: Fix ARM32 VIXL debug builds
Use the assembler addresses for debug scopes and finalize jump patches and trampolines so VIXL_DEBUG can compile and emit code correctly.
2026-10-10 21:47:42 +10:00
Stenzek cb3cfb8c1f CPU/Recompiler: Correct misaligned indirect jump exceptions
Check constant JALR targets and report invalid JR/JALR targets in EPC and BadVaddr before executing the delay slot on every backend.
2026-10-10 21:47:41 +10:00
Stenzek c401e9318d CPU/Recompiler: Preserve pending loads on memory exceptions
Include the pending load in exception flushes so RaiseException commits it before entering the handler on every backend.
2026-10-10 21:47:41 +10:00
Stenzek 3a8b6fccfc CPU/Recompiler: Trap constant signed arithmetic overflow
Detect overflow in folded ADD, SUB and ADDI and use the interpreter exception path, including writes to zero and branch delay slots.
2026-10-10 21:47:41 +10:00
Stenzek bd29ee475f CPU/Recompiler: Dispatch interpreter fallback exceptions
Exit generated blocks when the interpreter raises an exception, preserving its handler PC across all backends and implementing the missing RISC-V and LoongArch fallback paths.
2026-10-10 21:47:41 +10:00
Stenzek e78ab9a273 CPU/Recompiler: Keep link-register delay slots in order
Track ra as the implicit branch-and-link destination and check decoded register dependencies before swapping the delay slot.
2026-10-10 21:47:41 +10:00
Stenzek 0aa0c767e1 CPU/Recompiler: Cancel pending loads on self moves
Compile same-register moves as writes to cancel load delays, preserving constant operands before clearing the destination.
2026-10-10 21:47:41 +10:00
Stenzek ed990b9275 CPU/Recompiler: Respect load delays when swapping NOP slots
Check pending loads before accepting a NOP delay slot so branches read the original register value.
2026-10-10 21:47:41 +10:00
Stenzek 9bedaa6163 FileSystem: Add more ReadFileToString() overloads 2026-10-10 21:47:41 +10:00
Stenzek 6d96829465 FileSystem: More RVO optimizations 2026-10-10 21:47:41 +10:00
Stenzek a8fb9d70e4 FileSystem: Use shared file open for ReadBinaryFile/ReadFileToString 2026-10-10 21:47:41 +10:00
Stenzek aaffbd66d9 FileSystem: Extract find result sorting to function 2026-10-10 21:47:40 +10:00
Stenzek 066d89715c FileSystem: Add error parameter to FTell64() 2026-10-10 21:47:40 +10:00
Stenzek 60aec342eb FileSystem: Make OpenSharedCFile() wrap OpenCFile() on non-Windows 2026-10-10 21:47:40 +10:00
Stenzek 659ff37089 FileSystem: Backport additional helper functions 2026-10-10 21:47:40 +10:00
Stenzek ba3590f902 Core: Don't reset folders when resetting settings
Users having their data save locations would be unexpected.
2026-10-10 21:47:40 +10:00
Stenzek 95722d8e99 Settings: Don't copy controller type to game
These are part of the controller settings...
2026-10-10 21:47:40 +10:00
Stenzek 8bb030b8cf Settings: Add a dedicated key for overlays 2026-10-10 21:47:40 +10:00