Giovanni Mascellani
2c3a7b0dd9
vkd3d-shader/ir: Validate the register type for DCL_OUTPUT_SIV instructions.
2024-11-25 20:51:29 +01:00
Giovanni Mascellani
3832e38ce0
vkd3d-shader/ir: Validate the register type for DCL_OUTPUT instructions.
2024-11-25 20:51:25 +01:00
Giovanni Mascellani
e7770eaaf6
vkd3d-shader/ir: Validate the register type for DCL_INPUT_PS_SGV instructions.
2024-11-25 20:48:39 +01:00
Giovanni Mascellani
1d9862261f
vkd3d-shader/ir: Validate the register type for DCL_INPUT_PS_SIV instructions.
2024-11-25 20:48:39 +01:00
Giovanni Mascellani
09ede1e7f2
vkd3d-shader/ir: Validate the register type for DCL_INPUT_PS instructions.
2024-11-25 20:48:39 +01:00
Giovanni Mascellani
31f6b18c84
vkd3d-shader/ir: Validate the register type for DCL_INPUT_SGV instructions.
2024-11-25 20:48:39 +01:00
Giovanni Mascellani
fadaa69b92
vkd3d-shader/ir: Validate the register type for DCL_INPUT_SIV instructions.
2024-11-25 20:48:39 +01:00
Giovanni Mascellani
b007b1dd79
vkd3d-shader/ir: Validate the register type for DCL_INPUT instructions.
2024-11-25 20:48:39 +01:00
Giovanni Mascellani
a8c5f9e667
vkd3d-shader/dxil: Emit register SAMPLEMASK for output sysval SV_Coverage.
2024-11-25 20:47:24 +01:00
Giovanni Mascellani
c22812e20b
vkd3d-shader/ir: Validate index count for OUTSTENCILREF registers.
2024-11-25 20:45:44 +01:00
Giovanni Mascellani
e367dc0783
vkd3d-shader/ir: Validate index count for WAVELANEINDEX registers.
2024-11-25 20:45:44 +01:00
Giovanni Mascellani
5b04a7973b
vkd3d-shader/ir: Validate index count for WAVELANECOUNT registers.
2024-11-25 20:45:44 +01:00
Giovanni Mascellani
820a545950
vkd3d-shader/ir: Validate index count for GSINSTID registers.
2024-11-25 20:45:44 +01:00
Giovanni Mascellani
07b31761fb
vkd3d-shader/ir: Validate index count for SAMPLEMASK registers.
2024-11-25 20:45:44 +01:00
Giovanni Mascellani
9f3bbad6bc
vkd3d-shader/ir: Validate index count for COVERAGE registers.
2024-11-25 20:45:44 +01:00
Feifan He
71ce43313f
vkd3d-shader/msl: Implement VKD3DSIH_MOVC.
2024-11-25 20:43:13 +01:00
Feifan He
32a507ace6
vkd3d-shader/msl: Implement VKD3DSIH_FRC.
2024-11-25 20:43:13 +01:00
Feifan He
154847c696
vkd3d-shader/msl: Implement VKD3DSIH_GEO.
2024-11-25 20:43:13 +01:00
Feifan He
38d7f8415d
vkd3d-shader/msl: Implement support for VKD3DSPSM_NEG modifiers.
2024-11-25 20:43:13 +01:00
Feifan He
64ea19b7f7
vkd3d-shader/msl: Implement VKD3DSIH_DIV.
2024-11-25 20:43:13 +01:00
Feifan He
b7605f1c34
vkd3d-shader/msl: Implement VKD3DSIH_OR.
2024-11-25 20:43:13 +01:00
Feifan He
f2a32589ea
vkd3d-shader/msl: Implement VKD3DSIH_INE.
2024-11-25 20:43:13 +01:00
Feifan He
a2d56c8bfc
vkd3d-shader/msl: Implement VKD3DSIH_MUL.
2024-11-25 20:43:13 +01:00
Francisco Casas
4f549155c5
vkd3d-shader/hlsl: Store SM4 HLSL_RESOURCE_RESINFOs in the vsir program.
2024-11-24 00:01:03 +01:00
Francisco Casas
c89f503604
vkd3d-shader/hlsl: Store SM4 HLSL_RESOURCE_SAMPLE_INFOs in the vsir program.
2024-11-24 00:00:46 +01:00
Francisco Casas
4382af6e1b
vkd3d-shader/hlsl: Store SM4 HLSL_RESOURCE_GATHERs in the vsir program.
2024-11-23 23:55:07 +01:00
Francisco Casas
42ce821603
vkd3d-shader/hlsl: Store SM4 HLSL_RESOURCE_SAMPLEs in the vsir program.
2024-11-23 23:52:24 +01:00
Francisco Casas
52b81f42eb
vkd3d-shader/hlsl: Store SM4 HLSL_RESOURCE_LOADs in the vsir program.
2024-11-23 23:49:57 +01:00
Feifan He
fd1beedc07
vkd3d-shader/msl: Implement support for VSIR_DIMENSION_VEC4 immediate constants.
2024-11-23 23:43:42 +01:00
Feifan He
68d7470fc2
vkd3d-shader/msl: Implement VKD3DSIH_NEU.
2024-11-23 23:43:42 +01:00
Feifan He
65b0e13a1a
vkd3d-shader/msl: Implement VKD3DSIH_AND.
2024-11-23 23:43:42 +01:00
Feifan He
4add058cd8
vkd3d-shader/msl: Implement support for VKD3DSPSM_ABS modifiers.
2024-11-23 23:43:42 +01:00
Feifan He
5bb7dcaba3
vkd3d-shader/msl: Implement support for VKD3DSPR_IMMCONST registers.
2024-11-23 23:43:42 +01:00
Feifan He
05b9331d0d
vkd3d-shader/msl: Implement VKD3DSIH_ADD.
2024-11-23 23:43:42 +01:00
Nikolay Sivov
b314a9eb84
vkd3d-shader/fx: Remove newlines from the parser error messages.
...
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2024-11-23 23:24:05 +01:00
Nikolay Sivov
3784919213
vkd3d-shader/fx: Implement parsing inline shader blobs.
...
Signed-off-by: Nikolay Sivov <nsivov@codeweavers.com>
2024-11-23 23:21:39 +01:00
Giovanni Mascellani
0f362ab720
vkd3d-shader/ir: Check that tessellation system value registers are consecutive.
2024-11-23 23:19:57 +01:00
Giovanni Mascellani
5894e79064
vkd3d-shader/ir: Check that all tessellation system values appear in the patch constant signature.
2024-11-23 23:19:57 +01:00
Giovanni Mascellani
0245d22c83
vkd3d-shader/ir: Validate index count for LOCALTHREADINDEX registers.
2024-11-23 23:15:40 +01:00
Giovanni Mascellani
050840f493
vkd3d-shader/ir: Validate index count for LOCALTHREADID registers.
2024-11-23 23:15:39 +01:00
Giovanni Mascellani
595fe9a7aa
vkd3d-shader/ir: Validate index count for THREADGROUPID registers.
2024-11-23 23:15:39 +01:00
Giovanni Mascellani
fd9da5db2d
vkd3d-shader/ir: Validate index count for THREADID registers.
2024-11-23 23:15:39 +01:00
Giovanni Mascellani
26251d02a9
vkd3d-shader/ir: Validate index count for TESSCOORD registers.
2024-11-23 23:15:39 +01:00
Giovanni Mascellani
f2659c14a2
vkd3d-shader/ir: Validate index count for JOININSTID registers.
2024-11-23 23:15:39 +01:00
Giovanni Mascellani
808b28b425
vkd3d-shader/ir: Validate index count for FORKINSTID registers.
2024-11-23 23:15:39 +01:00
Giovanni Mascellani
860bb59c89
vkd3d-shader/ir: Validate index count for OUTPOINTID registers.
2024-11-23 23:15:39 +01:00
Giovanni Mascellani
0c3c4e0563
vkd3d-shader/ir: Validate index count for PRIMID registers.
2024-11-23 23:15:39 +01:00
Francisco Casas
64bc0515e0
vkd3d-shader/hlsl: Add special allocation rules for FFACE and SAMPLE.
2024-11-23 23:13:13 +01:00
Francisco Casas
2c15015ec2
tests: Test allocation rules for FFACE and SAMPLE.
...
These seem to have their own interpolation mode.
2024-11-23 23:10:56 +01:00
Francisco Casas
ad5377f995
vkd3d-shader/hlsl: Add special allocation rules for PRIMID, RTINDEX, and VPINDEX.
...
These system values are bound to the same allocation rules as other
semantics: they can share registers with other semantics with the same
interpolation mode and they prefer forming shorter writemasks. However,
for some reason, these don't allow further semantics to share the same
register once allocated, except among themselves.
2024-11-23 23:10:46 +01:00
