2003-03-06 23:23:54 +00:00
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/*
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* i386 emulator main execution loop
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*
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2005-04-06 20:47:48 +00:00
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* Copyright (c) 2003-2005 Fabrice Bellard
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2003-03-06 23:23:54 +00:00
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*
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2003-03-23 20:17:16 +00:00
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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2003-03-06 23:23:54 +00:00
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*
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2003-03-23 20:17:16 +00:00
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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2003-03-06 23:23:54 +00:00
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*
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2003-03-23 20:17:16 +00:00
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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2003-03-06 23:23:54 +00:00
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*/
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2003-06-15 19:51:39 +00:00
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#include "config.h"
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2003-09-30 20:57:29 +00:00
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#include "exec.h"
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2003-04-29 20:40:53 +00:00
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#include "disas.h"
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2003-03-06 23:23:54 +00:00
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2004-04-25 21:21:33 +00:00
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#if !defined(CONFIG_SOFTMMU)
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#undef EAX
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#undef ECX
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#undef EDX
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#undef EBX
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#undef ESP
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#undef EBP
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#undef ESI
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#undef EDI
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#undef EIP
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#include <signal.h>
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#include <sys/ucontext.h>
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#endif
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2003-11-19 22:12:02 +00:00
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int tb_invalidated_flag;
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2003-03-19 00:00:28 +00:00
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//#define DEBUG_EXEC
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2003-03-23 16:49:39 +00:00
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//#define DEBUG_SIGNAL
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2003-03-06 23:23:54 +00:00
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2006-10-22 00:18:54 +00:00
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#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
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2003-06-15 19:51:39 +00:00
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/* XXX: unify with i386 target */
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void cpu_loop_exit(void)
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{
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longjmp(env->jmp_env, 1);
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}
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#endif
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2006-10-22 00:18:54 +00:00
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#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
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2005-07-02 14:31:34 +00:00
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#define reg_T2
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#endif
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2003-06-15 19:51:39 +00:00
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2004-04-25 21:21:33 +00:00
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/* exit the current TB from a signal handler. The host registers are
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restored in a state compatible with the CPU emulator
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*/
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void cpu_resume_from_signal(CPUState *env1, void *puc)
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{
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#if !defined(CONFIG_SOFTMMU)
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struct ucontext *uc = puc;
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#endif
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env = env1;
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/* XXX: restore cpu registers saved in host registers */
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#if !defined(CONFIG_SOFTMMU)
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if (puc) {
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/* XXX: use siglongjmp ? */
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sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
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}
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#endif
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longjmp(env->jmp_env, 1);
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}
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2005-11-20 10:35:40 +00:00
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static TranslationBlock *tb_find_slow(target_ulong pc,
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target_ulong cs_base,
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unsigned int flags)
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{
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TranslationBlock *tb, **ptb1;
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int code_gen_size;
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unsigned int h;
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target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
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uint8_t *tc_ptr;
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spin_lock(&tb_lock);
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tb_invalidated_flag = 0;
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regs_to_env(); /* XXX: do it just before cpu_gen_code() */
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/* find translated block using physical mappings */
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phys_pc = get_phys_addr_code(env, pc);
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phys_page1 = phys_pc & TARGET_PAGE_MASK;
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phys_page2 = -1;
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h = tb_phys_hash_func(phys_pc);
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ptb1 = &tb_phys_hash[h];
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for(;;) {
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tb = *ptb1;
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if (!tb)
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goto not_found;
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if (tb->pc == pc &&
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tb->page_addr[0] == phys_page1 &&
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tb->cs_base == cs_base &&
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tb->flags == flags) {
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/* check next page if needed */
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if (tb->page_addr[1] != -1) {
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virt_page2 = (pc & TARGET_PAGE_MASK) +
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TARGET_PAGE_SIZE;
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phys_page2 = get_phys_addr_code(env, virt_page2);
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if (tb->page_addr[1] == phys_page2)
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goto found;
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} else {
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goto found;
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}
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}
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ptb1 = &tb->phys_hash_next;
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}
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not_found:
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/* if no translated code available, then translate it now */
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tb = tb_alloc(pc);
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if (!tb) {
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/* flush must be done */
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tb_flush(env);
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/* cannot fail at this point */
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tb = tb_alloc(pc);
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/* don't forget to invalidate previous TB info */
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2005-12-19 01:42:32 +00:00
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tb_invalidated_flag = 1;
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2005-11-20 10:35:40 +00:00
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}
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tc_ptr = code_gen_ptr;
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tb->tc_ptr = tc_ptr;
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tb->cs_base = cs_base;
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tb->flags = flags;
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cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
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code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
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/* check next page if needed */
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virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
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phys_page2 = -1;
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if ((pc & TARGET_PAGE_MASK) != virt_page2) {
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phys_page2 = get_phys_addr_code(env, virt_page2);
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}
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tb_link_phys(tb, phys_pc, phys_page2);
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found:
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/* we add the TB in the virtual pc hash table */
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env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
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spin_unlock(&tb_lock);
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return tb;
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}
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static inline TranslationBlock *tb_find_fast(void)
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{
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TranslationBlock *tb;
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target_ulong cs_base, pc;
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unsigned int flags;
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/* we record a subset of the CPU state. It will
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always be the same before a given translated block
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is executed. */
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#if defined(TARGET_I386)
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flags = env->hflags;
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flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
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cs_base = env->segs[R_CS].base;
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pc = cs_base + env->eip;
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#elif defined(TARGET_ARM)
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flags = env->thumb | (env->vfp.vec_len << 1)
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2005-11-26 10:38:39 +00:00
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| (env->vfp.vec_stride << 4);
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if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
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flags |= (1 << 6);
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2006-02-20 00:33:36 +00:00
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if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
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flags |= (1 << 7);
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2005-11-20 10:35:40 +00:00
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cs_base = 0;
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pc = env->regs[15];
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#elif defined(TARGET_SPARC)
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#ifdef TARGET_SPARC64
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2006-06-26 19:53:29 +00:00
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// Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
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flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
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| (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
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2005-11-20 10:35:40 +00:00
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#else
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2006-06-26 19:53:29 +00:00
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// FPU enable . MMU enabled . MMU no-fault . Supervisor
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flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
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| env->psrs;
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2005-11-20 10:35:40 +00:00
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#endif
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cs_base = env->npc;
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pc = env->pc;
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#elif defined(TARGET_PPC)
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flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
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(msr_se << MSR_SE) | (msr_le << MSR_LE);
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cs_base = 0;
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pc = env->nip;
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#elif defined(TARGET_MIPS)
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2006-03-11 16:23:39 +00:00
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flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
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2005-11-26 18:43:28 +00:00
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cs_base = 0;
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2005-11-20 10:35:40 +00:00
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pc = env->PC;
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2006-10-22 00:18:54 +00:00
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#elif defined(TARGET_M68K)
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flags = env->fpcr & M68K_FPCR_PREC;
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cs_base = 0;
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pc = env->pc;
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2006-04-27 21:07:38 +00:00
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#elif defined(TARGET_SH4)
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flags = env->sr & (SR_MD | SR_RB);
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cs_base = 0; /* XXXXX */
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pc = env->pc;
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2005-11-20 10:35:40 +00:00
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#else
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#error unsupported CPU
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#endif
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tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
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if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
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tb->flags != flags, 0)) {
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tb = tb_find_slow(pc, cs_base, flags);
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2005-12-19 01:42:32 +00:00
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/* Note: we do it here to avoid a gcc bug on Mac OS X when
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doing it in tb_find_slow */
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if (tb_invalidated_flag) {
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/* as some TB could have been invalidated because
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of memory exceptions while generating the code, we
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must recompute the hash index here */
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T0 = 0;
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}
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2005-11-20 10:35:40 +00:00
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}
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return tb;
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}
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2003-03-06 23:23:54 +00:00
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/* main execution loop */
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2003-06-15 19:51:39 +00:00
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int cpu_exec(CPUState *env1)
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2003-03-06 23:23:54 +00:00
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{
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2007-02-04 13:37:44 +00:00
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#define DECLARE_HOST_REGS 1
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#include "hostregs_helper.h"
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#if defined(TARGET_SPARC)
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2005-07-02 14:31:34 +00:00
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#if defined(reg_REGWPTR)
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uint32_t *saved_regwptr;
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#endif
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#endif
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2006-06-14 17:32:25 +00:00
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#if defined(__sparc__) && !defined(HOST_SOLARIS)
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2007-02-02 03:57:09 +00:00
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int saved_i7;
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target_ulong tmp_T0;
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2003-03-20 22:33:23 +00:00
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#endif
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2005-11-20 10:35:40 +00:00
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int ret, interrupt_request;
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2003-03-06 23:23:54 +00:00
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void (*gen_func)(void);
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2005-11-20 10:35:40 +00:00
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TranslationBlock *tb;
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2005-01-03 23:35:10 +00:00
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uint8_t *tc_ptr;
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2003-06-09 15:28:00 +00:00
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2005-11-23 21:02:53 +00:00
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#if defined(TARGET_I386)
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/* handle exit of HALTED state */
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if (env1->hflags & HF_HALTED_MASK) {
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/* disable halt condition */
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if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
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(env1->eflags & IF_MASK)) {
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env1->hflags &= ~HF_HALTED_MASK;
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} else {
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return EXCP_HALTED;
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2005-11-23 22:05:28 +00:00
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}
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}
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#elif defined(TARGET_PPC)
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2005-11-26 20:15:14 +00:00
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if (env1->halted) {
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2005-11-23 22:05:28 +00:00
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if (env1->msr[MSR_EE] &&
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(env1->interrupt_request &
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(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
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2005-11-26 20:15:14 +00:00
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env1->halted = 0;
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2005-11-23 22:05:28 +00:00
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} else {
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return EXCP_HALTED;
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2005-11-23 21:02:53 +00:00
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}
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}
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2005-12-05 20:31:52 +00:00
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#elif defined(TARGET_SPARC)
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if (env1->halted) {
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if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
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(env1->psret != 0)) {
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env1->halted = 0;
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} else {
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return EXCP_HALTED;
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}
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}
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2005-11-26 10:46:39 +00:00
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#elif defined(TARGET_ARM)
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if (env1->halted) {
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/* An interrupt wakes the CPU even if the I and F CPSR bits are
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set. */
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if (env1->interrupt_request
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& (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
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env1->halted = 0;
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} else {
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return EXCP_HALTED;
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}
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}
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2005-12-05 19:59:05 +00:00
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#elif defined(TARGET_MIPS)
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if (env1->halted) {
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if (env1->interrupt_request &
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(CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
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env1->halted = 0;
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} else {
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return EXCP_HALTED;
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}
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}
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2005-11-23 21:02:53 +00:00
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#endif
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2005-11-21 23:25:50 +00:00
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cpu_single_env = env1;
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2003-03-06 23:23:54 +00:00
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/* first we save global registers */
|
2007-02-04 13:37:44 +00:00
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#define SAVE_HOST_REGS 1
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#include "hostregs_helper.h"
|
2005-01-03 23:35:10 +00:00
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env = env1;
|
2006-06-14 17:32:25 +00:00
|
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|
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
2003-06-15 19:51:39 +00:00
|
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/* we also save i7 because longjmp may not restore it */
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|
|
asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
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#endif
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#if defined(TARGET_I386)
|
2004-10-12 22:01:28 +00:00
|
|
|
env_to_regs();
|
2003-03-23 16:49:39 +00:00
|
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|
/* put eflags in CPU temporary format */
|
2003-03-29 16:52:44 +00:00
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|
|
CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
|
|
|
DF = 1 - (2 * ((env->eflags >> 10) & 1));
|
2003-03-23 16:49:39 +00:00
|
|
|
CC_OP = CC_OP_EFLAGS;
|
2003-03-29 16:52:44 +00:00
|
|
|
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
2003-06-15 19:51:39 +00:00
|
|
|
#elif defined(TARGET_ARM)
|
2003-09-30 20:57:29 +00:00
|
|
|
#elif defined(TARGET_SPARC)
|
2005-07-02 14:31:34 +00:00
|
|
|
#if defined(reg_REGWPTR)
|
|
|
|
saved_regwptr = REGWPTR;
|
|
|
|
#endif
|
2003-11-23 17:05:30 +00:00
|
|
|
#elif defined(TARGET_PPC)
|
2006-10-22 00:18:54 +00:00
|
|
|
#elif defined(TARGET_M68K)
|
|
|
|
env->cc_op = CC_OP_FLAGS;
|
|
|
|
env->cc_dest = env->sr & 0xf;
|
|
|
|
env->cc_x = (env->sr >> 4) & 1;
|
2005-07-02 14:58:51 +00:00
|
|
|
#elif defined(TARGET_MIPS)
|
2006-04-27 21:07:38 +00:00
|
|
|
#elif defined(TARGET_SH4)
|
|
|
|
/* XXXXX */
|
2003-06-15 19:51:39 +00:00
|
|
|
#else
|
|
|
|
#error unsupported target CPU
|
|
|
|
#endif
|
2003-06-24 13:22:59 +00:00
|
|
|
env->exception_index = -1;
|
2003-05-10 13:13:54 +00:00
|
|
|
|
2003-03-06 23:23:54 +00:00
|
|
|
/* prepare setjmp context for exception handling */
|
2003-06-24 13:22:59 +00:00
|
|
|
for(;;) {
|
|
|
|
if (setjmp(env->jmp_env) == 0) {
|
2004-02-03 23:35:10 +00:00
|
|
|
env->current_tb = NULL;
|
2003-06-24 13:22:59 +00:00
|
|
|
/* if an exception is pending, we execute it here */
|
|
|
|
if (env->exception_index >= 0) {
|
|
|
|
if (env->exception_index >= EXCP_INTERRUPT) {
|
|
|
|
/* exit request from the cpu execution loop */
|
|
|
|
ret = env->exception_index;
|
|
|
|
break;
|
|
|
|
} else if (env->user_mode_only) {
|
|
|
|
/* if user mode only, we simulate a fake exception
|
2006-12-07 18:28:42 +00:00
|
|
|
which will be handled outside the cpu execution
|
2003-06-24 13:22:59 +00:00
|
|
|
loop */
|
2003-06-25 16:12:37 +00:00
|
|
|
#if defined(TARGET_I386)
|
2003-06-24 13:22:59 +00:00
|
|
|
do_interrupt_user(env->exception_index,
|
|
|
|
env->exception_is_int,
|
|
|
|
env->error_code,
|
|
|
|
env->exception_next_eip);
|
2003-06-25 16:12:37 +00:00
|
|
|
#endif
|
2003-06-24 13:22:59 +00:00
|
|
|
ret = env->exception_index;
|
|
|
|
break;
|
|
|
|
} else {
|
2003-06-25 16:12:37 +00:00
|
|
|
#if defined(TARGET_I386)
|
2003-06-24 13:22:59 +00:00
|
|
|
/* simulate a real cpu exception. On i386, it can
|
|
|
|
trigger new exceptions, but we do not handle
|
|
|
|
double or triple faults yet. */
|
|
|
|
do_interrupt(env->exception_index,
|
|
|
|
env->exception_is_int,
|
|
|
|
env->error_code,
|
2003-08-20 21:34:35 +00:00
|
|
|
env->exception_next_eip, 0);
|
2004-01-04 23:53:18 +00:00
|
|
|
#elif defined(TARGET_PPC)
|
|
|
|
do_interrupt(env);
|
2005-07-02 14:58:51 +00:00
|
|
|
#elif defined(TARGET_MIPS)
|
|
|
|
do_interrupt(env);
|
2004-09-30 22:22:08 +00:00
|
|
|
#elif defined(TARGET_SPARC)
|
2005-02-13 19:02:07 +00:00
|
|
|
do_interrupt(env->exception_index);
|
2005-11-26 10:38:39 +00:00
|
|
|
#elif defined(TARGET_ARM)
|
|
|
|
do_interrupt(env);
|
2006-04-27 21:07:38 +00:00
|
|
|
#elif defined(TARGET_SH4)
|
|
|
|
do_interrupt(env);
|
2003-06-25 16:12:37 +00:00
|
|
|
#endif
|
2003-06-24 13:22:59 +00:00
|
|
|
}
|
|
|
|
env->exception_index = -1;
|
2005-02-10 22:05:51 +00:00
|
|
|
}
|
|
|
|
#ifdef USE_KQEMU
|
|
|
|
if (kqemu_is_ok(env) && env->interrupt_request == 0) {
|
|
|
|
int ret;
|
|
|
|
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
|
|
|
|
ret = kqemu_cpu_exec(env);
|
|
|
|
/* put eflags in CPU temporary format */
|
|
|
|
CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
|
|
|
DF = 1 - (2 * ((env->eflags >> 10) & 1));
|
|
|
|
CC_OP = CC_OP_EFLAGS;
|
|
|
|
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
|
|
|
if (ret == 1) {
|
|
|
|
/* exception */
|
|
|
|
longjmp(env->jmp_env, 1);
|
|
|
|
} else if (ret == 2) {
|
|
|
|
/* softmmu execution needed */
|
|
|
|
} else {
|
|
|
|
if (env->interrupt_request != 0) {
|
|
|
|
/* hardware interrupt will be executed just after */
|
|
|
|
} else {
|
|
|
|
/* otherwise, we restart */
|
|
|
|
longjmp(env->jmp_env, 1);
|
|
|
|
}
|
|
|
|
}
|
2003-06-24 13:22:59 +00:00
|
|
|
}
|
2005-02-10 22:05:51 +00:00
|
|
|
#endif
|
|
|
|
|
2003-06-24 13:22:59 +00:00
|
|
|
T0 = 0; /* force lookup of first TB */
|
|
|
|
for(;;) {
|
2006-06-14 17:32:25 +00:00
|
|
|
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
2003-06-24 13:22:59 +00:00
|
|
|
/* g1 can be modified by some libc? functions */
|
|
|
|
tmp_T0 = T0;
|
2003-06-09 15:28:00 +00:00
|
|
|
#endif
|
2003-06-30 13:12:32 +00:00
|
|
|
interrupt_request = env->interrupt_request;
|
2003-08-21 23:25:21 +00:00
|
|
|
if (__builtin_expect(interrupt_request, 0)) {
|
2007-03-16 23:58:11 +00:00
|
|
|
if (interrupt_request & CPU_INTERRUPT_DEBUG) {
|
|
|
|
env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
|
|
|
|
env->exception_index = EXCP_DEBUG;
|
|
|
|
cpu_loop_exit();
|
|
|
|
}
|
2003-06-30 13:12:32 +00:00
|
|
|
#if defined(TARGET_I386)
|
2006-09-24 18:41:56 +00:00
|
|
|
if ((interrupt_request & CPU_INTERRUPT_SMI) &&
|
|
|
|
!(env->hflags & HF_SMM_MASK)) {
|
|
|
|
env->interrupt_request &= ~CPU_INTERRUPT_SMI;
|
|
|
|
do_smm_enter();
|
|
|
|
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
|
|
|
tmp_T0 = 0;
|
|
|
|
#else
|
|
|
|
T0 = 0;
|
|
|
|
#endif
|
|
|
|
} else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
2003-08-20 23:02:09 +00:00
|
|
|
(env->eflags & IF_MASK) &&
|
|
|
|
!(env->hflags & HF_INHIBIT_IRQ_MASK)) {
|
2003-06-30 13:12:32 +00:00
|
|
|
int intno;
|
2004-04-25 21:21:33 +00:00
|
|
|
env->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
2004-04-12 20:39:29 +00:00
|
|
|
intno = cpu_get_pic_interrupt(env);
|
2004-03-21 17:06:25 +00:00
|
|
|
if (loglevel & CPU_LOG_TB_IN_ASM) {
|
2003-06-30 13:12:32 +00:00
|
|
|
fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
|
|
|
|
}
|
2003-08-20 21:34:35 +00:00
|
|
|
do_interrupt(intno, 0, 0, 0, 1);
|
2003-06-30 23:18:22 +00:00
|
|
|
/* ensure that no TB jump will be modified as
|
|
|
|
the program flow was changed */
|
2006-06-14 17:32:25 +00:00
|
|
|
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
2003-06-30 23:18:22 +00:00
|
|
|
tmp_T0 = 0;
|
|
|
|
#else
|
|
|
|
T0 = 0;
|
|
|
|
#endif
|
2003-06-30 13:12:32 +00:00
|
|
|
}
|
2004-01-04 23:53:18 +00:00
|
|
|
#elif defined(TARGET_PPC)
|
2004-05-21 12:59:32 +00:00
|
|
|
#if 0
|
|
|
|
if ((interrupt_request & CPU_INTERRUPT_RESET)) {
|
|
|
|
cpu_ppc_reset(env);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
if (msr_ee != 0) {
|
2005-11-20 10:35:40 +00:00
|
|
|
if ((interrupt_request & CPU_INTERRUPT_HARD)) {
|
2004-05-21 12:59:32 +00:00
|
|
|
/* Raise it */
|
|
|
|
env->exception_index = EXCP_EXTERNAL;
|
|
|
|
env->error_code = 0;
|
2004-01-04 23:53:18 +00:00
|
|
|
do_interrupt(env);
|
2005-11-20 10:35:40 +00:00
|
|
|
env->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
2006-06-14 17:32:25 +00:00
|
|
|
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
2005-11-20 10:35:40 +00:00
|
|
|
tmp_T0 = 0;
|
|
|
|
#else
|
|
|
|
T0 = 0;
|
|
|
|
#endif
|
|
|
|
} else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
|
|
|
|
/* Raise it */
|
|
|
|
env->exception_index = EXCP_DECR;
|
|
|
|
env->error_code = 0;
|
|
|
|
do_interrupt(env);
|
2004-05-21 12:59:32 +00:00
|
|
|
env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
|
2006-06-14 17:32:25 +00:00
|
|
|
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
2005-11-20 10:35:40 +00:00
|
|
|
tmp_T0 = 0;
|
|
|
|
#else
|
|
|
|
T0 = 0;
|
|
|
|
#endif
|
|
|
|
}
|
2004-01-04 23:53:18 +00:00
|
|
|
}
|
2005-07-02 14:58:51 +00:00
|
|
|
#elif defined(TARGET_MIPS)
|
|
|
|
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
|
|
(env->CP0_Status & (1 << CP0St_IE)) &&
|
2005-08-21 09:43:38 +00:00
|
|
|
(env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
|
2005-07-02 14:58:51 +00:00
|
|
|
!(env->hflags & MIPS_HFLAG_EXL) &&
|
|
|
|
!(env->hflags & MIPS_HFLAG_ERL) &&
|
|
|
|
!(env->hflags & MIPS_HFLAG_DM)) {
|
|
|
|
/* Raise it */
|
|
|
|
env->exception_index = EXCP_EXT_INTERRUPT;
|
|
|
|
env->error_code = 0;
|
|
|
|
do_interrupt(env);
|
2006-06-14 17:32:25 +00:00
|
|
|
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
2005-11-20 10:35:40 +00:00
|
|
|
tmp_T0 = 0;
|
|
|
|
#else
|
|
|
|
T0 = 0;
|
|
|
|
#endif
|
2005-07-02 14:58:51 +00:00
|
|
|
}
|
2004-09-30 22:22:08 +00:00
|
|
|
#elif defined(TARGET_SPARC)
|
2005-04-06 20:47:48 +00:00
|
|
|
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
|
|
(env->psret != 0)) {
|
|
|
|
int pil = env->interrupt_index & 15;
|
|
|
|
int type = env->interrupt_index & 0xf0;
|
|
|
|
|
|
|
|
if (((type == TT_EXTINT) &&
|
|
|
|
(pil == 15 || pil > env->psrpil)) ||
|
|
|
|
type != TT_EXTINT) {
|
|
|
|
env->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
|
|
|
do_interrupt(env->interrupt_index);
|
|
|
|
env->interrupt_index = 0;
|
2006-06-14 17:32:25 +00:00
|
|
|
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
2005-11-20 10:35:40 +00:00
|
|
|
tmp_T0 = 0;
|
|
|
|
#else
|
|
|
|
T0 = 0;
|
|
|
|
#endif
|
2005-04-06 20:47:48 +00:00
|
|
|
}
|
2004-09-30 22:22:08 +00:00
|
|
|
} else if (interrupt_request & CPU_INTERRUPT_TIMER) {
|
|
|
|
//do_interrupt(0, 0, 0, 0, 0);
|
|
|
|
env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
|
2005-12-05 20:31:52 +00:00
|
|
|
} else if (interrupt_request & CPU_INTERRUPT_HALT) {
|
2006-09-20 20:30:57 +00:00
|
|
|
env->interrupt_request &= ~CPU_INTERRUPT_HALT;
|
|
|
|
env->halted = 1;
|
|
|
|
env->exception_index = EXCP_HLT;
|
|
|
|
cpu_loop_exit();
|
2005-12-05 20:31:52 +00:00
|
|
|
}
|
2005-11-26 10:38:39 +00:00
|
|
|
#elif defined(TARGET_ARM)
|
|
|
|
if (interrupt_request & CPU_INTERRUPT_FIQ
|
|
|
|
&& !(env->uncached_cpsr & CPSR_F)) {
|
|
|
|
env->exception_index = EXCP_FIQ;
|
|
|
|
do_interrupt(env);
|
|
|
|
}
|
|
|
|
if (interrupt_request & CPU_INTERRUPT_HARD
|
|
|
|
&& !(env->uncached_cpsr & CPSR_I)) {
|
|
|
|
env->exception_index = EXCP_IRQ;
|
|
|
|
do_interrupt(env);
|
|
|
|
}
|
2006-04-27 21:07:38 +00:00
|
|
|
#elif defined(TARGET_SH4)
|
|
|
|
/* XXXXX */
|
2003-06-30 13:12:32 +00:00
|
|
|
#endif
|
2006-05-22 22:03:52 +00:00
|
|
|
/* Don't use the cached interupt_request value,
|
|
|
|
do_interrupt may have updated the EXITTB flag. */
|
2005-11-26 10:38:39 +00:00
|
|
|
if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
|
2004-02-16 21:58:54 +00:00
|
|
|
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
|
|
|
|
/* ensure that no TB jump will be modified as
|
|
|
|
the program flow was changed */
|
2006-06-14 17:32:25 +00:00
|
|
|
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
2004-02-16 21:58:54 +00:00
|
|
|
tmp_T0 = 0;
|
|
|
|
#else
|
|
|
|
T0 = 0;
|
|
|
|
#endif
|
|
|
|
}
|
2003-06-30 13:12:32 +00:00
|
|
|
if (interrupt_request & CPU_INTERRUPT_EXIT) {
|
|
|
|
env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
|
|
|
|
env->exception_index = EXCP_INTERRUPT;
|
|
|
|
cpu_loop_exit();
|
|
|
|
}
|
2003-06-24 13:22:59 +00:00
|
|
|
}
|
2003-03-06 23:23:54 +00:00
|
|
|
#ifdef DEBUG_EXEC
|
2005-11-26 10:38:39 +00:00
|
|
|
if ((loglevel & CPU_LOG_TB_CPU)) {
|
2003-06-15 19:51:39 +00:00
|
|
|
#if defined(TARGET_I386)
|
2003-06-24 13:22:59 +00:00
|
|
|
/* restore flags in standard format */
|
2005-04-26 19:33:35 +00:00
|
|
|
#ifdef reg_EAX
|
2003-06-24 13:22:59 +00:00
|
|
|
env->regs[R_EAX] = EAX;
|
2005-04-26 19:33:35 +00:00
|
|
|
#endif
|
|
|
|
#ifdef reg_EBX
|
2003-06-24 13:22:59 +00:00
|
|
|
env->regs[R_EBX] = EBX;
|
2005-04-26 19:33:35 +00:00
|
|
|
#endif
|
|
|
|
#ifdef reg_ECX
|
2003-06-24 13:22:59 +00:00
|
|
|
env->regs[R_ECX] = ECX;
|
2005-04-26 19:33:35 +00:00
|
|
|
#endif
|
|
|
|
#ifdef reg_EDX
|
2003-06-24 13:22:59 +00:00
|
|
|
env->regs[R_EDX] = EDX;
|
2005-04-26 19:33:35 +00:00
|
|
|
#endif
|
|
|
|
#ifdef reg_ESI
|
2003-06-24 13:22:59 +00:00
|
|
|
env->regs[R_ESI] = ESI;
|
2005-04-26 19:33:35 +00:00
|
|
|
#endif
|
|
|
|
#ifdef reg_EDI
|
2003-06-24 13:22:59 +00:00
|
|
|
env->regs[R_EDI] = EDI;
|
2005-04-26 19:33:35 +00:00
|
|
|
#endif
|
|
|
|
#ifdef reg_EBP
|
2003-06-24 13:22:59 +00:00
|
|
|
env->regs[R_EBP] = EBP;
|
2005-04-26 19:33:35 +00:00
|
|
|
#endif
|
|
|
|
#ifdef reg_ESP
|
2003-06-24 13:22:59 +00:00
|
|
|
env->regs[R_ESP] = ESP;
|
2005-04-26 19:33:35 +00:00
|
|
|
#endif
|
2003-06-24 13:22:59 +00:00
|
|
|
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
|
2004-10-09 18:08:01 +00:00
|
|
|
cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
|
2003-06-24 13:22:59 +00:00
|
|
|
env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
|
2003-06-15 19:51:39 +00:00
|
|
|
#elif defined(TARGET_ARM)
|
2004-10-09 18:08:01 +00:00
|
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
2003-09-30 20:57:29 +00:00
|
|
|
#elif defined(TARGET_SPARC)
|
2005-07-02 14:31:34 +00:00
|
|
|
REGWPTR = env->regbase + (env->cwp * 16);
|
|
|
|
env->regwptr = REGWPTR;
|
|
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
2003-11-23 17:05:30 +00:00
|
|
|
#elif defined(TARGET_PPC)
|
2004-10-09 18:08:01 +00:00
|
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
2006-10-22 00:18:54 +00:00
|
|
|
#elif defined(TARGET_M68K)
|
|
|
|
cpu_m68k_flush_flags(env, env->cc_op);
|
|
|
|
env->cc_op = CC_OP_FLAGS;
|
|
|
|
env->sr = (env->sr & 0xffe0)
|
|
|
|
| env->cc_dest | (env->cc_x << 4);
|
|
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
2005-07-02 14:58:51 +00:00
|
|
|
#elif defined(TARGET_MIPS)
|
|
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
2006-04-27 21:07:38 +00:00
|
|
|
#elif defined(TARGET_SH4)
|
|
|
|
cpu_dump_state(env, logfile, fprintf, 0);
|
2003-06-15 19:51:39 +00:00
|
|
|
#else
|
|
|
|
#error unsupported target CPU
|
|
|
|
#endif
|
2003-06-24 13:22:59 +00:00
|
|
|
}
|
2003-03-06 23:23:54 +00:00
|
|
|
#endif
|
2005-11-20 10:35:40 +00:00
|
|
|
tb = tb_find_fast();
|
2003-05-10 13:13:54 +00:00
|
|
|
#ifdef DEBUG_EXEC
|
2005-01-30 22:41:54 +00:00
|
|
|
if ((loglevel & CPU_LOG_EXEC)) {
|
2005-01-03 23:35:10 +00:00
|
|
|
fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
|
|
|
|
(long)tb->tc_ptr, tb->pc,
|
|
|
|
lookup_symbol(tb->pc));
|
2003-06-24 13:22:59 +00:00
|
|
|
}
|
2003-05-10 13:13:54 +00:00
|
|
|
#endif
|
2006-06-14 17:32:25 +00:00
|
|
|
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
2003-06-24 13:22:59 +00:00
|
|
|
T0 = tmp_T0;
|
2003-06-09 15:28:00 +00:00
|
|
|
#endif
|
2005-11-20 10:35:40 +00:00
|
|
|
/* see if we can patch the calling TB. When the TB
|
|
|
|
spans two pages, we cannot safely do a direct
|
|
|
|
jump. */
|
2005-01-03 23:35:10 +00:00
|
|
|
{
|
2005-11-20 10:35:40 +00:00
|
|
|
if (T0 != 0 &&
|
2006-02-08 22:43:39 +00:00
|
|
|
#if USE_KQEMU
|
|
|
|
(env->kqemu_enabled != 2) &&
|
|
|
|
#endif
|
2005-11-20 10:35:40 +00:00
|
|
|
tb->page_addr[1] == -1
|
2004-02-16 21:58:54 +00:00
|
|
|
#if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
|
|
|
&& (tb->cflags & CF_CODE_COPY) ==
|
|
|
|
(((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
|
|
|
|
#endif
|
|
|
|
) {
|
2003-06-24 13:22:59 +00:00
|
|
|
spin_lock(&tb_lock);
|
2005-01-03 23:35:10 +00:00
|
|
|
tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
|
2004-02-25 23:19:55 +00:00
|
|
|
#if defined(USE_CODE_COPY)
|
|
|
|
/* propagates the FP use info */
|
|
|
|
((TranslationBlock *)(T0 & ~3))->cflags |=
|
|
|
|
(tb->cflags & CF_FP_USED);
|
|
|
|
#endif
|
2003-06-24 13:22:59 +00:00
|
|
|
spin_unlock(&tb_lock);
|
|
|
|
}
|
2005-01-03 23:35:10 +00:00
|
|
|
}
|
2003-06-24 13:22:59 +00:00
|
|
|
tc_ptr = tb->tc_ptr;
|
2003-06-25 16:12:37 +00:00
|
|
|
env->current_tb = tb;
|
2003-06-24 13:22:59 +00:00
|
|
|
/* execute the generated code */
|
|
|
|
gen_func = (void *)tc_ptr;
|
2003-06-09 15:28:00 +00:00
|
|
|
#if defined(__sparc__)
|
2003-06-24 13:22:59 +00:00
|
|
|
__asm__ __volatile__("call %0\n\t"
|
|
|
|
"mov %%o7,%%i0"
|
|
|
|
: /* no outputs */
|
|
|
|
: "r" (gen_func)
|
2006-06-14 17:32:25 +00:00
|
|
|
: "i0", "i1", "i2", "i3", "i4", "i5",
|
2007-03-19 20:39:49 +00:00
|
|
|
"o0", "o1", "o2", "o3", "o4", "o5",
|
2006-06-14 17:32:25 +00:00
|
|
|
"l0", "l1", "l2", "l3", "l4", "l5",
|
|
|
|
"l6", "l7");
|
2003-06-09 15:28:00 +00:00
|
|
|
#elif defined(__arm__)
|
2003-06-24 13:22:59 +00:00
|
|
|
asm volatile ("mov pc, %0\n\t"
|
|
|
|
".global exec_loop\n\t"
|
|
|
|
"exec_loop:\n\t"
|
|
|
|
: /* no outputs */
|
|
|
|
: "r" (gen_func)
|
|
|
|
: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
|
2004-02-16 21:58:54 +00:00
|
|
|
#elif defined(TARGET_I386) && defined(USE_CODE_COPY)
|
|
|
|
{
|
|
|
|
if (!(tb->cflags & CF_CODE_COPY)) {
|
2004-02-25 23:19:55 +00:00
|
|
|
if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
|
|
|
|
save_native_fp_state(env);
|
|
|
|
}
|
2004-02-16 21:58:54 +00:00
|
|
|
gen_func();
|
|
|
|
} else {
|
2004-02-25 23:19:55 +00:00
|
|
|
if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
|
|
|
|
restore_native_fp_state(env);
|
|
|
|
}
|
2004-02-16 21:58:54 +00:00
|
|
|
/* we work with native eflags */
|
|
|
|
CC_SRC = cc_table[CC_OP].compute_all();
|
|
|
|
CC_OP = CC_OP_EFLAGS;
|
|
|
|
asm(".globl exec_loop\n"
|
|
|
|
"\n"
|
|
|
|
"debug1:\n"
|
|
|
|
" pushl %%ebp\n"
|
|
|
|
" fs movl %10, %9\n"
|
|
|
|
" fs movl %11, %%eax\n"
|
|
|
|
" andl $0x400, %%eax\n"
|
|
|
|
" fs orl %8, %%eax\n"
|
|
|
|
" pushl %%eax\n"
|
|
|
|
" popf\n"
|
|
|
|
" fs movl %%esp, %12\n"
|
|
|
|
" fs movl %0, %%eax\n"
|
|
|
|
" fs movl %1, %%ecx\n"
|
|
|
|
" fs movl %2, %%edx\n"
|
|
|
|
" fs movl %3, %%ebx\n"
|
|
|
|
" fs movl %4, %%esp\n"
|
|
|
|
" fs movl %5, %%ebp\n"
|
|
|
|
" fs movl %6, %%esi\n"
|
|
|
|
" fs movl %7, %%edi\n"
|
|
|
|
" fs jmp *%9\n"
|
|
|
|
"exec_loop:\n"
|
|
|
|
" fs movl %%esp, %4\n"
|
|
|
|
" fs movl %12, %%esp\n"
|
|
|
|
" fs movl %%eax, %0\n"
|
|
|
|
" fs movl %%ecx, %1\n"
|
|
|
|
" fs movl %%edx, %2\n"
|
|
|
|
" fs movl %%ebx, %3\n"
|
|
|
|
" fs movl %%ebp, %5\n"
|
|
|
|
" fs movl %%esi, %6\n"
|
|
|
|
" fs movl %%edi, %7\n"
|
|
|
|
" pushf\n"
|
|
|
|
" popl %%eax\n"
|
|
|
|
" movl %%eax, %%ecx\n"
|
|
|
|
" andl $0x400, %%ecx\n"
|
|
|
|
" shrl $9, %%ecx\n"
|
|
|
|
" andl $0x8d5, %%eax\n"
|
|
|
|
" fs movl %%eax, %8\n"
|
|
|
|
" movl $1, %%eax\n"
|
|
|
|
" subl %%ecx, %%eax\n"
|
|
|
|
" fs movl %%eax, %11\n"
|
|
|
|
" fs movl %9, %%ebx\n" /* get T0 value */
|
|
|
|
" popl %%ebp\n"
|
|
|
|
:
|
|
|
|
: "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
|
|
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[1])),
|
|
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[2])),
|
|
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[3])),
|
|
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[4])),
|
|
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[5])),
|
|
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[6])),
|
|
|
|
"m" (*(uint8_t *)offsetof(CPUState, regs[7])),
|
|
|
|
"m" (*(uint8_t *)offsetof(CPUState, cc_src)),
|
|
|
|
"m" (*(uint8_t *)offsetof(CPUState, tmp0)),
|
|
|
|
"a" (gen_func),
|
|
|
|
"m" (*(uint8_t *)offsetof(CPUState, df)),
|
|
|
|
"m" (*(uint8_t *)offsetof(CPUState, saved_esp))
|
|
|
|
: "%ecx", "%edx"
|
|
|
|
);
|
|
|
|
}
|
|
|
|
}
|
2005-04-07 22:20:31 +00:00
|
|
|
#elif defined(__ia64)
|
|
|
|
struct fptr {
|
|
|
|
void *ip;
|
|
|
|
void *gp;
|
|
|
|
} fp;
|
|
|
|
|
|
|
|
fp.ip = tc_ptr;
|
|
|
|
fp.gp = code_gen_buffer + 2 * (1 << 20);
|
|
|
|
(*(void (*)(void)) &fp)();
|
2003-05-13 18:59:59 +00:00
|
|
|
#else
|
2003-06-24 13:22:59 +00:00
|
|
|
gen_func();
|
2003-05-13 18:59:59 +00:00
|
|
|
#endif
|
2003-06-25 16:12:37 +00:00
|
|
|
env->current_tb = NULL;
|
2003-08-10 21:48:43 +00:00
|
|
|
/* reset soft MMU for next block (it can currently
|
|
|
|
only be set by a memory fault) */
|
|
|
|
#if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
|
2003-08-20 23:02:09 +00:00
|
|
|
if (env->hflags & HF_SOFTMMU_MASK) {
|
|
|
|
env->hflags &= ~HF_SOFTMMU_MASK;
|
2003-08-10 21:48:43 +00:00
|
|
|
/* do not allow linking to another block */
|
|
|
|
T0 = 0;
|
|
|
|
}
|
2006-02-08 22:43:39 +00:00
|
|
|
#endif
|
|
|
|
#if defined(USE_KQEMU)
|
|
|
|
#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
|
|
|
|
if (kqemu_is_ok(env) &&
|
|
|
|
(cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
|
|
|
|
cpu_loop_exit();
|
|
|
|
}
|
2003-08-10 21:48:43 +00:00
|
|
|
#endif
|
2003-06-24 13:22:59 +00:00
|
|
|
}
|
|
|
|
} else {
|
2004-10-12 22:01:28 +00:00
|
|
|
env_to_regs();
|
2003-03-06 23:23:54 +00:00
|
|
|
}
|
2003-06-24 13:22:59 +00:00
|
|
|
} /* for(;;) */
|
|
|
|
|
2003-03-06 23:23:54 +00:00
|
|
|
|
2003-06-15 19:51:39 +00:00
|
|
|
#if defined(TARGET_I386)
|
2004-02-25 23:19:55 +00:00
|
|
|
#if defined(USE_CODE_COPY)
|
|
|
|
if (env->native_fp_regs) {
|
|
|
|
save_native_fp_state(env);
|
|
|
|
}
|
|
|
|
#endif
|
2003-03-23 16:49:39 +00:00
|
|
|
/* restore flags in standard format */
|
2003-03-29 16:52:44 +00:00
|
|
|
env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
|
2003-06-15 19:51:39 +00:00
|
|
|
#elif defined(TARGET_ARM)
|
2005-02-22 19:27:29 +00:00
|
|
|
/* XXX: Save/restore host fpu exception state?. */
|
2003-09-30 20:57:29 +00:00
|
|
|
#elif defined(TARGET_SPARC)
|
2005-07-02 14:31:34 +00:00
|
|
|
#if defined(reg_REGWPTR)
|
|
|
|
REGWPTR = saved_regwptr;
|
|
|
|
#endif
|
2003-11-23 17:05:30 +00:00
|
|
|
#elif defined(TARGET_PPC)
|
2006-10-22 00:18:54 +00:00
|
|
|
#elif defined(TARGET_M68K)
|
|
|
|
cpu_m68k_flush_flags(env, env->cc_op);
|
|
|
|
env->cc_op = CC_OP_FLAGS;
|
|
|
|
env->sr = (env->sr & 0xffe0)
|
|
|
|
| env->cc_dest | (env->cc_x << 4);
|
2005-07-02 14:58:51 +00:00
|
|
|
#elif defined(TARGET_MIPS)
|
2006-04-27 21:07:38 +00:00
|
|
|
#elif defined(TARGET_SH4)
|
|
|
|
/* XXXXX */
|
2003-06-15 19:51:39 +00:00
|
|
|
#else
|
|
|
|
#error unsupported target CPU
|
|
|
|
#endif
|
2007-02-04 13:37:44 +00:00
|
|
|
|
|
|
|
/* restore global registers */
|
2006-06-14 17:32:25 +00:00
|
|
|
#if defined(__sparc__) && !defined(HOST_SOLARIS)
|
2003-06-09 15:28:00 +00:00
|
|
|
asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
|
2003-03-20 22:33:23 +00:00
|
|
|
#endif
|
2007-02-04 13:37:44 +00:00
|
|
|
#include "hostregs_helper.h"
|
|
|
|
|
2005-11-21 23:25:50 +00:00
|
|
|
/* fail safe : never use cpu_single_env outside cpu_exec() */
|
|
|
|
cpu_single_env = NULL;
|
2003-03-06 23:23:54 +00:00
|
|
|
return ret;
|
|
|
|
}
|
2003-03-16 18:05:05 +00:00
|
|
|
|
2004-04-25 21:21:33 +00:00
|
|
|
/* must only be called from the generated code as an exception can be
|
|
|
|
generated */
|
|
|
|
void tb_invalidate_page_range(target_ulong start, target_ulong end)
|
|
|
|
{
|
2004-06-22 18:43:30 +00:00
|
|
|
/* XXX: cannot enable it yet because it yields to MMU exception
|
|
|
|
where NIP != read address on PowerPC */
|
|
|
|
#if 0
|
2004-04-25 21:21:33 +00:00
|
|
|
target_ulong phys_addr;
|
|
|
|
phys_addr = get_phys_addr_code(env, start);
|
|
|
|
tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
|
2004-06-22 18:43:30 +00:00
|
|
|
#endif
|
2004-04-25 21:21:33 +00:00
|
|
|
}
|
|
|
|
|
2003-10-30 01:07:51 +00:00
|
|
|
#if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
|
2003-06-15 19:51:39 +00:00
|
|
|
|
2003-03-16 18:05:05 +00:00
|
|
|
void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
|
|
|
|
{
|
|
|
|
CPUX86State *saved_env;
|
|
|
|
|
|
|
|
saved_env = env;
|
|
|
|
env = s;
|
2003-07-26 18:01:40 +00:00
|
|
|
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
|
2003-05-27 23:29:48 +00:00
|
|
|
selector &= 0xffff;
|
2003-08-21 23:25:21 +00:00
|
|
|
cpu_x86_load_seg_cache(env, seg_reg, selector,
|
2005-01-03 23:35:10 +00:00
|
|
|
(selector << 4), 0xffff, 0);
|
2003-05-27 23:29:48 +00:00
|
|
|
} else {
|
2004-01-04 15:45:21 +00:00
|
|
|
load_seg(seg_reg, selector);
|
2003-05-27 23:29:48 +00:00
|
|
|
}
|
2003-03-16 18:05:05 +00:00
|
|
|
env = saved_env;
|
|
|
|
}
|
2003-03-23 16:49:39 +00:00
|
|
|
|
2003-05-29 20:04:28 +00:00
|
|
|
void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
|
|
|
|
{
|
|
|
|
CPUX86State *saved_env;
|
|
|
|
|
|
|
|
saved_env = env;
|
|
|
|
env = s;
|
|
|
|
|
2005-01-03 23:35:10 +00:00
|
|
|
helper_fsave((target_ulong)ptr, data32);
|
2003-05-29 20:04:28 +00:00
|
|
|
|
|
|
|
env = saved_env;
|
|
|
|
}
|
|
|
|
|
|
|
|
void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
|
|
|
|
{
|
|
|
|
CPUX86State *saved_env;
|
|
|
|
|
|
|
|
saved_env = env;
|
|
|
|
env = s;
|
|
|
|
|
2005-01-03 23:35:10 +00:00
|
|
|
helper_frstor((target_ulong)ptr, data32);
|
2003-05-29 20:04:28 +00:00
|
|
|
|
|
|
|
env = saved_env;
|
|
|
|
}
|
|
|
|
|
2003-06-15 19:51:39 +00:00
|
|
|
#endif /* TARGET_I386 */
|
|
|
|
|
2004-03-31 23:37:16 +00:00
|
|
|
#if !defined(CONFIG_SOFTMMU)
|
|
|
|
|
2003-06-24 13:22:59 +00:00
|
|
|
#if defined(TARGET_I386)
|
|
|
|
|
2003-05-08 15:38:04 +00:00
|
|
|
/* 'pc' is the host PC at which the exception was raised. 'address' is
|
2003-05-14 19:00:11 +00:00
|
|
|
the effective address of the memory exception. 'is_write' is 1 if a
|
|
|
|
write caused the exception and otherwise 0'. 'old_set' is the
|
|
|
|
signal set which should be restored */
|
2003-05-14 23:01:10 +00:00
|
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
2004-02-16 21:58:54 +00:00
|
|
|
int is_write, sigset_t *old_set,
|
|
|
|
void *puc)
|
2003-03-23 16:49:39 +00:00
|
|
|
{
|
2003-05-27 23:29:48 +00:00
|
|
|
TranslationBlock *tb;
|
|
|
|
int ret;
|
2003-06-30 13:12:32 +00:00
|
|
|
|
2003-06-25 16:12:37 +00:00
|
|
|
if (cpu_single_env)
|
|
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
2003-05-14 19:00:11 +00:00
|
|
|
#if defined(DEBUG_SIGNAL)
|
2004-02-16 21:58:54 +00:00
|
|
|
qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
2003-03-23 16:49:39 +00:00
|
|
|
#endif
|
2003-05-14 21:50:54 +00:00
|
|
|
/* XXX: locking issue */
|
2006-03-25 19:31:22 +00:00
|
|
|
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
2003-05-14 19:00:11 +00:00
|
|
|
return 1;
|
|
|
|
}
|
2004-04-25 21:21:33 +00:00
|
|
|
|
2003-06-24 13:22:59 +00:00
|
|
|
/* see if it is an MMU fault */
|
2003-10-27 21:13:06 +00:00
|
|
|
ret = cpu_x86_handle_mmu_fault(env, address, is_write,
|
|
|
|
((env->hflags & HF_CPL_MASK) == 3), 0);
|
2003-06-24 13:22:59 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return 0; /* not an MMU fault */
|
|
|
|
if (ret == 0)
|
|
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
|
|
/* now we have a real cpu fault */
|
2003-05-27 23:29:48 +00:00
|
|
|
tb = tb_find_pc(pc);
|
|
|
|
if (tb) {
|
2003-03-23 16:49:39 +00:00
|
|
|
/* the PC is inside the translated code. It means that we have
|
|
|
|
a virtual CPU fault */
|
2004-02-16 21:58:54 +00:00
|
|
|
cpu_restore_state(tb, env, pc, puc);
|
2003-06-24 13:22:59 +00:00
|
|
|
}
|
2003-08-10 21:48:43 +00:00
|
|
|
if (ret == 1) {
|
2003-06-24 13:22:59 +00:00
|
|
|
#if 0
|
2003-08-10 21:48:43 +00:00
|
|
|
printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
|
|
|
|
env->eip, env->cr[2], env->error_code);
|
2003-06-24 13:22:59 +00:00
|
|
|
#endif
|
2003-08-10 21:48:43 +00:00
|
|
|
/* we restore the process signal mask as the sigreturn should
|
|
|
|
do it (XXX: use sigsetjmp) */
|
|
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
2005-12-04 18:46:06 +00:00
|
|
|
raise_exception_err(env->exception_index, env->error_code);
|
2003-08-10 21:48:43 +00:00
|
|
|
} else {
|
|
|
|
/* activate soft MMU for this block */
|
2003-08-20 23:02:09 +00:00
|
|
|
env->hflags |= HF_SOFTMMU_MASK;
|
2004-04-25 21:21:33 +00:00
|
|
|
cpu_resume_from_signal(env, puc);
|
2003-08-10 21:48:43 +00:00
|
|
|
}
|
2003-06-24 13:22:59 +00:00
|
|
|
/* never comes here */
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2003-06-15 19:51:39 +00:00
|
|
|
#elif defined(TARGET_ARM)
|
2003-06-24 13:22:59 +00:00
|
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
2004-02-16 21:58:54 +00:00
|
|
|
int is_write, sigset_t *old_set,
|
|
|
|
void *puc)
|
2003-06-24 13:22:59 +00:00
|
|
|
{
|
2005-02-07 23:12:27 +00:00
|
|
|
TranslationBlock *tb;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (cpu_single_env)
|
|
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
|
|
#if defined(DEBUG_SIGNAL)
|
|
|
|
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
|
|
|
#endif
|
2005-02-02 20:42:01 +00:00
|
|
|
/* XXX: locking issue */
|
2006-03-25 19:31:22 +00:00
|
|
|
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
2005-02-02 20:42:01 +00:00
|
|
|
return 1;
|
|
|
|
}
|
2005-02-07 23:12:27 +00:00
|
|
|
/* see if it is an MMU fault */
|
|
|
|
ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
|
|
|
|
if (ret < 0)
|
|
|
|
return 0; /* not an MMU fault */
|
|
|
|
if (ret == 0)
|
|
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
|
|
/* now we have a real cpu fault */
|
|
|
|
tb = tb_find_pc(pc);
|
|
|
|
if (tb) {
|
|
|
|
/* the PC is inside the translated code. It means that we have
|
|
|
|
a virtual CPU fault */
|
|
|
|
cpu_restore_state(tb, env, pc, puc);
|
|
|
|
}
|
|
|
|
/* we restore the process signal mask as the sigreturn should
|
|
|
|
do it (XXX: use sigsetjmp) */
|
|
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
|
|
|
cpu_loop_exit();
|
2003-06-24 13:22:59 +00:00
|
|
|
}
|
2003-09-30 20:57:29 +00:00
|
|
|
#elif defined(TARGET_SPARC)
|
|
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
2004-02-16 21:58:54 +00:00
|
|
|
int is_write, sigset_t *old_set,
|
|
|
|
void *puc)
|
2003-09-30 20:57:29 +00:00
|
|
|
{
|
2005-02-07 23:12:27 +00:00
|
|
|
TranslationBlock *tb;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (cpu_single_env)
|
|
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
|
|
#if defined(DEBUG_SIGNAL)
|
|
|
|
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
|
|
|
#endif
|
2004-01-04 15:45:21 +00:00
|
|
|
/* XXX: locking issue */
|
2006-03-25 19:31:22 +00:00
|
|
|
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
2004-01-04 15:45:21 +00:00
|
|
|
return 1;
|
|
|
|
}
|
2005-02-07 23:12:27 +00:00
|
|
|
/* see if it is an MMU fault */
|
|
|
|
ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
|
|
|
|
if (ret < 0)
|
|
|
|
return 0; /* not an MMU fault */
|
|
|
|
if (ret == 0)
|
|
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
|
|
/* now we have a real cpu fault */
|
|
|
|
tb = tb_find_pc(pc);
|
|
|
|
if (tb) {
|
|
|
|
/* the PC is inside the translated code. It means that we have
|
|
|
|
a virtual CPU fault */
|
|
|
|
cpu_restore_state(tb, env, pc, puc);
|
|
|
|
}
|
|
|
|
/* we restore the process signal mask as the sigreturn should
|
|
|
|
do it (XXX: use sigsetjmp) */
|
|
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
|
|
|
cpu_loop_exit();
|
2003-09-30 20:57:29 +00:00
|
|
|
}
|
2003-11-23 17:05:30 +00:00
|
|
|
#elif defined (TARGET_PPC)
|
|
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
2004-02-16 21:58:54 +00:00
|
|
|
int is_write, sigset_t *old_set,
|
|
|
|
void *puc)
|
2003-11-23 17:05:30 +00:00
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
2004-01-04 23:53:18 +00:00
|
|
|
int ret;
|
2003-11-23 17:05:30 +00:00
|
|
|
|
|
|
|
if (cpu_single_env)
|
|
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
|
|
#if defined(DEBUG_SIGNAL)
|
|
|
|
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
|
|
|
#endif
|
|
|
|
/* XXX: locking issue */
|
2006-03-25 19:31:22 +00:00
|
|
|
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
2003-11-23 17:05:30 +00:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2004-01-04 23:53:18 +00:00
|
|
|
/* see if it is an MMU fault */
|
2004-01-18 23:19:48 +00:00
|
|
|
ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
|
2004-01-04 23:53:18 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return 0; /* not an MMU fault */
|
|
|
|
if (ret == 0)
|
|
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
|
|
|
2003-11-23 17:05:30 +00:00
|
|
|
/* now we have a real cpu fault */
|
|
|
|
tb = tb_find_pc(pc);
|
|
|
|
if (tb) {
|
|
|
|
/* the PC is inside the translated code. It means that we have
|
|
|
|
a virtual CPU fault */
|
2004-02-16 21:58:54 +00:00
|
|
|
cpu_restore_state(tb, env, pc, puc);
|
2003-11-23 17:05:30 +00:00
|
|
|
}
|
2004-01-04 23:53:18 +00:00
|
|
|
if (ret == 1) {
|
2003-11-23 17:05:30 +00:00
|
|
|
#if 0
|
2004-01-04 23:53:18 +00:00
|
|
|
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
|
|
|
env->nip, env->error_code, tb);
|
2003-11-23 17:05:30 +00:00
|
|
|
#endif
|
|
|
|
/* we restore the process signal mask as the sigreturn should
|
|
|
|
do it (XXX: use sigsetjmp) */
|
2004-02-16 21:58:54 +00:00
|
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
2004-05-21 12:59:32 +00:00
|
|
|
do_raise_exception_err(env->exception_index, env->error_code);
|
2004-01-04 23:53:18 +00:00
|
|
|
} else {
|
|
|
|
/* activate soft MMU for this block */
|
2004-04-25 21:21:33 +00:00
|
|
|
cpu_resume_from_signal(env, puc);
|
2004-01-04 23:53:18 +00:00
|
|
|
}
|
2003-11-23 17:05:30 +00:00
|
|
|
/* never comes here */
|
2006-10-22 00:18:54 +00:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
#elif defined(TARGET_M68K)
|
|
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
|
|
|
int is_write, sigset_t *old_set,
|
|
|
|
void *puc)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (cpu_single_env)
|
|
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
|
|
#if defined(DEBUG_SIGNAL)
|
|
|
|
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
|
|
|
#endif
|
|
|
|
/* XXX: locking issue */
|
|
|
|
if (is_write && page_unprotect(address, pc, puc)) {
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
/* see if it is an MMU fault */
|
|
|
|
ret = cpu_m68k_handle_mmu_fault(env, address, is_write, 1, 0);
|
|
|
|
if (ret < 0)
|
|
|
|
return 0; /* not an MMU fault */
|
|
|
|
if (ret == 0)
|
|
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
|
|
/* now we have a real cpu fault */
|
|
|
|
tb = tb_find_pc(pc);
|
|
|
|
if (tb) {
|
|
|
|
/* the PC is inside the translated code. It means that we have
|
|
|
|
a virtual CPU fault */
|
|
|
|
cpu_restore_state(tb, env, pc, puc);
|
|
|
|
}
|
|
|
|
/* we restore the process signal mask as the sigreturn should
|
|
|
|
do it (XXX: use sigsetjmp) */
|
|
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
|
|
|
cpu_loop_exit();
|
|
|
|
/* never comes here */
|
2003-11-23 17:05:30 +00:00
|
|
|
return 1;
|
|
|
|
}
|
2005-07-02 14:58:51 +00:00
|
|
|
|
|
|
|
#elif defined (TARGET_MIPS)
|
|
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
|
|
|
int is_write, sigset_t *old_set,
|
|
|
|
void *puc)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (cpu_single_env)
|
|
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
|
|
#if defined(DEBUG_SIGNAL)
|
|
|
|
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
|
|
|
#endif
|
|
|
|
/* XXX: locking issue */
|
2006-03-25 19:31:22 +00:00
|
|
|
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
2005-07-02 14:58:51 +00:00
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* see if it is an MMU fault */
|
2005-11-26 18:43:28 +00:00
|
|
|
ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
|
2005-07-02 14:58:51 +00:00
|
|
|
if (ret < 0)
|
|
|
|
return 0; /* not an MMU fault */
|
|
|
|
if (ret == 0)
|
|
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
|
|
|
|
|
|
/* now we have a real cpu fault */
|
|
|
|
tb = tb_find_pc(pc);
|
|
|
|
if (tb) {
|
|
|
|
/* the PC is inside the translated code. It means that we have
|
|
|
|
a virtual CPU fault */
|
|
|
|
cpu_restore_state(tb, env, pc, puc);
|
|
|
|
}
|
|
|
|
if (ret == 1) {
|
|
|
|
#if 0
|
|
|
|
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
|
|
|
env->nip, env->error_code, tb);
|
|
|
|
#endif
|
|
|
|
/* we restore the process signal mask as the sigreturn should
|
|
|
|
do it (XXX: use sigsetjmp) */
|
|
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
|
|
|
do_raise_exception_err(env->exception_index, env->error_code);
|
|
|
|
} else {
|
|
|
|
/* activate soft MMU for this block */
|
|
|
|
cpu_resume_from_signal(env, puc);
|
|
|
|
}
|
|
|
|
/* never comes here */
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2006-04-27 21:07:38 +00:00
|
|
|
#elif defined (TARGET_SH4)
|
|
|
|
static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
|
|
|
|
int is_write, sigset_t *old_set,
|
|
|
|
void *puc)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
if (cpu_single_env)
|
|
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
|
|
#if defined(DEBUG_SIGNAL)
|
|
|
|
printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
|
|
|
|
pc, address, is_write, *(unsigned long *)old_set);
|
|
|
|
#endif
|
|
|
|
/* XXX: locking issue */
|
|
|
|
if (is_write && page_unprotect(h2g(address), pc, puc)) {
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* see if it is an MMU fault */
|
|
|
|
ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
|
|
|
|
if (ret < 0)
|
|
|
|
return 0; /* not an MMU fault */
|
|
|
|
if (ret == 0)
|
|
|
|
return 1; /* the MMU fault was handled without causing real CPU fault */
|
|
|
|
|
|
|
|
/* now we have a real cpu fault */
|
|
|
|
tb = tb_find_pc(pc);
|
|
|
|
if (tb) {
|
|
|
|
/* the PC is inside the translated code. It means that we have
|
|
|
|
a virtual CPU fault */
|
|
|
|
cpu_restore_state(tb, env, pc, puc);
|
|
|
|
}
|
|
|
|
#if 0
|
|
|
|
printf("PF exception: NIP=0x%08x error=0x%x %p\n",
|
|
|
|
env->nip, env->error_code, tb);
|
|
|
|
#endif
|
|
|
|
/* we restore the process signal mask as the sigreturn should
|
|
|
|
do it (XXX: use sigsetjmp) */
|
2006-06-17 19:58:25 +00:00
|
|
|
sigprocmask(SIG_SETMASK, old_set, NULL);
|
|
|
|
cpu_loop_exit();
|
2006-04-27 21:07:38 +00:00
|
|
|
/* never comes here */
|
|
|
|
return 1;
|
|
|
|
}
|
2003-06-15 19:51:39 +00:00
|
|
|
#else
|
|
|
|
#error unsupported target CPU
|
|
|
|
#endif
|
2003-03-23 16:49:39 +00:00
|
|
|
|
2003-05-14 23:01:10 +00:00
|
|
|
#if defined(__i386__)
|
|
|
|
|
2007-02-05 21:41:46 +00:00
|
|
|
#if defined(__APPLE__)
|
|
|
|
# include <sys/ucontext.h>
|
|
|
|
|
|
|
|
# define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
|
|
|
|
# define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
|
|
|
|
# define ERROR_sig(context) ((context)->uc_mcontext->es.err)
|
|
|
|
#else
|
|
|
|
# define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
|
|
|
|
# define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
|
|
|
|
# define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
|
|
|
|
#endif
|
|
|
|
|
2004-02-16 21:58:54 +00:00
|
|
|
#if defined(USE_CODE_COPY)
|
|
|
|
static void cpu_send_trap(unsigned long pc, int trap,
|
|
|
|
struct ucontext *uc)
|
|
|
|
{
|
|
|
|
TranslationBlock *tb;
|
|
|
|
|
|
|
|
if (cpu_single_env)
|
|
|
|
env = cpu_single_env; /* XXX: find a correct solution for multithread */
|
|
|
|
/* now we have a real cpu fault */
|
|
|
|
tb = tb_find_pc(pc);
|
|
|
|
if (tb) {
|
|
|
|
/* the PC is inside the translated code. It means that we have
|
|
|
|
a virtual CPU fault */
|
|
|
|
cpu_restore_state(tb, env, pc, uc);
|
|
|
|
}
|
|
|
|
sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
|
|
|
|
raise_exception_err(trap, env->error_code);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2007-01-31 12:16:51 +00:00
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
2003-06-15 19:51:39 +00:00
|
|
|
void *puc)
|
2003-03-23 16:49:39 +00:00
|
|
|
{
|
2007-01-31 12:16:51 +00:00
|
|
|
siginfo_t *info = pinfo;
|
2003-03-23 16:49:39 +00:00
|
|
|
struct ucontext *uc = puc;
|
|
|
|
unsigned long pc;
|
2004-02-16 21:58:54 +00:00
|
|
|
int trapno;
|
2004-02-25 23:19:55 +00:00
|
|
|
|
2003-03-24 21:58:34 +00:00
|
|
|
#ifndef REG_EIP
|
|
|
|
/* for glibc 2.1 */
|
2003-05-14 19:00:11 +00:00
|
|
|
#define REG_EIP EIP
|
|
|
|
#define REG_ERR ERR
|
|
|
|
#define REG_TRAPNO TRAPNO
|
2003-03-24 21:58:34 +00:00
|
|
|
#endif
|
2007-02-05 21:41:46 +00:00
|
|
|
pc = EIP_sig(uc);
|
|
|
|
trapno = TRAP_sig(uc);
|
2004-02-16 21:58:54 +00:00
|
|
|
#if defined(TARGET_I386) && defined(USE_CODE_COPY)
|
|
|
|
if (trapno == 0x00 || trapno == 0x05) {
|
|
|
|
/* send division by zero or bound exception */
|
|
|
|
cpu_send_trap(pc, trapno, uc);
|
|
|
|
return 1;
|
|
|
|
} else
|
|
|
|
#endif
|
|
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
|
trapno == 0xe ?
|
2007-02-05 21:41:46 +00:00
|
|
|
(ERROR_sig(uc) >> 1) & 1 : 0,
|
2004-02-16 21:58:54 +00:00
|
|
|
&uc->uc_sigmask, puc);
|
2003-05-14 23:01:10 +00:00
|
|
|
}
|
|
|
|
|
2004-03-17 23:46:04 +00:00
|
|
|
#elif defined(__x86_64__)
|
|
|
|
|
2007-01-31 12:16:51 +00:00
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
2004-03-17 23:46:04 +00:00
|
|
|
void *puc)
|
|
|
|
{
|
2007-01-31 12:16:51 +00:00
|
|
|
siginfo_t *info = pinfo;
|
2004-03-17 23:46:04 +00:00
|
|
|
struct ucontext *uc = puc;
|
|
|
|
unsigned long pc;
|
|
|
|
|
|
|
|
pc = uc->uc_mcontext.gregs[REG_RIP];
|
|
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
|
uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
|
|
|
|
(uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
|
|
|
|
&uc->uc_sigmask, puc);
|
|
|
|
}
|
|
|
|
|
2004-07-05 21:25:26 +00:00
|
|
|
#elif defined(__powerpc__)
|
2003-05-14 23:01:10 +00:00
|
|
|
|
2004-07-05 21:25:26 +00:00
|
|
|
/***********************************************************************
|
|
|
|
* signal context platform-specific definitions
|
|
|
|
* From Wine
|
|
|
|
*/
|
|
|
|
#ifdef linux
|
|
|
|
/* All Registers access - only for local access */
|
|
|
|
# define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
|
|
|
|
/* Gpr Registers access */
|
|
|
|
# define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
|
|
|
|
# define IAR_sig(context) REG_sig(nip, context) /* Program counter */
|
|
|
|
# define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
|
|
|
|
# define CTR_sig(context) REG_sig(ctr, context) /* Count register */
|
|
|
|
# define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
|
|
|
|
# define LR_sig(context) REG_sig(link, context) /* Link register */
|
|
|
|
# define CR_sig(context) REG_sig(ccr, context) /* Condition register */
|
|
|
|
/* Float Registers access */
|
|
|
|
# define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
|
|
|
|
# define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
|
|
|
|
/* Exception Registers access */
|
|
|
|
# define DAR_sig(context) REG_sig(dar, context)
|
|
|
|
# define DSISR_sig(context) REG_sig(dsisr, context)
|
|
|
|
# define TRAP_sig(context) REG_sig(trap, context)
|
|
|
|
#endif /* linux */
|
|
|
|
|
|
|
|
#ifdef __APPLE__
|
|
|
|
# include <sys/ucontext.h>
|
|
|
|
typedef struct ucontext SIGCONTEXT;
|
|
|
|
/* All Registers access - only for local access */
|
|
|
|
# define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
|
|
|
|
# define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
|
|
|
|
# define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
|
|
|
|
# define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
|
|
|
|
/* Gpr Registers access */
|
|
|
|
# define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
|
|
|
|
# define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
|
|
|
|
# define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
|
|
|
|
# define CTR_sig(context) REG_sig(ctr, context)
|
|
|
|
# define XER_sig(context) REG_sig(xer, context) /* Link register */
|
|
|
|
# define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
|
|
|
|
# define CR_sig(context) REG_sig(cr, context) /* Condition register */
|
|
|
|
/* Float Registers access */
|
|
|
|
# define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
|
|
|
|
# define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
|
|
|
|
/* Exception Registers access */
|
|
|
|
# define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
|
|
|
|
# define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
|
|
|
|
# define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
|
|
|
|
#endif /* __APPLE__ */
|
|
|
|
|
2007-01-31 12:16:51 +00:00
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
2003-06-15 19:51:39 +00:00
|
|
|
void *puc)
|
2003-05-14 23:01:10 +00:00
|
|
|
{
|
2007-01-31 12:16:51 +00:00
|
|
|
siginfo_t *info = pinfo;
|
2003-05-14 21:50:54 +00:00
|
|
|
struct ucontext *uc = puc;
|
|
|
|
unsigned long pc;
|
|
|
|
int is_write;
|
|
|
|
|
2004-07-05 21:25:26 +00:00
|
|
|
pc = IAR_sig(uc);
|
2003-05-14 21:50:54 +00:00
|
|
|
is_write = 0;
|
|
|
|
#if 0
|
|
|
|
/* ppc 4xx case */
|
2004-07-05 21:25:26 +00:00
|
|
|
if (DSISR_sig(uc) & 0x00800000)
|
2003-05-14 21:50:54 +00:00
|
|
|
is_write = 1;
|
|
|
|
#else
|
2004-07-05 21:25:26 +00:00
|
|
|
if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
|
2003-05-14 21:50:54 +00:00
|
|
|
is_write = 1;
|
|
|
|
#endif
|
|
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
2004-02-16 21:58:54 +00:00
|
|
|
is_write, &uc->uc_sigmask, puc);
|
2003-05-14 23:01:10 +00:00
|
|
|
}
|
|
|
|
|
2003-06-02 20:38:09 +00:00
|
|
|
#elif defined(__alpha__)
|
|
|
|
|
2007-01-31 12:16:51 +00:00
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
2003-06-02 20:38:09 +00:00
|
|
|
void *puc)
|
|
|
|
{
|
2007-01-31 12:16:51 +00:00
|
|
|
siginfo_t *info = pinfo;
|
2003-06-02 20:38:09 +00:00
|
|
|
struct ucontext *uc = puc;
|
|
|
|
uint32_t *pc = uc->uc_mcontext.sc_pc;
|
|
|
|
uint32_t insn = *pc;
|
|
|
|
int is_write = 0;
|
|
|
|
|
2003-06-09 15:28:00 +00:00
|
|
|
/* XXX: need kernel patch to get write flag faster */
|
2003-06-02 20:38:09 +00:00
|
|
|
switch (insn >> 26) {
|
|
|
|
case 0x0d: // stw
|
|
|
|
case 0x0e: // stb
|
|
|
|
case 0x0f: // stq_u
|
|
|
|
case 0x24: // stf
|
|
|
|
case 0x25: // stg
|
|
|
|
case 0x26: // sts
|
|
|
|
case 0x27: // stt
|
|
|
|
case 0x2c: // stl
|
|
|
|
case 0x2d: // stq
|
|
|
|
case 0x2e: // stl_c
|
|
|
|
case 0x2f: // stq_c
|
|
|
|
is_write = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
2004-02-16 21:58:54 +00:00
|
|
|
is_write, &uc->uc_sigmask, puc);
|
2003-06-02 20:38:09 +00:00
|
|
|
}
|
2003-06-09 15:28:00 +00:00
|
|
|
#elif defined(__sparc__)
|
|
|
|
|
2007-01-31 12:16:51 +00:00
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
2003-06-15 19:51:39 +00:00
|
|
|
void *puc)
|
2003-06-09 15:28:00 +00:00
|
|
|
{
|
2007-01-31 12:16:51 +00:00
|
|
|
siginfo_t *info = pinfo;
|
2003-06-09 15:28:00 +00:00
|
|
|
uint32_t *regs = (uint32_t *)(info + 1);
|
|
|
|
void *sigmask = (regs + 20);
|
|
|
|
unsigned long pc;
|
|
|
|
int is_write;
|
|
|
|
uint32_t insn;
|
|
|
|
|
|
|
|
/* XXX: is there a standard glibc define ? */
|
|
|
|
pc = regs[1];
|
|
|
|
/* XXX: need kernel patch to get write flag faster */
|
|
|
|
is_write = 0;
|
|
|
|
insn = *(uint32_t *)pc;
|
|
|
|
if ((insn >> 30) == 3) {
|
|
|
|
switch((insn >> 19) & 0x3f) {
|
|
|
|
case 0x05: // stb
|
|
|
|
case 0x06: // sth
|
|
|
|
case 0x04: // st
|
|
|
|
case 0x07: // std
|
|
|
|
case 0x24: // stf
|
|
|
|
case 0x27: // stdf
|
|
|
|
case 0x25: // stfsr
|
|
|
|
is_write = 1;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
2004-02-16 21:58:54 +00:00
|
|
|
is_write, sigmask, NULL);
|
2003-06-09 15:28:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#elif defined(__arm__)
|
|
|
|
|
2007-01-31 12:16:51 +00:00
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
2003-06-15 19:51:39 +00:00
|
|
|
void *puc)
|
2003-06-09 15:28:00 +00:00
|
|
|
{
|
2007-01-31 12:16:51 +00:00
|
|
|
siginfo_t *info = pinfo;
|
2003-06-09 15:28:00 +00:00
|
|
|
struct ucontext *uc = puc;
|
|
|
|
unsigned long pc;
|
|
|
|
int is_write;
|
|
|
|
|
|
|
|
pc = uc->uc_mcontext.gregs[R15];
|
|
|
|
/* XXX: compute is_write */
|
|
|
|
is_write = 0;
|
|
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
|
is_write,
|
2006-07-29 19:09:31 +00:00
|
|
|
&uc->uc_sigmask, puc);
|
2003-06-09 15:28:00 +00:00
|
|
|
}
|
|
|
|
|
2003-08-10 22:14:22 +00:00
|
|
|
#elif defined(__mc68000)
|
|
|
|
|
2007-01-31 12:16:51 +00:00
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
2003-08-10 22:14:22 +00:00
|
|
|
void *puc)
|
|
|
|
{
|
2007-01-31 12:16:51 +00:00
|
|
|
siginfo_t *info = pinfo;
|
2003-08-10 22:14:22 +00:00
|
|
|
struct ucontext *uc = puc;
|
|
|
|
unsigned long pc;
|
|
|
|
int is_write;
|
|
|
|
|
|
|
|
pc = uc->uc_mcontext.gregs[16];
|
|
|
|
/* XXX: compute is_write */
|
|
|
|
is_write = 0;
|
|
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
|
is_write,
|
2004-02-16 21:58:54 +00:00
|
|
|
&uc->uc_sigmask, puc);
|
2003-08-10 22:14:22 +00:00
|
|
|
}
|
|
|
|
|
2005-04-07 22:20:31 +00:00
|
|
|
#elif defined(__ia64)
|
|
|
|
|
|
|
|
#ifndef __ISR_VALID
|
|
|
|
/* This ought to be in <bits/siginfo.h>... */
|
|
|
|
# define __ISR_VALID 1
|
|
|
|
#endif
|
|
|
|
|
2007-01-31 12:16:51 +00:00
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
|
2005-04-07 22:20:31 +00:00
|
|
|
{
|
2007-01-31 12:16:51 +00:00
|
|
|
siginfo_t *info = pinfo;
|
2005-04-07 22:20:31 +00:00
|
|
|
struct ucontext *uc = puc;
|
|
|
|
unsigned long ip;
|
|
|
|
int is_write = 0;
|
|
|
|
|
|
|
|
ip = uc->uc_mcontext.sc_ip;
|
|
|
|
switch (host_signum) {
|
|
|
|
case SIGILL:
|
|
|
|
case SIGFPE:
|
|
|
|
case SIGSEGV:
|
|
|
|
case SIGBUS:
|
|
|
|
case SIGTRAP:
|
2006-04-24 20:32:17 +00:00
|
|
|
if (info->si_code && (info->si_segvflags & __ISR_VALID))
|
2005-04-07 22:20:31 +00:00
|
|
|
/* ISR.W (write-access) is bit 33: */
|
|
|
|
is_write = (info->si_isr >> 33) & 1;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return handle_cpu_signal(ip, (unsigned long)info->si_addr,
|
|
|
|
is_write,
|
|
|
|
&uc->uc_sigmask, puc);
|
|
|
|
}
|
|
|
|
|
2005-07-24 15:11:38 +00:00
|
|
|
#elif defined(__s390__)
|
|
|
|
|
2007-01-31 12:16:51 +00:00
|
|
|
int cpu_signal_handler(int host_signum, void *pinfo,
|
2005-07-24 15:11:38 +00:00
|
|
|
void *puc)
|
|
|
|
{
|
2007-01-31 12:16:51 +00:00
|
|
|
siginfo_t *info = pinfo;
|
2005-07-24 15:11:38 +00:00
|
|
|
struct ucontext *uc = puc;
|
|
|
|
unsigned long pc;
|
|
|
|
int is_write;
|
|
|
|
|
|
|
|
pc = uc->uc_mcontext.psw.addr;
|
|
|
|
/* XXX: compute is_write */
|
|
|
|
is_write = 0;
|
|
|
|
return handle_cpu_signal(pc, (unsigned long)info->si_addr,
|
|
|
|
is_write,
|
|
|
|
&uc->uc_sigmask, puc);
|
|
|
|
}
|
|
|
|
|
2003-03-23 16:49:39 +00:00
|
|
|
#else
|
2003-05-14 23:01:10 +00:00
|
|
|
|
2003-06-24 13:22:59 +00:00
|
|
|
#error host CPU specific signal handler needed
|
2003-05-14 23:01:10 +00:00
|
|
|
|
2003-03-23 16:49:39 +00:00
|
|
|
#endif
|
2004-03-31 23:37:16 +00:00
|
|
|
|
|
|
|
#endif /* !defined(CONFIG_SOFTMMU) */
|