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spapr: Move SpaprIrq::nr_xirqs to SpaprMachineClass

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For the benefit of peripheral device allocation, the number of available
irqs really wants to be the same on a given machine type version,
regardless of what irq backends we are using.  That's the case now, but
only because we make sure the different SpaprIrq instances have the same
value except for the special legacy one.

Since this really only depends on machine type version, move the value to
SpaprMachineClass instead of SpaprIrq.  This also puts the code to set it
to the lower value on old machine types right next to setting
legacy_irq_allocation, which needs to go hand in hand.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
David Gibson 2019-09-27 13:54:23 +10:00
parent 8cbe71ecb8
commit 54255c1f65
4 changed files with 19 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/ppc/spapr.c
View File

@ -4440,6 +4440,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
smc->dr_phb_enabled = true;
smc->linux_pci_probe = true;
smc->smp_threads_vsmt = true;
smc->nr_xirqs = SPAPR_NR_XIRQS;
}
static const TypeInfo spapr_machine_info = {
@ -4576,6 +4577,7 @@ static void spapr_machine_3_0_class_options(MachineClass *mc)
compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
smc->legacy_irq_allocation = true;
smc->nr_xirqs = 0x400;
smc->irq = &spapr_irq_xics_legacy;
}

33
hw/ppc/spapr_irq.c
View File

@ -106,7 +106,6 @@ int spapr_irq_init_kvm(int (*fn)(SpaprInterruptController *, Error **),
*/
SpaprIrq spapr_irq_xics = {
.nr_xirqs = SPAPR_NR_XIRQS,
.xics = true,
.xive = false,
};
@ -116,7 +115,6 @@ SpaprIrq spapr_irq_xics = {
*/
SpaprIrq spapr_irq_xive = {
.nr_xirqs = SPAPR_NR_XIRQS,
.xics = false,
.xive = true,
};
@ -134,7 +132,6 @@ SpaprIrq spapr_irq_xive = {
* Define values in sync with the XIVE and XICS backend
*/
SpaprIrq spapr_irq_dual = {
.nr_xirqs = SPAPR_NR_XIRQS,
.xics = true,
.xive = true,
};
@ -251,16 +248,19 @@ void spapr_irq_dt(SpaprMachineState *spapr, uint32_t nr_servers,
uint32_t spapr_irq_nr_msis(SpaprMachineState *spapr)
{
if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) {
return spapr->irq->nr_xirqs;
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
if (smc->legacy_irq_allocation) {
return smc->nr_xirqs;
} else {
return SPAPR_XIRQ_BASE + spapr->irq->nr_xirqs - SPAPR_IRQ_MSI;
return SPAPR_XIRQ_BASE + smc->nr_xirqs - SPAPR_IRQ_MSI;
}
}
void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
{
MachineState *machine = MACHINE(spapr);
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
if (machine_kernel_irqchip_split(machine)) {
error_setg(errp, "kernel_irqchip split mode not supported on pseries");
@ -298,8 +298,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
return;
}
object_property_set_int(obj, spapr->irq->nr_xirqs, "nr-irqs",
&local_err);
object_property_set_int(obj, smc->nr_xirqs, "nr-irqs", &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@ -320,8 +319,7 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
int i;
dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
qdev_prop_set_uint32(dev, "nr-irqs",
spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE);
qdev_prop_set_uint32(dev, "nr-irqs", smc->nr_xirqs + SPAPR_XIRQ_BASE);
/*
* 8 XIVE END structures per CPU. One for each available
* priority
@ -346,17 +344,18 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp)
}
spapr->qirqs = qemu_allocate_irqs(spapr_set_irq, spapr,
spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE);
smc->nr_xirqs + SPAPR_XIRQ_BASE);
}
int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp)
{
SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
int i;
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
int rc;
assert(irq >= SPAPR_XIRQ_BASE);
assert(irq < (spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE));
assert(irq < (smc->nr_xirqs + SPAPR_XIRQ_BASE));
for (i = 0; i < ARRAY_SIZE(intcs); i++) {
SpaprInterruptController *intc = intcs[i];
@ -376,9 +375,10 @@ void spapr_irq_free(SpaprMachineState *spapr, int irq, int num)
{
SpaprInterruptController *intcs[] = ALL_INTCS(spapr);
int i, j;
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
assert(irq >= SPAPR_XIRQ_BASE);
assert((irq + num) <= (spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE));
assert((irq + num) <= (smc->nr_xirqs + SPAPR_XIRQ_BASE));
for (i = irq; i < (irq + num); i++) {
for (j = 0; j < ARRAY_SIZE(intcs); j++) {
@ -395,6 +395,8 @@ void spapr_irq_free(SpaprMachineState *spapr, int irq, int num)
qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq)
{
SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
/*
* This interface is basically for VIO and PHB devices to find the
* right qemu_irq to manipulate, so we only allow access to the
@ -403,7 +405,7 @@ qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq)
* interfaces, we can change this if we need to in future.
*/
assert(irq >= SPAPR_XIRQ_BASE);
assert(irq < (spapr->irq->nr_xirqs + SPAPR_XIRQ_BASE));
assert(irq < (smc->nr_xirqs + SPAPR_XIRQ_BASE));
if (spapr->ics) {
assert(ics_valid_irq(spapr->ics, irq));
@ -556,10 +558,7 @@ int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp)
return first + ics->offset;
}
#define SPAPR_IRQ_XICS_LEGACY_NR_XIRQS 0x400
SpaprIrq spapr_irq_xics_legacy = {
.nr_xirqs = SPAPR_IRQ_XICS_LEGACY_NR_XIRQS,
.xics = true,
.xive = false,
};

1
include/hw/ppc/spapr.h
View File

@ -119,6 +119,7 @@ struct SpaprMachineClass {
bool use_ohci_by_default; /* use USB-OHCI instead of XHCI */
bool pre_2_10_has_unused_icps;
bool legacy_irq_allocation;
uint32_t nr_xirqs;
bool broken_host_serial_model; /* present real host info to the guest */
bool pre_4_1_migration; /* don't migrate hpt-max-page-size */
bool linux_pci_probe;

1
include/hw/ppc/spapr_irq.h
View File

@ -78,7 +78,6 @@ int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
typedef struct SpaprIrq {
uint32_t nr_xirqs;
bool xics;
bool xive;
} SpaprIrq;