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tcg-arm: Improve scheduling of tcg_out_tlb_read
The schedule was fully serial, with no possibility for dual issue. The old schedule had a minimal issue of 7 cycles; the new schedule has a minimal issue of 5 cycles. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
Aurelien Jarno
parent
cee87be80a
commit
702b33b1d5
@ -182,17 +182,11 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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#ifdef CONFIG_SOFTMMU
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/* r0 and r1 will be overwritten when reading the tlb entry,
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/* r0-r2 will be overwritten when reading the tlb entry,
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so don't use these. */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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#if TARGET_LONG_BITS == 64
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/* If we're passing env to the helper as r0 and need a regpair
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* for the address then r2 will be overwritten as we're setting
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* up the args to the helper.
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*/
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
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#endif
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#endif
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break;
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case 'L':
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@ -207,30 +201,16 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
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/* qemu_st address & data_reg */
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case 's':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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/* r0 and r1 will be overwritten when reading the tlb entry
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(softmmu only) and doing the byte swapping, so don't
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use these. */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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#if defined(CONFIG_SOFTMMU) && (TARGET_LONG_BITS == 64)
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/* Avoid clashes with registers being used for helper args */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
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#endif
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break;
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/* qemu_st64 data_reg2 */
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case 'S':
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ct->ct |= TCG_CT_REG;
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tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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/* r0 and r1 will be overwritten when reading the tlb entry
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(softmmu only) and doing the byte swapping, so don't
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use these. */
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/* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
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and r0-r1 doing the byte swapping, so don't use these. */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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#ifdef CONFIG_SOFTMMU
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/* r2 is still needed to load data_reg, so don't use it. */
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#if defined(CONFIG_SOFTMMU)
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/* Avoid clashes with registers being used for helper args */
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
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#if TARGET_LONG_BITS == 64
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/* Avoid clashes with registers being used for helper args */
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@ -347,6 +327,8 @@ typedef enum {
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INSN_LDRSB_REG = 0x001000d0,
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INSN_STRB_IMM = 0x04400000,
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INSN_STRB_REG = 0x06400000,
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INSN_LDRD_IMM = 0x004000d0,
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} ARMInsn;
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#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
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@ -805,15 +787,6 @@ static inline void tcg_out_ld32_12(TCGContext *s, int cond, TCGReg rt,
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tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 0);
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}
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/* Offset pre-increment with base writeback. */
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static inline void tcg_out_ld32_12wb(TCGContext *s, int cond, TCGReg rt,
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TCGReg rn, int imm12)
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{
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/* ldr with writeback and both register equals is UNPREDICTABLE */
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assert(rd != rn);
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tcg_out_memop_12(s, cond, INSN_LDR_IMM, rt, rn, imm12, 1, 1);
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}
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static inline void tcg_out_st32_12(TCGContext *s, int cond, TCGReg rt,
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TCGReg rn, int imm12)
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{
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@ -1150,47 +1123,78 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg,
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#define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
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/* Load and compare a TLB entry, leaving the flags set. Leaves R0 pointing
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/* Load and compare a TLB entry, leaving the flags set. Leaves R2 pointing
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to the tlb entry. Clobbers R1 and TMP. */
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static void tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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int s_bits, int tlb_offset)
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{
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TCGReg base = TCG_AREG0;
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/* Should generate something like the following:
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* shr r8, addr_reg, #TARGET_PAGE_BITS
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* and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8
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* add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
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* pre-v7:
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* shr tmp, addr_reg, #TARGET_PAGE_BITS (1)
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* add r2, env, #off & 0xff00
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* and r0, tmp, #(CPU_TLB_SIZE - 1) (2)
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* add r2, r2, r0, lsl #CPU_TLB_ENTRY_BITS (3)
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* ldr r0, [r2, #off & 0xff]! (4)
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* tst addr_reg, #s_mask
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* cmpeq r0, tmp, lsl #TARGET_PAGE_BITS (5)
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*
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* v7 (not implemented yet):
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* ubfx r2, addr_reg, #TARGET_PAGE_BITS, #CPU_TLB_BITS (1)
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* movw tmp, #~TARGET_PAGE_MASK & ~s_mask
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* movw r0, #off
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* add r2, env, r2, lsl #CPU_TLB_ENTRY_BITS (2)
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* bic tmp, addr_reg, tmp
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* ldr r0, [r2, r0]! (3)
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* cmp r0, tmp (4)
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*/
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# if CPU_TLB_BITS > 8
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# error
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# endif
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tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP,
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0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
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/* We assume that the offset is contained within 16 bits. */
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assert((tlb_offset & ~0xffff) == 0);
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if (tlb_offset > 0xff) {
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R2, base,
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(24 << 7) | (tlb_offset >> 8));
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tlb_offset &= 0xff;
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base = TCG_REG_R2;
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}
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tcg_out_dat_imm(s, COND_AL, ARITH_AND,
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TCG_REG_R0, TCG_REG_TMP, CPU_TLB_SIZE - 1);
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0,
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tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R2, base,
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TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
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/* We assume that the offset is contained within 20 bits. */
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assert((tlb_offset & ~0xfffff) == 0);
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if (tlb_offset > 0xfff) {
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tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0,
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0xa00 | (tlb_offset >> 12));
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tlb_offset &= 0xfff;
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/* Load the tlb comparator. Use ldrd if needed and available,
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but due to how the pointer needs setting up, ldm isn't useful.
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Base arm5 doesn't have ldrd, but armv5te does. */
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if (use_armv6_instructions && TARGET_LONG_BITS == 64) {
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tcg_out_memop_8(s, COND_AL, INSN_LDRD_IMM, TCG_REG_R0,
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TCG_REG_R2, tlb_offset, 1, 1);
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} else {
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tcg_out_memop_12(s, COND_AL, INSN_LDR_IMM, TCG_REG_R0,
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TCG_REG_R2, tlb_offset, 1, 1);
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if (TARGET_LONG_BITS == 64) {
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tcg_out_memop_12(s, COND_AL, INSN_LDR_IMM, TCG_REG_R0,
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TCG_REG_R2, 4, 1, 0);
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}
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}
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tcg_out_ld32_12wb(s, COND_AL, TCG_REG_R1, TCG_REG_R0, tlb_offset);
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tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1,
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TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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/* Check alignment. */
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if (s_bits) {
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tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
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tcg_out_dat_imm(s, COND_AL, ARITH_TST,
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0, addrlo, (1 << s_bits) - 1);
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}
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tcg_out_dat_reg(s, (s_bits ? COND_EQ : COND_AL), ARITH_CMP, 0,
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TCG_REG_R0, TCG_REG_TMP, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
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if (TARGET_LONG_BITS == 64) {
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/* XXX: possibly we could use a block data load in the first access. */
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4);
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tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
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TCG_REG_R1, addrhi, SHIFT_IMM_LSL(0));
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}
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@ -1223,7 +1227,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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tcg_out_tlb_read(s, addr_reg, addr_reg2, s_bits,
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offsetof(CPUArchState, tlb_table[mem_index][0].addr_read));
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R2,
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_read));
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@ -1395,7 +1399,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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offsetof(CPUArchState,
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tlb_table[mem_index][0].addr_write));
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0,
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tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R2,
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_write));
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