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target/arm: Convert "single-precision" register moves to decodetree
Convert the "single-precision" register moves to decodetree:
* VMSR
* VMRS
* VMOV between general purpose register and single precision
Note that the VMSR/VMRS conversions make our handling of
the "should this UNDEF?" checks consistent between the two
instructions:
* VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0
(previously was a nop)
* VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better
(previously was a nop)
* VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better
(previously would write to the register, which had no
guest-visible effect because we always UNDEF reads)
We also tighten up the decode: we were previously underdecoding
some SBZ or SBO bits.
The conversion of VMOV_single includes the expansion out of the
gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr()
sequences into the simpler direct load/store of the TCG temp via
neon_{load,store}_reg32(): we know in the new function that we're
always single-precision, we don't need to use the old-and-deprecated
cpu_F0* TCG globals, and we don't happen to have the declaration of
gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the
new function is.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Peter Maydell
parent
9851ed9269
commit
a9ab50011a
@ -622,3 +622,164 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
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return true;
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}
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static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
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{
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TCGv_i32 tmp;
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bool ignore_vfp_enabled = false;
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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/*
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* The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
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* Writes to R15 are UNPREDICTABLE; we choose to undef.
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*/
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if (a->rt == 15 || a->reg != ARM_VFP_FPSCR) {
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return false;
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}
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}
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switch (a->reg) {
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case ARM_VFP_FPSID:
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/*
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* VFPv2 allows access to FPSID from userspace; VFPv3 restricts
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* all ID registers to privileged access only.
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*/
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if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return false;
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}
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ignore_vfp_enabled = true;
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break;
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case ARM_VFP_MVFR0:
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case ARM_VFP_MVFR1:
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if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_MVFR)) {
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return false;
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}
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ignore_vfp_enabled = true;
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break;
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case ARM_VFP_MVFR2:
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if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V8)) {
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return false;
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}
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ignore_vfp_enabled = true;
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break;
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case ARM_VFP_FPSCR:
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break;
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case ARM_VFP_FPEXC:
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if (IS_USER(s)) {
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return false;
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}
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ignore_vfp_enabled = true;
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break;
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case ARM_VFP_FPINST:
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case ARM_VFP_FPINST2:
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/* Not present in VFPv3 */
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if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return false;
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}
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break;
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default:
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return false;
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}
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if (!full_vfp_access_check(s, ignore_vfp_enabled)) {
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return true;
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}
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if (a->l) {
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/* VMRS, move VFP special register to gp register */
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switch (a->reg) {
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case ARM_VFP_FPSID:
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case ARM_VFP_FPEXC:
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case ARM_VFP_FPINST:
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case ARM_VFP_FPINST2:
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case ARM_VFP_MVFR0:
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case ARM_VFP_MVFR1:
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case ARM_VFP_MVFR2:
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tmp = load_cpu_field(vfp.xregs[a->reg]);
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break;
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case ARM_VFP_FPSCR:
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if (a->rt == 15) {
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tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
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tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
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} else {
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tmp = tcg_temp_new_i32();
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gen_helper_vfp_get_fpscr(tmp, cpu_env);
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}
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break;
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default:
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g_assert_not_reached();
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}
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if (a->rt == 15) {
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/* Set the 4 flag bits in the CPSR. */
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gen_set_nzcv(tmp);
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tcg_temp_free_i32(tmp);
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} else {
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store_reg(s, a->rt, tmp);
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}
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} else {
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/* VMSR, move gp register to VFP special register */
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switch (a->reg) {
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case ARM_VFP_FPSID:
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case ARM_VFP_MVFR0:
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case ARM_VFP_MVFR1:
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case ARM_VFP_MVFR2:
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/* Writes are ignored. */
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break;
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case ARM_VFP_FPSCR:
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tmp = load_reg(s, a->rt);
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gen_helper_vfp_set_fpscr(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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gen_lookup_tb(s);
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break;
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case ARM_VFP_FPEXC:
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/*
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* TODO: VFP subarchitecture support.
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* For now, keep the EN bit only
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*/
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tmp = load_reg(s, a->rt);
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tcg_gen_andi_i32(tmp, tmp, 1 << 30);
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store_cpu_field(tmp, vfp.xregs[a->reg]);
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gen_lookup_tb(s);
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break;
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case ARM_VFP_FPINST:
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case ARM_VFP_FPINST2:
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tmp = load_reg(s, a->rt);
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store_cpu_field(tmp, vfp.xregs[a->reg]);
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break;
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default:
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g_assert_not_reached();
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}
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}
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return true;
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}
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static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
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{
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TCGv_i32 tmp;
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if (!vfp_access_check(s)) {
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return true;
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}
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if (a->l) {
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/* VFP to general purpose register */
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tmp = tcg_temp_new_i32();
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neon_load_reg32(tmp, a->vn);
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if (a->rt == 15) {
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/* Set the 4 flag bits in the CPSR. */
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gen_set_nzcv(tmp);
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tcg_temp_free_i32(tmp);
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} else {
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store_reg(s, a->rt, tmp);
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}
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} else {
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/* general purpose register to VFP */
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tmp = load_reg(s, a->rt);
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neon_store_reg32(tmp, a->vn);
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tcg_temp_free_i32(tmp);
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}
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return true;
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}
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@ -3097,7 +3097,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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TCGv_i32 addr;
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TCGv_i32 tmp;
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TCGv_i32 tmp2;
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bool ignore_vfp_enabled = false;
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if (!arm_dc_feature(s, ARM_FEATURE_VFP)) {
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return 1;
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@ -3133,14 +3132,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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* for invalid encodings; we will generate incorrect syndrome information
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* for attempts to execute invalid vfp/neon encodings with FP disabled.
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*/
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if ((insn & 0x0fe00fff) == 0x0ee00a10) {
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rn = (insn >> 16) & 0xf;
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if (rn == ARM_VFP_FPSID || rn == ARM_VFP_FPEXC || rn == ARM_VFP_MVFR2
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|| rn == ARM_VFP_MVFR1 || rn == ARM_VFP_MVFR0) {
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ignore_vfp_enabled = true;
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}
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}
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if (!full_vfp_access_check(s, ignore_vfp_enabled)) {
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if (!vfp_access_check(s)) {
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return 0;
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}
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@ -3148,142 +3140,8 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
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switch ((insn >> 24) & 0xf) {
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case 0xe:
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if (insn & (1 << 4)) {
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/* single register transfer */
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rd = (insn >> 12) & 0xf;
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if (dp) {
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/* already handled by decodetree */
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return 1;
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} else { /* !dp */
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bool is_sysreg;
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if ((insn & 0x6f) != 0x00)
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return 1;
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rn = VFP_SREG_N(insn);
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is_sysreg = extract32(insn, 21, 1);
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if (arm_dc_feature(s, ARM_FEATURE_M)) {
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/*
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* The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
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* Writes to R15 are UNPREDICTABLE; we choose to undef.
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*/
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if (is_sysreg && (rd == 15 || (rn >> 1) != ARM_VFP_FPSCR)) {
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return 1;
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}
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}
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if (insn & ARM_CP_RW_BIT) {
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/* vfp->arm */
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if (is_sysreg) {
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/* system register */
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rn >>= 1;
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switch (rn) {
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case ARM_VFP_FPSID:
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/* VFP2 allows access to FSID from userspace.
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VFP3 restricts all id registers to privileged
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accesses. */
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if (IS_USER(s)
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&& arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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tmp = load_cpu_field(vfp.xregs[rn]);
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break;
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case ARM_VFP_FPEXC:
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if (IS_USER(s))
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return 1;
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tmp = load_cpu_field(vfp.xregs[rn]);
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break;
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case ARM_VFP_FPINST:
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case ARM_VFP_FPINST2:
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/* Not present in VFP3. */
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if (IS_USER(s)
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|| arm_dc_feature(s, ARM_FEATURE_VFP3)) {
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return 1;
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}
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tmp = load_cpu_field(vfp.xregs[rn]);
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break;
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case ARM_VFP_FPSCR:
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if (rd == 15) {
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tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
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tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
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} else {
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tmp = tcg_temp_new_i32();
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gen_helper_vfp_get_fpscr(tmp, cpu_env);
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}
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break;
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case ARM_VFP_MVFR2:
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if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
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return 1;
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}
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/* fall through */
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case ARM_VFP_MVFR0:
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case ARM_VFP_MVFR1:
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if (IS_USER(s)
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|| !arm_dc_feature(s, ARM_FEATURE_MVFR)) {
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return 1;
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}
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tmp = load_cpu_field(vfp.xregs[rn]);
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break;
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default:
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return 1;
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}
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} else {
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gen_mov_F0_vreg(0, rn);
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tmp = gen_vfp_mrs();
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}
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if (rd == 15) {
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/* Set the 4 flag bits in the CPSR. */
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gen_set_nzcv(tmp);
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tcg_temp_free_i32(tmp);
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} else {
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store_reg(s, rd, tmp);
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}
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} else {
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/* arm->vfp */
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if (is_sysreg) {
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rn >>= 1;
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/* system register */
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switch (rn) {
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case ARM_VFP_FPSID:
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case ARM_VFP_MVFR0:
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case ARM_VFP_MVFR1:
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/* Writes are ignored. */
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break;
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case ARM_VFP_FPSCR:
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tmp = load_reg(s, rd);
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gen_helper_vfp_set_fpscr(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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gen_lookup_tb(s);
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break;
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case ARM_VFP_FPEXC:
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if (IS_USER(s))
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return 1;
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/* TODO: VFP subarchitecture support.
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* For now, keep the EN bit only */
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tmp = load_reg(s, rd);
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tcg_gen_andi_i32(tmp, tmp, 1 << 30);
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store_cpu_field(tmp, vfp.xregs[rn]);
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gen_lookup_tb(s);
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break;
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case ARM_VFP_FPINST:
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case ARM_VFP_FPINST2:
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if (IS_USER(s)) {
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return 1;
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}
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tmp = load_reg(s, rd);
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store_cpu_field(tmp, vfp.xregs[rn]);
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break;
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default:
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return 1;
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}
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} else {
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tmp = load_reg(s, rd);
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gen_vfp_msr(tmp);
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gen_mov_vreg_F0(0, rn);
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}
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}
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}
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/* already handled by decodetree */
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return 1;
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} else {
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/* data processing */
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bool rd_is_dp = dp;
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@ -62,3 +62,7 @@ VMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \
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VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
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vn=%vn_dp
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VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
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VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \
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vn=%vn_sp
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