Commit Graph

55006 Commits

Author SHA1 Message Date
Richard Henderson
22d716c28e target/alpha: Fix temp leak in gen_bcond
Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18 18:41:55 -10:00
Richard Henderson
bcd2625da5 target/alpha: Merge several flag bytes into ENV->FLAGS
The flags are arranged such that we can manipulate them either
a whole, or as individual bytes.  The computation within
cpu_get_tb_cpu_state is now reduced to a single load and mask.

Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18 18:41:52 -10:00
Richard Henderson
489a0e6410 target/alpha: Copy tb->flags into DisasContext
Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18 18:41:49 -10:00
Richard Henderson
c6d41b363c target/alpha: Remove amask from tb->flags
This value is constant for the cpu and does not need
to be stored within the TB.

Tested-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-18 18:41:46 -10:00
Richard Henderson
ec2eb22ebb target/sh4: Use tcg_gen_lookup_and_goto_ptr
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-28-rth@twiddle.net>
[aurel32: fix whitespace]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:18 +02:00
Richard Henderson
11b7aa234b target/sh4: Implement fsrra
Signed-off-by: Richard Henderson <rth@twiddle.net>

Message-Id: <20170718200255.31647-27-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:18 +02:00
Richard Henderson
61dedf2af7 target/sh4: Add missing FPSCR.PR == 0 checks
Both frchg and fschg require PR == 0, otherwise undefined_operation.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-26-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:18 +02:00
Richard Henderson
907759f997 target/sh4: Implement fpchg
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-25-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:18 +02:00
Richard Henderson
ccae24d498 target/sh4: Introduce CHECK_SH4A
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-24-rth@twiddle.net>
[aurel32: fix conflict]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:18 +02:00
Richard Henderson
7e9f7ca86f target/sh4: Introduce CHECK_FPSCR_PR_*
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-23-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:18 +02:00
Richard Henderson
93dc9c8964 target/sh4: Tidy misc illegal insn checks
Now that we have a do_illegal label, use goto in order
to self-document the forcing of the exception.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-22-rth@twiddle.net>
[aurel32: fix whitespace issues]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:17 +02:00
Richard Henderson
dec4f042a1 target/sh4: Unify code for CHECK_FPU_ENABLED
We do not need to emit N copies of raising an exception.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-21-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:17 +02:00
Richard Henderson
6b98213da9 target/sh4: Unify code for CHECK_PRIVILEGED
We do not need to emit N copies of raising an exception.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-20-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:17 +02:00
Richard Henderson
dec16c6ee8 target/sh4: Unify code for CHECK_NOT_DELAY_SLOT
We do not need to emit N copies of raising an exception.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-19-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:17 +02:00
Richard Henderson
bdcb373902 target/sh4: Simplify 64-bit fp reg-reg move
We do not need to form full 64-bit quantities in order to perform
the move.  This reduces code expansion on 64-bit hosts.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-18-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:17 +02:00
Richard Henderson
4d57fa50d5 target/sh4: Load/store Dr as 64-bit quantities
This enforces proper alignment and makes the register update
more natural.  Note that there is a more serious bug fix for
fmov {DX}Rn,@(R0,Rn) to use a store instead of a load.

Signed-off-by: Richard Henderson <rth@twiddle.net>

Message-Id: <20170718200255.31647-17-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:17 +02:00
Richard Henderson
1e0b21d856 target/sh4: Merge DREG into fpr64 routines
Also add a debugging assert that we did signal illegal opc
for odd double-precision registers.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-16-rth@twiddle.net>
[aurel32: fix whitespace issues]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:17 +02:00
Richard Henderson
0f73753d62 target/sh4: Eliminate unused XREG macro
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-15-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:17 +02:00
Richard Henderson
5c13bad9ec target/sh4: Hoist fp register bank selection
Compute which register bank to use once at the start of translation.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-14-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:17 +02:00
Richard Henderson
e5d8053e76 target/sh4: Pass DisasContext to fpr64 routines
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-13-rth@twiddle.net>
[aurel32: fix whitespace issues]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:16 +02:00
Richard Henderson
7c9f70386d target/sh4: Unify cpu_fregs into FREG
We were treating FREG as an index and REG as a TCGv.
Making FREG return a TCGv is both less confusing and
a step toward cleaner banking of cpu_fregs.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-12-rth@twiddle.net>
[aurel32: fix whitespace issues]
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:16 +02:00
Richard Henderson
3a3bb8d2b5 target/sh4: Hoist register bank selection
Compute which register bank to use once at the start of translation.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-11-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:16 +02:00
Richard Henderson
b0e9c51a00 linux-user/sh4: Clean env->flags on signal boundaries
If a signal is delivered during the execution of a delay slot,
or a gUSA region, clear those bits from the environment so that
the signal handler does not start in that same state.

Cleaning the bits on signal return is paranoid good sense.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-10-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:16 +02:00
Richard Henderson
b0e4f0edf5 linux-user/sh4: Notice gUSA regions during signal delivery
We translate gUSA regions atomically in a parallel context.
But in a serial context a gUSA region may be interrupted.
In that case, restart the region as the kernel would.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-9-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:16 +02:00
Richard Henderson
d6a6cffdd3 target/sh4: Recognize common gUSA sequences
For many of the sequences produced by gcc or glibc,
we can translate these as host atomic operations.
Which saves the need to acquire the exclusive lock.

Signed-off-by: Richard Henderson <rth@twiddle.net>

Message-Id: <20170718200255.31647-8-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:16 +02:00
Richard Henderson
4bfa602bc2 target/sh4: Handle user-space atomics
For uniprocessors, SH4 uses optimistic restartable atomic sequences.
Upon an interrupt, a real kernel would simply notice magic values in
the registers and reset the PC to the start of the sequence.

For QEMU, we cannot do this in quite the same way.  Instead, we notice
the normal start of such a sequence (mov #-x,r15), and start a new TB
that can be executed under cpu_exec_step_atomic.

Reported-by: Bruno Haible  <bruno@clisp.org>
LP: https://bugs.launchpad.net/bugs/1701971
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-7-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:16 +02:00
Richard Henderson
1516184d8e target/sh4: Adjust TB_FLAG_PENDING_MOVCA
Don't leave an unused bit after DELAY_SLOT_MASK.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-6-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:16 +02:00
Richard Henderson
ca69176d52 target/sh4: Keep env->flags clean
If we mask off any out-of-band bits before we assign to the
variable, then we don't need to clean it up when reading.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-5-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:16 +02:00
Richard Henderson
e1933d1435 target/sh4: Introduce TB_FLAG_ENVFLAGS_MASK
We'll be putting more things into this bitmask soon.
Let's have a name that covers all possible uses.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-4-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:15 +02:00
Richard Henderson
4448a83606 target/sh4: Consolidate end-of-TB tests
We can fold 3 different tests within the decode loop
into a more accurate computation of max_insns to start.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170718200255.31647-3-rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:15 +02:00
Aurelien Jarno
92f1f83e34 target/sh4: return result of fcmp using TCG
Since that the T bit of the SR register is mapped using a TGC global,
it's better to return the value through TCG than writing it directly. It
allows to declare the helpers with the flag TCG_CALL_NO_WG.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20170702202814.27793-5-aurelien@aurel32.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:15 +02:00
Aurelien Jarno
82e8251374 target/sh4: do not use a helper to implement fneg
There is no need to use a helper to flip one bit, just use a TCG xor
instruction instead.

Message-Id: <20170702202814.27793-5-aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:15 +02:00
Aurelien Jarno
801f4dac57 target/sh4: fix FPSCR cause vs flag inversion
The floating-point status/control register contains cause and flag
bits. The cause bits are set to 0 before executing the instruction,
while the flag bits hold the status of the exception generated after
the field was last cleared.

Message-Id: <20170702202814.27793-4-aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:15 +02:00
Aurelien Jarno
fea7d77d3e target/sh4: fix FPU unorderered compare
In case of unordered compare, the fcmp instructions should either
trigger and invalid exception (if enabled) or set T=0. The existing code
left it unchanged.

LP: https://bugs.launchpad.net/qemu/+bug/1701821
Reported-by: Bruno Haible <bruno@clisp.org>
Message-Id: <20170702202814.27793-3-aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:15 +02:00
Aurelien Jarno
57f5c1b093 target/sh4: do not check for PR bit for fabs instruction
The SH4 manual is not fully clear about that, but real hardware do not
check for the PR bit, which allows to select between single or double
precision, for the fabs instruction. This is probably what is meant by
"Same operation is performed regardless of precision."

Remove the check, and at the same time use a TCG instruction instead of
a helper to clear one bit.

LP: https://bugs.launchpad.net/qemu/+bug/1701821
Reported-by: Bruno Haible <bruno@clisp.org>
Message-Id: <20170702202814.27793-2-aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2017-07-18 23:39:15 +02:00
Igor Druzhinin
331b5189d7 xen: don't use xenstore to save/restore physmap anymore
If we have a system with xenforeignmemory_map2() implemented
we don't need to save/restore physmap on suspend/restore
anymore. In case we resume a VM without physmap - try to
recreate the physmap during memory region restore phase and
remap map cache entries accordingly. The old code is left
for compatibility reasons.

Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com>
Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18 14:16:52 -07:00
Igor Druzhinin
5ba3d75645 xen/mapcache: introduce xen_replace_cache_entry()
This new call is trying to update a requested map cache entry
according to the changes in the physmap. The call is searching
for the entry, unmaps it and maps again at the same place using
a new guest address. If the mapping is dummy this call will
make it real.

This function makes use of a new xenforeignmemory_map2() call
with an extended interface that was recently introduced in
libxenforeignmemory [1].

[1] https://www.mail-archive.com/xen-devel@lists.xen.org/msg113007.html

Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com>
Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18 14:16:09 -07:00
Igor Druzhinin
759235653d xen/mapcache: add an ability to create dummy mappings
Dummys are simple anonymous mappings that are placed instead
of regular foreign mappings in certain situations when we need
to postpone the actual mapping but still have to give a
memory region to QEMU to play with.

This is planned to be used for restore on Xen.

Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com>
Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18 14:12:20 -07:00
Igor Druzhinin
697b66d006 xen: move physmap saving into a separate function
Non-functional change.

Signed-off-by: Igor Druzhinin <igor.druzhinin@citrix.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Paul Durrant <paul.durrant@citrix.com>
2017-07-18 14:12:19 -07:00
Stefano Stabellini
04d6da4ff6 xen-platform: separate unplugging of NVMe disks
Commit 090fa1c8 "add support for unplugging NVMe disks..." extended the
existing disk unplug flag to cover NVMe disks as well as IDE and SCSI.

The recent thread on the xen-devel mailing list [1] has highlighted that
this is not desirable behaviour: PV frontends should be able to distinguish
NVMe disks from other types of disk and should have separate control over
whether they are unplugged.

This patch defines a new bit in the unplug mask for this purpose (see Xen
commit [2]) and also tidies up the definitions of, and improves the
comments regarding, the previously exiting bits in the protocol.

[1] https://lists.xen.org/archives/html/xen-devel/2017-03/msg02924.html
[2] http://xenbits.xen.org/gitweb/?p=xen.git;a=commit;h=1096aa02

Signed-off-by: Paul Durrant <paul.durrant@citrix.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18 14:12:06 -07:00
Peter Maydell
64c7c1175b xen_pt_msi.c: Check for xen_host_pci_get_* failures in xen_pt_msix_init()
Check the return status of the xen_host_pci_get_* functions we call in
xen_pt_msix_init(), and fail device init if the reads failed rather than
ploughing ahead. (Spotted by Coverity: CID 777338.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18 13:27:04 -07:00
Xiong Zhang
a19bae42e3 hw/xen: Set emu_mask for igd_opregion register
In igd passthrough environment, guest could only access opregion at the
first bootup time. Once guest shutdown, later guest couldn't access
opregion anymore.
This is because qemu set emulated guest opregion base address to host
register. Later guest get a wrong host opregion base address, and couldn't
access it anymore.

This patch set emu_mask for igd_opregion register, so guest won't set
guest opregion base address to host.

Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>
2017-07-18 13:26:35 -07:00
Peter Maydell
6887dc6700 s390: add z14 cpu model
- add a CPU model for the IBM z14 which was announced on July 17th 2017
 - update linux headers to 4.13-rc0 to get a fix for an ioctl definition
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJZbc04AAoJEBF7vIC1phx8xxkP/Rf/Y7jCvFzDXvE2+tJwkETi
 9l6un+gyoW64l4vI7RDT7wTl/A7uBNxZxJMXprFKaE2Kcg3D8IWdFq/RudmuJCJ5
 SzY4X/L1kWHdKxVzeEF6RVqKfeNnA2Hk4KggzDMqpXxztjenvJiJYHqL0n3+edLS
 LHfi4z5PMzXHMF9plE7Usw0GMp+8HzVe3Bk/d+gqBMG9TDTPJXdGP/E9FEDij4dE
 GcNNmilzowkz9JZh5Gw92oq7iLXoCMbf9QUiu5IF1Gqd/kw9tFYzWtq26nR8GJyf
 sr7DeNbUiOi6xJA/CWTwwlwS3FZXXNjbQPumRfP1kRllyHKyRIAHxhKVJajTDgQg
 FVZ46GAWuUnK38COhkuNN67zoH8YzRgHwn/Ls6RxTtGlJe1xlg2GgNJSxavWh6FE
 Hwr1twe13A/QyFN7dVyy52F/WYIPxggwUqEE7Xh5YL3eDIaPuC/2bKS5pTZmGrJZ
 47S+FwBGPvkt2+DmpynCShN1APpLLH+Ap448twYkEbOqoYMD8zoqZj2LPtZA13Rp
 htb56v0bRgTFrLQcIpUn+QeIsIgAde/FQl6PvbQujVJlwUG8mYCiin/4brVXRRFr
 JCEKjSf7qEDEnK2SAefdIlrpeQT9kBuHpWW8/pLhEuJMQpTk2qwUwOlN4AKaJb0T
 acsUZwXSl4hGR3L7k/VL
 =jOvs
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20170718' into staging

s390: add z14 cpu model

- add a CPU model for the IBM z14 which was announced on July 17th 2017
- update linux headers to 4.13-rc0 to get a fix for an ioctl definition

# gpg: Signature made Tue 18 Jul 2017 09:56:24 BST
# gpg:                using RSA key 0x117BBC80B5A61C7C
# gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>"
# Primary key fingerprint: F922 9381 A334 08F9 DBAB  FBCA 117B BC80 B5A6 1C7C

* remotes/borntraeger/tags/s390x-20170718:
  s390x/cpumodel: z14 cpu models
  linux header sync against v4.13-rc1

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18 21:13:48 +01:00
Peter Maydell
f9dada2baa -----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJZbYtHAAoJEL2+eyfA3jBXpFEP/1MYXG9Rwq3LF4sseoJv0vzq
 vyLVCj13/KNQUqyqLjz+zu72F266MGUrz43TLDwyPUk4gf12fNEDeRYQun16P7l6
 fcw4LdIfp21xQctSlTkH0s8d9CSHm3UciQEbJua4TyRL/a8V9vuVljmA5HGGNerO
 Cy3jWWVcxJlPuUPDQxeCjvpLGB2/89TfEUvUMgC4wd6qKLhiGBl8L2mRHEtEsF8n
 Q0DPUHDE3q88rWFiT/fgzJOl+CdGi6DlemcKb7CkB27xoI4LKYe3b5+ffC7fOEEX
 TG237kUYB4mJAMbV23epqi92vTX7rqm6B3rMVnKawd+VCXnYn8WjDyhCy22WB7gr
 Oup6ty9fx0MYRbex3KDjOHP9Srif6fFAWauEs0ulG63b8CbTkD3KriCz7HnXZ1Gt
 DwgWnMLZhEqU+cmJgSHzzcu0V8JB54tV38UcjMEtpr5f4Bzs2TNmf4HnhkeWr68w
 Yh6LHgLxS5CzVUm9CJA9b7HSZT3X8WDpUHbcJMPZ/OepbegeiMNKkXRy2F5DW2Gu
 WJliDtq6tO6WDTqIHBg5WDWaZUV74CPhfwaDZRj/N9Ry/PDvcqjC2nQRoevm01S9
 l2lXdqN2cU3aj40j6fCWNPFN+Ua9j4Hslz6mPU2P6hIU0JlWBCLDNhrf8SNGMWQA
 nviOfK6GU5wf5xHUkD29
 =NkPl
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into staging

# gpg: Signature made Tue 18 Jul 2017 05:15:03 BST
# gpg:                using RSA key 0xBDBE7B27C0DE3057
# gpg: Good signature from "Jeffrey Cody <jcody@redhat.com>"
# gpg:                 aka "Jeffrey Cody <jeff@codyprime.org>"
# gpg:                 aka "Jeffrey Cody <codyprime@gmail.com>"
# Primary key fingerprint: 9957 4B4D 3474 90E7 9D98  D624 BDBE 7B27 C0DE 3057

* remotes/cody/tags/block-pull-request:
  live-block-ops.txt: Rename, rewrite, and improve it
  bitmaps.md: Convert to rST; move it into 'interop' dir

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18 20:29:36 +01:00
Peter Maydell
20df6c7689 nbd patches for 2017-07-17
- Eric Blake: nbd: Fix iotests failure due to changed client error message
 - Eric Blake: [0/2] NBD fixes before softfreeze
 -----BEGIN PGP SIGNATURE-----
 Comment: Public key at http://people.redhat.com/eblake/eblake.gpg
 
 iQEcBAABCAAGBQJZbTZEAAoJEKeha0olJ0Nq5poH/2EnzfmMWt7WwZS194c371T5
 KTCJqa4kGWuESsbHT00HKuw2Q8+AOIwxT6VP4eFSeyKphBkWEeer3ethhsMzSN59
 Kyh+AxYDxul3YA1MAR38maMS7bpSvTu6tHVQB+d3qamCCWkil4aBtLdn0ci6esNf
 z5OhaA5sq4Cli72YljJXheqGLKlPxuX2oKDb3/uiwWNj2kev9tKLAKfnfNMd9aFe
 Kmu7k5up79N/cQHWJ/l1OlRg220/Nx9m8fuDtsqT2ul2LC7xZ88ALuhqzbCyUBR8
 vysFUDP9FB4zEnEtbuDjHJEItoA1o5CMFqpH89ink/+sEatAVlRjrZ9NxYTR6Fw=
 =s+TQ
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2017-07-17' into staging

nbd patches for 2017-07-17

- Eric Blake: nbd: Fix iotests failure due to changed client error message
- Eric Blake: [0/2] NBD fixes before softfreeze

# gpg: Signature made Mon 17 Jul 2017 23:12:20 BST
# gpg:                using RSA key 0xA7A16B4A2527436A
# gpg: Good signature from "Eric Blake <eblake@redhat.com>"
# gpg:                 aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>"
# gpg:                 aka "[jpeg image of size 6874]"
# Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2  F3AA A7A1 6B4A 2527 436A

* remotes/ericb/tags/pull-nbd-2017-07-17:
  nbd: Fix server reply to NBD_OPT_EXPORT_NAME of older clients
  nbd: Trace client command being sent
  nbd: Fix iotests failure due to changed client error message

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18 18:29:35 +01:00
Peter Maydell
ff3351d449 Queued s390x tcg patches, v2
-----BEGIN PGP SIGNATURE-----
 
 iQEcBAABAgAGBQJZbSqPAAoJEK0ScMxN0Ceb4k4H/Rzr1EuPTW+ulL9eKVOhEqYP
 YxUQzdDRlYHuuIz/X2UauVLTmf6tTEpJMjgLDU1EmaQhv6LC2u552SBvjJG9r+G5
 opE5BIELZ6021oUmsdjhGLfJtTdOnS1eUaAh0HSeqrsJBRd+cuG0r0EoQv9A5BTc
 uEsvtgFbvKDsy87biVyoaiId0aq+tPo7laOBTnU73m9XJeXK+uXbVOdastvzJAP1
 Szm4H3z436JR/KOFrchCuFK1w79abeOk/vIR7h0VwWXvyed/T/rvxtS8V5iZwLpg
 Qmmq4HzmgjVZbscHRp2pyDz9/5+sJJYs9GylorLpIL7UdUfvkQEEa7BaYu9O1Xg=
 =cM42
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/rth/tags/pull-s390-20170717' into staging

Queued s390x tcg patches, v2

# gpg: Signature made Mon 17 Jul 2017 22:22:23 BST
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-s390-20170717:
  target/s390x: Fix risbg handling
  target/s390x: Allow to enable "idtes" feature for TCG
  target/s390x: Mark ETF3 and ETF3_ENH facilities as available
  target/s390x: Implement TRTR
  target/s390x: Implement SRSTU
  target/s390x: Tidy SRST
  target/s390x: Implement CONVERT UNICODE insns
  target/s390x: Implement CSST

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-18 17:54:51 +01:00
Dr. David Alan Gilbert
ff0ca96234 tests/ahci-test: Be mean with RAM
The migration tests used two VMs each with -m 1024 this caused
problems when run in some small, pessimistic test VMs (netbsd).
We can just be meaner with the amount of RAM in the test and use -m 384

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-id: 20170714152820.24034-1-dgilbert@redhat.com
Reviewed-by: John Snow <jsnow@redhat.com>
Signed-off-by: John Snow <jsnow@redhat.com>
2017-07-18 11:47:57 -04:00
John Snow
70e2337030 ahci: split public and private interface
Complete the split by renaming ahci_public.h --> ahci.h and
moving the current ahci.h to hw/ide/ahci_internal.h.

Adjust ahci_internal.h to now load ahci.h instead of ahci_public.h.

Finalize the split by switching external users to the new header.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170623220926.11479-4-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2017-07-18 11:47:57 -04:00
John Snow
5402fda5ad ahci: Isolate public AHCI interface
Begin separating the public/private interface by removing the minimum
set of information used by code outside of hw/ide/ and calling this
a new ahci_public.h file, which will be renamed to ahci.h in a future
patch.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170623220926.11479-3-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2017-07-18 11:47:57 -04:00
John Snow
bbe3179a13 ahci: add ahci_get_num_ports
Instead of reaching into the PCI state, allow the AHCIDevice to
respond with how many ports it has.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20170623220926.11479-2-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2017-07-18 11:47:56 -04:00