Philippe Mathieu-Daudé 19b293472f target/avr/disas: Fix store instructions display order ... While LOAD instructions use the target register as first argument, STORE instructions use it as second argument: LD Rd, X // Rd <- (X) ST Y, Rd // (Y) <- Rr Reported-by: Joaquin de Andres <me@xcancerberox.com.ar> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200707070021.10031-4-f4bug@amsat.org>		2020-07-11 11:02:05 +02:00
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alpha
arm	error: Eliminate error_propagate() with Coccinelle, part 1	2020-07-10 15:18:08 +02:00
avr	target/avr/disas: Fix store instructions display order	2020-07-11 11:02:05 +02:00
cris
hppa
i386	error: Eliminate error_propagate() manually	2020-07-10 15:18:08 +02:00
lm32
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2020-07-06 21:39:57 +02:00
microblaze
mips	hw/mips: Implement the kvm_type() hook in MachineClass	2020-06-27 19:35:39 +02:00
moxie
nios2
openrisc
ppc	error: Eliminate error_propagate() with Coccinelle, part 1	2020-07-10 15:18:08 +02:00
riscv	target/riscv: configure and turn on vector extension from command line	2020-07-02 09:19:34 -07:00
rx
s390x	error: Eliminate error_propagate() with Coccinelle, part 1	2020-07-10 15:18:08 +02:00
sh4
sparc	error: Eliminate error_propagate() with Coccinelle, part 1	2020-07-10 15:18:08 +02:00
tilegx
tricore
unicore32	target/unicore32: Prefer qemu_semihosting_log_out() over curses	2020-06-09 19:58:53 +02:00
xtensa	target/xtensa fixes for 5.1:	2020-06-25 21:20:45 +01:00