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xemu/target/avr
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Philippe Mathieu-Daudé 19b293472f target/avr/disas: Fix store instructions display order 
While LOAD instructions use the target register as first
argument, STORE instructions use it as second argument:

  LD Rd, X        // Rd <- (X)

  ST Y, Rd        // (Y) <- Rr

Reported-by: Joaquin de Andres <me@xcancerberox.com.ar>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200707070021.10031-4-f4bug@amsat.org>
2020-07-11 11:02:05 +02:00
..
cpu-param.h
…
cpu-qom.h
…
cpu.c
target/avr/cpu: Fix $PC displayed address
2020-07-11 11:02:05 +02:00
cpu.h
target/avr: Add support for disassembling via option '-d in_asm'
2020-07-11 11:02:05 +02:00
disas.c
target/avr/disas: Fix store instructions display order
2020-07-11 11:02:05 +02:00
gdbstub.c
target/avr: CPU class: Add GDB support
2020-07-10 17:58:32 +02:00
helper.c
target/avr: Add instruction helpers
2020-07-11 11:02:05 +02:00
helper.h
target/avr: Add instruction helpers
2020-07-11 11:02:05 +02:00
insn.decode
target/avr: Add instruction translation - MCU Control Instructions
2020-07-11 11:02:05 +02:00
machine.c
target/avr: CPU class: Add migration support
2020-07-10 17:58:32 +02:00
Makefile.objs
target/avr: Register AVR support with the rest of QEMU
2020-07-11 11:02:05 +02:00
translate.c
target/avr: Add support for disassembling via option '-d in_asm'
2020-07-11 11:02:05 +02:00