xemu/target/openrisc
Richard Henderson 1cc9e5d896 target/openrisc: Increase the TLB size
The architecture supports 128 TLB entries.  There is no reason
not to provide all of them.  In the process we need to fix a
bug that failed to parameterize the configuration register that
tells the operating system the number of entries.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>

---
v2:
  - Change VMState version.
2018-07-03 00:05:28 +09:00
..
cpu.c target/openrisc: Increase the TLB size 2018-07-03 00:05:28 +09:00
cpu.h target/openrisc: Increase the TLB size 2018-07-03 00:05:28 +09:00
disas.c target/openrisc: Add print_insn_or1k 2018-07-03 00:05:28 +09:00
exception_helper.c misc: remove duplicated includes 2017-12-18 17:07:02 +03:00
exception.c
exception.h
fpu_helper.c target-openrisc: Write back result before FPE exception 2018-05-14 14:35:02 -07:00
gdbstub.c target/openrisc: implement shadow registers 2017-05-04 09:39:01 +09:00
helper.h target/openrisc: Form the spr index from tcg 2018-07-03 00:05:28 +09:00
insns.decode target/openrisc: Convert dec_float 2018-05-14 14:55:29 -07:00
interrupt_helper.c target/openrisc: Fix cpu_mmu_index 2018-07-03 00:05:28 +09:00
interrupt.c target/openrisc: Fix cpu_mmu_index 2018-07-03 00:05:28 +09:00
machine.c target/openrisc: Increase the TLB size 2018-07-03 00:05:28 +09:00
Makefile.objs target/openrisc: Merge mmu_helper.c into mmu.c 2018-07-03 00:05:28 +09:00
mmu.c target/openrisc: Stub out handle_mmu_fault for softmmu 2018-07-03 00:05:28 +09:00
sys_helper.c target/openrisc: Use identical sizes for ITLB and DTLB 2018-07-03 00:05:28 +09:00
translate.c target/openrisc: Fix cpu_mmu_index 2018-07-03 00:05:28 +09:00