Eduardo Habkost e33d22fab3 piix: Document coreboot-specific RAM size config register ... The existing i440fx initialization code sets a PCI config register that isn't documented anywhere in the Intel 440FX datasheet. Register 0x57 is DRAMC (DRAM Control) and has nothing to do with the RAM size. This was implemented in commit ec5f92ce6a because old coreboot code tried to read registers 0x5a-0x5f,0x56,0x57 to get the RAM size from QEMU, but I couldn't find out why coreboot did that. I assume it was a mistake, and the original code was supposed to be reading the DRB[0-7] registers (offsets 0x60-0x67). Document that coreboot-specific register offset in a macro and a comment, for future reference. Cc: Ed Swierk <eswierk@skyportsystems.com> Cc: Richard Smith <smithbone@gmail.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2015-08-13 14:08:25 +03:00
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apb.c	Switch non-CPU callers from ld/st*_phys to address_space_ld/st*	2015-04-26 16:49:24 +01:00
bonito.c	Convert (ffs(val) - 1) to ctz32(val)	2015-04-28 15:36:08 +02:00
gpex.c	pci: Add generic PCIe host bridge	2015-02-13 05:46:07 +00:00
grackle.c	pci: Trivial device model conversions to realize	2015-02-26 12:42:16 +01:00
Makefile.objs	pci: Add generic PCIe host bridge	2015-02-13 05:46:07 +00:00
pam.c	hw/i386: remove smram_update	2015-06-05 17:36:39 +02:00
piix.c	piix: Document coreboot-specific RAM size config register	2015-08-13 14:08:25 +03:00
ppce500.c	pci: Trivial device model conversions to realize	2015-02-26 12:42:16 +01:00
prep.c	exec.c: Make address_space_rw take transaction attributes	2015-04-26 16:49:24 +01:00
q35.c	q35: implement TSEG	2015-06-05 19:45:13 +02:00
uninorth.c	uninorth: convert ffs(3) to ctz32()	2015-04-28 15:36:08 +02:00
versatile.c	pci: Trivial device model conversions to realize	2015-02-26 12:42:16 +01:00