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xemu/target/riscv
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Emmanuel Blot 6cfcf77573 target/riscv: fix a typo with interrupt names 
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-05-11 20:02:07 +10:00
..
insn_trans
riscv: Add semihosting support
2021-01-18 10:05:06 +00:00
arch_dump.c
target-riscv: support QMP dump-guest-memory
2021-03-04 09:43:29 -05:00
cpu_bits.h
target/riscv: Define ePMP mseccfg
2021-05-11 20:02:06 +10:00
cpu_helper.c
target/riscv: fix exception index on instruction access fault
2021-05-11 20:02:07 +10:00
cpu_user.h
Supply missing header guards
2019-06-12 13:20:21 +02:00
cpu-param.h
target/riscv: Add a virtualised MMU Mode
2020-11-09 15:08:45 -08:00
cpu.c
target/riscv: fix a typo with interrupt names
2021-05-11 20:02:07 +10:00
cpu.h
target/riscv: Add a config option for ePMP
2021-05-11 20:02:06 +10:00
csr.c
target/riscv: Add ePMP CSR access functions
2021-05-11 20:02:06 +10:00
fpu_helper.c
target/riscv: fpu_helper: Match function defs in HELPER macros
2020-12-17 21:56:44 -08:00
gdbstub.c
target/riscv: Use RISCVException enum for CSR access
2021-05-11 20:02:06 +10:00
helper.h
target/riscv: fpu_helper: Match function defs in HELPER macros
2020-12-17 21:56:44 -08:00
insn16-32.decode
target/riscv: Split RVC32 and RVC64 insns into separate files
2019-05-24 12:09:22 -07:00
insn16-64.decode
target/riscv: Add checks for several RVC reserved operands
2019-05-24 12:09:25 -07:00
insn16.decode
target/riscv: Add checks for several RVC reserved operands
2019-05-24 12:09:25 -07:00
insn32-64.decode
target/riscv: Allow generating hlv/hlvx/hsv instructions
2020-08-25 09:11:35 -07:00
insn32.decode
target/riscv: Allow generating hlv/hlvx/hsv instructions
2020-08-25 09:11:35 -07:00
instmap.h
target/riscv: progressively load the instruction during decode
2020-02-25 20:20:23 +00:00
internals.h
target/riscv: Add basic vmstate description of CPU
2020-11-03 07:17:23 -08:00
machine.c
target/riscv: Remove privilege v1.9 specific CSR related code
2021-05-11 20:01:10 +10:00
meson.build
target-riscv: support QMP dump-guest-memory
2021-03-04 09:43:29 -05:00
monitor.c
hmp: Pass monitor to mon_get_cpu_env()
2020-11-13 12:45:51 +00:00
op_helper.c
target/riscv: Use RISCVException enum for CSR access
2021-05-11 20:02:06 +10:00
pmp.c
target/riscv/pmp: Remove outdated comment
2021-05-11 20:02:06 +10:00
pmp.h
target/riscv: Add ePMP CSR access functions
2021-05-11 20:02:06 +10:00
trace-events
target/riscv: Add ePMP CSR access functions
2021-05-11 20:02:06 +10:00
trace.h
trace: switch position of headers to what Meson requires
2020-08-21 06:18:24 -04:00
translate.c
target/riscv: Remove privilege v1.9 specific CSR related code
2021-05-11 20:01:10 +10:00
vector_helper.c
target/riscv: fix vrgather macro index variable type bug
2021-05-11 20:02:07 +10:00