Frédéric Pétrot 332dab6878 target/riscv: setup everything for rv64 to support rv128 execution ... This patch adds the support of the '-cpu rv128' option to qemu-system-riscv64 so that we can indicate that we want to run rv128 executables. Still, there is no support for 128-bit insns at that stage so qemu fails miserably (as expected) if launched with this option. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr [ Changed by AF - Rename CPU to "x-rv128" ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-01-08 15:46:10 +10:00
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libvixl	disas/libvixl: Protect C system header for C++ compiler	2021-05-25 16:01:43 +01:00
alpha.c
arm-a64.cc	include/disas/dis-asm.h: Handle being included outside 'extern "C"'	2021-05-10 17:21:54 +01:00
arm.c
capstone.c	disas: Push const down through host disassembly	2021-01-07 05:09:42 -10:00
cris.c	cris: do not leak struct cris_disasm_data	2019-10-04 18:49:17 +02:00
hexagon.c	Hexagon (disas/hexagon.c) fix memory leak for early exit cases	2021-08-12 09:06:05 -05:00
hppa.c	disas/: fix some comment spelling errors	2020-09-17 20:40:08 +02:00
i386.c
m68k.c	disas/: fix some comment spelling errors	2020-09-17 20:40:08 +02:00
meson.build	Drop the deprecated lm32 target	2021-05-12 18:20:25 +02:00
microblaze.c
mips.c	target/mips: Add implementation of GINVT instruction	2020-01-29 19:28:52 +01:00
nanomips.cpp	include/disas/dis-asm.h: Handle being included outside 'extern "C"'	2021-05-10 17:21:54 +01:00
nanomips.h
nios2.c	disas/nios2: Simplify endianess conversion	2021-10-22 18:07:30 +02:00
ppc.c	disas/: fix some comment spelling errors	2020-09-17 20:40:08 +02:00
riscv.c	target/riscv: setup everything for rv64 to support rv128 execution	2022-01-08 15:46:10 +10:00
s390.c
sh4.c	disas/sh4: Add missing fallthrough annotations	2020-07-13 11:40:52 +02:00
sparc.c
xtensa.c