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The core SJA1000 support is independent of following patches which map SJA1000 chip to PCI boards. The work is based on Jin Yang GSoC 2013 work funded by Google and mentored in frame of RTEMS project GSoC slot donated to QEMU. Rewritten for QEMU-2.0+ versions and architecture cleanup by Pavel Pisa (Czech Technical University in Prague). Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
147 lines
6.1 KiB
C
147 lines
6.1 KiB
C
/*
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* CAN device - SJA1000 chip emulation for QEMU
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*
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* Copyright (c) 2013-2014 Jin Yang
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* Copyright (c) 2014-2018 Pavel Pisa
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*
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* Initial development supported by Google GSoC 2013 from RTEMS project slot
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef HW_CAN_SJA1000_H
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#define HW_CAN_SJA1000_H
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#include "net/can_emu.h"
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#define CAN_SJA_MEM_SIZE 128
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/* The max size for a message buffer, EFF and DLC=8, DS-p39 */
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#define SJA_MSG_MAX_LEN 13
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/* The receive buffer size. */
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#define SJA_RCV_BUF_LEN 64
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typedef struct CanSJA1000State {
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/* PeliCAN state and registers sorted by address */
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uint8_t mode; /* 0 .. Mode register, DS-p26 */
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/* 1 .. Command register */
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uint8_t status_pel; /* 2 .. Status register, p15 */
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uint8_t interrupt_pel; /* 3 .. Interrupt register */
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uint8_t interrupt_en; /* 4 .. Interrupt Enable register */
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uint8_t rxmsg_cnt; /* 29 .. RX message counter. DS-p49 */
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uint8_t rxbuf_start; /* 30 .. RX buffer start address, DS-p49 */
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uint8_t clock; /* 31 .. Clock Divider register, DS-p55 */
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uint8_t code_mask[8]; /* 16~23 */
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uint8_t tx_buff[13]; /* 96~108 .. transmit buffer */
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/* 10~19 .. transmit buffer for BasicCAN */
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uint8_t rx_buff[SJA_RCV_BUF_LEN]; /* 32~95 .. 64bytes Rx FIFO */
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uint32_t rx_ptr; /* Count by bytes. */
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uint32_t rx_cnt; /* Count by bytes. */
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/* PeliCAN state and registers sorted by address */
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uint8_t control; /* 0 .. Control register */
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/* 1 .. Command register */
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uint8_t status_bas; /* 2 .. Status register */
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uint8_t interrupt_bas; /* 3 .. Interrupt register */
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uint8_t code; /* 4 .. Acceptance code register */
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uint8_t mask; /* 5 .. Acceptance mask register */
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qemu_can_filter filter[4];
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qemu_irq irq;
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CanBusClientState bus_client;
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} CanSJA1000State;
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/* PeliCAN mode */
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enum SJA1000_PeliCAN_regs {
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SJA_MOD = 0x00, /* Mode control register */
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SJA_CMR = 0x01, /* Command register */
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SJA_SR = 0x02, /* Status register */
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SJA_IR = 0x03, /* Interrupt register */
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SJA_IER = 0x04, /* Interrupt Enable */
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SJA_BTR0 = 0x06, /* Bus Timing register 0 */
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SJA_BTR1 = 0x07, /* Bus Timing register 1 */
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SJA_OCR = 0x08, /* Output Control register */
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SJA_ALC = 0x0b, /* Arbitration Lost Capture */
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SJA_ECC = 0x0c, /* Error Code Capture */
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SJA_EWLR = 0x0d, /* Error Warning Limit */
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SJA_RXERR = 0x0e, /* RX Error Counter */
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SJA_TXERR0 = 0x0e, /* TX Error Counter */
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SJA_TXERR1 = 0x0f,
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SJA_RMC = 0x1d, /* Rx Message Counter
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* number of messages in RX FIFO
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*/
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SJA_RBSA = 0x1e, /* Rx Buffer Start Addr
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* address of current message
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*/
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SJA_FRM = 0x10, /* Transmit Buffer
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* write: Receive Buffer
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* read: Frame Information
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*/
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/*
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* ID bytes (11 bits in 0 and 1 for standard message or
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* 16 bits in 0,1 and 13 bits in 2,3 for extended message)
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* The most significant bit of ID is placed in MSB
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* position of ID0 register.
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*/
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SJA_ID0 = 0x11, /* ID for standard and extended frames */
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SJA_ID1 = 0x12,
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SJA_ID2 = 0x13, /* ID cont. for extended frames */
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SJA_ID3 = 0x14,
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SJA_DATS = 0x13, /* Data start standard frame */
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SJA_DATE = 0x15, /* Data start extended frame */
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SJA_ACR0 = 0x10, /* Acceptance Code (4 bytes) in RESET mode */
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SJA_AMR0 = 0x14, /* Acceptance Mask (4 bytes) in RESET mode */
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SJA_PeliCAN_AC_LEN = 4, /* 4 bytes */
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SJA_CDR = 0x1f /* Clock Divider */
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};
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/* BasicCAN mode */
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enum SJA1000_BasicCAN_regs {
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SJA_BCAN_CTR = 0x00, /* Control register */
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SJA_BCAN_CMR = 0x01, /* Command register */
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SJA_BCAN_SR = 0x02, /* Status register */
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SJA_BCAN_IR = 0x03 /* Interrupt register */
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};
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void can_sja_hardware_reset(CanSJA1000State *s);
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void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val,
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unsigned size);
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uint64_t can_sja_mem_read(CanSJA1000State *s, hwaddr addr, unsigned size);
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int can_sja_connect_to_bus(CanSJA1000State *s, CanBusState *bus);
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void can_sja_disconnect(CanSJA1000State *s);
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int can_sja_init(CanSJA1000State *s, qemu_irq irq);
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int can_sja_can_receive(CanBusClientState *client);
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ssize_t can_sja_receive(CanBusClientState *client,
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const qemu_can_frame *frames, size_t frames_cnt);
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extern const VMStateDescription vmstate_can_sja;
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#endif
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