Rui Wang e913bace61 target/loongarch: Fix return value of CHECK_FPE ... Regarding the patchset v3 has been merged into main line, and not approved, this patch updates to patchset v4. Fixes: 2419978c ("target/loongarch: Fix emulation of float-point disable exception") Link: https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg00808.html Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Rui Wang <wangrui@loongson.cn> Message-Id: <20221107024526.702297-3-wangrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>		2022-11-07 10:54:11 +08:00
..
trans_arith.c.inc
trans_atomic.c.inc	target/loongarch: Add fixed point atomic instruction translation	2022-06-06 18:09:03 +00:00
trans_bit.c.inc	target/loongarch: bstrins.w src register need EXT_NONE	2022-10-17 10:28:35 +08:00
trans_branch.c.inc	target/loongarch: Add branch instruction translation	2022-06-06 18:09:03 +00:00
trans_extra.c.inc	target/loongarch: Add timer related instructions support.	2022-06-06 18:09:03 +00:00
trans_farith.c.inc	target/loongarch: Fix return value of CHECK_FPE	2022-11-07 10:54:11 +08:00
trans_fcmp.c.inc	target/loongarch: Fix emulation of float-point disable exception	2022-11-04 17:10:53 +08:00
trans_fcnv.c.inc	target/loongarch: Add floating point conversion instruction translation	2022-06-06 18:09:03 +00:00
trans_fmemory.c.inc	target/loongarch: Fix emulation of float-point disable exception	2022-11-04 17:10:53 +08:00
trans_fmov.c.inc	target/loongarch: Fix emulation of float-point disable exception	2022-11-04 17:10:53 +08:00
trans_memory.c.inc	target/loongarch: Add fixed point atomic instruction translation	2022-06-06 18:09:03 +00:00
trans_privileged.c.inc	target/loongarch: Separate the hardware flags into MMU index and PLV	2022-11-07 10:54:08 +08:00
trans_shift.c.inc