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https://github.com/xemu-project/xemu.git
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ee86bd58b8
This includes: - BEQ, BNE, BLT[U], BGE[U] - BEQZ, BNEZ - B - BL - JIRL - BCEQZ, BCNEZ Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-16-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
84 lines
2.3 KiB
C++
84 lines
2.3 KiB
C++
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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static bool trans_b(DisasContext *ctx, arg_b *a)
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{
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gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static bool trans_bl(DisasContext *ctx, arg_bl *a)
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{
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tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
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gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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tcg_gen_addi_tl(cpu_pc, src1, a->offs);
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tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
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gen_set_gpr(a->rd, dest, EXT_NONE);
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tcg_gen_lookup_and_goto_ptr();
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ctx->base.is_jmp = DISAS_NORETURN;
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return true;
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}
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static void gen_bc(DisasContext *ctx, TCGv src1, TCGv src2,
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target_long offs, TCGCond cond)
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{
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TCGLabel *l = gen_new_label();
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tcg_gen_brcond_tl(cond, src1, src2, l);
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gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
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gen_set_label(l);
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gen_goto_tb(ctx, 0, ctx->base.pc_next + offs);
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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static bool gen_rr_bc(DisasContext *ctx, arg_rr_offs *a, TCGCond cond)
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{
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);
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gen_bc(ctx, src1, src2, a->offs, cond);
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return true;
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}
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static bool gen_rz_bc(DisasContext *ctx, arg_r_offs *a, TCGCond cond)
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{
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv src2 = tcg_constant_tl(0);
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gen_bc(ctx, src1, src2, a->offs, cond);
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return true;
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}
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static bool gen_cz_bc(DisasContext *ctx, arg_c_offs *a, TCGCond cond)
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{
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TCGv src1 = tcg_temp_new();
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TCGv src2 = tcg_constant_tl(0);
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tcg_gen_ld8u_tl(src1, cpu_env,
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offsetof(CPULoongArchState, cf[a->cj]));
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gen_bc(ctx, src1, src2, a->offs, cond);
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return true;
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}
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TRANS(beq, gen_rr_bc, TCG_COND_EQ)
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TRANS(bne, gen_rr_bc, TCG_COND_NE)
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TRANS(blt, gen_rr_bc, TCG_COND_LT)
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TRANS(bge, gen_rr_bc, TCG_COND_GE)
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TRANS(bltu, gen_rr_bc, TCG_COND_LTU)
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TRANS(bgeu, gen_rr_bc, TCG_COND_GEU)
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TRANS(beqz, gen_rz_bc, TCG_COND_EQ)
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TRANS(bnez, gen_rz_bc, TCG_COND_NE)
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TRANS(bceqz, gen_cz_bc, TCG_COND_EQ)
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TRANS(bcnez, gen_cz_bc, TCG_COND_NE)
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