xemu/hw/intc
Peter Maydell f00f57f344 This PR includes multiple fixes and features for RISC-V:
- Fixes a bug in printing trap causes
  - Allows 16-bit writes to the SiFive test device. This fixes the
    failure to reboot the RISC-V virt machine
  - Support for the Microchip PolarFire SoC and Icicle Kit
  - A reafactor of RISC-V code out of hw/riscv
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Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging

This PR includes multiple fixes and features for RISC-V:
 - Fixes a bug in printing trap causes
 - Allows 16-bit writes to the SiFive test device. This fixes the
   failure to reboot the RISC-V virt machine
 - Support for the Microchip PolarFire SoC and Icicle Kit
 - A reafactor of RISC-V code out of hw/riscv

# gpg: Signature made Thu 10 Sep 2020 19:08:06 BST
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits)
  hw/riscv: Sort the Kconfig options in alphabetical order
  hw/riscv: Drop CONFIG_SIFIVE
  hw/riscv: Always build riscv_hart.c
  hw/riscv: Move sifive_test model to hw/misc
  hw/riscv: Move sifive_uart model to hw/char
  hw/riscv: Move riscv_htif model to hw/char
  hw/riscv: Move sifive_plic model to hw/intc
  hw/riscv: Move sifive_clint model to hw/intc
  hw/riscv: Move sifive_gpio model to hw/gpio
  hw/riscv: Move sifive_u_otp model to hw/misc
  hw/riscv: Move sifive_u_prci model to hw/misc
  hw/riscv: Move sifive_e_prci model to hw/misc
  hw/riscv: sifive_u: Connect a DMA controller
  hw/riscv: clint: Avoid using hard-coded timebase frequency
  hw/riscv: microchip_pfsoc: Hook GPIO controllers
  hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs
  hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23
  hw/net: cadence_gem: Add a new 'phy-addr' property
  hw/riscv: microchip_pfsoc: Connect a DMA controller
  hw/dma: Add SiFive platform DMA controller emulation
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	hw/riscv/trace-events
2020-09-13 20:29:35 +01:00
..
allwinner-a10-pic.c Clean up inclusion of sysemu/sysemu.h 2019-08-16 13:31:53 +02:00
apic_common.c apic: Report current_count via 'info lapic' 2020-07-10 19:26:55 -04:00
apic.c Use DECLARE_*CHECKER* when possible (--force mode) 2020-09-09 09:27:11 -04:00
arm_gic_common.c arm_gic: Mask the un-supported priority bits 2020-02-28 16:14:57 +00:00
arm_gic_kvm.c Use DECLARE_*CHECKER* when possible (--force mode) 2020-09-09 09:27:11 -04:00
arm_gic.c arm_gic: Mask the un-supported priority bits 2020-02-28 16:14:57 +00:00
arm_gicv2m.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
arm_gicv3_common.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
arm_gicv3_cpuif.c arm/gicv3: update virtual irq state after IAR register read 2020-01-17 14:27:16 +00:00
arm_gicv3_dist.c hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1 2019-06-17 15:13:19 +01:00
arm_gicv3_its_common.c Include migration/vmstate.h less 2019-08-16 13:31:52 +02:00
arm_gicv3_its_kvm.c Use DECLARE_*CHECKER* when possible (--force mode) 2020-09-09 09:27:11 -04:00
arm_gicv3_kvm.c Use DECLARE_*CHECKER* when possible (--force mode) 2020-09-09 09:27:11 -04:00
arm_gicv3_redist.c hw/intc/arm_gicv3: Fix decoding of ID register range 2019-06-17 15:13:19 +01:00
arm_gicv3.c Include qemu/module.h where needed, drop it from qemu-common.h 2019-06-12 13:18:33 +02:00
armv7m_nvic.c hw: Remove superfluous breaks 2020-09-01 08:38:00 +02:00
aspeed_vic.c Include migration/vmstate.h less 2019-08-16 13:31:52 +02:00
bcm2835_ic.c hw/arm/bcm283x: Correct the license text 2020-03-23 17:22:30 +00:00
bcm2836_control.c hw/arm/bcm283x: Correct the license text 2020-03-23 17:22:30 +00:00
etraxfs_pic.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
exynos4210_combiner.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
exynos4210_gic.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
gic_internal.h hw/intc/arm_gic: Drop GIC_BASE_IRQ macro 2018-09-25 15:13:24 +01:00
gicv3_internal.h target-arm: Add GICv3CPUState in CPUARMState struct 2017-02-28 17:10:00 +00:00
grlib_irqmp.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
heathrow_pic.c Include hw/hw.h exactly where needed 2019-08-16 13:31:52 +02:00
i8259_common.c isa: Convert uses of isa_create() with Coccinelle 2020-06-15 22:05:28 +02:00
i8259.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
ibex_plic.c hw/intc: ibex_plic: Honour source priorities 2020-08-21 22:37:55 -07:00
imx_avic.c Include migration/vmstate.h less 2019-08-16 13:31:52 +02:00
imx_gpcv2.c Include migration/vmstate.h less 2019-08-16 13:31:52 +02:00
intc.c
ioapic_common.c Include migration/vmstate.h less 2019-08-16 13:31:52 +02:00
ioapic.c KVM: Kick resamplefd for split kernel irqchip 2020-06-10 12:10:33 -04:00
Kconfig hw/riscv: Move sifive_plic model to hw/intc 2020-09-09 15:54:19 -07:00
lm32_pic.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
loongson_liointc.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
meson.build hw/riscv: Move sifive_plic model to hw/intc 2020-09-09 15:54:19 -07:00
mips_gic.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
nios2_iic.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
omap_intc.c omap_intc: Use typedef name for instance_size 2020-09-09 13:20:22 -04:00
ompic.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
openpic_kvm.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
openpic.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
pl190.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
pnv_xive_regs.h ppc/pnv: add a XIVE interrupt controller model for POWER9 2019-03-12 14:33:04 +11:00
pnv_xive.c error: Eliminate error_propagate() with Coccinelle, part 1 2020-07-10 15:18:08 +02:00
puv3_intc.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
realview_gic.c error: Eliminate error_propagate() with Coccinelle, part 1 2020-07-10 15:18:08 +02:00
rx_icu.c hw/intc: RX62N interrupt controller (ICUa) 2020-06-22 18:37:12 +02:00
s390_flic_kvm.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
s390_flic.c sysbus: Convert to sysbus_realize() etc. with Coccinelle 2020-06-15 22:05:28 +02:00
sh_intc.c Include hw/hw.h exactly where needed 2019-08-16 13:31:52 +02:00
sifive_clint.c hw/riscv: Move sifive_clint model to hw/intc 2020-09-09 15:54:19 -07:00
sifive_plic.c hw/riscv: Move sifive_plic model to hw/intc 2020-09-09 15:54:19 -07:00
sifive_plic.h hw/riscv: Move sifive_plic model to hw/intc 2020-09-09 15:54:19 -07:00
slavio_intctl.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
spapr_xive_kvm.c spapr/xive: Allocate vCPU IPIs from the vCPU contexts 2020-09-08 10:08:42 +10:00
spapr_xive.c spapr/xive: Add a 'hv-prio' property to represent the KVM escalation priority 2020-09-08 10:08:42 +10:00
trace-events xics: Rename misleading ics_simple_*() functions 2019-10-04 19:08:22 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
vgic_common.h
xics_kvm.c error: Eliminate error_propagate() with Coccinelle, part 1 2020-07-10 15:18:08 +02:00
xics_pnv.c Clean up inclusion of sysemu/sysemu.h 2019-08-16 13:31:53 +02:00
xics_spapr.c spapr: Pass the maximum number of vCPUs to the KVM interrupt controller 2019-12-17 10:39:48 +11:00
xics.c error: Eliminate error_propagate() with Coccinelle, part 2 2020-07-10 15:18:08 +02:00
xilinx_intc.c Use DECLARE_*CHECKER* macros 2020-09-09 09:27:09 -04:00
xive.c ppc/xive: Simplify error handling in xive_tctx_realize() 2020-08-13 21:07:28 +10:00
xlnx-pmu-iomod-intc.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
xlnx-zynqmp-ipi.c Include migration/vmstate.h less 2019-08-16 13:31:52 +02:00