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xemu/hw/mips
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Philippe Mathieu-Daudé 07741e6754 hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit() 
PTC field has 8 bits, PVPE has 4. We plan to use the
"hw/registerfields.h" API with MIPS CPU definitions
(target/mips/cpu.h). Meanwhile we use magic 8 and 4.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-6-f4bug@amsat.org>
2020-12-13 20:26:02 +01:00
..
boston.c
hw/mips: Move address translation helpers to target/mips/
2020-12-13 19:58:54 +01:00
cps.c
target/mips: Introduce ase_mt_available() helper
2020-12-13 20:26:02 +01:00
fuloong2e.c
vl: extract softmmu/datadir.c
2020-12-10 12:15:18 -05:00
gt64xxx_pci.c
Use OBJECT_DECLARE_SIMPLE_TYPE when possible
2020-09-18 14:12:32 -04:00
jazz.c
vl: extract softmmu/datadir.c
2020-12-10 12:15:18 -05:00
Kconfig
hw/mips: Remove the 'r4k' machine
2020-11-03 16:51:13 +01:00
malta.c
hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit()
2020-12-13 20:26:02 +01:00
meson.build
hw/mips: Move address translation helpers to target/mips/
2020-12-13 19:58:54 +01:00
mips_int.c
hw/mips: Add CPU IRQ3 delivery for KVM
2020-06-01 13:28:21 +02:00
mipssim.c
vl: extract softmmu/datadir.c
2020-12-10 12:15:18 -05:00
trace-events
trace-events: Fix attribution of trace points to source
2020-09-09 17:17:58 +01:00
trace.h
trace: switch position of headers to what Meson requires
2020-08-21 06:18:24 -04:00