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f61c3fb56b
'ARM SBCon two-wire serial bus interface' is the official name describing the pair of registers used to bitbanging I2C in the Versatile boards. Make the private VersatileI2CState structure as public ArmSbconI2CState. Add the TYPE_ARM_SBCON_I2C, alias to our current TYPE_VERSATILE_I2C model. Rename the memory region description as 'arm_sbcon_i2c'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200617072539.32686-5-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
112 lines
3.2 KiB
C
112 lines
3.2 KiB
C
/*
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* ARM SBCon two-wire serial bus interface (I2C bitbang)
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* a.k.a. ARM Versatile I2C controller
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Copyright (c) 2012 Oskar Andero <oskar.andero@gmail.com>
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*
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* This file is derived from hw/realview.c by Paul Brook
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/i2c/arm_sbcon_i2c.h"
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#include "hw/registerfields.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#define VERSATILE_I2C(obj) \
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OBJECT_CHECK(VersatileI2CState, (obj), TYPE_VERSATILE_I2C)
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typedef ArmSbconI2CState VersatileI2CState;
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REG32(CONTROL_GET, 0)
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REG32(CONTROL_SET, 0)
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REG32(CONTROL_CLR, 4)
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#define SCL BIT(0)
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#define SDA BIT(1)
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static uint64_t versatile_i2c_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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VersatileI2CState *s = (VersatileI2CState *)opaque;
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switch (offset) {
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case A_CONTROL_SET:
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return (s->out & 1) | (s->in << 1);
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%x\n", __func__, (int)offset);
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return -1;
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}
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}
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static void versatile_i2c_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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VersatileI2CState *s = (VersatileI2CState *)opaque;
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switch (offset) {
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case A_CONTROL_SET:
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s->out |= value & 3;
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break;
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case A_CONTROL_CLR:
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s->out &= ~value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%x\n", __func__, (int)offset);
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}
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bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SCL, (s->out & SCL) != 0);
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s->in = bitbang_i2c_set(&s->bitbang, BITBANG_I2C_SDA, (s->out & SDA) != 0);
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}
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static const MemoryRegionOps versatile_i2c_ops = {
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.read = versatile_i2c_read,
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.write = versatile_i2c_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void versatile_i2c_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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VersatileI2CState *s = VERSATILE_I2C(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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I2CBus *bus;
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bus = i2c_init_bus(dev, "i2c");
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bitbang_i2c_init(&s->bitbang, bus);
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memory_region_init_io(&s->iomem, obj, &versatile_i2c_ops, s,
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"arm_sbcon_i2c", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const TypeInfo versatile_i2c_info = {
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.name = TYPE_VERSATILE_I2C,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(VersatileI2CState),
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.instance_init = versatile_i2c_init,
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};
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static void versatile_i2c_register_types(void)
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{
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type_register_static(&versatile_i2c_info);
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}
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type_init(versatile_i2c_register_types)
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