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https://github.com/xemu-project/xemu.git
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ef96e3ae96
The VSX register array is a block of 64 128-bit registers where the first 32
registers consist of the existing 64-bit FP registers extended to 128-bit
using new VSR registers, and the last 32 registers are the VMX 128-bit
registers as show below:
64-bit 64-bit
+--------------------+--------------------+
| FP0 | | VSR0
+--------------------+--------------------+
| FP1 | | VSR1
+--------------------+--------------------+
| ... | ... | ...
+--------------------+--------------------+
| FP30 | | VSR30
+--------------------+--------------------+
| FP31 | | VSR31
+--------------------+--------------------+
| VMX0 | VSR32
+-----------------------------------------+
| VMX1 | VSR33
+-----------------------------------------+
| ... | ...
+-----------------------------------------+
| VMX30 | VSR62
+-----------------------------------------+
| VMX31 | VSR63
+-----------------------------------------+
In order to allow for future conversion of VSX instructions to use TCG vector
operations, recreate the same layout using an aligned version of the existing
vsr register array.
Since the old fpr and avr register arrays are removed, the existing callers
must also be updated to use the correct offset in the vsr register array. This
also includes switching the relevant VMState fields over to using subarrays
to make sure that migration is preserved.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
233 lines
9.4 KiB
C
233 lines
9.4 KiB
C
/*** Decimal Floating Point ***/
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static inline TCGv_ptr gen_fprp_ptr(int reg)
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{
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TCGv_ptr r = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, vsr[reg].u64[0]));
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return r;
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}
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#define GEN_DFP_T_A_B_Rc(name) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr rd, ra, rb; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->base.pc_next - 4); \
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rd = gen_fprp_ptr(rD(ctx->opcode)); \
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ra = gen_fprp_ptr(rA(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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gen_helper_##name(cpu_env, rd, ra, rb); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rd); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_ptr(rb); \
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}
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#define GEN_DFP_BF_A_B(name) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr ra, rb; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->base.pc_next - 4); \
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ra = gen_fprp_ptr(rA(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
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cpu_env, ra, rb); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_ptr(rb); \
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}
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#define GEN_DFP_BF_I_B(name) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_i32 uim; \
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TCGv_ptr rb; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->base.pc_next - 4); \
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uim = tcg_const_i32(UIMM5(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
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cpu_env, uim, rb); \
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tcg_temp_free_i32(uim); \
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tcg_temp_free_ptr(rb); \
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}
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#define GEN_DFP_BF_A_DCM(name) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr ra; \
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TCGv_i32 dcm; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->base.pc_next - 4); \
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ra = gen_fprp_ptr(rA(ctx->opcode)); \
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dcm = tcg_const_i32(DCM(ctx->opcode)); \
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gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
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cpu_env, ra, dcm); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_i32(dcm); \
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}
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#define GEN_DFP_T_B_U32_U32_Rc(name, u32f1, u32f2) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr rt, rb; \
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TCGv_i32 u32_1, u32_2; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->base.pc_next - 4); \
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rt = gen_fprp_ptr(rD(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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u32_1 = tcg_const_i32(u32f1(ctx->opcode)); \
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u32_2 = tcg_const_i32(u32f2(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, rb, u32_1, u32_2); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rb); \
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tcg_temp_free_i32(u32_1); \
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tcg_temp_free_i32(u32_2); \
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}
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#define GEN_DFP_T_A_B_I32_Rc(name, i32fld) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr rt, ra, rb; \
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TCGv_i32 i32; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->base.pc_next - 4); \
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rt = gen_fprp_ptr(rD(ctx->opcode)); \
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ra = gen_fprp_ptr(rA(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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i32 = tcg_const_i32(i32fld(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, ra, rb, i32); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rb); \
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tcg_temp_free_ptr(ra); \
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tcg_temp_free_i32(i32); \
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}
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#define GEN_DFP_T_B_Rc(name) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr rt, rb; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->base.pc_next - 4); \
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rt = gen_fprp_ptr(rD(ctx->opcode)); \
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rb = gen_fprp_ptr(rB(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, rb); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rb); \
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}
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#define GEN_DFP_T_FPR_I32_Rc(name, fprfld, i32fld) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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TCGv_ptr rt, rs; \
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TCGv_i32 i32; \
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if (unlikely(!ctx->fpu_enabled)) { \
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gen_exception(ctx, POWERPC_EXCP_FPU); \
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return; \
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} \
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gen_update_nip(ctx, ctx->base.pc_next - 4); \
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rt = gen_fprp_ptr(rD(ctx->opcode)); \
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rs = gen_fprp_ptr(fprfld(ctx->opcode)); \
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i32 = tcg_const_i32(i32fld(ctx->opcode)); \
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gen_helper_##name(cpu_env, rt, rs, i32); \
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if (unlikely(Rc(ctx->opcode) != 0)) { \
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gen_set_cr1_from_fpscr(ctx); \
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} \
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tcg_temp_free_ptr(rt); \
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tcg_temp_free_ptr(rs); \
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tcg_temp_free_i32(i32); \
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}
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GEN_DFP_T_A_B_Rc(dadd)
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GEN_DFP_T_A_B_Rc(daddq)
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GEN_DFP_T_A_B_Rc(dsub)
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GEN_DFP_T_A_B_Rc(dsubq)
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GEN_DFP_T_A_B_Rc(dmul)
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GEN_DFP_T_A_B_Rc(dmulq)
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GEN_DFP_T_A_B_Rc(ddiv)
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GEN_DFP_T_A_B_Rc(ddivq)
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GEN_DFP_BF_A_B(dcmpu)
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GEN_DFP_BF_A_B(dcmpuq)
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GEN_DFP_BF_A_B(dcmpo)
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GEN_DFP_BF_A_B(dcmpoq)
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GEN_DFP_BF_A_DCM(dtstdc)
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GEN_DFP_BF_A_DCM(dtstdcq)
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GEN_DFP_BF_A_DCM(dtstdg)
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GEN_DFP_BF_A_DCM(dtstdgq)
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GEN_DFP_BF_A_B(dtstex)
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GEN_DFP_BF_A_B(dtstexq)
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GEN_DFP_BF_A_B(dtstsf)
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GEN_DFP_BF_A_B(dtstsfq)
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GEN_DFP_BF_I_B(dtstsfi)
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GEN_DFP_BF_I_B(dtstsfiq)
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GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
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GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
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GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
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GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
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GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
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GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
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GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
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GEN_DFP_T_B_Rc(dctdp)
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GEN_DFP_T_B_Rc(dctqpq)
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GEN_DFP_T_B_Rc(drsp)
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GEN_DFP_T_B_Rc(drdpq)
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GEN_DFP_T_B_Rc(dcffix)
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GEN_DFP_T_B_Rc(dcffixq)
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GEN_DFP_T_B_Rc(dctfix)
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GEN_DFP_T_B_Rc(dctfixq)
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GEN_DFP_T_FPR_I32_Rc(ddedpd, rB, SP)
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GEN_DFP_T_FPR_I32_Rc(ddedpdq, rB, SP)
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GEN_DFP_T_FPR_I32_Rc(denbcd, rB, SP)
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GEN_DFP_T_FPR_I32_Rc(denbcdq, rB, SP)
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GEN_DFP_T_B_Rc(dxex)
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GEN_DFP_T_B_Rc(dxexq)
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GEN_DFP_T_A_B_Rc(diex)
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GEN_DFP_T_A_B_Rc(diexq)
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GEN_DFP_T_FPR_I32_Rc(dscli, rA, DCM)
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GEN_DFP_T_FPR_I32_Rc(dscliq, rA, DCM)
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GEN_DFP_T_FPR_I32_Rc(dscri, rA, DCM)
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GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM)
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#undef GEN_DFP_T_A_B_Rc
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#undef GEN_DFP_BF_A_B
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#undef GEN_DFP_BF_A_DCM
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#undef GEN_DFP_T_B_U32_U32_Rc
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#undef GEN_DFP_T_A_B_I32_Rc
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#undef GEN_DFP_T_B_Rc
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#undef GEN_DFP_T_FPR_I32_Rc
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