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[gpu] sm86 decoder scripts

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This commit is contained in:
lizzie
2026-02-15 19:21:21 +00:00
committed by Nikilite
parent fcfb984f92
commit 8b7e67939f
8 changed files with 121172 additions and 212 deletions
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.gitignore
+1
View File
@@ -3,3 +3,4 @@
/third_party/boost_1_89_0
.vscode/
rad/
research/
license.txt → LICENSE.txt
View File
core/src/gpu/sm86.rs
+58 -47
View File
@@ -184,76 +184,88 @@ enum BitSize {
pub struct Decoder<'a> {
pub ir: &'a mut spirv::Emitter,
// Declared types for headers
type_u8: u32,
type_u16: u32,
type_u32: u32,
type_u64: u32,
type_s8: u32,
type_s16: u32,
type_s32: u32,
type_s64: u32,
type_f16: u32,
type_f32: u32,
type_f64: u32,
type_void: u32,
// Pointers
type_ptr_u32: u32,
// State
regs: Vec<u32>,
// Declared types for headers
type_u8: [u32; 4],
type_u16: [u32; 4],
type_u32: [u32; 4],
type_u64: [u32; 4],
type_s8: [u32; 4],
type_s16: [u32; 4],
type_s32: [u32; 4],
type_s64: [u32; 4],
type_f16: [u32; 4],
type_f32: [u32; 4],
type_f64: [u32; 4],
type_bool: [u32; 4],
// abstract state machine
regs: [u32; MAX_REG_COUNT],
}
impl<'a> Decoder<'a> {
pub fn init(&mut self) {
self.type_u8 = self.ir.emit_type_int(8, 0);
self.type_u16 = self.ir.emit_type_int(16, 0);
self.type_u32 = self.ir.emit_type_int(32, 0);
self.type_u64 = self.ir.emit_type_int(64, 0);
self.type_s8 = self.ir.emit_type_int(8, 1);
self.type_s16 = self.ir.emit_type_int(16, 1);
self.type_s32 = self.ir.emit_type_int(32, 1);
self.type_s64 = self.ir.emit_type_int(64, 1);
self.type_f16 = self.ir.emit_type_float(16);
self.type_f32 = self.ir.emit_type_float(32);
self.type_f64 = self.ir.emit_type_float(64);
self.type_void = self.ir.emit_type_void();
self.type_u8[1] = self.ir.emit_type_int(8, 0);
self.type_u16[1] = self.ir.emit_type_int(16, 0);
self.type_u32[1] = self.ir.emit_type_int(32, 0);
self.type_u64[1] = self.ir.emit_type_int(64, 0);
self.type_s8[1] = self.ir.emit_type_int(8, 1);
self.type_s16[1] = self.ir.emit_type_int(16, 1);
self.type_s32[1] = self.ir.emit_type_int(32, 1);
self.type_s64[1] = self.ir.emit_type_int(64, 1);
self.type_f16[1] = self.ir.emit_type_float(16);
self.type_f32[1] = self.ir.emit_type_float(32);
self.type_f64[1] = self.ir.emit_type_float(64);
self.type_bool[1] = self.ir.emit_type_bool();
for i in 2..=4 {
for type_sxx in [
self.type_u8, self.type_u16, self.type_u32, self.type_u64,
self.type_s8, self.type_s16, self.type_s32, self.type_s64,
self.type_f16, self.type_f32, self.type_f64, self.type_bool
] {
self.ir.emit_type_vector(type_sxx[i], i as u32);
}
}
// Define generic pointers
// Storage class 7 = Function
self.type_ptr_u32 = self.ir.emit_type_pointer(7, self.type_u32);
self.type_ptr_u32 = self.ir.emit_type_pointer(7, self.type_u32[1]);
// Define registers
self.regs = Vec::new();
for _ in 0..=MAX_REG_COUNT {
let reg_var = self.ir.emit_variable(self.type_ptr_u32, 7);
self.regs.push(reg_var);
for r in self.regs.iter_mut() {
*r = self.ir.emit_variable(self.type_ptr_u32, 7);
}
}
fn load_reg(&mut self, reg: u8) -> u32 {
if reg as usize == 255 {
// RZ (Zero Register)
return self.ir.emit_constant_typed(self.type_u32, 0u32);
fn load_reg(&mut self, reg: usize) -> u32 {
if reg == 255 {
// RZ (Zero Register)
return self.ir.emit_constant_typed(self.type_u32[1], 0u32);
}
assert!((reg as usize) < self.regs.len(), "Register index out of bounds");
let ptr = self.regs[reg as usize];
self.ir.emit_load(self.type_u32, ptr)
assert!(reg < self.regs.len(), "Register index out of bounds");
let ptr = self.regs[reg];
self.ir.emit_load(self.type_u32[1], ptr)
}
fn store_reg(&mut self, reg: u8, val: u32) {
if reg as usize == 255 {
fn store_reg(&mut self, reg: usize, val: u32) {
if reg == 255 {
// Write to RZ is ignored
return;
}
assert!((reg as usize) < self.regs.len(), "Register index out of bounds");
let ptr = self.regs[reg as usize];
assert!(reg < self.regs.len(), "Register index out of bounds");
let ptr = self.regs[reg];
self.ir.emit_store(ptr, val);
}
pub fn finish(&mut self) {
}
// %rd := %ra + $ra_offset
pub fn al2p(&mut self, inst: u128) {
let _pg = (((inst >> 12) & 0x7) << 0);
let _pg_not = (((inst >> 15) & 0x1) << 0);
let _rd = (((inst >> 16) & 0xff) << 0);
let rd = (((inst >> 16) & 0xff) << 0) as usize;
let ra = (((inst >> 24) & 0xff) << 0) as usize;
let ra_offset = (((inst >> 40) & 0x7ff) << 0) as usize;
let bop = (((inst >> 74) & 0x3) << 0) as usize;
@@ -263,13 +275,12 @@ impl<'a> Decoder<'a> {
let _src_rel_sb = (((inst >> 113) & 0x7) << 0);
let _req_bit_set = (((inst >> 116) & 0x3f) << 0);
let _opex = (((inst >> 122) & 0x7) << 5) | (((inst >> 105) & 0x1f) << 0);
// %rd := %ra + $ra_offset
assert!(ra <= MAX_REG_COUNT || ra == 255);
assert!(bop == BitSize::B32 as usize);
let base = self.load_reg(ra as u8);
let offset = self.ir.emit_constant_typed::<u32>(self.type_u32, ra_offset as u32);
let dst_val = self.ir.emit_iadd(self.type_u32, base, offset);
self.store_reg(_rd as u8, dst_val);
let base = self.load_reg(ra);
let offset = self.ir.emit_constant_typed(self.type_u32[1], ra_offset as u32);
let dst_val = self.ir.emit_iadd(self.type_u32[1], base, offset);
self.store_reg(rd, dst_val);
}
pub fn ald(&mut self, inst: u128) {
let _pg = (((inst >> 12) & 0x7) << 0);
core/src/gpu/spirv.rs
+10
View File
@@ -480,6 +480,16 @@ impl Emitter {
r
}
pub fn emit_constant_composite_typed<T: Literal + Copy>(&mut self, ty: u32, constituents: &[T]) -> u32 {
let r = self.alloc_id();
let mut data = vec![ty, r];
for e in constituents.iter() {
data.extend(e.to_words());
}
self.inst(44, &data);
r
}
pub fn emit_spec_constant(&mut self, ty: u32, value_words: &[u32]) -> u32 {
let r = self.alloc_id();
let mut data = vec![ty, r];
core/src/nn/mod.rs
+165 -165
View File
@@ -55,169 +55,169 @@ pub trait ServiceTrait {
}
pub fn start_host_services(state: &mut sys::State) {
let entries: [(&str, fn(&mut sys::State)); 160] = [
("acc", nn::acc::State::run),
("adraw", nn::adraw::State::run),
("ahid", nn::ahid::State::run),
("aoc", nn::aoc::State::run),
("apm", nn::apm::State::run),
("applet_ae", nn::applet_ae::State::run),
("applet_oe", nn::applet_oe::State::run),
("arp", nn::arp::State::run),
("aud", nn::aud::State::run),
("audctl", nn::audctl::State::run),
("auddebug", nn::auddebug::State::run),
("auddev", nn::auddev::State::run),
("auddmg", nn::auddmg::State::run),
("audin", nn::audin::State::run),
("audout", nn::audout::State::run),
("audrec", nn::audrec::State::run),
("audren", nn::audren::State::run),
("audsmx", nn::audsmx::State::run),
("avm", nn::avm::State::run),
("banana", nn::banana::State::run),
("batlog", nn::batlog::State::run),
("bcat", nn::bcat::State::run),
("bgtc", nn::bgtc::State::run),
("bpc", nn::bpc::State::run),
("bpmpmr", nn::bpmpmr::State::run),
("bsd", nn::bsd::State::run),
("bsdcfg", nn::bsdcfg::State::run),
("bt", nn::bt::State::run),
("btdrv", nn::btdrv::State::run),
("btm", nn::btm::State::run),
("btp", nn::btp::State::run),
("capmtp", nn::capmtp::State::run),
("caps", nn::caps::State::run),
("caps2", nn::caps2::State::run),
("cec_mgr", nn::cec_mgr::State::run),
("chat", nn::chat::State::run),
("clkrst", nn::clkrst::State::run),
("codecctl", nn::codecctl::State::run),
("csrng", nn::csrng::State::run),
("dauth", nn::dauth::State::run),
("disp", nn::disp::State::run),
("dispdrv", nn::dispdrv::State::run),
("dmnt", nn::dmnt::State::run),
("dns", nn::dns::State::run),
("dt", nn::dt::State::run),
("ectx", nn::ectx::State::run),
("erpt", nn::erpt::State::run),
("es", nn::es::State::run),
("eth", nn::eth::State::run),
("ethc", nn::ethc::State::run),
("eupld", nn::eupld::State::run),
("fan", nn::fan::State::run),
("fatal", nn::fatal::State::run),
("fgm", nn::fgm::State::run),
("file_io", nn::file_io::State::run),
("friend", nn::friend::State::run),
("fs", nn::fs::State::run),
("fsp_ldr", nn::fsp_ldr::State::run),
("fsp_pr", nn::fsp_pr::State::run),
("fsp_srv", nn::fsp_srv::State::run),
("gds", nn::gds::State::run),
("gpio", nn::gpio::State::run),
("gpuk", nn::gpuk::State::run),
("grc", nn::grc::State::run),
("gsv", nn::gsv::State::run),
("hdcp", nn::hdcp::State::run),
("hid", nn::hid::State::run),
("hidbus", nn::hidbus::State::run),
("host1x", nn::host1x::State::run),
("hshl", nn::hshl::State::run),
("htc", nn::htc::State::run),
("htcs", nn::htcs::State::run),
("hwopus", nn::hwopus::State::run),
("i2c", nn::i2c::State::run),
("idle", nn::idle::State::run),
("ifcfg", nn::ifcfg::State::run),
("imf", nn::imf::State::run),
("ins", nn::ins::State::run),
("irs", nn::irs::State::run),
("jit", nn::jit::State::run),
("lbl", nn::lbl::State::run),
("ldn", nn::ldn::State::run),
("ldr", nn::ldr::State::run),
("led", nn::led::State::run),
("lm", nn::lm::State::run),
("lp2p", nn::lp2p::State::run),
("lr", nn::lr::State::run),
("manu", nn::manu::State::run),
("mig", nn::mig::State::run),
("mii", nn::mii::State::run),
("miiimg", nn::miiimg::State::run),
("mm", nn::mm::State::run),
("mnpp", nn::mnpp::State::run),
("ncm", nn::ncm::State::run),
("nd", nn::nd::State::run),
("ndd", nn::ndd::State::run),
("ndrm", nn::ndrm::State::run),
("news", nn::news::State::run),
("nfc", nn::nfc::State::run),
("nfp", nn::nfp::State::run),
("ngc", nn::ngc::State::run),
("ngct", nn::ngct::State::run),
("nifm", nn::nifm::State::run),
("nim", nn::nim::State::run),
("notif", nn::notif::State::run),
("npns", nn::npns::State::run),
("ns", nn::ns::State::run),
("nsd", nn::nsd::State::run),
("ntc", nn::ntc::State::run),
("nvdbg", nn::nvdbg::State::run),
("nvdrv", nn::nvdrv::State::run),
("nvdrvdbg", nn::nvdrvdbg::State::run),
("nvgem", nn::nvgem::State::run),
("nvmemp", nn::nvmemp::State::run),
("olsc", nn::olsc::State::run),
("omm", nn::omm::State::run),
("ommdisp", nn::ommdisp::State::run),
("ovln", nn::ovln::State::run),
("pcie", nn::pcie::State::run),
("pcm", nn::pcm::State::run),
("pctl", nn::pctl::State::run),
("pcv", nn::pcv::State::run),
("pdm", nn::pdm::State::run),
("pgl", nn::pgl::State::run),
("pinmux", nn::pinmux::State::run),
("pl", nn::pl::State::run),
("pm", nn::pm::State::run),
("prepo", nn::prepo::State::run),
("psc", nn::psc::State::run),
("psm", nn::psm::State::run),
("pwm", nn::pwm::State::run),
("rgltr", nn::rgltr::State::run),
("ro", nn::ro::State::run),
("rtc", nn::rtc::State::run),
("sasbus", nn::sasbus::State::run),
("set", nn::set::State::run),
("sf_uds", nn::sf_uds::State::run),
("sfdnsres", nn::sfdnsres::State::run),
("spbg", nn::spbg::State::run),
("spi", nn::spi::State::run),
("spl", nn::spl::State::run),
("sprof", nn::sprof::State::run),
("spsm", nn::spsm::State::run),
("srepo", nn::srepo::State::run),
("ssl", nn::ssl::State::run),
("syncpt", nn::syncpt::State::run),
("tc", nn::tc::State::run),
("tcap", nn::tcap::State::run),
("time", nn::time::State::run),
("tma_log", nn::tma_log::State::run),
("tmagent", nn::tmagent::State::run),
("ts", nn::ts::State::run),
("tspm", nn::tspm::State::run),
("uart", nn::uart::State::run),
("usb", nn::usb::State::run),
("vi", nn::vi::State::run),
("vi2", nn::vi2::State::run),
("vic", nn::vic::State::run),
("wlan", nn::wlan::State::run),
("xcd", nn::xcd::State::run),
];
for (_name, run_fn) in entries.iter() {
run_fn(state);
}
let entries: [(&str, fn(&mut sys::State)); 160] = [
("acc", nn::acc::State::run),
("adraw", nn::adraw::State::run),
("ahid", nn::ahid::State::run),
("aoc", nn::aoc::State::run),
("apm", nn::apm::State::run),
("applet-ae", nn::applet_ae::State::run),
("applet-oe", nn::applet_oe::State::run),
("arp", nn::arp::State::run),
("aud", nn::aud::State::run),
("audctl", nn::audctl::State::run),
("auddebug", nn::auddebug::State::run),
("auddev", nn::auddev::State::run),
("auddmg", nn::auddmg::State::run),
("audin", nn::audin::State::run),
("audout", nn::audout::State::run),
("audrec", nn::audrec::State::run),
("audren", nn::audren::State::run),
("audsmx", nn::audsmx::State::run),
("avm", nn::avm::State::run),
("banana", nn::banana::State::run),
("batlog", nn::batlog::State::run),
("bcat", nn::bcat::State::run),
("bgtc", nn::bgtc::State::run),
("bpc", nn::bpc::State::run),
("bpmpmr", nn::bpmpmr::State::run),
("bsd", nn::bsd::State::run),
("bsdcfg", nn::bsdcfg::State::run),
("bt", nn::bt::State::run),
("btdrv", nn::btdrv::State::run),
("btm", nn::btm::State::run),
("btp", nn::btp::State::run),
("capmtp", nn::capmtp::State::run),
("caps", nn::caps::State::run),
("caps2", nn::caps2::State::run),
("cec_mgr", nn::cec_mgr::State::run),
("chat", nn::chat::State::run),
("clkrst", nn::clkrst::State::run),
("codecctl", nn::codecctl::State::run),
("csrng", nn::csrng::State::run),
("dauth", nn::dauth::State::run),
("disp", nn::disp::State::run),
("dispdrv", nn::dispdrv::State::run),
("dmnt", nn::dmnt::State::run),
("dns", nn::dns::State::run),
("dt", nn::dt::State::run),
("ectx", nn::ectx::State::run),
("erpt", nn::erpt::State::run),
("es", nn::es::State::run),
("eth", nn::eth::State::run),
("ethc", nn::ethc::State::run),
("eupld", nn::eupld::State::run),
("fan", nn::fan::State::run),
("fatal", nn::fatal::State::run),
("fgm", nn::fgm::State::run),
("file_io", nn::file_io::State::run),
("friend", nn::friend::State::run),
("fs", nn::fs::State::run),
("fsp-ldr", nn::fsp_ldr::State::run),
("fsp-pr", nn::fsp_pr::State::run),
("fsp-srv", nn::fsp_srv::State::run),
("gds", nn::gds::State::run),
("gpio", nn::gpio::State::run),
("gpuk", nn::gpuk::State::run),
("grc", nn::grc::State::run),
("gsv", nn::gsv::State::run),
("hdcp", nn::hdcp::State::run),
("hid", nn::hid::State::run),
("hidbus", nn::hidbus::State::run),
("host1x", nn::host1x::State::run),
("hshl", nn::hshl::State::run),
("htc", nn::htc::State::run),
("htcs", nn::htcs::State::run),
("hwopus", nn::hwopus::State::run),
("i2c", nn::i2c::State::run),
("idle", nn::idle::State::run),
("ifcfg", nn::ifcfg::State::run),
("imf", nn::imf::State::run),
("ins", nn::ins::State::run),
("irs", nn::irs::State::run),
("jit", nn::jit::State::run),
("lbl", nn::lbl::State::run),
("ldn", nn::ldn::State::run),
("ldr", nn::ldr::State::run),
("led", nn::led::State::run),
("lm", nn::lm::State::run),
("lp2p", nn::lp2p::State::run),
("lr", nn::lr::State::run),
("manu", nn::manu::State::run),
("mig", nn::mig::State::run),
("mii", nn::mii::State::run),
("miiimg", nn::miiimg::State::run),
("mm", nn::mm::State::run),
("mnpp", nn::mnpp::State::run),
("ncm", nn::ncm::State::run),
("nd", nn::nd::State::run),
("ndd", nn::ndd::State::run),
("ndrm", nn::ndrm::State::run),
("news", nn::news::State::run),
("nfc", nn::nfc::State::run),
("nfp", nn::nfp::State::run),
("ngc", nn::ngc::State::run),
("ngct", nn::ngct::State::run),
("nifm", nn::nifm::State::run),
("nim", nn::nim::State::run),
("notif", nn::notif::State::run),
("npns", nn::npns::State::run),
("ns", nn::ns::State::run),
("nsd", nn::nsd::State::run),
("ntc", nn::ntc::State::run),
("nvdbg", nn::nvdbg::State::run),
("nvdrv", nn::nvdrv::State::run),
("nvdrvdbg", nn::nvdrvdbg::State::run),
("nvgem", nn::nvgem::State::run),
("nvmemp", nn::nvmemp::State::run),
("olsc", nn::olsc::State::run),
("omm", nn::omm::State::run),
("ommdisp", nn::ommdisp::State::run),
("ovln", nn::ovln::State::run),
("pcie", nn::pcie::State::run),
("pcm", nn::pcm::State::run),
("pctl", nn::pctl::State::run),
("pcv", nn::pcv::State::run),
("pdm", nn::pdm::State::run),
("pgl", nn::pgl::State::run),
("pinmux", nn::pinmux::State::run),
("pl", nn::pl::State::run),
("pm", nn::pm::State::run),
("prepo", nn::prepo::State::run),
("psc", nn::psc::State::run),
("psm", nn::psm::State::run),
("pwm", nn::pwm::State::run),
("rgltr", nn::rgltr::State::run),
("ro", nn::ro::State::run),
("rtc", nn::rtc::State::run),
("sasbus", nn::sasbus::State::run),
("set", nn::set::State::run),
("sf_uds", nn::sf_uds::State::run),
("sfdnsres", nn::sfdnsres::State::run),
("spbg", nn::spbg::State::run),
("spi", nn::spi::State::run),
("spl", nn::spl::State::run),
("sprof", nn::sprof::State::run),
("spsm", nn::spsm::State::run),
("srepo", nn::srepo::State::run),
("ssl", nn::ssl::State::run),
("syncpt", nn::syncpt::State::run),
("tc", nn::tc::State::run),
("tcap", nn::tcap::State::run),
("time", nn::time::State::run),
("tma-log", nn::tma_log::State::run),
("tmagent", nn::tmagent::State::run),
("ts", nn::ts::State::run),
("tspm", nn::tspm::State::run),
("uart", nn::uart::State::run),
("usb", nn::usb::State::run),
("vi", nn::vi::State::run),
("vi2", nn::vi2::State::run),
("vic", nn::vic::State::run),
("wlan", nn::wlan::State::run),
("xcd", nn::xcd::State::run),
];
for (_name, run_fn) in entries.iter() {
run_fn(state);
}
}
scripts/decoder_generator.rs
+390
View File
@@ -0,0 +1,390 @@
use std::io::Write;
#[derive(PartialEq, Eq, PartialOrd, Ord, Clone, Copy, Debug)]
enum ParserState {
None,
Opcodes,
Encoding,
Class
}
#[derive(Default, Debug, Clone)]
struct ParserField {
name: String,
total_bits: usize,
bits: Vec<(usize, usize)>,
value: Option<usize>
}
#[derive(Default, Clone, Debug)]
struct ParserInst {
name: String,
op: usize,
fixed_fields: Vec<ParserField>,
fields: Vec<ParserField>
}
fn collect_sass_instructions(f: &str) -> Result<Vec<ParserInst>, Box<dyn std::error::Error>> {
let mut instructions = Vec::new();
let mut dfa_state = ParserState::None;
for line in f.lines() {
if line == "OPCODES" {
dfa_state = ParserState::Opcodes;
} else if line == "ENCODING" {
dfa_state = ParserState::Encoding;
} else if line == "CLASS" {
dfa_state = ParserState::Class;
} else if dfa_state == ParserState::Opcodes && line.starts_with(" ") {
let mut iter = line.split("=").map(|x| x.trim());
let name = iter.next().unwrap();
if !name.ends_with("cbu_pipe") && !name.ends_with("mio_pipe") && !name.ends_with("int_pipe")
&& !name.ends_with("lite_pipe") && !name.ends_with("fe_pipe") && !name.ends_with("malighter_pipe")
&& !name.ends_with("fp16_pipe") && !name.ends_with("udp_pipe") && !name.ends_with("ttu_pipe") {
let bits = iter.next().unwrap().trim_start_matches("0b").trim_end_matches(";");
//writeln!(w, "{name}={bits}");
instructions.push(ParserInst{
name: name.to_string(),
op: usize::from_str_radix(bits, 2)?,
fixed_fields: Vec::new(),
fields: Vec::new()
});
}
} else if dfa_state == ParserState::Encoding && line.starts_with("BITS") {
//writeln!(w, "{}", line);
let tpt = line
.split_once("=")
.unwrap();
let segments = tpt.0.split(",");
for seg in segments {
let mut pairs = seg
.trim_start_matches("BITS_").trim()
.split("_");
let mut field: ParserField = ParserField::default();
field.value = tpt.1.parse::<usize>().ok();
field.total_bits = pairs.next().unwrap().parse::<usize>().unwrap();
let mut rem_size = field.total_bits;
while rem_size > 0 {
let (end, start) = (
pairs.next().unwrap().parse::<usize>().unwrap(),
pairs.next().unwrap().parse::<usize>().unwrap()
);
let bit_size = (end - start) + 1;
rem_size -= bit_size;
field.bits.push((start, end));
}
field.name = pairs.collect::<Vec<_>>().join("_").to_lowercase();
if field.name == "opcode" { //horrible hack for opcodes
field.value = Some(instructions.last_mut().unwrap().op);
}
field.name = field.name.replace(".", "_");
if field.value.is_some() {
instructions.last_mut().unwrap().fixed_fields.push(field);
} else {
instructions.last_mut().unwrap().fields.push(field);
}
}
}
}
/*for i in 0..instructions.len() {
let mut count = 0;
loop {
let new_name = if count == 0 {
format!("{}", instructions[i].name)
} else {
format!("{}_{count}", instructions[i].name)
};
let found = instructions.iter()
.find(|&e| e.name == new_name).is_some();
if !found {
if count > 0 {
instructions[i].name = new_name;
}
break;
}
count += 1;
}
}*/
Ok(instructions)
}
fn get_mask(start: usize, end: usize) -> usize {
let count = (end - start) + 1;
(1 << count) - 1
}
fn get_stmt_mask(name: &str, start: usize, end: usize) -> String {
if start > 0 {
format!("({name} >> {start}) & 0x{:x}", get_mask(start, end))
} else {
format!("{name} & 0x{:x}", get_mask(start, end))
}
}
fn get_multi_merge_stmt(name: &str, total_bits: usize, bits: &Vec<(usize, usize)>) -> String {
let mut s = String::new();
let mut rem_bits = total_bits;
for e in bits {
rem_bits -= e.1 - e.0 + 1;
s = format!("{s}{}(({}) << {rem_bits})",
if s.is_empty() { "" } else { " | " },
get_stmt_mask("inst", e.0, e.1),
);
}
s
}
fn get_multi_cmp_stmt(total_bits: usize, bits: &Vec<(usize, usize)>, value: usize) -> String {
let mut s = String::new();
let mut rem_bits = total_bits;
for e in bits {
rem_bits -= e.1 - e.0 + 1;
s = format!("{s}{}(({}) << {rem_bits})",
if s.is_empty() { "" } else { " | " },
get_stmt_mask("inst", e.0, e.1),
);
}
format!("({s}) == 0x{value:0x}")
}
fn get_canon_inst_name(s: &str) -> String {
let ns = s.replace(".", "_");
if ns == "match" || ns == "break" || ns == "yield" {
format!("{ns}_")
} else {
ns
}
}
fn write_rust<W: std::fmt::Write>(w: &mut W, list: &Vec<ParserInst>) -> Result<(), Box<dyn std::error::Error>> {
let mut instructions = list.clone();
for iter in instructions.iter_mut() {
let mut i = 0;
while i < iter.fields.len() {
if iter.fields[i].bits.len() == 0 {
writeln!(w, "// removed empty field #{i} {} of {}", iter.fields[i].name, iter.name)?;
iter.fields.swap_remove(i);
} else {
i += 1;
}
}
}
for e in instructions.iter_mut() {
e.fields.sort_by(|a, b| a.bits[0].0.cmp(&b.bits[0].0));
}
instructions.sort_by(|a, b| a.name.cmp(&b.name));
writeln!(w, "// this file is autogenered, do not modify")?;
/* writeln!(w, r"pub struct Decoder {{
/* symbolic only */
ir: &mut spirv::Emitter
}}")?;*/
writeln!(w, "impl<'a> Decoder<'a> {{")?;
writeln!(w, "\t// {} instructions", instructions.len())?;
writeln!(w, "\tpub fn translate(&self, inst: u128) {{")?;
writeln!(w, "\t\tif false {{")?;
writeln!(w, "\t\t\tunreachable!();")?;
write!(w, "\t\t}} ")?;
for inst in instructions.iter() {
if let Some(opcode_field) = inst.fixed_fields.iter().find(|&e| e.name == "opcode") {
let b_opcode = &opcode_field.bits;
assert!(b_opcode.len() == 2);
write!(w, "else if /*{}*/ ", inst.name)?;
for ff in inst.fixed_fields.iter() {
write!(w, "{}", get_multi_cmp_stmt(ff.total_bits, &ff.bits, ff.value.unwrap()))?;
}
writeln!(w, " {{")?;
writeln!(w, "\t\t\tself.{}(inst);", get_canon_inst_name(&inst.name.to_lowercase()))?;
write!(w, "\t\t}} ")?;
}
}
writeln!(w, "")?;
writeln!(w, "\t}}")?;
writeln!(w, "}}")?;
let mut seen_names = std::collections::BTreeSet::<String>::new();
writeln!(w, "/*")?;
writeln!(w, "impl Decoder {{")?;
for inst in instructions.iter() {
if let Some(opcode_field) = inst.fixed_fields.iter().find(|&e| e.name == "opcode") {
if seen_names.contains(&inst.name) {
//writeln!(w, "// dup {}", inst.name)?;
continue;
}
seen_names.insert(inst.name.clone());
let b_opcode = &opcode_field.bits;
assert!(b_opcode.len() == 2);
writeln!(w, "\tpub fn {}(&self, inst: u128) {{", get_canon_inst_name(&inst.name.to_lowercase()))?;
for f in inst.fields.iter() {
writeln!(w, "\t\tlet _{} = {};", f.name, get_multi_merge_stmt("inst", f.total_bits, &f.bits))?;
}
writeln!(w, "\t\ttodo!();")?;
writeln!(w, "\t}}")?;
}
}
writeln!(w, "}}")?;
writeln!(w, "*/")?;
Ok(())
}
fn get_html_field_color(s: &str) -> u32 {
if s.starts_with("opcode") {
0xffa0a0
} else if s == "ra" {
0xa0ffa0
} else if s == "rb" {
0xffa0ff
} else if s == "rd" {
0xa0ffff
} else if s.starts_with("pg") {
0xe0e0ff
} else if s.is_empty() {
0xe0e0e0
} else {
0xffffff
}
}
fn get_html_field_name(_op: usize, f: &ParserField) -> String {
f.name.clone()
/*if f.name == "opcode" {
format!("0x{:x}", op)
} else {
f.value.map(|e| format!("0x{e:x}"))
.unwrap_or(f.name.clone())
}*/
}
fn get_html_masked_value(ao: usize, f: &ParserField) -> usize {
for i in 0..f.bits.len() {
let count = f.bits[i].1 - f.bits[i].0 + 1;
let offset = f.bits[i].0;
if ao >= offset && ao <= offset + count {
return get_mask(f.bits[i].0, f.bits[i].1);
}
}
unreachable!()
}
fn write_html<W: std::fmt::Write>(w: &mut W, list: &Vec<ParserInst>) -> Result<(), Box<dyn std::error::Error>> {
writeln!(w, r#"<!DOCTYPE html>
<style>
table, th, td {{
border: 1px solid black;
border-collapse: collapse;
}}
</style>
<html>
<body>
"#)?;
writeln!(w, "<h1>SM86_0 (Ampere)</h1>")?;
/*
writeln!(w, "<a href='https://github.com/0xD0GF00D/DocumentSASS/blob/main/NOTES.md'>NOTES</a></br>")?;
writeln!(w, "<a href='https://github.com/NoxNode/AmpItUp'>AmpItUp</a></br>")?;
writeln!(w, "<a href='https://handmade.network/p/691/ampitup/blog/p/9034-iadd3_binary_encoding_breakdown'>IADD32</a></br>")?;
*/
let mut instructions = list.clone();
for iter in instructions.iter_mut() {
let mut i = 0;
while i < iter.fields.len() {
if iter.fields[i].bits.len() == 0 {
writeln!(w, "<b>removed empty field #{i} {} of {}</b>", iter.fields[i].name, iter.name)?;
iter.fields.swap_remove(i);
} else {
i += 1;
}
}
}
for e in instructions.iter_mut() {
e.fields.sort_by(|a, b| a.bits[0].0.cmp(&b.bits[0].0));
}
instructions.sort_by(|a, b| a.name.cmp(&b.name));
let mut count = 0;
let mut seen_insn = std::collections::BTreeSet::<String>::new();
for inst in instructions {
write!(w, "<div>")?;
if seen_insn.iter().find(|&e| *e == inst.name).is_none() {
write!(w, "<hr><h2>{}</h2>", inst.name)?;
}
seen_insn.insert(inst.name);
write!(w, "<table style='width:100%;'>")?;
let elems_per_col = 4;
let elems_per_row = 128 / elems_per_col;
for i in 0..elems_per_col {
write!(w, "<tr>")?;
for j in 0..elems_per_row {
write!(w, "<th style='background-color:#d0d0d0;font-size:8px;'>{}</th>", i * elems_per_row + j)?;
}
write!(w, "</tr>")?;
write!(w, "<tr>")?;
let mut last_stride = 0;
let mut last_name = String::new();
let mut last_value = String::new();
for j in 0..elems_per_row {
let bitpos = i * elems_per_row + j;
let color = get_html_field_color(&last_name);
if let Some(f) = inst.fields.iter()
.find(|&e| e.bits.iter()
.find(|(start, end)| bitpos >= *start && bitpos <= *end).is_some()) {
if last_name != f.name && j != 0 {
write!(w, "<td style=\"background-color:#{color:x};\" colspan=\"{last_stride}\">{last_value}</td>")?;
last_stride = 0;
}
last_stride += 1;
last_name = f.name.clone();
last_value = if f.bits.len() > 1 {
let range = f.bits.iter().find(|(start, end)| bitpos >= *start && bitpos <= *end).unwrap();
format!("{} ({}-{})", f.name, range.0, range.1)
} else {
f.name.clone()
};
} else if let Some(f) = inst.fixed_fields.iter()
.find(|&e| e.bits.iter()
.find(|(start, end)| bitpos >= *start && bitpos <= *end).is_some()) {
if last_name != f.name && j != 0 {
write!(w, "<td style=\"background-color:#{color:x};\" colspan=\"{last_stride}\">{last_value}</td>")?;
last_stride = 0;
}
last_stride += 1;
last_name = f.name.clone();
last_value = format!("{:b}", f.value.unwrap() & get_html_masked_value(bitpos, f));
} else {
if last_name != "" && j != 0 {
write!(w, "<td style=\"background-color:#{color:x};\" colspan=\"{last_stride}\">{last_value}</td>")?;
last_stride = 0;
}
last_stride += 1;
last_name = "".to_string();
last_value = "".to_string();
}
}
let color = get_html_field_color(&last_name);
write!(w, "<td style=\"background-color:#{color:x};\" colspan=\"{last_stride}\">{last_value}</td>")?;
write!(w, "</tr>")?;
}
write!(w, "</table>")?;
write!(w, "</div>")?;
count += 1;
if count >= 16 {
//break;
}
}
writeln!(w, "</body></html>")?;
Ok(())
}
pub fn generate() -> Result<(), Box<dyn std::error::Error>> {
let list = collect_sass_instructions(&std::fs::read_to_string("sm_86_instructions.txt")?)?;
let mut w = String::new();
write_rust(&mut w, &list)?;
let out_dir = std::env::var_os("OUT_DIR").unwrap();
let dest_path = std::path::Path::new(&out_dir).join("sm86_decoder_generated.rs");
std::fs::write(&dest_path, w).unwrap();
//println!("{w}");
Ok(())
}
scripts/sm_86_instructions.txt
+120202
View File
File diff suppressed because it is too large Load Diff
scripts/sm_86_latencies.txt
+346
View File
@@ -0,0 +1,346 @@
OPERATION SETS
int_pipe = {CS2R,CS2Rint_pipe,ICMP,ICMPint_pipe,ISCADD,ISCADDint_pipe,ISCADD32I,ISCADD32Iint_pipe,IMNMX,IMNMXint_pipe,BFE,BFEint_pipe,BFI,BFIint_pipe,SHR,SHRint_pipe,SHL,SHLint_pipe,ISET,ISETint_pipe,ISETP,ISETPint_pipe,SHF,SHFint_pipe,FCMP,FCMPint_pipe,FMNMX,FMNMXint_pipe,FSET,FSETint_pipe,FSETP,FSETPint_pipe,GETFPFLAGS,GETFPFLAGSint_pipe,SETFPFLAGS,SETFPFLAGSint_pipe,SEL,SELint_pipe,FSEL,FSELint_pipe,P2R,P2Rint_pipe,R2P,R2Pint_pipe,CSET,CSETint_pipe,CSETP,CSETPint_pipe,PSET,PSETint_pipe,PSETP,PSETPint_pipe,LEPC,LEPCint_pipe,VOTE,VOTEint_pipe,LEA,LEAint_pipe,PRMT,PRMTint_pipe,VMAD,VMADint_pipe,VADD,VADDint_pipe,VABSDIFF,VABSDIFFint_pipe,VMNMX,VMNMXint_pipe,VSET,VSETint_pipe,VSHL,VSHLint_pipe,VSHR,VSHRint_pipe,VSETP,VSETPint_pipe,VABSDIFF4,VABSDIFF4int_pipe,IDE,IDEint_pipe,IADD3,IADD3int_pipe,IADD,IADDint_pipe,IADD32I,IADD32Iint_pipe,LOP,LOPint_pipe,LOP32I,LOP32Iint_pipe,LOP3,LOP3int_pipe,XMAD,XMADint_pipe,MOV,MOVint_pipe,MOV32I,MOV32Iint_pipe,MOVM,MOVMint_pipe,PLOP3,PLOP3int_pipe,SGXT,SGXTint_pipe,BMSK,BMSKint_pipe,IABS,IABSint_pipe,RPCMOV,RPCMOVint_pipe,IMMA,IMMAint_pipe,I2I,I2Iint_pipe,I2IP,I2IPint_pipe,BMMA,BMMAint_pipe,SCATTER,SCATTERint_pipe,SPMETADATA,SPMETADATAint_pipe,F2FP,F2FPint_pipe,GATHER,GATHERint_pipe,GENMETADATA,GENMETADATAint_pipe,F2IP,F2IPint_pipe,I2FP,I2FPint_pipe,BITEXTRACT,BITEXTRACTint_pipe};
mio_pipe = {IMADSP,IMADSPmio_pipe,MUFU,MUFUmio_pipe,POPC,POPCmio_pipe,FLO,FLOmio_pipe,BREV,BREVmio_pipe,IPA,IPAmio_pipe,LDTRAM,LDTRAMmio_pipe,F2F,F2Fmio_pipe,F2I,F2Imio_pipe,I2F,I2Fmio_pipe,FRND,FRNDmio_pipe,FCHK,FCHKmio_pipe,F2F64,F2F64mio_pipe,I2F64,I2F64mio_pipe,F2I64,F2I64mio_pipe,FRND64,FRND64mio_pipe,AL2P,AL2Pmio_pipe,SETLMEMBASE,SETLMEMBASEmio_pipe,GETLMEMBASE,GETLMEMBASEmio_pipe,S2R,S2Rmio_pipe,B2R,B2Rmio_pipe,R2B,R2Bmio_pipe,BAR,BARmio_pipe,FOOTPRINT,FOOTPRINTmio_pipe,TEX,TEXmio_pipe,TEXS,TEXSmio_pipe,TLD,TLDmio_pipe,TLDS,TLDSmio_pipe,TLD4,TLD4mio_pipe,TLD4S,TLD4Smio_pipe,TMML,TMMLmio_pipe,TXA,TXAmio_pipe,TXD,TXDmio_pipe,TXQ,TXQmio_pipe,PIXLD,PIXLDmio_pipe,LDC,LDCmio_pipe,VILD,VILDmio_pipe,ALD,ALDmio_pipe,LDS,LDSmio_pipe,LDSM,LDSMmio_pipe,SHFL,SHFLmio_pipe,ISBERD,ISBERDmio_pipe,ISBEWR,ISBEWRmio_pipe,ATOMS,ATOMSmio_pipe,AST,ASTmio_pipe,STS,STSmio_pipe,OUT,OUTmio_pipe,MEMBAR,MEMBARmio_pipe,ERRBAR,ERRBARmio_pipe,STG,STGmio_pipe,STL,STLmio_pipe,ST,STmio_pipe,RED,REDmio_pipe,SUST,SUSTmio_pipe,SURED,SUREDmio_pipe,LDG,LDGmio_pipe,LDL,LDLmio_pipe,LD,LDmio_pipe,ATOM,ATOMmio_pipe,ATOMG,ATOMGmio_pipe,CCTL,CCTLmio_pipe,CCTLL,CCTLLmio_pipe,SULD,SULDmio_pipe,SUQUERY,SUQUERYmio_pipe,SUATOM,SUATOMmio_pipe,SUCCTL,SUCCTLmio_pipe,CCTLT,CCTLTmio_pipe,MATCH,MATCHmio_pipe,QSPC,QSPCmio_pipe,SETCTAID,SETCTAIDmio_pipe,LDGSTS,LDGSTSmio_pipe,LDGDEPBAR,LDGDEPBARmio_pipe,ARRIVES,ARRIVESmio_pipe,LD_OLD,LD_OLDmio_pipe,LDG_OLD,LDG_OLDmio_pipe};
fe_pipe = {PMTRIGfe_pipe,PMTRIG,NOP,NOPfe_pipe,DEPBAR,DEPBARfe_pipe,STP,STPfe_pipe,VOTE_VTG,VOTE_VTGfe_pipe,CSMTEST,CSMTESTfe_pipe};
fmalighter_pipe = {FFMA,FFMAfmalighter_pipe,FFMA32I,FFMA32Ifmalighter_pipe,FADD,FADDfmalighter_pipe,FADD32I,FADD32Ifmalighter_pipe,FMUL,FMULfmalighter_pipe,FMUL32I,FMUL32Ifmalighter_pipe,FSWZADD,FSWZADDfmalighter_pipe,RRO,RROfmalighter_pipe,IDP4A,IDP4Afmalighter_pipe,IDP,IDPfmalighter_pipe,IMAD,IMADfmalighter_pipe,IMUL,IMULfmalighter_pipe,IMAD32I,IMAD32Ifmalighter_pipe,IMUL32I,IMUL32Ifmalighter_pipe};
fp16_pipe = {HADD2fp16_pipe,HADD2,HADD2_32Ifp16_pipe,HADD2_32I,HFMA2fp16_pipe,HFMA2,HFMA2_32Ifp16_pipe,HFMA2_32I,HMUL2fp16_pipe,HMUL2,HMUL2_32Ifp16_pipe,HMUL2_32I,HMMA,HMMAfp16_pipe,HSET2fp16_pipe,HSET2,HSETP2fp16_pipe,HSETP2,HMNMX2,HMNMX2fp16_pipe};
cbu_pipe = {BSYNC,BSYNCcbu_pipe,KIL,KILcbu_pipe,KILL,KILLcbu_pipe,YIELD,YIELDcbu_pipe,NANOSLEEP,NANOSLEEPcbu_pipe,NANOTRAP,NANOTRAPcbu_pipe,BRX,BRXcbu_pipe,JMX,JMXcbu_pipe,CALL,CALLcbu_pipe,RET,RETcbu_pipe,BRA,BRAcbu_pipe,JMP,JMPcbu_pipe,EXIT,EXITcbu_pipe,RTT,RTTcbu_pipe,BPT,BPTcbu_pipe,BSSY,BSSYcbu_pipe,BSSY_OLD,BSSY_OLDcbu_pipe,BMOVcbu_pipe,BMOV,BREAK,BREAKcbu_pipe,WARPSYNC,WARPSYNCcbu_pipe,BRXU,BRXUcbu_pipe,JMXU,JMXUcbu_pipe};
fma64lite_pipe = {DFMA,DFMAfma64lite_pipe,DADD,DADDfma64lite_pipe,DMUL,DMULfma64lite_pipe,DSETP,DSETPfma64lite_pipe,DMMA,DMMAfma64lite_pipe,CLMAD,CLMADfma64lite_pipe,HFMA2.MMA,HFMA2.MMAfma64lite_pipe};
fma64heavy_pipe = {DMNMX,DMNMXfma64heavy_pipe,DSET,DSETfma64heavy_pipe};
udp_pipe = {UCLEA,UCLEAudp_pipe,ULDC,ULDCudp_pipe,UF2FP,UF2FPudp_pipe,UMOV,UMOVudp_pipe,UMOV32I,UMOV32Iudp_pipe,UR2UP,UR2UPudp_pipe,UP2UR,UP2URudp_pipe,R2UR,R2URudp_pipe,REDUX,REDUXudp_pipe,S2UR,S2URudp_pipe,VOTEU,VOTEUudp_pipe,UBMSK,UBMSKudp_pipe,UBREV,UBREVudp_pipe,UIADD3,UIADD3udp_pipe,UIADD3.64,UIADD3.64udp_pipe,UIMAD,UIMADudp_pipe,ULEA,ULEAudp_pipe,ULOP3,ULOP3udp_pipe,ULOP,ULOPudp_pipe,ULOP32I,ULOP32Iudp_pipe,USHF,USHFudp_pipe,USHL,USHLudp_pipe,USHR,USHRudp_pipe,UFLO,UFLOudp_pipe,USEL,USELudp_pipe,USGXT,USGXTudp_pipe,UPOPC,UPOPCudp_pipe,UISETP,UISETPudp_pipe,UPLOP3,UPLOP3udp_pipe,UPSETP,UPSETPudp_pipe,UPRMT,UPRMTudp_pipe};
ttu_pipe = {TTUOPEN,TTUOPENttu_pipe,TTUCLOSE,TTUCLOSEttu_pipe,TTUGO,TTUGOttu_pipe,TTULD,TTULDttu_pipe,TTUST,TTUSTttu_pipe,TTUMACROFUSE,TTUMACROFUSEttu_pipe,TTUCCTL,TTUCCTLttu_pipe};
mixed_pipe = { VMAD, VMADmio_pipe };
HMMA_OP = {HMMA,HMMAfp16_pipe};
IMMA_OP = {IMMA,IMMAint_pipe,BMMA,BMMAint_pipe};
DMMA_OP = {DMMA,DMMAfma64lite_pipe};
CLMAD_OP = {CLMAD,CLMADfma64lite_pipe};
MOVM_OP = {MOVM,MOVMint_pipe};
HFMA2MMA_OP = {HFMA2.MMA, HFMA2.MMAfma64lite_pipe};
FXU_OPS = int_pipe + fe_pipe - IMMA_OP - MOVM_OP;
FMAI_OPS = fmalighter_pipe;
FMALITE_OPS = fma64lite_pipe - DMMA_OP - CLMAD_OP - HFMA2MMA_OP;
FP16_ALU_OPS = {HSET2fp16_pipe,HSET2,HSETP2fp16_pipe,HSETP2,HMNMX2,HMNMX2fp16_pipe};
FP16_OPS = fp16_pipe - FP16_ALU_OPS - HMMA_OP;
MATH_OPS = FXU_OPS + FMAI_OPS + FP16_OPS + FP16_ALU_OPS + FMALITE_OPS + HFMA2MMA_OP;
UDP_OPS = udp_pipe;
OP_R2UR = {R2UR,R2URudp_pipe,REDUX,REDUXudp_pipe,S2UR,S2URudp_pipe};
OP_VOTEU = {VOTEU,VOTEUudp_pipe};
OP_ULDC = {ULDC,ULDCudp_pipe};
MIO_OPS = mio_pipe + ttu_pipe + MOVM_OP;
BRU_OPS = cbu_pipe;
MIO_CBU_OPS = MIO_OPS + BRU_OPS;
MIO_SLOW_OPS = {LDS,LDSmio_pipe,STS,STSmio_pipe,ATOMS,ATOMSmio_pipe,ALD,ALDmio_pipe,AST,ASTmio_pipe,
OUT,OUTmio_pipe,IPA,IPAmio_pipe,ISBERD,ISBERDmio_pipe,ISBEWR,ISBEWRmio_pipe,PIXLD,PIXLDmio_pipe,SHFL,SHFLmio_pipe,
S2R,S2Rmio_pipe,MEMBAR,MEMBARmio_pipe,QSPC,QSPCmio_pipe,BAR,BARmio_pipe,B2R,B2Rmio_pipe,R2B,
R2Bmio_pipe,LDL,LDLmio_pipe,LDG,LDGmio_pipe,LD,LDmio_pipe,STL,STLmio_pipe,STG,STGmio_pipe,ST,
STmio_pipe,ATOM,ATOMmio_pipe,RED,REDmio_pipe,ATOMG,ATOMGmio_pipe,CCTL,CCTLmio_pipe,CCTLL,CCTLLmio_pipe,
LDGSTS,LDGSTSmio_pipe,LDSM,LDSMmio_pipe,LD_OLD,LD_OLDmio_pipe,LDG_OLD,LDG_OLDmio_pipe} + MOVM_OP;
MIO_FAST_OPS = MIO_OPS - MIO_SLOW_OPS;
ALL_OPS_WITHOUT_CBU = FXU_OPS + FMAI_OPS + FP16_OPS + FP16_ALU_OPS + FMALITE_OPS + HFMA2MMA_OP + MIO_OPS + HMMA_OP + IMMA_OP + DMMA_OP + CLMAD_OP + UDP_OPS;
IMAD_OP = {IMAD,IMADfmalighter_pipe,IMAD32I,IMAD32Ifmalighter_pipe,
IMUL,IMULfmalighter_pipe,IMUL32I,IMUL32Ifmalighter_pipe};
CCTL_OP = {CCTL,CCTLmio_pipe};
BMOV_OP = {BMOV,BMOVcbu_pipe};
FMAI_WITHOUT_IMAD = FMAI_OPS - IMAD_OP;
ALL_OPS_WITH_BMOV = ALL_OPS_WITHOUT_CBU + BMOV_OP;
ALL_OPS = ALL_OPS_WITHOUT_CBU + BRU_OPS;
HARD RESOURCE
GPR(R1) = { R(0..254), RZ } DEFAULT_ANTI=ORDERED_ZERO DEFAULT_OUTPUT=ORDERED_ZERO;
CONNECTOR NAMES
Ra_with_offset, barname, barcount, Ra, Rb, Rc, Re, Rd, Rd2: GPR;
CONNECTOR CONDITIONS
RaRange = (((((MD_PRED(ISRC_A_SIZE)) >= (1)) ? (MD_PRED(ISRC_A_SIZE)) : (1)) - 1) >> 5) + 1;
RbRange = (((((MD_PRED(ISRC_B_SIZE)) >= (1)) ? (MD_PRED(ISRC_B_SIZE)) : (1)) - 1) >> 5) + 1;
RcRange = (((((MD_PRED(ISRC_C_SIZE)) >= (1)) ? (MD_PRED(ISRC_C_SIZE)) : (1)) - 1) >> 5) + 1;
ReRange = (((((MD_PRED(ISRC_E_SIZE)) >= (1)) ? (MD_PRED(ISRC_E_SIZE)) : (1)) - 1) >> 5) + 1;
RdRange = (((((MD_PRED(IDEST_SIZE)) >= (1)) ? (MD_PRED(IDEST_SIZE)) : (1)) - 1) >> 5) + 1;
Rd2Range = (((((MD_PRED(IDEST2_SIZE)) >= (1)) ? (MD_PRED(IDEST2_SIZE)) : (1)) - 1) >> 5) + 1;
TABLE_TRUE(GPR) : FXU_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange}
FMAI_WITHOUT_IMAD`{Ra @RaRange,Rb @RbRange,Rc @RcRange}
IMAD_OP`{Ra @RaRange,Rb @RbRange,Rc @RcRange}
FP16_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange}
FP16_ALU_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange}
FMALITE_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange}
HFMA2MMA_OP`{Ra @RaRange,Rb @RbRange,Rc @RcRange}
MIO_FAST_OPS`{Ra_with_offset @RaRange,barname @RaRange,barcount @RaRange,Ra @RaRange,Rb @RbRange,Rc @RcRange}
MIO_SLOW_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange}
BRU_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange}
OP_R2UR`{Ra @RaRange}
HMMA_OP`{Ra @RaRange,Rb @RbRange,Re @ReRange}
IMMA_OP`{Ra @RaRange,Rb @RbRange,Re @ReRange}
DMMA_OP`{Ra @RaRange,Rb @RbRange,Re @ReRange}
HMMA_OP`{Rc @RcRange}
IMMA_OP`{Rc @RcRange}
DMMA_OP`{Rc @RcRange}
CLMAD_OP`{Ra @RaRange,Rb @RbRange,Rc @RcRange}=
{
FXU_OPS`{Rd @RdRange,Rd2 @Rd2Range} : 6 6 6 6 6 6 6 4 5 4 6 7 7 7 7 7 7 6
FMAI_WITHOUT_IMAD`{Rd @RdRange,Rd2 @Rd2Range} : 5 4 4 6 6 6 6 4 5 4 6 7 7 7 7 7 7 6
IMAD_OP`{Rd @RdRange,Rd2 @Rd2Range} : 5 4 6 5 5 6 6 4 5 4 6 7 7 7 7 7 7 6
FP16_OPS`{Rd @RdRange,Rd2 @Rd2Range} : 5 5 5 5 5 6 6 4 5 4 6 7 7 7 7 7 7 6
FP16_ALU_OPS`{Rd @RdRange,Rd2 @Rd2Range} : 5 5 5 5 4 6 6 4 5 4 6 7 7 7 7 7 7 6
FMALITE_OPS`{Rd @RdRange,Rd2 @Rd2Range} : 10 10 10 10 10 6 10 6 7 6 10 11 11 11 11 11 11 10
HFMA2MMA_OP`{Rd @RdRange,Rd2 @Rd2Range} : 10 10 10 10 10 6 6 6 7 6 10 11 11 11 11 11 11 10
CLMAD_OP`{Rd @RdRange,Rd2 @Rd2Range} : 12 12 12 12 12 12 12 8 9 8 12 13 13 13 13 13 13 8
HMMA_OP`{Rd @RdRange,Rd2 @Rd2Range} : 27 27 27 27 27 27 27 22 23 22 27 28 28 28 28 28 28 27
IMMA_OP`{Rd @RdRange,Rd2 @Rd2Range} : 27 27 27 27 27 27 27 22 24 22 27 28 28 28 28 28 28 27
DMMA_OP`{Rd @RdRange,Rd2 @Rd2Range} : 25 25 25 25 25 25 25 23 24 23 25 26 26 26 26 26 18 25
};
TABLE_OUTPUT(GPR) : FXU_OPS`{Rd @RdRange,Rd2 @Rd2Range}
FMAI_OPS`{Rd @RdRange,Rd2 @Rd2Range}
FP16_OPS`{Rd @RdRange,Rd2 @Rd2Range}
FP16_ALU_OPS`{Rd @RdRange,Rd2 @Rd2Range}
FMALITE_OPS`{Rd @RdRange,Rd2 @Rd2Range}
HFMA2MMA_OP`{Rd @RdRange,Rd2 @Rd2Range}
MIO_OPS`{Rd @RdRange,Rd2 @Rd2Range}
BRU_OPS`{Rd @RdRange,Rd2 @Rd2Range}
CLMAD_OP`{Rd @RdRange,Rd2 @Rd2Range}
IMMA_OP`{Rd @RdRange,Rd2 @Rd2Range}
HMMA_OP`{Rd @RdRange,Rd2 @Rd2Range}
DMMA_OP`{Rd @RdRange,Rd2 @Rd2Range}=
{
FXU_OPS`{Rd @RdRange,Rd2 @Rd2Range} : 1 1 1 1 1 1 1 1 2 2 2 2
FMAI_OPS`{Rd @RdRange,Rd2 @Rd2Range} : 1 1 1 1 1 1 1 1 2 2 2 2
FP16_OPS`{Rd @RdRange,Rd2 @Rd2Range} : 1 1 1 1 1 1 1 1 2 2 2 2
FP16_ALU_OPS`{Rd @RdRange,Rd2 @Rd2Range} : 1 1 1 1 1 1 1 1 2 2 2 2
FMALITE_OPS`{Rd @RdRange,Rd2 @Rd2Range} : 3 3 3 2 2 3 1 1 2 2 2 2
HFMA2MMA_OP`{Rd @RdRange,Rd2 @Rd2Range} : 3 3 3 3 2 2 1 1 2 2 2 2
CLMAD_OP`{Rd @RdRange,Rd2 @Rd2Range} : 5 5 5 5 5 5 1 1 2 2 2 2
IMMA_OP`{Rd @RdRange,Rd2 @Rd2Range} : 22 22 22 22 22 22 21 21 21 18 18 18
HMMA_OP`{Rd @RdRange,Rd2 @Rd2Range} : 22 22 22 22 22 22 21 21 21 18 18 18
DMMA_OP`{Rd @RdRange,Rd2 @Rd2Range} : 20 20 20 20 20 20 19 19 19 17 17 16
};
TABLE_ANTI(GPR) : FXU_OPS`{Rd @RdRange,Rd2 @Rd2Range}
FMAI_OPS`{Rd @RdRange,Rd2 @Rd2Range}
FP16_OPS`{Rd @RdRange,Rd2 @Rd2Range}
FP16_ALU_OPS`{Rd @RdRange,Rd2 @Rd2Range}
FMALITE_OPS`{Rd @RdRange,Rd2 @Rd2Range}
HFMA2MMA_OP`{Rd @RdRange,Rd2 @Rd2Range}
MIO_OPS`{Rd @RdRange,Rd2 @Rd2Range}
BRU_OPS`{Rd @RdRange,Rd2 @Rd2Range}
CLMAD_OP`{Rd @RdRange}
IMMA_OP`{Rd @RdRange}
HMMA_OP`{Rd @RdRange}
DMMA_OP`{Rd @RdRange}=
{
FXU_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange} : 1 1 1 1 1 1 2 2 2 2 2 2
FMAI_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange} : 1 1 1 1 1 1 2 2 2 2 2 2
FP16_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange} : 1 1 2 2 1 1 2 2 2 2 2 2
FP16_ALU_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange} : 1 1 2 2 1 1 2 2 2 2 2 2
FMALITE_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange} : 1 1 1 1 1 1 1 1 1 1 1 1
HFMA2MMA_OP`{Ra @RaRange,Rb @RbRange,Rc @RcRange} : 1 1 1 1 1 1 2 2 2 2 2 2
CLMAD_OP`{Ra @RaRange,Rb @RbRange,Rc @RcRange} : 1 1 1 1 1 1 1 1 1 1 1 1
IMMA_OP`{Ra @RaRange,Rb @RbRange,Rc @RcRange,Re @ReRange} : 7 7 7 7 1 7 1 7 1 1 1 1
HMMA_OP`{Ra @RaRange,Rb @RbRange,Rc @RcRange,Re @ReRange} : 7 7 7 7 1 7 1 7 1 1 1 1
DMMA_OP`{Ra @RaRange,Rb @RbRange,Rc @RcRange,Re @ReRange} : 1 1 1 1 1 1 1 1 1 1 1 1
CCTL_OP`{Ra @RaRange,Rb @RbRange} : 1 1 1 1 1 1 1 1 2 2 2 2
};
TABLE_TRUE(GPR) : ALL_OPS`{Ra @RaRange,Rb @RbRange,Rc @RcRange,Re @ReRange} = { MIO_CBU_OPS`{Rd @RdRange,Rd2 @Rd2Range} : 2 };
HARD RESOURCE
UGPR(UR1) = { UR(0..62), URZ } DEFAULT_ANTI=ORDERED_ZERO DEFAULT_OUTPUT=ORDERED_ZERO;
CONNECTOR NAMES
URa, URb, URc, Ra_URb, Ra_URc, Rb_URc, URd, URd2, UR, attr, Ra_URd: UGPR;
CONNECTOR CONDITIONS
URaRange = (((((MD_PRED(ISRC_A_SIZE)) >= (1)) ? (MD_PRED(ISRC_A_SIZE)) : (1)) - 1) >> 5) + 1;
URbRange = (((((MD_PRED(ISRC_B_SIZE)) >= (1)) ? (MD_PRED(ISRC_B_SIZE)) : (1)) - 1) >> 5) + 1;
URcRange = (((((MD_PRED(ISRC_C_SIZE)) >= (1)) ? (MD_PRED(ISRC_C_SIZE)) : (1)) - 1) >> 5) + 1;
UReRange = (((((MD_PRED(ISRC_E_SIZE)) >= (1)) ? (MD_PRED(ISRC_E_SIZE)) : (1)) - 1) >> 5) + 1;
URdRange = (((((MD_PRED(IDEST_SIZE)) >= (1)) ? (MD_PRED(IDEST_SIZE)) : (1)) - 1) >> 5) + 1;
URd2Range = (((((MD_PRED(IDEST2_SIZE)) >= (1)) ? (MD_PRED(IDEST2_SIZE)) : (1)) - 1) >> 5) + 1;
OPERATION SETS
OP_UMOV = {UMOV,UMOVudp_pipe};
ULDC_VOTEU = OP_ULDC + OP_VOTEU;
ULDC_VOTEU_UMOV = OP_ULDC + OP_VOTEU + OP_UMOV;
R2UR_S2UR = {R2UR,R2URudp_pipe,REDUX,REDUXudp_pipe,S2UR,S2URudp_pipe};
MOV_OP = {MOV,MOVint_pipe};
UDP_subset = UDP_OPS - R2UR_S2UR - ULDC_VOTEU_UMOV;
RPCMOV_OP = {RPCMOV,RPCMOVint_pipe};
MATH_OPS_WITHOUT_RPCMOV = MATH_OPS - RPCMOV_OP + CLMAD_OP;
TABLE_TRUE(UGPR) : UDP_subset`{URa @URaRange,UR @URaRange,URb @URbRange,URc @URcRange,Ra_URb @URaRange,Ra_URc @URaRange,Rb_URc @URbRange}
MATH_OPS_WITHOUT_RPCMOV`{URa @URaRange,UR @URaRange,URb @URbRange,URc @URcRange,Ra_URb @URaRange,Ra_URc @URaRange,Rb_URc @URbRange}
MIO_CBU_OPS`{attr @URaRange,URa @URaRange,UR @URaRange,URb @URbRange,URc @URcRange,Ra_URb @URaRange,Ra_URc @URaRange,Rb_URc @URbRange,Ra_URd @URcRange}
ULDC_VOTEU`{URa @URaRange,UR @URaRange,URb @URbRange,URc @URcRange,Ra_URb @URaRange,Ra_URc @URaRange,Rb_URc @URbRange}
OP_UMOV`{URa @URaRange,UR @URaRange,URb @URbRange,URc @URcRange,Ra_URb @URaRange,Ra_URc @URaRange,Rb_URc @URbRange}
RPCMOV_OP`{URa @URaRange,UR @URaRange,URb @URbRange,URc @URcRange,Ra_URb @URaRange,Ra_URc @URaRange,Rb_URc @URbRange}
HMMA_OP`{URd @URdRange,URc @URcRange}
MOV_OP`{URd @URdRange}=
{
UDP_subset`{URd @URdRange,URd2 @URd2Range} : 4 12 12 12 7 9 12 12
R2UR_S2UR`{URd @URdRange,URd2 @URd2Range} : 2 2 3 2 2 2 2 2
ULDC_VOTEU_UMOV`{URd @URdRange,URd2 @URd2Range} : 2 5 5 5 2 2 5 5
};
TABLE_OUTPUT(UGPR) : UDP_subset`{URd @URdRange,URd2 @URd2Range}
R2UR_S2UR`{URd @URdRange,URd2 @URd2Range}
ULDC_VOTEU_UMOV`{URd @URdRange,URd2 @URd2Range}=
{
UDP_subset`{URd @URdRange,URd2 @URd2Range} : 1 4 7
R2UR_S2UR`{URd @URdRange,URd2 @URd2Range} : 2 2 2
ULDC_VOTEU_UMOV`{URd @URdRange,URd2 @URd2Range} : 1 4 1
};
TABLE_ANTI(UGPR) : UDP_subset`{URd @URdRange,URd2 @URd2Range}
R2UR_S2UR`{URd @URdRange,URd2 @URd2Range}
ULDC_VOTEU_UMOV`{URd @URdRange,URd2 @URd2Range}=
{
UDP_subset`{URa @URaRange,UR @URaRange,URb @URbRange,URc @URcRange,Ra_URb @URaRange,Ra_URc @URaRange,Rb_URc @URbRange} : 1 1 3
MATH_OPS`{URa @URaRange,UR @URaRange,URb @URbRange,URc @URcRange,Ra_URb @URaRange,Ra_URc @URaRange,Rb_URc @URbRange,URd @URdRange} : 1 1 1
MIO_CBU_OPS`{attr @URaRange,URa @URaRange,UR @URaRange,URb @URbRange,URc @URcRange,Ra_URb @URaRange,Ra_URc @URaRange,Rb_URc @URbRange,Ra_URd @URcRange} : 1 1 1
OP_UMOV`{URa @URaRange,UR @URaRange,URb @URbRange,URc @URcRange,Ra_URb @URaRange,Ra_URc @URaRange,Rb_URc @URbRange} : 1 1 1
OP_ULDC`{URa @URaRange,UR @URaRange,URb @URbRange,URc @URcRange,Ra_URb @URaRange,Ra_URc @URaRange,Rb_URc @URbRange} : 1 1 1
};
RESOURCE
SCOREBOARD (SB0) = { SB(0..5) } DEFAULT_OUTPUT=- DEFAULT_ANTI=ORDERED_ZERO;
CONNECTOR NAME
sBoard {} : SCOREBOARD;
sbidx : SCOREBOARD;
OPERATION SETS
DEPBAR = {DEPBAR,DEPBARfe_pipe};
CBU_OPS_WITH_REQ = {BRA,BRAcbu_pipe,NANOSLEEP,NANOSLEEPcbu_pipe,NANOTRAP,NANOTRAPcbu_pipe,BRX,BRXcbu_pipe,JMX,JMXcbu_pipe,CALL,CALLcbu_pipe,RET,RETcbu_pipe,BMOV,BMOVcbu_pipe,BREAK,BREAKcbu_pipe,WARPSYNC,WARPSYNCcbu_pipe,BRXU,BRXUcbu_pipe,JMXU,JMXUcbu_pipe};
TABLE_TRUE(SCOREBOARD) : ALL_OPS_WITH_BMOV`{sBoard}
DEPBAR`{sbidx}
CBU_OPS_WITH_REQ`{sBoard}
= { ALL_OPS_WITH_BMOV`{sBoard} : ORDERED_ZERO };
HARD RESOURCE
PRED(P1) = { P(0..6), PT } DEFAULT_ANTI=ORDERED_ZERO DEFAULT_OUTPUT=ORDERED_ZERO;
CONNECTOR NAMES
Pr, Pu, Pv, Pq, Pp, Pa, Pb, Pc, Pg, Ps, Plg, Pd, nPd, Pnz : PRED;
PR_PRED { P(0..6) } : PRED;
OPERATION SETS
OP_P2R = {P2Rint_pipe,P2R};
OP_R2P = {R2Pint_pipe,R2P};
OP_CSMTEST = {CSMTESTfe_pipe,CSMTEST,VOTE_VTGfe_pipe,VOTE_VTG};
OP_VOTE = {VOTE, VOTEint_pipe};
MATH_PRED_OPS = MATH_OPS - OP_VOTE;
CoupledDispOverlapWithMathOps = {NOP,NOPfe_pipe,CS2R,CS2Rint_pipe,LEPC,LEPCint_pipe,RPCMOV,RPCMOVint_pipe,PMTRIG,PMTRIGfe_pipe,DEPBAR,DEPBARfe_pipe,IDE,IDEint_pipe};
MATH_PRED_NO_FP16_FP64_OPS = MATH_OPS - OP_VOTE - FMALITE_OPS - FP16_OPS - FP16_ALU_OPS - CoupledDispOverlapWithMathOps;
FMALITE_WITH_HMMA = FMALITE_OPS + HMMA_OP + DMMA_OP;
FXU_WITH_IMMA = FXU_OPS + IMMA_OP;
MATH_WITH_MMA = MATH_OPS + HMMA_OP + IMMA_OP + DMMA_OP + CLMAD_OP;
FP16_OPS_ALL = FP16_OPS + FP16_ALU_OPS;
CONNECTOR CONDITIONS
VTG_PRED = ((vtgmode == 2 || vtgmode == 3) _OR_ 0);
CONNECTOR SETS
NON_MATH_PRED_READERS = OP_P2R`{PR_PRED} + OP_R2P`{PR_PRED} + OP_CSMTEST[VTG_PRED]`{PR_PRED} + OP_VOTE`{Pr,Pq,Pp,Pa,Pb,Pc,Ps,Plg,Pnz};
TABLE_TRUE(PRED) : MATH_PRED_NO_FP16_FP64_OPS`{Pr,Pq,Pp,Pa,Pb,Pc,Ps,Plg}
FP16_OPS_ALL`{Pr,Pq,Pp,Pa,Pb,Pc,Ps,Plg}
FMALITE_OPS`{Pr,Pq,Pp,Pa,Pb,Pc,Ps,Plg}
NON_MATH_PRED_READERS
CoupledDispOverlapWithMathOps`{Pr,Pq,Pp,Pa,Pb,Pc,Ps,Plg}
MIO_OPS`{Pr,Pq,Pp,Pa,Pb,Pc,Pg,Ps,Plg,Pnz}
OP_R2UR`{Pg}
OP_VOTEU`{Pg,Pp}
BRU_OPS`{Pr,Pq,Pp,Pa,Pb,Pc,Pg,Ps,Plg,Pnz}
MATH_WITH_MMA`{Pg}=
{
FXU_WITH_IMMA`{Pu,Pv,Pd,nPd} : 5 13 13 13 13 13 13 13 13 13
OP_R2P`{Pu,Pv,PR_PRED} : 5 13 13 13 13 13 13 13 13 13
FMAI_OPS`{Pu,Pv,Pd,nPd} : 5 13 13 13 13 13 13 13 13 13
FP16_OPS_ALL`{Pu,Pv,Pd,nPd} : 5 5 13 13 13 13 13 13 13 13
FMALITE_WITH_HMMA`{Pu,Pv,Pd,nPd} : 6 14 6 14 14 14 14 14 14 14
MIO_OPS`{Pu,Pv,Pd,nPd,Pnz} : 1 1 1 1 1 1 1 1 1 1
OP_R2UR`{Pu} : 1 1 1 1 1 1 1 1 1 1
};
TABLE_OUTPUT(PRED) : FXU_WITH_IMMA`{Pu,Pv,Pd,nPd}
FMAI_OPS`{Pu,Pv,Pd,nPd}
FP16_OPS_ALL`{Pu,Pv,Pd,nPd}
FMALITE_WITH_HMMA`{Pu,Pv,Pd,nPd}
MIO_OPS`{Pu,Pv,Pd,nPd,Pnz}
OP_R2UR`{Pu}=
{
FXU_WITH_IMMA`{Pu,Pv,Pd,nPd} : 1 1 2 2 2 2
FMAI_OPS`{Pu,Pv,Pd,nPd} : 1 1 2 2 2 2
FP16_OPS_ALL`{Pu,Pv,Pd,nPd} : 1 1 1 2 2 2
FMALITE_WITH_HMMA`{Pu,Pv,Pd,nPd} : 2 2 2 1 1 1
OP_R2P`{Pu,Pv,PR_PRED} : 1 1 2 2 2 2
OP_R2UR`{Pu} : 2 2 2 2 2 2
};
TABLE_ANTI(PRED) : FXU_WITH_IMMA`{Pu,Pv,Pd,nPd}
FMAI_OPS`{Pu,Pv,Pd,nPd}
OP_R2P`{Pu,Pv,PR_PRED}
FP16_OPS_ALL`{Pu,Pv,Pd,nPd}
FMALITE_WITH_HMMA`{Pu,Pv,Pd,nPd}
MIO_OPS`{Pu,Pv,Pd,nPd,Pnz}
OP_R2UR`{Pu}=
{
MATH_PRED_OPS`{Pr,Pq,Pp,Pa,Pb,Pc,Ps,Plg}: 1 1 1 1 1 1 1
NON_MATH_PRED_READERS : 1 1 1 1 1 1 1
MIO_OPS`{Pr,Pq,Pp,Pa,Pb,Pc,Ps,Plg} : 1 1 1 1 1 1 1
MIO_OPS`{Pg} : 1 1 1 1 1 1 1
OP_R2UR`{Pg} : 1 1 1 1 1 1 1
BRU_OPS`{Pr,Pq,Pp,Pa,Pb,Pc,Ps,Plg} : 1 1 1 1 1 1 1
BRU_OPS`{Pg} : 1 1 1 1 1 1 1
MATH_WITH_MMA`{Pg} : 1 1 1 1 1 1 1
OP_VOTEU`{Pp,Pg} : 1 1 1 1 1 1 1
};
HARD RESOURCE
UPRED(UP1) = { UP(0..6), UPT } DEFAULT_ANTI=ORDERED_ZERO DEFAULT_OUTPUT=ORDERED_ZERO;
CONNECTOR NAMES
UPx, UPp, UPq, UPr, UPu, UPv, UPg : UPRED;
UPR_UPRED { UP(0..6) } : UPRED;
OPERATION SETS
OP_UP2UR = {UP2UR,UP2URudp_pipe};
OP_UR2UP = {UR2UP,UR2UPudp_pipe};
UPRED_OPS = UDP_OPS - OP_ULDC - OP_VOTEU - OP_UP2UR - OP_UR2UP;
OP_BRA_JMP = {BRA, BRAcbu_pipe, JMP, JMPcbu_pipe};
VECTOR_INST = {PLOP3, PLOP3int_pipe, PSETP, PSETPint_pipe} + BRU_OPS - OP_BRA_JMP;
MMA_OPS = HMMA_OP + IMMA_OP + DMMA_OP;
CONNECTOR SETS
WHOLE_UPRED_OPS = OP_UP2UR`{UPR_UPRED} + OP_UR2UP`{UPR_UPRED};
TABLE_TRUE(UPRED) : VECTOR_INST`{UPr,UPq,UPp}
UPRED_OPS`{UPr,UPq,UPp}
WHOLE_UPRED_OPS
UDP_OPS`{UPg}
OP_BRA_JMP`{UPr,UPq,UPp}
OP_ULDC`{UPx}
MMA_OPS`{UPp}=
{
UPRED_OPS`{UPu,UPv} : 6 4 4 11 9 11 11
OP_UR2UP`{UPR_UPRED} : 6 4 4 11 9 11 11
OP_VOTEU`{UPu,UPv} : 1 1 1 5 2 5 5
};
TABLE_OUTPUT(UPRED) : UPRED_OPS`{UPu,UPv}
OP_UR2UP`{UPR_UPRED}
OP_VOTEU`{UPu,UPv}=
{
UPRED_OPS`{UPu,UPv} : 1 1 7
OP_UR2UP`{UPR_UPRED} : 1 1 7
OP_VOTEU`{UPu,UPv} : 1 1 1
};
TABLE_ANTI(UPRED) : UPRED_OPS`{UPu,UPv}
OP_VOTEU`{UPu,UPv}=
{
UPRED_OPS`{UPx,UPr,UPq,UPp} : 1 2
VECTOR_INST`{UPr} : 1 2
WHOLE_UPRED_OPS : 1 2
MMA_OPS`{UPp} : 1 1
UDP_OPS`{UPg} : 1 1
OP_BRA_JMP`{UPr} : 1 1
};
HARD RESOURCE
MEMORY DEFAULT_OUTPUT=1 DEFAULT_ANTI=0;
CONNECTOR NAME
Mem : MEMORY;
RESOURCE
CC DEFAULT_OUTPUT=1 DEFAULT_ANTI=1;
RESOURCE
BSTACK DEFAULT_OUTPUT=1 DEFAULT_ANTI=1;
RESOURCE
CONTROL DEFAULT_OUTPUT=HARD(1) DEFAULT_ANTI=HARD(1);
CONNECTOR NAME
Ctl : CONTROL;
TABLE_OUTPUT(CONTROL) : BRU_OPS`{Ctl} = { BRU_OPS`{Ctl} : 1 };
OPERATION SETS
BAR_OP = {BAR,BARmio_pipe};
ALL_OPS_WITHOUT_BAR = ALL_OPS - BAR_OP;
PIPELINE RESOURCE FXU_Occupancy : 1;
PIPELINE RESOURCE FMAI_Occupancy : 1;
PIPELINE RESOURCE FMALITE_Occupancy : 1;
PIPELINE RESOURCE BARWAIT_Occupancy : 1;
OPERATION PIPELINE RESOURCES
FXU_OPS : FXU_Occupancy [2];
FMAI_OPS : FMAI_Occupancy [2];
FMALITE_OPS : FMALITE_Occupancy [2];
HMMA_OP : FMALITE_Occupancy [2];
IMMA_OP : FXU_Occupancy [2];
DMMA_OP : FMALITE_Occupancy [4];
BAR_OP : BARWAIT_Occupancy [6];
ALL_OPS_WITHOUT_BAR : BARWAIT_Occupancy [1];