Commit Graph

671 Commits

Author SHA1 Message Date
Juan Castillo
05799ae0c8 TBB: add authentication framework
This patch adds the authentication framework that will be used as
the base to implement Trusted Board Boot in the Trusted Firmware.
The framework comprises the following modules:

- Image Parser Module (IPM)

    This module is responsible for interpreting images, check
    their integrity and extract authentication information from
    them during Trusted Board Boot.

    The module currently supports three types of images i.e.
    raw binaries, X509v3 certificates and any type specific to
    a platform. An image parser library must be registered for
    each image type (the only exception is the raw image parser,
    which is included in the main module by default).

    Each parser library (if used) must export a structure in a
    specific linker section which contains function pointers to:

        1. Initialize the library
        2. Check the integrity of the image type supported by
           the library
        3. Extract authentication information from the image

- Cryptographic Module (CM)

    This module is responsible for verifying digital signatures
    and hashes. It relies on an external cryptographic library
    to perform the cryptographic operations.

    To register a cryptographic library, the library must use the
    REGISTER_CRYPTO_LIB macro, passing function pointers to:

        1. Initialize the library
        2. Verify a digital signature
        3. Verify a hash

    Failing to register a cryptographic library will generate
    a build time error.

- Authentication Module (AM)

    This module provides methods to authenticate an image, like
    hash comparison or digital signatures. It uses the image parser
    module to extract authentication parameters, the crypto module
    to perform cryptographic operations and the Chain of Trust to
    authenticate the images.

    The Chain of Trust (CoT) is a data structure that defines the
    dependencies between images and the authentication methods
    that must be followed to authenticate an image.

The Chain of Trust, when added, must provide a header file named
cot_def.h with the following definitions:

- COT_MAX_VERIFIED_PARAMS

    Integer value indicating the maximum number of authentication
    parameters an image can present. This value will be used by the
    authentication module to allocate the memory required to load
    the parameters in the image descriptor.

Change-Id: Ied11bd5cd410e1df8767a1df23bb720ce7e58178
2015-06-25 08:53:26 +01:00
Juan Castillo
95cfd4ad84 TBB: add platform API to read the ROTPK information
This patch extends the platform port by adding an API that returns
either the Root of Trust public key (ROTPK) or its hash. This is
usually stored in ROM or eFUSE memory. The ROTPK returned must be
encoded in DER format according to the following ASN.1 structure:

    SubjectPublicKeyInfo  ::=  SEQUENCE  {
        algorithm           AlgorithmIdentifier,
        subjectPublicKey    BIT STRING
    }

In case the platform returns a hash of the key:

    DigestInfo  ::= SEQUENCE {
        digestAlgorithm     AlgorithmIdentifier,
        keyDigest           OCTET STRING
    }

An implementation for ARM development platforms is provided in this
patch. When TBB is enabled, the ROTPK hash location must be specified
using the build option 'ARM_ROTPK_LOCATION'. Available options are:

    - 'regs' : return the ROTPK hash stored in the Trusted
      root-key storage registers.

    - 'devel_rsa' : return a ROTPK hash embedded in the BL1 and
      BL2 binaries. This hash has been obtained from the development
      RSA public key located in 'plat/arm/board/common/rotpk'.

On FVP, the number of MMU tables has been increased to map and
access the ROTPK registers.

A new file 'board_common.mk' has been added to improve code sharing
in the ARM develelopment platforms.

Change-Id: Ib25862e5507d1438da10773e62bd338da8f360bf
2015-06-25 08:53:26 +01:00
Juan Castillo
16948ae1d9 Use numbers to identify images instead of names
The Trusted firmware code identifies BL images by name. The platform
port defines a name for each image e.g. the IO framework uses this
mechanism in the platform function plat_get_image_source(). For
a given image name, it returns the handle to the image file which
involves comparing images names. In addition, if the image is
packaged in a FIP, a name comparison is required to find the UUID
for the image. This method is not optimal.

This patch changes the interface between the generic and platform
code with regard to identifying images. The platform port must now
allocate a unique number (ID) for every image. The generic code will
use the image ID instead of the name to access its attributes.

As a result, the plat_get_image_source() function now takes an image
ID as an input parameter. The organisation of data structures within
the IO framework has been rationalised to use an image ID as an index
into an array which contains attributes of the image such as UUID and
name. This prevents the name comparisons.

A new type 'io_uuid_spec_t' has been introduced in the IO framework
to specify images identified by UUID (i.e. when the image is contained
in a FIP file). There is no longer need to maintain a look-up table
[iname_name --> uuid] in the io_fip driver code.

Because image names are no longer mandatory in the platform port, the
debug messages in the generic code will show the image identifier
instead of the file name. The platforms that support semihosting to
load images (i.e. FVP) must provide the file names as definitions
private to the platform.

The ARM platform ports and documentation have been updated accordingly.
All ARM platforms reuse the image IDs defined in the platform common
code. These IDs will be used to access other attributes of an image in
subsequent patches.

IMPORTANT: applying this patch breaks compatibility for platforms that
use TF BL1 or BL2 images or the image loading code. The platform port
must be updated to match the new interface.

Change-Id: I9c1b04cb1a0684c6ee65dee66146dd6731751ea5
2015-06-25 08:53:26 +01:00
Juan Castillo
d5e0a933b3 TBB: replace assert() with runtime checks in PolarSSL module
Using assert() to check the length of keys and hashes included in
a certificate is not a safe approach because assert() only applies
to debug builds. A malformed certificate could exploit security
flaws in release binaries due to buffer overflows.

This patch replaces assert() with runtime checkings in the PolarSSL
authentication module, so malformed certificates can not cause a
memory overflow.

Change-Id: I42ba912020595752c806cbd242fe3c74077d993b
2015-06-25 08:53:26 +01:00
Juan Castillo
c3da66b1bb TBB: use ASN.1 type DigestInfo to represent hashes
The cert_create tool calculates the hash of each BL image and includes
it as an ASN.1 OCTET STRING in the corresponding certificate extension.
Without additional information, the firmware running on the platform
has to know in advance the algorithm used to generate the hash.

This patch modifies the cert_create tool so the certificate extensions
that include an image hash are generated according to the following
ASN.1 structure:

    DigestInfo ::= SEQUENCE {
        digestAlgorithm  AlgorithmIdentifier,
        digest           OCTET STRING
    }

    AlgorithmIdentifier ::=  SEQUENCE  {
        algorithm        OBJECT IDENTIFIER,
        parameters       ANY DEFINED BY algorithm OPTIONAL
    }

The PolarSSL module has been updated to extract the image hash
from the certificate extension according to this structure.

Change-Id: I6d83430f12a8a0eea8447bec7c936e903f644c85
2015-06-25 08:53:26 +01:00
Juan Castillo
fd34e7ba77 TBB: add build option to save private keys
This patch adds a boolean build option 'SAVE_KEYS' to indicate the
certificate generation tool that it must save the private keys used
to establish the chain of trust. This option depends on 'CREATE_KEYS'
to be enabled. Default is '0' (do not save).

Because the same filenames are used as outputs to save the keys,
they are no longer a dependency to the cert_tool. This dependency
has been removed from the Makefile.

Documentation updated accordingly.

Change-Id: I67ab1c2b1f8a25793f0de95e8620ce7596a6bc3b
2015-06-25 08:53:26 +01:00
danh-arm
dba1289403 Merge pull request #325 from sandrine-bailleux/sb/fix-rw-data-relocation
Bug fix: Build time condition to relocate RW data
2015-06-24 19:05:50 +01:00
Sandrine Bailleux
c9915c0b0f Bug fix: Build time condition to relocate RW data
This patch fixes the build time condition deciding whether the
read-write data should be relocated from ROM to RAM. It was incorrectly
using __DATA_ROM_START__, which is a linker symbol and not a compiler
build flag. As a result, the relocation code was always compiled out.

This bug has been introduced by the following patch:
"Rationalize reset handling code"

Change-Id: I1c8d49de32f791551ab4ac832bd45101d6934045
2015-06-24 17:19:26 +01:00
danh-arm
5a6954fbfb Merge pull request #321 from vwadekar/tegra-gic-implementation-v1
Add missing features to the Tegra GIC driver
2015-06-24 11:41:24 +01:00
danh-arm
e347e843a9 Merge pull request #310 from sandrine-bailleux/sb/tf-issue-304-phase1
Enhance BL3-1 entrypoint handling to support non-TF boot firmware - Phase 1
2015-06-24 11:23:33 +01:00
Varun Wadekar
e1e094c799 Add missing features to the Tegra GIC driver
In order to handle secure/non-secure interrupts, overload the plat_ic_*
functions and copy GIC helper functions from arm_gic.c. Use arm_gic.c
as the reference to add Tegra's GIC helper functions.

Now that Tegra has its own GIC implementation, we have no use for
plat_gic.c and arm_gic.c files.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-06-22 14:55:49 +05:30
danh-arm
f1f99f3af5 Merge pull request #322 from athoelke/at/fix-bl1-assertions
Fix incorrect assertions in bl1_main()
2015-06-19 14:17:14 +01:00
danh-arm
08b337f50d Merge pull request #323 from athoelke/at/fix-aff-inst-overflow
Fix integer extension in mpidr_set_aff_inst()
2015-06-19 14:16:40 +01:00
Andrew Thoelke
354ab57dba Fix incorrect assertions in bl1_main()
The validation of the caching enable state in bl1_main() was
incorrect resulting in the state not being checked. Using the right
operator fixes this.

Change-Id: I2a99478f420281a1dcdf365d3d4fd8394cd21b51
2015-06-19 11:29:41 +01:00
Andrew Thoelke
9b89613eeb Fix integer extension in mpidr_set_aff_inst()
mpidr_set_aff_inst() is left shifting an int constant and an
unsigned char value to construct an MPIDR. For affinity level 3 a
shift of 32 would result in shifting out of the 32-bit type and
have no effect on the MPIDR.

These values need to be extended to unsigned long before shifting
to ensure correct results for affinity level 3.

Change-Id: I1ef40afea535f14cfd820c347a065a228e8f4536
2015-06-19 11:26:16 +01:00
danh-arm
649591bbab Merge pull request #320 from danh-arm/rh/timer-api-v10
Add delay timer API v10
2015-06-18 16:55:47 +01:00
Ryan Harkin
b49b322190 FVP: Add SP804 delay timer
Add SP804 delay timer support to the FVP BSP.

This commit simply provides the 3 constants needed by the SP804
delay timer driver and calls sp804_timer_init() in
bl2_platform_setup(). The BSP does not currently use the delay
timer functions.

Note that the FVP SP804 is a normal world accessible peripheral
and should not be used by the secure world after transition
to the normal world.

Change-Id: I5f91d2ac9eb336fd81943b3bb388860dfb5f2b39
Co-authored-by: Dan Handley <dan.handley@arm.com>
2015-06-18 16:06:32 +01:00
Ryan Harkin
cc58b2d0f5 Add SP804 delay timer driver
Add a delay timer driver for the ARM SP804 dual timer.

This driver only uses the first timer, called timer 1 in the
SP804 Technical Reference Manual (ARM DDI 0271D).

To use this driver, the BSP must provide three constants:

*   The base address of the SP804 dual timer
*   The clock multiplier
*   The clock divider

The BSP is responsible for calling sp804_timer_init(). The SP804
driver instantiates a constant timer_ops_t and calls the generic
timer_init().

Change-Id: I49ba0a52bdf6072f403d1d0a20e305151d4bc086
Co-authored-by: Dan Handley <dan.handley@arm.com>
2015-06-18 16:06:26 +01:00
danh-arm
09aa0392b3 Merge pull request #319 from vwadekar/tegra-video-mem-aperture-v3
Reserve a Video Memory aperture in DRAM memory
2015-06-18 14:58:33 +01:00
Ryan Harkin
9055c7d149 Add a simple delay timer driver API
The API is simple. The BSP or specific timer driver creates an
instance of timer_ops_t, fills in the timer specific data, then calls
timer_init(). The timer specific data includes a function pointer
to return the timer value and a clock multiplier/divider. The ratio
of the multiplier and the divider is the clock frequency in MHz.

After that, mdelay() or udelay() can be called to delay execution for
the specified time (milliseconds or microseconds, respectively).

Change-Id: Icf8a295e1d25874f789bf28b7412156329dc975c
Co-authored-by: Dan Handley <dan.handley@arm.com>
2015-06-17 13:13:54 +01:00
Achin Gupta
79b1ebdaae Merge pull request #317 from vwadekar/run-bl32-on-tegra-v3
Run bl32 on tegra v3
2015-06-12 14:08:53 +01:00
Varun Wadekar
9a9645105b Reserve a Video Memory aperture in DRAM memory
This patch adds support to reserve a memory carveout region in the
DRAM on Tegra SoCs. The memory controller provides specific registers
to specify the aperture's base and size. This aperture can also be
changed dynamically in order to re-size the memory available for
DRM video playback. In case of the new aperture not overlapping
the previous one, the previous aperture has to be cleared before
setting up the new one. This means we do not "leak" any video data
to the NS world.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-06-12 17:40:31 +05:30
Varun Wadekar
c2dfe2e0d7 Move dispatcher documents to the docs/spd folder
This patch moves the optee-dispatcher.md and tlk-dispatcher.md to
docs/spd.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-06-11 14:48:10 +05:30
Varun Wadekar
dc7fdad251 Boot Trusted OS' on Tegra SoCs
This patch adds support to run a Trusted OS during boot time. The
previous stage bootloader passes the entry point information in
the 'bl32_ep_info' structure, which is passed over to the SPD.

The build system expects the dispatcher to be passed as an input
parameter using the 'SPD=<dispatcher>' option. The Tegra docs have
also been updated with this information.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-06-11 14:46:32 +05:30
danh-arm
056904cb4c Merge pull request #314 from sandrine-bailleux/sb/css-data-structs
Clarify some CSS data structures
2015-06-09 17:06:33 +01:00
danh-arm
5720b28072 Merge pull request #312 from jcastillo-arm/jc/tf-issues/308
Fix build option 'ARM_TSP_RAM_LOCATION' in user guide
2015-06-09 14:01:13 +01:00
Sandrine Bailleux
fe55612bdb CSS: Remove the constants MHU_SECURE_BASE/SIZE
For CSS based platforms, the constants MHU_SECURE_BASE and
MHU_SECURE_SIZE used to define the extents of the Trusted Mailboxes.
As such, they were misnamed because the mailboxes are completely
unrelated to the MHU hardware.

This patch removes the MHU_SECURE_BASE and MHU_SECURE_SIZE #defines.
The address of the Trusted Mailboxes is now relative to the base of
the Trusted SRAM.

This patch also introduces a new constant, SCP_COM_SHARED_MEM_BASE,
which is the address of the first memory region used for communication
between AP and SCP. This is used by the BOM and SCPI protocols.

Change-Id: Ib200f057b19816bf05e834d111271c3ea777291f
2015-06-09 13:03:45 +01:00
Sandrine Bailleux
9255da5f63 CSS: Clarify what the SCP boot config is
Add a comment explaining what the SCP boot configuration information
is on CSS based platforms like Juno. Also express its address
relatively to the base of the Trusted SRAM rather than hard-coding it.

Change-Id: I82cf708a284c8b8212933074ea8c37bdf48b403b
2015-06-09 11:49:34 +01:00
Juan Castillo
e5da24f700 Fix build option 'ARM_TSP_RAM_LOCATION' in user guide
The 'ARM_TSP_RAM_LOCATION_ID' option specified in the user guide
corresponds to the internal definition not visible to the final
user. The proper build option is 'ARM_TSP_RAM_LOCATION'. This
patch fixes it.

Fixes ARM-software/tf-issues#308

Change-Id: Ica8cb72c0c5e8b3503f60b5357d16698e869b1bd
2015-06-08 11:35:06 +01:00
danh-arm
789c220135 Merge pull request #309 from soby-mathew/sm/fix_fvp_get_entry
FVP: Correct the PSYSR_WK bit width in platform_get_entrypoint
2015-06-05 17:32:25 +01:00
Sandrine Bailleux
bf031bba2b Introduce PROGRAMMABLE_RESET_ADDRESS build option
This patch introduces a new platform build option, called
PROGRAMMABLE_RESET_ADDRESS, which tells whether the platform has
a programmable or fixed reset vector address.

If the reset vector address is fixed then the code relies on the
platform_get_entrypoint() mailbox mechanism to figure out where
it is supposed to jump. On the other hand, if it is programmable
then it is assumed that the platform code will program directly
the right address into the RVBAR register (instead of using the
mailbox redirection) so the mailbox is ignored in this case.

Change-Id: If59c3b11fb1f692976e1d8b96c7e2da0ebfba308
2015-06-04 11:38:58 +01:00
Sandrine Bailleux
52010cc779 Rationalize reset handling code
The attempt to run the CPU reset code as soon as possible after reset
results in highly complex conditional code relating to the
RESET_TO_BL31 option.

This patch relaxes this requirement a little. In the BL1, BL3-1 and
PSCI entrypoints code, the sequence of operations is now as follows:
 1) Detect whether it is a cold or warm boot;
 2) For cold boot, detect whether it is the primary or a secondary
    CPU. This is needed to handle multiple CPUs entering cold reset
    simultaneously;
 3) Run the CPU init code.

This patch also abstracts the EL3 registers initialisation done by
the BL1, BL3-1 and PSCI entrypoints into common code.

This improves code re-use and consolidates the code flows for
different types of systems.

NOTE: THE FUNCTION plat_secondary_cold_boot() IS NOW EXPECTED TO
NEVER RETURN. THIS PATCH FORCES PLATFORM PORTS THAT RELIED ON THE
FORMER RETRY LOOP AT THE CALL SITE TO MODIFY THEIR IMPLEMENTATION.
OTHERWISE, SECONDARY CPUS WILL PANIC.

Change-Id: If5ecd74d75bee700b1bd718d23d7556b8f863546
2015-06-04 11:38:54 +01:00
Sandrine Bailleux
452b7fa25e Remove FIRST_RESET_HANDLER_CALL build option
This patch removes the FIRST_RESET_HANDLER_CALL build flag and its
use in ARM development platforms. If a different reset handling
behavior is required between the first and subsequent invocations
of the reset handling code, this should be detected at runtime.

On Juno, the platform reset handler is now always compiled in.
This means it is now executed twice on the cold boot path, first in
BL1 then in BL3-1, and it has the same behavior in both cases. It is
also executed twice on the warm boot path, first in BL1 then in the
PSCI entrypoint code.

Also update the documentation to reflect this change.

NOTE: THIS PATCH MAY FORCE PLATFORM PORTS THAT USE THE
FIRST_RESET_HANDLER_CALL BUILD OPTION TO FIX THEIR RESET HANDLER.

Change-Id: Ie5c17dbbd0932f5fa3b446efc6e590798a5beae2
2015-06-04 10:44:26 +01:00
Soby Mathew
c8f0c3f76c FVP: Correct the PSYSR_WK bit width in platform_get_entrypoint
This patch fixes the incorrect bit width used to extract the wakeup
reason from PSYSR in platform_get_entrypoint() function. This defect
did not have any observed regression.

Change-Id: I42652dbffc99f5bf50cc86a5878f28d730720d9a
2015-06-03 14:43:14 +01:00
Achin Gupta
de975e85ff Merge pull request #305 from achingupta/ag/tf-issues#306
Ag/tf issues#306
2015-06-02 15:17:05 +01:00
Achin Gupta
dbc963e2bf Merge pull request #307 from soby-mathew/sm/css_bit_width_fix
CSS: Extract primary cpu id using the correct bit width
2015-06-02 11:18:18 +01:00
Achin Gupta
1081e9c800 Merge pull request #308 from vwadekar/tegra-soc-support-v4
Tegra soc support v4
2015-06-02 11:06:01 +01:00
Sandrine Bailleux
a669527505 Always enable CCI coherency in BL3-1
On ARM standard platforms, snoop and DVM requests used to be enabled
for the primary CPU's cluster only in the first EL3 bootloader.
In other words, if the platform reset into BL1 then CCI coherency
would be enabled by BL1 only, and not by BL3-1 again.

However, this doesn't cater for platforms that use BL3-1 along with
a non-TF ROM bootloader that doesn't enable snoop and DVM requests.
In this case, CCI coherency is never enabled.

This patch modifies the function bl31_early_platform_setup() on
ARM standard platforms so that it always enables snoop and DVM
requests regardless of whether earlier bootloader stages have
already done it. There is no harm in executing this code twice.

ARM Trusted Firmware Design document updated accordingly.

Change-Id: Idf1bdeb24d2e1947adfbb76a509f10beef224e1c
2015-06-01 10:03:32 +01:00
Varun Wadekar
08438e24e1 Support for NVIDIA's Tegra T210 SoCs
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given point in time.

This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
also adds support to boot secondary CPUs, enter/exit core power states for
all CPUs in the slow/fast clusters. The support to switch between clusters
is still not available in this patch and would be available later.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-05-29 16:43:25 +05:30
Varun Wadekar
c13b2e32f1 Driver for 16550 UART interface
This patch adds driver for the 16550 UART interface. The driver is exposed
as a console, which platforms can use to dump their boot/crash logs.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-05-29 11:25:20 +05:30
Soby Mathew
19af6fceaf CSS: Extract primary cpu id using the correct bit width
This patch fixes the incorrect bit width used to extract the primary
cpu id from `ap_data` exported by scp at SCP_BOOT_CFG_ADDR in
platform_is_primary_cpu().

Change-Id: I14abb361685f31164ecce0755fc1a145903b27aa
2015-05-27 10:08:55 +01:00
danh-arm
c163ec455b Merge pull request #303 from danh-arm/dh/fix-fvp-setup-topology
Fix return type of FVP plat_arm_topology_setup
2015-05-20 11:32:15 +01:00
Achin Gupta
ca0225a5dc Fix reporting of interrupt ID in ARM GIC driver
The ARM GIC driver treats the entire contents of the GICC_HPPIR as the interrupt
ID instead of just bits[9:0]. This could result in an SGI being treated as a
Group 1 interrupt on a GICv2 system.

This patch introduces a mask to retrieve only the ID from a read of GICC_HPPIR,
GICC_IAR and similar registers. The value read from these registers is masked
with this constant prior to use as an interrupt ID.

Fixes ARM-software/tf-issues#306

Change-Id: Ie3885157de33b71df9781a41f6ef015a30c4608d
2015-05-19 11:53:54 +01:00
Dan Handley
12ad4d887b Fix return type of FVP plat_arm_topology_setup
Fix the return type of the FVP `plat_arm_topology_setup` function
to be `void` instead of `int` to match the declaration in
`plat_arm.h`.

This does not result in any change in behavior.

Change-Id: I62edfa7652b83bd26cffb7d167153959b38e37e7
2015-05-19 10:04:54 +01:00
achingupta
57e56bba34 Merge pull request #301 from soby-mathew/sm/cpu_on_pend_state_fix
PSCI: Set ON_PENDING state early during CPU_ON
2015-05-18 18:32:38 +01:00
Achin Gupta
5717aae1c3 Fix handling of spurious interrupts in BL3_1
There are couple of issues with how the interrupt routing framework in BL3_1
handles spurious interrupts.

1. In the macro 'handle_interrupt_exception', if a spurious interrupt is
   detected by plat_ic_get_pending_interrupt_type(), then execution jumps to
   'interrupt_exit_\label'. This macro uses the el3_exit() function to return to
   the original exception level. el3_exit() attempts to restore the SPSR_EL3 and
   ELR_EL3 registers with values from the current CPU context. Since these
   registers were not saved in this code path, it programs stale values into
   these registers. This leads to unpredictable behaviour after the execution of
   the ERET instruction.

2. When an interrupt is routed to EL3, it could be de-asserted before the
   GICC_HPPIR is read in plat_ic_get_pending_interrupt_type(). There could be
   another interrupt pending at the same time e.g. a non-secure interrupt. Its
   type will be returned instead of the original interrupt. This would result in
   a call to get_interrupt_type_handler(). The firmware will panic if the
   handler for this type of interrupt has not been registered.

This patch fixes the first problem by saving SPSR_EL3 and ELR_EL3 early in the
'handle_interrupt_exception' macro, instead of only doing so once the validity
of the interrupt has been determined.

The second problem is fixed by returning execution back to the lower exception
level through the 'interrupt_exit_\label' label instead of treating it as an
error condition. The 'interrupt_error_\label' label has been removed since it is
no longer used.

Fixes ARM-software/tf-issues#305

Change-Id: I81c729a206d461084db501bb81b44dff435021e8
2015-05-13 18:58:58 +01:00
Soby Mathew
42cae5a166 PSCI: Set ON_PENDING state early during CPU_ON
In the debug build of the function get_power_on_target_afflvl(), there is a
check to ensure that the CPU is emerging from a SUSPEND or ON_PENDING state.
The state is checked without acquiring the lock for the CPU node. The state
could be updated to ON_PENDING in psci_afflvl_on() after the target CPU has
been powered up. This results in a race condition which could cause the
check for the ON_PENDING state in get_power_on_target_afflvl() to fail.
This patch resolves this race condition by setting the state of the target
CPU to ON_PENDING before the platform port attempts to power it on. The
target CPU is thus guaranteed to read the correct the state. In case
the power on operation fails, the state of the CPU is restored to OFF.

Fixes ARM-software/tf-issues#302

Change-Id: I3f2306a78c58d47b1a0fb7e33ab04f917a2d5044
2015-05-13 10:52:02 +01:00
danh-arm
aaa48a86b9 Merge pull request #297 from sandrine-bailleux/sb/move-up-deps
Move up dependency versions
2015-04-29 17:09:09 +01:00
danh-arm
28ef011c07 Merge pull request #296 from danh-arm/sb/scpi-min-changes
Move to the new ARM SCP Messaging Interfaces v2
2015-04-29 17:07:40 +01:00
danh-arm
4731e8f0f1 Merge pull request #295 from danh-arm/dh/plat-port-reorg
ARM platform port reorganization
2015-04-29 17:04:51 +01:00