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29,619 Commits 71 Branches 122 Tags 697 MiB
bc16a55028
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231 Commits

Author SHA1 Message Date
Unknown W. Brackets
bc16a55028 jit: Count delay slot cycles separately. 
This makes it easier to count cycles per instruction, instead of ignoring
the delay slot's instruction for cycle count.
 2021-04-12 07:04:22 -07:00
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cae0815095 jit: Avoid using mips identifier directly. 
Apparently this gets defined on mips systems.
 2021-02-26 07:24:58 -08:00
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f32f89dd90 Global: Remove some unused variables. 2021-02-15 11:59:45 -08:00
Unknown W. Brackets
5d60fa0d0d Common: Maintain C++11 support in sign extend. 2021-01-31 08:44:02 -08:00
Unknown W. Brackets
1b00da2f3a Common: Sign extend w/func not chained casts. 
Should be clearer to read and easier to get right.
 2021-01-31 01:25:52 -08:00
Unknown W. Brackets
e99c69f19e jit: Be very clear on sign extension. 2021-01-30 11:41:30 -08:00
Unknown W. Brackets
c179cad5c2 jit: Make branch shift more obvious. 
And also not technically undefined behavior.
 2021-01-29 20:53:41 -08:00
Unknown W. Brackets
5354459476 irjit: Update clobber flag on inst swap. 
Fixes IR in Persona 3.
 2021-01-10 16:41:45 -08:00
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9dcb70d502 irjit: Add disable flag for simplify passes. 2021-01-10 14:50:32 -08:00
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021f4adfad irjit: Fix mtv for INF4. 2021-01-09 12:43:50 -08:00
Unknown W. Brackets
670334bd0c irjit: Correct flags for SetCtrlVFPUReg. 
Fixes #13897.  Caused the reg to be optimized out.
 2021-01-09 12:33:08 -08:00
Unknown W. Brackets
d3c06266c5 jit: Fix conditional disable flags. 2021-01-09 11:50:32 -08:00
Henrik Rydgård
4c034ce988 Make all the Comp_Cache implementations the same. 
We have the informative comments in the interpreter implementation
anyway.
 2020-10-16 09:13:41 +02:00
Henrik Rydgård
821817e6d4 Move the profiler to Common 2020-10-04 11:42:16 +02:00
Henrik Rydgård
9e41fafd0d Move math and some file and data conversion files out from native to Common. 
Buildfixing

Move some file util files

Buildfix

Move KeyMap.cpp/h to Core where they belong better.

libretro buildfix attempt

Move ini_file

More buildfixes
 2020-10-04 09:12:46 +02:00
Henrik Rydgård
4d3ec20082 ByteSwap.h results in a file name collision on some systems with byteswap.h. Fix this by merging it into BitSet.h. 2020-09-30 00:09:13 +02:00
Henrik Rydgård
40ec0d8358 Finish getting rid of basictypes.h 2020-09-29 15:51:51 +02:00
Henrik Rydgård
3162f30158 Merge base/basictypes.h into Common/Common.h (mostly). 2020-09-29 15:51:51 +02:00
Unknown W. Brackets
53d9c10b22 irjit: Switch to XXH3. 2020-08-27 20:40:55 -07:00
Henrik Rydgård
b43698a13d Remove most instances of base/logging.h from Common, Core, GPU, more 2020-08-15 19:08:44 +02:00
Unknown W. Brackets
b8342fb8ec SaveState: Rename ChunkFile files to Serialize. 
Makes more sense and less weird than ChunkFileDoMap, etc.
 2020-08-10 08:04:05 +00:00
Unknown W. Brackets
1dc5ee424b SaveState: Split out Do types to reduce headers. 2020-08-10 08:03:44 +00:00
Unknown W. Brackets
4b4e3432cd SaveState: Split Do() into a separate header. 2020-08-10 08:03:41 +00:00
Henrik Rydgård
c5e0b799d9 Remove category from _assert_msg_ functions. We don't filter these by category anyway. 
Fixes the inconsistency where we _assert_ didn't take a category but
_assert_msg_ did.
 2020-07-19 20:33:25 +02:00
Henrik Rydgard
c988d42b04 ARM/ARM64 instruction analysis, hook up to handler 2020-07-14 09:25:45 +02:00
Unknown W. Brackets
3c34c7c456 irjit: Add jump crash checks. 
Doesn't seem to have any significant impact on performance.
 2020-07-12 22:17:36 -07:00
Henrik Rydgård
8461ea19b1 Centralize handling of memory exceptions a bit 2020-07-12 15:25:20 +02:00
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5afc020fbd x86jit: Force INF * 0 to +NAN. 
See #12519 - this is needed for some graphics to render properly.  Seems
to already happen on ARM, so no change to armjit.
 2020-04-06 06:33:39 -07:00
Henrik Rydgård
f65a71d6d8 Compat: Option to use accurate dotprod for VMMUL. 
Eliminates Tekken 6 leg shaking.
 2019-08-05 11:44:52 -07:00
Henrik Rydgård
30831f3ea1 Implement and test clz32, use it in the MIPS interpreter cores. 
This will be useful for our vfpu-dot implementations later.
 2019-06-14 18:39:15 +02:00
Henrik Rydgård
7853c90abb JIT: Split VFPU_MTX disable options. To help with #9843 2019-06-03 23:28:15 +02:00
Unknown W. Brackets
c773359095 arm64jit: Tweak matrix vfpu overlap detect, etc. 
Tried making changes to them to guess at issues for #9843, but didn't find
any.  Still, I think these changes are worthwhile, if small.
 2019-06-02 22:10:20 -07:00
Henrik Rydgård
2f26297062 Clean up some more ifdefs 2019-05-10 23:25:57 +02:00
driver1998
5072584781 Fix neon headers for MSVC ARM64 
MSVC uses arm64_neon.h for ARM64, arm_neon.h is ARM32 only.
 2019-05-04 22:45:15 +08:00
Unknown W. Brackets
ec7cffa847 interp: Handle vtfm/vhtfm prefixes properly. 2019-04-02 18:46:39 -07:00
Unknown W. Brackets
5414c12a15 interp: Cleanup prefix/size in vcrsp/vqmul. 2019-04-02 07:12:34 -07:00
Henrik Rydgård
b346142df8
Merge pull request #11954 from unknownbrackets/vfpu-chunk5 
Fix prefix and size handling for vsbx, vsocp, and integer conv ops
 2019-04-01 17:12:03 +02:00
Unknown W. Brackets
b24f84d1a2 interp: Handle prefixes on matrix init ops. 2019-03-31 17:11:24 -07:00
Unknown W. Brackets
59905de719 interp: Correct vsgn out of swizzle bounds. 2019-03-31 17:10:51 -07:00
Unknown W. Brackets
b881a689c4 interp: Ignore high bit in vmfvc/vmtvc. 
Both 0 and 128 read/write the S prefix, for example.
 2019-03-31 17:09:55 -07:00
Unknown W. Brackets
175ceef583 interp: Cleanup vsocp size handling. 2019-03-31 13:52:07 -07:00
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4a2f8a74dc interp: Correct size handling for vi2x ops. 2019-03-31 13:51:12 -07:00
Unknown W. Brackets
b75690787e interp: Correct swizzle on vx2i ops. 2019-03-31 13:51:12 -07:00
Unknown W. Brackets
68cdcba6c5 interp: Don't write lane 2 on single colorconv. 
Not that it's valid to use the op with that size anyway.
 2019-03-31 13:51:12 -07:00
Unknown W. Brackets
5749ae09d0 interp: Correct vmfvc register behavior. 
The target and source registers were completely wrong.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets
b2e024025f interp: Handle wrong sizes of vf2h/vh2f. 
Probably not ever used, but they have consistent behavior.
 2019-03-31 13:41:48 -07:00
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af3ed69144 interp: Mask moves to vfpu ctrl. 
These bits of the registers can't be written.
 2019-03-31 10:37:07 -07:00
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d40ac043d4 interp: Handle prefixes for Vmmov/Vmmul/Vmscl. 
I doubt any actual code uses this, but we have some tricky VFPU bugs left,
so just trying for maximum accuracy in the interpreter.
 2019-03-31 10:37:07 -07:00
Unknown W. Brackets
ec1dae57eb interp: Fix vbfy prefix handling. 2019-03-31 10:09:18 -07:00
Unknown W. Brackets
d5273f589a interp: Mask value in vpfxd. 
The actual register ends up with only the lower 12 bits, which makes sense
since those are the only ones that do anything.
 2019-03-31 08:23:36 -07:00