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36,359 Commits 73 Branches 122 Tags 710 MiB
f390c3a6ee
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2343 Commits

Author SHA1 Message Date
Henrik Rydgård
f390c3a6ee
Merge pull request #17244 from unknownbrackets/debugger-memcheck 
Debugger: Trigger mem breakpoints for mirrors
 2023-04-06 07:56:56 +02:00
Unknown W. Brackets
6df939034a Core: Cleanup some sign extensions for clarity. 2023-04-05 17:16:51 -07:00
Unknown W. Brackets
142707ccf3 x86jit: Reduce memory breakpoint codegen. 
Was generating a lot of code and, in some games, burning through the jit
cache causing constant recompilation with just a few breakpoints.
 2023-04-05 17:14:51 -07:00
Henrik Rydgård
ff907bd523 Fix crash in MIPSStackWalk 2023-04-05 09:48:03 +02:00
Henrik Rydgård
aba026f7e9 Add back our older VFPU approximations, as fallbacks if files are missing. 
PR #16984 added more accurate versions of these functions, but they require
large lookup tables stored in assets/.

If these files are missing, PPSSPP would simply crash, which isn't good.

We should probably try to warn the user somehow that these files are
missing, though...
 2023-04-03 11:33:41 +02:00
Henrik Rydgård
d996fb74d4 MSVC: Set language standard to c++17. 
Noticed that we were getting some new warnings after merging the
constexpr stuff.
 2023-04-02 17:55:15 +02:00
Henrik Rydgård
fc62d587c0 Fix whitespace issues 2023-04-02 16:36:39 +02:00
Герман Семенов
8d5af48efd Core: using if constexpr C++17 optimization 2023-04-02 16:35:57 +02:00
Henrik Rydgård
2814668cf5
Show a MIPS stack trace on crash screen (#17211) 
* Print simple stack traces to log on crashes.

* Display stack traces on crash screen

* Show the in-function offset in the printed callstacks.

* Libretro buildfix attempt
 2023-03-31 10:08:12 +02:00
Henrik Rydgård
98d9a9c8ca
Merge pull request #16984 from fp64/vfpu-sincos 
VFPU sin/cos
 2023-03-28 16:36:51 +02:00
Henrik Rydgård
d586ec0d5e Don't create Host objects except in headless/unittest 2023-03-25 10:47:01 +01:00
Unknown W. Brackets
d97790e28e irjit: Fix vi2us/vi2s with non-consecutive. 
Vec2ClampToZero and similar assume consecutive.
 2023-03-15 21:30:35 -07:00
fp64
38fc21a2c0 Implement load-on-demand of vfpu tables 2023-03-12 08:21:15 -04:00
fp64
d3be0ee654 Fix tabs vs spaces, tweak comments, error on BE 2023-03-12 08:21:15 -04:00
fp64
67bb17eba3 Add more vfpu_*, move tables to assets 2023-03-12 08:21:15 -04:00
fp64
ee98603fe7 Fix the sign of cos(2*n+1) 
Also fix the license text.
 2023-03-12 08:21:14 -04:00
fp64
3661bb27ce Implement sin/cos as per #16946 2023-03-12 08:21:13 -04:00
Henrik Rydgård
718cb9ee4a Reorder savestates to put memory before CoreTiming. 
Also, don't clear the JIT for rounding after saving, only after loading.
 2023-02-14 16:43:22 +01:00
Unknown W. Brackets
89c18d8077 riscv: Cleanup missing Poison, Crash. 2023-02-12 12:10:29 -08:00
Henrik Rydgård
9e736ca50c Workaround for sin/cos issue in GTA on Mac (and maybe others) 2023-02-07 17:43:12 +01:00
Henrik Rydgård
6dc930feb7
Merge pull request #16796 from unknownbrackets/icache-typo 
jit: Fix reporting of icache invalidate near PC
 2023-01-12 07:30:24 +01:00
Unknown W. Brackets
8341b09087 jit: Fix reporting of icache invalidate near PC. 
Reversed the check, that's what I get for not testing it.
 2023-01-11 20:22:09 -08:00
Henrik Rydgård
e1a48d74c4 A bit more GetPointer cleanup. 
Probably not worth it for performance reasons, but some semantic cleanup
is good, especially the accidental GetPointer -> writable casts without
using GetPointerWrite.

Using Unchecked on already checked pointers, or when we'd crash anyway
if it returned nullptr, is good for clarity.
 2023-01-10 12:13:47 +01:00
Unknown W. Brackets
dea9cac16c Core: Add range checks to some helpers and similar. 2023-01-09 16:56:18 -08:00
Unknown W. Brackets
1f66c1d689 jit: Also report invalidation near PC. 2023-01-06 19:51:43 -08:00
Unknown W. Brackets
b073d3e207 jit: Report unaligned icache invalidations. 
And over invalidate them a bit.
 2023-01-06 19:46:43 -08:00
Unknown W. Brackets
fb13dbf169 riscv: Correct type warning, oops. 2023-01-04 21:42:22 -08:00
Henrik Rydgård
14bd411036 Round addr to nearest cacheline when invalidating 2023-01-04 11:40:53 +01:00
Henrik Rydgård
830f1064e6
Merge pull request #16676 from unknownbrackets/riscv-disasm 
Add disassembler for RISC-V
 2023-01-04 09:52:56 +01:00
Henrik Rydgård
700a018ef0 IRInterpreter: Use alignment as access size in exceptions 2023-01-01 20:48:16 +01:00
Henrik Rydgård
aa80659530 Memory exception: Add facility to track size 
Might theoretically help in tracking some things down.

Not fully utilized yet, the fault handler needs to extract the
information from the faulting instruction. But we can use it for
GetPointerRange etc.
 2023-01-01 20:30:29 +01:00
Unknown W. Brackets
cee8bfd5cf riscv: Avoid a jit warning. 
We'll end up doing the same as arm64, most likely.
 2023-01-01 10:28:54 -08:00
Unknown W. Brackets
77849d3eed riscv: Add disassembler. 
From https://github.com/anthony-coulter/riscv-disassembler.
Modified slightly to pull in less headers in the h, prefix funcs.
 2023-01-01 10:28:53 -08:00
Unknown W. Brackets
808f47fd15 Core: Prevent crash if FakeJit is actually used. 
Just make it fall back to the interpreter.
 2022-12-24 17:42:50 +00:00
Unknown W. Brackets
b9fe48f42d Crash: Lookup block numbers more efficiently. 
We only care about the first one in these places anyway.  Also make sure
we don't try to match an invalid block number.
 2022-12-20 21:02:52 -08:00
Unknown W. Brackets
21332c677b Build: Allow compiling without armips. 2022-12-17 10:08:46 -08:00
Henrik Rydgård
e48a1599d4 Delete a few obsolete lines of code 2022-12-11 10:01:55 +01:00
Unknown W. Brackets
9cfcbc46e6 Global: Cleanup initialization/pointer checks. 
Cleaning up a lot of cases of uninitialized data, unchecked return values
for failures, and similar.
 2022-12-10 21:13:36 -08:00
Unknown W. Brackets
a7b7bf7826 Global: Set many read-only params as const. 
This makes what they do and which args to use clearer, if nothing else.
 2022-12-10 21:13:36 -08:00
Unknown W. Brackets
f44852bb18 Global: Cleanup virtual/override specifiers. 
Also missing virtual destructors, hidden non-overrides, etc.
 2022-12-10 21:13:36 -08:00
Henrik Rydgård
250ea5e592
Merge pull request #16407 from unknownbrackets/jit-wx 
In jits, protect and unprotect using better estimates
 2022-11-20 20:39:04 +01:00
Unknown W. Brackets
b2798c7ada jit: Add more reasonable estimates for RX protect. 2022-11-20 10:55:35 -08:00
Henrik Rydgård
15e66080df
Merge pull request #16396 from unknownbrackets/ir-vneg 
Correct misbehavior on uninitialized values in IR
 2022-11-19 06:59:29 +01:00
Unknown W. Brackets
c085413326 irjit: Consistently check vec4 safety. 
Just to prevent confusion/surprises, this is clearer.
 2022-11-18 19:06:50 -08:00
Unknown W. Brackets
ada0674415 irjit: Allow VV2Op SIMD with exact overlap. 
None of these look at other lanes.
 2022-11-18 17:54:58 -08:00
Unknown W. Brackets
2419e5680a irjit: Correct VV2Op SIMD check. 
It's unlikely, but possible, uninitialized data could cause
IsConsecutive4() to return true when n < 4.
 2022-11-18 17:53:53 -08:00
Unknown W. Brackets
0f79afa172 interp: Support memory breakpoints too. 2022-11-13 17:45:43 -08:00
Unknown W. Brackets
f9da9e6b60 interp: Centralize memory size handling. 2022-11-13 17:38:53 -08:00
Unknown W. Brackets
76cf4dbf12 interp: Allow breakpoints in release mode. 2022-11-13 16:52:40 -08:00
Unknown W. Brackets
1662bd3bb8 interp: Allow resume from breakpoint. 2022-11-13 16:03:29 -08:00