FEX-Emu/FEX
1
0
Fork 0
mirror of https://github.com/FEX-Emu/FEX.git synced 2025-01-05 13:00:34 +00:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity
9,126 Commits 4 Branches 47 Tags 47 MiB
f0dad86332
Commit Graph

9126 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Ryan Houdek
f0dad86332
Merge pull request #3559 from bylaws/ec-pt5 
LookupCache: Track ARM64EC page state in the code cache
 2024-04-09 07:08:29 -07:00
Mai
eedb120fd0
Merge pull request #3563 from Sonicadvance1/fill_spill_pairs 
JIT: Adds support for spilling/Filling GPRPair
 2024-04-08 23:05:11 -04:00
Ryan Houdek
1616b4e77c
Merge pull request #3564 from lioncash/header 
DebugData: Remove header
 2024-04-08 14:33:42 -07:00
Lioncache
b26bf2eaf6 DebugData: Remove header 
This isn't included or used anywhere, so it can be removed.
 2024-04-08 16:05:40 -04:00
Ryan Houdek
e91e1d5533
Merge pull request #3550 from alyssarosenzweig/ra/validate 
Validate that we have no crossblock liveness
 2024-04-08 12:07:23 -07:00
Ryan Houdek
574fdcef32
JIT: Adds support for spilling/Filling GPRPair 
Tony noticed this last week. I encountered it this week.
Add support for spilling and filling GPR pairs.
 2024-04-08 11:55:29 -07:00
Alyssa Rosenzweig
063954c9b3 ValueDominanceValidation: rm deadcode 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:49:35 -04:00
Alyssa Rosenzweig
7b3e031678 ValueDominanceValidation: forbid crossblock liveness 
Now that we have successfully eliminated crossblock liveness from the IR we
generate, validate as much to ensure it doesn't come back. We will take
advantage of this new invariant in RA in the future.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:49:35 -04:00
Alyssa Rosenzweig
a775e474d5 ValueDominanceValidation: do not validate inline constants 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:49:35 -04:00
Alyssa Rosenzweig
0e99019586 ValueDominanceValidation: actually validate 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:49:35 -04:00
Alyssa Rosenzweig
d0ff3e64d9 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:49:31 -04:00
Alyssa Rosenzweig
d9493e5d9b OpcodeDispatcher: fix xblock liveness in xsave/xrstr 
didn't fix this hard enough before. caught by validation.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:48:29 -04:00
Alyssa Rosenzweig
eb83c9e7f2 Core: use safe CondJump for self-modifying code 
this ensures we put the StoreNZCV in the right block, which will fix validation
fails later in the series.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-08 13:48:29 -04:00
Ryan Houdek
bb24e1419c
Merge pull request #3558 from bylaws/ec-pt3 
AllocatorHooks: Mark JIT code memory as EC code on ARM64EC
 2024-04-08 09:32:51 -07:00
Ryan Houdek
cbfa426b59
Merge pull request #3548 from alyssarosenzweig/ra/shifts-rework 
Eliminate xblock liveness for shifts
 2024-04-08 09:31:49 -07:00
Billy Laws
526e3e654f LookupCache: Track ARM64EC page state in the code cache 
Rather than checking the actual EC bitmap in the dispatcher (~6 instrs), this
indirection through the code cache allows just 1 instr for the hot path
of calling repeated EC code/x64 code.
 2024-04-08 16:08:17 +01:00
Billy Laws
bd5b817c3a AllocatorHooks: Mark JIT code memory as EC code on ARM64EC 
Executable mapped memory is treated as x86 code by default when
running under EC, VirtualAlloc2 needs to be used together with a
special flag to map JIT arm64 code.
 2024-04-06 12:40:52 +00:00
Alyssa Rosenzweig
b54d4931fb InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
95589f6172 OpcodeDispatcher: rm deferred variable shift flag calcs 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
098859caf7 OpcodeDispatcher: use _ShiftFlags for ASHR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
c632543451 OpcodeDispatcher: use _ShiftFlags for SHRD 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
801cf72f95 OpcodeDispatcher: use _ShiftFlags for SHLD 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
650cd2c46e OpcodeDispatcher: use _ShiftFlags for SHR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
5b48ce2228 OpcodeDispatcher: use _ShiftFlags for SHL 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
2173c26fd8 OpcodeDispatcher: add HandleShift helper 
all the variable shift impls need to do this dance, make it common.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
982391ba9d IR: add ShiftFlags op 
Generates flags for a variable shift as a dedicated IR op. This lets us optimize
around it (without generating control flow, relying on deferred flag infra,
etc). And it neatly solves our RA problem for shifts.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
a99c48b7a3 RedundantFlagCalculationElimination: do not eliminate if there are uses 
we'll hit this with _ShiftFlags.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
90d5bd3aec unittests: add test for shift PF bug 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
59c3f96a23 unittests: add test for deferred flags + shift with cl=0 
this failed on an earlier version of the series that otherwise passed ci.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
3661da1bc6 OpcodeDispatcher: calculate deferred flags before RMW on NZCV 
otherwise we might have the wrong input NZCV.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 20:34:05 -04:00
Alyssa Rosenzweig
859df5e0b2 OpcodeDispatcher: optimize shl flag 
This is something the new shift flag code will do. Backporting the opt since
that's stalled and this reduces the diff.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-05 19:38:44 -04:00
Ryan Houdek
e8127b92e8
Docs: Update for release FEX-2404 2024-04-05 15:20:24 -07:00
Ryan Houdek
7786c23405
Merge pull request #3556 from Sonicadvance1/move_app_config 
FEXCore: Fixes priority of FEX_APP_CONFIG
 2024-04-05 15:18:24 -07:00
Ryan Houdek
904646e93b
FEXCore: Fixes priority of FEX_APP_CONFIG 
This environment variable had an incorrect priority on the configuration
system. The expectation was higher priority than most other layers.

Now the only layer that has higher priority is the environment
variables.
 2024-04-05 13:10:43 -07:00
Alyssa Rosenzweig
c43af8e975
Merge pull request #3553 from alyssarosenzweig/ra/shifts-rework-easy 
OpcodeDispatcher: clean up shifts
 2024-04-05 11:36:33 -04:00
Alyssa Rosenzweig
a787daae41 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:27 -04:00
Alyssa Rosenzweig
a05cc06ab4 OpcodeDispatcher: unify imm/1-bit ASHR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
031e756a78 OpcodeDispatcher: unify imm/1-bit SHR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
2a9f1ce8cb OpcodeDispatcher: unify imm/1-bit SHL 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
8c53a9f051 OpcodeDispatcher: use LoadConstantShift for rotates 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
cf26ec7898 OpcodeDispatcher: use LoadConstantShift for SHRD 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
582c3dae6e OpcodeDispatcher: use LoadConstantShift for SHLD 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
2abac03ab0 OpcodeDispatcher: add LoadConstantShift helper 
shows up a bunch

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
8cc684fa12 OpcodeDispatcher: drop misinformed comment 
tbnz only tests a single bit, not a mask.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
d92de1d947 OpcodeDispatcher: drop result masking for shifts 
flag calcs are fine with upper garbage.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-04 07:42:15 -04:00
Alyssa Rosenzweig
202a60b77a
Merge pull request #3549 from alyssarosenzweig/constprop/dce 
ConstProp: drop dead code
 2024-04-03 11:22:30 -04:00
Alyssa Rosenzweig
aa8d04c341
Merge pull request #3551 from alyssarosenzweig/opt/negate-adds 
Negate more to inline constants
 2024-04-03 11:22:01 -04:00
Alyssa Rosenzweig
d6425d05f3 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:57:06 -04:00
Alyssa Rosenzweig
e07c81a5e7 ConstProp: also negate sub -> add 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:56:59 -04:00
Alyssa Rosenzweig
fa76961873 ConstProp: negate adds -> subs 
the arm ops are equiv, even though the x86 isn't (due to inverted carry).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-04-02 13:53:21 -04:00