2014-04-29 03:21:04 +00:00
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/* Capstone Disassembly Engine */
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2015-03-04 09:45:23 +00:00
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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2013-11-27 04:11:31 +00:00
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2014-01-02 05:15:07 +00:00
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#ifndef CS_PRIV_H
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#define CS_PRIV_H
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2013-11-27 04:11:31 +00:00
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2015-02-24 03:55:55 +00:00
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#include <capstone/capstone.h>
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2013-11-27 04:11:31 +00:00
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#include "MCInst.h"
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#include "SStream.h"
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typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info);
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// function to be called after Printer_t
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// this is the best time to gather insn's characteristics
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2014-05-19 08:46:31 +00:00
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typedef void (*PostPrinter_t)(csh handle, cs_insn *, char *mnem, MCInst *mci);
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2013-11-27 04:11:31 +00:00
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2014-05-07 00:25:24 +00:00
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typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
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2013-11-27 04:11:31 +00:00
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2014-07-08 00:59:27 +00:00
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typedef const char *(*GetName_t)(csh handle, unsigned int id);
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2013-11-27 04:11:31 +00:00
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2014-01-06 02:56:59 +00:00
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typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
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2013-11-27 04:11:31 +00:00
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2014-03-10 16:18:50 +00:00
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// return register name, given register ID
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2017-10-22 00:45:40 +00:00
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typedef const char *(*GetRegisterName_t)(unsigned RegNo);
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2014-03-10 16:18:50 +00:00
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2015-03-25 07:02:13 +00:00
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// return registers accessed by instruction
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typedef void (*GetRegisterAccess_t)(const cs_insn *insn,
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cs_regs regs_read, uint8_t *regs_read_count,
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cs_regs regs_write, uint8_t *regs_write_count);
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2013-12-02 05:16:44 +00:00
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// for ARM only
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typedef struct ARM_ITStatus {
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2015-06-03 14:25:22 +00:00
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unsigned char ITStates[8];
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2013-12-02 05:16:44 +00:00
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unsigned int size;
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} ARM_ITStatus;
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2015-04-26 14:54:41 +00:00
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// Customize mnemonic for instructions with alternative name.
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struct customized_mnem {
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// ID of instruction to be customized.
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unsigned int id;
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// Customized instruction mnemonic.
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2015-04-27 01:47:59 +00:00
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char mnemonic[CS_MNEMONIC_SIZE];
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2015-04-26 14:54:41 +00:00
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};
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struct insn_mnem {
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struct customized_mnem insn;
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struct insn_mnem *next; // linked list of customized mnemonics
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};
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2013-12-29 16:15:25 +00:00
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struct cs_struct {
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2013-11-27 04:11:31 +00:00
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cs_arch arch;
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cs_mode mode;
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Printer_t printer; // asm printer
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void *printer_info; // aux info for printer
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Disasm_t disasm; // disassembler
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void *getinsn_info; // auxiliary info for printer
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GetName_t reg_name;
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GetName_t insn_name;
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2014-07-08 00:59:27 +00:00
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GetName_t group_name;
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2013-11-27 04:11:31 +00:00
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GetID_t insn_id;
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PostPrinter_t post_printer;
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2013-11-27 07:24:47 +00:00
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cs_err errnum;
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2013-12-02 05:16:44 +00:00
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ARM_ITStatus ITBlock; // for Arm only
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2016-03-14 05:52:23 +00:00
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cs_opt_value detail, imm_unsigned;
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2014-03-10 16:18:50 +00:00
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int syntax; // asm syntax for simple printer such as ARM, Mips & PPC
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2013-12-31 14:40:04 +00:00
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bool doing_mem; // handling memory operand in InstPrinter code
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2014-01-06 02:56:59 +00:00
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unsigned short *insn_cache; // index caching for mapping.c
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2014-03-10 16:18:50 +00:00
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GetRegisterName_t get_regname;
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2014-04-09 15:49:30 +00:00
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bool skipdata; // set this to True if we skip data when disassembling
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uint8_t skipdata_size; // how many bytes to skip
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cs_opt_skipdata skipdata_setup; // user-defined skipdata setup
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2017-10-22 00:45:40 +00:00
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const uint8_t *regsize_map; // map to register size (x86-only for now)
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2015-03-25 07:02:13 +00:00
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GetRegisterAccess_t reg_access;
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2015-04-26 14:54:41 +00:00
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struct insn_mnem *mnem_list; // linked list of customized instruction mnemonic
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2013-12-29 16:15:25 +00:00
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};
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2013-11-27 04:11:31 +00:00
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M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 13:44:36 +00:00
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#define MAX_ARCH CS_ARCH_MAX
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2013-12-21 04:16:47 +00:00
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2017-10-20 15:33:24 +00:00
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// Returns a bool (0 or 1) whether big endian is enabled for a mode
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#define MODE_IS_BIG_ENDIAN(mode) (((mode) & CS_MODE_BIG_ENDIAN) != 0)
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2014-01-11 04:55:31 +00:00
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extern cs_malloc_t cs_mem_malloc;
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extern cs_calloc_t cs_mem_calloc;
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extern cs_realloc_t cs_mem_realloc;
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extern cs_free_t cs_mem_free;
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2014-01-15 12:44:03 +00:00
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extern cs_vsnprintf_t cs_vsnprintf;
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2014-01-05 03:35:47 +00:00
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2013-11-27 04:11:31 +00:00
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#endif
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