* Add AArch64 linux build again.
* Enable package build also for PRs and pushes.
* Fix: don't append python version to injected platform name.
* Add musllinux build to wheel checking script
* Trigger wheel upload only on published full-releases.
* Remove duplicate workflow file
* Ensure all artifacts are moved to the same directory 'dist'
* Enable verbose twine upload.
* Add step to show downloaded artifacts for debugging.
Disassembling the "slwi", "srwi" and "rldicr" PowerPC instructions
with the "-d" option displays the wrong operands in the detailed
view. This is due to an incorrect break condition in the
"PPC_insert_detail_op_imm_at" function.
This patch fixes#2401.
* resolve conflict for loongarch and RISCV in Mapping.c and Mapping.h
* Use RISCV_get_detail for simplicity
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
* Use detail_is_set for simplicity
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
* Change comment style
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
* remove redundant add_str
* fix bug for RISCV_add_detail
* fix operands for csr instructions
* add python binding and tester for RISC-V
* add more test cases for RISC-V (M,A,F,D,C instructions)
* fix incorrect operand and access for sc.w and sc.d
* fix incorrect operand for fence and sfence.vma
* assert -> CS_ASSERT
* some instructions in test_riscv.c should be RISCV64
* add cs details test
* update python testers
---------
Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com>
* Run clang-format
* Remove arm.h header from AArch64 files
* Update all AArch64 module files to LLVM-18.
* Add check if the differs save file is up-to-date with the current files.
* Add new generator for MC test trnaslation.
* Fix warnings
* Update generated AsmWriter files
* Remove unused variable
* Change MCPhysReg type to int16_t as LLVM 18 dictates.
With LLVM 18 the MCPhysReg value's type is changed to int16_t.
If we update modules to LLVM 18, they will generate
compiler warnings that uint16_t* should not be casted to int16_t*.
This makes changing the all tables to int16_t necessary, because the alternative is
to duplicate all MCPhysReg related code. Which is even worse.
* Assign enum values to raw_struct member
* Add printAdrAdrpLabel def
* Add header to regression test files.
* Write files to build dir and ignore more parsing errors.
* Fix parsing of MC test files.
* Reset parser after every block
* Add write and patch header step.
* Add and update MC tests for AArch64
* Fix clang-tidy warnings
* Don't warn about padding issues.
They break automatically initialized structs we can not change easily.
* Fix: Incorrect access of LLVM instruction descriptions.
* Initialize DecoderComplete flag
* Add more mapping and flag details
* Add function to get MCInstDesc from table
* Fix incorrect memory operand access types.
* Fix test where memory was not written, ut only read.
* Attempt to fix Windows build
* Fix 2268
The enum values were different and hence lead to different decoding.
* Refactor SME operands.
- Splits SME operands in Matrix and Predicate operands.
- Fixes general problems of incorrect detections with
the vector select/index operands of predicate registers.
- Simplifies code.
* Fix up typo in WRITE
* Print actual path to struct fields
* Add Registers of SME operands to the reg-read list
* Add tests for SME operands.
* Use Capstone reg enum for comparison
* Fix tests: 'Vector arra...' to 'operands[x].vas'
* Add the developer fuzz option.
* Fix Python bindings for SME operands
* Fix variable shadowing.
* Fix clang-tidy warnings
* Add missing break.
* Fix varg usage
* Brackets for case
* Handle AArch64_OP_GROUP_AdrAdrpLabel
* Fix endian issue with fuzzing start bytes
* Move previous sme.pred to it's own operand type.
* Fix calculation for imm ranges
* Print list member flag
* Fix up operand strings for cstest
* Do only a shallow clone of the cmocka stable branch
* Fix: Don't categorize ZT0 as a SME matrix operand.
* Remove unused code.
* Add flag to distinguish Vn and Qn registers.
* Add all registers to detail struct, even if emitted in the asm text
* Fix: Increment op count after each list member is added.
* Remove implicit write to NZCV for MSR Imm instructions.
* Handle several alias operands.
* Add details for zero alias with za0.h
* Add SME tile to write list if written
* Add write access flags to operands which are zeroed.
* Add SME tests of #2285
* Fix tests with latest syntax changes.
* Fix segfault if memory operand is only a label without register.
* Fix python bindings
* Attempt to fix clang-tidy warning for some configurations.
* Add missing test file (accidentially blocked by gitignore.)
* Print clang-tidy version before linting.
* Update differ save file
* Formatting
* Use clang-tidy-15 as if possible.
* Remove search patterns for MC tests, since they need to be reworked anyways.
* Enum to upper case change
* Add information to read the OSS fuzz result.
* Fix special case of SVE2 operands.
Apparently ZT0 registers can an index attached,
get which is BOUND to it. We have no "index for reg" field.
So it is simply saved as an immediate.
* Handle LLVM expressions without asserts.
* Ensure choices are always saved.
* OP_GROUP enums can't be all upper case because they contain type information.
* Fix compatibility header patching
* Update saved_choices.json
* Allow mode == None in test_corpus
* Initial auto-sync LoongArch support
- Accompanied llvm changes: https://github.com/capstone-engine/llvm-capstone/pull/45
- MC Tests are generated from llvm
- Instruction groups are implemented
- Register accesses are implemented
- Memory operands are handled for memory instructions
- Code are formatted using clang-format of LLVM 17
- Import tests from LLVM MC
- Collect operand type and access
- Collect registers read/modified
---------
Co-authored-by: CoA <1109673069@qq.com>
* Ensure same indent for all patched lines.
* Emit upper case OP_GROUP enum
* Spell all enum values in capital letters.
* Capticalize enums in loongarch_detail.c
* Add test which contains now a tab.
* Run clang-format on test_loongarch.c
---------
Co-authored-by: CoA <1109673069@qq.com>
Co-authored-by: Rot127 <unisono@quyllur.org>
