4191 Commits

Author SHA1 Message Date
Nguyen Anh Quynh
0113195d49 arm: delete unused ARMRegisterName.inc 2019-03-16 18:05:30 +08:00
Nguyen Anh Quynh
ad3264e9c2 arm: use ARMMappingInsnName.inc for instruction names 2019-03-16 18:03:11 +08:00
Nguyen Anh Quynh
e48ebc18b1 cstest: temporarily disable issue 913 2019-03-16 17:11:39 +08:00
Nguyen Anh Quynh
5417858895 MC: fix heading of fpv8.c.cs to make fuzzer happy 2019-03-16 15:42:21 +08:00
Nguyen Anh Quynh
58750a1b71 arm: fix more MSVC warnings 2019-03-16 15:40:38 +08:00
Nguyen Anh Quynh
41f24e31af arm: fix more MSVC warnings 2019-03-16 15:32:14 +08:00
Nguyen Anh Quynh
b540ece988 arm: fix warnings reported by MSVC 2019-03-16 15:29:25 +08:00
Nguyen Anh Quynh
af891f125a bindings: update ARM const after the last ARM update 2019-03-16 15:22:45 +08:00
Nguyen Anh Quynh
eb4dcfb214 arm: sync with llvm 7.0.1 2019-03-16 15:22:15 +08:00
Nguyen Anh Quynh
3b3f40fec5 cstool: add armv8be & thumbv8be modes 2019-03-15 20:16:45 +08:00
Nguyen Anh Quynh
9a8b23892a cstool: arm v8, thumb v8 2019-03-15 13:01:04 +08:00
Nguyen Anh Quynh
5ab5ed249a cstool: add armv8 & thumbv8 to usage instruction 2019-03-15 12:57:31 +08:00
Catena cyber
cb2940ccf6 Fix memory leak in RISC V (#1424) 2019-03-15 12:31:17 +08:00
ceeac
b5964c1bfc Fix #1420: Capstone 4 fails to build when targeting UWP (#1421) 2019-03-14 23:27:55 +08:00
Catena cyber
f1618c78ce Corpus generation is more robust (#1419) 2019-03-11 13:12:54 +08:00
Nguyen Anh Quynh
76550a7bfd put together all static architecture setups in cs.c 2019-03-09 18:24:57 +08:00
Nguyen Anh Quynh
ed96912a46 cleanup tests/ 2019-03-09 08:51:30 +08:00
Nguyen Anh Quynh
34d92258e0 riscv: coding style cleanup 2019-03-09 08:47:11 +08:00
z
b8fcf27b22 RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h

* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction

* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h

* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter

* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h

* Backport it from: 0db412ce3b

* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.

* Add refactored cs.c for RISCV

* Testing all I instructions in test_riscv.c

* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture

* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c

* fixed bug related to incorrect initialization of memory after malloc

* fix compile bug

* Fix compile errors.

* move riscv.h to include/capstone

* fix indentation issues

* fix coding style issues

* Fix indentation issues

* fix coding style

* Move variable declaration to the top of the block

* Fix coding indentation

* Move some stuff into RISCVMappingInsn.inc

* Fix code sytle

* remove cs_mode support for RISCV

* update asmwriter-inc to LLVM upstream

* update the .inc files to riscv upstream

* update riscv disassembler function for suport 16bit instructions

* update printer & tablegen inc files which have fixed arguments mismatch

* update headers and mapping source

* add riscv architecture specific test code

* fix all RISCV tons of compiler errors

* pass final tests

* add riscv tablegen patchs

* merge with upstream/next

* fix cstool missing riscv file

* fix root Makefile

* add new TableGen patchs for riscv

* fix cmakefile.txt of missing one riscv file

* fix declaration conflict

* fix incompatible declaration type

* change riscvc from arch to mode

* fix test_riscv warnning

* fix code style and add riscv part of test_basic

* add RISCV64 mode

* add suite for riscv

* crack fuzz test

* fix getfeaturebits test add riscvc

* fix test missing const qualifier warnning

* fix testcase type mismatch

* fix return value missing

* change getfeaturebits test

* add test cs files

* using a winder type contain the decode string

* fix a copy typo

* remove useless mode for riscv

* change cs file blank type

* add repo for update_riscv & fix cstool missing riscv mode

* fix typo

* add riscv for cstool useage

* add TableGen patch for riscv asmwriter

* clean ctags file

* remove black comment line

* fix fuzz related something

* fix missing RISCV string of fuzz

* update readme, etc..

* add riscv *.s.cs file

* add riscv *.s.cs file & clear ctags

* clear useless array declarations at capstone_test

* update to 5e4069f

* update readme change name more formal

* change position of riscv after bpf and modify copyright more uniform

* clear useless ctags file

* change blank with tab in riscv.h

* add riscv python bindings

* add riscv in __init__.py

* fix riscv define value for python binding

* fix test_riscv.py typo

* add missing riscvc in __init__.py of python bindings

* fix alias-insn printer bug, remove useless newline

* change inst print delimter from tab to bankspace for travis

* add riscv tablegen patch

* fix inst output more consistency

* add TableGen patch which fix inst output formal

* crack the effective address output for detail and change register print function

* fix not detail crash bug

* change item declaration position at cs_riscv

* update riscv.py

* change function name more meaningfull

* update python binding makefile

* fix register enum sequence according to riscvgenreginfo.inc

* test function name

* add enum s0/fp in riscv.h & update riscv_const.py

* add register name enum
2019-03-09 08:41:12 +08:00
Nguyen Anh Quynh
be60fe4202 Merge branch 'next' of github.com:aquynh/capstone into next 2019-03-08 13:24:53 +08:00
Nguyen Anh Quynh
6c4bc4fe71 cstest: build with local libcapstone 2019-03-08 13:24:36 +08:00
Nguyen Anh Quynh
0f4300cf11 arm: cleanup ARMGenInstrInfo.inc 2019-03-07 18:13:39 +08:00
Nguyen Anh Quynh
165a964bb5 x86: operand size of BNDxxx is 16 2019-03-07 09:09:35 +08:00
Catena cyber
c5180bffd3 Fixes uninitialized memory for X86 BND instructions (#1415) 2019-03-07 09:06:45 +08:00
Catena cyber
2e13b39af5 Avoids type confusion in cpu12 for M680X (#1417) 2019-03-05 10:19:42 +08:00
Nguyen Anh Quynh
8c7cbaf415 x86: operand access for BND instructions 2019-03-04 16:12:56 +08:00
Nguyen Anh Quynh
f2233b7f44 x86: new files X86GenRegisterName.inc & X86GenRegisterName1.inc 2019-03-04 00:56:07 +08:00
Đỗ Minh Tuấn
5812414b2a normalize in issue mode (#1414)
* normalize tab character in cs

* normalize in issue mode
2019-03-03 19:10:55 +08:00
Đỗ Minh Tuấn
2fbc238e85 normalize tab character in cs (#1413)
* normalize tab character in cs
2019-03-03 18:09:20 +08:00
Travis Finkenauer
31d0de4552 [M68K] store correct register value in op.reg_pair (#1411)
* m68k: store correct m68k_reg value in op.reg_pair

Originally, value - M68K_REG_D0 was stored and the print logic added
M68K_REG_D0.

* m68k: fix license typo
2019-03-02 17:40:29 +08:00
Nguyen Anh Quynh
7e1efae487 x86: remove PRINT_ALIAS_INSTR 2019-03-02 15:32:07 +08:00
Nguyen Anh Quynh
cb2b1bda53 x86: add BND registers to regsize_map_32 & regsize_map_64 2019-03-02 15:16:48 +08:00
Nguyen Anh Quynh
9058367c07 fuzz_disasm: declare cs_fuzz_arch() 2019-03-02 15:07:28 +08:00
Nguyen Anh Quynh
ee237e128a bingdings: update X86 consts 2019-03-02 14:59:16 +08:00
Nguyen Anh Quynh
3dd39b0bc5 x86: add BND registers. this fixes OSS-fuzz issue 13467 2019-03-02 14:58:29 +08:00
Daniel Collin
9f53e3b0d4 Made instruction table static (#1408) 2019-03-02 10:53:30 +08:00
Catena cyber
1f0ff5e437 Fuzz more modes and ATT syntax (#1410) 2019-03-02 10:52:09 +08:00
Alexey Nurmukhametov
91f6189f97 cstest: add issue #1263 (#1407) 2019-03-01 18:08:21 +08:00
Nguyen Anh Quynh
21ee872b85 cmake: update HEADERS_X86 2019-03-01 12:54:08 +08:00
z
6eaf37cf87 fix SystemZRegDesc&SystemZMCRegisterClasses number of SystemZ InitMCRegisterInfo (#1405) 2019-03-01 09:55:11 +08:00
Stephen
228c733950 add xenial tests (#1404)
* add xenial tests

* add cmocka remove reminder
2019-03-01 09:55:02 +08:00
Nguyen Anh Quynh
b7ed33a1a0 Merge branch 'next' of github.com:aquynh/capstone into next 2019-03-01 01:12:50 +08:00
Nguyen Anh Quynh
0e3dc97fd9 Merge branch 'next-x86' into next 2019-03-01 01:12:32 +08:00
Nguyen Anh Quynh
2dc77357e1 x86: update ISA & mapping tables 2019-03-01 01:05:52 +08:00
Nguyen Anh Quynh
650b26e324 cstest: add 1 more test for #1335 2019-02-28 08:03:12 +08:00
Nguyen Anh Quynh
16f70fc354 cstest: add issue #1335 2019-02-28 08:01:23 +08:00
Nguyen Anh Quynh
ac311fd7f6 cstest: add issue #1259 2019-02-28 07:57:58 +08:00
Sebastian Macke
6ba9f001b9 MOS65XX: Fix instruction length for indirect addressing modes (#1402)
Signed-off-by: Sebastian Macke <sebastian@macke.de>
2019-02-28 07:39:59 +08:00
Nguyen Anh Quynh
3e624c0e02 sync cs.c 2019-02-28 06:14:50 +08:00
Philippe Antoine
e3bcb06681 Make travis print the fuzzed input to be used with cstool
Adds architectures and modes to cstool as well
2019-02-28 00:59:33 +08:00