* Fail CI if a command fails
* Apply cs_options in MC tests
* Emit a space if the alias has one at position I.
* Fix pop instruction tests.
* Update reglist patch and fix it again in ARMGenCSMappingInsnOps.inc
* Fix VSCCLRM* patch and write attributes.
* Emit new system operand formatting in tests
* Set new syntax in issues.cs
* Fix correct setting of neon lane
* Fix cstest arm SYSM operand type output
* Add implicit reads and writes of SP to POP and PUSH.
* Fix issue tests with new syntax and group names.
---------
Co-authored-by: Rot127 <unisono@quyllur.org>
- Differentiates between banked and non-banked registers.
- Saves the MSR mask.
- PSR field bits are saved separately.
- SYSm value is saved if possible.
Note: System registers and banked register encodings overlap.
So this might lead to problems. But cstool only asks for system registers.
So it should be fine for now.
* Add auto-sync updater.
* Update Capstone core with auto-sync changes.
* Update ARM via auto-sync.
* Make changes to arch modules which are introduced by auto-sync.
* Update tests for ARM.
* Fix build warnings for make
* Remove meson.build
* Print shift amount in decimal
* Patch non LLVM register alias.
* Change type of immediate operand to unsiged (due to: #771)
* Replace all occurances of a register with its alias.
* Fix printing of signed imms
* Print rotate amount in decimal
* CHange imm type to int64_t to match LLVM imm type.
* Fix search for register names, by completing string first.
* Print ModImm operands always in decimal
* Use number format of previous capstone version.
* Correct implicit writes and update_flags according to SBit.
* Add missing test for RegImmShift
* Reverse incorrect comparision.
* Set shift information for move instructions.
* Set mem access for all memory operands
* Set subtracted flag if offset is negative.
* Add flag for post-index memory operands.
* Add detail op for BX_RET and MOVPCLR
* Use instruction post_index operand.
* Add VPOP and VPUSH as unique CS IDs.
* Add shifting info for MOVsr.
* Add TODOs.
* Add in LLVM hardcoded operands to detail.
* Move detail editing from InstPrinter to Mapping
* Formatting
* Add removed check.
* Add writeback register and constraints to RFEI instructions.
* Translate shift immediate
* Print negative immediates
* Remove duplicate invalid entry
* Add CS groups to instructions
* Fix write attriutes of stores.
* Add missing names of added instructions
* Fix LLVM bug
* Add more post_index flags
* http -> https
* Make generated functions static
* Remove tab prefix for alias instructions.
* Set ValidateMCOperand to NULL.
* Fix AddrMode3Operand operands
* Allow getting system and banked register name via API
* Add writeback to STC/LDC instructions.
* Fix (hopefully) last case where disp is negative and subtracted = true
* Remove accidentially introduced regressions
* Fix access bug for TEST op
Results for TEST instructions are discarded hence operands should have
no write access.
* Fix access bug for TEST (reduce)
* trigger new ci test
---------
Co-authored-by: kabeor <1597915586@qq.com>
Because the cs_insn->mnemonic gets set *after* the
post_printer is called and cs_insn->mnemonic is not memset to 0
before, post_printer() of PPC receives a cs_insn->mnemonic with
random data.
This in turn leads randomly to incorrect setting of the branch hints
and the update_cr0 flag. Because those are set in the post_printer()
of PPC.
