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2,438 Commits 13 Branches 41 Tags 106 MiB
0f456b3379
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133 Commits

Author SHA1 Message Date
Nguyen Anh Quynh
0f456b3379 switch endian mode with cs_option() for Arm/Arm64/Mips/Sparc. fix issue #849 2017-02-01 11:17:13 +08:00
Nguyen Anh Quynh
b158b93a7d remove myinttypes.h 2016-04-26 09:47:30 +08:00
Nguyen Anh Quynh
901f407c0c mips: remove alias_insns[] 2015-06-22 15:48:45 +08:00
Nguyen Anh Quynh
ffb878ab53 mips: delete the alias map SUBU to NEGU. bug reported by @joelpx 2015-06-22 11:21:49 +08:00
Nguyen Anh Quynh
2ec0f814f9 mips: return Fail on assert failure in MipsDisassembler.c 2015-06-16 14:09:25 +08:00
learn_more
9668b2641f Fix compiling with nmake 2015-04-14 15:36:10 +02:00
Cr4sh
9d60607645 inttypes.h fix 2015-03-29 18:29:06 +08:00
Nguyen Anh Quynh
7334a88041 Merge branch 'master' into v3 2015-03-03 11:43:36 +08:00
Félix Cloutier
c141af9052 Silencing Clang warning bys casting values 
Warnings were: "Implicit conversion loses integer precision: 'size_t' to 'cs_mode'/'cs_opt_value'"
 2015-03-02 22:11:55 -05:00
Nguyen Anh Quynh
fbfa06deb7 mips: sanity check for input code length of Mips64 2015-02-27 17:31:24 +08:00
Nguyen Anh Quynh
22278ec937 mips & xcore: some safety guards to make sure printOperand() do not overflow Operands[] for some unknown reasons 2014-11-17 22:59:24 +08:00
Nguyen Anh Quynh
0d97a3b3aa mips: CS_MODE_MIPS32R6 is an independent mode, and should not combine with CS_MODE_32 2014-11-13 11:12:52 +08:00
Marcin Bukat
921a46c38f mips: Fix j/jal target address calculation 2014-11-12 11:06:34 +01:00
Nguyen Anh Quynh
c36e675213 mips: refine getFeatureBits() to make it more clear what Mips features are supported 2014-11-12 15:57:52 +08:00
Nguyen Anh Quynh
05bd294920 mips: Mips64 does not go with Mips32R6. this fixes some 64bit instructions 2014-11-10 15:20:49 +08:00
Nguyen Anh Quynh
248519efea mips: properly handle Mips32R6 mode. bug reported by Jay Oster 2014-11-09 14:07:07 +08:00
Nguyen Anh Quynh
c2ea812ea7 fix cs_group_name() after the change on generic group ids 2014-10-31 15:36:19 +08:00
Nguyen Anh Quynh
1084f3afda mips: properly support modes MIPS32R6 & CS_MODE_MIPSGP64 2014-10-29 22:20:38 +08:00
Jay Oster
79e253c516 Remove CS_MODE_N64 
- This mode is for the so-called MIPS "N64" ABI; it has nothing to do with the Nintendo 64 game platform.
- N64, O64, et al. are just different ABIs for the 64-bit MIPS architecture, so we replace CS_MODE_N64 with the existing CS_MODE_64
 2014-10-12 16:03:12 -07:00
Nguyen Anh Quynh
c64d6292fc mips: remove MIPS_REG_PC register. reviewed by Jay Oster 2014-10-10 21:11:50 +08:00
Nguyen Anh Quynh
df92a7f346 mips: BC0F is relative branch instruction. bug reported by Pancake 2014-10-01 21:25:18 +08:00
Nguyen Anh Quynh
c96f1b06b2 x86: fix Out-of-bounds read error in is16BitEquivalent(). issue reported by Coverity 2014-10-01 14:35:29 +08:00
Nguyen Anh Quynh
9bf1b87a66 mips: fix out-of-bounds read error in Mips_reg_name(). issue reported by Coverity 2014-10-01 14:32:15 +08:00
Nguyen Anh Quynh
9d54544288 mips: verify if RegDecoder can get NULL value. issue reported by Coverity 2014-10-01 14:16:07 +08:00
Nguyen Anh Quynh
d7e42b7d36 rename all the constants marking ending from _MAX to _ENDING. this also updates Java/Python/Ocaml bindings accordingly 2014-09-29 17:15:25 +08:00
Nguyen Anh Quynh
54f8cef449 mips: add JR.HB & JALR.HB instructions. also update Ocaml/Python/Java bindings 2014-09-24 22:53:54 +08:00
Nguyen Anh Quynh
7ac7d4e245 mips: on BEQZL, printAlias() should return instruction string. also cleanup some redundant code 2014-09-24 22:29:03 +08:00
Nguyen Anh Quynh
240e1c75be mips: print absolute target address for relative branch instructions: BEQL, BGEZALL, BGEZL, BGTZL, BLEZL, BLTZALL, BLTZL, BNEL, BNEZL, BEQZL, BC1F, BC1FL, BC1TL 2014-09-24 18:16:23 +08:00
Nguyen Anh Quynh
5691dd4637 mips: fixed & added new instructions. also updated Ocaml/Python/Java bindings 2014-09-24 18:03:47 +08:00
Yegor Derevenets
ced9d24e35 Workaround missing <inttypes.h> on MSVC 2010 2014-09-21 17:27:11 +02:00
Nguyen Anh Quynh
36567558b7 mips: cleanup 2014-09-15 15:25:19 +08:00
Nguyen Anh Quynh
04d9f8ee17 arm: update core with a lot more details provided in detail mode now. update Python & Java bindings to reflect the core's changes 2014-09-01 23:27:24 +08:00
Nguyen Anh Quynh
e0eb06b7ab mips: correct mapping instruction string to instruction ID for alias instructions BAL & BEQZ. bug reported by Pancake 2014-08-29 22:40:38 +08:00
Nguyen Anh Quynh
eda85064ee mips: add BC1T & BLTZAL to the list of relative branch instructions. thanks @hlide for the input. 2014-08-29 09:58:07 +08:00
Nguyen Anh Quynh
d1a9090eab mips: relative branch address calculated current IP added to the relative offset. thanks Pancake, Jay Oster, hlide & jvoisin for helping 2014-08-28 11:36:57 +08:00
Nguyen Anh Quynh
0c07cc9b06 zero-out instruction details, mnemonic & op_str so cs_insn doesnt have garbage in Diet mode 2014-08-27 22:31:54 +08:00
Nguyen Anh Quynh
4b6b15fcb1 fix more MSVC warnings 2014-08-26 15:57:04 +08:00
Nguyen Anh Quynh
14b684e07d last commit missed a check 2014-08-25 23:45:52 +08:00
Nguyen Anh Quynh
b1e87e3e31 arm, mips, ppc, spac, x86: printAliasInstr() should handle \t (besides space) as separate char between mnemonic & operands 2014-08-25 23:27:33 +08:00
Nguyen Anh Quynh
46a74e53b7 arm64: update core. this added a lot more details to cs_arm64_op struct 2014-08-25 16:47:12 +08:00
Nguyen Anh Quynh
2124b8a9c9 mips: indentations 2014-08-15 16:37:03 +08:00
Nguyen Anh Quynh
0f0eb9851a mips: update core. this added bunch of new instructions & groups. updated Python & Java bindings accordingly 2014-08-14 18:26:39 +08:00
Nguyen Anh Quynh
650f96ce43 add new API cs_group_name() to return group name in string, given the group id 2014-07-08 08:59:27 +08:00
Nguyen Anh Quynh
f08b83ddba mips: use CreateImm0() & CreateReg0() to create MCOperand* to avoid using malloc/free 2014-06-16 12:04:25 +08:00
Nguyen Anh Quynh
0c764d4a70 mips: use SStream_concat0() instead of SStream_concat() for simple string processing whenever possible 2014-06-16 11:53:08 +08:00
Nguyen Anh Quynh
69582d71ae initialize cs_insn.detail by properly zero-out right members for each arch 2014-06-09 17:50:01 +07:00
Nguyen Anh Quynh
29fd0f6405 fix all the code in other non-X86 archs after the change made by commit 5329a6ffd4 2014-06-09 08:00:18 +07:00
Nguyen Anh Quynh
5e2e660be7 fix some warnings reported by Coverity 2014-05-30 17:43:36 +08:00
Nguyen Anh Quynh
9148420b0d replace strcasecmp() with strcmp() 2014-05-28 12:57:46 +08:00
Nguyen Anh Quynh
f721e3124d Disassembler -> Disassembly 2014-05-27 10:45:58 +08:00